3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
11 * - jumps between blocks are tracked for SMC handling (in block_entry->links),
12 * except jumps between different tcaches
15 * - static register allocation
16 * - remaining register caching and tracking in temporaries
17 * - block-local branch linking
18 * - block linking (except between tcaches)
19 * - some constant propagation
22 * - better constant propagation
31 #include "../../pico/pico_int.h"
34 #include "../drc/cmn.h"
38 #define PROPAGATE_CONSTANTS 1
39 #define LINK_BRANCHES 1
42 #define MAX_BLOCK_SIZE (BLOCK_INSN_LIMIT * 6 * 6)
44 // max literal offset from the block end
45 #define MAX_LITERAL_OFFSET 32*2
46 #define MAX_LITERALS (BLOCK_INSN_LIMIT / 4)
47 #define MAX_LOCAL_BRANCHES 32
50 // 01 - warnings/errors
51 // 02 - block info/smc
53 // 08 - runtime block entry log
54 // 10 - smc self-check
61 #define dbg(l,...) { \
62 if ((l) & DRC_DEBUG) \
63 elprintf(EL_STATUS, ##__VA_ARGS__); \
65 #include "mame/sh2dasm.h"
66 #include <platform/libpicofe/linux/host_dasm.h>
67 static int insns_compiled, hash_collisions, host_insn_count;
76 #define FETCH_OP(pc) \
80 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
82 #define CHECK_UNHANDLED_BITS(mask, label) { \
83 if ((op & (mask)) != 0) \
95 #define BITMASK1(v0) (1 << (v0))
96 #define BITMASK2(v0,v1) ((1 << (v0)) | (1 << (v1)))
97 #define BITMASK3(v0,v1,v2) (BITMASK2(v0,v1) | (1 << (v2)))
98 #define BITMASK4(v0,v1,v2,v3) (BITMASK3(v0,v1,v2) | (1 << (v3)))
99 #define BITMASK5(v0,v1,v2,v3,v4) (BITMASK4(v0,v1,v2,v3) | (1 << (v4)))
101 #define SHR_T SHR_SR // might make them separate someday
103 static struct op_data {
106 u8 size; // 0, 1, 2 - byte, word, long
107 s8 rm; // branch or load/store data reg
108 u32 source; // bitmask of src regs
109 u32 dest; // bitmask of dest regs
110 u32 imm; // immediate/io address/branch target
111 // (for literal - address, not value)
112 } ops[BLOCK_INSN_LIMIT];
117 OP_BRANCH_CT, // conditional, branch if T set
118 OP_BRANCH_CF, // conditional, branch if T clear
119 OP_BRANCH_R, // indirect
120 OP_BRANCH_RF, // indirect far (PC + Rm)
121 OP_SETCLRT, // T flag set/clear
122 OP_MOVE, // register move
123 OP_LOAD_POOL, // literal pool load, imm is address
131 static int literal_disabled_frames;
134 static u8 *tcache_dsm_ptrs[3];
135 static char sh2dasm_buff[64];
136 #define do_host_disasm(tcid) \
137 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
138 tcache_dsm_ptrs[tcid] = tcache_ptr
140 #define do_host_disasm(x)
143 #if (DRC_DEBUG & 8) || defined(PDB)
144 static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
147 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
148 sh2->pc, block, (signed int)sr >> 12);
149 pdb_step(sh2, sh2->pc);
156 #define TCACHE_BUFFERS 3
158 // we have 3 translation cache buffers, split from one drc/cmn buffer.
159 // BIOS shares tcache with data array because it's only used for init
160 // and can be discarded early
161 // XXX: need to tune sizes
162 static const int tcache_sizes[TCACHE_BUFFERS] = {
163 DRC_TCACHE_SIZE * 6 / 8, // ROM (rarely used), DRAM
164 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
165 DRC_TCACHE_SIZE / 8, // ... slave
168 static u8 *tcache_bases[TCACHE_BUFFERS];
169 static u8 *tcache_ptrs[TCACHE_BUFFERS];
171 // ptr for code emiters
172 static u8 *tcache_ptr;
174 #define MAX_BLOCK_ENTRIES (BLOCK_INSN_LIMIT / 8)
178 void *jump; // insn address
179 struct block_link *next; // either in block_entry->links or
184 void *tcache_ptr; // translated block for above PC
185 struct block_entry *next; // next block in hash_table with same pc hash
186 struct block_link *links; // links to this entry
188 struct block_desc *block;
193 u32 addr; // block start SH2 PC address
194 u16 size; // ..of recompiled insns+lit. pool
195 u16 size_nolit; // same without literals
200 struct block_entry entryp[MAX_BLOCK_ENTRIES];
203 static const int block_max_counts[TCACHE_BUFFERS] = {
208 static struct block_desc *block_tables[TCACHE_BUFFERS];
209 static int block_counts[TCACHE_BUFFERS];
211 // we have block_link_pool to avoid using mallocs
212 static const int block_link_pool_max_counts[TCACHE_BUFFERS] = {
217 static struct block_link *block_link_pool[TCACHE_BUFFERS];
218 static int block_link_pool_counts[TCACHE_BUFFERS];
219 static struct block_link *unresolved_links[TCACHE_BUFFERS];
221 // used for invalidation
222 static const int ram_sizes[TCACHE_BUFFERS] = {
227 #define INVAL_PAGE_SIZE 0x100
230 struct block_desc *block;
231 struct block_list *next;
234 // array of pointers to block_lists for RAM and 2 data arrays
235 // each array has len: sizeof(mem) / INVAL_PAGE_SIZE
236 static struct block_list **inval_lookup[TCACHE_BUFFERS];
238 static const int hash_table_sizes[TCACHE_BUFFERS] = {
243 static struct block_entry **hash_tables[TCACHE_BUFFERS];
245 #define HASH_FUNC(hash_tab, addr, mask) \
246 (hash_tab)[(((addr) >> 20) ^ ((addr) >> 2)) & (mask)]
248 // host register tracking
251 HR_CACHED, // 'val' has sh2_reg_e
252 // HR_CONST, // 'val' has a constant
253 HR_TEMP, // reg used for temp storage
257 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
258 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
262 u32 hreg:5; // "host" reg
263 u32 greg:5; // "guest" reg
266 u32 stamp:16; // kind of a timestamp
269 // note: reg_temp[] must have at least the amount of
270 // registers used by handlers in worst case (currently 4)
272 #include "../drc/emit_arm.c"
276 static const int reg_map_g2h[] = {
280 -1, -1, -1, 9, // r12 .. sp
281 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
282 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
288 static const int reg_map_g2h[] = {
292 -1, -1, -1, 8, // r12 .. sp
293 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
294 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
299 static temp_reg_t reg_temp[] = {
308 #elif defined(__i386__)
309 #include "../drc/emit_x86.c"
311 static const int reg_map_g2h[] = {
320 // ax, cx, dx are usually temporaries by convention
321 static temp_reg_t reg_temp[] = {
329 #error unsupported arch
337 #define T_save 0x00000800
343 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
344 static void (*sh2_drc_dispatcher)(void);
345 static void (*sh2_drc_exit)(void);
346 static void (*sh2_drc_test_irq)(void);
348 static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
349 static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
350 static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
351 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
352 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
353 static void REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
355 // address space stuff
356 static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
360 if ((a & ~0x7ff) == 0) {
362 poffs = offsetof(SH2, p_bios);
365 else if ((a & 0xfffff000) == 0xc0000000) {
367 // FIXME: access sh2->data_array instead
368 poffs = offsetof(SH2, p_da);
371 else if ((a & 0xc6000000) == 0x06000000) {
373 poffs = offsetof(SH2, p_sdram);
376 else if ((a & 0xc6000000) == 0x02000000) {
378 poffs = offsetof(SH2, p_rom);
385 static struct block_entry *dr_get_entry(u32 pc, int is_slave, int *tcache_id)
387 struct block_entry *be;
390 // data arrays have their own caches
391 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0)
396 mask = hash_table_sizes[tcid] - 1;
397 be = HASH_FUNC(hash_tables[tcid], pc, mask);
398 for (; be != NULL; be = be->next)
405 // ---------------------------------------------------------------
408 static void add_to_block_list(struct block_list **blist, struct block_desc *block)
410 struct block_list *added = malloc(sizeof(*added));
412 elprintf(EL_ANOMALY, "drc OOM (1)");
415 added->block = block;
416 added->next = *blist;
420 static void rm_from_block_list(struct block_list **blist, struct block_desc *block)
422 struct block_list *prev = NULL, *current = *blist;
423 for (; current != NULL; current = current->next) {
424 if (current->block == block) {
426 *blist = current->next;
428 prev->next = current->next;
434 dbg(1, "can't rm block %p (%08x-%08x)",
435 block, block->addr, block->addr + block->size);
438 static void rm_block_list(struct block_list **blist)
440 struct block_list *tmp, *current = *blist;
441 while (current != NULL) {
443 current = current->next;
449 static void REGPARM(1) flush_tcache(int tcid)
453 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
454 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
455 block_counts[tcid], block_max_counts[tcid]);
457 block_counts[tcid] = 0;
458 block_link_pool_counts[tcid] = 0;
459 unresolved_links[tcid] = NULL;
460 memset(hash_tables[tcid], 0, sizeof(*hash_tables[0]) * hash_table_sizes[tcid]);
461 tcache_ptrs[tcid] = tcache_bases[tcid];
462 if (Pico32xMem != NULL) {
463 if (tcid == 0) // ROM, RAM
464 memset(Pico32xMem->drcblk_ram, 0,
465 sizeof(Pico32xMem->drcblk_ram));
467 memset(Pico32xMem->drcblk_da[tcid - 1], 0,
468 sizeof(Pico32xMem->drcblk_da[0]));
471 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
474 for (i = 0; i < ram_sizes[tcid] / INVAL_PAGE_SIZE; i++)
475 rm_block_list(&inval_lookup[tcid][i]);
478 static void add_to_hashlist(struct block_entry *be, int tcache_id)
480 u32 tcmask = hash_table_sizes[tcache_id] - 1;
482 be->next = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
483 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be;
486 if (be->next != NULL) {
487 printf(" %08x: hash collision with %08x\n",
488 be->pc, be->next->pc);
494 static void rm_from_hashlist(struct block_entry *be, int tcache_id)
496 u32 tcmask = hash_table_sizes[tcache_id] - 1;
497 struct block_entry *cur, *prev;
499 cur = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
503 if (be == cur) { // first
504 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be->next;
508 for (prev = cur, cur = cur->next; cur != NULL; cur = cur->next) {
510 prev->next = cur->next;
516 dbg(1, "rm_from_hashlist: be %p %08x missing?", be, be->pc);
519 static void unregister_links(struct block_entry *be, int tcache_id)
521 struct block_link *bl_unresolved = unresolved_links[tcache_id];
522 struct block_link *bl, *bl_next;
524 for (bl = be->links; bl != NULL; ) {
526 bl->next = bl_unresolved;
531 unresolved_links[tcache_id] = bl_unresolved;
534 // unlike sh2_smc_rm_block, the block stays and can still be accessed
535 // by other already directly linked blocks, just not preferred
536 static void kill_block_entry(struct block_entry *be, int tcache_id)
538 rm_from_hashlist(be, tcache_id);
539 unregister_links(be, tcache_id);
542 static struct block_desc *dr_add_block(u32 addr, u16 size_lit,
543 u16 size_nolit, int is_slave, int *blk_id)
545 struct block_entry *be;
546 struct block_desc *bd;
550 // do a lookup to get tcache_id and override check
551 be = dr_get_entry(addr, is_slave, &tcache_id);
553 dbg(1, "block override for %08x, was %p", addr, be->tcache_ptr);
554 kill_block_entry(be, tcache_id);
557 bcount = &block_counts[tcache_id];
558 if (*bcount >= block_max_counts[tcache_id]) {
559 dbg(1, "bd overflow for tcache %d", tcache_id);
563 bd = &block_tables[tcache_id][*bcount];
566 bd->size_nolit = size_nolit;
569 bd->entryp[0].pc = addr;
570 bd->entryp[0].tcache_ptr = tcache_ptr;
571 bd->entryp[0].links = NULL;
573 bd->entryp[0].block = bd;
576 add_to_hashlist(&bd->entryp[0], tcache_id);
584 static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
586 struct block_entry *be = NULL;
589 be = dr_get_entry(pc, is_slave, tcache_id);
591 block = be->tcache_ptr;
595 be->block->refcount++;
600 static void *dr_failure(void)
602 lprintf("recompilation failed\n");
606 static void *dr_prepare_ext_branch(u32 pc, int is_slave, int tcache_id)
609 struct block_link *bl = block_link_pool[tcache_id];
610 int cnt = block_link_pool_counts[tcache_id];
611 struct block_entry *be = NULL;
612 int target_tcache_id;
615 be = dr_get_entry(pc, is_slave, &target_tcache_id);
616 if (target_tcache_id != tcache_id)
617 return sh2_drc_dispatcher;
619 // if pool has been freed, reuse
620 for (i = cnt - 1; i >= 0; i--)
621 if (bl[i].target_pc != 0)
624 if (cnt >= block_link_pool_max_counts[tcache_id]) {
625 dbg(1, "bl overflow for tcache %d", tcache_id);
629 block_link_pool_counts[tcache_id]++;
632 bl->jump = tcache_ptr;
635 dbg(2, "- early link from %p to pc %08x", bl->jump, pc);
636 bl->next = be->links;
638 return be->tcache_ptr;
641 bl->next = unresolved_links[tcache_id];
642 unresolved_links[tcache_id] = bl;
643 return sh2_drc_dispatcher;
646 return sh2_drc_dispatcher;
650 static void dr_link_blocks(struct block_entry *be, int tcache_id)
653 struct block_link *first = unresolved_links[tcache_id];
654 struct block_link *bl, *prev, *tmp;
657 for (bl = prev = first; bl != NULL; ) {
658 if (bl->target_pc == pc) {
659 dbg(2, "- link from %p to pc %08x", bl->jump, pc);
660 emith_jump_patch(bl->jump, tcache_ptr);
662 // move bl from unresolved_links to block_entry
664 bl->next = be->links;
668 first = prev = bl = tmp;
670 prev->next = bl = tmp;
676 unresolved_links[tcache_id] = first;
678 // could sync arm caches here, but that's unnecessary
682 #define ADD_TO_ARRAY(array, count, item, failcode) \
683 if (count >= ARRAY_SIZE(array)) { \
684 dbg(1, "warning: " #array " overflow"); \
687 array[count++] = item;
689 static int find_in_array(u32 *array, size_t size, u32 what)
692 for (i = 0; i < size; i++)
693 if (what == array[i])
699 // ---------------------------------------------------------------
701 // register cache / constant propagation stuff
708 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
710 // guest regs with constants
711 static u32 dr_gcregs[24];
712 // a mask of constant/dirty regs
713 static u32 dr_gcregs_mask;
714 static u32 dr_gcregs_dirty;
716 #if PROPAGATE_CONSTANTS
717 static void gconst_new(sh2_reg_e r, u32 val)
721 dr_gcregs_mask |= 1 << r;
722 dr_gcregs_dirty |= 1 << r;
725 // throw away old r that we might have cached
726 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
727 if ((reg_temp[i].type == HR_CACHED) &&
728 reg_temp[i].greg == r) {
729 reg_temp[i].type = HR_FREE;
730 reg_temp[i].flags = 0;
736 static int gconst_get(sh2_reg_e r, u32 *val)
738 if (dr_gcregs_mask & (1 << r)) {
745 static int gconst_check(sh2_reg_e r)
747 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
752 // update hr if dirty, else do nothing
753 static int gconst_try_read(int hr, sh2_reg_e r)
755 if (dr_gcregs_dirty & (1 << r)) {
756 emith_move_r_imm(hr, dr_gcregs[r]);
757 dr_gcregs_dirty &= ~(1 << r);
763 static void gconst_check_evict(sh2_reg_e r)
765 if (dr_gcregs_mask & (1 << r))
766 // no longer cached in reg, make dirty again
767 dr_gcregs_dirty |= 1 << r;
770 static void gconst_kill(sh2_reg_e r)
772 dr_gcregs_mask &= ~(1 << r);
773 dr_gcregs_dirty &= ~(1 << r);
776 static void gconst_clean(void)
780 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
781 if (dr_gcregs_dirty & (1 << i)) {
782 // using RC_GR_READ here: it will call gconst_try_read,
783 // cache the reg and mark it dirty.
784 rcache_get_reg_(i, RC_GR_READ, 0);
788 static void gconst_invalidate(void)
790 dr_gcregs_mask = dr_gcregs_dirty = 0;
793 static u16 rcache_counter;
795 static temp_reg_t *rcache_evict(void)
797 // evict reg with oldest stamp
799 u16 min_stamp = (u16)-1;
801 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
802 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
803 reg_temp[i].stamp <= min_stamp) {
804 min_stamp = reg_temp[i].stamp;
810 printf("no registers to evict, aborting\n");
815 if (reg_temp[i].type == HR_CACHED) {
816 if (reg_temp[i].flags & HRF_DIRTY)
818 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
819 gconst_check_evict(reg_temp[i].greg);
822 reg_temp[i].type = HR_FREE;
823 reg_temp[i].flags = 0;
827 static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
829 int i = reg_map_g2h[r];
831 if (mode != RC_GR_WRITE)
832 gconst_try_read(i, r);
837 // note: must not be called when doing conditional code
838 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
843 // maybe statically mapped?
844 ret = get_reg_static(r, mode);
850 // maybe already cached?
851 // if so, prefer against gconst (they must be in sync)
852 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
853 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
854 reg_temp[i].stamp = rcache_counter;
855 if (mode != RC_GR_READ)
856 reg_temp[i].flags |= HRF_DIRTY;
857 ret = reg_temp[i].hreg;
863 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
864 if (reg_temp[i].type == HR_FREE) {
873 tr->type = HR_CACHED;
875 tr->flags |= HRF_LOCKED;
876 if (mode != RC_GR_READ)
877 tr->flags |= HRF_DIRTY;
879 tr->stamp = rcache_counter;
882 if (mode != RC_GR_WRITE) {
883 if (gconst_check(r)) {
884 if (gconst_try_read(ret, r))
885 tr->flags |= HRF_DIRTY;
888 emith_ctx_read(tr->hreg, r * 4);
892 if (mode != RC_GR_READ)
898 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
900 return rcache_get_reg_(r, mode, 1);
903 static int rcache_get_tmp(void)
908 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
909 if (reg_temp[i].type == HR_FREE) {
921 static int rcache_get_arg_id(int arg)
924 host_arg2reg(r, arg);
926 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
927 if (reg_temp[i].hreg == r)
930 if (i == ARRAY_SIZE(reg_temp)) // can't happen
933 if (reg_temp[i].type == HR_CACHED) {
935 if (reg_temp[i].flags & HRF_DIRTY)
936 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
937 gconst_check_evict(reg_temp[i].greg);
939 else if (reg_temp[i].type == HR_TEMP) {
940 printf("arg %d reg %d already used, aborting\n", arg, r);
944 reg_temp[i].type = HR_FREE;
945 reg_temp[i].flags = 0;
950 // get a reg to be used as function arg
951 static int rcache_get_tmp_arg(int arg)
953 int id = rcache_get_arg_id(arg);
954 reg_temp[id].type = HR_TEMP;
956 return reg_temp[id].hreg;
959 // same but caches a reg. RC_GR_READ only.
960 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
962 int i, srcr, dstr, dstid;
963 int dirty = 0, src_dirty = 0;
965 dstid = rcache_get_arg_id(arg);
966 dstr = reg_temp[dstid].hreg;
968 // maybe already statically mapped?
969 srcr = get_reg_static(r, RC_GR_READ);
973 // maybe already cached?
974 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
975 if ((reg_temp[i].type == HR_CACHED) &&
976 reg_temp[i].greg == r)
978 srcr = reg_temp[i].hreg;
979 if (reg_temp[i].flags & HRF_DIRTY)
987 if (gconst_check(r)) {
988 if (gconst_try_read(srcr, r))
992 emith_ctx_read(srcr, r * 4);
996 emith_move_r_r(dstr, srcr);
1002 // must clean, callers might want to modify the arg before call
1003 emith_ctx_write(dstr, r * 4);
1006 reg_temp[dstid].flags |= HRF_DIRTY;
1009 reg_temp[dstid].stamp = ++rcache_counter;
1010 reg_temp[dstid].type = HR_CACHED;
1011 reg_temp[dstid].greg = r;
1012 reg_temp[dstid].flags |= HRF_LOCKED;
1016 static void rcache_free_tmp(int hr)
1019 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1020 if (reg_temp[i].hreg == hr)
1023 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
1024 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
1028 reg_temp[i].type = HR_FREE;
1029 reg_temp[i].flags = 0;
1032 static void rcache_unlock(int hr)
1035 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1036 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
1037 reg_temp[i].flags &= ~HRF_LOCKED;
1040 static void rcache_unlock_all(void)
1043 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1044 reg_temp[i].flags &= ~HRF_LOCKED;
1048 static u32 rcache_used_hreg_mask(void)
1053 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1054 if (reg_temp[i].type != HR_FREE)
1055 mask |= 1 << reg_temp[i].hreg;
1061 static void rcache_clean(void)
1066 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1067 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
1069 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
1070 reg_temp[i].flags &= ~HRF_DIRTY;
1074 static void rcache_invalidate(void)
1077 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
1078 reg_temp[i].type = HR_FREE;
1079 reg_temp[i].flags = 0;
1083 gconst_invalidate();
1086 static void rcache_flush(void)
1089 rcache_invalidate();
1092 // ---------------------------------------------------------------
1094 static int emit_get_rbase_and_offs(u32 a, u32 *offs)
1100 poffs = dr_ctx_get_mem_ptr(a, &mask);
1104 // XXX: could use some related reg
1105 hr = rcache_get_tmp();
1106 emith_ctx_read(hr, poffs);
1107 emith_add_r_imm(hr, a & mask & ~0xff);
1108 *offs = a & 0xff; // XXX: ARM oriented..
1112 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
1114 #if PROPAGATE_CONSTANTS
1115 gconst_new(dst, imm);
1117 int hr = rcache_get_reg(dst, RC_GR_WRITE);
1118 emith_move_r_imm(hr, imm);
1122 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
1124 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
1125 int hr_s = rcache_get_reg(src, RC_GR_READ);
1127 emith_move_r_r(hr_d, hr_s);
1130 // T must be clear, and comparison done just before this
1131 static void emit_or_t_if_eq(int srr)
1133 EMITH_SJMP_START(DCOND_NE);
1134 emith_or_r_imm_c(DCOND_EQ, srr, T);
1135 EMITH_SJMP_END(DCOND_NE);
1138 // arguments must be ready
1139 // reg cache must be clean before call
1140 static int emit_memhandler_read_(int size, int ram_check)
1145 host_arg2reg(arg0, 0);
1150 // must writeback cycles for poll detection stuff
1152 if (reg_map_g2h[SHR_SR] != -1)
1153 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1155 arg1 = rcache_get_tmp_arg(1);
1156 emith_move_r_r(arg1, CONTEXT_REG);
1158 #if 0 // can't do this because of unmapped reads
1160 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
1161 int tmp = rcache_get_tmp();
1162 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
1163 emith_cmp_r_imm(tmp, 0x02000000);
1166 EMITH_SJMP3_START(DCOND_NE);
1167 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
1168 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1169 EMITH_SJMP3_MID(DCOND_NE);
1170 emith_call_cond(DCOND_NE, sh2_drc_read8);
1174 EMITH_SJMP3_START(DCOND_NE);
1175 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1176 EMITH_SJMP3_MID(DCOND_NE);
1177 emith_call_cond(DCOND_NE, sh2_drc_read16);
1181 EMITH_SJMP3_START(DCOND_NE);
1182 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1183 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
1184 EMITH_SJMP3_MID(DCOND_NE);
1185 emith_call_cond(DCOND_NE, sh2_drc_read32);
1195 emith_call(sh2_drc_read8);
1198 emith_call(sh2_drc_read16);
1201 emith_call(sh2_drc_read32);
1205 rcache_invalidate();
1207 if (reg_map_g2h[SHR_SR] != -1)
1208 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1210 // assuming arg0 and retval reg matches
1211 return rcache_get_tmp_arg(0);
1214 static int emit_memhandler_read(int size)
1216 return emit_memhandler_read_(size, 1);
1219 static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
1221 int hr, hr2, ram_check = 1;
1224 if (gconst_get(rs, &val)) {
1225 hr = emit_get_rbase_and_offs(val + offs, &offs2);
1227 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1230 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
1231 emith_sext(hr2, hr2, 8);
1234 emith_read16_r_r_offs(hr2, hr, offs2);
1235 emith_sext(hr2, hr2, 16);
1238 emith_read_r_r_offs(hr2, hr, offs2);
1239 emith_ror(hr2, hr2, 16);
1242 rcache_free_tmp(hr);
1249 hr = rcache_get_reg_arg(0, rs);
1251 emith_add_r_imm(hr, offs);
1252 hr = emit_memhandler_read_(size, ram_check);
1253 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1255 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1257 emith_move_r_r(hr2, hr);
1258 rcache_free_tmp(hr);
1263 static void emit_memhandler_write(int size)
1266 host_arg2reg(ctxr, 2);
1267 if (reg_map_g2h[SHR_SR] != -1)
1268 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1274 // XXX: consider inlining sh2_drc_write8
1275 emith_call(sh2_drc_write8);
1278 emith_call(sh2_drc_write16);
1281 emith_move_r_r(ctxr, CONTEXT_REG);
1282 emith_call(sh2_drc_write32);
1286 rcache_invalidate();
1287 if (reg_map_g2h[SHR_SR] != -1)
1288 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1292 static int emit_indirect_indexed_read(int rx, int ry, int size)
1295 a0 = rcache_get_reg_arg(0, rx);
1296 t = rcache_get_reg(ry, RC_GR_READ);
1297 emith_add_r_r(a0, t);
1298 return emit_memhandler_read(size);
1302 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1306 rcache_get_reg_arg(0, rn);
1307 tmp = emit_memhandler_read(size);
1308 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1309 rcache_free_tmp(tmp);
1310 tmp = rcache_get_reg(rn, RC_GR_RMW);
1311 emith_add_r_imm(tmp, 1 << size);
1314 rcache_get_reg_arg(0, rm);
1315 *rmr = emit_memhandler_read(size);
1316 *rnr = rcache_get_tmp();
1317 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1318 tmp = rcache_get_reg(rm, RC_GR_RMW);
1319 emith_add_r_imm(tmp, 1 << size);
1323 static void emit_do_static_regs(int is_write, int tmpr)
1327 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1332 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1333 if (reg_map_g2h[i + 1] != r + 1)
1339 // i, r point to last item
1341 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1343 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1346 emith_ctx_write(r, i * 4);
1348 emith_ctx_read(r, i * 4);
1353 static void emit_block_entry(void)
1357 host_arg2reg(arg0, 0);
1359 #if (DRC_DEBUG & 8) || defined(PDB)
1361 host_arg2reg(arg1, 1);
1362 host_arg2reg(arg2, 2);
1364 emit_do_static_regs(1, arg2);
1365 emith_move_r_r(arg1, CONTEXT_REG);
1366 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
1367 emith_call(sh2_drc_log_entry);
1368 rcache_invalidate();
1370 emith_tst_r_r(arg0, arg0);
1371 EMITH_SJMP_START(DCOND_EQ);
1372 emith_jump_reg_c(DCOND_NE, arg0);
1373 EMITH_SJMP_END(DCOND_EQ);
1376 #define DELAY_SAVE_T(sr) { \
1377 emith_bic_r_imm(sr, T_save); \
1378 emith_tst_r_imm(sr, T); \
1379 EMITH_SJMP_START(DCOND_EQ); \
1380 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1381 EMITH_SJMP_END(DCOND_EQ); \
1384 #define FLUSH_CYCLES(sr) \
1386 emith_sub_r_imm(sr, cycles << 12); \
1390 static void *dr_get_pc_base(u32 pc, int is_slave);
1392 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
1394 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
1395 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1396 int branch_target_count = 0;
1397 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1398 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1399 int branch_patch_count = 0;
1400 u32 literal_addr[MAX_LITERALS];
1401 int literal_addr_count = 0;
1402 u8 op_flags[BLOCK_INSN_LIMIT];
1405 u32 pending_branch_direct:1;
1406 u32 pending_branch_indirect:1;
1407 u32 literals_disabled:1;
1410 // PC of current, first, last SH2 insn
1411 u32 pc, base_pc, end_pc;
1413 void *block_entry_ptr;
1414 struct block_desc *block;
1416 struct op_data *opd;
1425 drcf.literals_disabled = literal_disabled_frames != 0;
1427 // get base/validate PC
1428 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1429 if (dr_pc_base == (void *)-1) {
1430 printf("invalid PC, aborting: %08x\n", base_pc);
1431 // FIXME: be less destructive
1435 tcache_ptr = tcache_ptrs[tcache_id];
1437 // predict tcache overflow
1438 tmp = tcache_ptr - tcache_bases[tcache_id];
1439 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
1440 dbg(1, "tcache %d overflow", tcache_id);
1444 // initial passes to disassemble and analyze the block
1445 scan_block(base_pc, sh2->is_slave, op_flags, &end_pc, &end_literals);
1447 if (drcf.literals_disabled)
1448 end_literals = end_pc;
1450 block = dr_add_block(base_pc, end_literals - base_pc,
1451 end_pc - base_pc, sh2->is_slave, &blkid_main);
1455 block_entry_ptr = tcache_ptr;
1456 dbg(2, "== %csh2 block #%d,%d %08x-%08x -> %p", sh2->is_slave ? 's' : 'm',
1457 tcache_id, blkid_main, base_pc, end_pc, block_entry_ptr);
1459 dr_link_blocks(&block->entryp[0], tcache_id);
1461 // collect branch_targets that don't land on delay slots
1462 for (pc = base_pc, i = 0; pc < end_pc; i++, pc += 2) {
1463 if (!(op_flags[i] & OF_BTARGET))
1465 if (op_flags[i] & OF_DELAY_OP) {
1466 op_flags[i] &= ~OF_BTARGET;
1469 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
1472 if (branch_target_count > 0) {
1473 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1476 // clear stale state after compile errors
1477 rcache_invalidate();
1479 // -------------------------------------------------
1480 // 3rd pass: actual compilation
1483 for (i = 0; pc < end_pc; i++)
1485 u32 delay_dep_fw = 0, delay_dep_bk = 0;
1495 DasmSH2(sh2dasm_buff, pc, op);
1496 printf("%c%08x %04x %s\n", (op_flags[i] & OF_BTARGET) ? '*' : ' ',
1497 pc, op, sh2dasm_buff);
1500 if ((op_flags[i] & OF_BTARGET) || pc == base_pc)
1504 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1509 v = block->entry_count;
1510 if (v < ARRAY_SIZE(block->entryp))
1512 struct block_entry *be_old;
1514 block->entryp[v].pc = pc;
1515 block->entryp[v].tcache_ptr = tcache_ptr;
1516 block->entryp[v].links = NULL;
1518 block->entryp[v].block = block;
1520 be_old = dr_get_entry(pc, sh2->is_slave, &tcache_id);
1521 if (be_old != NULL) {
1522 dbg(1, "entry override for %08x, was %p", pc, be_old->tcache_ptr);
1523 kill_block_entry(be_old, tcache_id);
1526 add_to_hashlist(&block->entryp[v], tcache_id);
1527 block->entry_count++;
1529 dbg(2, "-- %csh2 block #%d,%d entry %08x -> %p",
1530 sh2->is_slave ? 's' : 'm', tcache_id, blkid_main,
1533 // since we made a block entry, link any other blocks
1534 // that jump to current pc
1535 dr_link_blocks(&block->entryp[v], tcache_id);
1538 dbg(1, "too many entryp for block #%d,%d pc=%08x",
1539 tcache_id, blkid_main, pc);
1542 do_host_disasm(tcache_id);
1545 v = find_in_array(branch_target_pc, branch_target_count, pc);
1547 branch_target_ptr[v] = tcache_ptr;
1550 emit_move_r_imm32(SHR_PC, pc);
1553 #if (DRC_DEBUG & 0x10)
1554 rcache_get_reg_arg(0, SHR_PC);
1555 tmp = emit_memhandler_read(2);
1556 tmp2 = rcache_get_tmp();
1557 tmp3 = rcache_get_tmp();
1558 emith_move_r_imm(tmp2, FETCH32(pc));
1559 emith_move_r_imm(tmp3, 0);
1560 emith_cmp_r_r(tmp, tmp2);
1561 EMITH_SJMP_START(DCOND_EQ);
1562 emith_read_r_r_offs_c(DCOND_NE, tmp3, tmp3, 0); // crash
1563 EMITH_SJMP_END(DCOND_EQ);
1564 rcache_free_tmp(tmp);
1565 rcache_free_tmp(tmp2);
1566 rcache_free_tmp(tmp3);
1570 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1571 emith_cmp_r_imm(sr, 0);
1572 emith_jump_cond(DCOND_LE, sh2_drc_exit);
1573 do_host_disasm(tcache_id);
1574 rcache_unlock_all();
1578 if (!(op_flags[i] & OF_DELAY_OP)) {
1579 emit_move_r_imm32(SHR_PC, pc);
1580 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1584 tmp = rcache_used_hreg_mask();
1585 emith_save_caller_regs(tmp);
1586 emit_do_static_regs(1, 0);
1587 emith_pass_arg_r(0, CONTEXT_REG);
1588 emith_call(do_sh2_cmp);
1589 emith_restore_caller_regs(tmp);
1600 if (op_flags[i] & OF_DELAY_OP)
1602 // handle delay slot dependencies
1603 delay_dep_fw = opd->dest & ops[i-1].source;
1604 delay_dep_bk = opd->source & ops[i-1].dest;
1605 if (delay_dep_fw & BITMASK1(SHR_T)) {
1606 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1609 if (delay_dep_bk & BITMASK1(SHR_PC)) {
1610 if (opd->op != OP_LOAD_POOL && opd->op != OP_MOVA) {
1611 // can only be those 2 really..
1612 elprintf_sh2(sh2, EL_ANOMALY,
1613 "drc: illegal slot insn %04x @ %08x?", op, pc - 2);
1616 ; // addr already resolved somehow
1618 switch (ops[i-1].op) {
1620 emit_move_r_imm32(SHR_PC, ops[i-1].imm);
1624 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1625 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1626 emith_move_r_imm(tmp, pc);
1627 emith_tst_r_imm(sr, T);
1628 tmp2 = ops[i-1].op == OP_BRANCH_CT ? DCOND_NE : DCOND_EQ;
1629 emith_move_r_imm_c(tmp2, tmp, ops[i-1].imm);
1631 // case OP_BRANCH_R OP_BRANCH_RF - PC already loaded
1635 //if (delay_dep_fw & ~BITMASK1(SHR_T))
1636 // dbg(1, "unhandled delay_dep_fw: %x", delay_dep_fw & ~BITMASK1(SHR_T));
1637 if (delay_dep_bk & ~BITMASK2(SHR_PC, SHR_PR))
1638 dbg(1, "unhandled delay_dep_bk: %x", delay_dep_bk);
1646 if (opd->dest & BITMASK1(SHR_PR))
1647 emit_move_r_imm32(SHR_PR, pc + 2);
1648 drcf.pending_branch_direct = 1;
1652 if (opd->dest & BITMASK1(SHR_PR))
1653 emit_move_r_imm32(SHR_PR, pc + 2);
1654 emit_move_r_r(SHR_PC, opd->rm);
1655 drcf.pending_branch_indirect = 1;
1659 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1660 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1661 if (opd->dest & BITMASK1(SHR_PR)) {
1662 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1663 emith_move_r_imm(tmp3, pc + 2);
1664 emith_add_r_r_r(tmp, tmp2, tmp3);
1667 emith_move_r_r(tmp, tmp2);
1668 emith_add_r_imm(tmp, pc + 2);
1670 drcf.pending_branch_indirect = 1;
1674 printf("TODO sleep\n");
1679 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
1681 tmp = rcache_get_reg_arg(0, SHR_SP);
1682 emith_add_r_imm(tmp, 4);
1683 tmp = emit_memhandler_read(2);
1684 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1685 emith_write_sr(sr, tmp);
1686 rcache_free_tmp(tmp);
1687 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1688 emith_add_r_imm(tmp, 4*2);
1690 drcf.pending_branch_indirect = 1;
1694 #if PROPAGATE_CONSTANTS
1695 if (opd->imm != 0 && opd->imm < end_literals
1696 && literal_addr_count < MAX_LITERALS)
1698 ADD_TO_ARRAY(literal_addr, literal_addr_count, opd->imm,);
1700 tmp = FETCH32(opd->imm);
1702 tmp = (u32)(int)(signed short)FETCH_OP(opd->imm);
1703 gconst_new(GET_Rn(), tmp);
1708 tmp = rcache_get_tmp_arg(0);
1710 emith_move_r_imm(tmp, opd->imm);
1712 // have to calculate read addr from PC
1713 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1714 if (opd->size == 2) {
1715 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1716 emith_bic_r_imm(tmp, 3);
1719 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 2);
1721 tmp2 = emit_memhandler_read(opd->size);
1722 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1724 emith_move_r_r(tmp3, tmp2);
1726 emith_sext(tmp3, tmp2, 16);
1727 rcache_free_tmp(tmp2);
1733 emit_move_r_imm32(SHR_R0, opd->imm);
1735 tmp = rcache_get_reg(SHR_R0, RC_GR_WRITE);
1736 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1737 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1738 emith_bic_r_imm(tmp, 3);
1743 switch ((op >> 12) & 0x0f)
1745 /////////////////////////////////////////////
1750 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1753 case 0: // STC SR,Rn 0000nnnn00000010
1756 case 1: // STC GBR,Rn 0000nnnn00010010
1759 case 2: // STC VBR,Rn 0000nnnn00100010
1765 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1766 emith_move_r_r(tmp, tmp3);
1768 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1770 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1771 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1772 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1774 tmp = rcache_get_reg_arg(1, GET_Rm());
1775 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1776 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1777 emith_add_r_r(tmp2, tmp3);
1778 emit_memhandler_write(op & 3);
1781 // MUL.L Rm,Rn 0000nnnnmmmm0111
1782 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1783 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1784 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1785 emith_mul(tmp3, tmp2, tmp);
1790 case 0: // CLRT 0000000000001000
1791 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1792 emith_bic_r_imm(sr, T);
1794 case 1: // SETT 0000000000011000
1795 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1796 emith_or_r_imm(sr, T);
1798 case 2: // CLRMAC 0000000000101000
1799 emit_move_r_imm32(SHR_MACL, 0);
1800 emit_move_r_imm32(SHR_MACH, 0);
1809 case 0: // NOP 0000000000001001
1811 case 1: // DIV0U 0000000000011001
1812 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1813 emith_bic_r_imm(sr, M|Q|T);
1815 case 2: // MOVT Rn 0000nnnn00101001
1816 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1817 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1818 emith_clear_msb(tmp2, sr, 31);
1825 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1828 case 0: // STS MACH,Rn 0000nnnn00001010
1831 case 1: // STS MACL,Rn 0000nnnn00011010
1834 case 2: // STS PR,Rn 0000nnnn00101010
1840 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1841 emith_move_r_r(tmp, tmp2);
1843 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1844 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1845 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1846 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1847 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1848 if ((op & 3) != 2) {
1849 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1851 emith_move_r_r(tmp2, tmp);
1852 rcache_free_tmp(tmp);
1854 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1855 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1856 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1857 /* MS 16 MAC bits unused if saturated */
1858 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1859 emith_tst_r_imm(sr, S);
1860 EMITH_SJMP_START(DCOND_EQ);
1861 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1862 EMITH_SJMP_END(DCOND_EQ);
1864 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1865 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1866 rcache_free_tmp(tmp2);
1867 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1868 emith_tst_r_imm(sr, S);
1870 EMITH_JMP_START(DCOND_EQ);
1871 emith_asr(tmp, tmp4, 15);
1872 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1873 EMITH_SJMP_START(DCOND_GE);
1874 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1875 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1876 EMITH_SJMP_END(DCOND_GE);
1877 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1878 EMITH_SJMP_START(DCOND_LE);
1879 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1880 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1881 EMITH_SJMP_END(DCOND_LE);
1882 EMITH_JMP_END(DCOND_EQ);
1884 rcache_free_tmp(tmp);
1889 /////////////////////////////////////////////
1891 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1893 tmp = rcache_get_reg_arg(0, GET_Rn());
1894 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1896 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1897 emit_memhandler_write(2);
1903 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1904 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1905 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1907 rcache_get_reg_arg(0, GET_Rn());
1908 rcache_get_reg_arg(1, GET_Rm());
1909 emit_memhandler_write(op & 3);
1911 case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100
1912 case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101
1913 case 0x06: // MOV.L Rm,@-Rn 0010nnnnmmmm0110
1914 rcache_get_reg_arg(1, GET_Rm()); // for Rm == Rn
1915 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1916 emith_sub_r_imm(tmp, (1 << (op & 3)));
1918 rcache_get_reg_arg(0, GET_Rn());
1919 emit_memhandler_write(op & 3);
1921 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1922 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1923 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1924 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1925 emith_bic_r_imm(sr, M|Q|T);
1926 emith_tst_r_imm(tmp2, (1<<31));
1927 EMITH_SJMP_START(DCOND_EQ);
1928 emith_or_r_imm_c(DCOND_NE, sr, Q);
1929 EMITH_SJMP_END(DCOND_EQ);
1930 emith_tst_r_imm(tmp3, (1<<31));
1931 EMITH_SJMP_START(DCOND_EQ);
1932 emith_or_r_imm_c(DCOND_NE, sr, M);
1933 EMITH_SJMP_END(DCOND_EQ);
1934 emith_teq_r_r(tmp2, tmp3);
1935 EMITH_SJMP_START(DCOND_PL);
1936 emith_or_r_imm_c(DCOND_MI, sr, T);
1937 EMITH_SJMP_END(DCOND_PL);
1939 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1940 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1941 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1942 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1943 emith_bic_r_imm(sr, T);
1944 emith_tst_r_r(tmp2, tmp3);
1945 emit_or_t_if_eq(sr);
1947 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1948 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1949 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1950 emith_and_r_r(tmp, tmp2);
1952 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1953 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1954 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1955 emith_eor_r_r(tmp, tmp2);
1957 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1958 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1959 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1960 emith_or_r_r(tmp, tmp2);
1962 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1963 tmp = rcache_get_tmp();
1964 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1965 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1966 emith_eor_r_r_r(tmp, tmp2, tmp3);
1967 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1968 emith_bic_r_imm(sr, T);
1969 emith_tst_r_imm(tmp, 0x000000ff);
1970 emit_or_t_if_eq(sr);
1971 emith_tst_r_imm(tmp, 0x0000ff00);
1972 emit_or_t_if_eq(sr);
1973 emith_tst_r_imm(tmp, 0x00ff0000);
1974 emit_or_t_if_eq(sr);
1975 emith_tst_r_imm(tmp, 0xff000000);
1976 emit_or_t_if_eq(sr);
1977 rcache_free_tmp(tmp);
1979 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1980 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1981 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1982 emith_lsr(tmp, tmp, 16);
1983 emith_or_r_r_lsl(tmp, tmp2, 16);
1985 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1986 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1987 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1988 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1990 emith_sext(tmp, tmp2, 16);
1992 emith_clear_msb(tmp, tmp2, 16);
1993 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1994 tmp2 = rcache_get_tmp();
1996 emith_sext(tmp2, tmp3, 16);
1998 emith_clear_msb(tmp2, tmp3, 16);
1999 emith_mul(tmp, tmp, tmp2);
2000 rcache_free_tmp(tmp2);
2005 /////////////////////////////////////////////
2009 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
2010 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
2011 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
2012 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
2013 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
2014 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2015 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
2016 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2017 emith_bic_r_imm(sr, T);
2018 emith_cmp_r_r(tmp2, tmp3);
2021 case 0x00: // CMP/EQ
2022 emit_or_t_if_eq(sr);
2024 case 0x02: // CMP/HS
2025 EMITH_SJMP_START(DCOND_LO);
2026 emith_or_r_imm_c(DCOND_HS, sr, T);
2027 EMITH_SJMP_END(DCOND_LO);
2029 case 0x03: // CMP/GE
2030 EMITH_SJMP_START(DCOND_LT);
2031 emith_or_r_imm_c(DCOND_GE, sr, T);
2032 EMITH_SJMP_END(DCOND_LT);
2034 case 0x06: // CMP/HI
2035 EMITH_SJMP_START(DCOND_LS);
2036 emith_or_r_imm_c(DCOND_HI, sr, T);
2037 EMITH_SJMP_END(DCOND_LS);
2039 case 0x07: // CMP/GT
2040 EMITH_SJMP_START(DCOND_LE);
2041 emith_or_r_imm_c(DCOND_GT, sr, T);
2042 EMITH_SJMP_END(DCOND_LE);
2046 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
2047 // Q1 = carry(Rn = (Rn << 1) | T)
2049 // Q2 = carry(Rn += Rm)
2051 // Q2 = carry(Rn -= Rm)
2053 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
2054 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2055 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2056 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2057 emith_tpop_carry(sr, 0);
2058 emith_adcf_r_r(tmp2, tmp2);
2059 emith_tpush_carry(sr, 0); // keep Q1 in T for now
2060 tmp4 = rcache_get_tmp();
2061 emith_and_r_r_imm(tmp4, sr, M);
2062 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
2063 rcache_free_tmp(tmp4);
2064 // add or sub, invert T if carry to get Q1 ^ Q2
2065 // in: (Q ^ M) passed in Q, Q1 in T
2066 emith_sh2_div1_step(tmp2, tmp3, sr);
2067 emith_bic_r_imm(sr, Q);
2068 emith_tst_r_imm(sr, M);
2069 EMITH_SJMP_START(DCOND_EQ);
2070 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
2071 EMITH_SJMP_END(DCOND_EQ);
2072 emith_tst_r_imm(sr, T);
2073 EMITH_SJMP_START(DCOND_EQ);
2074 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
2075 EMITH_SJMP_END(DCOND_EQ);
2076 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
2078 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
2079 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2080 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2081 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2082 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
2083 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
2085 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
2086 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
2087 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2088 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2090 emith_add_r_r(tmp, tmp2);
2092 emith_sub_r_r(tmp, tmp2);
2094 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
2095 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
2096 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2097 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2098 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2099 if (op & 4) { // adc
2100 emith_tpop_carry(sr, 0);
2101 emith_adcf_r_r(tmp, tmp2);
2102 emith_tpush_carry(sr, 0);
2104 emith_tpop_carry(sr, 1);
2105 emith_sbcf_r_r(tmp, tmp2);
2106 emith_tpush_carry(sr, 1);
2109 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
2110 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
2111 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2112 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2113 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2114 emith_bic_r_imm(sr, T);
2116 emith_addf_r_r(tmp, tmp2);
2118 emith_subf_r_r(tmp, tmp2);
2119 EMITH_SJMP_START(DCOND_VC);
2120 emith_or_r_imm_c(DCOND_VS, sr, T);
2121 EMITH_SJMP_END(DCOND_VC);
2123 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
2124 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2125 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2126 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2127 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
2128 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
2133 /////////////////////////////////////////////
2140 case 0: // SHLL Rn 0100nnnn00000000
2141 case 2: // SHAL Rn 0100nnnn00100000
2142 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2143 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2144 emith_tpop_carry(sr, 0); // dummy
2145 emith_lslf(tmp, tmp, 1);
2146 emith_tpush_carry(sr, 0);
2148 case 1: // DT Rn 0100nnnn00010000
2149 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2150 #if 0 // scheduling needs tuning
2151 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
2152 if (gconst_get(GET_Rn(), &tmp)) {
2153 // XXX: limit burned cycles
2154 emit_move_r_imm32(GET_Rn(), 0);
2155 emith_or_r_imm(sr, T);
2156 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
2160 emith_sh2_dtbf_loop();
2164 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2165 emith_bic_r_imm(sr, T);
2166 emith_subf_r_imm(tmp, 1);
2167 emit_or_t_if_eq(sr);
2174 case 0: // SHLR Rn 0100nnnn00000001
2175 case 2: // SHAR Rn 0100nnnn00100001
2176 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2177 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2178 emith_tpop_carry(sr, 0); // dummy
2180 emith_asrf(tmp, tmp, 1);
2182 emith_lsrf(tmp, tmp, 1);
2183 emith_tpush_carry(sr, 0);
2185 case 1: // CMP/PZ Rn 0100nnnn00010001
2186 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2187 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2188 emith_bic_r_imm(sr, T);
2189 emith_cmp_r_imm(tmp, 0);
2190 EMITH_SJMP_START(DCOND_LT);
2191 emith_or_r_imm_c(DCOND_GE, sr, T);
2192 EMITH_SJMP_END(DCOND_LT);
2200 case 0x02: // STS.L MACH,@-Rn 0100nnnn00000010
2203 case 0x12: // STS.L MACL,@-Rn 0100nnnn00010010
2206 case 0x22: // STS.L PR,@-Rn 0100nnnn00100010
2209 case 0x03: // STC.L SR,@-Rn 0100nnnn00000011
2212 case 0x13: // STC.L GBR,@-Rn 0100nnnn00010011
2215 case 0x23: // STC.L VBR,@-Rn 0100nnnn00100011
2221 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2222 emith_sub_r_imm(tmp2, 4);
2224 rcache_get_reg_arg(0, GET_Rn());
2225 tmp3 = rcache_get_reg_arg(1, tmp);
2227 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
2228 emit_memhandler_write(2);
2234 case 0x04: // ROTL Rn 0100nnnn00000100
2235 case 0x05: // ROTR Rn 0100nnnn00000101
2236 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2237 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2238 emith_tpop_carry(sr, 0); // dummy
2240 emith_rorf(tmp, tmp, 1);
2242 emith_rolf(tmp, tmp, 1);
2243 emith_tpush_carry(sr, 0);
2245 case 0x24: // ROTCL Rn 0100nnnn00100100
2246 case 0x25: // ROTCR Rn 0100nnnn00100101
2247 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2248 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2249 emith_tpop_carry(sr, 0);
2254 emith_tpush_carry(sr, 0);
2256 case 0x15: // CMP/PL Rn 0100nnnn00010101
2257 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2258 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2259 emith_bic_r_imm(sr, T);
2260 emith_cmp_r_imm(tmp, 0);
2261 EMITH_SJMP_START(DCOND_LE);
2262 emith_or_r_imm_c(DCOND_GT, sr, T);
2263 EMITH_SJMP_END(DCOND_LE);
2271 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
2274 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
2277 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
2280 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
2283 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
2286 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
2292 rcache_get_reg_arg(0, GET_Rn());
2293 tmp2 = emit_memhandler_read(2);
2294 if (tmp == SHR_SR) {
2295 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2296 emith_write_sr(sr, tmp2);
2299 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2300 emith_move_r_r(tmp, tmp2);
2302 rcache_free_tmp(tmp2);
2303 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2304 emith_add_r_imm(tmp, 4);
2311 // SHLL2 Rn 0100nnnn00001000
2312 // SHLR2 Rn 0100nnnn00001001
2316 // SHLL8 Rn 0100nnnn00011000
2317 // SHLR8 Rn 0100nnnn00011001
2321 // SHLL16 Rn 0100nnnn00101000
2322 // SHLR16 Rn 0100nnnn00101001
2328 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2330 emith_lsr(tmp2, tmp2, tmp);
2332 emith_lsl(tmp2, tmp2, tmp);
2337 case 0: // LDS Rm,MACH 0100mmmm00001010
2340 case 1: // LDS Rm,MACL 0100mmmm00011010
2343 case 2: // LDS Rm,PR 0100mmmm00101010
2349 emit_move_r_r(tmp2, GET_Rn());
2354 case 1: // TAS.B @Rn 0100nnnn00011011
2355 // XXX: is TAS working on 32X?
2356 rcache_get_reg_arg(0, GET_Rn());
2357 tmp = emit_memhandler_read(0);
2358 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2359 emith_bic_r_imm(sr, T);
2360 emith_cmp_r_imm(tmp, 0);
2361 emit_or_t_if_eq(sr);
2363 emith_or_r_imm(tmp, 0x80);
2364 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2365 emith_move_r_r(tmp2, tmp);
2366 rcache_free_tmp(tmp);
2367 rcache_get_reg_arg(0, GET_Rn());
2368 emit_memhandler_write(0);
2375 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2378 case 0: // LDC Rm,SR 0100mmmm00001110
2381 case 1: // LDC Rm,GBR 0100mmmm00011110
2384 case 2: // LDC Rm,VBR 0100mmmm00101110
2390 if (tmp2 == SHR_SR) {
2391 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2392 emith_write_sr(sr, tmp);
2395 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2396 emith_move_r_r(tmp2, tmp);
2400 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
2401 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2402 emith_sext(tmp, tmp, 16);
2403 emith_sext(tmp2, tmp2, 16);
2404 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2405 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2406 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
2407 rcache_free_tmp(tmp2);
2408 // XXX: MACH should be untouched when S is set?
2409 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2410 emith_tst_r_imm(sr, S);
2411 EMITH_JMP_START(DCOND_EQ);
2413 emith_asr(tmp, tmp3, 31);
2414 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2415 EMITH_JMP_START(DCOND_EQ);
2416 emith_move_r_imm(tmp3, 0x80000000);
2417 emith_tst_r_r(tmp4, tmp4);
2418 EMITH_SJMP_START(DCOND_MI);
2419 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2420 EMITH_SJMP_END(DCOND_MI);
2421 EMITH_JMP_END(DCOND_EQ);
2423 EMITH_JMP_END(DCOND_EQ);
2424 rcache_free_tmp(tmp);
2429 /////////////////////////////////////////////
2431 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
2432 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
2435 /////////////////////////////////////////////
2439 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2440 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2441 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2442 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2443 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2444 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
2445 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
2446 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2447 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2448 emith_add_r_imm(tmp, (1 << (op & 3)));
2453 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2454 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2457 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2458 emith_move_r_r(tmp2, tmp);
2460 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2461 emith_mvn_r_r(tmp2, tmp);
2463 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2466 tmp3 = rcache_get_tmp();
2467 tmp4 = rcache_get_tmp();
2468 emith_lsr(tmp3, tmp, 16);
2469 emith_or_r_r_lsl(tmp3, tmp, 24);
2470 emith_and_r_r_imm(tmp4, tmp, 0xff00);
2471 emith_or_r_r_lsl(tmp3, tmp4, 8);
2472 emith_rol(tmp2, tmp3, 16);
2473 rcache_free_tmp(tmp4);
2475 rcache_free_tmp(tmp3);
2477 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2478 emith_rol(tmp2, tmp, 16);
2480 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
2481 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2482 emith_tpop_carry(sr, 1);
2483 emith_negcf_r_r(tmp2, tmp);
2484 emith_tpush_carry(sr, 1);
2486 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2487 emith_neg_r_r(tmp2, tmp);
2489 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2490 emith_clear_msb(tmp2, tmp, 24);
2492 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2493 emith_clear_msb(tmp2, tmp, 16);
2495 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2496 emith_sext(tmp2, tmp, 8);
2498 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2499 emith_sext(tmp2, tmp, 16);
2506 /////////////////////////////////////////////
2508 // ADD #imm,Rn 0111nnnniiiiiiii
2509 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2510 if (op & 0x80) { // adding negative
2511 emith_sub_r_imm(tmp, -op & 0xff);
2513 emith_add_r_imm(tmp, op & 0xff);
2516 /////////////////////////////////////////////
2518 switch (op & 0x0f00)
2520 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2521 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2523 tmp = rcache_get_reg_arg(0, GET_Rm());
2524 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2525 tmp3 = (op & 0x100) >> 8;
2527 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
2528 emit_memhandler_write(tmp3);
2530 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2531 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
2532 tmp = (op & 0x100) >> 8;
2533 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
2535 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2536 // XXX: could use cmn
2537 tmp = rcache_get_tmp();
2538 tmp2 = rcache_get_reg(0, RC_GR_READ);
2539 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2540 emith_move_r_imm_s8(tmp, op & 0xff);
2541 emith_bic_r_imm(sr, T);
2542 emith_cmp_r_r(tmp2, tmp);
2543 emit_or_t_if_eq(sr);
2544 rcache_free_tmp(tmp);
2549 /////////////////////////////////////////////
2551 switch (op & 0x0f00)
2553 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2554 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2555 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2557 tmp = rcache_get_reg_arg(0, SHR_GBR);
2558 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2559 tmp3 = (op & 0x300) >> 8;
2560 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2561 emit_memhandler_write(tmp3);
2563 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2564 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2565 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2566 tmp = (op & 0x300) >> 8;
2567 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
2569 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2570 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2571 emith_sub_r_imm(tmp, 4*2);
2573 tmp = rcache_get_reg_arg(0, SHR_SP);
2574 emith_add_r_imm(tmp, 4);
2575 tmp = rcache_get_reg_arg(1, SHR_SR);
2576 emith_clear_msb(tmp, tmp, 22);
2577 emit_memhandler_write(2);
2579 rcache_get_reg_arg(0, SHR_SP);
2580 tmp = rcache_get_tmp_arg(1);
2581 emith_move_r_imm(tmp, pc);
2582 emit_memhandler_write(2);
2584 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
2585 // indirect jump -> back to dispatcher
2587 emith_jump(sh2_drc_dispatcher);
2589 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2590 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2591 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2592 emith_bic_r_imm(sr, T);
2593 emith_tst_r_imm(tmp, op & 0xff);
2594 emit_or_t_if_eq(sr);
2596 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2597 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2598 emith_and_r_imm(tmp, op & 0xff);
2600 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2601 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2602 emith_eor_r_imm(tmp, op & 0xff);
2604 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2605 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2606 emith_or_r_imm(tmp, op & 0xff);
2608 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2609 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2610 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2611 emith_bic_r_imm(sr, T);
2612 emith_tst_r_imm(tmp, op & 0xff);
2613 emit_or_t_if_eq(sr);
2614 rcache_free_tmp(tmp);
2616 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2617 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2618 emith_and_r_imm(tmp, op & 0xff);
2620 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2621 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2622 emith_eor_r_imm(tmp, op & 0xff);
2624 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2625 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2626 emith_or_r_imm(tmp, op & 0xff);
2628 tmp2 = rcache_get_tmp_arg(1);
2629 emith_move_r_r(tmp2, tmp);
2630 rcache_free_tmp(tmp);
2631 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2632 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2633 emith_add_r_r(tmp3, tmp4);
2634 emit_memhandler_write(0);
2639 /////////////////////////////////////////////
2641 // MOV #imm,Rn 1110nnnniiiiiiii
2642 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
2647 if (!(op_flags[i] & OF_B_IN_DS))
2648 elprintf_sh2(sh2, EL_ANOMALY,
2649 "drc: illegal op %04x @ %08x", op, pc - 2);
2651 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2652 emith_sub_r_imm(tmp, 4*2);
2654 tmp = rcache_get_reg_arg(0, SHR_SP);
2655 emith_add_r_imm(tmp, 4);
2656 tmp = rcache_get_reg_arg(1, SHR_SR);
2657 emith_clear_msb(tmp, tmp, 22);
2658 emit_memhandler_write(2);
2660 rcache_get_reg_arg(0, SHR_SP);
2661 tmp = rcache_get_tmp_arg(1);
2662 if (drcf.pending_branch_indirect) {
2663 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
2664 emith_move_r_r(tmp, tmp2);
2667 emith_move_r_imm(tmp, pc - 2);
2668 emit_memhandler_write(2);
2670 v = (op_flags[i] & OF_B_IN_DS) ? 6 : 4;
2671 emit_memhandler_read_rr(SHR_PC, SHR_VBR, v * 4, 2);
2672 // indirect jump -> back to dispatcher
2674 emith_jump(sh2_drc_dispatcher);
2679 rcache_unlock_all();
2681 cycles += opd->cycles;
2683 if (op_flags[i+1] & OF_DELAY_OP) {
2684 do_host_disasm(tcache_id);
2689 if (drcf.test_irq && !drcf.pending_branch_direct) {
2690 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2692 if (!drcf.pending_branch_indirect)
2693 emit_move_r_imm32(SHR_PC, pc);
2695 emith_call(sh2_drc_test_irq);
2699 // branch handling (with/without delay)
2700 if (drcf.pending_branch_direct)
2702 struct op_data *opd_b =
2703 (op_flags[i] & OF_DELAY_OP) ? &ops[i-1] : opd;
2704 u32 target_pc = opd_b->imm;
2706 void *target = NULL;
2708 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2711 if (opd_b->op != OP_BRANCH)
2712 cond = (opd_b->op == OP_BRANCH_CF) ? DCOND_EQ : DCOND_NE;
2714 int ctaken = (op_flags[i] & OF_DELAY_OP) ? 1 : 2;
2716 if (delay_dep_fw & BITMASK1(SHR_T))
2717 emith_tst_r_imm(sr, T_save);
2719 emith_tst_r_imm(sr, T);
2721 emith_sub_r_imm_c(cond, sr, ctaken<<12);
2726 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0)
2729 // XXX: jumps back can be linked already
2730 if (branch_patch_count < MAX_LOCAL_BRANCHES) {
2731 target = tcache_ptr;
2732 branch_patch_pc[branch_patch_count] = target_pc;
2733 branch_patch_ptr[branch_patch_count] = target;
2734 branch_patch_count++;
2737 dbg(1, "warning: too many local branches");
2743 // can't resolve branch locally, make a block exit
2744 emit_move_r_imm32(SHR_PC, target_pc);
2747 target = dr_prepare_ext_branch(target_pc, sh2->is_slave, tcache_id);
2753 emith_jump_cond_patchable(cond, target);
2755 emith_jump_patchable(target);
2756 rcache_invalidate();
2759 drcf.pending_branch_direct = 0;
2761 else if (drcf.pending_branch_indirect) {
2762 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2765 emith_jump(sh2_drc_dispatcher);
2766 drcf.pending_branch_indirect = 0;
2769 do_host_disasm(tcache_id);
2772 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2776 // check the last op
2777 if (op_flags[i-1] & OF_DELAY_OP)
2782 if (opd->op != OP_BRANCH && opd->op != OP_BRANCH_R
2783 && opd->op != OP_BRANCH_RF && opd->op != OP_RTE)
2787 emit_move_r_imm32(SHR_PC, pc);
2790 target = dr_prepare_ext_branch(pc, sh2->is_slave, tcache_id);
2793 emith_jump_patchable(target);
2796 // link local branches
2797 for (i = 0; i < branch_patch_count; i++) {
2800 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2801 target = branch_target_ptr[t];
2802 if (target == NULL) {
2803 // flush pc and go back to dispatcher (this should no longer happen)
2804 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
2805 target = tcache_ptr;
2806 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2808 emith_jump(sh2_drc_dispatcher);
2810 emith_jump_patch(branch_patch_ptr[i], target);
2813 // mark memory blocks as containing compiled code
2814 // override any overlay blocks as they become unreachable anyway
2815 if ((block->addr & 0xc7fc0000) == 0x06000000
2816 || (block->addr & 0xfffff000) == 0xc0000000)
2818 u16 *drc_ram_blk = NULL;
2819 u32 addr, mask = 0, shift = 0;
2821 if (tcache_id != 0) {
2823 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2824 shift = SH2_DRCBLK_DA_SHIFT;
2829 drc_ram_blk = Pico32xMem->drcblk_ram;
2830 shift = SH2_DRCBLK_RAM_SHIFT;
2834 // mark recompiled insns
2835 drc_ram_blk[(base_pc & mask) >> shift] = 1;
2836 for (pc = base_pc; pc < end_pc; pc += 2)
2837 drc_ram_blk[(pc & mask) >> shift] = 1;
2840 for (i = 0; i < literal_addr_count; i++) {
2841 tmp = literal_addr[i];
2842 drc_ram_blk[(tmp & mask) >> shift] = 1;
2845 // add to invalidation lookup lists
2846 addr = base_pc & ~(INVAL_PAGE_SIZE - 1);
2847 for (; addr < end_literals; addr += INVAL_PAGE_SIZE) {
2848 i = (addr & mask) / INVAL_PAGE_SIZE;
2849 add_to_block_list(&inval_lookup[tcache_id][i], block);
2853 tcache_ptrs[tcache_id] = tcache_ptr;
2855 host_instructions_updated(block_entry_ptr, tcache_ptr);
2857 do_host_disasm(tcache_id);
2859 if (drcf.literals_disabled && literal_addr_count)
2860 dbg(1, "literals_disabled && literal_addr_count?");
2861 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2862 tcache_id, blkid_main,
2863 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2864 insns_compiled, host_insn_count, (float)host_insn_count / insns_compiled);
2865 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2866 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2869 tcache_dsm_ptrs[tcache_id] = block_entry_ptr;
2870 do_host_disasm(tcache_id);
2878 return block_entry_ptr;
2881 static void sh2_generate_utils(void)
2883 int arg0, arg1, arg2, sr, tmp;
2885 sh2_drc_write32 = p32x_sh2_write32;
2886 sh2_drc_read8 = p32x_sh2_read8;
2887 sh2_drc_read16 = p32x_sh2_read16;
2888 sh2_drc_read32 = p32x_sh2_read32;
2890 host_arg2reg(arg0, 0);
2891 host_arg2reg(arg1, 1);
2892 host_arg2reg(arg2, 2);
2893 emith_move_r_r(arg0, arg0); // nop
2895 // sh2_drc_exit(void)
2896 sh2_drc_exit = (void *)tcache_ptr;
2897 emit_do_static_regs(1, arg2);
2898 emith_sh2_drc_exit();
2900 // sh2_drc_dispatcher(void)
2901 sh2_drc_dispatcher = (void *)tcache_ptr;
2902 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2903 emith_cmp_r_imm(sr, 0);
2904 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2905 rcache_invalidate();
2906 emith_ctx_read(arg0, SHR_PC * 4);
2907 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2908 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2909 emith_call(dr_lookup_block);
2911 // lookup failed, call sh2_translate()
2912 emith_move_r_r(arg0, CONTEXT_REG);
2913 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2914 emith_call(sh2_translate);
2916 // sh2_translate() failed, flush cache and retry
2917 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2918 emith_call(flush_tcache);
2919 emith_move_r_r(arg0, CONTEXT_REG);
2920 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2921 emith_call(sh2_translate);
2923 // XXX: can't translate, fail
2924 emith_call(dr_failure);
2926 // sh2_drc_test_irq(void)
2927 // assumes it's called from main function (may jump to dispatcher)
2928 sh2_drc_test_irq = (void *)tcache_ptr;
2929 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2930 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2931 emith_lsr(arg0, sr, I_SHIFT);
2932 emith_and_r_imm(arg0, 0x0f);
2933 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2934 EMITH_SJMP_START(DCOND_GT);
2935 emith_ret_c(DCOND_LE); // nope, return
2936 EMITH_SJMP_END(DCOND_GT);
2938 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2939 emith_sub_r_imm(tmp, 4*2);
2942 tmp = rcache_get_reg_arg(0, SHR_SP);
2943 emith_add_r_imm(tmp, 4);
2944 tmp = rcache_get_reg_arg(1, SHR_SR);
2945 emith_clear_msb(tmp, tmp, 22);
2946 emith_move_r_r(arg2, CONTEXT_REG);
2947 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
2948 rcache_invalidate();
2950 rcache_get_reg_arg(0, SHR_SP);
2951 emith_ctx_read(arg1, SHR_PC * 4);
2952 emith_move_r_r(arg2, CONTEXT_REG);
2953 emith_call(p32x_sh2_write32);
2954 rcache_invalidate();
2955 // update I, cycles, do callback
2956 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2957 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2958 emith_bic_r_imm(sr, I);
2959 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2960 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2962 emith_move_r_r(arg0, CONTEXT_REG);
2963 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2965 emith_lsl(arg0, arg0, 2);
2966 emith_ctx_read(arg1, SHR_VBR * 4);
2967 emith_add_r_r(arg0, arg1);
2968 emit_memhandler_read(2);
2969 emith_ctx_write(arg0, SHR_PC * 4);
2971 emith_add_r_imm(xSP, 4); // fix stack
2973 emith_jump(sh2_drc_dispatcher);
2974 rcache_invalidate();
2976 // sh2_drc_entry(SH2 *sh2)
2977 sh2_drc_entry = (void *)tcache_ptr;
2978 emith_sh2_drc_entry();
2979 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2980 emit_do_static_regs(0, arg2);
2981 emith_call(sh2_drc_test_irq);
2982 emith_jump(sh2_drc_dispatcher);
2984 // sh2_drc_write8(u32 a, u32 d)
2985 sh2_drc_write8 = (void *)tcache_ptr;
2986 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2987 emith_sh2_wcall(arg0, arg2);
2989 // sh2_drc_write16(u32 a, u32 d)
2990 sh2_drc_write16 = (void *)tcache_ptr;
2991 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2992 emith_sh2_wcall(arg0, arg2);
2996 #define MAKE_READ_WRAPPER(func) { \
2997 void *tmp = (void *)tcache_ptr; \
3000 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
3001 emith_addf_r_r(arg2, arg0); \
3002 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
3003 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
3004 emith_adc_r_imm(arg2, 0x01000000); \
3005 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
3006 emith_pop_and_ret(); \
3009 #define MAKE_WRITE_WRAPPER(func) { \
3010 void *tmp = (void *)tcache_ptr; \
3011 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
3012 emith_addf_r_r(arg2, arg1); \
3013 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
3014 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
3015 emith_adc_r_imm(arg2, 0x01000000); \
3016 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
3017 emith_move_r_r(arg2, CONTEXT_REG); \
3022 MAKE_READ_WRAPPER(sh2_drc_read8);
3023 MAKE_READ_WRAPPER(sh2_drc_read16);
3024 MAKE_READ_WRAPPER(sh2_drc_read32);
3025 MAKE_WRITE_WRAPPER(sh2_drc_write8);
3026 MAKE_WRITE_WRAPPER(sh2_drc_write16);
3027 MAKE_WRITE_WRAPPER(sh2_drc_write32);
3029 host_dasm_new_symbol(sh2_drc_read8);
3030 host_dasm_new_symbol(sh2_drc_read16);
3031 host_dasm_new_symbol(sh2_drc_read32);
3032 host_dasm_new_symbol(sh2_drc_write32);
3036 rcache_invalidate();
3038 host_dasm_new_symbol(sh2_drc_entry);
3039 host_dasm_new_symbol(sh2_drc_dispatcher);
3040 host_dasm_new_symbol(sh2_drc_exit);
3041 host_dasm_new_symbol(sh2_drc_test_irq);
3042 host_dasm_new_symbol(sh2_drc_write8);
3043 host_dasm_new_symbol(sh2_drc_write16);
3047 static void sh2_smc_rm_block(struct block_desc *bd, int tcache_id, u32 ram_mask)
3049 u32 i, addr, end_addr;
3052 dbg(2, " killing block %08x-%08x-%08x, blkid %d,%d",
3053 bd->addr, bd->addr + bd->size_nolit, bd->addr + bd->size,
3054 tcache_id, bd - block_tables[tcache_id]);
3055 if (bd->addr == 0 || bd->entry_count == 0) {
3056 dbg(1, " killing dead block!? %08x", bd->addr);
3060 // remove from inval_lookup
3061 addr = bd->addr & ~(INVAL_PAGE_SIZE - 1);
3062 end_addr = bd->addr + bd->size;
3063 for (; addr < end_addr; addr += INVAL_PAGE_SIZE) {
3064 i = (addr & ram_mask) / INVAL_PAGE_SIZE;
3065 rm_from_block_list(&inval_lookup[tcache_id][i], bd);
3070 // remove from hash table, make incoming links unresolved
3071 // XXX: maybe patch branches w/flush instead?
3072 for (i = 0; i < bd->entry_count; i++) {
3073 rm_from_hashlist(&bd->entryp[i], tcache_id);
3075 // since we never reuse tcache space of dead blocks,
3076 // insert jump to dispatcher for blocks that are linked to this
3077 tcache_ptr = bd->entryp[i].tcache_ptr;
3078 emit_move_r_imm32(SHR_PC, bd->entryp[i].pc);
3080 emith_jump(sh2_drc_dispatcher);
3082 host_instructions_updated(bd->entryp[i].tcache_ptr, tcache_ptr);
3084 unregister_links(&bd->entryp[i], tcache_id);
3089 bd->addr = bd->size = bd->size_nolit = 0;
3090 bd->entry_count = 0;
3094 04205:243: == msh2 block #0,200 060017a8-060017f0 -> 0x27cb9c
3095 060017a8 d11c MOV.L @($70,PC),R1 ; @$0600181c
3097 04230:261: msh2 xsh w32 [260017a8] d225e304
3098 04230:261: msh2 smc check @260017a8
3099 04239:226: = ssh2 enter 060017a8 0x27cb9c, c=173
3101 static void sh2_smc_rm_blocks(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
3103 struct block_list **blist = NULL, *entry;
3104 struct block_desc *block;
3105 u32 start_addr, end_addr, taddr, i;
3106 u32 from = ~0, to = 0;
3108 // ignore cache-through
3111 blist = &inval_lookup[tcache_id][(a & mask) / INVAL_PAGE_SIZE];
3113 while (entry != NULL) {
3114 block = entry->block;
3115 start_addr = block->addr & ~0x20000000;
3116 end_addr = start_addr + block->size;
3117 if (start_addr <= a && a < end_addr) {
3118 // get addr range that includes all removed blocks
3119 if (from > start_addr)
3124 sh2_smc_rm_block(block, tcache_id, mask);
3125 if (a >= start_addr + block->size_nolit)
3126 literal_disabled_frames = 3;
3128 // entry lost, restart search
3132 entry = entry->next;
3138 // update range around a to match latest state
3139 from &= ~(INVAL_PAGE_SIZE - 1);
3140 to |= (INVAL_PAGE_SIZE - 1);
3141 for (taddr = from; taddr < to; taddr += INVAL_PAGE_SIZE) {
3142 i = (taddr & mask) / INVAL_PAGE_SIZE;
3143 entry = inval_lookup[tcache_id][i];
3145 for (; entry != NULL; entry = entry->next) {
3146 block = entry->block;
3148 start_addr = block->addr & ~0x20000000;
3149 if (start_addr > a) {
3150 if (to > start_addr)
3154 end_addr = start_addr + block->size;
3155 if (from < end_addr)
3163 u16 *p = drc_ram_blk + ((from & mask) >> shift);
3164 memset(p, 0, (to - from) >> (shift - 1));
3168 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
3170 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3171 sh2_smc_rm_blocks(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
3174 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
3176 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3177 sh2_smc_rm_blocks(a, Pico32xMem->drcblk_da[cpuid],
3178 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
3181 int sh2_execute_drc(SH2 *sh2c, int cycles)
3185 // cycles are kept in SHR_SR unused bits (upper 20)
3186 // bit11 contains T saved for delay slot
3187 // others are usual SH2 flags
3189 sh2c->sr |= cycles << 12;
3190 sh2_drc_entry(sh2c);
3193 ret_cycles = (signed int)sh2c->sr >> 12;
3195 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
3202 void block_stats(void)
3204 int c, b, i, total = 0;
3206 printf("block stats:\n");
3207 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3208 for (i = 0; i < block_counts[b]; i++)
3209 if (block_tables[b][i].addr != 0)
3210 total += block_tables[b][i].refcount;
3212 for (c = 0; c < 10; c++) {
3213 struct block_desc *blk, *maxb = NULL;
3215 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
3216 for (i = 0; i < block_counts[b]; i++) {
3217 blk = &block_tables[b][i];
3218 if (blk->addr != 0 && blk->refcount > max) {
3219 max = blk->refcount;
3226 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
3227 (double)maxb->refcount / total * 100.0);
3231 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3232 for (i = 0; i < block_counts[b]; i++)
3233 block_tables[b][i].refcount = 0;
3236 #define block_stats()
3239 void sh2_drc_flush_all(void)
3247 void sh2_drc_mem_setup(SH2 *sh2)
3249 // fill the convenience pointers
3250 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
3251 sh2->p_da = sh2->data_array;
3252 sh2->p_sdram = Pico32xMem->sdram;
3253 sh2->p_rom = Pico.rom;
3256 void sh2_drc_frame(void)
3258 if (literal_disabled_frames > 0)
3259 literal_disabled_frames--;
3262 int sh2_drc_init(SH2 *sh2)
3266 if (block_tables[0] == NULL)
3268 for (i = 0; i < TCACHE_BUFFERS; i++) {
3269 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3270 if (block_tables[i] == NULL)
3272 // max 2 block links (exits) per block
3273 block_link_pool[i] = calloc(block_link_pool_max_counts[i],
3274 sizeof(*block_link_pool[0]));
3275 if (block_link_pool[i] == NULL)
3278 inval_lookup[i] = calloc(ram_sizes[i] / INVAL_PAGE_SIZE,
3279 sizeof(inval_lookup[0]));
3280 if (inval_lookup[i] == NULL)
3283 hash_tables[i] = calloc(hash_table_sizes[i], sizeof(*hash_tables[0]));
3284 if (hash_tables[i] == NULL)
3287 memset(block_counts, 0, sizeof(block_counts));
3288 memset(block_link_pool_counts, 0, sizeof(block_link_pool_counts));
3291 tcache_ptr = tcache;
3292 sh2_generate_utils();
3293 host_instructions_updated(tcache, tcache_ptr);
3295 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
3296 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
3297 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
3300 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3301 tcache_dsm_ptrs[i] = tcache_bases[i];
3303 tcache_dsm_ptrs[0] = tcache;
3307 hash_collisions = 0;
3314 sh2_drc_finish(sh2);
3318 void sh2_drc_finish(SH2 *sh2)
3322 if (block_tables[0] == NULL)
3325 sh2_drc_flush_all();
3327 for (i = 0; i < TCACHE_BUFFERS; i++) {
3329 printf("~~~ tcache %d\n", i);
3330 tcache_dsm_ptrs[i] = tcache_bases[i];
3331 tcache_ptr = tcache_ptrs[i];
3335 if (block_tables[i] != NULL)
3336 free(block_tables[i]);
3337 block_tables[i] = NULL;
3338 if (block_link_pool[i] == NULL)
3339 free(block_link_pool[i]);
3340 block_link_pool[i] = NULL;
3342 if (inval_lookup[i] == NULL)
3343 free(inval_lookup[i]);
3344 inval_lookup[i] = NULL;
3346 if (hash_tables[i] != NULL) {
3347 free(hash_tables[i]);
3348 hash_tables[i] = NULL;
3355 #endif /* DRC_SH2 */
3357 static void *dr_get_pc_base(u32 pc, int is_slave)
3362 if ((pc & ~0x7ff) == 0) {
3364 ret = is_slave ? Pico32xMem->sh2_rom_s.w : Pico32xMem->sh2_rom_m.w;
3367 else if ((pc & 0xfffff000) == 0xc0000000) {
3369 ret = sh2s[is_slave].data_array;
3372 else if ((pc & 0xc6000000) == 0x06000000) {
3374 ret = Pico32xMem->sdram;
3377 else if ((pc & 0xc6000000) == 0x02000000) {
3379 if ((pc & 0x3fffff) < Pico.romsize)
3385 return (void *)-1; // NULL is valid value
3387 return (char *)ret - (pc & ~mask);
3390 void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
3391 u32 *end_literals_out)
3395 u32 end_pc, end_literals = 0;
3396 u32 lowest_mova = 0;
3397 struct op_data *opd;
3398 int next_is_delay = 0;
3402 memset(op_flags, 0, BLOCK_INSN_LIMIT);
3404 dr_pc_base = dr_get_pc_base(base_pc, is_slave);
3406 // 1st pass: disassemble
3407 for (i = 0, pc = base_pc; ; i++, pc += 2) {
3408 // we need an ops[] entry after the last one initialized,
3409 // so do it before end_block checks
3411 opd->op = OP_UNHANDLED;
3413 opd->source = opd->dest = 0;
3417 if (next_is_delay) {
3418 op_flags[i] |= OF_DELAY_OP;
3421 else if (end_block || i >= BLOCK_INSN_LIMIT - 2)
3425 switch ((op & 0xf000) >> 12)
3427 /////////////////////////////////////////////
3434 case 0: // STC SR,Rn 0000nnnn00000010
3437 case 1: // STC GBR,Rn 0000nnnn00010010
3440 case 2: // STC VBR,Rn 0000nnnn00100010
3447 opd->source = BITMASK1(tmp);
3448 opd->dest = BITMASK1(GET_Rn());
3451 CHECK_UNHANDLED_BITS(0xd0, undefined);
3452 // BRAF Rm 0000mmmm00100011
3453 // BSRF Rm 0000mmmm00000011
3454 opd->op = OP_BRANCH_RF;
3456 opd->source = BITMASK1(opd->rm);
3457 opd->dest = BITMASK1(SHR_PC);
3459 opd->dest |= BITMASK1(SHR_PR);
3464 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
3465 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
3466 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
3467 opd->source = BITMASK3(GET_Rm(), SHR_R0, GET_Rn());
3470 // MUL.L Rm,Rn 0000nnnnmmmm0111
3471 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3472 opd->dest = BITMASK1(SHR_MACL);
3476 CHECK_UNHANDLED_BITS(0xf00, undefined);
3479 case 0: // CLRT 0000000000001000
3480 opd->op = OP_SETCLRT;
3481 opd->dest = BITMASK1(SHR_T);
3484 case 1: // SETT 0000000000011000
3485 opd->op = OP_SETCLRT;
3486 opd->dest = BITMASK1(SHR_T);
3489 case 2: // CLRMAC 0000000000101000
3490 opd->dest = BITMASK3(SHR_T, SHR_MACL, SHR_MACH);
3499 case 0: // NOP 0000000000001001
3500 CHECK_UNHANDLED_BITS(0xf00, undefined);
3502 case 1: // DIV0U 0000000000011001
3503 CHECK_UNHANDLED_BITS(0xf00, undefined);
3504 opd->dest = BITMASK2(SHR_SR, SHR_T);
3506 case 2: // MOVT Rn 0000nnnn00101001
3507 opd->source = BITMASK1(SHR_T);
3508 opd->dest = BITMASK1(GET_Rn());
3517 case 0: // STS MACH,Rn 0000nnnn00001010
3520 case 1: // STS MACL,Rn 0000nnnn00011010
3523 case 2: // STS PR,Rn 0000nnnn00101010
3530 opd->source = BITMASK1(tmp);
3531 opd->dest = BITMASK1(GET_Rn());
3534 CHECK_UNHANDLED_BITS(0xf00, undefined);
3537 case 0: // RTS 0000000000001011
3538 opd->op = OP_BRANCH_R;
3540 opd->source = BITMASK1(opd->rm);
3541 opd->dest = BITMASK1(SHR_PC);
3546 case 1: // SLEEP 0000000000011011
3550 case 2: // RTE 0000000000101011
3552 opd->source = BITMASK1(SHR_SP);
3553 opd->dest = BITMASK2(SHR_SR, SHR_PC);
3562 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
3563 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
3564 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
3565 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3566 opd->dest = BITMASK1(GET_Rn());
3568 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
3569 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3570 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3578 /////////////////////////////////////////////
3580 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
3581 opd->source = BITMASK1(GET_Rm());
3582 opd->source = BITMASK1(GET_Rn());
3583 opd->imm = (op & 0x0f) * 4;
3586 /////////////////////////////////////////////
3590 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
3591 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
3592 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
3593 opd->source = BITMASK1(GET_Rm());
3594 opd->source = BITMASK1(GET_Rn());
3596 case 0x04: // MOV.B Rm,@-Rn 0010nnnnmmmm0100
3597 case 0x05: // MOV.W Rm,@-Rn 0010nnnnmmmm0101
3598 case 0x06: // MOV.L Rm,@-Rn 0010nnnnmmmm0110
3599 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3600 opd->dest = BITMASK1(GET_Rn());
3602 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
3603 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3604 opd->dest = BITMASK1(SHR_SR);
3606 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
3607 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3608 opd->dest = BITMASK1(SHR_T);
3610 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
3611 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
3612 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
3613 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3614 opd->dest = BITMASK1(GET_Rn());
3616 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
3617 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3618 opd->dest = BITMASK1(SHR_T);
3620 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
3621 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3622 opd->dest = BITMASK1(GET_Rn());
3624 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
3625 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
3626 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3627 opd->dest = BITMASK1(SHR_MACL);
3634 /////////////////////////////////////////////
3638 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
3639 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
3640 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
3641 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
3642 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
3643 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3644 opd->dest = BITMASK1(SHR_T);
3646 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
3647 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_SR);
3648 opd->dest = BITMASK2(GET_Rn(), SHR_SR);
3650 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
3651 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
3652 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3653 opd->dest = BITMASK2(SHR_MACL, SHR_MACH);
3656 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
3657 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
3658 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3659 opd->dest = BITMASK1(GET_Rn());
3661 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
3662 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
3663 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_T);
3664 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3666 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
3667 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
3668 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3669 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3676 /////////////////////////////////////////////
3683 case 0: // SHLL Rn 0100nnnn00000000
3684 case 2: // SHAL Rn 0100nnnn00100000
3685 opd->source = BITMASK1(GET_Rn());
3686 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3688 case 1: // DT Rn 0100nnnn00010000
3689 opd->source = BITMASK1(GET_Rn());
3690 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3699 case 0: // SHLR Rn 0100nnnn00000001
3700 case 2: // SHAR Rn 0100nnnn00100001
3701 opd->source = BITMASK1(GET_Rn());
3702 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3704 case 1: // CMP/PZ Rn 0100nnnn00010001
3705 opd->source = BITMASK1(GET_Rn());
3706 opd->dest = BITMASK1(SHR_T);
3716 case 0x02: // STS.L MACH,@-Rn 0100nnnn00000010
3719 case 0x12: // STS.L MACL,@-Rn 0100nnnn00010010
3722 case 0x22: // STS.L PR,@-Rn 0100nnnn00100010
3725 case 0x03: // STC.L SR,@-Rn 0100nnnn00000011
3729 case 0x13: // STC.L GBR,@-Rn 0100nnnn00010011
3733 case 0x23: // STC.L VBR,@-Rn 0100nnnn00100011
3740 opd->source = BITMASK2(GET_Rn(), tmp);
3741 opd->dest = BITMASK1(GET_Rn());
3747 case 0x04: // ROTL Rn 0100nnnn00000100
3748 case 0x05: // ROTR Rn 0100nnnn00000101
3749 opd->source = BITMASK1(GET_Rn());
3750 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3752 case 0x24: // ROTCL Rn 0100nnnn00100100
3753 case 0x25: // ROTCR Rn 0100nnnn00100101
3754 opd->source = BITMASK2(GET_Rn(), SHR_T);
3755 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3757 case 0x15: // CMP/PL Rn 0100nnnn00010101
3758 opd->source = BITMASK1(GET_Rn());
3759 opd->dest = BITMASK1(SHR_T);
3769 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
3772 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
3775 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
3778 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
3782 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
3786 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
3793 opd->source = BITMASK1(GET_Rn());
3794 opd->dest = BITMASK2(GET_Rn(), tmp);
3801 // SHLL2 Rn 0100nnnn00001000
3802 // SHLR2 Rn 0100nnnn00001001
3805 // SHLL8 Rn 0100nnnn00011000
3806 // SHLR8 Rn 0100nnnn00011001
3809 // SHLL16 Rn 0100nnnn00101000
3810 // SHLR16 Rn 0100nnnn00101001
3815 opd->source = BITMASK1(GET_Rn());
3816 opd->dest = BITMASK1(GET_Rn());
3821 case 0: // LDS Rm,MACH 0100mmmm00001010
3824 case 1: // LDS Rm,MACL 0100mmmm00011010
3827 case 2: // LDS Rm,PR 0100mmmm00101010
3834 opd->source = BITMASK1(GET_Rn());
3835 opd->dest = BITMASK1(tmp);
3840 case 0: // JSR @Rm 0100mmmm00001011
3841 opd->dest = BITMASK1(SHR_PR);
3842 case 2: // JMP @Rm 0100mmmm00101011
3843 opd->op = OP_BRANCH_R;
3845 opd->source = BITMASK1(opd->rm);
3846 opd->dest |= BITMASK1(SHR_PC);
3851 case 1: // TAS.B @Rn 0100nnnn00011011
3852 opd->source = BITMASK1(GET_Rn());
3853 opd->dest = BITMASK1(SHR_T);
3863 case 0: // LDC Rm,SR 0100mmmm00001110
3866 case 1: // LDC Rm,GBR 0100mmmm00011110
3869 case 2: // LDC Rm,VBR 0100mmmm00101110
3876 opd->source = BITMASK1(GET_Rn());
3877 opd->dest = BITMASK1(tmp);
3880 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
3881 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3882 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3890 /////////////////////////////////////////////
3892 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
3893 opd->source = BITMASK1(GET_Rm());
3894 opd->dest = BITMASK1(GET_Rn());
3895 opd->imm = (op & 0x0f) * 4;
3898 /////////////////////////////////////////////
3902 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
3903 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
3904 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
3905 opd->dest = BITMASK1(GET_Rm());
3906 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
3907 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
3908 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
3909 opd->source = BITMASK1(GET_Rm());
3910 opd->dest |= BITMASK1(GET_Rn());
3912 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
3913 opd->source = BITMASK2(GET_Rm(), SHR_T);
3914 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3916 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
3919 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
3920 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
3921 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
3922 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
3923 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
3924 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
3925 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
3926 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
3928 opd->source = BITMASK1(GET_Rm());
3929 opd->dest = BITMASK1(GET_Rn());
3934 /////////////////////////////////////////////
3936 // ADD #imm,Rn 0111nnnniiiiiiii
3937 opd->source = opd->dest = BITMASK1(GET_Rn());
3938 opd->imm = (int)(signed char)op;
3941 /////////////////////////////////////////////
3943 switch (op & 0x0f00)
3945 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
3946 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3947 opd->imm = (op & 0x0f);
3949 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
3950 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3951 opd->imm = (op & 0x0f) * 2;
3953 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
3954 opd->source = BITMASK1(GET_Rm());
3955 opd->dest = BITMASK1(SHR_R0);
3956 opd->imm = (op & 0x0f);
3958 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
3959 opd->source = BITMASK1(GET_Rm());
3960 opd->dest = BITMASK1(SHR_R0);
3961 opd->imm = (op & 0x0f) * 2;
3963 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
3964 opd->source = BITMASK1(SHR_R0);
3965 opd->dest = BITMASK1(SHR_T);
3966 opd->imm = (int)(signed char)op;
3968 case 0x0d00: // BT/S label 10001101dddddddd
3969 case 0x0f00: // BF/S label 10001111dddddddd
3972 case 0x0900: // BT label 10001001dddddddd
3973 case 0x0b00: // BF label 10001011dddddddd
3974 opd->op = (op & 0x0200) ? OP_BRANCH_CF : OP_BRANCH_CT;
3975 opd->source = BITMASK1(SHR_T);
3976 opd->dest = BITMASK1(SHR_PC);
3977 opd->imm = ((signed int)(op << 24) >> 23);
3979 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
3980 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
3987 /////////////////////////////////////////////
3989 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
3990 opd->op = OP_LOAD_POOL;
3992 if (op_flags[i] & OF_DELAY_OP) {
3993 if (ops[i-1].op == OP_BRANCH)
3998 opd->source = BITMASK1(SHR_PC);
3999 opd->dest = BITMASK1(GET_Rn());
4001 opd->imm = tmp + 2 + (op & 0xff) * 2;
4005 /////////////////////////////////////////////
4007 // BSR label 1011dddddddddddd
4008 opd->dest = BITMASK1(SHR_PR);
4010 // BRA label 1010dddddddddddd
4011 opd->op = OP_BRANCH;
4012 opd->dest |= BITMASK1(SHR_PC);
4013 opd->imm = ((signed int)(op << 20) >> 19);
4018 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
4019 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
4022 /////////////////////////////////////////////
4024 switch (op & 0x0f00)
4026 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
4027 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
4028 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
4029 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4030 opd->size = (op & 0x300) >> 8;
4031 opd->imm = (op & 0xff) << opd->size;
4033 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
4034 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
4035 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
4036 opd->source = BITMASK1(SHR_GBR);
4037 opd->dest = BITMASK1(SHR_R0);
4038 opd->size = (op & 0x300) >> 8;
4039 opd->imm = (op & 0xff) << opd->size;
4041 case 0x0300: // TRAPA #imm 11000011iiiiiiii
4042 opd->source = BITMASK2(SHR_PC, SHR_SR);
4043 opd->dest = BITMASK1(SHR_PC);
4044 opd->imm = (op & 0xff) * 4;
4046 end_block = 1; // FIXME
4048 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
4051 if (op_flags[i] & OF_DELAY_OP) {
4052 if (ops[i-1].op == OP_BRANCH)
4057 opd->dest = BITMASK1(SHR_R0);
4059 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
4060 if (opd->imm >= base_pc) {
4061 if (lowest_mova == 0 || opd->imm < lowest_mova)
4062 lowest_mova = opd->imm;
4066 case 0x0800: // TST #imm,R0 11001000iiiiiiii
4067 opd->source = BITMASK1(SHR_R0);
4068 opd->dest = BITMASK1(SHR_T);
4069 opd->imm = op & 0xff;
4071 case 0x0900: // AND #imm,R0 11001001iiiiiiii
4072 opd->source = opd->dest = BITMASK1(SHR_R0);
4073 opd->imm = op & 0xff;
4075 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
4076 opd->source = opd->dest = BITMASK1(SHR_R0);
4077 opd->imm = op & 0xff;
4079 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
4080 opd->source = opd->dest = BITMASK1(SHR_R0);
4081 opd->imm = op & 0xff;
4083 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
4084 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4085 opd->dest = BITMASK1(SHR_T);
4086 opd->imm = op & 0xff;
4089 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
4090 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
4091 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
4092 opd->source = BITMASK2(SHR_GBR, SHR_R0);
4093 opd->imm = op & 0xff;
4101 /////////////////////////////////////////////
4103 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
4104 opd->op = OP_LOAD_POOL;
4106 if (op_flags[i] & OF_DELAY_OP) {
4107 if (ops[i-1].op == OP_BRANCH)
4112 opd->source = BITMASK1(SHR_PC);
4113 opd->dest = BITMASK1(GET_Rn());
4115 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
4119 /////////////////////////////////////////////
4121 // MOV #imm,Rn 1110nnnniiiiiiii
4122 opd->dest = BITMASK1(GET_Rn());
4123 opd->imm = (u32)(signed int)(signed char)op;
4128 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
4129 is_slave ? 's' : 'm', op, pc);
4133 if (op_flags[i] & OF_DELAY_OP) {
4140 elprintf(EL_ANOMALY, "%csh2 drc: branch in DS @ %08x",
4141 is_slave ? 's' : 'm', pc);
4142 opd->op = OP_UNHANDLED;
4143 op_flags[i] |= OF_B_IN_DS;
4152 // 2nd pass: some analysis
4153 for (i = 0; i < i_end; i++) {
4156 // propagate T (TODO: DIV0U)
4157 if ((opd->op == OP_SETCLRT && !opd->imm) || opd->op == OP_BRANCH_CT)
4158 op_flags[i + 1] |= OF_T_CLEAR;
4159 else if ((opd->op == OP_SETCLRT && opd->imm) || opd->op == OP_BRANCH_CF)
4160 op_flags[i + 1] |= OF_T_SET;
4162 if ((op_flags[i] & OF_BTARGET) || (opd->dest & BITMASK1(SHR_T)))
4163 op_flags[i] &= ~(OF_T_SET | OF_T_CLEAR);
4165 op_flags[i + 1] |= op_flags[i] & (OF_T_SET | OF_T_CLEAR);
4167 if ((opd->op == OP_BRANCH_CT && (op_flags[i] & OF_T_SET))
4168 || (opd->op == OP_BRANCH_CF && (op_flags[i] & OF_T_CLEAR)))
4170 opd->op = OP_BRANCH;
4173 if (op_flags[i + 1] & OF_DELAY_OP) {
4178 else if (opd->op == OP_LOAD_POOL)
4180 if (opd->imm < end_pc + MAX_LITERAL_OFFSET) {
4181 if (end_literals < opd->imm + opd->size * 2)
4182 end_literals = opd->imm + opd->size * 2;
4186 end_pc = base_pc + i_end * 2;
4187 if (end_literals < end_pc)
4188 end_literals = end_pc;
4190 // end_literals is used to decide to inline a literal or not
4191 // XXX: need better detection if this actually is used in write
4192 if (lowest_mova >= base_pc) {
4193 if (lowest_mova < end_literals) {
4194 dbg(1, "mova for %08x, block %08x", lowest_mova, base_pc);
4195 end_literals = end_pc;
4197 if (lowest_mova < end_pc) {
4198 dbg(1, "warning: mova inside of blk for %08x, block %08x",
4199 lowest_mova, base_pc);
4200 end_literals = end_pc;
4204 *end_pc_out = end_pc;
4205 if (end_literals_out != NULL)
4206 *end_literals_out = end_literals;
4209 // vim:shiftwidth=2:ts=2:expandtab