3 * (C) notaz, 2009,2010,2013
5 * This work is licensed under the terms of MAME license.
6 * See COPYING file in the top-level directory.
9 * - tcache, block descriptor, link buffer overflows result in sh2_translate()
10 * failure, followed by full tcache invalidation for that region
11 * - jumps between blocks are tracked for SMC handling (in block_entry->links),
12 * except jumps between different tcaches
15 * - static register allocation
16 * - remaining register caching and tracking in temporaries
17 * - block-local branch linking
18 * - block linking (except between tcaches)
19 * - some constant propagation
22 * - better constant propagation
31 #include "../../pico/pico_int.h"
34 #include "../drc/cmn.h"
38 #define PROPAGATE_CONSTANTS 1
39 #define LINK_BRANCHES 1
42 #define MAX_BLOCK_SIZE (BLOCK_INSN_LIMIT * 6 * 6)
44 // max literal offset from the block end
45 #define MAX_LITERAL_OFFSET 32*2
46 #define MAX_LITERALS (BLOCK_INSN_LIMIT / 4)
47 #define MAX_LOCAL_BRANCHES 32
50 // 1 - warnings/errors
53 // 8 - runtime block entry log
60 #define dbg(l,...) { \
61 if ((l) & DRC_DEBUG) \
62 elprintf(EL_STATUS, ##__VA_ARGS__); \
64 #include "mame/sh2dasm.h"
65 #include <platform/libpicofe/linux/host_dasm.h>
66 static int insns_compiled, hash_collisions, host_insn_count;
75 #define FETCH_OP(pc) \
79 ((dr_pc_base[(a) / 2] << 16) | dr_pc_base[(a) / 2 + 1])
81 #define CHECK_UNHANDLED_BITS(mask, label) { \
82 if ((op & (mask)) != 0) \
94 #define BITMASK1(v0) (1 << (v0))
95 #define BITMASK2(v0,v1) ((1 << (v0)) | (1 << (v1)))
96 #define BITMASK3(v0,v1,v2) (BITMASK2(v0,v1) | (1 << (v2)))
97 #define BITMASK4(v0,v1,v2,v3) (BITMASK3(v0,v1,v2) | (1 << (v3)))
98 #define BITMASK5(v0,v1,v2,v3,v4) (BITMASK4(v0,v1,v2,v3) | (1 << (v4)))
100 #define SHR_T SHR_SR // might make them separate someday
102 static struct op_data {
105 u8 size; // 0, 1, 2 - byte, word, long
106 s8 rm; // branch or load/store data reg
107 u32 source; // bitmask of src regs
108 u32 dest; // bitmask of dest regs
109 u32 imm; // immediate/io address/branch target
110 // (for literal - address, not value)
111 } ops[BLOCK_INSN_LIMIT];
116 OP_BRANCH_CT, // conditional, branch if T set
117 OP_BRANCH_CF, // conditional, branch if T clear
118 OP_BRANCH_R, // indirect
119 OP_BRANCH_RF, // indirect far (PC + Rm)
120 OP_SETCLRT, // T flag set/clear
121 OP_MOVE, // register move
122 OP_LOAD_POOL, // literal pool load, imm is address
131 static u8 *tcache_dsm_ptrs[3];
132 static char sh2dasm_buff[64];
133 #define do_host_disasm(tcid) \
134 host_dasm(tcache_dsm_ptrs[tcid], tcache_ptr - tcache_dsm_ptrs[tcid]); \
135 tcache_dsm_ptrs[tcid] = tcache_ptr
137 #define do_host_disasm(x)
140 #if (DRC_DEBUG & 8) || defined(PDB)
141 static void REGPARM(3) *sh2_drc_log_entry(void *block, SH2 *sh2, u32 sr)
144 dbg(8, "= %csh2 enter %08x %p, c=%d", sh2->is_slave ? 's' : 'm',
145 sh2->pc, block, (signed int)sr >> 12);
146 pdb_step(sh2, sh2->pc);
153 #define TCACHE_BUFFERS 3
155 // we have 3 translation cache buffers, split from one drc/cmn buffer.
156 // BIOS shares tcache with data array because it's only used for init
157 // and can be discarded early
158 // XXX: need to tune sizes
159 static const int tcache_sizes[TCACHE_BUFFERS] = {
160 DRC_TCACHE_SIZE * 6 / 8, // ROM (rarely used), DRAM
161 DRC_TCACHE_SIZE / 8, // BIOS, data array in master sh2
162 DRC_TCACHE_SIZE / 8, // ... slave
165 static u8 *tcache_bases[TCACHE_BUFFERS];
166 static u8 *tcache_ptrs[TCACHE_BUFFERS];
168 // ptr for code emiters
169 static u8 *tcache_ptr;
171 #define MAX_BLOCK_ENTRIES (BLOCK_INSN_LIMIT / 8)
175 void *jump; // insn address
176 struct block_link *next; // either in block_entry->links or
181 void *tcache_ptr; // translated block for above PC
182 struct block_entry *next; // next block in hash_table with same pc hash
183 struct block_link *links; // links to this entry
185 struct block_desc *block;
190 u32 addr; // block start SH2 PC address
191 u32 end_addr; // address after last op or literal
196 struct block_entry entryp[MAX_BLOCK_ENTRIES];
199 static const int block_max_counts[TCACHE_BUFFERS] = {
204 static struct block_desc *block_tables[TCACHE_BUFFERS];
205 static int block_counts[TCACHE_BUFFERS];
207 // we have block_link_pool to avoid using mallocs
208 static const int block_link_pool_max_counts[TCACHE_BUFFERS] = {
213 static struct block_link *block_link_pool[TCACHE_BUFFERS];
214 static int block_link_pool_counts[TCACHE_BUFFERS];
215 static struct block_link *unresolved_links[TCACHE_BUFFERS];
217 // used for invalidation
218 static const int ram_sizes[TCACHE_BUFFERS] = {
223 #define ADDR_TO_BLOCK_PAGE 0x100
226 struct block_desc *block;
227 struct block_list *next;
230 // array of pointers to block_lists for RAM and 2 data arrays
231 // each array has len: sizeof(mem) / ADDR_TO_BLOCK_PAGE
232 static struct block_list **inval_lookup[TCACHE_BUFFERS];
234 static const int hash_table_sizes[TCACHE_BUFFERS] = {
239 static struct block_entry **hash_tables[TCACHE_BUFFERS];
241 #define HASH_FUNC(hash_tab, addr, mask) \
242 (hash_tab)[(((addr) >> 20) ^ ((addr) >> 2)) & (mask)]
244 // host register tracking
247 HR_CACHED, // 'val' has sh2_reg_e
248 // HR_CONST, // 'val' has a constant
249 HR_TEMP, // reg used for temp storage
253 HRF_DIRTY = 1 << 0, // reg has "dirty" value to be written to ctx
254 HRF_LOCKED = 1 << 1, // HR_CACHED can't be evicted
258 u32 hreg:5; // "host" reg
259 u32 greg:5; // "guest" reg
262 u32 stamp:16; // kind of a timestamp
265 // note: reg_temp[] must have at least the amount of
266 // registers used by handlers in worst case (currently 4)
268 #include "../drc/emit_arm.c"
270 static const int reg_map_g2h[] = {
274 -1, -1, -1, 9, // r12 .. sp
275 -1, -1, -1, 10, // SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
276 -1, -1, -1, -1, // SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
279 static temp_reg_t reg_temp[] = {
288 #elif defined(__i386__)
289 #include "../drc/emit_x86.c"
291 static const int reg_map_g2h[] = {
300 // ax, cx, dx are usually temporaries by convention
301 static temp_reg_t reg_temp[] = {
309 #error unsupported arch
317 #define T_save 0x00000800
323 static void REGPARM(1) (*sh2_drc_entry)(SH2 *sh2);
324 static void (*sh2_drc_dispatcher)(void);
325 static void (*sh2_drc_exit)(void);
326 static void (*sh2_drc_test_irq)(void);
328 static u32 REGPARM(2) (*sh2_drc_read8)(u32 a, SH2 *sh2);
329 static u32 REGPARM(2) (*sh2_drc_read16)(u32 a, SH2 *sh2);
330 static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
331 static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
332 static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
333 static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
335 // address space stuff
336 static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
340 if ((a & ~0x7ff) == 0) {
342 poffs = offsetof(SH2, p_bios);
345 else if ((a & 0xfffff000) == 0xc0000000) {
347 poffs = offsetof(SH2, p_da);
350 else if ((a & 0xc6000000) == 0x06000000) {
352 poffs = offsetof(SH2, p_sdram);
355 else if ((a & 0xc6000000) == 0x02000000) {
357 poffs = offsetof(SH2, p_rom);
364 static struct block_entry *dr_get_entry(u32 pc, int is_slave, int *tcache_id)
366 struct block_entry *be;
369 // data arrays have their own caches
370 if ((pc & 0xe0000000) == 0xc0000000 || (pc & ~0xfff) == 0)
375 mask = hash_table_sizes[tcid] - 1;
376 be = HASH_FUNC(hash_tables[tcid], pc, mask);
377 for (; be != NULL; be = be->next)
384 // ---------------------------------------------------------------
387 static void add_to_block_list(struct block_list **blist, struct block_desc *block)
389 struct block_list *added = malloc(sizeof(*added));
391 elprintf(EL_ANOMALY, "drc OOM (1)");
394 added->block = block;
395 added->next = *blist;
399 static void rm_from_block_list(struct block_list **blist, struct block_desc *block)
401 struct block_list *prev = NULL, *current = *blist;
402 for (; current != NULL; prev = current, current = current->next) {
403 if (current->block == block) {
405 *blist = current->next;
407 prev->next = current->next;
412 dbg(1, "can't rm block %p (%08x-%08x)",
413 block, block->addr, block->end_addr);
416 static void rm_block_list(struct block_list **blist)
418 struct block_list *tmp, *current = *blist;
419 while (current != NULL) {
421 current = current->next;
427 static void REGPARM(1) flush_tcache(int tcid)
431 dbg(1, "tcache #%d flush! (%d/%d, bds %d/%d)", tcid,
432 tcache_ptrs[tcid] - tcache_bases[tcid], tcache_sizes[tcid],
433 block_counts[tcid], block_max_counts[tcid]);
435 block_counts[tcid] = 0;
436 block_link_pool_counts[tcid] = 0;
437 unresolved_links[tcid] = NULL;
438 memset(hash_tables[tcid], 0, sizeof(*hash_tables[0]) * hash_table_sizes[tcid]);
439 tcache_ptrs[tcid] = tcache_bases[tcid];
440 if (Pico32xMem != NULL) {
441 if (tcid == 0) // ROM, RAM
442 memset(Pico32xMem->drcblk_ram, 0,
443 sizeof(Pico32xMem->drcblk_ram));
445 memset(Pico32xMem->drcblk_da[tcid - 1], 0,
446 sizeof(Pico32xMem->drcblk_da[0]));
449 tcache_dsm_ptrs[tcid] = tcache_bases[tcid];
452 for (i = 0; i < ram_sizes[tcid] / ADDR_TO_BLOCK_PAGE; i++)
453 rm_block_list(&inval_lookup[tcid][i]);
456 static void add_to_hashlist(struct block_entry *be, int tcache_id)
458 u32 tcmask = hash_table_sizes[tcache_id] - 1;
460 be->next = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
461 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be;
464 if (be->next != NULL) {
465 printf(" %08x: hash collision with %08x\n",
466 be->pc, be->next->pc);
472 static void rm_from_hashlist(struct block_entry *be, int tcache_id)
474 u32 tcmask = hash_table_sizes[tcache_id] - 1;
475 struct block_entry *cur, *prev;
477 cur = HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask);
481 if (be == cur) { // first
482 HASH_FUNC(hash_tables[tcache_id], be->pc, tcmask) = be->next;
486 for (prev = cur, cur = cur->next; cur != NULL; cur = cur->next) {
488 prev->next = cur->next;
494 dbg(1, "rm_from_hashlist: be %p %08x missing?", be, be->pc);
497 static struct block_desc *dr_add_block(u32 addr, u32 end_addr, int is_slave, int *blk_id)
499 struct block_entry *be;
500 struct block_desc *bd;
504 // do a lookup to get tcache_id and override check
505 be = dr_get_entry(addr, is_slave, &tcache_id);
507 dbg(1, "block override for %08x", addr);
509 bcount = &block_counts[tcache_id];
510 if (*bcount >= block_max_counts[tcache_id]) {
511 dbg(1, "bd overflow for tcache %d", tcache_id);
515 bd = &block_tables[tcache_id][*bcount];
517 bd->end_addr = end_addr;
520 bd->entryp[0].pc = addr;
521 bd->entryp[0].tcache_ptr = tcache_ptr;
522 bd->entryp[0].links = NULL;
524 bd->entryp[0].block = bd;
527 add_to_hashlist(&bd->entryp[0], tcache_id);
535 static void REGPARM(3) *dr_lookup_block(u32 pc, int is_slave, int *tcache_id)
537 struct block_entry *be = NULL;
540 be = dr_get_entry(pc, is_slave, tcache_id);
542 block = be->tcache_ptr;
546 be->block->refcount++;
551 static void *dr_failure(void)
553 lprintf("recompilation failed\n");
557 static void *dr_prepare_ext_branch(u32 pc, int is_slave, int tcache_id)
560 struct block_link *bl = block_link_pool[tcache_id];
561 int cnt = block_link_pool_counts[tcache_id];
562 struct block_entry *be = NULL;
563 int target_tcache_id;
566 be = dr_get_entry(pc, is_slave, &target_tcache_id);
567 if (target_tcache_id != tcache_id)
568 return sh2_drc_dispatcher;
570 // if pool has been freed, reuse
571 for (i = cnt - 1; i >= 0; i--)
572 if (bl[i].target_pc != 0)
575 if (cnt >= block_link_pool_max_counts[tcache_id]) {
576 dbg(1, "bl overflow for tcache %d", tcache_id);
580 block_link_pool_counts[tcache_id]++;
583 bl->jump = tcache_ptr;
586 dbg(2, "- early link from %p to pc %08x", bl->jump, pc);
587 bl->next = be->links;
589 return be->tcache_ptr;
592 bl->next = unresolved_links[tcache_id];
593 unresolved_links[tcache_id] = bl;
594 return sh2_drc_dispatcher;
597 return sh2_drc_dispatcher;
601 static void dr_link_blocks(struct block_entry *be, int tcache_id)
604 struct block_link *first = unresolved_links[tcache_id];
605 struct block_link *bl, *prev, *tmp;
608 for (bl = prev = first; bl != NULL; ) {
609 if (bl->target_pc == pc) {
610 dbg(2, "- link from %p to pc %08x", bl->jump, pc);
611 emith_jump_patch(bl->jump, tcache_ptr);
613 // move bl from unresolved_links to block_entry
615 bl->next = be->links;
619 first = prev = bl = tmp;
621 prev->next = bl = tmp;
627 unresolved_links[tcache_id] = first;
629 // could sync arm caches here, but that's unnecessary
633 #define ADD_TO_ARRAY(array, count, item, failcode) \
634 if (count >= ARRAY_SIZE(array)) { \
635 dbg(1, "warning: " #array " overflow"); \
638 array[count++] = item;
640 static int find_in_array(u32 *array, size_t size, u32 what)
643 for (i = 0; i < size; i++)
644 if (what == array[i])
650 // ---------------------------------------------------------------
652 // register cache / constant propagation stuff
659 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking);
661 // guest regs with constants
662 static u32 dr_gcregs[24];
663 // a mask of constant/dirty regs
664 static u32 dr_gcregs_mask;
665 static u32 dr_gcregs_dirty;
667 #if PROPAGATE_CONSTANTS
668 static void gconst_new(sh2_reg_e r, u32 val)
672 dr_gcregs_mask |= 1 << r;
673 dr_gcregs_dirty |= 1 << r;
676 // throw away old r that we might have cached
677 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
678 if ((reg_temp[i].type == HR_CACHED) &&
679 reg_temp[i].greg == r) {
680 reg_temp[i].type = HR_FREE;
681 reg_temp[i].flags = 0;
687 static int gconst_get(sh2_reg_e r, u32 *val)
689 if (dr_gcregs_mask & (1 << r)) {
696 static int gconst_check(sh2_reg_e r)
698 if ((dr_gcregs_mask | dr_gcregs_dirty) & (1 << r))
703 // update hr if dirty, else do nothing
704 static int gconst_try_read(int hr, sh2_reg_e r)
706 if (dr_gcregs_dirty & (1 << r)) {
707 emith_move_r_imm(hr, dr_gcregs[r]);
708 dr_gcregs_dirty &= ~(1 << r);
714 static void gconst_check_evict(sh2_reg_e r)
716 if (dr_gcregs_mask & (1 << r))
717 // no longer cached in reg, make dirty again
718 dr_gcregs_dirty |= 1 << r;
721 static void gconst_kill(sh2_reg_e r)
723 dr_gcregs_mask &= ~(1 << r);
724 dr_gcregs_dirty &= ~(1 << r);
727 static void gconst_clean(void)
731 for (i = 0; i < ARRAY_SIZE(dr_gcregs); i++)
732 if (dr_gcregs_dirty & (1 << i)) {
733 // using RC_GR_READ here: it will call gconst_try_read,
734 // cache the reg and mark it dirty.
735 rcache_get_reg_(i, RC_GR_READ, 0);
739 static void gconst_invalidate(void)
741 dr_gcregs_mask = dr_gcregs_dirty = 0;
744 static u16 rcache_counter;
746 static temp_reg_t *rcache_evict(void)
748 // evict reg with oldest stamp
750 u16 min_stamp = (u16)-1;
752 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
753 if (reg_temp[i].type == HR_CACHED && !(reg_temp[i].flags & HRF_LOCKED) &&
754 reg_temp[i].stamp <= min_stamp) {
755 min_stamp = reg_temp[i].stamp;
761 printf("no registers to evict, aborting\n");
766 if (reg_temp[i].type == HR_CACHED) {
767 if (reg_temp[i].flags & HRF_DIRTY)
769 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
770 gconst_check_evict(reg_temp[i].greg);
773 reg_temp[i].type = HR_FREE;
774 reg_temp[i].flags = 0;
778 static int get_reg_static(sh2_reg_e r, rc_gr_mode mode)
780 int i = reg_map_g2h[r];
782 if (mode != RC_GR_WRITE)
783 gconst_try_read(i, r);
788 // note: must not be called when doing conditional code
789 static int rcache_get_reg_(sh2_reg_e r, rc_gr_mode mode, int do_locking)
794 // maybe statically mapped?
795 ret = get_reg_static(r, mode);
801 // maybe already cached?
802 // if so, prefer against gconst (they must be in sync)
803 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
804 if (reg_temp[i].type == HR_CACHED && reg_temp[i].greg == r) {
805 reg_temp[i].stamp = rcache_counter;
806 if (mode != RC_GR_READ)
807 reg_temp[i].flags |= HRF_DIRTY;
808 ret = reg_temp[i].hreg;
814 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
815 if (reg_temp[i].type == HR_FREE) {
824 tr->type = HR_CACHED;
826 tr->flags |= HRF_LOCKED;
827 if (mode != RC_GR_READ)
828 tr->flags |= HRF_DIRTY;
830 tr->stamp = rcache_counter;
833 if (mode != RC_GR_WRITE) {
834 if (gconst_check(r)) {
835 if (gconst_try_read(ret, r))
836 tr->flags |= HRF_DIRTY;
839 emith_ctx_read(tr->hreg, r * 4);
843 if (mode != RC_GR_READ)
849 static int rcache_get_reg(sh2_reg_e r, rc_gr_mode mode)
851 return rcache_get_reg_(r, mode, 1);
854 static int rcache_get_tmp(void)
859 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
860 if (reg_temp[i].type == HR_FREE) {
872 static int rcache_get_arg_id(int arg)
875 host_arg2reg(r, arg);
877 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
878 if (reg_temp[i].hreg == r)
881 if (i == ARRAY_SIZE(reg_temp)) // can't happen
884 if (reg_temp[i].type == HR_CACHED) {
886 if (reg_temp[i].flags & HRF_DIRTY)
887 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
888 gconst_check_evict(reg_temp[i].greg);
890 else if (reg_temp[i].type == HR_TEMP) {
891 printf("arg %d reg %d already used, aborting\n", arg, r);
895 reg_temp[i].type = HR_FREE;
896 reg_temp[i].flags = 0;
901 // get a reg to be used as function arg
902 static int rcache_get_tmp_arg(int arg)
904 int id = rcache_get_arg_id(arg);
905 reg_temp[id].type = HR_TEMP;
907 return reg_temp[id].hreg;
910 // same but caches a reg. RC_GR_READ only.
911 static int rcache_get_reg_arg(int arg, sh2_reg_e r)
913 int i, srcr, dstr, dstid;
914 int dirty = 0, src_dirty = 0;
916 dstid = rcache_get_arg_id(arg);
917 dstr = reg_temp[dstid].hreg;
919 // maybe already statically mapped?
920 srcr = get_reg_static(r, RC_GR_READ);
924 // maybe already cached?
925 for (i = ARRAY_SIZE(reg_temp) - 1; i >= 0; i--) {
926 if ((reg_temp[i].type == HR_CACHED) &&
927 reg_temp[i].greg == r)
929 srcr = reg_temp[i].hreg;
930 if (reg_temp[i].flags & HRF_DIRTY)
938 if (gconst_check(r)) {
939 if (gconst_try_read(srcr, r))
943 emith_ctx_read(srcr, r * 4);
947 emith_move_r_r(dstr, srcr);
953 // must clean, callers might want to modify the arg before call
954 emith_ctx_write(dstr, r * 4);
957 reg_temp[dstid].flags |= HRF_DIRTY;
960 reg_temp[dstid].stamp = ++rcache_counter;
961 reg_temp[dstid].type = HR_CACHED;
962 reg_temp[dstid].greg = r;
963 reg_temp[dstid].flags |= HRF_LOCKED;
967 static void rcache_free_tmp(int hr)
970 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
971 if (reg_temp[i].hreg == hr)
974 if (i == ARRAY_SIZE(reg_temp) || reg_temp[i].type != HR_TEMP) {
975 printf("rcache_free_tmp fail: #%i hr %d, type %d\n", i, hr, reg_temp[i].type);
979 reg_temp[i].type = HR_FREE;
980 reg_temp[i].flags = 0;
983 static void rcache_unlock(int hr)
986 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
987 if (reg_temp[i].type == HR_CACHED && reg_temp[i].hreg == hr)
988 reg_temp[i].flags &= ~HRF_LOCKED;
991 static void rcache_unlock_all(void)
994 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
995 reg_temp[i].flags &= ~HRF_LOCKED;
998 static inline u32 rcache_used_hreg_mask(void)
1003 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1004 if (reg_temp[i].type != HR_FREE)
1005 mask |= 1 << reg_temp[i].hreg;
1010 static void rcache_clean(void)
1015 for (i = 0; i < ARRAY_SIZE(reg_temp); i++)
1016 if (reg_temp[i].type == HR_CACHED && (reg_temp[i].flags & HRF_DIRTY)) {
1018 emith_ctx_write(reg_temp[i].hreg, reg_temp[i].greg * 4);
1019 reg_temp[i].flags &= ~HRF_DIRTY;
1023 static void rcache_invalidate(void)
1026 for (i = 0; i < ARRAY_SIZE(reg_temp); i++) {
1027 reg_temp[i].type = HR_FREE;
1028 reg_temp[i].flags = 0;
1032 gconst_invalidate();
1035 static void rcache_flush(void)
1038 rcache_invalidate();
1041 // ---------------------------------------------------------------
1043 static int emit_get_rbase_and_offs(u32 a, u32 *offs)
1049 poffs = dr_ctx_get_mem_ptr(a, &mask);
1053 // XXX: could use some related reg
1054 hr = rcache_get_tmp();
1055 emith_ctx_read(hr, poffs);
1056 emith_add_r_imm(hr, a & mask & ~0xff);
1057 *offs = a & 0xff; // XXX: ARM oriented..
1061 static void emit_move_r_imm32(sh2_reg_e dst, u32 imm)
1063 #if PROPAGATE_CONSTANTS
1064 gconst_new(dst, imm);
1066 int hr = rcache_get_reg(dst, RC_GR_WRITE);
1067 emith_move_r_imm(hr, imm);
1071 static void emit_move_r_r(sh2_reg_e dst, sh2_reg_e src)
1073 int hr_d = rcache_get_reg(dst, RC_GR_WRITE);
1074 int hr_s = rcache_get_reg(src, RC_GR_READ);
1076 emith_move_r_r(hr_d, hr_s);
1079 // T must be clear, and comparison done just before this
1080 static void emit_or_t_if_eq(int srr)
1082 EMITH_SJMP_START(DCOND_NE);
1083 emith_or_r_imm_c(DCOND_EQ, srr, T);
1084 EMITH_SJMP_END(DCOND_NE);
1087 // arguments must be ready
1088 // reg cache must be clean before call
1089 static int emit_memhandler_read_(int size, int ram_check)
1092 host_arg2reg(arg0, 0);
1096 // must writeback cycles for poll detection stuff
1098 if (reg_map_g2h[SHR_SR] != -1)
1099 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1101 arg1 = rcache_get_tmp_arg(1);
1102 emith_move_r_r(arg1, CONTEXT_REG);
1104 #if 0 // can't do this because of unmapped reads
1106 if (ram_check && Pico.rom == (void *)0x02000000 && Pico32xMem->sdram == (void *)0x06000000) {
1107 int tmp = rcache_get_tmp();
1108 emith_and_r_r_imm(tmp, arg0, 0xfb000000);
1109 emith_cmp_r_imm(tmp, 0x02000000);
1112 EMITH_SJMP3_START(DCOND_NE);
1113 emith_eor_r_imm_c(DCOND_EQ, arg0, 1);
1114 emith_read8_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1115 EMITH_SJMP3_MID(DCOND_NE);
1116 emith_call_cond(DCOND_NE, sh2_drc_read8);
1120 EMITH_SJMP3_START(DCOND_NE);
1121 emith_read16_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1122 EMITH_SJMP3_MID(DCOND_NE);
1123 emith_call_cond(DCOND_NE, sh2_drc_read16);
1127 EMITH_SJMP3_START(DCOND_NE);
1128 emith_read_r_r_offs_c(DCOND_EQ, arg0, arg0, 0);
1129 emith_ror_c(DCOND_EQ, arg0, arg0, 16);
1130 EMITH_SJMP3_MID(DCOND_NE);
1131 emith_call_cond(DCOND_NE, sh2_drc_read32);
1141 emith_call(sh2_drc_read8);
1144 emith_call(sh2_drc_read16);
1147 emith_call(sh2_drc_read32);
1151 rcache_invalidate();
1153 if (reg_map_g2h[SHR_SR] != -1)
1154 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1156 // assuming arg0 and retval reg matches
1157 return rcache_get_tmp_arg(0);
1160 static int emit_memhandler_read(int size)
1162 return emit_memhandler_read_(size, 1);
1165 static int emit_memhandler_read_rr(sh2_reg_e rd, sh2_reg_e rs, u32 offs, int size)
1167 int hr, hr2, ram_check = 1;
1170 if (gconst_get(rs, &val)) {
1171 hr = emit_get_rbase_and_offs(val + offs, &offs2);
1173 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1176 emith_read8_r_r_offs(hr2, hr, offs2 ^ 1);
1177 emith_sext(hr2, hr2, 8);
1180 emith_read16_r_r_offs(hr2, hr, offs2);
1181 emith_sext(hr2, hr2, 16);
1184 emith_read_r_r_offs(hr2, hr, offs2);
1185 emith_ror(hr2, hr2, 16);
1188 rcache_free_tmp(hr);
1195 hr = rcache_get_reg_arg(0, rs);
1197 emith_add_r_imm(hr, offs);
1198 hr = emit_memhandler_read_(size, ram_check);
1199 hr2 = rcache_get_reg(rd, RC_GR_WRITE);
1201 emith_sext(hr2, hr, (size == 1) ? 16 : 8);
1203 emith_move_r_r(hr2, hr);
1204 rcache_free_tmp(hr);
1209 static void emit_memhandler_write(int size, u32 pc)
1212 host_arg2reg(ctxr, 2);
1213 if (reg_map_g2h[SHR_SR] != -1)
1214 emith_ctx_write(reg_map_g2h[SHR_SR], SHR_SR * 4);
1220 // XXX: consider inlining sh2_drc_write8
1221 emith_call(sh2_drc_write8);
1224 emith_call(sh2_drc_write16);
1227 emith_move_r_r(ctxr, CONTEXT_REG);
1228 emith_call(sh2_drc_write32);
1232 rcache_invalidate();
1233 if (reg_map_g2h[SHR_SR] != -1)
1234 emith_ctx_read(reg_map_g2h[SHR_SR], SHR_SR * 4);
1238 static int emit_indirect_indexed_read(int rx, int ry, int size)
1241 a0 = rcache_get_reg_arg(0, rx);
1242 t = rcache_get_reg(ry, RC_GR_READ);
1243 emith_add_r_r(a0, t);
1244 return emit_memhandler_read(size);
1248 static void emit_indirect_read_double(u32 *rnr, u32 *rmr, int rn, int rm, int size)
1252 rcache_get_reg_arg(0, rn);
1253 tmp = emit_memhandler_read(size);
1254 emith_ctx_write(tmp, offsetof(SH2, drc_tmp));
1255 rcache_free_tmp(tmp);
1256 tmp = rcache_get_reg(rn, RC_GR_RMW);
1257 emith_add_r_imm(tmp, 1 << size);
1260 rcache_get_reg_arg(0, rm);
1261 *rmr = emit_memhandler_read(size);
1262 *rnr = rcache_get_tmp();
1263 emith_ctx_read(*rnr, offsetof(SH2, drc_tmp));
1264 tmp = rcache_get_reg(rm, RC_GR_RMW);
1265 emith_add_r_imm(tmp, 1 << size);
1269 static void emit_do_static_regs(int is_write, int tmpr)
1273 for (i = 0; i < ARRAY_SIZE(reg_map_g2h); i++) {
1278 for (count = 1; i < ARRAY_SIZE(reg_map_g2h) - 1; i++, r++) {
1279 if (reg_map_g2h[i + 1] != r + 1)
1285 // i, r point to last item
1287 emith_ctx_write_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1289 emith_ctx_read_multiple(r - count + 1, (i - count + 1) * 4, count, tmpr);
1292 emith_ctx_write(r, i * 4);
1294 emith_ctx_read(r, i * 4);
1299 static void emit_block_entry(void)
1303 host_arg2reg(arg0, 0);
1305 #if (DRC_DEBUG & 8) || defined(PDB)
1307 host_arg2reg(arg1, 1);
1308 host_arg2reg(arg2, 2);
1310 emit_do_static_regs(1, arg2);
1311 emith_move_r_r(arg1, CONTEXT_REG);
1312 emith_move_r_r(arg2, rcache_get_reg(SHR_SR, RC_GR_READ));
1313 emith_call(sh2_drc_log_entry);
1314 rcache_invalidate();
1316 emith_tst_r_r(arg0, arg0);
1317 EMITH_SJMP_START(DCOND_EQ);
1318 emith_jump_reg_c(DCOND_NE, arg0);
1319 EMITH_SJMP_END(DCOND_EQ);
1322 #define DELAY_SAVE_T(sr) { \
1323 emith_bic_r_imm(sr, T_save); \
1324 emith_tst_r_imm(sr, T); \
1325 EMITH_SJMP_START(DCOND_EQ); \
1326 emith_or_r_imm_c(DCOND_NE, sr, T_save); \
1327 EMITH_SJMP_END(DCOND_EQ); \
1330 #define FLUSH_CYCLES(sr) \
1332 emith_sub_r_imm(sr, cycles << 12); \
1336 static void *dr_get_pc_base(u32 pc, int is_slave);
1338 static void REGPARM(2) *sh2_translate(SH2 *sh2, int tcache_id)
1340 u32 branch_target_pc[MAX_LOCAL_BRANCHES];
1341 void *branch_target_ptr[MAX_LOCAL_BRANCHES];
1342 int branch_target_count = 0;
1343 void *branch_patch_ptr[MAX_LOCAL_BRANCHES];
1344 u32 branch_patch_pc[MAX_LOCAL_BRANCHES];
1345 int branch_patch_count = 0;
1346 u32 literal_addr[MAX_LITERALS];
1347 int literal_addr_count = 0;
1348 u8 op_flags[BLOCK_INSN_LIMIT];
1351 u32 pending_branch_direct:1;
1352 u32 pending_branch_indirect:1;
1355 // PC of current, first, last SH2 insn
1356 u32 pc, base_pc, end_pc;
1358 void *block_entry_ptr;
1359 struct block_desc *block;
1361 struct op_data *opd;
1371 // get base/validate PC
1372 dr_pc_base = dr_get_pc_base(base_pc, sh2->is_slave);
1373 if (dr_pc_base == (void *)-1) {
1374 printf("invalid PC, aborting: %08x\n", base_pc);
1375 // FIXME: be less destructive
1379 tcache_ptr = tcache_ptrs[tcache_id];
1381 // predict tcache overflow
1382 tmp = tcache_ptr - tcache_bases[tcache_id];
1383 if (tmp > tcache_sizes[tcache_id] - MAX_BLOCK_SIZE) {
1384 dbg(1, "tcache %d overflow", tcache_id);
1388 // initial passes to disassemble and analyze the block
1389 scan_block(base_pc, sh2->is_slave, op_flags, &end_pc, &end_literals);
1391 block = dr_add_block(base_pc, end_literals, sh2->is_slave, &blkid_main);
1395 block_entry_ptr = tcache_ptr;
1396 dbg(2, "== %csh2 block #%d,%d %08x-%08x -> %p", sh2->is_slave ? 's' : 'm',
1397 tcache_id, blkid_main, base_pc, end_pc, block_entry_ptr);
1399 dr_link_blocks(&block->entryp[0], tcache_id);
1401 // collect branch_targets that don't land on delay slots
1402 for (pc = base_pc, i = 0; pc < end_pc; i++, pc += 2) {
1403 if (!(op_flags[i] & OF_BTARGET))
1405 if (op_flags[i] & OF_DELAY_OP) {
1406 op_flags[i] &= ~OF_BTARGET;
1409 ADD_TO_ARRAY(branch_target_pc, branch_target_count, pc, break);
1412 if (branch_target_count > 0) {
1413 memset(branch_target_ptr, 0, sizeof(branch_target_ptr[0]) * branch_target_count);
1416 // clear stale state after compile errors
1417 rcache_invalidate();
1419 // -------------------------------------------------
1420 // 3rd pass: actual compilation
1423 for (i = 0; pc < end_pc; i++)
1425 u32 delay_dep_fw = 0, delay_dep_bk = 0;
1435 DasmSH2(sh2dasm_buff, pc, op);
1436 printf("%c%08x %04x %s\n", (op_flags[i] & OF_BTARGET) ? '*' : ' ',
1437 pc, op, sh2dasm_buff);
1440 if ((op_flags[i] & OF_BTARGET) || pc == base_pc)
1444 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1449 v = block->entry_count;
1450 if (v < ARRAY_SIZE(block->entryp)) {
1451 block->entryp[v].pc = pc;
1452 block->entryp[v].tcache_ptr = tcache_ptr;
1453 block->entryp[v].links = NULL;
1455 block->entryp[v].block = block;
1457 add_to_hashlist(&block->entryp[v], tcache_id);
1458 block->entry_count++;
1460 dbg(2, "-- %csh2 block #%d,%d entry %08x -> %p",
1461 sh2->is_slave ? 's' : 'm', tcache_id, blkid_main,
1464 // since we made a block entry, link any other blocks
1465 // that jump to current pc
1466 dr_link_blocks(&block->entryp[v], tcache_id);
1469 dbg(1, "too many entryp for block #%d,%d pc=%08x",
1470 tcache_id, blkid_main, pc);
1473 do_host_disasm(tcache_id);
1476 v = find_in_array(branch_target_pc, branch_target_count, pc);
1478 branch_target_ptr[v] = tcache_ptr;
1481 emit_move_r_imm32(SHR_PC, pc);
1485 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1486 emith_cmp_r_imm(sr, 0);
1487 emith_jump_cond(DCOND_LE, sh2_drc_exit);
1488 do_host_disasm(tcache_id);
1489 rcache_unlock_all();
1493 if (!(op_flags[i] & OF_DELAY_OP)) {
1494 emit_move_r_imm32(SHR_PC, pc);
1495 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1499 tmp = rcache_used_hreg_mask();
1500 emith_save_caller_regs(tmp);
1501 emit_do_static_regs(1, 0);
1502 emith_pass_arg_r(0, CONTEXT_REG);
1503 emith_call(do_sh2_cmp);
1504 emith_restore_caller_regs(tmp);
1515 if (op_flags[i] & OF_DELAY_OP)
1517 // handle delay slot dependencies
1518 delay_dep_fw = opd->dest & ops[i-1].source;
1519 delay_dep_bk = opd->source & ops[i-1].dest;
1520 if (delay_dep_fw & BITMASK1(SHR_T)) {
1521 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1524 if (delay_dep_bk & BITMASK1(SHR_PC)) {
1525 if (opd->op != OP_LOAD_POOL && opd->op != OP_MOVA) {
1526 // can only be those 2 really..
1527 elprintf(EL_ANOMALY, "%csh2 drc: illegal slot insn %04x @ %08x?",
1528 sh2->is_slave ? 's' : 'm', op, pc - 2);
1531 ; // addr already resolved somehow
1533 switch (ops[i-1].op) {
1535 emit_move_r_imm32(SHR_PC, ops[i-1].imm);
1539 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1540 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1541 emith_move_r_imm(tmp, pc);
1542 emith_tst_r_imm(sr, T);
1543 tmp2 = ops[i-1].op == OP_BRANCH_CT ? DCOND_NE : DCOND_EQ;
1544 emith_move_r_imm_c(tmp2, tmp, ops[i-1].imm);
1546 // case OP_BRANCH_R OP_BRANCH_RF - PC already loaded
1550 //if (delay_dep_fw & ~BITMASK1(SHR_T))
1551 // dbg(1, "unhandled delay_dep_fw: %x", delay_dep_fw & ~BITMASK1(SHR_T));
1552 if (delay_dep_bk & ~BITMASK2(SHR_PC, SHR_PR))
1553 dbg(1, "unhandled delay_dep_bk: %x", delay_dep_bk);
1561 if (opd->dest & BITMASK1(SHR_PR))
1562 emit_move_r_imm32(SHR_PR, pc + 2);
1563 drcf.pending_branch_direct = 1;
1567 if (opd->dest & BITMASK1(SHR_PR))
1568 emit_move_r_imm32(SHR_PR, pc + 2);
1569 emit_move_r_r(SHR_PC, opd->rm);
1570 drcf.pending_branch_indirect = 1;
1574 tmp = rcache_get_reg(SHR_PC, RC_GR_WRITE);
1575 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1576 if (opd->dest & BITMASK1(SHR_PR)) {
1577 tmp3 = rcache_get_reg(SHR_PR, RC_GR_WRITE);
1578 emith_move_r_imm(tmp3, pc + 2);
1579 emith_add_r_r_r(tmp, tmp2, tmp3);
1582 emith_move_r_r(tmp, tmp2);
1583 emith_add_r_imm(tmp, pc + 2);
1585 drcf.pending_branch_indirect = 1;
1589 printf("TODO sleep\n");
1594 emit_memhandler_read_rr(SHR_PC, SHR_SP, 0, 2);
1596 tmp = rcache_get_reg_arg(0, SHR_SP);
1597 emith_add_r_imm(tmp, 4);
1598 tmp = emit_memhandler_read(2);
1599 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1600 emith_write_sr(sr, tmp);
1601 rcache_free_tmp(tmp);
1602 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
1603 emith_add_r_imm(tmp, 4*2);
1605 drcf.pending_branch_indirect = 1;
1609 #if PROPAGATE_CONSTANTS
1610 if (opd->imm != 0 && opd->imm < end_pc + MAX_LITERAL_OFFSET
1611 && literal_addr_count < MAX_LITERALS)
1613 ADD_TO_ARRAY(literal_addr, literal_addr_count, opd->imm,);
1615 tmp = FETCH32(opd->imm);
1617 tmp = (u32)(int)(signed short)FETCH_OP(opd->imm);
1618 gconst_new(GET_Rn(), tmp);
1623 tmp = rcache_get_tmp_arg(0);
1625 emith_move_r_imm(tmp, opd->imm);
1627 // have to calculate read addr from PC
1628 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1629 if (opd->size == 2) {
1630 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1631 emith_bic_r_imm(tmp, 3);
1634 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 2);
1636 tmp2 = emit_memhandler_read(opd->size);
1637 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1639 emith_move_r_r(tmp3, tmp2);
1641 emith_sext(tmp3, tmp2, 16);
1642 rcache_free_tmp(tmp2);
1648 emit_move_r_imm32(SHR_R0, opd->imm);
1650 tmp = rcache_get_reg(SHR_R0, RC_GR_WRITE);
1651 tmp2 = rcache_get_reg(SHR_PC, RC_GR_READ);
1652 emith_add_r_r_imm(tmp, tmp2, 2 + (op & 0xff) * 4);
1653 emith_bic_r_imm(tmp, 3);
1658 switch ((op >> 12) & 0x0f)
1660 /////////////////////////////////////////////
1665 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1668 case 0: // STC SR,Rn 0000nnnn00000010
1671 case 1: // STC GBR,Rn 0000nnnn00010010
1674 case 2: // STC VBR,Rn 0000nnnn00100010
1680 tmp3 = rcache_get_reg(tmp2, RC_GR_READ);
1681 emith_move_r_r(tmp, tmp3);
1683 emith_clear_msb(tmp, tmp, 22); // reserved bits defined by ISA as 0
1685 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
1686 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
1687 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
1689 tmp = rcache_get_reg_arg(1, GET_Rm());
1690 tmp2 = rcache_get_reg_arg(0, SHR_R0);
1691 tmp3 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1692 emith_add_r_r(tmp2, tmp3);
1693 emit_memhandler_write(op & 3, pc);
1696 // MUL.L Rm,Rn 0000nnnnmmmm0111
1697 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1698 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1699 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1700 emith_mul(tmp3, tmp2, tmp);
1705 case 0: // CLRT 0000000000001000
1706 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1707 emith_bic_r_imm(sr, T);
1709 case 1: // SETT 0000000000011000
1710 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1711 emith_or_r_imm(sr, T);
1713 case 2: // CLRMAC 0000000000101000
1714 emit_move_r_imm32(SHR_MACL, 0);
1715 emit_move_r_imm32(SHR_MACH, 0);
1724 case 0: // NOP 0000000000001001
1726 case 1: // DIV0U 0000000000011001
1727 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1728 emith_bic_r_imm(sr, M|Q|T);
1730 case 2: // MOVT Rn 0000nnnn00101001
1731 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1732 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1733 emith_clear_msb(tmp2, sr, 31);
1740 tmp = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1743 case 0: // STS MACH,Rn 0000nnnn00001010
1746 case 1: // STS MACL,Rn 0000nnnn00011010
1749 case 2: // STS PR,Rn 0000nnnn00101010
1755 tmp2 = rcache_get_reg(tmp2, RC_GR_READ);
1756 emith_move_r_r(tmp, tmp2);
1758 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
1759 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
1760 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
1761 tmp = emit_indirect_indexed_read(SHR_R0, GET_Rm(), op & 3);
1762 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
1763 if ((op & 3) != 2) {
1764 emith_sext(tmp2, tmp, (op & 1) ? 16 : 8);
1766 emith_move_r_r(tmp2, tmp);
1767 rcache_free_tmp(tmp);
1769 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
1770 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 2);
1771 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
1772 /* MS 16 MAC bits unused if saturated */
1773 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
1774 emith_tst_r_imm(sr, S);
1775 EMITH_SJMP_START(DCOND_EQ);
1776 emith_clear_msb_c(DCOND_NE, tmp4, tmp4, 16);
1777 EMITH_SJMP_END(DCOND_EQ);
1779 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW); // might evict SR
1780 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
1781 rcache_free_tmp(tmp2);
1782 sr = rcache_get_reg(SHR_SR, RC_GR_READ); // reget just in case
1783 emith_tst_r_imm(sr, S);
1785 EMITH_JMP_START(DCOND_EQ);
1786 emith_asr(tmp, tmp4, 15);
1787 emith_cmp_r_imm(tmp, -1); // negative overflow (0x80000000..0xffff7fff)
1788 EMITH_SJMP_START(DCOND_GE);
1789 emith_move_r_imm_c(DCOND_LT, tmp4, 0x8000);
1790 emith_move_r_imm_c(DCOND_LT, tmp3, 0x0000);
1791 EMITH_SJMP_END(DCOND_GE);
1792 emith_cmp_r_imm(tmp, 0); // positive overflow (0x00008000..0x7fffffff)
1793 EMITH_SJMP_START(DCOND_LE);
1794 emith_move_r_imm_c(DCOND_GT, tmp4, 0x00007fff);
1795 emith_move_r_imm_c(DCOND_GT, tmp3, 0xffffffff);
1796 EMITH_SJMP_END(DCOND_LE);
1797 EMITH_JMP_END(DCOND_EQ);
1799 rcache_free_tmp(tmp);
1804 /////////////////////////////////////////////
1806 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
1808 tmp = rcache_get_reg_arg(0, GET_Rn());
1809 tmp2 = rcache_get_reg_arg(1, GET_Rm());
1811 emith_add_r_imm(tmp, (op & 0x0f) * 4);
1812 emit_memhandler_write(2, pc);
1818 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
1819 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
1820 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
1822 rcache_get_reg_arg(0, GET_Rn());
1823 rcache_get_reg_arg(1, GET_Rm());
1824 emit_memhandler_write(op & 3, pc);
1826 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
1827 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
1828 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
1829 rcache_get_reg_arg(1, GET_Rm()); // for Rm == Rn
1830 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1831 emith_sub_r_imm(tmp, (1 << (op & 3)));
1833 rcache_get_reg_arg(0, GET_Rn());
1834 emit_memhandler_write(op & 3, pc);
1836 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
1837 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1838 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1839 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1840 emith_bic_r_imm(sr, M|Q|T);
1841 emith_tst_r_imm(tmp2, (1<<31));
1842 EMITH_SJMP_START(DCOND_EQ);
1843 emith_or_r_imm_c(DCOND_NE, sr, Q);
1844 EMITH_SJMP_END(DCOND_EQ);
1845 emith_tst_r_imm(tmp3, (1<<31));
1846 EMITH_SJMP_START(DCOND_EQ);
1847 emith_or_r_imm_c(DCOND_NE, sr, M);
1848 EMITH_SJMP_END(DCOND_EQ);
1849 emith_teq_r_r(tmp2, tmp3);
1850 EMITH_SJMP_START(DCOND_PL);
1851 emith_or_r_imm_c(DCOND_MI, sr, T);
1852 EMITH_SJMP_END(DCOND_PL);
1854 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
1855 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1856 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1857 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1858 emith_bic_r_imm(sr, T);
1859 emith_tst_r_r(tmp2, tmp3);
1860 emit_or_t_if_eq(sr);
1862 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
1863 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1864 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1865 emith_and_r_r(tmp, tmp2);
1867 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
1868 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1869 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1870 emith_eor_r_r(tmp, tmp2);
1872 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
1873 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1874 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1875 emith_or_r_r(tmp, tmp2);
1877 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
1878 tmp = rcache_get_tmp();
1879 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1880 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1881 emith_eor_r_r_r(tmp, tmp2, tmp3);
1882 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1883 emith_bic_r_imm(sr, T);
1884 emith_tst_r_imm(tmp, 0x000000ff);
1885 emit_or_t_if_eq(sr);
1886 emith_tst_r_imm(tmp, 0x0000ff00);
1887 emit_or_t_if_eq(sr);
1888 emith_tst_r_imm(tmp, 0x00ff0000);
1889 emit_or_t_if_eq(sr);
1890 emith_tst_r_imm(tmp, 0xff000000);
1891 emit_or_t_if_eq(sr);
1892 rcache_free_tmp(tmp);
1894 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
1895 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1896 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1897 emith_lsr(tmp, tmp, 16);
1898 emith_or_r_r_lsl(tmp, tmp2, 16);
1900 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
1901 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
1902 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1903 tmp = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1905 emith_sext(tmp, tmp2, 16);
1907 emith_clear_msb(tmp, tmp2, 16);
1908 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1909 tmp2 = rcache_get_tmp();
1911 emith_sext(tmp2, tmp3, 16);
1913 emith_clear_msb(tmp2, tmp3, 16);
1914 emith_mul(tmp, tmp, tmp2);
1915 rcache_free_tmp(tmp2);
1920 /////////////////////////////////////////////
1924 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
1925 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
1926 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
1927 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
1928 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
1929 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1930 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_READ);
1931 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1932 emith_bic_r_imm(sr, T);
1933 emith_cmp_r_r(tmp2, tmp3);
1936 case 0x00: // CMP/EQ
1937 emit_or_t_if_eq(sr);
1939 case 0x02: // CMP/HS
1940 EMITH_SJMP_START(DCOND_LO);
1941 emith_or_r_imm_c(DCOND_HS, sr, T);
1942 EMITH_SJMP_END(DCOND_LO);
1944 case 0x03: // CMP/GE
1945 EMITH_SJMP_START(DCOND_LT);
1946 emith_or_r_imm_c(DCOND_GE, sr, T);
1947 EMITH_SJMP_END(DCOND_LT);
1949 case 0x06: // CMP/HI
1950 EMITH_SJMP_START(DCOND_LS);
1951 emith_or_r_imm_c(DCOND_HI, sr, T);
1952 EMITH_SJMP_END(DCOND_LS);
1954 case 0x07: // CMP/GT
1955 EMITH_SJMP_START(DCOND_LE);
1956 emith_or_r_imm_c(DCOND_GT, sr, T);
1957 EMITH_SJMP_END(DCOND_LE);
1961 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
1962 // Q1 = carry(Rn = (Rn << 1) | T)
1964 // Q2 = carry(Rn += Rm)
1966 // Q2 = carry(Rn -= Rm)
1968 // T = (Q == M) = !(Q ^ M) = !(Q1 ^ Q2)
1969 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
1970 tmp3 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1971 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
1972 emith_tpop_carry(sr, 0);
1973 emith_adcf_r_r(tmp2, tmp2);
1974 emith_tpush_carry(sr, 0); // keep Q1 in T for now
1975 tmp4 = rcache_get_tmp();
1976 emith_and_r_r_imm(tmp4, sr, M);
1977 emith_eor_r_r_lsr(sr, tmp4, M_SHIFT - Q_SHIFT); // Q ^= M
1978 rcache_free_tmp(tmp4);
1979 // add or sub, invert T if carry to get Q1 ^ Q2
1980 // in: (Q ^ M) passed in Q, Q1 in T
1981 emith_sh2_div1_step(tmp2, tmp3, sr);
1982 emith_bic_r_imm(sr, Q);
1983 emith_tst_r_imm(sr, M);
1984 EMITH_SJMP_START(DCOND_EQ);
1985 emith_or_r_imm_c(DCOND_NE, sr, Q); // Q = M
1986 EMITH_SJMP_END(DCOND_EQ);
1987 emith_tst_r_imm(sr, T);
1988 EMITH_SJMP_START(DCOND_EQ);
1989 emith_eor_r_imm_c(DCOND_NE, sr, Q); // Q = M ^ Q1 ^ Q2
1990 EMITH_SJMP_END(DCOND_EQ);
1991 emith_eor_r_imm(sr, T); // T = !(Q1 ^ Q2)
1993 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
1994 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
1995 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
1996 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
1997 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
1998 emith_mul_u64(tmp3, tmp4, tmp, tmp2);
2000 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
2001 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
2002 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2003 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2005 emith_add_r_r(tmp, tmp2);
2007 emith_sub_r_r(tmp, tmp2);
2009 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
2010 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
2011 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2012 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2013 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2014 if (op & 4) { // adc
2015 emith_tpop_carry(sr, 0);
2016 emith_adcf_r_r(tmp, tmp2);
2017 emith_tpush_carry(sr, 0);
2019 emith_tpop_carry(sr, 1);
2020 emith_sbcf_r_r(tmp, tmp2);
2021 emith_tpush_carry(sr, 1);
2024 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
2025 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
2026 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2027 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2028 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2029 emith_bic_r_imm(sr, T);
2031 emith_addf_r_r(tmp, tmp2);
2033 emith_subf_r_r(tmp, tmp2);
2034 EMITH_SJMP_START(DCOND_VC);
2035 emith_or_r_imm_c(DCOND_VS, sr, T);
2036 EMITH_SJMP_END(DCOND_VC);
2038 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
2039 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2040 tmp2 = rcache_get_reg(GET_Rm(), RC_GR_READ);
2041 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_WRITE);
2042 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_WRITE);
2043 emith_mul_s64(tmp3, tmp4, tmp, tmp2);
2048 /////////////////////////////////////////////
2055 case 0: // SHLL Rn 0100nnnn00000000
2056 case 2: // SHAL Rn 0100nnnn00100000
2057 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2058 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2059 emith_tpop_carry(sr, 0); // dummy
2060 emith_lslf(tmp, tmp, 1);
2061 emith_tpush_carry(sr, 0);
2063 case 1: // DT Rn 0100nnnn00010000
2064 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2065 #if 0 // scheduling needs tuning
2066 if (FETCH_OP(pc) == 0x8bfd) { // BF #-2
2067 if (gconst_get(GET_Rn(), &tmp)) {
2068 // XXX: limit burned cycles
2069 emit_move_r_imm32(GET_Rn(), 0);
2070 emith_or_r_imm(sr, T);
2071 cycles += tmp * 4 + 1; // +1 syncs with noconst version, not sure why
2075 emith_sh2_dtbf_loop();
2079 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2080 emith_bic_r_imm(sr, T);
2081 emith_subf_r_imm(tmp, 1);
2082 emit_or_t_if_eq(sr);
2089 case 0: // SHLR Rn 0100nnnn00000001
2090 case 2: // SHAR Rn 0100nnnn00100001
2091 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2092 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2093 emith_tpop_carry(sr, 0); // dummy
2095 emith_asrf(tmp, tmp, 1);
2097 emith_lsrf(tmp, tmp, 1);
2098 emith_tpush_carry(sr, 0);
2100 case 1: // CMP/PZ Rn 0100nnnn00010001
2101 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2102 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2103 emith_bic_r_imm(sr, T);
2104 emith_cmp_r_imm(tmp, 0);
2105 EMITH_SJMP_START(DCOND_LT);
2106 emith_or_r_imm_c(DCOND_GE, sr, T);
2107 EMITH_SJMP_END(DCOND_LT);
2115 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
2118 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
2121 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
2124 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
2127 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
2130 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
2136 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2137 emith_sub_r_imm(tmp2, 4);
2139 rcache_get_reg_arg(0, GET_Rn());
2140 tmp3 = rcache_get_reg_arg(1, tmp);
2142 emith_clear_msb(tmp3, tmp3, 22); // reserved bits defined by ISA as 0
2143 emit_memhandler_write(2, pc);
2149 case 0x04: // ROTL Rn 0100nnnn00000100
2150 case 0x05: // ROTR Rn 0100nnnn00000101
2151 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2152 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2153 emith_tpop_carry(sr, 0); // dummy
2155 emith_rorf(tmp, tmp, 1);
2157 emith_rolf(tmp, tmp, 1);
2158 emith_tpush_carry(sr, 0);
2160 case 0x24: // ROTCL Rn 0100nnnn00100100
2161 case 0x25: // ROTCR Rn 0100nnnn00100101
2162 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2163 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2164 emith_tpop_carry(sr, 0);
2169 emith_tpush_carry(sr, 0);
2171 case 0x15: // CMP/PL Rn 0100nnnn00010101
2172 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2173 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2174 emith_bic_r_imm(sr, T);
2175 emith_cmp_r_imm(tmp, 0);
2176 EMITH_SJMP_START(DCOND_LE);
2177 emith_or_r_imm_c(DCOND_GT, sr, T);
2178 EMITH_SJMP_END(DCOND_LE);
2186 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
2189 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
2192 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
2195 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
2198 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
2201 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
2207 rcache_get_reg_arg(0, GET_Rn());
2208 tmp2 = emit_memhandler_read(2);
2209 if (tmp == SHR_SR) {
2210 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2211 emith_write_sr(sr, tmp2);
2214 tmp = rcache_get_reg(tmp, RC_GR_WRITE);
2215 emith_move_r_r(tmp, tmp2);
2217 rcache_free_tmp(tmp2);
2218 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2219 emith_add_r_imm(tmp, 4);
2226 // SHLL2 Rn 0100nnnn00001000
2227 // SHLR2 Rn 0100nnnn00001001
2231 // SHLL8 Rn 0100nnnn00011000
2232 // SHLR8 Rn 0100nnnn00011001
2236 // SHLL16 Rn 0100nnnn00101000
2237 // SHLR16 Rn 0100nnnn00101001
2243 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2245 emith_lsr(tmp2, tmp2, tmp);
2247 emith_lsl(tmp2, tmp2, tmp);
2252 case 0: // LDS Rm,MACH 0100mmmm00001010
2255 case 1: // LDS Rm,MACL 0100mmmm00011010
2258 case 2: // LDS Rm,PR 0100mmmm00101010
2264 emit_move_r_r(tmp2, GET_Rn());
2269 case 1: // TAS.B @Rn 0100nnnn00011011
2270 // XXX: is TAS working on 32X?
2271 rcache_get_reg_arg(0, GET_Rn());
2272 tmp = emit_memhandler_read(0);
2273 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2274 emith_bic_r_imm(sr, T);
2275 emith_cmp_r_imm(tmp, 0);
2276 emit_or_t_if_eq(sr);
2278 emith_or_r_imm(tmp, 0x80);
2279 tmp2 = rcache_get_tmp_arg(1); // assuming it differs to tmp
2280 emith_move_r_r(tmp2, tmp);
2281 rcache_free_tmp(tmp);
2282 rcache_get_reg_arg(0, GET_Rn());
2283 emit_memhandler_write(0, pc);
2290 tmp = rcache_get_reg(GET_Rn(), RC_GR_READ);
2293 case 0: // LDC Rm,SR 0100mmmm00001110
2296 case 1: // LDC Rm,GBR 0100mmmm00011110
2299 case 2: // LDC Rm,VBR 0100mmmm00101110
2305 if (tmp2 == SHR_SR) {
2306 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2307 emith_write_sr(sr, tmp);
2310 tmp2 = rcache_get_reg(tmp2, RC_GR_WRITE);
2311 emith_move_r_r(tmp2, tmp);
2315 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
2316 emit_indirect_read_double(&tmp, &tmp2, GET_Rn(), GET_Rm(), 1);
2317 emith_sext(tmp, tmp, 16);
2318 emith_sext(tmp2, tmp2, 16);
2319 tmp3 = rcache_get_reg(SHR_MACL, RC_GR_RMW);
2320 tmp4 = rcache_get_reg(SHR_MACH, RC_GR_RMW);
2321 emith_mula_s64(tmp3, tmp4, tmp, tmp2);
2322 rcache_free_tmp(tmp2);
2323 // XXX: MACH should be untouched when S is set?
2324 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2325 emith_tst_r_imm(sr, S);
2326 EMITH_JMP_START(DCOND_EQ);
2328 emith_asr(tmp, tmp3, 31);
2329 emith_eorf_r_r(tmp, tmp4); // tmp = ((signed)macl >> 31) ^ mach
2330 EMITH_JMP_START(DCOND_EQ);
2331 emith_move_r_imm(tmp3, 0x80000000);
2332 emith_tst_r_r(tmp4, tmp4);
2333 EMITH_SJMP_START(DCOND_MI);
2334 emith_sub_r_imm_c(DCOND_PL, tmp3, 1); // positive
2335 EMITH_SJMP_END(DCOND_MI);
2336 EMITH_JMP_END(DCOND_EQ);
2338 EMITH_JMP_END(DCOND_EQ);
2339 rcache_free_tmp(tmp);
2344 /////////////////////////////////////////////
2346 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
2347 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), (op & 0x0f) * 4, 2);
2350 /////////////////////////////////////////////
2354 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
2355 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
2356 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
2357 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
2358 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
2359 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
2360 emit_memhandler_read_rr(GET_Rn(), GET_Rm(), 0, op & 3);
2361 if ((op & 7) >= 4 && GET_Rn() != GET_Rm()) {
2362 tmp = rcache_get_reg(GET_Rm(), RC_GR_RMW);
2363 emith_add_r_imm(tmp, (1 << (op & 3)));
2368 tmp = rcache_get_reg(GET_Rm(), RC_GR_READ);
2369 tmp2 = rcache_get_reg(GET_Rn(), RC_GR_WRITE);
2372 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
2373 emith_move_r_r(tmp2, tmp);
2375 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
2376 emith_mvn_r_r(tmp2, tmp);
2378 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
2381 tmp3 = rcache_get_tmp();
2382 tmp4 = rcache_get_tmp();
2383 emith_lsr(tmp3, tmp, 16);
2384 emith_or_r_r_lsl(tmp3, tmp, 24);
2385 emith_and_r_r_imm(tmp4, tmp, 0xff00);
2386 emith_or_r_r_lsl(tmp3, tmp4, 8);
2387 emith_rol(tmp2, tmp3, 16);
2388 rcache_free_tmp(tmp4);
2390 rcache_free_tmp(tmp3);
2392 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
2393 emith_rol(tmp2, tmp, 16);
2395 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
2396 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2397 emith_tpop_carry(sr, 1);
2398 emith_negcf_r_r(tmp2, tmp);
2399 emith_tpush_carry(sr, 1);
2401 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
2402 emith_neg_r_r(tmp2, tmp);
2404 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
2405 emith_clear_msb(tmp2, tmp, 24);
2407 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
2408 emith_clear_msb(tmp2, tmp, 16);
2410 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
2411 emith_sext(tmp2, tmp, 8);
2413 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
2414 emith_sext(tmp2, tmp, 16);
2421 /////////////////////////////////////////////
2423 // ADD #imm,Rn 0111nnnniiiiiiii
2424 tmp = rcache_get_reg(GET_Rn(), RC_GR_RMW);
2425 if (op & 0x80) { // adding negative
2426 emith_sub_r_imm(tmp, -op & 0xff);
2428 emith_add_r_imm(tmp, op & 0xff);
2431 /////////////////////////////////////////////
2433 switch (op & 0x0f00)
2435 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
2436 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
2438 tmp = rcache_get_reg_arg(0, GET_Rm());
2439 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2440 tmp3 = (op & 0x100) >> 8;
2442 emith_add_r_imm(tmp, (op & 0x0f) << tmp3);
2443 emit_memhandler_write(tmp3, pc);
2445 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
2446 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
2447 tmp = (op & 0x100) >> 8;
2448 emit_memhandler_read_rr(SHR_R0, GET_Rm(), (op & 0x0f) << tmp, tmp);
2450 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
2451 // XXX: could use cmn
2452 tmp = rcache_get_tmp();
2453 tmp2 = rcache_get_reg(0, RC_GR_READ);
2454 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2455 emith_move_r_imm_s8(tmp, op & 0xff);
2456 emith_bic_r_imm(sr, T);
2457 emith_cmp_r_r(tmp2, tmp);
2458 emit_or_t_if_eq(sr);
2459 rcache_free_tmp(tmp);
2464 /////////////////////////////////////////////
2466 switch (op & 0x0f00)
2468 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
2469 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
2470 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
2472 tmp = rcache_get_reg_arg(0, SHR_GBR);
2473 tmp2 = rcache_get_reg_arg(1, SHR_R0);
2474 tmp3 = (op & 0x300) >> 8;
2475 emith_add_r_imm(tmp, (op & 0xff) << tmp3);
2476 emit_memhandler_write(tmp3, pc);
2478 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
2479 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
2480 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
2481 tmp = (op & 0x300) >> 8;
2482 emit_memhandler_read_rr(SHR_R0, SHR_GBR, (op & 0xff) << tmp, tmp);
2484 case 0x0300: // TRAPA #imm 11000011iiiiiiii
2485 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2486 emith_sub_r_imm(tmp, 4*2);
2488 tmp = rcache_get_reg_arg(0, SHR_SP);
2489 emith_add_r_imm(tmp, 4);
2490 tmp = rcache_get_reg_arg(1, SHR_SR);
2491 emith_clear_msb(tmp, tmp, 22);
2492 emit_memhandler_write(2, pc);
2494 rcache_get_reg_arg(0, SHR_SP);
2495 tmp = rcache_get_tmp_arg(1);
2496 emith_move_r_imm(tmp, pc);
2497 emit_memhandler_write(2, pc);
2499 emit_memhandler_read_rr(SHR_PC, SHR_VBR, (op & 0xff) * 4, 2);
2500 // indirect jump -> back to dispatcher
2502 emith_jump(sh2_drc_dispatcher);
2504 case 0x0800: // TST #imm,R0 11001000iiiiiiii
2505 tmp = rcache_get_reg(SHR_R0, RC_GR_READ);
2506 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2507 emith_bic_r_imm(sr, T);
2508 emith_tst_r_imm(tmp, op & 0xff);
2509 emit_or_t_if_eq(sr);
2511 case 0x0900: // AND #imm,R0 11001001iiiiiiii
2512 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2513 emith_and_r_imm(tmp, op & 0xff);
2515 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
2516 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2517 emith_eor_r_imm(tmp, op & 0xff);
2519 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
2520 tmp = rcache_get_reg(SHR_R0, RC_GR_RMW);
2521 emith_or_r_imm(tmp, op & 0xff);
2523 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
2524 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2525 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2526 emith_bic_r_imm(sr, T);
2527 emith_tst_r_imm(tmp, op & 0xff);
2528 emit_or_t_if_eq(sr);
2529 rcache_free_tmp(tmp);
2531 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
2532 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2533 emith_and_r_imm(tmp, op & 0xff);
2535 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
2536 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2537 emith_eor_r_imm(tmp, op & 0xff);
2539 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
2540 tmp = emit_indirect_indexed_read(SHR_R0, SHR_GBR, 0);
2541 emith_or_r_imm(tmp, op & 0xff);
2543 tmp2 = rcache_get_tmp_arg(1);
2544 emith_move_r_r(tmp2, tmp);
2545 rcache_free_tmp(tmp);
2546 tmp3 = rcache_get_reg_arg(0, SHR_GBR);
2547 tmp4 = rcache_get_reg(SHR_R0, RC_GR_READ);
2548 emith_add_r_r(tmp3, tmp4);
2549 emit_memhandler_write(0, pc);
2554 /////////////////////////////////////////////
2556 // MOV #imm,Rn 1110nnnniiiiiiii
2557 emit_move_r_imm32(GET_Rn(), (u32)(signed int)(signed char)op);
2562 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
2563 sh2->is_slave ? 's' : 'm', op, pc - 2);
2568 rcache_unlock_all();
2570 cycles += opd->cycles;
2572 if (op_flags[i+1] & OF_DELAY_OP) {
2573 do_host_disasm(tcache_id);
2578 if (drcf.test_irq && !drcf.pending_branch_direct) {
2579 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2581 if (!drcf.pending_branch_indirect)
2582 emit_move_r_imm32(SHR_PC, pc);
2584 emith_call(sh2_drc_test_irq);
2588 // branch handling (with/without delay)
2589 if (drcf.pending_branch_direct)
2591 struct op_data *opd_b =
2592 (op_flags[i] & OF_DELAY_OP) ? &ops[i-1] : opd;
2593 u32 target_pc = opd_b->imm;
2595 void *target = NULL;
2597 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2600 if (opd_b->op != OP_BRANCH)
2601 cond = (opd_b->op == OP_BRANCH_CF) ? DCOND_EQ : DCOND_NE;
2603 int ctaken = (op_flags[i] & OF_DELAY_OP) ? 1 : 2;
2605 if (delay_dep_fw & BITMASK1(SHR_T))
2606 emith_tst_r_imm(sr, T_save);
2608 emith_tst_r_imm(sr, T);
2610 emith_sub_r_imm_c(cond, sr, ctaken<<12);
2615 if (find_in_array(branch_target_pc, branch_target_count, target_pc) >= 0)
2618 // XXX: jumps back can be linked already
2619 if (branch_patch_count < MAX_LOCAL_BRANCHES) {
2620 target = tcache_ptr;
2621 branch_patch_pc[branch_patch_count] = target_pc;
2622 branch_patch_ptr[branch_patch_count] = target;
2623 branch_patch_count++;
2626 dbg(1, "warning: too many local branches");
2632 // can't resolve branch locally, make a block exit
2633 emit_move_r_imm32(SHR_PC, target_pc);
2636 target = dr_prepare_ext_branch(target_pc, sh2->is_slave, tcache_id);
2642 emith_jump_cond_patchable(cond, target);
2644 emith_jump_patchable(target);
2645 rcache_invalidate();
2648 drcf.pending_branch_direct = 0;
2650 else if (drcf.pending_branch_indirect) {
2651 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2654 emith_jump(sh2_drc_dispatcher);
2655 drcf.pending_branch_indirect = 0;
2658 do_host_disasm(tcache_id);
2661 tmp = rcache_get_reg(SHR_SR, RC_GR_RMW);
2665 // check the last op
2666 if (op_flags[i-1] & OF_DELAY_OP)
2671 if (opd->op != OP_BRANCH && opd->op != OP_BRANCH_R
2672 && opd->op != OP_BRANCH_RF && opd->op != OP_RTE)
2676 emit_move_r_imm32(SHR_PC, pc);
2679 target = dr_prepare_ext_branch(pc, sh2->is_slave, tcache_id);
2682 emith_jump_patchable(target);
2685 // link local branches
2686 for (i = 0; i < branch_patch_count; i++) {
2689 t = find_in_array(branch_target_pc, branch_target_count, branch_patch_pc[i]);
2690 target = branch_target_ptr[t];
2691 if (target == NULL) {
2692 // flush pc and go back to dispatcher (this should no longer happen)
2693 dbg(1, "stray branch to %08x %p", branch_patch_pc[i], tcache_ptr);
2694 target = tcache_ptr;
2695 emit_move_r_imm32(SHR_PC, branch_patch_pc[i]);
2697 emith_jump(sh2_drc_dispatcher);
2699 emith_jump_patch(branch_patch_ptr[i], target);
2702 // mark memory blocks as containing compiled code
2703 // override any overlay blocks as they become unreachable anyway
2704 if ((block->addr & 0xc7fc0000) == 0x06000000
2705 || (block->addr & 0xfffff000) == 0xc0000000)
2707 u16 *drc_ram_blk = NULL;
2708 u32 addr, mask = 0, shift = 0;
2710 if (tcache_id != 0) {
2712 drc_ram_blk = Pico32xMem->drcblk_da[sh2->is_slave];
2713 shift = SH2_DRCBLK_DA_SHIFT;
2718 drc_ram_blk = Pico32xMem->drcblk_ram;
2719 shift = SH2_DRCBLK_RAM_SHIFT;
2723 // mark recompiled insns
2724 drc_ram_blk[(base_pc & mask) >> shift] = 1;
2725 for (pc = base_pc; pc < end_pc; pc += 2)
2726 drc_ram_blk[(pc & mask) >> shift] = 1;
2729 for (i = 0; i < literal_addr_count; i++) {
2730 tmp = literal_addr[i];
2731 drc_ram_blk[(tmp & mask) >> shift] = 1;
2734 // add to invalidation lookup lists
2735 addr = base_pc & ~(ADDR_TO_BLOCK_PAGE - 1);
2736 for (; addr < end_literals; addr += ADDR_TO_BLOCK_PAGE) {
2737 i = (addr & mask) / ADDR_TO_BLOCK_PAGE;
2738 add_to_block_list(&inval_lookup[tcache_id][i], block);
2742 tcache_ptrs[tcache_id] = tcache_ptr;
2744 host_instructions_updated(block_entry_ptr, tcache_ptr);
2746 do_host_disasm(tcache_id);
2747 dbg(2, " block #%d,%d tcache %d/%d, insns %d -> %d %.3f",
2748 tcache_id, blkid_main,
2749 tcache_ptr - tcache_bases[tcache_id], tcache_sizes[tcache_id],
2750 insns_compiled, host_insn_count, (float)host_insn_count / insns_compiled);
2751 if ((sh2->pc & 0xc6000000) == 0x02000000) // ROM
2752 dbg(2, " hash collisions %d/%d", hash_collisions, block_counts[tcache_id]);
2755 tcache_dsm_ptrs[tcache_id] = block_entry_ptr;
2756 do_host_disasm(tcache_id);
2764 return block_entry_ptr;
2767 static void sh2_generate_utils(void)
2769 int arg0, arg1, arg2, sr, tmp;
2771 sh2_drc_write32 = p32x_sh2_write32;
2772 sh2_drc_read8 = p32x_sh2_read8;
2773 sh2_drc_read16 = p32x_sh2_read16;
2774 sh2_drc_read32 = p32x_sh2_read32;
2776 host_arg2reg(arg0, 0);
2777 host_arg2reg(arg1, 1);
2778 host_arg2reg(arg2, 2);
2779 emith_move_r_r(arg0, arg0); // nop
2781 // sh2_drc_exit(void)
2782 sh2_drc_exit = (void *)tcache_ptr;
2783 emit_do_static_regs(1, arg2);
2784 emith_sh2_drc_exit();
2786 // sh2_drc_dispatcher(void)
2787 sh2_drc_dispatcher = (void *)tcache_ptr;
2788 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2789 emith_cmp_r_imm(sr, 0);
2790 emith_jump_cond(DCOND_LT, sh2_drc_exit);
2791 rcache_invalidate();
2792 emith_ctx_read(arg0, SHR_PC * 4);
2793 emith_ctx_read(arg1, offsetof(SH2, is_slave));
2794 emith_add_r_r_imm(arg2, CONTEXT_REG, offsetof(SH2, drc_tmp));
2795 emith_call(dr_lookup_block);
2797 // lookup failed, call sh2_translate()
2798 emith_move_r_r(arg0, CONTEXT_REG);
2799 emith_ctx_read(arg1, offsetof(SH2, drc_tmp)); // tcache_id
2800 emith_call(sh2_translate);
2802 // sh2_translate() failed, flush cache and retry
2803 emith_ctx_read(arg0, offsetof(SH2, drc_tmp));
2804 emith_call(flush_tcache);
2805 emith_move_r_r(arg0, CONTEXT_REG);
2806 emith_ctx_read(arg1, offsetof(SH2, drc_tmp));
2807 emith_call(sh2_translate);
2809 // XXX: can't translate, fail
2810 emith_call(dr_failure);
2812 // sh2_drc_test_irq(void)
2813 // assumes it's called from main function (may jump to dispatcher)
2814 sh2_drc_test_irq = (void *)tcache_ptr;
2815 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2816 sr = rcache_get_reg(SHR_SR, RC_GR_READ);
2817 emith_lsr(arg0, sr, I_SHIFT);
2818 emith_and_r_imm(arg0, 0x0f);
2819 emith_cmp_r_r(arg1, arg0); // pending_level > ((sr >> 4) & 0x0f)?
2820 EMITH_SJMP_START(DCOND_GT);
2821 emith_ret_c(DCOND_LE); // nope, return
2822 EMITH_SJMP_END(DCOND_GT);
2824 tmp = rcache_get_reg(SHR_SP, RC_GR_RMW);
2825 emith_sub_r_imm(tmp, 4*2);
2828 tmp = rcache_get_reg_arg(0, SHR_SP);
2829 emith_add_r_imm(tmp, 4);
2830 tmp = rcache_get_reg_arg(1, SHR_SR);
2831 emith_clear_msb(tmp, tmp, 22);
2832 emith_move_r_r(arg2, CONTEXT_REG);
2833 emith_call(p32x_sh2_write32); // XXX: use sh2_drc_write32?
2834 rcache_invalidate();
2836 rcache_get_reg_arg(0, SHR_SP);
2837 emith_ctx_read(arg1, SHR_PC * 4);
2838 emith_move_r_r(arg2, CONTEXT_REG);
2839 emith_call(p32x_sh2_write32);
2840 rcache_invalidate();
2841 // update I, cycles, do callback
2842 emith_ctx_read(arg1, offsetof(SH2, pending_level));
2843 sr = rcache_get_reg(SHR_SR, RC_GR_RMW);
2844 emith_bic_r_imm(sr, I);
2845 emith_or_r_r_lsl(sr, arg1, I_SHIFT);
2846 emith_sub_r_imm(sr, 13 << 12); // at least 13 cycles
2848 emith_move_r_r(arg0, CONTEXT_REG);
2849 emith_call_ctx(offsetof(SH2, irq_callback)); // vector = sh2->irq_callback(sh2, level);
2851 emith_lsl(arg0, arg0, 2);
2852 emith_ctx_read(arg1, SHR_VBR * 4);
2853 emith_add_r_r(arg0, arg1);
2854 emit_memhandler_read(2);
2855 emith_ctx_write(arg0, SHR_PC * 4);
2857 emith_add_r_imm(xSP, 4); // fix stack
2859 emith_jump(sh2_drc_dispatcher);
2860 rcache_invalidate();
2862 // sh2_drc_entry(SH2 *sh2)
2863 sh2_drc_entry = (void *)tcache_ptr;
2864 emith_sh2_drc_entry();
2865 emith_move_r_r(CONTEXT_REG, arg0); // move ctx, arg0
2866 emit_do_static_regs(0, arg2);
2867 emith_call(sh2_drc_test_irq);
2868 emith_jump(sh2_drc_dispatcher);
2870 // sh2_drc_write8(u32 a, u32 d)
2871 sh2_drc_write8 = (void *)tcache_ptr;
2872 emith_ctx_read(arg2, offsetof(SH2, write8_tab));
2873 emith_sh2_wcall(arg0, arg2);
2875 // sh2_drc_write16(u32 a, u32 d)
2876 sh2_drc_write16 = (void *)tcache_ptr;
2877 emith_ctx_read(arg2, offsetof(SH2, write16_tab));
2878 emith_sh2_wcall(arg0, arg2);
2882 #define MAKE_READ_WRAPPER(func) { \
2883 void *tmp = (void *)tcache_ptr; \
2886 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2887 emith_addf_r_r(arg2, arg0); \
2888 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2889 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2890 emith_adc_r_imm(arg2, 0x01000000); \
2891 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2892 emith_pop_and_ret(); \
2895 #define MAKE_WRITE_WRAPPER(func) { \
2896 void *tmp = (void *)tcache_ptr; \
2897 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[0])); \
2898 emith_addf_r_r(arg2, arg1); \
2899 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[0])); \
2900 emith_ctx_read(arg2, offsetof(SH2, pdb_io_csum[1])); \
2901 emith_adc_r_imm(arg2, 0x01000000); \
2902 emith_ctx_write(arg2, offsetof(SH2, pdb_io_csum[1])); \
2903 emith_move_r_r(arg2, CONTEXT_REG); \
2908 MAKE_READ_WRAPPER(sh2_drc_read8);
2909 MAKE_READ_WRAPPER(sh2_drc_read16);
2910 MAKE_READ_WRAPPER(sh2_drc_read32);
2911 MAKE_WRITE_WRAPPER(sh2_drc_write8);
2912 MAKE_WRITE_WRAPPER(sh2_drc_write16);
2913 MAKE_WRITE_WRAPPER(sh2_drc_write32);
2915 host_dasm_new_symbol(sh2_drc_read8);
2916 host_dasm_new_symbol(sh2_drc_read16);
2917 host_dasm_new_symbol(sh2_drc_read32);
2918 host_dasm_new_symbol(sh2_drc_write32);
2922 rcache_invalidate();
2924 host_dasm_new_symbol(sh2_drc_entry);
2925 host_dasm_new_symbol(sh2_drc_dispatcher);
2926 host_dasm_new_symbol(sh2_drc_exit);
2927 host_dasm_new_symbol(sh2_drc_test_irq);
2928 host_dasm_new_symbol(sh2_drc_write8);
2929 host_dasm_new_symbol(sh2_drc_write16);
2933 static void sh2_smc_rm_block_entry(struct block_desc *bd, int tcache_id, u32 ram_mask)
2935 struct block_link *bl, *bl_next, *bl_unresolved;
2939 dbg(2, " killing entry %08x-%08x, blkid %d,%d",
2940 bd->addr, bd->end_addr, tcache_id, bd - block_tables[tcache_id]);
2941 if (bd->addr == 0 || bd->entry_count == 0) {
2942 dbg(1, " killing dead block!? %08x", bd->addr);
2946 // remove from inval_lookup
2947 addr = bd->addr & ~(ADDR_TO_BLOCK_PAGE - 1);
2948 for (; addr < bd->end_addr; addr += ADDR_TO_BLOCK_PAGE) {
2949 i = (addr & ram_mask) / ADDR_TO_BLOCK_PAGE;
2950 rm_from_block_list(&inval_lookup[tcache_id][i], bd);
2954 bl_unresolved = unresolved_links[tcache_id];
2956 // remove from hash table, make incoming links unresolved
2957 // XXX: maybe patch branches w/flush instead?
2958 for (i = 0; i < bd->entry_count; i++) {
2959 rm_from_hashlist(&bd->entryp[i], tcache_id);
2961 // since we never reuse tcache space of dead blocks,
2962 // insert jump to dispatcher for blocks that are linked to this
2963 tcache_ptr = bd->entryp[i].tcache_ptr;
2964 emit_move_r_imm32(SHR_PC, bd->entryp[i].pc);
2966 emith_jump(sh2_drc_dispatcher);
2968 host_instructions_updated(bd->entryp[i].tcache_ptr, tcache_ptr);
2970 for (bl = bd->entryp[i].links; bl != NULL; ) {
2972 bl->next = bl_unresolved;
2979 unresolved_links[tcache_id] = bl_unresolved;
2981 bd->addr = bd->end_addr = 0;
2982 bd->entry_count = 0;
2985 static void sh2_smc_rm_block(u32 a, u16 *drc_ram_blk, int tcache_id, u32 shift, u32 mask)
2987 struct block_list **blist = NULL, *entry;
2988 u32 from = ~0, to = 0;
2989 struct block_desc *block;
2991 blist = &inval_lookup[tcache_id][(a & mask) / ADDR_TO_BLOCK_PAGE];
2993 while (entry != NULL) {
2994 block = entry->block;
2995 if (block->addr <= a && a < block->end_addr) {
2996 if (block->addr < from)
2998 if (block->end_addr > to)
2999 to = block->end_addr;
3001 sh2_smc_rm_block_entry(block, tcache_id, mask);
3003 // entry lost, restart search
3007 entry = entry->next;
3010 // update range to not clear still alive blocks
3011 for (entry = *blist; entry != NULL; entry = entry->next) {
3012 block = entry->block;
3013 if (block->addr > a) {
3014 if (to > block->addr)
3018 if (from < block->end_addr)
3019 from = block->end_addr;
3025 u16 *p = drc_ram_blk + ((from & mask) >> shift);
3026 memset(p, 0, (to - from) >> (shift - 1));
3030 void sh2_drc_wcheck_ram(unsigned int a, int val, int cpuid)
3032 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3033 sh2_smc_rm_block(a, Pico32xMem->drcblk_ram, 0, SH2_DRCBLK_RAM_SHIFT, 0x3ffff);
3036 void sh2_drc_wcheck_da(unsigned int a, int val, int cpuid)
3038 dbg(2, "%csh2 smc check @%08x", cpuid ? 's' : 'm', a);
3039 sh2_smc_rm_block(a, Pico32xMem->drcblk_da[cpuid],
3040 1 + cpuid, SH2_DRCBLK_DA_SHIFT, 0xfff);
3043 int sh2_execute(SH2 *sh2c, int cycles)
3047 sh2c->cycles_timeslice = cycles;
3049 // cycles are kept in SHR_SR unused bits (upper 20)
3050 // bit11 contains T saved for delay slot
3051 // others are usual SH2 flags
3053 sh2c->sr |= cycles << 12;
3054 sh2_drc_entry(sh2c);
3057 ret_cycles = (signed int)sh2c->sr >> 12;
3059 dbg(1, "warning: drc returned with cycles: %d", ret_cycles);
3061 return sh2c->cycles_timeslice - ret_cycles;
3065 void block_stats(void)
3067 int c, b, i, total = 0;
3069 printf("block stats:\n");
3070 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3071 for (i = 0; i < block_counts[b]; i++)
3072 if (block_tables[b][i].addr != 0)
3073 total += block_tables[b][i].refcount;
3075 for (c = 0; c < 10; c++) {
3076 struct block_desc *blk, *maxb = NULL;
3078 for (b = 0; b < ARRAY_SIZE(block_tables); b++) {
3079 for (i = 0; i < block_counts[b]; i++) {
3080 blk = &block_tables[b][i];
3081 if (blk->addr != 0 && blk->refcount > max) {
3082 max = blk->refcount;
3089 printf("%08x %9d %2.3f%%\n", maxb->addr, maxb->refcount,
3090 (double)maxb->refcount / total * 100.0);
3094 for (b = 0; b < ARRAY_SIZE(block_tables); b++)
3095 for (i = 0; i < block_counts[b]; i++)
3096 block_tables[b][i].refcount = 0;
3099 #define block_stats()
3102 void sh2_drc_flush_all(void)
3110 void sh2_drc_mem_setup(SH2 *sh2)
3112 // fill the convenience pointers
3113 sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3114 sh2->p_da = Pico32xMem->data_array[sh2->is_slave];
3115 sh2->p_sdram = Pico32xMem->sdram;
3116 sh2->p_rom = Pico.rom;
3119 int sh2_drc_init(SH2 *sh2)
3123 if (block_tables[0] == NULL)
3125 for (i = 0; i < TCACHE_BUFFERS; i++) {
3126 block_tables[i] = calloc(block_max_counts[i], sizeof(*block_tables[0]));
3127 if (block_tables[i] == NULL)
3129 // max 2 block links (exits) per block
3130 block_link_pool[i] = calloc(block_link_pool_max_counts[i],
3131 sizeof(*block_link_pool[0]));
3132 if (block_link_pool[i] == NULL)
3135 inval_lookup[i] = calloc(ram_sizes[i] / ADDR_TO_BLOCK_PAGE,
3136 sizeof(inval_lookup[0]));
3137 if (inval_lookup[i] == NULL)
3140 hash_tables[i] = calloc(hash_table_sizes[i], sizeof(*hash_tables[0]));
3141 if (hash_tables[i] == NULL)
3144 memset(block_counts, 0, sizeof(block_counts));
3145 memset(block_link_pool_counts, 0, sizeof(block_link_pool_counts));
3148 tcache_ptr = tcache;
3149 sh2_generate_utils();
3150 host_instructions_updated(tcache, tcache_ptr);
3152 tcache_bases[0] = tcache_ptrs[0] = tcache_ptr;
3153 for (i = 1; i < ARRAY_SIZE(tcache_bases); i++)
3154 tcache_bases[i] = tcache_ptrs[i] = tcache_bases[i - 1] + tcache_sizes[i - 1];
3157 for (i = 0; i < ARRAY_SIZE(block_tables); i++)
3158 tcache_dsm_ptrs[i] = tcache_bases[i];
3160 tcache_dsm_ptrs[0] = tcache;
3164 hash_collisions = 0;
3171 sh2_drc_finish(sh2);
3175 void sh2_drc_finish(SH2 *sh2)
3179 if (block_tables[0] == NULL)
3182 sh2_drc_flush_all();
3184 for (i = 0; i < TCACHE_BUFFERS; i++) {
3186 printf("~~~ tcache %d\n", i);
3187 tcache_dsm_ptrs[i] = tcache_bases[i];
3188 tcache_ptr = tcache_ptrs[i];
3192 if (block_tables[i] != NULL)
3193 free(block_tables[i]);
3194 block_tables[i] = NULL;
3195 if (block_link_pool[i] == NULL)
3196 free(block_link_pool[i]);
3197 block_link_pool[i] = NULL;
3199 if (inval_lookup[i] == NULL)
3200 free(inval_lookup[i]);
3201 inval_lookup[i] = NULL;
3203 if (hash_tables[i] != NULL) {
3204 free(hash_tables[i]);
3205 hash_tables[i] = NULL;
3212 #endif /* DRC_SH2 */
3214 static void *dr_get_pc_base(u32 pc, int is_slave)
3219 if ((pc & ~0x7ff) == 0) {
3221 ret = is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
3224 else if ((pc & 0xfffff000) == 0xc0000000) {
3226 ret = Pico32xMem->data_array[is_slave];
3229 else if ((pc & 0xc6000000) == 0x06000000) {
3231 ret = Pico32xMem->sdram;
3234 else if ((pc & 0xc6000000) == 0x02000000) {
3241 return (void *)-1; // NULL is valid value
3243 return (char *)ret - (pc & ~mask);
3246 void scan_block(u32 base_pc, int is_slave, u8 *op_flags, u32 *end_pc_out,
3247 u32 *end_literals_out)
3251 u32 end_pc, end_literals = 0;
3252 struct op_data *opd;
3253 int next_is_delay = 0;
3257 memset(op_flags, 0, BLOCK_INSN_LIMIT);
3259 dr_pc_base = dr_get_pc_base(base_pc, is_slave);
3261 // 1st pass: disassemble
3262 for (i = 0, pc = base_pc; ; i++, pc += 2) {
3263 // we need an ops[] entry after the last one initialized,
3264 // so do it before end_block checks
3266 opd->op = OP_UNHANDLED;
3268 opd->source = opd->dest = 0;
3272 if (next_is_delay) {
3273 op_flags[i] |= OF_DELAY_OP;
3276 else if (end_block || i >= BLOCK_INSN_LIMIT - 2)
3280 switch ((op & 0xf000) >> 12)
3282 /////////////////////////////////////////////
3289 case 0: // STC SR,Rn 0000nnnn00000010
3292 case 1: // STC GBR,Rn 0000nnnn00010010
3295 case 2: // STC VBR,Rn 0000nnnn00100010
3302 opd->source = BITMASK1(tmp);
3303 opd->dest = BITMASK1(GET_Rn());
3306 CHECK_UNHANDLED_BITS(0xd0, undefined);
3307 // BRAF Rm 0000mmmm00100011
3308 // BSRF Rm 0000mmmm00000011
3309 opd->op = OP_BRANCH_RF;
3311 opd->source = BITMASK1(opd->rm);
3312 opd->dest = BITMASK1(SHR_PC);
3314 opd->dest |= BITMASK1(SHR_PR);
3319 case 0x04: // MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100
3320 case 0x05: // MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101
3321 case 0x06: // MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110
3322 opd->source = BITMASK3(GET_Rm(), SHR_R0, GET_Rn());
3325 // MUL.L Rm,Rn 0000nnnnmmmm0111
3326 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3327 opd->dest = BITMASK1(SHR_MACL);
3331 CHECK_UNHANDLED_BITS(0xf00, undefined);
3334 case 0: // CLRT 0000000000001000
3335 opd->op = OP_SETCLRT;
3336 opd->dest = BITMASK1(SHR_T);
3339 case 1: // SETT 0000000000011000
3340 opd->op = OP_SETCLRT;
3341 opd->dest = BITMASK1(SHR_T);
3344 case 2: // CLRMAC 0000000000101000
3345 opd->dest = BITMASK3(SHR_T, SHR_MACL, SHR_MACH);
3354 case 0: // NOP 0000000000001001
3355 CHECK_UNHANDLED_BITS(0xf00, undefined);
3357 case 1: // DIV0U 0000000000011001
3358 CHECK_UNHANDLED_BITS(0xf00, undefined);
3359 opd->dest = BITMASK2(SHR_SR, SHR_T);
3361 case 2: // MOVT Rn 0000nnnn00101001
3362 opd->source = BITMASK1(SHR_T);
3363 opd->dest = BITMASK1(GET_Rn());
3372 case 0: // STS MACH,Rn 0000nnnn00001010
3375 case 1: // STS MACL,Rn 0000nnnn00011010
3378 case 2: // STS PR,Rn 0000nnnn00101010
3385 opd->source = BITMASK1(tmp);
3386 opd->dest = BITMASK1(GET_Rn());
3389 CHECK_UNHANDLED_BITS(0xf00, undefined);
3392 case 0: // RTS 0000000000001011
3393 opd->op = OP_BRANCH_R;
3395 opd->source = BITMASK1(opd->rm);
3396 opd->dest = BITMASK1(SHR_PC);
3401 case 1: // SLEEP 0000000000011011
3405 case 2: // RTE 0000000000101011
3407 opd->source = BITMASK1(SHR_SP);
3408 opd->dest = BITMASK2(SHR_SR, SHR_PC);
3417 case 0x0c: // MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100
3418 case 0x0d: // MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101
3419 case 0x0e: // MOV.L @(R0,Rm),Rn 0000nnnnmmmm1110
3420 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3421 opd->dest = BITMASK1(GET_Rn());
3423 case 0x0f: // MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111
3424 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3425 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3433 /////////////////////////////////////////////
3435 // MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd
3436 opd->source = BITMASK1(GET_Rm());
3437 opd->source = BITMASK1(GET_Rn());
3438 opd->imm = (op & 0x0f) * 4;
3441 /////////////////////////////////////////////
3445 case 0x00: // MOV.B Rm,@Rn 0010nnnnmmmm0000
3446 case 0x01: // MOV.W Rm,@Rn 0010nnnnmmmm0001
3447 case 0x02: // MOV.L Rm,@Rn 0010nnnnmmmm0010
3448 opd->source = BITMASK1(GET_Rm());
3449 opd->source = BITMASK1(GET_Rn());
3451 case 0x04: // MOV.B Rm,@–Rn 0010nnnnmmmm0100
3452 case 0x05: // MOV.W Rm,@–Rn 0010nnnnmmmm0101
3453 case 0x06: // MOV.L Rm,@–Rn 0010nnnnmmmm0110
3454 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3455 opd->dest = BITMASK1(GET_Rn());
3457 case 0x07: // DIV0S Rm,Rn 0010nnnnmmmm0111
3458 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3459 opd->dest = BITMASK1(SHR_SR);
3461 case 0x08: // TST Rm,Rn 0010nnnnmmmm1000
3462 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3463 opd->dest = BITMASK1(SHR_T);
3465 case 0x09: // AND Rm,Rn 0010nnnnmmmm1001
3466 case 0x0a: // XOR Rm,Rn 0010nnnnmmmm1010
3467 case 0x0b: // OR Rm,Rn 0010nnnnmmmm1011
3468 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3469 opd->dest = BITMASK1(GET_Rn());
3471 case 0x0c: // CMP/STR Rm,Rn 0010nnnnmmmm1100
3472 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3473 opd->dest = BITMASK1(SHR_T);
3475 case 0x0d: // XTRCT Rm,Rn 0010nnnnmmmm1101
3476 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3477 opd->dest = BITMASK1(GET_Rn());
3479 case 0x0e: // MULU.W Rm,Rn 0010nnnnmmmm1110
3480 case 0x0f: // MULS.W Rm,Rn 0010nnnnmmmm1111
3481 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3482 opd->dest = BITMASK1(SHR_MACL);
3489 /////////////////////////////////////////////
3493 case 0x00: // CMP/EQ Rm,Rn 0011nnnnmmmm0000
3494 case 0x02: // CMP/HS Rm,Rn 0011nnnnmmmm0010
3495 case 0x03: // CMP/GE Rm,Rn 0011nnnnmmmm0011
3496 case 0x06: // CMP/HI Rm,Rn 0011nnnnmmmm0110
3497 case 0x07: // CMP/GT Rm,Rn 0011nnnnmmmm0111
3498 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3499 opd->dest = BITMASK1(SHR_T);
3501 case 0x04: // DIV1 Rm,Rn 0011nnnnmmmm0100
3502 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_SR);
3503 opd->dest = BITMASK2(GET_Rn(), SHR_SR);
3505 case 0x05: // DMULU.L Rm,Rn 0011nnnnmmmm0101
3506 case 0x0d: // DMULS.L Rm,Rn 0011nnnnmmmm1101
3507 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3508 opd->dest = BITMASK2(SHR_MACL, SHR_MACH);
3511 case 0x08: // SUB Rm,Rn 0011nnnnmmmm1000
3512 case 0x0c: // ADD Rm,Rn 0011nnnnmmmm1100
3513 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3514 opd->dest = BITMASK1(GET_Rn());
3516 case 0x0a: // SUBC Rm,Rn 0011nnnnmmmm1010
3517 case 0x0e: // ADDC Rm,Rn 0011nnnnmmmm1110
3518 opd->source = BITMASK3(GET_Rm(), GET_Rn(), SHR_T);
3519 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3521 case 0x0b: // SUBV Rm,Rn 0011nnnnmmmm1011
3522 case 0x0f: // ADDV Rm,Rn 0011nnnnmmmm1111
3523 opd->source = BITMASK2(GET_Rm(), GET_Rn());
3524 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3531 /////////////////////////////////////////////
3538 case 0: // SHLL Rn 0100nnnn00000000
3539 case 2: // SHAL Rn 0100nnnn00100000
3540 opd->source = BITMASK1(GET_Rn());
3541 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3543 case 1: // DT Rn 0100nnnn00010000
3544 opd->source = BITMASK1(GET_Rn());
3545 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3554 case 0: // SHLR Rn 0100nnnn00000001
3555 case 2: // SHAR Rn 0100nnnn00100001
3556 opd->source = BITMASK1(GET_Rn());
3557 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3559 case 1: // CMP/PZ Rn 0100nnnn00010001
3560 opd->source = BITMASK1(GET_Rn());
3561 opd->dest = BITMASK1(SHR_T);
3571 case 0x02: // STS.L MACH,@–Rn 0100nnnn00000010
3574 case 0x12: // STS.L MACL,@–Rn 0100nnnn00010010
3577 case 0x22: // STS.L PR,@–Rn 0100nnnn00100010
3580 case 0x03: // STC.L SR,@–Rn 0100nnnn00000011
3584 case 0x13: // STC.L GBR,@–Rn 0100nnnn00010011
3588 case 0x23: // STC.L VBR,@–Rn 0100nnnn00100011
3595 opd->source = BITMASK2(GET_Rn(), tmp);
3596 opd->dest = BITMASK1(GET_Rn());
3602 case 0x04: // ROTL Rn 0100nnnn00000100
3603 case 0x05: // ROTR Rn 0100nnnn00000101
3604 opd->source = BITMASK1(GET_Rn());
3605 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3607 case 0x24: // ROTCL Rn 0100nnnn00100100
3608 case 0x25: // ROTCR Rn 0100nnnn00100101
3609 opd->source = BITMASK2(GET_Rn(), SHR_T);
3610 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3612 case 0x15: // CMP/PL Rn 0100nnnn00010101
3613 opd->source = BITMASK1(GET_Rn());
3614 opd->dest = BITMASK1(SHR_T);
3624 case 0x06: // LDS.L @Rm+,MACH 0100mmmm00000110
3627 case 0x16: // LDS.L @Rm+,MACL 0100mmmm00010110
3630 case 0x26: // LDS.L @Rm+,PR 0100mmmm00100110
3633 case 0x07: // LDC.L @Rm+,SR 0100mmmm00000111
3637 case 0x17: // LDC.L @Rm+,GBR 0100mmmm00010111
3641 case 0x27: // LDC.L @Rm+,VBR 0100mmmm00100111
3648 opd->source = BITMASK1(GET_Rn());
3649 opd->dest = BITMASK2(GET_Rn(), tmp);
3656 // SHLL2 Rn 0100nnnn00001000
3657 // SHLR2 Rn 0100nnnn00001001
3660 // SHLL8 Rn 0100nnnn00011000
3661 // SHLR8 Rn 0100nnnn00011001
3664 // SHLL16 Rn 0100nnnn00101000
3665 // SHLR16 Rn 0100nnnn00101001
3670 opd->source = BITMASK1(GET_Rn());
3671 opd->dest = BITMASK1(GET_Rn());
3676 case 0: // LDS Rm,MACH 0100mmmm00001010
3679 case 1: // LDS Rm,MACL 0100mmmm00011010
3682 case 2: // LDS Rm,PR 0100mmmm00101010
3689 opd->source = BITMASK1(GET_Rn());
3690 opd->dest = BITMASK1(tmp);
3695 case 0: // JSR @Rm 0100mmmm00001011
3696 opd->dest = BITMASK1(SHR_PR);
3697 case 2: // JMP @Rm 0100mmmm00101011
3698 opd->op = OP_BRANCH_R;
3700 opd->source = BITMASK1(opd->rm);
3701 opd->dest |= BITMASK1(SHR_PC);
3706 case 1: // TAS.B @Rn 0100nnnn00011011
3707 opd->source = BITMASK1(GET_Rn());
3708 opd->dest = BITMASK1(SHR_T);
3718 case 0: // LDC Rm,SR 0100mmmm00001110
3721 case 1: // LDC Rm,GBR 0100mmmm00011110
3724 case 2: // LDC Rm,VBR 0100mmmm00101110
3731 opd->source = BITMASK1(GET_Rn());
3732 opd->dest = BITMASK1(tmp);
3735 // MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111
3736 opd->source = BITMASK5(GET_Rm(), GET_Rn(), SHR_SR, SHR_MACL, SHR_MACH);
3737 opd->dest = BITMASK4(GET_Rm(), GET_Rn(), SHR_MACL, SHR_MACH);
3745 /////////////////////////////////////////////
3747 // MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd
3748 opd->source = BITMASK1(GET_Rm());
3749 opd->dest = BITMASK1(GET_Rn());
3750 opd->imm = (op & 0x0f) * 4;
3753 /////////////////////////////////////////////
3757 case 0x04: // MOV.B @Rm+,Rn 0110nnnnmmmm0100
3758 case 0x05: // MOV.W @Rm+,Rn 0110nnnnmmmm0101
3759 case 0x06: // MOV.L @Rm+,Rn 0110nnnnmmmm0110
3760 opd->dest = BITMASK1(GET_Rm());
3761 case 0x00: // MOV.B @Rm,Rn 0110nnnnmmmm0000
3762 case 0x01: // MOV.W @Rm,Rn 0110nnnnmmmm0001
3763 case 0x02: // MOV.L @Rm,Rn 0110nnnnmmmm0010
3764 opd->source = BITMASK1(GET_Rm());
3765 opd->dest |= BITMASK1(GET_Rn());
3767 case 0x0a: // NEGC Rm,Rn 0110nnnnmmmm1010
3768 opd->source = BITMASK2(GET_Rm(), SHR_T);
3769 opd->dest = BITMASK2(GET_Rn(), SHR_T);
3771 case 0x03: // MOV Rm,Rn 0110nnnnmmmm0011
3774 case 0x07: // NOT Rm,Rn 0110nnnnmmmm0111
3775 case 0x08: // SWAP.B Rm,Rn 0110nnnnmmmm1000
3776 case 0x09: // SWAP.W Rm,Rn 0110nnnnmmmm1001
3777 case 0x0b: // NEG Rm,Rn 0110nnnnmmmm1011
3778 case 0x0c: // EXTU.B Rm,Rn 0110nnnnmmmm1100
3779 case 0x0d: // EXTU.W Rm,Rn 0110nnnnmmmm1101
3780 case 0x0e: // EXTS.B Rm,Rn 0110nnnnmmmm1110
3781 case 0x0f: // EXTS.W Rm,Rn 0110nnnnmmmm1111
3783 opd->source = BITMASK1(GET_Rm());
3784 opd->dest = BITMASK1(GET_Rn());
3789 /////////////////////////////////////////////
3791 // ADD #imm,Rn 0111nnnniiiiiiii
3792 opd->source = opd->dest = BITMASK1(GET_Rn());
3793 opd->imm = (int)(signed char)op;
3796 /////////////////////////////////////////////
3798 switch (op & 0x0f00)
3800 case 0x0000: // MOV.B R0,@(disp,Rn) 10000000nnnndddd
3801 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3802 opd->imm = (op & 0x0f);
3804 case 0x0100: // MOV.W R0,@(disp,Rn) 10000001nnnndddd
3805 opd->source = BITMASK2(GET_Rm(), SHR_R0);
3806 opd->imm = (op & 0x0f) * 2;
3808 case 0x0400: // MOV.B @(disp,Rm),R0 10000100mmmmdddd
3809 opd->source = BITMASK1(GET_Rm());
3810 opd->dest = BITMASK1(SHR_R0);
3811 opd->imm = (op & 0x0f);
3813 case 0x0500: // MOV.W @(disp,Rm),R0 10000101mmmmdddd
3814 opd->source = BITMASK1(GET_Rm());
3815 opd->dest = BITMASK1(SHR_R0);
3816 opd->imm = (op & 0x0f) * 2;
3818 case 0x0800: // CMP/EQ #imm,R0 10001000iiiiiiii
3819 opd->source = BITMASK1(SHR_R0);
3820 opd->dest = BITMASK1(SHR_T);
3821 opd->imm = (int)(signed char)op;
3823 case 0x0d00: // BT/S label 10001101dddddddd
3824 case 0x0f00: // BF/S label 10001111dddddddd
3827 case 0x0900: // BT label 10001001dddddddd
3828 case 0x0b00: // BF label 10001011dddddddd
3829 opd->op = (op & 0x0200) ? OP_BRANCH_CF : OP_BRANCH_CT;
3830 opd->source = BITMASK1(SHR_T);
3831 opd->dest = BITMASK1(SHR_PC);
3832 opd->imm = ((signed int)(op << 24) >> 23);
3834 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
3835 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
3842 /////////////////////////////////////////////
3844 // MOV.W @(disp,PC),Rn 1001nnnndddddddd
3845 opd->op = OP_LOAD_POOL;
3847 if (op_flags[i] & OF_DELAY_OP) {
3848 if (ops[i-1].op == OP_BRANCH)
3853 opd->source = BITMASK1(SHR_PC);
3854 opd->dest = BITMASK1(GET_Rn());
3856 opd->imm = tmp + 2 + (op & 0xff) * 2;
3860 /////////////////////////////////////////////
3862 // BSR label 1011dddddddddddd
3863 opd->dest = BITMASK1(SHR_PR);
3865 // BRA label 1010dddddddddddd
3866 opd->op = OP_BRANCH;
3867 opd->dest |= BITMASK1(SHR_PC);
3868 opd->imm = ((signed int)(op << 20) >> 19);
3873 if (base_pc <= opd->imm && opd->imm < base_pc + BLOCK_INSN_LIMIT * 2)
3874 op_flags[(opd->imm - base_pc) / 2] |= OF_BTARGET;
3877 /////////////////////////////////////////////
3879 switch (op & 0x0f00)
3881 case 0x0000: // MOV.B R0,@(disp,GBR) 11000000dddddddd
3882 case 0x0100: // MOV.W R0,@(disp,GBR) 11000001dddddddd
3883 case 0x0200: // MOV.L R0,@(disp,GBR) 11000010dddddddd
3884 opd->source = BITMASK2(SHR_GBR, SHR_R0);
3885 opd->size = (op & 0x300) >> 8;
3886 opd->imm = (op & 0xff) << opd->size;
3888 case 0x0400: // MOV.B @(disp,GBR),R0 11000100dddddddd
3889 case 0x0500: // MOV.W @(disp,GBR),R0 11000101dddddddd
3890 case 0x0600: // MOV.L @(disp,GBR),R0 11000110dddddddd
3891 opd->source = BITMASK1(SHR_GBR);
3892 opd->dest = BITMASK1(SHR_R0);
3893 opd->size = (op & 0x300) >> 8;
3894 opd->imm = (op & 0xff) << opd->size;
3896 case 0x0300: // TRAPA #imm 11000011iiiiiiii
3897 opd->source = BITMASK2(SHR_PC, SHR_SR);
3898 opd->dest = BITMASK1(SHR_PC);
3899 opd->imm = (op & 0xff) * 4;
3901 end_block = 1; // FIXME
3903 case 0x0700: // MOVA @(disp,PC),R0 11000111dddddddd
3906 if (op_flags[i] & OF_DELAY_OP) {
3907 if (ops[i-1].op == OP_BRANCH)
3912 opd->dest = BITMASK1(SHR_R0);
3914 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
3916 case 0x0800: // TST #imm,R0 11001000iiiiiiii
3917 opd->source = BITMASK1(SHR_R0);
3918 opd->dest = BITMASK1(SHR_T);
3919 opd->imm = op & 0xff;
3921 case 0x0900: // AND #imm,R0 11001001iiiiiiii
3922 opd->source = opd->dest = BITMASK1(SHR_R0);
3923 opd->imm = op & 0xff;
3925 case 0x0a00: // XOR #imm,R0 11001010iiiiiiii
3926 opd->source = opd->dest = BITMASK1(SHR_R0);
3927 opd->imm = op & 0xff;
3929 case 0x0b00: // OR #imm,R0 11001011iiiiiiii
3930 opd->source = opd->dest = BITMASK1(SHR_R0);
3931 opd->imm = op & 0xff;
3933 case 0x0c00: // TST.B #imm,@(R0,GBR) 11001100iiiiiiii
3934 opd->source = BITMASK2(SHR_GBR, SHR_R0);
3935 opd->dest = BITMASK1(SHR_T);
3936 opd->imm = op & 0xff;
3939 case 0x0d00: // AND.B #imm,@(R0,GBR) 11001101iiiiiiii
3940 case 0x0e00: // XOR.B #imm,@(R0,GBR) 11001110iiiiiiii
3941 case 0x0f00: // OR.B #imm,@(R0,GBR) 11001111iiiiiiii
3942 opd->source = BITMASK2(SHR_GBR, SHR_R0);
3943 opd->imm = op & 0xff;
3951 /////////////////////////////////////////////
3953 // MOV.L @(disp,PC),Rn 1101nnnndddddddd
3954 opd->op = OP_LOAD_POOL;
3956 if (op_flags[i] & OF_DELAY_OP) {
3957 if (ops[i-1].op == OP_BRANCH)
3962 opd->source = BITMASK1(SHR_PC);
3963 opd->dest = BITMASK1(GET_Rn());
3965 opd->imm = (tmp + 2 + (op & 0xff) * 4) & ~3;
3969 /////////////////////////////////////////////
3971 // MOV #imm,Rn 1110nnnniiiiiiii
3972 opd->dest = BITMASK1(GET_Rn());
3973 opd->imm = (u32)(signed int)(signed char)op;
3978 elprintf(EL_ANOMALY, "%csh2 drc: unhandled op %04x @ %08x",
3979 is_slave ? 's' : 'm', op, pc);
3986 // 2nd pass: some analysis
3987 for (i = 0; i < i_end; i++) {
3990 // propagate T (TODO: DIV0U)
3991 if ((opd->op == OP_SETCLRT && !opd->imm) || opd->op == OP_BRANCH_CT)
3992 op_flags[i + 1] |= OF_T_CLEAR;
3993 else if ((opd->op == OP_SETCLRT && opd->imm) || opd->op == OP_BRANCH_CF)
3994 op_flags[i + 1] |= OF_T_SET;
3996 if ((op_flags[i] & OF_BTARGET) || (opd->dest & BITMASK1(SHR_T)))
3997 op_flags[i] &= ~(OF_T_SET | OF_T_CLEAR);
3999 op_flags[i + 1] |= op_flags[i] & (OF_T_SET | OF_T_CLEAR);
4001 if ((opd->op == OP_BRANCH_CT && (op_flags[i] & OF_T_SET))
4002 || (opd->op == OP_BRANCH_CF && (op_flags[i] & OF_T_CLEAR)))
4004 opd->op = OP_BRANCH;
4007 if (op_flags[i + 1] & OF_DELAY_OP) {
4012 else if (opd->op == OP_LOAD_POOL)
4014 if (opd->imm < end_pc + MAX_LITERAL_OFFSET) {
4015 if (end_literals < opd->imm + opd->size * 2)
4016 end_literals = opd->imm + opd->size * 2;
4020 end_pc = base_pc + i_end * 2;
4021 if (end_literals < end_pc)
4022 end_literals = end_pc;
4024 *end_pc_out = end_pc;
4025 if (end_literals_out != NULL)
4026 *end_literals_out = end_literals;
4029 // vim:shiftwidth=2:ts=2:expandtab