1 /*****************************************************************************
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4 * Portable Hitachi SH-2 (SH7600 family) emulator
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6 * Copyright Juergen Buchmueller <pullmoll@t-online.de>,
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7 * all rights reserved.
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9 * - This source code is released as freeware for non-commercial purposes.
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10 * - You are free to use and redistribute this code in modified or
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11 * unmodified form, provided you list me in the credits.
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12 * - If you modify this source code, you must add a notice to each modified
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13 * source file that it has been changed. If you're a nice person, you
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14 * will clearly mark each change too. :)
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15 * - If you wish to use this for commercial purposes, please contact me at
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16 * pullmoll@t-online.de
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17 * - The author of this copywritten work reserves the right to change the
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18 * terms of its usage and license at any time, including retroactively
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19 * - This entire notice must remain in the source code.
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21 * This work is based on <tiraniddo@hotmail.com> C/C++ implementation of
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22 * the SH-2 CPU core and was adapted to the MAME CPU core requirements.
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23 * Thanks also go to Chuck Mason <chukjr@sundail.net> and Olivier Galibert
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24 * <galibert@pobox.com> for letting me peek into their SEMU code :-)
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26 *****************************************************************************/
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28 /*****************************************************************************
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30 20051129 Mariusz Wojcieszek
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31 - introduced memory_decrypted_read_word() for opcode fetching
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33 20050813 Mariusz Wojcieszek
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34 - fixed 64 bit / 32 bit division in division unit
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36 20031015 O. Galibert
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37 - dma fixes, thanks to sthief
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39 20031013 O. Galibert, A. Giles
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41 - multi-cpu simplifications
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43 20030915 O. Galibert
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44 - fix DMA1 irq vector
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45 - ignore writes to DRCRx
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46 - fix cpu number issues
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47 - fix slave/master recognition
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48 - fix wrong-cpu-in-context problem with the timers
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50 20021020 O. Galibert
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51 - DMA implementation, lightly tested
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52 - delay slot in debugger fixed
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53 - add divide box mirrors
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54 - Nicola-ify the indentation
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55 - Uncrapify sh2_internal_*
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56 - Put back nmi support that had been lost somehow
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59 - Initial SH2 internal timers implementation, based on code by O. Galibert.
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60 Makes music work in galspanic4/s/s2, panic street, cyvern, other SKNS games.
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61 - Fix to external division, thanks to "spice" on the E2J board.
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62 Corrects behavior of s1945ii turret boss.
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64 20020302 Olivier Galibert (galibert@mame.net)
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65 - Fixed interrupt in delay slot
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72 - Fixed external division
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74 20020225 Olivier Galibert (galibert@mame.net)
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75 - Fixed interrupt handling
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77 20010207 Sylvain Glaize (mokona@puupuu.org)
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79 - Bug fix in INLINE void MOVBM(UINT32 m, UINT32 n) (see comment)
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80 - Support of full 32 bit addressing (RB, RW, RL and WB, WW, WL functions)
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81 reason : when the two high bits of the address are set, access is
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82 done directly in the cache data array. The SUPER KANEKO NOVA SYSTEM
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83 sets the stack pointer here, using these addresses as usual RAM access.
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85 No real cache support has been added.
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86 - Read/Write memory format correction (_bew to _bedw) (see also SH2
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87 definition in cpuintrf.c and DasmSH2(..) in sh2dasm.c )
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89 20010623 James Forshaw (TyRaNiD@totalise.net)
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91 - Modified operation of sh2_exception. Done cause mame irq system is stupid, and
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92 doesnt really seem designed for any more than 8 interrupt lines.
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94 20010701 James Forshaw (TyRaNiD@totalise.net)
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96 - Fixed DIV1 operation. Q bit now correctly generated
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98 20020218 Added save states (mokona@puupuu.org)
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100 *****************************************************************************/
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102 //#include "debugger.h"
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104 //#include "sh2comn.h"
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105 #define INLINE static
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107 //CPU_DISASSEMBLE( sh2 );
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111 /* speed up delay loops, bail out of tight loops */
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112 #define BUSY_LOOP_HACKS 1
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116 #define LOG(x) do { if (VERBOSE) logerror x; } while (0)
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122 INLINE UINT8 RB(offs_t A)
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124 if (A >= 0xe0000000)
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125 return sh2_internal_r(sh2->internal, (A & 0x1fc)>>2, 0xff << (((~A) & 3)*8)) >> (((~A) & 3)*8);
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127 if (A >= 0xc0000000)
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128 return memory_read_byte_32be(sh2->program, A);
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130 if (A >= 0x40000000)
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133 return memory_read_byte_32be(sh2->program, A & AM);
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136 INLINE UINT16 RW(offs_t A)
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138 if (A >= 0xe0000000)
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139 return sh2_internal_r(sh2->internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);
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141 if (A >= 0xc0000000)
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142 return memory_read_word_32be(sh2->program, A);
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144 if (A >= 0x40000000)
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147 return memory_read_word_32be(sh2->program, A & AM);
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150 INLINE UINT32 RL(offs_t A)
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152 if (A >= 0xe0000000)
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153 return sh2_internal_r(sh2->internal, (A & 0x1fc)>>2, 0xffffffff);
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155 if (A >= 0xc0000000)
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156 return memory_read_dword_32be(sh2->program, A);
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158 if (A >= 0x40000000)
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161 return memory_read_dword_32be(sh2->program, A & AM);
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164 INLINE void WB(offs_t A, UINT8 V)
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167 if (A >= 0xe0000000)
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169 sh2_internal_w(sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 3)*8), 0xff << (((~A) & 3)*8));
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173 if (A >= 0xc0000000)
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175 memory_write_byte_32be(sh2->program, A,V);
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179 if (A >= 0x40000000)
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182 memory_write_byte_32be(sh2->program, A & AM,V);
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185 INLINE void WW(offs_t A, UINT16 V)
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187 if (A >= 0xe0000000)
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189 sh2_internal_w(sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 2)*8), 0xffff << (((~A) & 2)*8));
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193 if (A >= 0xc0000000)
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195 memory_write_word_32be(sh2->program, A,V);
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199 if (A >= 0x40000000)
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202 memory_write_word_32be(sh2->program, A & AM,V);
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205 INLINE void WL(offs_t A, UINT32 V)
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207 if (A >= 0xe0000000)
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209 sh2_internal_w(sh2->internal, (A & 0x1fc)>>2, V, 0xffffffff);
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213 if (A >= 0xc0000000)
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215 memory_write_dword_32be(sh2->program, A,V);
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219 if (A >= 0x40000000)
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222 memory_write_dword_32be(sh2->program, A & AM,V);
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226 /* code cycles t-bit
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227 * 0011 nnnn mmmm 1100 1 -
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230 INLINE void ADD(UINT32 m, UINT32 n)
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232 sh2->r[n] += sh2->r[m];
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235 /* code cycles t-bit
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236 * 0111 nnnn iiii iiii 1 -
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239 INLINE void ADDI(UINT32 i, UINT32 n)
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241 sh2->r[n] += (INT32)(INT16)(INT8)i;
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244 /* code cycles t-bit
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245 * 0011 nnnn mmmm 1110 1 carry
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248 INLINE void ADDC(UINT32 m, UINT32 n)
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252 tmp1 = sh2->r[n] + sh2->r[m];
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254 sh2->r[n] = tmp1 + (sh2->sr & T);
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259 if (tmp1 > sh2->r[n])
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263 /* code cycles t-bit
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264 * 0011 nnnn mmmm 1111 1 overflow
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267 INLINE void ADDV(UINT32 m, UINT32 n)
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269 INT32 dest, src, ans;
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271 if ((INT32) sh2->r[n] >= 0)
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275 if ((INT32) sh2->r[m] >= 0)
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280 sh2->r[n] += sh2->r[m];
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281 if ((INT32) sh2->r[n] >= 0)
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286 if (src == 0 || src == 2)
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297 /* code cycles t-bit
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298 * 0010 nnnn mmmm 1001 1 -
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301 INLINE void AND(UINT32 m, UINT32 n)
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303 sh2->r[n] &= sh2->r[m];
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307 /* code cycles t-bit
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308 * 1100 1001 iiii iiii 1 -
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311 INLINE void ANDI(UINT32 i)
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316 /* code cycles t-bit
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317 * 1100 1101 iiii iiii 1 -
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318 * AND.B #imm,@(R0,GBR)
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320 INLINE void ANDM(UINT32 i)
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324 sh2->ea = sh2->gbr + sh2->r[0];
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325 temp = i & RB( sh2->ea );
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326 WB( sh2->ea, temp );
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330 /* code cycles t-bit
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331 * 1000 1011 dddd dddd 3/1 -
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334 INLINE void BF(UINT32 d)
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336 if ((sh2->sr & T) == 0)
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338 INT32 disp = ((INT32)d << 24) >> 24;
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339 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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344 /* code cycles t-bit
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345 * 1000 1111 dddd dddd 3/1 -
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348 INLINE void BFS(UINT32 d)
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350 if ((sh2->sr & T) == 0)
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352 INT32 disp = ((INT32)d << 24) >> 24;
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353 sh2->delay = sh2->pc;
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354 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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359 /* code cycles t-bit
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360 * 1010 dddd dddd dddd 2 -
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363 INLINE void BRA(UINT32 d)
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365 INT32 disp = ((INT32)d << 20) >> 20;
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367 #if BUSY_LOOP_HACKS
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370 UINT32 next_opcode = RW(sh2->pc & AM);
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374 if (next_opcode == 0x0009)
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375 sh2_icount %= 3; /* cycles for BRA $ and NOP taken (3) */
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378 sh2->delay = sh2->pc;
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379 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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383 /* code cycles t-bit
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384 * 0000 mmmm 0010 0011 2 -
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387 INLINE void BRAF(UINT32 m)
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389 sh2->delay = sh2->pc;
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390 sh2->pc += sh2->r[m] + 2;
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394 /* code cycles t-bit
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395 * 1011 dddd dddd dddd 2 -
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398 INLINE void BSR(UINT32 d)
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400 INT32 disp = ((INT32)d << 20) >> 20;
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402 sh2->pr = sh2->pc + 2;
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403 sh2->delay = sh2->pc;
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404 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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408 /* code cycles t-bit
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409 * 0000 mmmm 0000 0011 2 -
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412 INLINE void BSRF(UINT32 m)
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414 sh2->pr = sh2->pc + 2;
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415 sh2->delay = sh2->pc;
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416 sh2->pc += sh2->r[m] + 2;
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420 /* code cycles t-bit
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421 * 1000 1001 dddd dddd 3/1 -
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424 INLINE void BT(UINT32 d)
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426 if ((sh2->sr & T) != 0)
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428 INT32 disp = ((INT32)d << 24) >> 24;
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429 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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434 /* code cycles t-bit
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435 * 1000 1101 dddd dddd 2/1 -
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438 INLINE void BTS(UINT32 d)
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440 if ((sh2->sr & T) != 0)
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442 INT32 disp = ((INT32)d << 24) >> 24;
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443 sh2->delay = sh2->pc;
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444 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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449 /* code cycles t-bit
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450 * 0000 0000 0010 1000 1 -
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453 INLINE void CLRMAC(void)
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459 /* code cycles t-bit
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460 * 0000 0000 0000 1000 1 -
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463 INLINE void CLRT(void)
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468 /* code cycles t-bit
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469 * 0011 nnnn mmmm 0000 1 comparison result
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472 INLINE void CMPEQ(UINT32 m, UINT32 n)
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474 if (sh2->r[n] == sh2->r[m])
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480 /* code cycles t-bit
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481 * 0011 nnnn mmmm 0011 1 comparison result
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484 INLINE void CMPGE(UINT32 m, UINT32 n)
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486 if ((INT32) sh2->r[n] >= (INT32) sh2->r[m])
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492 /* code cycles t-bit
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493 * 0011 nnnn mmmm 0111 1 comparison result
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496 INLINE void CMPGT(UINT32 m, UINT32 n)
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498 if ((INT32) sh2->r[n] > (INT32) sh2->r[m])
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504 /* code cycles t-bit
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505 * 0011 nnnn mmmm 0110 1 comparison result
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508 INLINE void CMPHI(UINT32 m, UINT32 n)
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510 if ((UINT32) sh2->r[n] > (UINT32) sh2->r[m])
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516 /* code cycles t-bit
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517 * 0011 nnnn mmmm 0010 1 comparison result
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520 INLINE void CMPHS(UINT32 m, UINT32 n)
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522 if ((UINT32) sh2->r[n] >= (UINT32) sh2->r[m])
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529 /* code cycles t-bit
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530 * 0100 nnnn 0001 0101 1 comparison result
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533 INLINE void CMPPL(UINT32 n)
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535 if ((INT32) sh2->r[n] > 0)
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541 /* code cycles t-bit
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542 * 0100 nnnn 0001 0001 1 comparison result
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545 INLINE void CMPPZ(UINT32 n)
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547 if ((INT32) sh2->r[n] >= 0)
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553 /* code cycles t-bit
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554 * 0010 nnnn mmmm 1100 1 comparison result
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557 INLINE void CMPSTR(UINT32 m, UINT32 n)
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560 INT32 HH, HL, LH, LL;
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561 temp = sh2->r[n] ^ sh2->r[m];
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562 HH = (temp >> 24) & 0xff;
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563 HL = (temp >> 16) & 0xff;
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564 LH = (temp >> 8) & 0xff;
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566 if (HH && HL && LH && LL)
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573 /* code cycles t-bit
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574 * 1000 1000 iiii iiii 1 comparison result
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577 INLINE void CMPIM(UINT32 i)
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579 UINT32 imm = (UINT32)(INT32)(INT16)(INT8)i;
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581 if (sh2->r[0] == imm)
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587 /* code cycles t-bit
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588 * 0010 nnnn mmmm 0111 1 calculation result
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591 INLINE void DIV0S(UINT32 m, UINT32 n)
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593 if ((sh2->r[n] & 0x80000000) == 0)
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597 if ((sh2->r[m] & 0x80000000) == 0)
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601 if ((sh2->r[m] ^ sh2->r[n]) & 0x80000000)
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607 /* code cycles t-bit
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608 * 0000 0000 0001 1001 1 0
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611 INLINE void DIV0U(void)
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613 sh2->sr &= ~(M | Q | T);
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616 /* code cycles t-bit
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617 * 0011 nnnn mmmm 0100 1 calculation result
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620 INLINE void DIV1(UINT32 m, UINT32 n)
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625 old_q = sh2->sr & Q;
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626 if (0x80000000 & sh2->r[n])
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631 sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);
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635 if (!(sh2->sr & M))
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638 sh2->r[n] -= sh2->r[m];
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640 if(sh2->r[n] > tmp0)
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645 if(sh2->r[n] > tmp0)
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653 sh2->r[n] += sh2->r[m];
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656 if(sh2->r[n] < tmp0)
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663 if(sh2->r[n] < tmp0)
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672 if (!(sh2->sr & M))
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675 sh2->r[n] += sh2->r[m];
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677 if(sh2->r[n] < tmp0)
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682 if(sh2->r[n] < tmp0)
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690 sh2->r[n] -= sh2->r[m];
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692 if(sh2->r[n] > tmp0)
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697 if(sh2->r[n] > tmp0)
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704 tmp0 = (sh2->sr & (Q | M));
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705 if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */
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711 /* DMULS.L Rm,Rn */
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712 INLINE void DMULS(UINT32 m, UINT32 n)
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714 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
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715 UINT32 temp0, temp1, temp2, temp3;
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716 INT32 tempm, tempn, fnLmL;
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718 tempn = (INT32) sh2->r[n];
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719 tempm = (INT32) sh2->r[m];
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724 if ((INT32) (sh2->r[n] ^ sh2->r[m]) < 0)
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728 temp1 = (UINT32) tempn;
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729 temp2 = (UINT32) tempm;
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730 RnL = temp1 & 0x0000ffff;
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731 RnH = (temp1 >> 16) & 0x0000ffff;
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732 RmL = temp2 & 0x0000ffff;
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733 RmH = (temp2 >> 16) & 0x0000ffff;
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739 Res1 = temp1 + temp2;
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741 Res2 += 0x00010000;
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742 temp1 = (Res1 << 16) & 0xffff0000;
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743 Res0 = temp0 + temp1;
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746 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
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753 Res0 = (~Res0) + 1;
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760 /* DMULU.L Rm,Rn */
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761 INLINE void DMULU(UINT32 m, UINT32 n)
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763 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
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764 UINT32 temp0, temp1, temp2, temp3;
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766 RnL = sh2->r[n] & 0x0000ffff;
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767 RnH = (sh2->r[n] >> 16) & 0x0000ffff;
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768 RmL = sh2->r[m] & 0x0000ffff;
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769 RmH = (sh2->r[m] >> 16) & 0x0000ffff;
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775 Res1 = temp1 + temp2;
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777 Res2 += 0x00010000;
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778 temp1 = (Res1 << 16) & 0xffff0000;
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779 Res0 = temp0 + temp1;
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782 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
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789 INLINE void DT(UINT32 n)
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792 if (sh2->r[n] == 0)
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796 #if BUSY_LOOP_HACKS
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798 UINT32 next_opcode = RW(sh2->pc & AM);
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802 if (next_opcode == 0x8bfd)
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804 while (sh2->r[n] > 1 && sh2_icount > 4)
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807 sh2_icount -= 4; /* cycles for DT (1) and BF taken (3) */
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815 INLINE void EXTSB(UINT32 m, UINT32 n)
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817 sh2->r[n] = ((INT32)sh2->r[m] << 24) >> 24;
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821 INLINE void EXTSW(UINT32 m, UINT32 n)
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823 sh2->r[n] = ((INT32)sh2->r[m] << 16) >> 16;
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827 INLINE void EXTUB(UINT32 m, UINT32 n)
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829 sh2->r[n] = sh2->r[m] & 0x000000ff;
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833 INLINE void EXTUW(UINT32 m, UINT32 n)
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835 sh2->r[n] = sh2->r[m] & 0x0000ffff;
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839 INLINE void JMP(UINT32 m)
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841 sh2->delay = sh2->pc;
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842 sh2->pc = sh2->ea = sh2->r[m];
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846 INLINE void JSR(UINT32 m)
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848 sh2->delay = sh2->pc;
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849 sh2->pr = sh2->pc + 2;
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850 sh2->pc = sh2->ea = sh2->r[m];
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856 INLINE void LDCSR(UINT32 m)
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859 sh2->sr |= sh2->r[m] & FLAGS;
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864 INLINE void LDCGBR(UINT32 m)
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866 sh2->gbr = sh2->r[m];
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870 INLINE void LDCVBR(UINT32 m)
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872 sh2->vbr = sh2->r[m];
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875 /* LDC.L @Rm+,SR */
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876 INLINE void LDCMSR(UINT32 m)
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878 sh2->ea = sh2->r[m];
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880 sh2->sr |= RL( sh2->ea ) & FLAGS;
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886 /* LDC.L @Rm+,GBR */
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887 INLINE void LDCMGBR(UINT32 m)
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889 sh2->ea = sh2->r[m];
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890 sh2->gbr = RL( sh2->ea );
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895 /* LDC.L @Rm+,VBR */
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896 INLINE void LDCMVBR(UINT32 m)
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898 sh2->ea = sh2->r[m];
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899 sh2->vbr = RL( sh2->ea );
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905 INLINE void LDSMACH(UINT32 m)
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907 sh2->mach = sh2->r[m];
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911 INLINE void LDSMACL(UINT32 m)
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913 sh2->macl = sh2->r[m];
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917 INLINE void LDSPR(UINT32 m)
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919 sh2->pr = sh2->r[m];
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922 /* LDS.L @Rm+,MACH */
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923 INLINE void LDSMMACH(UINT32 m)
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925 sh2->ea = sh2->r[m];
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926 sh2->mach = RL( sh2->ea );
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930 /* LDS.L @Rm+,MACL */
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931 INLINE void LDSMMACL(UINT32 m)
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933 sh2->ea = sh2->r[m];
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934 sh2->macl = RL( sh2->ea );
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938 /* LDS.L @Rm+,PR */
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939 INLINE void LDSMPR(UINT32 m)
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941 sh2->ea = sh2->r[m];
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942 sh2->pr = RL( sh2->ea );
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946 /* MAC.L @Rm+,@Rn+ */
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947 INLINE void MAC_L(UINT32 m, UINT32 n)
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949 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
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950 UINT32 temp0, temp1, temp2, temp3;
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951 INT32 tempm, tempn, fnLmL;
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953 tempn = (INT32) RL( sh2->r[n] );
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955 tempm = (INT32) RL( sh2->r[m] );
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957 if ((INT32) (tempn ^ tempm) < 0)
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965 temp1 = (UINT32) tempn;
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966 temp2 = (UINT32) tempm;
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967 RnL = temp1 & 0x0000ffff;
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968 RnH = (temp1 >> 16) & 0x0000ffff;
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969 RmL = temp2 & 0x0000ffff;
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970 RmH = (temp2 >> 16) & 0x0000ffff;
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976 Res1 = temp1 + temp2;
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978 Res2 += 0x00010000;
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979 temp1 = (Res1 << 16) & 0xffff0000;
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980 Res0 = temp0 + temp1;
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983 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
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990 Res0 = (~Res0) + 1;
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994 Res0 = sh2->macl + Res0;
\r
995 if (sh2->macl > Res0)
\r
997 Res2 += (sh2->mach & 0x0000ffff);
\r
998 if (((INT32) Res2 < 0) && (Res2 < 0xffff8000))
\r
1000 Res2 = 0x00008000;
\r
1001 Res0 = 0x00000000;
\r
1003 else if (((INT32) Res2 > 0) && (Res2 > 0x00007fff))
\r
1005 Res2 = 0x00007fff;
\r
1006 Res0 = 0xffffffff;
\r
1013 Res0 = sh2->macl + Res0;
\r
1014 if (sh2->macl > Res0)
\r
1016 Res2 += sh2->mach;
\r
1023 /* MAC.W @Rm+,@Rn+ */
\r
1024 INLINE void MAC_W(UINT32 m, UINT32 n)
\r
1026 INT32 tempm, tempn, dest, src, ans;
\r
1029 tempn = (INT32) RW( sh2->r[n] );
\r
1031 tempm = (INT32) RW( sh2->r[m] );
\r
1033 templ = sh2->macl;
\r
1034 tempm = ((INT32) (short) tempn * (INT32) (short) tempm);
\r
1035 if ((INT32) sh2->macl >= 0)
\r
1039 if ((INT32) tempm >= 0)
\r
1047 tempn = 0xffffffff;
\r
1050 sh2->macl += tempm;
\r
1051 if ((INT32) sh2->macl >= 0)
\r
1061 sh2->macl = 0x7fffffff;
\r
1063 sh2->macl = 0x80000000;
\r
1068 sh2->mach += tempn;
\r
1069 if (templ > sh2->macl)
\r
1076 INLINE void MOV(UINT32 m, UINT32 n)
\r
1078 sh2->r[n] = sh2->r[m];
\r
1081 /* MOV.B Rm,@Rn */
\r
1082 INLINE void MOVBS(UINT32 m, UINT32 n)
\r
1084 sh2->ea = sh2->r[n];
\r
1085 WB( sh2->ea, sh2->r[m] & 0x000000ff);
\r
1088 /* MOV.W Rm,@Rn */
\r
1089 INLINE void MOVWS(UINT32 m, UINT32 n)
\r
1091 sh2->ea = sh2->r[n];
\r
1092 WW( sh2->ea, sh2->r[m] & 0x0000ffff);
\r
1095 /* MOV.L Rm,@Rn */
\r
1096 INLINE void MOVLS(UINT32 m, UINT32 n)
\r
1098 sh2->ea = sh2->r[n];
\r
1099 WL( sh2->ea, sh2->r[m] );
\r
1102 /* MOV.B @Rm,Rn */
\r
1103 INLINE void MOVBL(UINT32 m, UINT32 n)
\r
1105 sh2->ea = sh2->r[m];
\r
1106 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );
\r
1109 /* MOV.W @Rm,Rn */
\r
1110 INLINE void MOVWL(UINT32 m, UINT32 n)
\r
1112 sh2->ea = sh2->r[m];
\r
1113 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->ea );
\r
1116 /* MOV.L @Rm,Rn */
\r
1117 INLINE void MOVLL(UINT32 m, UINT32 n)
\r
1119 sh2->ea = sh2->r[m];
\r
1120 sh2->r[n] = RL( sh2->ea );
\r
1123 /* MOV.B Rm,@-Rn */
\r
1124 INLINE void MOVBM(UINT32 m, UINT32 n)
\r
1126 /* SMG : bug fix, was reading sh2->r[n] */
\r
1127 UINT32 data = sh2->r[m] & 0x000000ff;
\r
1130 WB( sh2->r[n], data );
\r
1133 /* MOV.W Rm,@-Rn */
\r
1134 INLINE void MOVWM(UINT32 m, UINT32 n)
\r
1136 UINT32 data = sh2->r[m] & 0x0000ffff;
\r
1139 WW( sh2->r[n], data );
\r
1142 /* MOV.L Rm,@-Rn */
\r
1143 INLINE void MOVLM(UINT32 m, UINT32 n)
\r
1145 UINT32 data = sh2->r[m];
\r
1148 WL( sh2->r[n], data );
\r
1151 /* MOV.B @Rm+,Rn */
\r
1152 INLINE void MOVBP(UINT32 m, UINT32 n)
\r
1154 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->r[m] );
\r
1159 /* MOV.W @Rm+,Rn */
\r
1160 INLINE void MOVWP(UINT32 m, UINT32 n)
\r
1162 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->r[m] );
\r
1167 /* MOV.L @Rm+,Rn */
\r
1168 INLINE void MOVLP(UINT32 m, UINT32 n)
\r
1170 sh2->r[n] = RL( sh2->r[m] );
\r
1175 /* MOV.B Rm,@(R0,Rn) */
\r
1176 INLINE void MOVBS0(UINT32 m, UINT32 n)
\r
1178 sh2->ea = sh2->r[n] + sh2->r[0];
\r
1179 WB( sh2->ea, sh2->r[m] & 0x000000ff );
\r
1182 /* MOV.W Rm,@(R0,Rn) */
\r
1183 INLINE void MOVWS0(UINT32 m, UINT32 n)
\r
1185 sh2->ea = sh2->r[n] + sh2->r[0];
\r
1186 WW( sh2->ea, sh2->r[m] & 0x0000ffff );
\r
1189 /* MOV.L Rm,@(R0,Rn) */
\r
1190 INLINE void MOVLS0(UINT32 m, UINT32 n)
\r
1192 sh2->ea = sh2->r[n] + sh2->r[0];
\r
1193 WL( sh2->ea, sh2->r[m] );
\r
1196 /* MOV.B @(R0,Rm),Rn */
\r
1197 INLINE void MOVBL0(UINT32 m, UINT32 n)
\r
1199 sh2->ea = sh2->r[m] + sh2->r[0];
\r
1200 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );
\r
1203 /* MOV.W @(R0,Rm),Rn */
\r
1204 INLINE void MOVWL0(UINT32 m, UINT32 n)
\r
1206 sh2->ea = sh2->r[m] + sh2->r[0];
\r
1207 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->ea );
\r
1210 /* MOV.L @(R0,Rm),Rn */
\r
1211 INLINE void MOVLL0(UINT32 m, UINT32 n)
\r
1213 sh2->ea = sh2->r[m] + sh2->r[0];
\r
1214 sh2->r[n] = RL( sh2->ea );
\r
1218 INLINE void MOVI(UINT32 i, UINT32 n)
\r
1220 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) i;
\r
1223 /* MOV.W @(disp8,PC),Rn */
\r
1224 INLINE void MOVWI(UINT32 d, UINT32 n)
\r
1226 UINT32 disp = d & 0xff;
\r
1227 sh2->ea = sh2->pc + disp * 2 + 2;
\r
1228 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2->ea );
\r
1231 /* MOV.L @(disp8,PC),Rn */
\r
1232 INLINE void MOVLI(UINT32 d, UINT32 n)
\r
1234 UINT32 disp = d & 0xff;
\r
1235 sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;
\r
1236 sh2->r[n] = RL( sh2->ea );
\r
1239 /* MOV.B @(disp8,GBR),R0 */
\r
1240 INLINE void MOVBLG(UINT32 d)
\r
1242 UINT32 disp = d & 0xff;
\r
1243 sh2->ea = sh2->gbr + disp;
\r
1244 sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );
\r
1247 /* MOV.W @(disp8,GBR),R0 */
\r
1248 INLINE void MOVWLG(UINT32 d)
\r
1250 UINT32 disp = d & 0xff;
\r
1251 sh2->ea = sh2->gbr + disp * 2;
\r
1252 sh2->r[0] = (INT32)(INT16) RW( sh2->ea );
\r
1255 /* MOV.L @(disp8,GBR),R0 */
\r
1256 INLINE void MOVLLG(UINT32 d)
\r
1258 UINT32 disp = d & 0xff;
\r
1259 sh2->ea = sh2->gbr + disp * 4;
\r
1260 sh2->r[0] = RL( sh2->ea );
\r
1263 /* MOV.B R0,@(disp8,GBR) */
\r
1264 INLINE void MOVBSG(UINT32 d)
\r
1266 UINT32 disp = d & 0xff;
\r
1267 sh2->ea = sh2->gbr + disp;
\r
1268 WB( sh2->ea, sh2->r[0] & 0x000000ff );
\r
1271 /* MOV.W R0,@(disp8,GBR) */
\r
1272 INLINE void MOVWSG(UINT32 d)
\r
1274 UINT32 disp = d & 0xff;
\r
1275 sh2->ea = sh2->gbr + disp * 2;
\r
1276 WW( sh2->ea, sh2->r[0] & 0x0000ffff );
\r
1279 /* MOV.L R0,@(disp8,GBR) */
\r
1280 INLINE void MOVLSG(UINT32 d)
\r
1282 UINT32 disp = d & 0xff;
\r
1283 sh2->ea = sh2->gbr + disp * 4;
\r
1284 WL( sh2->ea, sh2->r[0] );
\r
1287 /* MOV.B R0,@(disp4,Rn) */
\r
1288 INLINE void MOVBS4(UINT32 d, UINT32 n)
\r
1290 UINT32 disp = d & 0x0f;
\r
1291 sh2->ea = sh2->r[n] + disp;
\r
1292 WB( sh2->ea, sh2->r[0] & 0x000000ff );
\r
1295 /* MOV.W R0,@(disp4,Rn) */
\r
1296 INLINE void MOVWS4(UINT32 d, UINT32 n)
\r
1298 UINT32 disp = d & 0x0f;
\r
1299 sh2->ea = sh2->r[n] + disp * 2;
\r
1300 WW( sh2->ea, sh2->r[0] & 0x0000ffff );
\r
1303 /* MOV.L Rm,@(disp4,Rn) */
\r
1304 INLINE void MOVLS4(UINT32 m, UINT32 d, UINT32 n)
\r
1306 UINT32 disp = d & 0x0f;
\r
1307 sh2->ea = sh2->r[n] + disp * 4;
\r
1308 WL( sh2->ea, sh2->r[m] );
\r
1311 /* MOV.B @(disp4,Rm),R0 */
\r
1312 INLINE void MOVBL4(UINT32 m, UINT32 d)
\r
1314 UINT32 disp = d & 0x0f;
\r
1315 sh2->ea = sh2->r[m] + disp;
\r
1316 sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2->ea );
\r
1319 /* MOV.W @(disp4,Rm),R0 */
\r
1320 INLINE void MOVWL4(UINT32 m, UINT32 d)
\r
1322 UINT32 disp = d & 0x0f;
\r
1323 sh2->ea = sh2->r[m] + disp * 2;
\r
1324 sh2->r[0] = (UINT32)(INT32)(INT16) RW( sh2->ea );
\r
1327 /* MOV.L @(disp4,Rm),Rn */
\r
1328 INLINE void MOVLL4(UINT32 m, UINT32 d, UINT32 n)
\r
1330 UINT32 disp = d & 0x0f;
\r
1331 sh2->ea = sh2->r[m] + disp * 4;
\r
1332 sh2->r[n] = RL( sh2->ea );
\r
1335 /* MOVA @(disp8,PC),R0 */
\r
1336 INLINE void MOVA(UINT32 d)
\r
1338 UINT32 disp = d & 0xff;
\r
1339 sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;
\r
1340 sh2->r[0] = sh2->ea;
\r
1344 INLINE void MOVT(UINT32 n)
\r
1346 sh2->r[n] = sh2->sr & T;
\r
1350 INLINE void MULL(UINT32 m, UINT32 n)
\r
1352 sh2->macl = sh2->r[n] * sh2->r[m];
\r
1357 INLINE void MULS(UINT32 m, UINT32 n)
\r
1359 sh2->macl = (INT16) sh2->r[n] * (INT16) sh2->r[m];
\r
1363 INLINE void MULU(UINT32 m, UINT32 n)
\r
1365 sh2->macl = (UINT16) sh2->r[n] * (UINT16) sh2->r[m];
\r
1369 INLINE void NEG(UINT32 m, UINT32 n)
\r
1371 sh2->r[n] = 0 - sh2->r[m];
\r
1375 INLINE void NEGC(UINT32 m, UINT32 n)
\r
1380 sh2->r[n] = -temp - (sh2->sr & T);
\r
1381 if (temp || (sh2->sr & T))
\r
1388 INLINE void NOP(void)
\r
1393 INLINE void NOT(UINT32 m, UINT32 n)
\r
1395 sh2->r[n] = ~sh2->r[m];
\r
1399 INLINE void OR(UINT32 m, UINT32 n)
\r
1401 sh2->r[n] |= sh2->r[m];
\r
1405 INLINE void ORI(UINT32 i)
\r
1411 /* OR.B #imm,@(R0,GBR) */
\r
1412 INLINE void ORM(UINT32 i)
\r
1416 sh2->ea = sh2->gbr + sh2->r[0];
\r
1417 temp = RB( sh2->ea );
\r
1419 WB( sh2->ea, temp );
\r
1423 INLINE void ROTCL(UINT32 n)
\r
1427 temp = (sh2->r[n] >> 31) & T;
\r
1428 sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);
\r
1429 sh2->sr = (sh2->sr & ~T) | temp;
\r
1433 INLINE void ROTCR(UINT32 n)
\r
1436 temp = (sh2->sr & T) << 31;
\r
1437 if (sh2->r[n] & T)
\r
1441 sh2->r[n] = (sh2->r[n] >> 1) | temp;
\r
1445 INLINE void ROTL(UINT32 n)
\r
1447 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
\r
1448 sh2->r[n] = (sh2->r[n] << 1) | (sh2->r[n] >> 31);
\r
1452 INLINE void ROTR(UINT32 n)
\r
1454 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
\r
1455 sh2->r[n] = (sh2->r[n] >> 1) | (sh2->r[n] << 31);
\r
1459 INLINE void RTE(void)
\r
1461 sh2->ea = sh2->r[15];
\r
1462 sh2->delay = sh2->pc;
\r
1463 sh2->pc = RL( sh2->ea );
\r
1465 sh2->ea = sh2->r[15];
\r
1466 sh2->sr &= ~0xfff;
\r
1467 sh2->sr |= RL( sh2->ea ) & FLAGS;
\r
1470 sh2->test_irq = 1;
\r
1474 INLINE void RTS(void)
\r
1476 sh2->delay = sh2->pc;
\r
1477 sh2->pc = sh2->ea = sh2->pr;
\r
1482 INLINE void SETT(void)
\r
1487 /* SHAL Rn (same as SHLL) */
\r
1488 INLINE void SHAL(UINT32 n)
\r
1490 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
\r
1495 INLINE void SHAR(UINT32 n)
\r
1497 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
\r
1498 sh2->r[n] = (UINT32)((INT32)sh2->r[n] >> 1);
\r
1501 /* SHLL Rn (same as SHAL) */
\r
1502 INLINE void SHLL(UINT32 n)
\r
1504 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
\r
1509 INLINE void SHLL2(UINT32 n)
\r
1515 INLINE void SHLL8(UINT32 n)
\r
1521 INLINE void SHLL16(UINT32 n)
\r
1527 INLINE void SHLR(UINT32 n)
\r
1529 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
\r
1534 INLINE void SHLR2(UINT32 n)
\r
1540 INLINE void SHLR8(UINT32 n)
\r
1546 INLINE void SHLR16(UINT32 n)
\r
1552 INLINE void SLEEP(void)
\r
1556 /* Wait_for_exception; */
\r
1560 INLINE void STCSR(UINT32 n)
\r
1562 sh2->r[n] = sh2->sr & FLAGS;
\r
1566 INLINE void STCGBR(UINT32 n)
\r
1568 sh2->r[n] = sh2->gbr;
\r
1572 INLINE void STCVBR(UINT32 n)
\r
1574 sh2->r[n] = sh2->vbr;
\r
1577 /* STC.L SR,@-Rn */
\r
1578 INLINE void STCMSR(UINT32 n)
\r
1581 sh2->ea = sh2->r[n];
\r
1582 WL( sh2->ea, sh2->sr & FLAGS );
\r
1586 /* STC.L GBR,@-Rn */
\r
1587 INLINE void STCMGBR(UINT32 n)
\r
1590 sh2->ea = sh2->r[n];
\r
1591 WL( sh2->ea, sh2->gbr );
\r
1595 /* STC.L VBR,@-Rn */
\r
1596 INLINE void STCMVBR(UINT32 n)
\r
1599 sh2->ea = sh2->r[n];
\r
1600 WL( sh2->ea, sh2->vbr );
\r
1605 INLINE void STSMACH(UINT32 n)
\r
1607 sh2->r[n] = sh2->mach;
\r
1611 INLINE void STSMACL(UINT32 n)
\r
1613 sh2->r[n] = sh2->macl;
\r
1617 INLINE void STSPR(UINT32 n)
\r
1619 sh2->r[n] = sh2->pr;
\r
1622 /* STS.L MACH,@-Rn */
\r
1623 INLINE void STSMMACH(UINT32 n)
\r
1626 sh2->ea = sh2->r[n];
\r
1627 WL( sh2->ea, sh2->mach );
\r
1630 /* STS.L MACL,@-Rn */
\r
1631 INLINE void STSMMACL(UINT32 n)
\r
1634 sh2->ea = sh2->r[n];
\r
1635 WL( sh2->ea, sh2->macl );
\r
1638 /* STS.L PR,@-Rn */
\r
1639 INLINE void STSMPR(UINT32 n)
\r
1642 sh2->ea = sh2->r[n];
\r
1643 WL( sh2->ea, sh2->pr );
\r
1647 INLINE void SUB(UINT32 m, UINT32 n)
\r
1649 sh2->r[n] -= sh2->r[m];
\r
1653 INLINE void SUBC(UINT32 m, UINT32 n)
\r
1655 UINT32 tmp0, tmp1;
\r
1657 tmp1 = sh2->r[n] - sh2->r[m];
\r
1659 sh2->r[n] = tmp1 - (sh2->sr & T);
\r
1664 if (tmp1 < sh2->r[n])
\r
1669 INLINE void SUBV(UINT32 m, UINT32 n)
\r
1671 INT32 dest, src, ans;
\r
1673 if ((INT32) sh2->r[n] >= 0)
\r
1677 if ((INT32) sh2->r[m] >= 0)
\r
1682 sh2->r[n] -= sh2->r[m];
\r
1683 if ((INT32) sh2->r[n] >= 0)
\r
1699 /* SWAP.B Rm,Rn */
\r
1700 INLINE void SWAPB(UINT32 m, UINT32 n)
\r
1702 UINT32 temp0, temp1;
\r
1704 temp0 = sh2->r[m] & 0xffff0000;
\r
1705 temp1 = (sh2->r[m] & 0x000000ff) << 8;
\r
1706 sh2->r[n] = (sh2->r[m] >> 8) & 0x000000ff;
\r
1707 sh2->r[n] = sh2->r[n] | temp1 | temp0;
\r
1710 /* SWAP.W Rm,Rn */
\r
1711 INLINE void SWAPW(UINT32 m, UINT32 n)
\r
1715 temp = (sh2->r[m] >> 16) & 0x0000ffff;
\r
1716 sh2->r[n] = (sh2->r[m] << 16) | temp;
\r
1720 INLINE void TAS(UINT32 n)
\r
1723 sh2->ea = sh2->r[n];
\r
1724 /* Bus Lock enable */
\r
1725 temp = RB( sh2->ea );
\r
1731 /* Bus Lock disable */
\r
1732 WB( sh2->ea, temp );
\r
1737 INLINE void TRAPA(UINT32 i)
\r
1739 UINT32 imm = i & 0xff;
\r
1741 sh2->ea = sh2->vbr + imm * 4;
\r
1744 WL( sh2->r[15], sh2->sr & FLAGS );
\r
1746 WL( sh2->r[15], sh2->pc );
\r
1748 sh2->pc = RL( sh2->ea );
\r
1754 INLINE void TST(UINT32 m, UINT32 n)
\r
1756 if ((sh2->r[n] & sh2->r[m]) == 0)
\r
1763 INLINE void TSTI(UINT32 i)
\r
1765 UINT32 imm = i & 0xff;
\r
1767 if ((imm & sh2->r[0]) == 0)
\r
1773 /* TST.B #imm,@(R0,GBR) */
\r
1774 INLINE void TSTM(UINT32 i)
\r
1776 UINT32 imm = i & 0xff;
\r
1778 sh2->ea = sh2->gbr + sh2->r[0];
\r
1779 if ((imm & RB( sh2->ea )) == 0)
\r
1787 INLINE void XOR(UINT32 m, UINT32 n)
\r
1789 sh2->r[n] ^= sh2->r[m];
\r
1793 INLINE void XORI(UINT32 i)
\r
1795 UINT32 imm = i & 0xff;
\r
1799 /* XOR.B #imm,@(R0,GBR) */
\r
1800 INLINE void XORM(UINT32 i)
\r
1802 UINT32 imm = i & 0xff;
\r
1805 sh2->ea = sh2->gbr + sh2->r[0];
\r
1806 temp = RB( sh2->ea );
\r
1808 WB( sh2->ea, temp );
\r
1813 INLINE void XTRCT(UINT32 m, UINT32 n)
\r
1817 temp = (sh2->r[m] << 16) & 0xffff0000;
\r
1818 sh2->r[n] = (sh2->r[n] >> 16) & 0x0000ffff;
\r
1819 sh2->r[n] |= temp;
\r
1822 /*****************************************************************************
\r
1823 * OPCODE DISPATCHERS
\r
1824 *****************************************************************************/
\r
1826 INLINE void op0000(UINT16 opcode)
\r
1828 switch (opcode & 0x3F)
\r
1830 case 0x00: NOP(); rlog(0); break;
\r
1831 case 0x01: NOP(); rlog(0); break;
\r
1832 case 0x02: STCSR(Rn); rlog(LRN); break;
\r
1833 case 0x03: BSRF(Rn); rlog(LRN); break;
\r
1834 case 0x04: MOVBS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1835 case 0x05: MOVWS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1836 case 0x06: MOVLS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1837 case 0x07: MULL(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1838 case 0x08: CLRT(); rlog(0); break;
\r
1839 case 0x09: NOP(); rlog(0); break;
\r
1840 case 0x0a: STSMACH(Rn); rlog(LRN); rlog1(SHR_MACH); break;
\r
1841 case 0x0b: RTS(); rlog(0); rlog1(SHR_PR); break;
\r
1842 case 0x0c: MOVBL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1843 case 0x0d: MOVWL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1844 case 0x0e: MOVLL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1845 case 0x0f: MAC_L(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1847 case 0x10: NOP(); rlog(0); break;
\r
1848 case 0x11: NOP(); rlog(0); break;
\r
1849 case 0x12: STCGBR(Rn); rlog(LRN); rlog1(SHR_GBR); break;
\r
1850 case 0x13: NOP(); rlog(0); break;
\r
1851 case 0x14: MOVBS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1852 case 0x15: MOVWS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1853 case 0x16: MOVLS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1854 case 0x17: MULL(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1855 case 0x18: SETT(); rlog(0); break;
\r
1856 case 0x19: DIV0U(); rlog(0); break;
\r
1857 case 0x1a: STSMACL(Rn); rlog(LRN); rlog1(SHR_MACL); break;
\r
1858 case 0x1b: SLEEP(); rlog(0); break;
\r
1859 case 0x1c: MOVBL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1860 case 0x1d: MOVWL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1861 case 0x1e: MOVLL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1862 case 0x1f: MAC_L(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1864 case 0x20: NOP(); rlog(0); break;
\r
1865 case 0x21: NOP(); rlog(0); break;
\r
1866 case 0x22: STCVBR(Rn); rlog(LRN); rlog1(SHR_VBR); break;
\r
1867 case 0x23: BRAF(Rn); rlog(LRN); break;
\r
1868 case 0x24: MOVBS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1869 case 0x25: MOVWS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1870 case 0x26: MOVLS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1871 case 0x27: MULL(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1872 case 0x28: CLRMAC(); rlog(0); rlog2(SHR_MACL,SHR_MACH); break;
\r
1873 case 0x29: MOVT(Rn); rlog(LRN); break;
\r
1874 case 0x2a: STSPR(Rn); rlog(LRN); rlog1(SHR_PR); break;
\r
1875 case 0x2b: RTE(); rlog(0); break;
\r
1876 case 0x2c: MOVBL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1877 case 0x2d: MOVWL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1878 case 0x2e: MOVLL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1879 case 0x2f: MAC_L(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1881 case 0x30: NOP(); rlog(0); break;
\r
1882 case 0x31: NOP(); rlog(0); break;
\r
1883 case 0x32: NOP(); rlog(0); break;
\r
1884 case 0x33: NOP(); rlog(0); break;
\r
1885 case 0x34: MOVBS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1886 case 0x35: MOVWS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1887 case 0x36: MOVLS0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1888 case 0x37: MULL(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1889 case 0x38: NOP(); rlog(0); break;
\r
1890 case 0x39: NOP(); rlog(0); break;
\r
1891 case 0x3c: MOVBL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1892 case 0x3d: MOVWL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1893 case 0x3e: MOVLL0(Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1894 case 0x3f: MAC_L(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1895 case 0x3a: NOP(); rlog(0); break;
\r
1896 case 0x3b: NOP(); rlog(0); break;
\r
1900 INLINE void op0001(UINT16 opcode)
\r
1902 MOVLS4(Rm, opcode & 0x0f, Rn);
\r
1906 INLINE void op0010(UINT16 opcode)
\r
1908 switch (opcode & 15)
\r
1910 case 0: MOVBS(Rm, Rn); rlog(LRNM); break;
\r
1911 case 1: MOVWS(Rm, Rn); rlog(LRNM); break;
\r
1912 case 2: MOVLS(Rm, Rn); rlog(LRNM); break;
\r
1913 case 3: NOP(); rlog(0); break;
\r
1914 case 4: MOVBM(Rm, Rn); rlog(LRNM); break;
\r
1915 case 5: MOVWM(Rm, Rn); rlog(LRNM); break;
\r
1916 case 6: MOVLM(Rm, Rn); rlog(LRNM); break;
\r
1917 case 7: DIV0S(Rm, Rn); rlog(LRNM); break;
\r
1918 case 8: TST(Rm, Rn); rlog(LRNM); break;
\r
1919 case 9: AND(Rm, Rn); rlog(LRNM); break;
\r
1920 case 10: XOR(Rm, Rn); rlog(LRNM); break;
\r
1921 case 11: OR(Rm, Rn); rlog(LRNM); break;
\r
1922 case 12: CMPSTR(Rm, Rn); rlog(LRNM); break;
\r
1923 case 13: XTRCT(Rm, Rn); rlog(LRNM); break;
\r
1924 case 14: MULU(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1925 case 15: MULS(Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1929 INLINE void op0011(UINT16 opcode)
\r
1931 switch (opcode & 15)
\r
1933 case 0: CMPEQ(Rm, Rn); rlog(LRNM); break;
\r
1934 case 1: NOP(); rlog(0); break;
\r
1935 case 2: CMPHS(Rm, Rn); rlog(LRNM); break;
\r
1936 case 3: CMPGE(Rm, Rn); rlog(LRNM); break;
\r
1937 case 4: DIV1(Rm, Rn); rlog(LRNM); break;
\r
1938 case 5: DMULU(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1939 case 6: CMPHI(Rm, Rn); rlog(LRNM); break;
\r
1940 case 7: CMPGT(Rm, Rn); rlog(LRNM); break;
\r
1941 case 8: SUB(Rm, Rn); rlog(LRNM); break;
\r
1942 case 9: NOP(); rlog(0); break;
\r
1943 case 10: SUBC(Rm, Rn); rlog(LRNM); break;
\r
1944 case 11: SUBV(Rm, Rn); rlog(LRNM); break;
\r
1945 case 12: ADD(Rm, Rn); rlog(LRNM); break;
\r
1946 case 13: DMULS(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1947 case 14: ADDC(Rm, Rn); rlog(LRNM); break;
\r
1948 case 15: ADDV(Rm, Rn); rlog(LRNM); break;
\r
1952 INLINE void op0100(UINT16 opcode)
\r
1954 switch (opcode & 0x3F)
\r
1956 case 0x00: SHLL(Rn); rlog(LRN); break;
\r
1957 case 0x01: SHLR(Rn); rlog(LRN); break;
\r
1958 case 0x02: STSMMACH(Rn); rlog(LRN); rlog1(SHR_MACH); break;
\r
1959 case 0x03: STCMSR(Rn); rlog(LRN); break;
\r
1960 case 0x04: ROTL(Rn); rlog(LRN); break;
\r
1961 case 0x05: ROTR(Rn); rlog(LRN); break;
\r
1962 case 0x06: LDSMMACH(Rn); rlog(LRN); rlog1(SHR_MACH); break;
\r
1963 case 0x07: LDCMSR(Rn); rlog(LRN); break;
\r
1964 case 0x08: SHLL2(Rn); rlog(LRN); break;
\r
1965 case 0x09: SHLR2(Rn); rlog(LRN); break;
\r
1966 case 0x0a: LDSMACH(Rn); rlog(LRN); rlog1(SHR_MACH); break;
\r
1967 case 0x0b: JSR(Rn); rlog(LRN); rlog1(SHR_PR); break;
\r
1968 case 0x0c: NOP(); rlog(0); break;
\r
1969 case 0x0d: NOP(); rlog(0); break;
\r
1970 case 0x0e: LDCSR(Rn); rlog(LRN); break;
\r
1971 case 0x0f: MAC_W(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1973 case 0x10: DT(Rn); rlog(LRN); break;
\r
1974 case 0x11: CMPPZ(Rn); rlog(LRN); break;
\r
1975 case 0x12: STSMMACL(Rn); rlog(LRN); rlog1(SHR_MACL); break;
\r
1976 case 0x13: STCMGBR(Rn); rlog(LRN); rlog1(SHR_GBR); break;
\r
1977 case 0x14: NOP(); rlog(0); break;
\r
1978 case 0x15: CMPPL(Rn); rlog(LRN); break;
\r
1979 case 0x16: LDSMMACL(Rn); rlog(LRN); rlog1(SHR_MACL); break;
\r
1980 case 0x17: LDCMGBR(Rn); rlog(LRN); rlog1(SHR_GBR); break;
\r
1981 case 0x18: SHLL8(Rn); rlog(LRN); break;
\r
1982 case 0x19: SHLR8(Rn); rlog(LRN); break;
\r
1983 case 0x1a: LDSMACL(Rn); rlog(LRN); rlog1(SHR_MACL); break;
\r
1984 case 0x1b: TAS(Rn); rlog(LRN); break;
\r
1985 case 0x1c: NOP(); rlog(0); break;
\r
1986 case 0x1d: NOP(); rlog(0); break;
\r
1987 case 0x1e: LDCGBR(Rn); rlog(LRN); rlog1(SHR_GBR); break;
\r
1988 case 0x1f: MAC_W(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1990 case 0x20: SHAL(Rn); rlog(LRN); break;
\r
1991 case 0x21: SHAR(Rn); rlog(LRN); break;
\r
1992 case 0x22: STSMPR(Rn); rlog(LRN); rlog1(SHR_PR); break;
\r
1993 case 0x23: STCMVBR(Rn); rlog(LRN); rlog1(SHR_VBR); break;
\r
1994 case 0x24: ROTCL(Rn); rlog(LRN); break;
\r
1995 case 0x25: ROTCR(Rn); rlog(LRN); break;
\r
1996 case 0x26: LDSMPR(Rn); rlog(LRN); rlog1(SHR_PR); break;
\r
1997 case 0x27: LDCMVBR(Rn); rlog(LRN); rlog1(SHR_VBR); break;
\r
1998 case 0x28: SHLL16(Rn); rlog(LRN); break;
\r
1999 case 0x29: SHLR16(Rn); rlog(LRN); break;
\r
2000 case 0x2a: LDSPR(Rn); rlog(LRN); rlog1(SHR_PR); break;
\r
2001 case 0x2b: JMP(Rn); rlog(LRN); break;
\r
2002 case 0x2c: NOP(); rlog(0); break;
\r
2003 case 0x2d: NOP(); rlog(0); break;
\r
2004 case 0x2e: LDCVBR(Rn); rlog(LRN); rlog1(SHR_VBR); break;
\r
2005 case 0x2f: MAC_W(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
2021 case 0x3e: NOP(); rlog(0); break;
\r
2022 case 0x3f: MAC_W(Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
2026 INLINE void op0101(UINT16 opcode)
\r
2028 MOVLL4(Rm, opcode & 0x0f, Rn);
\r
2032 INLINE void op0110(UINT16 opcode)
\r
2034 switch (opcode & 15)
\r
2036 case 0: MOVBL(Rm, Rn); break;
\r
2037 case 1: MOVWL(Rm, Rn); break;
\r
2038 case 2: MOVLL(Rm, Rn); break;
\r
2039 case 3: MOV(Rm, Rn); break;
\r
2040 case 4: MOVBP(Rm, Rn); break;
\r
2041 case 5: MOVWP(Rm, Rn); break;
\r
2042 case 6: MOVLP(Rm, Rn); break;
\r
2043 case 7: NOT(Rm, Rn); break;
\r
2044 case 8: SWAPB(Rm, Rn); break;
\r
2045 case 9: SWAPW(Rm, Rn); break;
\r
2046 case 10: NEGC(Rm, Rn); break;
\r
2047 case 11: NEG(Rm, Rn); break;
\r
2048 case 12: EXTUB(Rm, Rn); break;
\r
2049 case 13: EXTUW(Rm, Rn); break;
\r
2050 case 14: EXTSB(Rm, Rn); break;
\r
2051 case 15: EXTSW(Rm, Rn); break;
\r
2056 INLINE void op0111(UINT16 opcode)
\r
2058 ADDI(opcode & 0xff, Rn);
\r
2062 INLINE void op1000(UINT16 opcode)
\r
2064 switch ( opcode & (15<<8) )
\r
2066 case 0<< 8: MOVBS4(opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;
\r
2067 case 1<< 8: MOVWS4(opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;
\r
2068 case 2<< 8: NOP(); rlog(0); break;
\r
2069 case 3<< 8: NOP(); rlog(0); break;
\r
2070 case 4<< 8: MOVBL4(Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;
\r
2071 case 5<< 8: MOVWL4(Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;
\r
2072 case 6<< 8: NOP(); rlog(0); break;
\r
2073 case 7<< 8: NOP(); rlog(0); break;
\r
2074 case 8<< 8: CMPIM(opcode & 0xff); rlog(0); rlog1(0); break;
\r
2075 case 9<< 8: BT(opcode & 0xff); rlog(0); break;
\r
2076 case 10<< 8: NOP(); rlog(0); break;
\r
2077 case 11<< 8: BF(opcode & 0xff); rlog(0); break;
\r
2078 case 12<< 8: NOP(); rlog(0); break;
\r
2079 case 13<< 8: BTS(opcode & 0xff); rlog(0); break;
\r
2080 case 14<< 8: NOP(); rlog(0); break;
\r
2081 case 15<< 8: BFS(opcode & 0xff); rlog(0); break;
\r
2086 INLINE void op1001(UINT16 opcode)
\r
2088 MOVWI(opcode & 0xff, Rn);
\r
2092 INLINE void op1010(UINT16 opcode)
\r
2094 BRA(opcode & 0xfff);
\r
2098 INLINE void op1011(UINT16 opcode)
\r
2100 BSR(opcode & 0xfff);
\r
2105 INLINE void op1100(UINT16 opcode)
\r
2107 switch (opcode & (15<<8))
\r
2109 case 0<<8: MOVBSG(opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2110 case 1<<8: MOVWSG(opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2111 case 2<<8: MOVLSG(opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2112 case 3<<8: TRAPA(opcode & 0xff); rlog1(SHR_VBR); break;
\r
2113 case 4<<8: MOVBLG(opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2114 case 5<<8: MOVWLG(opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2115 case 6<<8: MOVLLG(opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2116 case 7<<8: MOVA(opcode & 0xff); rlog1(0); break;
\r
2117 case 8<<8: TSTI(opcode & 0xff); rlog1(0); break;
\r
2118 case 9<<8: ANDI(opcode & 0xff); rlog1(0); break;
\r
2119 case 10<<8: XORI(opcode & 0xff); rlog1(0); break;
\r
2120 case 11<<8: ORI(opcode & 0xff); rlog1(0); break;
\r
2121 case 12<<8: TSTM(opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2122 case 13<<8: ANDM(opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2123 case 14<<8: XORM(opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2124 case 15<<8: ORM(opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2129 INLINE void op1101(UINT16 opcode)
\r
2131 MOVLI(opcode & 0xff, Rn);
\r
2135 INLINE void op1110(UINT16 opcode)
\r
2137 MOVI(opcode & 0xff, Rn);
\r
2141 INLINE void op1111(UINT16 opcode)
\r