cpu/sh2/mame/sh2pico.c

   1 #include "../sh2.h"
   2
   3 // MAME types
   4 typedef signed char  INT8;
   5 typedef signed short INT16;
   6 typedef signed int   INT32;
   7 typedef unsigned int   UINT32;
   8 typedef unsigned short UINT16;
   9 typedef unsigned char  UINT8;
  10
  11 #define RB(a) p32x_sh2_read8(a,sh2)
  12 #define RW(a) p32x_sh2_read16(a,sh2)
  13 #define RL(a) p32x_sh2_read32(a,sh2)
  14 #define WB(a,d) p32x_sh2_write8(a,d,sh2)
  15 #define WW(a,d) p32x_sh2_write16(a,d,sh2)
  16 #define WL(a,d) p32x_sh2_write32(a,d,sh2)
  17
  18 // some stuff from sh2comn.h
  19 #define T       0x00000001
  20 #define S       0x00000002
  21 #define I       0x000000f0
  22 #define Q       0x00000100
  23 #define M       0x00000200
  24
  25 #define AM      0xc7ffffff
  26
  27 #define FLAGS   (M|Q|I|S|T)
  28
  29 #define Rn      ((opcode>>8)&15)
  30 #define Rm      ((opcode>>4)&15)
  31
  32 #define sh2_icount sh2->icount
  33
  34 #include "sh2.c"
  35
  36 #ifndef DRC_SH2
  37
  38 void sh2_execute(SH2 *sh2_, int cycles)
  39 {
  40         sh2 = sh2_;
  41         sh2->cycles_aim += cycles;
  42         sh2->icount = cycles = sh2->cycles_aim - sh2->cycles_done;
  43
  44         if (sh2->icount <= 0)
  45                 return;
  46
  47         do
  48         {
  49                 UINT32 opcode;
  50
  51                 /* FIXME: Darxide doesn't like this */
  52                 if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
  53                 {
  54                         if (sh2->pending_irl > sh2->pending_int_irq)
  55                                 sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2);
  56                         else {
  57                                 sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
  58                                 sh2->pending_int_irq = 0; // auto-clear
  59                                 sh2->pending_level = sh2->pending_irl;
  60                         }
  61                         sh2->test_irq = 0;
  62                 }
  63
  64                 if (sh2->delay)
  65                 {
  66                         sh2->ppc = sh2->delay;
  67                         opcode = RW(sh2->delay);
  68                         sh2->pc -= 2;
  69                 }
  70                 else
  71                 {
  72                         sh2->ppc = sh2->pc;
  73                         opcode = RW(sh2->pc);
  74                 }
  75
  76                 sh2->delay = 0;
  77                 sh2->pc += 2;
  78
  79                 switch (opcode & ( 15 << 12))
  80                 {
  81                 case  0<<12: op0000(opcode); break;
  82                 case  1<<12: op0001(opcode); break;
  83                 case  2<<12: op0010(opcode); break;
  84                 case  3<<12: op0011(opcode); break;
  85                 case  4<<12: op0100(opcode); break;
  86                 case  5<<12: op0101(opcode); break;
  87                 case  6<<12: op0110(opcode); break;
  88                 case  7<<12: op0111(opcode); break;
  89                 case  8<<12: op1000(opcode); break;
  90                 case  9<<12: op1001(opcode); break;
  91                 case 10<<12: op1010(opcode); break;
  92                 case 11<<12: op1011(opcode); break;
  93                 case 12<<12: op1100(opcode); break;
  94                 case 13<<12: op1101(opcode); break;
  95                 case 14<<12: op1110(opcode); break;
  96                 default: op1111(opcode); break;
  97                 }
  98
  99                 sh2->icount--;
 100         }
 101         while (sh2->icount > 0 || sh2->delay);  /* can't interrupt before delay */
 102
 103         sh2->cycles_done += cycles - sh2->icount;
 104 }
 105
 106 #else // DRC_SH2
 107
 108 #ifdef __i386__
 109 #define REGPARM(x) __attribute__((regparm(x)))
 110 #else
 111 #define REGPARM(x)
 112 #endif
 113
 114 // drc debug
 115 void REGPARM(2) sh2_do_op(SH2 *sh2_, int opcode)
 116 {
 117         sh2 = sh2_;
 118         sh2->pc += 2;
 119
 120         switch (opcode & ( 15 << 12))
 121         {
 122                 case  0<<12: op0000(opcode); break;
 123                 case  1<<12: op0001(opcode); break;
 124                 case  2<<12: op0010(opcode); break;
 125                 case  3<<12: op0011(opcode); break;
 126                 case  4<<12: op0100(opcode); break;
 127                 case  5<<12: op0101(opcode); break;
 128                 case  6<<12: op0110(opcode); break;
 129                 case  7<<12: op0111(opcode); break;
 130                 case  8<<12: op1000(opcode); break;
 131                 case  9<<12: op1001(opcode); break;
 132                 case 10<<12: op1010(opcode); break;
 133                 case 11<<12: op1011(opcode); break;
 134                 case 12<<12: op1100(opcode); break;
 135                 case 13<<12: op1101(opcode); break;
 136                 case 14<<12: op1110(opcode); break;
 137                 default: op1111(opcode); break;
 138         }
 139 }
 140
 141 #endif
 142