32x: drc: inline dispatcher and irq handling; do write-caused irqs
[picodrive.git] / cpu / sh2 / sh2.c
1 #include <string.h>
2 #include "sh2.h"
3 #include "compiler.h"
4
5 #define I 0xf0
6
7 SH2 *sh2; // active sh2
8
9 int sh2_init(SH2 *sh2, int is_slave)
10 {
11         int ret = 0;
12
13         memset(sh2, 0, sizeof(*sh2));
14         sh2->is_slave = is_slave;
15 #ifdef DRC_SH2
16         ret = sh2_drc_init(sh2);
17 #endif
18         return ret;
19 }
20
21 void sh2_finish(SH2 *sh2)
22 {
23 #ifdef DRC_SH2
24         sh2_drc_finish(sh2);
25 #endif
26 }
27
28 void sh2_reset(SH2 *sh2)
29 {
30         sh2->pc = p32x_sh2_read32(0, sh2);
31         sh2->r[15] = p32x_sh2_read32(4, sh2);
32         sh2->sr = I;
33         sh2->vbr = 0;
34         sh2->pending_int_irq = 0;
35 }
36
37 void sh2_do_irq(SH2 *sh2, int level, int vector)
38 {
39         sh2->r[15] -= 4;
40         p32x_sh2_write32(sh2->r[15], sh2->sr, sh2);     /* push SR onto stack */
41         sh2->r[15] -= 4;
42         p32x_sh2_write32(sh2->r[15], sh2->pc, sh2);     /* push PC onto stack */
43
44         /* set I flags in SR */
45         sh2->sr = (sh2->sr & ~I) | (level << 4);
46
47         /* fetch PC */
48         sh2->pc = p32x_sh2_read32(sh2->vbr + vector * 4, sh2);
49
50         /* 13 cycles at best */
51         sh2->cycles_done += 13;
52 //      sh2->icount -= 13;
53 }
54
55 void sh2_irl_irq(SH2 *sh2, int level)
56 {
57         sh2->pending_irl = level;
58         if (level > sh2->pending_int_irq)
59                 sh2->pending_level = level;
60         else
61                 sh2->pending_level = sh2->pending_int_irq;
62
63         sh2->test_irq = 1;
64 }
65
66 void sh2_internal_irq(SH2 *sh2, int level, int vector)
67 {
68         // FIXME: multiple internal irqs not handled..
69         // assuming internal irqs never clear until accepted
70         sh2->pending_int_irq = level;
71         sh2->pending_int_vector = vector;
72         if (level > sh2->pending_level)
73                 sh2->pending_level = level;
74
75         sh2->test_irq = 1;
76 }
77