4 // registers - matches structure order
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6 SHR_R0 = 0, SHR_SP = 15,
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7 SHR_PC, SHR_PPC, SHR_PR, SHR_SR,
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8 SHR_GBR, SHR_VBR, SHR_MACH, SHR_MACL,
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13 unsigned int r[16]; // 00
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14 unsigned int pc; // 40
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18 unsigned int gbr, vbr; // 50
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19 unsigned int mach, macl; // 58
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22 const void *read8_map; // 60
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23 const void *read16_map;
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24 const void **write8_tab;
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25 const void **write16_tab;
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30 // interpreter stuff
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31 int icount; // cycles left in current timeslice
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34 unsigned int test_irq;
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36 int pending_level; // MAX(pending_irl, pending_int_irq)
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38 int pending_int_irq; // internal irq
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39 int pending_int_vector;
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40 void (*irq_callback)(int id, int level);
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43 unsigned int cycles_aim; // subtract sh2_icount to get global counter
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44 unsigned int cycles_done;
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47 extern SH2 *sh2; // active sh2. XXX: consider removing
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49 int sh2_init(SH2 *sh2, int is_slave);
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50 void sh2_finish(SH2 *sh2);
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51 void sh2_reset(SH2 *sh2);
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52 void sh2_irl_irq(SH2 *sh2, int level);
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53 void sh2_internal_irq(SH2 *sh2, int level, int vector);
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54 void sh2_do_irq(SH2 *sh2, int level, int vector);
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56 void sh2_execute(SH2 *sh2, int cycles);
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59 // XXX: move somewhere else
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60 #if !defined(REGPARM) && defined(__i386__)
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61 #define REGPARM(x) __attribute__((regparm(x)))
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66 unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);
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67 unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);
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68 unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);
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69 void REGPARM(3) p32x_sh2_write8(unsigned int a, unsigned int d, SH2 *sh2);
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70 void REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);
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71 void REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);
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73 #endif /* __SH2_H__ */
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