cpu/sh2mame/sh2pico.c

   1 #include <string.h>
   2
   3 // MAME types
   4 typedef signed char  INT8;
   5 typedef signed short INT16;
   6 typedef signed int   INT32;
   7 typedef unsigned int   UINT32;
   8 typedef unsigned short UINT16;
   9 typedef unsigned char  UINT8;
  10
  11 // pico memhandlers
  12 unsigned int p32x_sh2_read8(unsigned int a, int id);
  13 unsigned int p32x_sh2_read16(unsigned int a, int id);
  14 unsigned int p32x_sh2_read32(unsigned int a, int id);
  15 void p32x_sh2_write8(unsigned int a, unsigned int d, int id);
  16 void p32x_sh2_write16(unsigned int a, unsigned int d, int id);
  17 void p32x_sh2_write32(unsigned int a, unsigned int d, int id);
  18
  19 #define RB(a) p32x_sh2_read8(a,sh2->is_slave)
  20 #define RW(a) p32x_sh2_read16(a,sh2->is_slave)
  21 #define RL(a) p32x_sh2_read32(a,sh2->is_slave)
  22 #define WB(a,d) p32x_sh2_write8(a,d,sh2->is_slave)
  23 #define WW(a,d) p32x_sh2_write16(a,d,sh2->is_slave)
  24 #define WL(a,d) p32x_sh2_write32(a,d,sh2->is_slave)
  25
  26 // some stuff from sh2comn.h
  27 #define T       0x00000001
  28 #define S       0x00000002
  29 #define I       0x000000f0
  30 #define Q       0x00000100
  31 #define M       0x00000200
  32
  33 #define AM      0xc7ffffff
  34
  35 #define FLAGS   (M|Q|I|S|T)
  36
  37 #define Rn      ((opcode>>8)&15)
  38 #define Rm      ((opcode>>4)&15)
  39
  40 #include "sh2.c"
  41
  42 void sh2_reset(SH2 *sh2)
  43 {
  44         int save_is_slave;
  45         void *save_irqcallback;
  46
  47         save_irqcallback = sh2->irq_callback;
  48         save_is_slave = sh2->is_slave;
  49
  50         memset(sh2, 0, sizeof(SH2));
  51
  52         sh2->is_slave = save_is_slave;
  53         sh2->irq_callback = save_irqcallback;
  54
  55         sh2->pc = RL(0);
  56         sh2->r[15] = RL(4);
  57         sh2->sr = I;
  58 }
  59
  60 /* Execute cycles - returns number of cycles actually run */
  61 int sh2_execute(SH2 *sh2_, int cycles)
  62 {
  63         sh2 = sh2_;
  64         sh2_icount = cycles;
  65         sh2->cycles_aim += cycles;
  66
  67         do
  68         {
  69                 UINT32 opcode;
  70
  71                 if (sh2->delay)
  72                 {
  73                         sh2->ppc = sh2->delay;
  74                         opcode = RW(sh2->delay);
  75                         sh2->pc -= 2;
  76                 }
  77                 else
  78                 {
  79                         sh2->ppc = sh2->pc;
  80                         opcode = RW(sh2->pc);
  81                 }
  82
  83                 sh2->delay = 0;
  84                 sh2->pc += 2;
  85
  86                 switch (opcode & ( 15 << 12))
  87                 {
  88                 case  0<<12: op0000(opcode); break;
  89                 case  1<<12: op0001(opcode); break;
  90                 case  2<<12: op0010(opcode); break;
  91                 case  3<<12: op0011(opcode); break;
  92                 case  4<<12: op0100(opcode); break;
  93                 case  5<<12: op0101(opcode); break;
  94                 case  6<<12: op0110(opcode); break;
  95                 case  7<<12: op0111(opcode); break;
  96                 case  8<<12: op1000(opcode); break;
  97                 case  9<<12: op1001(opcode); break;
  98                 case 10<<12: op1010(opcode); break;
  99                 case 11<<12: op1011(opcode); break;
 100                 case 12<<12: op1100(opcode); break;
 101                 case 13<<12: op1101(opcode); break;
 102                 case 14<<12: op1110(opcode); break;
 103                 default: op1111(opcode); break;
 104                 }
 105
 106                 if (sh2->test_irq && !sh2->delay)
 107                 {
 108                         if (sh2->pending_irq)
 109                                 sh2_irl_irq(sh2, sh2->pending_irq);
 110                         sh2->test_irq = 0;
 111                 }
 112                 sh2_icount--;
 113         }
 114         while (sh2_icount > 0 || sh2->delay);   /* can't interrupt before delay */
 115
 116         return cycles - sh2_icount;
 117 }
 118
 119 void sh2_init(SH2 *sh2, int is_slave)
 120 {
 121         memset(sh2, 0, sizeof(*sh2));
 122         sh2->is_slave = is_slave;
 123 }
 124
 125 void sh2_irl_irq(SH2 *sh2, int level)
 126 {
 127         int vector;
 128
 129         sh2->pending_irq = level;
 130
 131         if (level <= ((sh2->sr >> 4) & 0x0f))
 132                 /* masked */
 133                 return;
 134
 135         sh2->irq_callback(sh2->is_slave, level);
 136         vector = 64 + level/2;
 137
 138         sh2->r[15] -= 4;
 139         WL(sh2->r[15], sh2->sr);                /* push SR onto stack */
 140         sh2->r[15] -= 4;
 141         WL(sh2->r[15], sh2->pc);                /* push PC onto stack */
 142
 143         /* set I flags in SR */
 144         sh2->sr = (sh2->sr & ~I) | (level << 4);
 145
 146         /* fetch PC */
 147         sh2->pc = RL(sh2->vbr + vector * 4);
 148
 149         /* 13 cycles at best */
 150         sh2_icount -= 13;
 151 }
 152