3 * Copyright (C) 2006 Exophase <exophase@gmail.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 // - stm reglist writeback when base is in the list needs adjustment
22 // - block memory needs psr swapping and user mode reg swapping
26 u32 memory_region_access_read_u8[16];
27 u32 memory_region_access_read_s8[16];
28 u32 memory_region_access_read_u16[16];
29 u32 memory_region_access_read_s16[16];
30 u32 memory_region_access_read_u32[16];
31 u32 memory_region_access_write_u8[16];
32 u32 memory_region_access_write_u16[16];
33 u32 memory_region_access_write_u32[16];
40 u32 memory_writes_u16;
41 u32 memory_writes_u32;
43 const u8 bit_count[256] =
45 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4, 1, 2, 2, 3, 2, 3, 3,
46 4, 2, 3, 3, 4, 3, 4, 4, 5, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3, 3, 4, 3, 4,
47 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 1, 2, 2, 3, 2,
48 3, 3, 4, 2, 3, 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5,
49 4, 5, 5, 6, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4,
50 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 1, 2, 2, 3, 2, 3, 3, 4, 2, 3,
51 3, 4, 3, 4, 4, 5, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 2,
52 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5, 6, 3, 4, 4, 5, 4, 5, 5, 6,
53 4, 5, 5, 6, 5, 6, 6, 7, 2, 3, 3, 4, 3, 4, 4, 5, 3, 4, 4, 5, 4, 5, 5,
54 6, 3, 4, 4, 5, 4, 5, 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 3, 4, 4, 5, 4, 5,
55 5, 6, 4, 5, 5, 6, 5, 6, 6, 7, 4, 5, 5, 6, 5, 6, 6, 7, 5, 6, 6, 7, 6,
60 #ifdef REGISTER_USAGE_ANALYZE
62 u64 instructions_total = 0;
65 u64 arm_reg_access_total = 0;
66 u64 arm_instructions_total = 0;
68 u64 thumb_reg_freq[16];
69 u64 thumb_reg_access_total = 0;
70 u64 thumb_instructions_total = 0;
72 // mla/long mla's addition operand are not counted yet.
74 #define using_register(instruction_set, register, type) \
75 instruction_set##_reg_freq[register]++; \
76 instruction_set##_reg_access_total++ \
78 #define using_register_list(instruction_set, rlist, count) \
81 for(i = 0; i < count; i++) \
83 if((reg_list >> i) & 0x01) \
85 using_register(instruction_set, i, memory_target); \
90 #define using_instruction(instruction_set) \
91 instruction_set##_instructions_total++; \
92 instructions_total++ \
94 int sort_tagged_element(const void *_a, const void *_b)
99 return (int)(b[1] - a[1]);
102 void print_register_usage()
105 u64 arm_reg_freq_tagged[32];
106 u64 thumb_reg_freq_tagged[32];
108 double percent_total = 0.0;
110 for(i = 0; i < 16; i++)
112 arm_reg_freq_tagged[i * 2] = i;
113 arm_reg_freq_tagged[(i * 2) + 1] = arm_reg_freq[i];
114 thumb_reg_freq_tagged[i * 2] = i;
115 thumb_reg_freq_tagged[(i * 2) + 1] = thumb_reg_freq[i];
118 qsort(arm_reg_freq_tagged, 16, sizeof(u64) * 2, sort_tagged_element);
119 qsort(thumb_reg_freq_tagged, 16, sizeof(u64) * 2, sort_tagged_element);
121 printf("ARM register usage (%lf%% ARM instructions):\n",
122 (arm_instructions_total * 100.0) / instructions_total);
123 for(i = 0; i < 16; i++)
125 percent = (arm_reg_freq_tagged[(i * 2) + 1] * 100.0) /
126 arm_reg_access_total;
127 percent_total += percent;
128 printf("r%02d: %lf%% (-- %lf%%)\n",
129 (u32)arm_reg_freq_tagged[(i * 2)], percent, percent_total);
134 printf("\nThumb register usage (%lf%% Thumb instructions):\n",
135 (thumb_instructions_total * 100.0) / instructions_total);
136 for(i = 0; i < 16; i++)
138 percent = (thumb_reg_freq_tagged[(i * 2) + 1] * 100.0) /
139 thumb_reg_access_total;
140 percent_total += percent;
141 printf("r%02d: %lf%% (-- %lf%%)\n",
142 (u32)thumb_reg_freq_tagged[(i * 2)], percent, percent_total);
145 memset(arm_reg_freq, 0, sizeof(u64) * 16);
146 memset(thumb_reg_freq, 0, sizeof(u64) * 16);
147 arm_reg_access_total = 0;
148 thumb_reg_access_total = 0;
153 #define using_register(instruction_set, register, type) \
155 #define using_register_list(instruction_set, rlist, count) \
157 #define using_instruction(instruction_set) \
162 #define arm_decode_data_proc_reg() \
163 u32 rn = (opcode >> 16) & 0x0F; \
164 u32 rd = (opcode >> 12) & 0x0F; \
165 u32 rm = opcode & 0x0F; \
166 using_register(arm, rd, op_dest); \
167 using_register(arm, rn, op_src); \
168 using_register(arm, rm, op_src) \
170 #define arm_decode_data_proc_imm() \
171 u32 rn = (opcode >> 16) & 0x0F; \
172 u32 rd = (opcode >> 12) & 0x0F; \
174 ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2); \
175 using_register(arm, rd, op_dest); \
176 using_register(arm, rn, op_src) \
178 #define arm_decode_psr_reg() \
179 u32 psr_field = (opcode >> 16) & 0x0F; \
180 u32 rd = (opcode >> 12) & 0x0F; \
181 u32 rm = opcode & 0x0F; \
182 using_register(arm, rd, op_dest); \
183 using_register(arm, rm, op_src) \
185 #define arm_decode_psr_imm() \
186 u32 psr_field = (opcode >> 16) & 0x0F; \
187 u32 rd = (opcode >> 12) & 0x0F; \
189 ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2); \
190 using_register(arm, rd, op_dest) \
192 #define arm_decode_branchx() \
193 u32 rn = opcode & 0x0F; \
194 using_register(arm, rn, branch_target) \
196 #define arm_decode_multiply() \
197 u32 rd = (opcode >> 16) & 0x0F; \
198 u32 rn = (opcode >> 12) & 0x0F; \
199 u32 rs = (opcode >> 8) & 0x0F; \
200 u32 rm = opcode & 0x0F; \
201 using_register(arm, rd, op_dest); \
202 using_register(arm, rn, op_src); \
203 using_register(arm, rm, op_src) \
205 #define arm_decode_multiply_long() \
206 u32 rdhi = (opcode >> 16) & 0x0F; \
207 u32 rdlo = (opcode >> 12) & 0x0F; \
208 u32 rn = (opcode >> 8) & 0x0F; \
209 u32 rm = opcode & 0x0F; \
210 using_register(arm, rdhi, op_dest); \
211 using_register(arm, rdlo, op_dest); \
212 using_register(arm, rn, op_src); \
213 using_register(arm, rm, op_src) \
215 #define arm_decode_swap() \
216 u32 rn = (opcode >> 16) & 0x0F; \
217 u32 rd = (opcode >> 12) & 0x0F; \
218 u32 rm = opcode & 0x0F; \
219 using_register(arm, rd, memory_target); \
220 using_register(arm, rn, memory_base); \
221 using_register(arm, rm, memory_target) \
223 #define arm_decode_half_trans_r() \
224 u32 rn = (opcode >> 16) & 0x0F; \
225 u32 rd = (opcode >> 12) & 0x0F; \
226 u32 rm = opcode & 0x0F; \
227 using_register(arm, rd, memory_target); \
228 using_register(arm, rn, memory_base); \
229 using_register(arm, rm, memory_offset) \
231 #define arm_decode_half_trans_of() \
232 u32 rn = (opcode >> 16) & 0x0F; \
233 u32 rd = (opcode >> 12) & 0x0F; \
234 u32 offset = ((opcode >> 4) & 0xF0) | (opcode & 0x0F); \
235 using_register(arm, rd, memory_target); \
236 using_register(arm, rn, memory_base) \
238 #define arm_decode_data_trans_imm() \
239 u32 rn = (opcode >> 16) & 0x0F; \
240 u32 rd = (opcode >> 12) & 0x0F; \
241 u32 offset = opcode & 0x0FFF; \
242 using_register(arm, rd, memory_target); \
243 using_register(arm, rn, memory_base) \
245 #define arm_decode_data_trans_reg() \
246 u32 rn = (opcode >> 16) & 0x0F; \
247 u32 rd = (opcode >> 12) & 0x0F; \
248 u32 rm = opcode & 0x0F; \
249 using_register(arm, rd, memory_target); \
250 using_register(arm, rn, memory_base); \
251 using_register(arm, rm, memory_offset) \
253 #define arm_decode_block_trans() \
254 u32 rn = (opcode >> 16) & 0x0F; \
255 u32 reg_list = opcode & 0xFFFF; \
256 using_register(arm, rn, memory_base); \
257 using_register_list(arm, reg_list, 16) \
259 #define arm_decode_branch() \
260 s32 offset = ((s32)(opcode & 0xFFFFFF) << 8) >> 6 \
263 #define thumb_decode_shift() \
264 u32 imm = (opcode >> 6) & 0x1F; \
265 u32 rs = (opcode >> 3) & 0x07; \
266 u32 rd = opcode & 0x07; \
267 using_register(thumb, rd, op_dest); \
268 using_register(thumb, rs, op_shift) \
270 #define thumb_decode_add_sub() \
271 u32 rn = (opcode >> 6) & 0x07; \
272 u32 rs = (opcode >> 3) & 0x07; \
273 u32 rd = opcode & 0x07; \
274 using_register(thumb, rd, op_dest); \
275 using_register(thumb, rn, op_src); \
276 using_register(thumb, rn, op_src) \
278 #define thumb_decode_add_sub_imm() \
279 u32 imm = (opcode >> 6) & 0x07; \
280 u32 rs = (opcode >> 3) & 0x07; \
281 u32 rd = opcode & 0x07; \
282 using_register(thumb, rd, op_src_dest); \
283 using_register(thumb, rs, op_src) \
285 #define thumb_decode_imm() \
286 u32 imm = opcode & 0xFF; \
287 using_register(thumb, ((opcode >> 8) & 0x07), op_dest) \
289 #define thumb_decode_alu_op() \
290 u32 rs = (opcode >> 3) & 0x07; \
291 u32 rd = opcode & 0x07; \
292 using_register(thumb, rd, op_src_dest); \
293 using_register(thumb, rs, op_src) \
295 #define thumb_decode_hireg_op() \
296 u32 rs = (opcode >> 3) & 0x0F; \
297 u32 rd = ((opcode >> 4) & 0x08) | (opcode & 0x07); \
298 using_register(thumb, rd, op_src_dest); \
299 using_register(thumb, rs, op_src) \
302 #define thumb_decode_mem_reg() \
303 u32 ro = (opcode >> 6) & 0x07; \
304 u32 rb = (opcode >> 3) & 0x07; \
305 u32 rd = opcode & 0x07; \
306 using_register(thumb, rd, memory_target); \
307 using_register(thumb, rb, memory_base); \
308 using_register(thumb, ro, memory_offset) \
311 #define thumb_decode_mem_imm() \
312 u32 imm = (opcode >> 6) & 0x1F; \
313 u32 rb = (opcode >> 3) & 0x07; \
314 u32 rd = opcode & 0x07; \
315 using_register(thumb, rd, memory_target); \
316 using_register(thumb, rb, memory_base) \
319 #define thumb_decode_add_sp() \
320 u32 imm = opcode & 0x7F; \
321 using_register(thumb, REG_SP, op_dest) \
323 #define thumb_decode_rlist() \
324 u32 reg_list = opcode & 0xFF; \
325 using_register_list(thumb, rlist, 8) \
327 #define thumb_decode_branch_cond() \
328 s32 offset = (s8)(opcode & 0xFF) \
330 #define thumb_decode_swi() \
331 u32 comment = opcode & 0xFF \
333 #define thumb_decode_branch() \
334 u32 offset = opcode & 0x07FF \
337 #define get_shift_register(dest) \
338 u32 shift = reg[(opcode >> 8) & 0x0F]; \
339 using_register(arm, ((opcode >> 8) & 0x0F), op_shift); \
345 #define calculate_z_flag(dest) \
346 z_flag = (dest == 0) \
348 #define calculate_n_flag(dest) \
349 n_flag = ((signed)dest < 0) \
351 #define calculate_c_flag_sub(dest, src_a, src_b) \
352 c_flag = ((unsigned)src_b <= (unsigned)src_a) \
354 #define calculate_v_flag_sub(dest, src_a, src_b) \
355 v_flag = ((signed)src_b > (signed)src_a) != ((signed)dest < 0) \
357 #define calculate_c_flag_add(dest, src_a, src_b) \
358 c_flag = ((unsigned)dest < (unsigned)src_a) \
360 #define calculate_v_flag_add(dest, src_a, src_b) \
361 v_flag = ((signed)dest < (signed)src_a) != ((signed)src_b < 0) \
364 #define calculate_reg_sh() \
366 switch((opcode >> 4) & 0x07) \
371 reg_sh = reg[rm] << ((opcode >> 7) & 0x1F); \
378 get_shift_register(reg_sh); \
380 reg_sh = reg_sh << shift; \
389 u32 imm = (opcode >> 7) & 0x1F; \
393 reg_sh = reg[rm] >> imm; \
400 get_shift_register(reg_sh); \
402 reg_sh = reg_sh >> shift; \
411 u32 imm = (opcode >> 7) & 0x1F; \
415 reg_sh = (s32)reg_sh >> 31; \
417 reg_sh = (s32)reg_sh >> imm; \
424 get_shift_register(reg_sh); \
426 reg_sh = (s32)reg_sh >> shift; \
428 reg_sh = (s32)reg_sh >> 31; \
435 u32 imm = (opcode >> 7) & 0x1F; \
438 reg_sh = (reg[rm] >> 1) | (c_flag << 31); \
440 ror(reg_sh, reg[rm], imm); \
447 get_shift_register(reg_sh); \
448 ror(reg_sh, reg_sh, shift); \
453 #define calculate_reg_sh_flags() \
455 switch((opcode >> 4) & 0x07) \
460 u32 imm = (opcode >> 7) & 0x1F; \
465 c_flag = (reg_sh >> (32 - imm)) & 0x01; \
475 get_shift_register(reg_sh); \
481 c_flag = reg_sh & 0x01; \
488 c_flag = (reg_sh >> (32 - shift)) & 0x01; \
498 u32 imm = (opcode >> 7) & 0x1F; \
502 c_flag = reg_sh >> 31; \
507 c_flag = (reg_sh >> (imm - 1)) & 0x01; \
516 get_shift_register(reg_sh); \
522 c_flag = (reg_sh >> 31) & 0x01; \
529 c_flag = (reg_sh >> (shift - 1)) & 0x01; \
539 u32 imm = (opcode >> 7) & 0x1F; \
543 reg_sh = (s32)reg_sh >> 31; \
544 c_flag = reg_sh & 0x01; \
548 c_flag = (reg_sh >> (imm - 1)) & 0x01; \
549 reg_sh = (s32)reg_sh >> imm; \
557 get_shift_register(reg_sh); \
562 reg_sh = (s32)reg_sh >> 31; \
563 c_flag = reg_sh & 0x01; \
567 c_flag = (reg_sh >> (shift - 1)) & 0x01; \
568 reg_sh = (s32)reg_sh >> shift; \
577 u32 imm = (opcode >> 7) & 0x1F; \
581 u32 old_c_flag = c_flag; \
582 c_flag = reg_sh & 0x01; \
583 reg_sh = (reg_sh >> 1) | (old_c_flag << 31); \
587 c_flag = (reg_sh >> (imm - 1)) & 0x01; \
588 ror(reg_sh, reg_sh, imm); \
596 get_shift_register(reg_sh); \
599 c_flag = (reg_sh >> (shift - 1)) & 0x01; \
600 ror(reg_sh, reg_sh, shift); \
606 #define calculate_reg_offset() \
607 u32 reg_offset = 0; \
608 switch((opcode >> 5) & 0x03) \
613 reg_offset = reg[rm] << ((opcode >> 7) & 0x1F); \
620 u32 imm = (opcode >> 7) & 0x1F; \
624 reg_offset = reg[rm] >> imm; \
631 u32 imm = (opcode >> 7) & 0x1F; \
633 reg_offset = (s32)reg[rm] >> 31; \
635 reg_offset = (s32)reg[rm] >> imm; \
642 u32 imm = (opcode >> 7) & 0x1F; \
644 reg_offset = (reg[rm] >> 1) | (c_flag << 31); \
646 ror(reg_offset, reg[rm], imm); \
651 #define calculate_flags_add(dest, src_a, src_b) \
652 calculate_z_flag(dest); \
653 calculate_n_flag(dest); \
654 calculate_c_flag_add(dest, src_a, src_b); \
655 calculate_v_flag_add(dest, src_a, src_b) \
657 #define calculate_flags_sub(dest, src_a, src_b) \
658 calculate_z_flag(dest); \
659 calculate_n_flag(dest); \
660 calculate_c_flag_sub(dest, src_a, src_b); \
661 calculate_v_flag_sub(dest, src_a, src_b) \
663 #define calculate_flags_logic(dest) \
664 calculate_z_flag(dest); \
665 calculate_n_flag(dest) \
667 #define extract_flags() \
668 n_flag = reg[REG_CPSR] >> 31; \
669 z_flag = (reg[REG_CPSR] >> 30) & 0x01; \
670 c_flag = (reg[REG_CPSR] >> 29) & 0x01; \
671 v_flag = (reg[REG_CPSR] >> 28) & 0x01; \
673 #define collapse_flags() \
674 reg[REG_CPSR] = (n_flag << 31) | (z_flag << 30) | (c_flag << 29) | \
675 (v_flag << 28) | (reg[REG_CPSR] & 0xFF) \
677 #define memory_region(r_dest, l_dest, address) \
678 r_dest = memory_regions[address >> 24]; \
679 l_dest = memory_limits[address >> 24] \
682 #define pc_region() \
683 memory_region(pc_region, pc_limit, pc) \
685 #define check_pc_region() \
686 new_pc_region = (pc >> 15); \
687 if(new_pc_region != pc_region) \
689 pc_region = new_pc_region; \
690 pc_address_block = memory_map_read[new_pc_region]; \
692 if(pc_address_block == NULL) \
693 pc_address_block = load_gamepak_page(pc_region & 0x3FF); \
696 u32 branch_targets = 0;
697 u32 high_frequency_branch_targets = 0;
699 #define BRANCH_ACTIVITY_THRESHOLD 50
701 #define arm_update_pc() \
704 #define arm_pc_offset(val) \
708 #define arm_pc_offset_update(val) \
712 #define arm_pc_offset_update_direct(val) \
717 // It should be okay to still generate result flags, spsr will overwrite them.
718 // This is pretty infrequent (returning from interrupt handlers, et al) so
719 // probably not worth optimizing for.
721 #define check_for_interrupts() \
722 if((io_registers[REG_IE] & io_registers[REG_IF]) && \
723 io_registers[REG_IME] && ((reg[REG_CPSR] & 0x80) == 0)) \
725 reg_mode[MODE_IRQ][6] = reg[REG_PC] + 4; \
726 spsr[MODE_IRQ] = reg[REG_CPSR]; \
727 reg[REG_CPSR] = 0xD2; \
728 reg[REG_PC] = 0x00000018; \
730 set_cpu_mode(MODE_IRQ); \
734 #define arm_spsr_restore() \
737 if(reg[CPU_MODE] != MODE_USER) \
739 reg[REG_CPSR] = spsr[reg[CPU_MODE]]; \
741 set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]); \
742 check_for_interrupts(); \
746 if(reg[REG_CPSR] & 0x20) \
750 #define arm_data_proc_flags_reg() \
751 arm_decode_data_proc_reg(); \
752 calculate_reg_sh_flags() \
754 #define arm_data_proc_reg() \
755 arm_decode_data_proc_reg(); \
758 #define arm_data_proc_flags_imm() \
759 arm_decode_data_proc_imm() \
761 #define arm_data_proc_imm() \
762 arm_decode_data_proc_imm() \
764 #define arm_data_proc(expr, type) \
768 arm_data_proc_##type(); \
779 #define flags_vars(src_a, src_b) \
781 const u32 _sa = src_a; \
782 const u32 _sb = src_b \
784 #define arm_data_proc_logic_flags(expr, type) \
787 arm_data_proc_flags_##type(); \
789 calculate_flags_logic(dest); \
792 arm_spsr_restore(); \
795 #define arm_data_proc_add_flags(src_a, src_b, type) \
798 arm_data_proc_##type(); \
799 flags_vars(src_a, src_b); \
801 calculate_flags_add(dest, _sa, _sb); \
804 arm_spsr_restore(); \
807 #define arm_data_proc_sub_flags(src_a, src_b, type) \
810 arm_data_proc_##type(); \
811 flags_vars(src_a, src_b); \
813 calculate_flags_sub(dest, _sa, _sb); \
816 arm_spsr_restore(); \
819 #define arm_data_proc_test_logic(expr, type) \
822 arm_data_proc_flags_##type(); \
824 calculate_flags_logic(dest); \
828 #define arm_data_proc_test_add(src_a, src_b, type) \
831 arm_data_proc_##type(); \
832 flags_vars(src_a, src_b); \
834 calculate_flags_add(dest, _sa, _sb); \
838 #define arm_data_proc_test_sub(src_a, src_b, type) \
841 arm_data_proc_##type(); \
842 flags_vars(src_a, src_b); \
844 calculate_flags_sub(dest, _sa, _sb); \
848 #define arm_multiply_flags_yes(_dest) \
849 calculate_z_flag(_dest); \
850 calculate_n_flag(_dest); \
852 #define arm_multiply_flags_no(_dest) \
854 #define arm_multiply_long_flags_yes(_dest_lo, _dest_hi) \
855 z_flag = (_dest_lo == 0) & (_dest_hi == 0); \
856 calculate_n_flag(_dest_hi) \
858 #define arm_multiply_long_flags_no(_dest_lo, _dest_hi) \
860 #define arm_multiply(add_op, flags) \
863 arm_decode_multiply(); \
864 dest = (reg[rm] * reg[rs]) add_op; \
865 arm_multiply_flags_##flags(dest); \
870 #define arm_multiply_long_addop(type) \
871 + ((type##64)((((type##64)reg[rdhi]) << 32) | reg[rdlo])); \
873 #define arm_multiply_long(add_op, flags, type) \
878 arm_decode_multiply_long(); \
879 dest = ((type##64)((type##32)reg[rm]) * \
880 (type##64)((type##32)reg[rn])) add_op; \
881 dest_lo = (u32)dest; \
882 dest_hi = (u32)(dest >> 32); \
883 arm_multiply_long_flags_##flags(dest_lo, dest_hi); \
884 reg[rdlo] = dest_lo; \
885 reg[rdhi] = dest_hi; \
889 const u32 psr_masks[16] =
891 0x00000000, 0x000000FF, 0x0000FF00, 0x0000FFFF, 0x00FF0000,
892 0x00FF00FF, 0x00FFFF00, 0x00FFFFFF, 0xFF000000, 0xFF0000FF,
893 0xFF00FF00, 0xFF00FFFF, 0xFFFF0000, 0xFFFF00FF, 0xFFFFFF00,
897 #define arm_psr_read(dummy, psr_reg) \
901 #define arm_psr_store_cpsr(source) \
902 reg[REG_CPSR] = (source & store_mask) | (reg[REG_CPSR] & (~store_mask)); \
904 if(store_mask & 0xFF) \
906 set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0x1F]); \
907 check_for_interrupts(); \
910 #define arm_psr_store_spsr(source) \
911 u32 _psr = spsr[reg[CPU_MODE]]; \
912 spsr[reg[CPU_MODE]] = (source & store_mask) | (_psr & (~store_mask)) \
914 #define arm_psr_store(source, psr_reg) \
915 const u32 store_mask = psr_masks[psr_field]; \
916 arm_psr_store_##psr_reg(source) \
918 #define arm_psr_src_reg reg[rm]
920 #define arm_psr_src_imm imm
922 #define arm_psr(op_type, transfer_type, psr_reg) \
924 arm_decode_psr_##op_type(); \
926 arm_psr_##transfer_type(arm_psr_src_##op_type, psr_reg); \
929 #define arm_data_trans_reg() \
930 arm_decode_data_trans_reg(); \
931 calculate_reg_offset() \
933 #define arm_data_trans_imm() \
934 arm_decode_data_trans_imm() \
936 #define arm_data_trans_half_reg() \
937 arm_decode_half_trans_r() \
939 #define arm_data_trans_half_imm() \
940 arm_decode_half_trans_of() \
942 #define aligned_address_mask8 0xF0000000
943 #define aligned_address_mask16 0xF0000001
944 #define aligned_address_mask32 0xF0000003
946 #define fast_read_memory(size, type, address, dest) \
949 u32 _address = address; \
951 if(_address < 0x10000000) \
953 memory_region_access_read_##type[_address >> 24]++; \
954 memory_reads_##type++; \
956 if(((_address >> 24) == 0) && (pc >= 0x4000)) \
958 dest = *((type *)((u8 *)&bios_read_protect + (_address & 0x03))); \
962 if(((_address & aligned_address_mask##size) == 0) && \
963 (map = memory_map_read[_address >> 15])) \
965 dest = *((type *)((u8 *)map + (_address & 0x7FFF))); \
969 dest = (type)read_memory##size(_address); \
973 #define fast_read_memory_s16(address, dest) \
976 u32 _address = address; \
977 if(_address < 0x10000000) \
979 memory_region_access_read_s16[_address >> 24]++; \
980 memory_reads_s16++; \
982 if(((_address & aligned_address_mask16) == 0) && \
983 (map = memory_map_read[_address >> 15])) \
985 dest = *((s16 *)((u8 *)map + (_address & 0x7FFF))); \
989 dest = (s16)read_memory16_signed(_address); \
994 #define fast_write_memory(size, type, address, value) \
997 u32 _address = (address) & ~(aligned_address_mask##size & 0x03); \
998 if(_address < 0x10000000) \
1000 memory_region_access_write_##type[_address >> 24]++; \
1001 memory_writes_##type++; \
1004 if(((_address & aligned_address_mask##size) == 0) && \
1005 (map = memory_map_write[_address >> 15])) \
1007 *((type *)((u8 *)map + (_address & 0x7FFF))) = value; \
1011 cpu_alert = write_memory##size(_address, value); \
1017 #define load_aligned32(address, dest) \
1019 u32 _address = address; \
1020 u8 *map = memory_map_read[_address >> 15]; \
1021 if(_address < 0x10000000) \
1023 memory_region_access_read_u32[_address >> 24]++; \
1024 memory_reads_u32++; \
1028 dest = address32(map, _address & 0x7FFF); \
1032 dest = read_memory32(_address); \
1036 #define store_aligned32(address, value) \
1038 u32 _address = address; \
1039 u8 *map = memory_map_write[_address >> 15]; \
1040 if(_address < 0x10000000) \
1042 memory_region_access_write_u32[_address >> 24]++; \
1043 memory_writes_u32++; \
1047 address32(map, _address & 0x7FFF) = value; \
1051 cpu_alert = write_memory32(_address, value); \
1057 #define load_memory_u8(address, dest) \
1058 fast_read_memory(8, u8, address, dest) \
1060 #define load_memory_u16(address, dest) \
1061 fast_read_memory(16, u16, address, dest) \
1063 #define load_memory_u32(address, dest) \
1064 fast_read_memory(32, u32, address, dest) \
1066 #define load_memory_s8(address, dest) \
1067 fast_read_memory(8, s8, address, dest) \
1069 #define load_memory_s16(address, dest) \
1070 fast_read_memory_s16(address, dest) \
1072 #define store_memory_u8(address, value) \
1073 fast_write_memory(8, u8, address, value) \
1075 #define store_memory_u16(address, value) \
1076 fast_write_memory(16, u16, address, value) \
1078 #define store_memory_u32(address, value) \
1079 fast_write_memory(32, u32, address, value) \
1083 #define arm_access_memory_writeback_yes(off_op) \
1084 reg[rn] = address off_op \
1086 #define arm_access_memory_writeback_no(off_op) \
1088 #define arm_access_memory_pc_preadjust_load() \
1090 #define arm_access_memory_pc_preadjust_store() \
1091 u32 reg_op = reg[rd]; \
1095 #define arm_access_memory_pc_postadjust_load() \
1098 #define arm_access_memory_pc_postadjust_store() \
1100 #define load_reg_op reg[rd] \
1102 #define store_reg_op reg_op \
1104 #define arm_access_memory(access_type, off_op, off_type, mem_type, \
1108 arm_data_trans_##off_type(); \
1109 u32 address = reg[rn] off_op; \
1110 arm_access_memory_pc_preadjust_##access_type(); \
1112 arm_pc_offset(-4); \
1113 arm_access_memory_writeback_##wb(wb_off_op); \
1114 access_type##_memory_##mem_type(address, access_type##_reg_op); \
1115 arm_access_memory_pc_postadjust_##access_type(); \
1118 #define word_bit_count(word) \
1119 (bit_count[word >> 8] + bit_count[word & 0xFF]) \
1121 #define sprint_no(access_type, offset_type, writeback_type) \
1123 #define sprint_yes(access_type, offset_type, writeback_type) \
1124 printf("sbit on %s %s %s\n", #access_type, #offset_type, #writeback_type) \
1126 #define arm_block_writeback_load() \
1127 if(!((reg_list >> rn) & 0x01)) \
1129 reg[rn] = address; \
1132 #define arm_block_writeback_store() \
1135 #define arm_block_writeback_yes(access_type) \
1136 arm_block_writeback_##access_type() \
1138 #define arm_block_writeback_no(access_type) \
1140 #define load_block_memory(address, dest) \
1141 dest = address32(address_region, (address + offset) & 0x7FFF) \
1143 #define store_block_memory(address, dest) \
1144 address32(address_region, (address + offset) & 0x7FFF) = dest \
1146 #define arm_block_memory_offset_down_a() \
1147 (base - (word_bit_count(reg_list) * 4) + 4) \
1149 #define arm_block_memory_offset_down_b() \
1150 (base - (word_bit_count(reg_list) * 4)) \
1152 #define arm_block_memory_offset_no() \
1155 #define arm_block_memory_offset_up() \
1158 #define arm_block_memory_writeback_down() \
1159 reg[rn] = base - (word_bit_count(reg_list) * 4) \
1161 #define arm_block_memory_writeback_up() \
1162 reg[rn] = base + (word_bit_count(reg_list) * 4) \
1164 #define arm_block_memory_writeback_no() \
1166 #define arm_block_memory_load_pc() \
1167 load_aligned32(address, pc); \
1170 #define arm_block_memory_store_pc() \
1171 store_aligned32(address, pc + 4) \
1173 #define arm_block_memory(access_type, offset_type, writeback_type, s_bit) \
1175 arm_decode_block_trans(); \
1176 u32 base = reg[rn]; \
1177 u32 address = arm_block_memory_offset_##offset_type() & 0xFFFFFFFC; \
1180 arm_block_memory_writeback_##writeback_type(); \
1182 for(i = 0; i < 15; i++) \
1184 if((reg_list >> i) & 0x01) \
1186 access_type##_aligned32(address, reg[i]); \
1192 if(reg_list & 0x8000) \
1194 arm_block_memory_##access_type##_pc(); \
1198 #define arm_swap(type) \
1200 arm_decode_swap(); \
1202 load_memory_##type(reg[rn], temp); \
1203 store_memory_##type(reg[rn], reg[rm]); \
1208 #define arm_next_instruction() \
1211 goto skip_instruction; \
1214 #define thumb_update_pc() \
1217 #define thumb_pc_offset(val) \
1221 #define thumb_pc_offset_update(val) \
1225 #define thumb_pc_offset_update_direct(val) \
1229 // Types: add_sub, add_sub_imm, alu_op, imm
1230 // Affects N/Z/C/V flags
1232 #define thumb_add(type, dest_reg, src_a, src_b) \
1234 thumb_decode_##type(); \
1235 const u32 _sa = src_a; \
1236 const u32 _sb = src_b; \
1237 u32 dest = _sa + _sb; \
1238 calculate_flags_add(dest, _sa, _sb); \
1239 reg[dest_reg] = dest; \
1240 thumb_pc_offset(2); \
1243 #define thumb_add_noflags(type, dest_reg, src_a, src_b) \
1245 thumb_decode_##type(); \
1246 u32 dest = (src_a) + (src_b); \
1247 reg[dest_reg] = dest; \
1248 thumb_pc_offset(2); \
1251 #define thumb_sub(type, dest_reg, src_a, src_b) \
1253 thumb_decode_##type(); \
1254 const u32 _sa = src_a; \
1255 const u32 _sb = src_b; \
1256 u32 dest = _sa - _sb; \
1257 calculate_flags_sub(dest, _sa, _sb); \
1258 reg[dest_reg] = dest; \
1259 thumb_pc_offset(2); \
1262 // Affects N/Z flags
1264 #define thumb_logic(type, dest_reg, expr) \
1266 thumb_decode_##type(); \
1268 calculate_flags_logic(dest); \
1269 reg[dest_reg] = dest; \
1270 thumb_pc_offset(2); \
1273 // Decode types: shift, alu_op
1274 // Operation types: lsl, lsr, asr, ror
1275 // Affects N/Z/C flags
1277 #define thumb_shift_lsl_reg() \
1278 u32 shift = reg[rs]; \
1279 u32 dest = reg[rd]; \
1285 c_flag = dest & 0x01; \
1292 c_flag = (dest >> (32 - shift)) & 0x01; \
1297 #define thumb_shift_lsr_reg() \
1298 u32 shift = reg[rs]; \
1299 u32 dest = reg[rd]; \
1305 c_flag = dest >> 31; \
1312 c_flag = (dest >> (shift - 1)) & 0x01; \
1317 #define thumb_shift_asr_reg() \
1318 u32 shift = reg[rs]; \
1319 u32 dest = reg[rd]; \
1324 dest = (s32)dest >> 31; \
1325 c_flag = dest & 0x01; \
1329 c_flag = (dest >> (shift - 1)) & 0x01; \
1330 dest = (s32)dest >> shift; \
1334 #define thumb_shift_ror_reg() \
1335 u32 shift = reg[rs]; \
1336 u32 dest = reg[rd]; \
1339 c_flag = (dest >> (shift - 1)) & 0x01; \
1340 ror(dest, dest, shift); \
1343 #define thumb_shift_lsl_imm() \
1344 u32 dest = reg[rs]; \
1347 c_flag = (dest >> (32 - imm)) & 0x01; \
1351 #define thumb_shift_lsr_imm() \
1356 c_flag = reg[rs] >> 31; \
1361 c_flag = (dest >> (imm - 1)) & 0x01; \
1365 #define thumb_shift_asr_imm() \
1369 dest = (s32)reg[rs] >> 31; \
1370 c_flag = dest & 0x01; \
1375 c_flag = (dest >> (imm - 1)) & 0x01; \
1376 dest = (s32)dest >> imm; \
1379 #define thumb_shift_ror_imm() \
1380 u32 dest = reg[rs]; \
1383 u32 old_c_flag = c_flag; \
1384 c_flag = dest & 0x01; \
1385 dest = (dest >> 1) | (old_c_flag << 31); \
1389 c_flag = (dest >> (imm - 1)) & 0x01; \
1390 ror(dest, dest, imm); \
1393 #define thumb_shift(decode_type, op_type, value_type) \
1395 thumb_decode_##decode_type(); \
1396 thumb_shift_##op_type##_##value_type(); \
1397 calculate_flags_logic(dest); \
1399 thumb_pc_offset(2); \
1402 #define thumb_test_add(type, src_a, src_b) \
1404 thumb_decode_##type(); \
1405 const u32 _sa = src_a; \
1406 const u32 _sb = src_b; \
1407 u32 dest = _sa + _sb; \
1408 calculate_flags_add(dest, src_a, src_b); \
1409 thumb_pc_offset(2); \
1412 #define thumb_test_sub(type, src_a, src_b) \
1414 thumb_decode_##type(); \
1415 const u32 _sa = src_a; \
1416 const u32 _sb = src_b; \
1417 u32 dest = _sa - _sb; \
1418 calculate_flags_sub(dest, src_a, src_b); \
1419 thumb_pc_offset(2); \
1422 #define thumb_test_logic(type, expr) \
1424 thumb_decode_##type(); \
1426 calculate_flags_logic(dest); \
1427 thumb_pc_offset(2); \
1430 #define thumb_hireg_op(expr) \
1432 thumb_pc_offset(4); \
1433 thumb_decode_hireg_op(); \
1435 thumb_pc_offset(-2); \
1438 reg[REG_PC] = dest & ~0x01; \
1439 thumb_update_pc(); \
1447 // Operation types: imm, mem_reg, mem_imm
1449 #define thumb_access_memory(access_type, op_type, address, reg_op, \
1452 thumb_decode_##op_type(); \
1453 access_type##_memory_##mem_type(address, reg_op); \
1454 thumb_pc_offset(2); \
1457 #define thumb_block_address_preadjust_no_op() \
1459 #define thumb_block_address_preadjust_up() \
1460 address += bit_count[reg_list] * 4 \
1462 #define thumb_block_address_preadjust_down() \
1463 address -= bit_count[reg_list] * 4 \
1465 #define thumb_block_address_preadjust_push_lr() \
1466 address -= (bit_count[reg_list] + 1) * 4 \
1468 #define thumb_block_address_postadjust_no_op() \
1470 #define thumb_block_address_postadjust_up() \
1473 #define thumb_block_address_postadjust_down() \
1476 #define thumb_block_address_postadjust_pop_pc() \
1477 load_memory_u32(address + offset, pc); \
1480 address += offset + 4 \
1482 #define thumb_block_address_postadjust_push_lr() \
1483 store_memory_u32(address + offset, reg[REG_LR]); \
1485 #define thumb_block_memory_wb_load(base_reg) \
1486 if(!((reg_list >> base_reg) & 0x01)) \
1488 reg[base_reg] = address; \
1491 #define thumb_block_memory_wb_store(base_reg) \
1492 reg[base_reg] = address \
1494 #define thumb_block_memory(access_type, pre_op, post_op, base_reg) \
1498 thumb_decode_rlist(); \
1499 using_register(thumb, base_reg, memory_base); \
1500 u32 address = reg[base_reg] & ~0x03; \
1501 thumb_block_address_preadjust_##pre_op(); \
1503 for(i = 0; i < 8; i++) \
1505 if((reg_list >> i) & 1) \
1507 access_type##_aligned32(address + offset, reg[i]); \
1512 thumb_pc_offset(2); \
1514 thumb_block_address_postadjust_##post_op(); \
1515 thumb_block_memory_wb_##access_type(base_reg); \
1518 #define thumb_conditional_branch(condition) \
1520 thumb_decode_branch_cond(); \
1523 thumb_pc_offset((offset * 2) + 4); \
1527 thumb_pc_offset(2); \
1531 // When a mode change occurs from non-FIQ to non-FIQ retire the current
1532 // reg[13] and reg[14] into reg_mode[cpu_mode][5] and reg_mode[cpu_mode][6]
1533 // respectively and load into reg[13] and reg[14] reg_mode[new_mode][5] and
1534 // reg_mode[new_mode][6]. When swapping to/from FIQ retire/load reg[8]
1535 // through reg[14] to/from reg_mode[MODE_FIQ][0] through reg_mode[MODE_FIQ][6].
1541 MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID,
1542 MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID,
1543 MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID, MODE_INVALID,
1544 MODE_INVALID, MODE_USER, MODE_FIQ, MODE_IRQ, MODE_SUPERVISOR, MODE_INVALID,
1545 MODE_INVALID, MODE_INVALID, MODE_ABORT, MODE_INVALID, MODE_INVALID,
1546 MODE_INVALID, MODE_INVALID, MODE_UNDEFINED, MODE_INVALID, MODE_INVALID,
1550 u32 cpu_modes_cpsr[7] = { 0x10, 0x11, 0x12, 0x13, 0x17, 0x1B, 0x1F };
1552 // When switching modes set spsr[new_mode] to cpsr. Modifying PC as the
1553 // target of a data proc instruction will set cpsr to spsr[cpu_mode].
1555 u32 initial_reg[64];
1556 u32 *reg = initial_reg;
1559 // ARM/Thumb mode is stored in the flags directly, this is simpler than
1560 // shadowing it since it has a constant 1bit represenation.
1562 char *reg_names[16] =
1564 " r0", " r1", " r2", " r3", " r4", " r5", " r6", " r7",
1565 " r8", " r9", "r10", " fp", " ip", " sp", " lr", " pc"
1568 char *cpu_mode_names[] =
1570 "user", "irq", "fiq", "svsr", "abrt", "undf", "invd"
1574 #define execute_arm_instruction() \
1575 using_instruction(arm); \
1576 check_pc_region(); \
1578 opcode = address32(pc_address_block, (pc & 0x7FFF)); \
1579 condition = opcode >> 28; \
1586 arm_next_instruction(); \
1592 arm_next_instruction(); \
1598 arm_next_instruction(); \
1604 arm_next_instruction(); \
1610 arm_next_instruction(); \
1616 arm_next_instruction(); \
1622 arm_next_instruction(); \
1628 arm_next_instruction(); \
1633 if((c_flag == 0) | z_flag) \
1634 arm_next_instruction(); \
1639 if(c_flag & (z_flag ^ 1)) \
1640 arm_next_instruction(); \
1645 if(n_flag != v_flag) \
1646 arm_next_instruction(); \
1651 if(n_flag == v_flag) \
1652 arm_next_instruction(); \
1657 if(z_flag | (n_flag != v_flag)) \
1658 arm_next_instruction(); \
1663 if((z_flag == 0) & (n_flag == v_flag)) \
1664 arm_next_instruction(); \
1672 /* Reserved - treat as "never" */ \
1674 arm_next_instruction(); \
1678 switch((opcode >> 20) & 0xFF) \
1681 if((opcode & 0x90) == 0x90) \
1685 /* STRH rd, [rn], -rm */ \
1686 arm_access_memory(store, no_op, half_reg, u16, yes, - reg[rm]); \
1690 /* MUL rd, rm, rs */ \
1691 arm_multiply(no_op, no); \
1696 /* AND rd, rn, reg_op */ \
1697 arm_data_proc(reg[rn] & reg_sh, reg); \
1702 if((opcode & 0x90) == 0x90) \
1704 switch((opcode >> 5) & 0x03) \
1707 /* MULS rd, rm, rs */ \
1708 arm_multiply(no_op, yes); \
1712 /* LDRH rd, [rn], -rm */ \
1713 arm_access_memory(load, no_op, half_reg, u16, yes, - reg[rm]); \
1717 /* LDRSB rd, [rn], -rm */ \
1718 arm_access_memory(load, no_op, half_reg, s8, yes, - reg[rm]); \
1722 /* LDRSH rd, [rn], -rm */ \
1723 arm_access_memory(load, no_op, half_reg, s16, yes, - reg[rm]); \
1729 /* ANDS rd, rn, reg_op */ \
1730 arm_data_proc_logic_flags(reg[rn] & reg_sh, reg); \
1735 if((opcode & 0x90) == 0x90) \
1739 /* STRH rd, [rn], -rm */ \
1740 arm_access_memory(store, no_op, half_reg, u16, yes, - reg[rm]); \
1744 /* MLA rd, rm, rs, rn */ \
1745 arm_multiply(+ reg[rn], no); \
1750 /* EOR rd, rn, reg_op */ \
1751 arm_data_proc(reg[rn] ^ reg_sh, reg); \
1756 if((opcode & 0x90) == 0x90) \
1758 switch((opcode >> 5) & 0x03) \
1761 /* MLAS rd, rm, rs, rn */ \
1762 arm_multiply(+ reg[rn], yes); \
1766 /* LDRH rd, [rn], -rm */ \
1767 arm_access_memory(load, no_op, half_reg, u16, yes, - reg[rm]); \
1771 /* LDRSB rd, [rn], -rm */ \
1772 arm_access_memory(load, no_op, half_reg, s8, yes, - reg[rm]); \
1776 /* LDRSH rd, [rn], -rm */ \
1777 arm_access_memory(load, no_op, half_reg, s16, yes, - reg[rm]); \
1783 /* EORS rd, rn, reg_op */ \
1784 arm_data_proc_logic_flags(reg[rn] ^ reg_sh, reg); \
1789 if((opcode & 0x90) == 0x90) \
1791 /* STRH rd, [rn], -imm */ \
1792 arm_access_memory(store, no_op, half_imm, u16, yes, - offset); \
1796 /* SUB rd, rn, reg_op */ \
1797 arm_data_proc(reg[rn] - reg_sh, reg); \
1802 if((opcode & 0x90) == 0x90) \
1804 switch((opcode >> 5) & 0x03) \
1807 /* LDRH rd, [rn], -imm */ \
1808 arm_access_memory(load, no_op, half_imm, u16, yes, - offset); \
1812 /* LDRSB rd, [rn], -imm */ \
1813 arm_access_memory(load, no_op, half_imm, s8, yes, - offset); \
1817 /* LDRSH rd, [rn], -imm */ \
1818 arm_access_memory(load, no_op, half_imm, s16, yes, - offset); \
1824 /* SUBS rd, rn, reg_op */ \
1825 arm_data_proc_sub_flags(reg[rn], reg_sh, reg); \
1830 if((opcode & 0x90) == 0x90) \
1832 /* STRH rd, [rn], -imm */ \
1833 arm_access_memory(store, no_op, half_imm, u16, yes, - offset); \
1837 /* RSB rd, rn, reg_op */ \
1838 arm_data_proc(reg_sh - reg[rn], reg); \
1843 if((opcode & 0x90) == 0x90) \
1845 switch((opcode >> 5) & 0x03) \
1848 /* LDRH rd, [rn], -imm */ \
1849 arm_access_memory(load, no_op, half_imm, u16, yes, - offset); \
1853 /* LDRSB rd, [rn], -imm */ \
1854 arm_access_memory(load, no_op, half_imm, s8, yes, - offset); \
1858 /* LDRSH rd, [rn], -imm */ \
1859 arm_access_memory(load, no_op, half_imm, s16, yes, - offset); \
1865 /* RSBS rd, rn, reg_op */ \
1866 arm_data_proc_sub_flags(reg_sh, reg[rn], reg); \
1871 if((opcode & 0x90) == 0x90) \
1875 /* STRH rd, [rn], +rm */ \
1876 arm_access_memory(store, no_op, half_reg, u16, yes, + reg[rm]); \
1880 /* UMULL rd, rm, rs */ \
1881 arm_multiply_long(no_op, no, u); \
1886 /* ADD rd, rn, reg_op */ \
1887 arm_data_proc(reg[rn] + reg_sh, reg); \
1892 if((opcode & 0x90) == 0x90) \
1894 switch((opcode >> 5) & 0x03) \
1897 /* UMULLS rdlo, rdhi, rm, rs */ \
1898 arm_multiply_long(no_op, yes, u); \
1902 /* LDRH rd, [rn], +rm */ \
1903 arm_access_memory(load, no_op, half_reg, u16, yes, + reg[rm]); \
1907 /* LDRSB rd, [rn], +rm */ \
1908 arm_access_memory(load, no_op, half_reg, s8, yes, + reg[rm]); \
1912 /* LDRSH rd, [rn], +rm */ \
1913 arm_access_memory(load, no_op, half_reg, s16, yes, + reg[rm]); \
1919 /* ADDS rd, rn, reg_op */ \
1920 arm_data_proc_add_flags(reg[rn], reg_sh, reg); \
1925 if((opcode & 0x90) == 0x90) \
1929 /* STRH rd, [rn], +rm */ \
1930 arm_access_memory(store, no_op, half_reg, u16, yes, + reg[rm]); \
1934 /* UMLAL rd, rm, rs */ \
1935 arm_multiply_long(arm_multiply_long_addop(u), no, u); \
1940 /* ADC rd, rn, reg_op */ \
1941 arm_data_proc(reg[rn] + reg_sh + c_flag, reg); \
1946 if((opcode & 0x90) == 0x90) \
1948 switch((opcode >> 5) & 0x03) \
1951 /* UMLALS rdlo, rdhi, rm, rs */ \
1952 arm_multiply_long(arm_multiply_long_addop(u), yes, u); \
1956 /* LDRH rd, [rn], +rm */ \
1957 arm_access_memory(load, no_op, half_reg, u16, yes, + reg[rm]); \
1961 /* LDRSB rd, [rn], +rm */ \
1962 arm_access_memory(load, no_op, half_reg, s8, yes, + reg[rm]); \
1966 /* LDRSH rd, [rn], +rm */ \
1967 arm_access_memory(load, no_op, half_reg, s16, yes, + reg[rm]); \
1973 /* ADCS rd, rn, reg_op */ \
1974 arm_data_proc_add_flags(reg[rn], reg_sh + c_flag, reg); \
1979 if((opcode & 0x90) == 0x90) \
1983 /* STRH rd, [rn], +imm */ \
1984 arm_access_memory(store, no_op, half_imm, u16, yes, + offset); \
1988 /* SMULL rd, rm, rs */ \
1989 arm_multiply_long(no_op, no, s); \
1994 /* SBC rd, rn, reg_op */ \
1995 arm_data_proc(reg[rn] - (reg_sh + (c_flag ^ 1)), reg); \
2000 if((opcode & 0x90) == 0x90) \
2002 switch((opcode >> 5) & 0x03) \
2005 /* SMULLS rdlo, rdhi, rm, rs */ \
2006 arm_multiply_long(no_op, yes, s); \
2010 /* LDRH rd, [rn], +imm */ \
2011 arm_access_memory(load, no_op, half_imm, u16, yes, + offset); \
2015 /* LDRSB rd, [rn], +imm */ \
2016 arm_access_memory(load, no_op, half_imm, s8, yes, + offset); \
2020 /* LDRSH rd, [rn], +imm */ \
2021 arm_access_memory(load, no_op, half_imm, s16, yes, + offset); \
2027 /* SBCS rd, rn, reg_op */ \
2028 arm_data_proc_sub_flags(reg[rn], (reg_sh + (c_flag ^ 1)), reg); \
2033 if((opcode & 0x90) == 0x90) \
2037 /* STRH rd, [rn], +imm */ \
2038 arm_access_memory(store, no_op, half_imm, u16, yes, + offset); \
2042 /* SMLAL rd, rm, rs */ \
2043 arm_multiply_long(arm_multiply_long_addop(s), no, s); \
2048 /* RSC rd, rn, reg_op */ \
2049 arm_data_proc(reg_sh - reg[rn] + c_flag - 1, reg); \
2054 if((opcode & 0x90) == 0x90) \
2056 switch((opcode >> 5) & 0x03) \
2059 /* SMLALS rdlo, rdhi, rm, rs */ \
2060 arm_multiply_long(arm_multiply_long_addop(s), yes, s); \
2064 /* LDRH rd, [rn], +imm */ \
2065 arm_access_memory(load, no_op, half_imm, u16, yes, + offset); \
2069 /* LDRSB rd, [rn], +imm */ \
2070 arm_access_memory(load, no_op, half_imm, s8, yes, + offset); \
2074 /* LDRSH rd, [rn], +imm */ \
2075 arm_access_memory(load, no_op, half_imm, s16, yes, + offset); \
2081 /* RSCS rd, rn, reg_op */ \
2082 arm_data_proc_sub_flags((reg_sh + c_flag - 1), reg[rn], reg); \
2087 if((opcode & 0x90) == 0x90) \
2091 /* STRH rd, [rn - rm] */ \
2092 arm_access_memory(store, - reg[rm], half_reg, u16, no, no_op); \
2096 /* SWP rd, rm, [rn] */ \
2102 /* MRS rd, cpsr */ \
2103 arm_psr(reg, read, reg[REG_CPSR]); \
2108 if((opcode & 0x90) == 0x90) \
2110 switch((opcode >> 5) & 0x03) \
2113 /* LDRH rd, [rn - rm] */ \
2114 arm_access_memory(load, - reg[rm], half_reg, u16, no, no_op); \
2118 /* LDRSB rd, [rn - rm] */ \
2119 arm_access_memory(load, - reg[rm], half_reg, s8, no, no_op); \
2123 /* LDRSH rd, [rn - rm] */ \
2124 arm_access_memory(load, - reg[rm], half_reg, s16, no, no_op); \
2130 /* TST rd, rn, reg_op */ \
2131 arm_data_proc_test_logic(reg[rn] & reg_sh, reg); \
2136 if((opcode & 0x90) == 0x90) \
2138 /* STRH rd, [rn - rm]! */ \
2139 arm_access_memory(store, - reg[rm], half_reg, u16, yes, no_op); \
2146 arm_decode_branchx(); \
2147 u32 src = reg[rn]; \
2151 arm_pc_offset_update_direct(src); \
2152 reg[REG_CPSR] |= 0x20; \
2157 arm_pc_offset_update_direct(src); \
2162 /* MSR cpsr, rm */ \
2163 arm_psr(reg, store, cpsr); \
2169 if((opcode & 0x90) == 0x90) \
2171 switch((opcode >> 5) & 0x03) \
2174 /* LDRH rd, [rn - rm]! */ \
2175 arm_access_memory(load, - reg[rm], half_reg, u16, yes, no_op); \
2179 /* LDRSB rd, [rn - rm]! */ \
2180 arm_access_memory(load, - reg[rm], half_reg, s8, yes, no_op); \
2184 /* LDRSH rd, [rn - rm]! */ \
2185 arm_access_memory(load, - reg[rm], half_reg, s16, yes, no_op); \
2191 /* TEQ rd, rn, reg_op */ \
2192 arm_data_proc_test_logic(reg[rn] ^ reg_sh, reg); \
2197 if((opcode & 0x90) == 0x90) \
2201 /* STRH rd, [rn - imm] */ \
2202 arm_access_memory(store, - offset, half_imm, u16, no, no_op); \
2206 /* SWPB rd, rm, [rn] */ \
2212 /* MRS rd, spsr */ \
2213 arm_psr(reg, read, spsr[reg[CPU_MODE]]); \
2218 if((opcode & 0x90) == 0x90) \
2220 switch((opcode >> 5) & 0x03) \
2223 /* LDRH rd, [rn - imm] */ \
2224 arm_access_memory(load, - offset, half_imm, u16, no, no_op); \
2228 /* LDRSB rd, [rn - imm] */ \
2229 arm_access_memory(load, - offset, half_imm, s8, no, no_op); \
2233 /* LDRSH rd, [rn - imm] */ \
2234 arm_access_memory(load, - offset, half_imm, s16, no, no_op); \
2240 /* CMP rn, reg_op */ \
2241 arm_data_proc_test_sub(reg[rn], reg_sh, reg); \
2246 if((opcode & 0x90) == 0x90) \
2248 /* STRH rd, [rn - imm]! */ \
2249 arm_access_memory(store, - offset, half_imm, u16, yes, no_op); \
2253 /* MSR spsr, rm */ \
2254 arm_psr(reg, store, spsr); \
2259 if((opcode & 0x90) == 0x90) \
2261 switch((opcode >> 5) & 0x03) \
2264 /* LDRH rd, [rn - imm]! */ \
2265 arm_access_memory(load, - offset, half_imm, u16, yes, no_op); \
2269 /* LDRSB rd, [rn - imm]! */ \
2270 arm_access_memory(load, - offset, half_imm, s8, yes, no_op); \
2274 /* LDRSH rd, [rn - imm]! */ \
2275 arm_access_memory(load, - offset, half_imm, s16, yes, no_op); \
2281 /* CMN rd, rn, reg_op */ \
2282 arm_data_proc_test_add(reg[rn], reg_sh, reg); \
2287 if((opcode & 0x90) == 0x90) \
2289 /* STRH rd, [rn + rm] */ \
2290 arm_access_memory(store, + reg[rm], half_reg, u16, no, no_op); \
2294 /* ORR rd, rn, reg_op */ \
2295 arm_data_proc(reg[rn] | reg_sh, reg); \
2300 if((opcode & 0x90) == 0x90) \
2302 switch((opcode >> 5) & 0x03) \
2305 /* LDRH rd, [rn + rm] */ \
2306 arm_access_memory(load, + reg[rm], half_reg, u16, no, no_op); \
2310 /* LDRSB rd, [rn + rm] */ \
2311 arm_access_memory(load, + reg[rm], half_reg, s8, no, no_op); \
2315 /* LDRSH rd, [rn + rm] */ \
2316 arm_access_memory(load, + reg[rm], half_reg, s16, no, no_op); \
2322 /* ORRS rd, rn, reg_op */ \
2323 arm_data_proc_logic_flags(reg[rn] | reg_sh, reg); \
2328 if((opcode & 0x90) == 0x90) \
2330 /* STRH rd, [rn + rm]! */ \
2331 arm_access_memory(store, + reg[rm], half_reg, u16, yes, no_op); \
2335 /* MOV rd, reg_op */ \
2336 arm_data_proc(reg_sh, reg); \
2341 if((opcode & 0x90) == 0x90) \
2343 switch((opcode >> 5) & 0x03) \
2346 /* LDRH rd, [rn + rm]! */ \
2347 arm_access_memory(load, + reg[rm], half_reg, u16, yes, no_op); \
2351 /* LDRSB rd, [rn + rm]! */ \
2352 arm_access_memory(load, + reg[rm], half_reg, s8, yes, no_op); \
2356 /* LDRSH rd, [rn + rm]! */ \
2357 arm_access_memory(load, + reg[rm], half_reg, s16, yes, no_op); \
2363 /* MOVS rd, reg_op */ \
2364 arm_data_proc_logic_flags(reg_sh, reg); \
2369 if((opcode & 0x90) == 0x90) \
2371 /* STRH rd, [rn + imm] */ \
2372 arm_access_memory(store, + offset, half_imm, u16, no, no_op); \
2376 /* BIC rd, rn, reg_op */ \
2377 arm_data_proc(reg[rn] & (~reg_sh), reg); \
2382 if((opcode & 0x90) == 0x90) \
2384 switch((opcode >> 5) & 0x03) \
2387 /* LDRH rd, [rn + imm] */ \
2388 arm_access_memory(load, + offset, half_imm, u16, no, no_op); \
2392 /* LDRSB rd, [rn + imm] */ \
2393 arm_access_memory(load, + offset, half_imm, s8, no, no_op); \
2397 /* LDRSH rd, [rn + imm] */ \
2398 arm_access_memory(load, + offset, half_imm, s16, no, no_op); \
2404 /* BICS rd, rn, reg_op */ \
2405 arm_data_proc_logic_flags(reg[rn] & (~reg_sh), reg); \
2410 if((opcode & 0x90) == 0x90) \
2412 /* STRH rd, [rn + imm]! */ \
2413 arm_access_memory(store, + offset, half_imm, u16, yes, no_op); \
2417 /* MVN rd, reg_op */ \
2418 arm_data_proc(~reg_sh, reg); \
2423 if((opcode & 0x90) == 0x90) \
2425 switch((opcode >> 5) & 0x03) \
2428 /* LDRH rd, [rn + imm]! */ \
2429 arm_access_memory(load, + offset, half_imm, u16, yes, no_op); \
2433 /* LDRSB rd, [rn + imm]! */ \
2434 arm_access_memory(load, + offset, half_imm, s8, yes, no_op); \
2438 /* LDRSH rd, [rn + imm]! */ \
2439 arm_access_memory(load, + offset, half_imm, s16, yes, no_op); \
2445 /* MVNS rd, rn, reg_op */ \
2446 arm_data_proc_logic_flags(~reg_sh, reg); \
2451 /* AND rd, rn, imm */ \
2452 arm_data_proc(reg[rn] & imm, imm); \
2456 /* ANDS rd, rn, imm */ \
2457 arm_data_proc_logic_flags(reg[rn] & imm, imm); \
2461 /* EOR rd, rn, imm */ \
2462 arm_data_proc(reg[rn] ^ imm, imm); \
2466 /* EORS rd, rn, imm */ \
2467 arm_data_proc_logic_flags(reg[rn] ^ imm, imm); \
2471 /* SUB rd, rn, imm */ \
2472 arm_data_proc(reg[rn] - imm, imm); \
2476 /* SUBS rd, rn, imm */ \
2477 arm_data_proc_sub_flags(reg[rn], imm, imm); \
2481 /* RSB rd, rn, imm */ \
2482 arm_data_proc(imm - reg[rn], imm); \
2486 /* RSBS rd, rn, imm */ \
2487 arm_data_proc_sub_flags(imm, reg[rn], imm); \
2491 /* ADD rd, rn, imm */ \
2492 arm_data_proc(reg[rn] + imm, imm); \
2496 /* ADDS rd, rn, imm */ \
2497 arm_data_proc_add_flags(reg[rn], imm, imm); \
2501 /* ADC rd, rn, imm */ \
2502 arm_data_proc(reg[rn] + imm + c_flag, imm); \
2506 /* ADCS rd, rn, imm */ \
2507 arm_data_proc_add_flags(reg[rn] + imm, c_flag, imm); \
2511 /* SBC rd, rn, imm */ \
2512 arm_data_proc(reg[rn] - imm + c_flag - 1, imm); \
2516 /* SBCS rd, rn, imm */ \
2517 arm_data_proc_sub_flags(reg[rn], (imm + (c_flag ^ 1)), imm); \
2521 /* RSC rd, rn, imm */ \
2522 arm_data_proc(imm - reg[rn] + c_flag - 1, imm); \
2526 /* RSCS rd, rn, imm */ \
2527 arm_data_proc_sub_flags((imm + c_flag - 1), reg[rn], imm); \
2530 case 0x30 ... 0x31: \
2532 arm_data_proc_test_logic(reg[rn] & imm, imm); \
2536 /* MSR cpsr, imm */ \
2537 arm_psr(imm, store, cpsr); \
2542 arm_data_proc_test_logic(reg[rn] ^ imm, imm); \
2545 case 0x34 ... 0x35: \
2547 arm_data_proc_test_sub(reg[rn], imm, imm); \
2551 /* MSR spsr, imm */ \
2552 arm_psr(imm, store, spsr); \
2557 arm_data_proc_test_add(reg[rn], imm, imm); \
2561 /* ORR rd, rn, imm */ \
2562 arm_data_proc(reg[rn] | imm, imm); \
2566 /* ORRS rd, rn, imm */ \
2567 arm_data_proc_logic_flags(reg[rn] | imm, imm); \
2572 arm_data_proc(imm, imm); \
2576 /* MOVS rd, imm */ \
2577 arm_data_proc_logic_flags(imm, imm); \
2581 /* BIC rd, rn, imm */ \
2582 arm_data_proc(reg[rn] & (~imm), imm); \
2586 /* BICS rd, rn, imm */ \
2587 arm_data_proc_logic_flags(reg[rn] & (~imm), imm); \
2592 arm_data_proc(~imm, imm); \
2596 /* MVNS rd, imm */ \
2597 arm_data_proc_logic_flags(~imm, imm); \
2601 /* STR rd, [rn], -imm */ \
2602 arm_access_memory(store, no_op, imm, u32, yes, - offset); \
2606 /* LDR rd, [rn], -imm */ \
2607 arm_access_memory(load, no_op, imm, u32, yes, - offset); \
2611 /* STRT rd, [rn], -imm */ \
2612 arm_access_memory(store, no_op, imm, u32, yes, - offset); \
2616 /* LDRT rd, [rn], -imm */ \
2617 arm_access_memory(load, no_op, imm, u32, yes, - offset); \
2621 /* STRB rd, [rn], -imm */ \
2622 arm_access_memory(store, no_op, imm, u8, yes, - offset); \
2626 /* LDRB rd, [rn], -imm */ \
2627 arm_access_memory(load, no_op, imm, u8, yes, - offset); \
2631 /* STRBT rd, [rn], -imm */ \
2632 arm_access_memory(store, no_op, imm, u8, yes, - offset); \
2636 /* LDRBT rd, [rn], -imm */ \
2637 arm_access_memory(load, no_op, imm, u8, yes, - offset); \
2641 /* STR rd, [rn], +imm */ \
2642 arm_access_memory(store, no_op, imm, u32, yes, + offset); \
2646 /* LDR rd, [rn], +imm */ \
2647 arm_access_memory(load, no_op, imm, u32, yes, + offset); \
2651 /* STRT rd, [rn], +imm */ \
2652 arm_access_memory(store, no_op, imm, u32, yes, + offset); \
2656 /* LDRT rd, [rn], +imm */ \
2657 arm_access_memory(load, no_op, imm, u32, yes, + offset); \
2661 /* STRB rd, [rn], +imm */ \
2662 arm_access_memory(store, no_op, imm, u8, yes, + offset); \
2666 /* LDRB rd, [rn], +imm */ \
2667 arm_access_memory(load, no_op, imm, u8, yes, + offset); \
2671 /* STRBT rd, [rn], +imm */ \
2672 arm_access_memory(store, no_op, imm, u8, yes, + offset); \
2676 /* LDRBT rd, [rn], +imm */ \
2677 arm_access_memory(load, no_op, imm, u8, yes, + offset); \
2681 /* STR rd, [rn - imm] */ \
2682 arm_access_memory(store, - offset, imm, u32, no, no_op); \
2686 /* LDR rd, [rn - imm] */ \
2687 arm_access_memory(load, - offset, imm, u32, no, no_op); \
2691 /* STR rd, [rn - imm]! */ \
2692 arm_access_memory(store, - offset, imm, u32, yes, no_op); \
2696 /* LDR rd, [rn - imm]! */ \
2697 arm_access_memory(load, - offset, imm, u32, yes, no_op); \
2701 /* STRB rd, [rn - imm] */ \
2702 arm_access_memory(store, - offset, imm, u8, no, no_op); \
2706 /* LDRB rd, [rn - imm] */ \
2707 arm_access_memory(load, - offset, imm, u8, no, no_op); \
2711 /* STRB rd, [rn - imm]! */ \
2712 arm_access_memory(store, - offset, imm, u8, yes, no_op); \
2716 /* LDRB rd, [rn - imm]! */ \
2717 arm_access_memory(load, - offset, imm, u8, yes, no_op); \
2721 /* STR rd, [rn + imm] */ \
2722 arm_access_memory(store, + offset, imm, u32, no, no_op); \
2726 /* LDR rd, [rn + imm] */ \
2727 arm_access_memory(load, + offset, imm, u32, no, no_op); \
2731 /* STR rd, [rn + imm]! */ \
2732 arm_access_memory(store, + offset, imm, u32, yes, no_op); \
2736 /* LDR rd, [rn + imm]! */ \
2737 arm_access_memory(load, + offset, imm, u32, yes, no_op); \
2741 /* STRB rd, [rn + imm] */ \
2742 arm_access_memory(store, + offset, imm, u8, no, no_op); \
2746 /* LDRB rd, [rn + imm] */ \
2747 arm_access_memory(load, + offset, imm, u8, no, no_op); \
2751 /* STRB rd, [rn + imm]! */ \
2752 arm_access_memory(store, + offset, imm, u8, yes, no_op); \
2756 /* LDRBT rd, [rn + imm]! */ \
2757 arm_access_memory(load, + offset, imm, u8, yes, no_op); \
2761 /* STR rd, [rn], -reg_op */ \
2762 arm_access_memory(store, no_op, reg, u32, yes, - reg_offset); \
2766 /* LDR rd, [rn], -reg_op */ \
2767 arm_access_memory(load, no_op, reg, u32, yes, - reg_offset); \
2771 /* STRT rd, [rn], -reg_op */ \
2772 arm_access_memory(store, no_op, reg, u32, yes, - reg_offset); \
2776 /* LDRT rd, [rn], -reg_op */ \
2777 arm_access_memory(load, no_op, reg, u32, yes, - reg_offset); \
2781 /* STRB rd, [rn], -reg_op */ \
2782 arm_access_memory(store, no_op, reg, u8, yes, - reg_offset); \
2786 /* LDRB rd, [rn], -reg_op */ \
2787 arm_access_memory(load, no_op, reg, u8, yes, - reg_offset); \
2791 /* STRBT rd, [rn], -reg_op */ \
2792 arm_access_memory(store, no_op, reg, u8, yes, - reg_offset); \
2796 /* LDRBT rd, [rn], -reg_op */ \
2797 arm_access_memory(load, no_op, reg, u8, yes, - reg_offset); \
2801 /* STR rd, [rn], +reg_op */ \
2802 arm_access_memory(store, no_op, reg, u32, yes, + reg_offset); \
2806 /* LDR rd, [rn], +reg_op */ \
2807 arm_access_memory(load, no_op, reg, u32, yes, + reg_offset); \
2811 /* STRT rd, [rn], +reg_op */ \
2812 arm_access_memory(store, no_op, reg, u32, yes, + reg_offset); \
2816 /* LDRT rd, [rn], +reg_op */ \
2817 arm_access_memory(load, no_op, reg, u32, yes, + reg_offset); \
2821 /* STRB rd, [rn], +reg_op */ \
2822 arm_access_memory(store, no_op, reg, u8, yes, + reg_offset); \
2826 /* LDRB rd, [rn], +reg_op */ \
2827 arm_access_memory(load, no_op, reg, u8, yes, + reg_offset); \
2831 /* STRBT rd, [rn], +reg_op */ \
2832 arm_access_memory(store, no_op, reg, u8, yes, + reg_offset); \
2836 /* LDRBT rd, [rn], +reg_op */ \
2837 arm_access_memory(load, no_op, reg, u8, yes, + reg_offset); \
2841 /* STR rd, [rn - reg_op] */ \
2842 arm_access_memory(store, - reg_offset, reg, u32, no, no_op); \
2846 /* LDR rd, [rn - reg_op] */ \
2847 arm_access_memory(load, - reg_offset, reg, u32, no, no_op); \
2851 /* STR rd, [rn - reg_op]! */ \
2852 arm_access_memory(store, - reg_offset, reg, u32, yes, no_op); \
2856 /* LDR rd, [rn - reg_op]! */ \
2857 arm_access_memory(load, - reg_offset, reg, u32, yes, no_op); \
2861 /* STRB rd, [rn - reg_op] */ \
2862 arm_access_memory(store, - reg_offset, reg, u8, no, no_op); \
2866 /* LDRB rd, [rn - reg_op] */ \
2867 arm_access_memory(load, - reg_offset, reg, u8, no, no_op); \
2871 /* STRB rd, [rn - reg_op]! */ \
2872 arm_access_memory(store, - reg_offset, reg, u8, yes, no_op); \
2876 /* LDRB rd, [rn - reg_op]! */ \
2877 arm_access_memory(load, - reg_offset, reg, u8, yes, no_op); \
2881 /* STR rd, [rn + reg_op] */ \
2882 arm_access_memory(store, + reg_offset, reg, u32, no, no_op); \
2886 /* LDR rd, [rn + reg_op] */ \
2887 arm_access_memory(load, + reg_offset, reg, u32, no, no_op); \
2891 /* STR rd, [rn + reg_op]! */ \
2892 arm_access_memory(store, + reg_offset, reg, u32, yes, no_op); \
2896 /* LDR rd, [rn + reg_op]! */ \
2897 arm_access_memory(load, + reg_offset, reg, u32, yes, no_op); \
2901 /* STRB rd, [rn + reg_op] */ \
2902 arm_access_memory(store, + reg_offset, reg, u8, no, no_op); \
2906 /* LDRB rd, [rn + reg_op] */ \
2907 arm_access_memory(load, + reg_offset, reg, u8, no, no_op); \
2911 /* STRB rd, [rn + reg_op]! */ \
2912 arm_access_memory(store, + reg_offset, reg, u8, yes, no_op); \
2916 /* LDRBT rd, [rn + reg_op]! */ \
2917 arm_access_memory(load, + reg_offset, reg, u8, yes, no_op); \
2921 /* STMDA rn, rlist */ \
2922 arm_block_memory(store, down_a, no, no); \
2926 /* LDMDA rn, rlist */ \
2927 arm_block_memory(load, down_a, no, no); \
2931 /* STMDA rn!, rlist */ \
2932 arm_block_memory(store, down_a, down, no); \
2936 /* LDMDA rn!, rlist */ \
2937 arm_block_memory(load, down_a, down, no); \
2941 /* STMDA rn, rlist^ */ \
2942 arm_block_memory(store, down_a, no, yes); \
2946 /* LDMDA rn, rlist^ */ \
2947 arm_block_memory(load, down_a, no, yes); \
2951 /* STMDA rn!, rlist^ */ \
2952 arm_block_memory(store, down_a, down, yes); \
2956 /* LDMDA rn!, rlist^ */ \
2957 arm_block_memory(load, down_a, down, yes); \
2961 /* STMIA rn, rlist */ \
2962 arm_block_memory(store, no, no, no); \
2966 /* LDMIA rn, rlist */ \
2967 arm_block_memory(load, no, no, no); \
2971 /* STMIA rn!, rlist */ \
2972 arm_block_memory(store, no, up, no); \
2976 /* LDMIA rn!, rlist */ \
2977 arm_block_memory(load, no, up, no); \
2981 /* STMIA rn, rlist^ */ \
2982 arm_block_memory(store, no, no, yes); \
2986 /* LDMIA rn, rlist^ */ \
2987 arm_block_memory(load, no, no, yes); \
2991 /* STMIA rn!, rlist^ */ \
2992 arm_block_memory(store, no, up, yes); \
2996 /* LDMIA rn!, rlist^ */ \
2997 arm_block_memory(load, no, up, yes); \
3001 /* STMDB rn, rlist */ \
3002 arm_block_memory(store, down_b, no, no); \
3006 /* LDMDB rn, rlist */ \
3007 arm_block_memory(load, down_b, no, no); \
3011 /* STMDB rn!, rlist */ \
3012 arm_block_memory(store, down_b, down, no); \
3016 /* LDMDB rn!, rlist */ \
3017 arm_block_memory(load, down_b, down, no); \
3021 /* STMDB rn, rlist^ */ \
3022 arm_block_memory(store, down_b, no, yes); \
3026 /* LDMDB rn, rlist^ */ \
3027 arm_block_memory(load, down_b, no, yes); \
3031 /* STMDB rn!, rlist^ */ \
3032 arm_block_memory(store, down_b, down, yes); \
3036 /* LDMDB rn!, rlist^ */ \
3037 arm_block_memory(load, down_b, down, yes); \
3041 /* STMIB rn, rlist */ \
3042 arm_block_memory(store, up, no, no); \
3046 /* LDMIB rn, rlist */ \
3047 arm_block_memory(load, up, no, no); \
3051 /* STMIB rn!, rlist */ \
3052 arm_block_memory(store, up, up, no); \
3056 /* LDMIB rn!, rlist */ \
3057 arm_block_memory(load, up, up, no); \
3061 /* STMIB rn, rlist^ */ \
3062 arm_block_memory(store, up, no, yes); \
3066 /* LDMIB rn, rlist^ */ \
3067 arm_block_memory(load, up, no, yes); \
3071 /* STMIB rn!, rlist^ */ \
3072 arm_block_memory(store, up, up, yes); \
3076 /* LDMIB rn!, rlist^ */ \
3077 arm_block_memory(load, up, up, yes); \
3098 arm_decode_branch(); \
3099 arm_pc_offset_update(offset + 8); \
3103 case 0xB0 ... 0xBF: \
3106 arm_decode_branch(); \
3107 reg[REG_LR] = pc + 4; \
3108 arm_pc_offset_update(offset + 8); \
3112 case 0xC0 ... 0xEF: \
3113 /* coprocessor instructions, reserved on GBA */ \
3116 case 0xF0 ... 0xFF: \
3119 u32 swi_comment = opcode & 0x00FFFFFF; \
3121 switch(swi_comment >> 16) \
3123 /* Jump to BIOS SWI handler */ \
3125 reg_mode[MODE_SUPERVISOR][6] = pc + 4; \
3127 spsr[MODE_SUPERVISOR] = reg[REG_CPSR]; \
3128 reg[REG_PC] = 0x00000008; \
3130 reg[REG_CPSR] = (reg[REG_CPSR] & ~0x1F) | 0x13; \
3131 set_cpu_mode(MODE_SUPERVISOR); \
3140 #define execute_thumb_instruction() \
3141 using_instruction(thumb); \
3142 check_pc_region(); \
3144 opcode = address16(pc_address_block, (pc & 0x7FFF)); \
3146 switch((opcode >> 8) & 0xFF) \
3148 case 0x00 ... 0x07: \
3149 /* LSL rd, rs, offset */ \
3150 thumb_shift(shift, lsl, imm); \
3153 case 0x08 ... 0x0F: \
3154 /* LSR rd, rs, offset */ \
3155 thumb_shift(shift, lsr, imm); \
3158 case 0x10 ... 0x17: \
3159 /* ASR rd, rs, offset */ \
3160 thumb_shift(shift, asr, imm); \
3163 case 0x18 ... 0x19: \
3164 /* ADD rd, rs, rn */ \
3165 thumb_add(add_sub, rd, reg[rs], reg[rn]); \
3168 case 0x1A ... 0x1B: \
3169 /* SUB rd, rs, rn */ \
3170 thumb_sub(add_sub, rd, reg[rs], reg[rn]); \
3173 case 0x1C ... 0x1D: \
3174 /* ADD rd, rs, imm */ \
3175 thumb_add(add_sub_imm, rd, reg[rs], imm); \
3178 case 0x1E ... 0x1F: \
3179 /* SUB rd, rs, imm */ \
3180 thumb_sub(add_sub_imm, rd, reg[rs], imm); \
3185 thumb_logic(imm, 0, imm); \
3190 thumb_logic(imm, 1, imm); \
3195 thumb_logic(imm, 2, imm); \
3200 thumb_logic(imm, 3, imm); \
3205 thumb_logic(imm, 4, imm); \
3210 thumb_logic(imm, 5, imm); \
3215 thumb_logic(imm, 6, imm); \
3220 thumb_logic(imm, 7, imm); \
3225 thumb_test_sub(imm, reg[0], imm); \
3230 thumb_test_sub(imm, reg[1], imm); \
3235 thumb_test_sub(imm, reg[2], imm); \
3240 thumb_test_sub(imm, reg[3], imm); \
3245 thumb_test_sub(imm, reg[4], imm); \
3250 thumb_test_sub(imm, reg[5], imm); \
3255 thumb_test_sub(imm, reg[6], imm); \
3260 thumb_test_sub(imm, reg[7], imm); \
3265 thumb_add(imm, 0, reg[0], imm); \
3270 thumb_add(imm, 1, reg[1], imm); \
3275 thumb_add(imm, 2, reg[2], imm); \
3280 thumb_add(imm, 3, reg[3], imm); \
3285 thumb_add(imm, 4, reg[4], imm); \
3290 thumb_add(imm, 5, reg[5], imm); \
3295 thumb_add(imm, 6, reg[6], imm); \
3300 thumb_add(imm, 7, reg[7], imm); \
3305 thumb_sub(imm, 0, reg[0], imm); \
3310 thumb_sub(imm, 1, reg[1], imm); \
3315 thumb_sub(imm, 2, reg[2], imm); \
3320 thumb_sub(imm, 3, reg[3], imm); \
3325 thumb_sub(imm, 4, reg[4], imm); \
3330 thumb_sub(imm, 5, reg[5], imm); \
3335 thumb_sub(imm, 6, reg[6], imm); \
3340 thumb_sub(imm, 7, reg[7], imm); \
3344 switch((opcode >> 6) & 0x03) \
3348 thumb_logic(alu_op, rd, reg[rd] & reg[rs]); \
3353 thumb_logic(alu_op, rd, reg[rd] ^ reg[rs]); \
3358 thumb_shift(alu_op, lsl, reg); \
3363 thumb_shift(alu_op, lsr, reg); \
3369 switch((opcode >> 6) & 0x03) \
3373 thumb_shift(alu_op, asr, reg); \
3378 thumb_add(alu_op, rd, reg[rd] + reg[rs], c_flag); \
3383 thumb_sub(alu_op, rd, reg[rd] - reg[rs], (c_flag ^ 1)); \
3388 thumb_shift(alu_op, ror, reg); \
3394 switch((opcode >> 6) & 0x03) \
3398 thumb_test_logic(alu_op, reg[rd] & reg[rs]); \
3403 thumb_sub(alu_op, rd, 0, reg[rs]); \
3408 thumb_test_sub(alu_op, reg[rd], reg[rs]); \
3413 thumb_test_add(alu_op, reg[rd], reg[rs]); \
3419 switch((opcode >> 6) & 0x03) \
3423 thumb_logic(alu_op, rd, reg[rd] | reg[rs]); \
3428 thumb_logic(alu_op, rd, reg[rd] * reg[rs]); \
3433 thumb_logic(alu_op, rd, reg[rd] & (~reg[rs])); \
3438 thumb_logic(alu_op, rd, ~reg[rs]); \
3445 thumb_hireg_op(reg[rd] + reg[rs]); \
3451 thumb_pc_offset(4); \
3452 thumb_decode_hireg_op(); \
3453 u32 _sa = reg[rd]; \
3454 u32 _sb = reg[rs]; \
3455 u32 dest = _sa - _sb; \
3456 thumb_pc_offset(-2); \
3457 calculate_flags_sub(dest, _sa, _sb); \
3463 thumb_hireg_op(reg[rs]); \
3469 thumb_decode_hireg_op(); \
3471 thumb_pc_offset(4); \
3476 thumb_pc_offset_update_direct(src); \
3480 /* Switch to ARM mode */ \
3481 thumb_pc_offset_update_direct(src); \
3482 reg[REG_CPSR] &= ~0x20; \
3490 /* LDR r0, [pc + imm] */ \
3491 thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[0], u32); \
3495 /* LDR r1, [pc + imm] */ \
3496 thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[1], u32); \
3500 /* LDR r2, [pc + imm] */ \
3501 thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[2], u32); \
3505 /* LDR r3, [pc + imm] */ \
3506 thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[3], u32); \
3510 /* LDR r4, [pc + imm] */ \
3511 thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[4], u32); \
3515 /* LDR r5, [pc + imm] */ \
3516 thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[5], u32); \
3520 /* LDR r6, [pc + imm] */ \
3521 thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[6], u32); \
3525 /* LDR r7, [pc + imm] */ \
3526 thumb_access_memory(load, imm, (pc & ~2) + (imm * 4) + 4, reg[7], u32); \
3529 case 0x50 ... 0x51: \
3530 /* STR rd, [rb + ro] */ \
3531 thumb_access_memory(store, mem_reg, reg[rb] + reg[ro], reg[rd], u32); \
3534 case 0x52 ... 0x53: \
3535 /* STRH rd, [rb + ro] */ \
3536 thumb_access_memory(store, mem_reg, reg[rb] + reg[ro], reg[rd], u16); \
3539 case 0x54 ... 0x55: \
3540 /* STRB rd, [rb + ro] */ \
3541 thumb_access_memory(store, mem_reg, reg[rb] + reg[ro], reg[rd], u8); \
3544 case 0x56 ... 0x57: \
3545 /* LDSB rd, [rb + ro] */ \
3546 thumb_access_memory(load, mem_reg, reg[rb] + reg[ro], reg[rd], s8); \
3549 case 0x58 ... 0x59: \
3550 /* LDR rd, [rb + ro] */ \
3551 thumb_access_memory(load, mem_reg, reg[rb] + reg[ro], reg[rd], u32); \
3554 case 0x5A ... 0x5B: \
3555 /* LDRH rd, [rb + ro] */ \
3556 thumb_access_memory(load, mem_reg, reg[rb] + reg[ro], reg[rd], u16); \
3559 case 0x5C ... 0x5D: \
3560 /* LDRB rd, [rb + ro] */ \
3561 thumb_access_memory(load, mem_reg, reg[rb] + reg[ro], reg[rd], u8); \
3564 case 0x5E ... 0x5F: \
3565 /* LDSH rd, [rb + ro] */ \
3566 thumb_access_memory(load, mem_reg, reg[rb] + reg[ro], reg[rd], s16); \
3569 case 0x60 ... 0x67: \
3570 /* STR rd, [rb + imm] */ \
3571 thumb_access_memory(store, mem_imm, reg[rb] + (imm * 4), reg[rd], u32); \
3574 case 0x68 ... 0x6F: \
3575 /* LDR rd, [rb + imm] */ \
3576 thumb_access_memory(load, mem_imm, reg[rb] + (imm * 4), reg[rd], u32); \
3579 case 0x70 ... 0x77: \
3580 /* STRB rd, [rb + imm] */ \
3581 thumb_access_memory(store, mem_imm, reg[rb] + imm, reg[rd], u8); \
3584 case 0x78 ... 0x7F: \
3585 /* LDRB rd, [rb + imm] */ \
3586 thumb_access_memory(load, mem_imm, reg[rb] + imm, reg[rd], u8); \
3589 case 0x80 ... 0x87: \
3590 /* STRH rd, [rb + imm] */ \
3591 thumb_access_memory(store, mem_imm, reg[rb] + (imm * 2), reg[rd], u16); \
3594 case 0x88 ... 0x8F: \
3595 /* LDRH rd, [rb + imm] */ \
3596 thumb_access_memory(load, mem_imm, reg[rb] + (imm * 2), reg[rd], u16); \
3600 /* STR r0, [sp + imm] */ \
3601 thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[0], u32); \
3605 /* STR r1, [sp + imm] */ \
3606 thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[1], u32); \
3610 /* STR r2, [sp + imm] */ \
3611 thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[2], u32); \
3615 /* STR r3, [sp + imm] */ \
3616 thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[3], u32); \
3620 /* STR r4, [sp + imm] */ \
3621 thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[4], u32); \
3625 /* STR r5, [sp + imm] */ \
3626 thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[5], u32); \
3630 /* STR r6, [sp + imm] */ \
3631 thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[6], u32); \
3635 /* STR r7, [sp + imm] */ \
3636 thumb_access_memory(store, imm, reg[REG_SP] + (imm * 4), reg[7], u32); \
3640 /* LDR r0, [sp + imm] */ \
3641 thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[0], u32); \
3645 /* LDR r1, [sp + imm] */ \
3646 thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[1], u32); \
3650 /* LDR r2, [sp + imm] */ \
3651 thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[2], u32); \
3655 /* LDR r3, [sp + imm] */ \
3656 thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[3], u32); \
3660 /* LDR r4, [sp + imm] */ \
3661 thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[4], u32); \
3665 /* LDR r5, [sp + imm] */ \
3666 thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[5], u32); \
3670 /* LDR r6, [sp + imm] */ \
3671 thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[6], u32); \
3675 /* LDR r7, [sp + imm] */ \
3676 thumb_access_memory(load, imm, reg[REG_SP] + (imm * 4), reg[7], u32); \
3680 /* ADD r0, pc, +imm */ \
3681 thumb_add_noflags(imm, 0, (pc & ~2) + 4, (imm * 4)); \
3685 /* ADD r1, pc, +imm */ \
3686 thumb_add_noflags(imm, 1, (pc & ~2) + 4, (imm * 4)); \
3690 /* ADD r2, pc, +imm */ \
3691 thumb_add_noflags(imm, 2, (pc & ~2) + 4, (imm * 4)); \
3695 /* ADD r3, pc, +imm */ \
3696 thumb_add_noflags(imm, 3, (pc & ~2) + 4, (imm * 4)); \
3700 /* ADD r4, pc, +imm */ \
3701 thumb_add_noflags(imm, 4, (pc & ~2) + 4, (imm * 4)); \
3705 /* ADD r5, pc, +imm */ \
3706 thumb_add_noflags(imm, 5, (pc & ~2) + 4, (imm * 4)); \
3710 /* ADD r6, pc, +imm */ \
3711 thumb_add_noflags(imm, 6, (pc & ~2) + 4, (imm * 4)); \
3715 /* ADD r7, pc, +imm */ \
3716 thumb_add_noflags(imm, 7, (pc & ~2) + 4, (imm * 4)); \
3720 /* ADD r0, sp, +imm */ \
3721 thumb_add_noflags(imm, 0, reg[REG_SP], (imm * 4)); \
3725 /* ADD r1, sp, +imm */ \
3726 thumb_add_noflags(imm, 1, reg[REG_SP], (imm * 4)); \
3730 /* ADD r2, sp, +imm */ \
3731 thumb_add_noflags(imm, 2, reg[REG_SP], (imm * 4)); \
3735 /* ADD r3, sp, +imm */ \
3736 thumb_add_noflags(imm, 3, reg[REG_SP], (imm * 4)); \
3740 /* ADD r4, sp, +imm */ \
3741 thumb_add_noflags(imm, 4, reg[REG_SP], (imm * 4)); \
3745 /* ADD r5, sp, +imm */ \
3746 thumb_add_noflags(imm, 5, reg[REG_SP], (imm * 4)); \
3750 /* ADD r6, sp, +imm */ \
3751 thumb_add_noflags(imm, 6, reg[REG_SP], (imm * 4)); \
3755 /* ADD r7, sp, +imm */ \
3756 thumb_add_noflags(imm, 7, reg[REG_SP], (imm * 4)); \
3759 case 0xB0 ... 0xB3: \
3760 if((opcode >> 7) & 0x01) \
3762 /* ADD sp, -imm */ \
3763 thumb_add_noflags(add_sp, 13, reg[REG_SP], -(imm * 4)); \
3767 /* ADD sp, +imm */ \
3768 thumb_add_noflags(add_sp, 13, reg[REG_SP], (imm * 4)); \
3774 thumb_block_memory(store, down, no_op, 13); \
3778 /* PUSH rlist, lr */ \
3779 thumb_block_memory(store, push_lr, push_lr, 13); \
3784 thumb_block_memory(load, no_op, up, 13); \
3788 /* POP rlist, pc */ \
3789 thumb_block_memory(load, no_op, pop_pc, 13); \
3793 /* STMIA r0!, rlist */ \
3794 thumb_block_memory(store, no_op, up, 0); \
3798 /* STMIA r1!, rlist */ \
3799 thumb_block_memory(store, no_op, up, 1); \
3803 /* STMIA r2!, rlist */ \
3804 thumb_block_memory(store, no_op, up, 2); \
3808 /* STMIA r3!, rlist */ \
3809 thumb_block_memory(store, no_op, up, 3); \
3813 /* STMIA r4!, rlist */ \
3814 thumb_block_memory(store, no_op, up, 4); \
3818 /* STMIA r5!, rlist */ \
3819 thumb_block_memory(store, no_op, up, 5); \
3823 /* STMIA r6!, rlist */ \
3824 thumb_block_memory(store, no_op, up, 6); \
3828 /* STMIA r7!, rlist */ \
3829 thumb_block_memory(store, no_op, up, 7); \
3833 /* LDMIA r0!, rlist */ \
3834 thumb_block_memory(load, no_op, up, 0); \
3838 /* LDMIA r1!, rlist */ \
3839 thumb_block_memory(load, no_op, up, 1); \
3843 /* LDMIA r2!, rlist */ \
3844 thumb_block_memory(load, no_op, up, 2); \
3848 /* LDMIA r3!, rlist */ \
3849 thumb_block_memory(load, no_op, up, 3); \
3853 /* LDMIA r4!, rlist */ \
3854 thumb_block_memory(load, no_op, up, 4); \
3858 /* LDMIA r5!, rlist */ \
3859 thumb_block_memory(load, no_op, up, 5); \
3863 /* LDMIA r6!, rlist */ \
3864 thumb_block_memory(load, no_op, up, 6); \
3868 /* LDMIA r7!, rlist */ \
3869 thumb_block_memory(load, no_op, up, 7); \
3874 thumb_conditional_branch(z_flag == 1); \
3879 thumb_conditional_branch(z_flag == 0); \
3884 thumb_conditional_branch(c_flag == 1); \
3889 thumb_conditional_branch(c_flag == 0); \
3894 thumb_conditional_branch(n_flag == 1); \
3899 thumb_conditional_branch(n_flag == 0); \
3904 thumb_conditional_branch(v_flag == 1); \
3909 thumb_conditional_branch(v_flag == 0); \
3914 thumb_conditional_branch(c_flag & (z_flag ^ 1)); \
3919 thumb_conditional_branch((c_flag == 0) | z_flag); \
3924 thumb_conditional_branch(n_flag == v_flag); \
3929 thumb_conditional_branch(n_flag != v_flag); \
3934 thumb_conditional_branch((z_flag == 0) & (n_flag == v_flag)); \
3939 thumb_conditional_branch(z_flag | (n_flag != v_flag)); \
3945 u32 swi_comment = opcode & 0xFF; \
3947 switch(swi_comment) \
3950 reg_mode[MODE_SUPERVISOR][6] = pc + 2; \
3951 spsr[MODE_SUPERVISOR] = reg[REG_CPSR]; \
3952 reg[REG_PC] = 0x00000008; \
3953 thumb_update_pc(); \
3954 reg[REG_CPSR] = (reg[REG_CPSR] & ~0x3F) | 0x13; \
3955 set_cpu_mode(MODE_SUPERVISOR); \
3962 case 0xE0 ... 0xE7: \
3965 thumb_decode_branch(); \
3966 thumb_pc_offset_update(((s32)(offset << 21) >> 20) + 4); \
3970 case 0xF0 ... 0xF7: \
3972 /* (low word) BL label */ \
3973 thumb_decode_branch(); \
3974 reg[REG_LR] = pc + 4 + ((s32)(offset << 21) >> 9); \
3975 thumb_pc_offset(2); \
3979 case 0xF8 ... 0xFF: \
3981 /* (high word) BL label */ \
3982 thumb_decode_branch(); \
3983 u32 lr = (pc + 2) | 0x01; \
3984 pc = reg[REG_LR] + (offset * 2); \
3991 void print_arm_registers()
3995 for(i = 0, i3 = 0; i < 4; i++)
3997 debug_screen_printf(" ");
3998 for(i2 = 0; i2 < 4; i2++, i3++)
4000 debug_screen_printf("R%02d %08x ", i3, reg[i3]);
4002 debug_screen_newline(1);
4006 void print_thumb_instruction()
4008 debug_screen_printf("Thumb instruction at PC: %04x",
4009 read_memory16(reg[REG_PC]));
4010 debug_screen_newline(1);
4013 void print_arm_instruction()
4015 debug_screen_printf("ARM instruction at PC: %08x",
4016 read_memory32(reg[REG_PC]));
4017 debug_screen_newline(1);
4022 u32 cpsr = reg[REG_CPSR];
4023 debug_screen_newline(1);
4024 debug_screen_printf(
4025 " N: %d Z: %d C: %d V: %d CPSR: %08x SPSR: %08x mode: %s",
4026 (cpsr >> 31) & 0x01, (cpsr >> 30) & 0x01, (cpsr >> 29) & 0x01,
4027 (cpsr >> 28) & 0x01, cpsr, spsr[reg[CPU_MODE]],
4028 cpu_mode_names[reg[CPU_MODE]]);
4029 debug_screen_newline(2);
4032 const u32 stack_print_lines = 2;
4038 debug_screen_printf("Stack:");
4039 debug_screen_newline(1);
4041 for(i = 0, i3 = reg[REG_SP]; i < stack_print_lines; i++)
4043 for(i2 = 0; i2 < 5; i2++, i3 += 4)
4045 debug_screen_printf(" %08x", read_memory32(i3));
4047 if(i != stack_print_lines)
4048 debug_screen_newline(1);
4051 debug_screen_newline(1);
4054 u32 instruction_count = 0;
4056 u32 output_field = 0;
4057 const u32 num_output_fields = 2;
4059 u32 last_instruction = 0;
4061 u32 in_interrupt = 0;
4065 current_debug_state = STEP;
4066 debug_screen_start();
4069 void debug_off(debug_state new_debug_state)
4071 current_debug_state = new_debug_state;
4075 void function_cc step_debug(u32 pc, u32 cycles)
4081 if(reg[REG_CPSR] & 0x20)
4084 instruction_count++;
4086 switch(current_debug_state)
4089 if(reg[REG_PC] == breakpoint_value)
4095 if(reg[REG_Z_FLAG] == 1)
4100 case VCOUNT_BREAKPOINT:
4101 if(io_registers[REG_VCOUNT] == breakpoint_value)
4106 case COUNTDOWN_BREAKPOINT:
4107 if(breakpoint_value == 0)
4114 case COUNTDOWN_BREAKPOINT_B:
4115 if(breakpoint_value == instruction_count)
4120 case COUNTDOWN_BREAKPOINT_C:
4125 if((breakpoint_value == 0) && (in_interrupt == 0))
4131 if(in_interrupt == 0)
4134 if(in_interrupt && (pc == 0x13c))
4144 if((current_debug_state == STEP) ||
4145 (current_debug_state == STEP_RUN))
4149 SDL_LockMutex(sound_mutex);
4152 if(output_field >= num_output_fields)
4155 debug_screen_clear();
4159 print_thumb_instruction(cycles);
4161 print_arm_instruction(cycles);
4163 print_arm_registers();
4168 printf("%x instructions in, VCOUNT %d, cycles remaining: %d \n",
4169 instruction_count, io_registers[REG_VCOUNT], cycles);
4171 debug_screen_update();
4174 if(current_debug_state != STEP_RUN)
4181 gui_action_type next_input = CURSOR_NONE;
4182 while(next_input == CURSOR_NONE)
4184 next_input = get_gui_input();
4211 dump_translation_cache();
4215 debug_off(Z_BREAKPOINT);
4220 printf("break at PC (hex): ");
4221 scanf("%08x", &breakpoint_value);
4222 debug_off(PC_BREAKPOINT);
4226 printf("break after N instructions (hex): ");
4227 scanf("%08x", &breakpoint_value);
4228 breakpoint_value -= 1;
4229 debug_off(COUNTDOWN_BREAKPOINT);
4233 printf("break after N instructions, skip in IRQ (hex): ");
4234 scanf("%08x", &breakpoint_value);
4235 breakpoint_value -= 1;
4236 debug_off(COUNTDOWN_BREAKPOINT_C);
4240 printf("break after N instructions (since start): ");
4241 scanf("%d", &breakpoint_value);
4242 debug_off(COUNTDOWN_BREAKPOINT_B);
4246 printf("break at VCOUNT: ");
4247 scanf("%d", &breakpoint_value);
4248 debug_off(VCOUNT_BREAKPOINT);
4253 current_debug_state = STEP_RUN;
4261 debug_off(PC_BREAKPOINT);
4265 global_cycles_per_instruction = 0;
4271 char current_savestate_filename[512];
4272 u16 *current_screen = copy_screen();
4273 get_savestate_filename_noshot(savestate_slot,
4274 current_savestate_filename);
4275 save_state(current_savestate_filename, current_screen);
4276 free(current_screen);
4285 SDL_UnlockMutex(sound_mutex);
4288 last_instruction = reg[REG_PC];
4291 reg[REG_PC] = pc + 2;
4293 reg[REG_PC] = pc + 4;
4296 void set_cpu_mode(cpu_mode_type new_mode)
4299 cpu_mode_type cpu_mode = reg[CPU_MODE];
4301 if(cpu_mode != new_mode)
4303 if(new_mode == MODE_FIQ)
4305 for(i = 8; i < 15; i++)
4307 reg_mode[cpu_mode][i - 8] = reg[i];
4312 reg_mode[cpu_mode][5] = reg[REG_SP];
4313 reg_mode[cpu_mode][6] = reg[REG_LR];
4316 if(cpu_mode == MODE_FIQ)
4318 for(i = 8; i < 15; i++)
4320 reg[i] = reg_mode[new_mode][i - 8];
4325 reg[REG_SP] = reg_mode[new_mode][5];
4326 reg[REG_LR] = reg_mode[new_mode][6];
4329 reg[CPU_MODE] = new_mode;
4333 void raise_interrupt(irq_type irq_raised)
4335 // The specific IRQ must be enabled in IE, master IRQ enable must be on,
4336 // and it must be on in the flags.
4337 io_registers[REG_IF] |= irq_raised;
4339 if((io_registers[REG_IE] & irq_raised) && io_registers[REG_IME] &&
4340 ((reg[REG_CPSR] & 0x80) == 0))
4342 bios_read_protect = 0xe55ec002;
4344 // Interrupt handler in BIOS
4345 reg_mode[MODE_IRQ][6] = reg[REG_PC] + 4;
4346 spsr[MODE_IRQ] = reg[REG_CPSR];
4347 reg[REG_CPSR] = 0xD2;
4348 reg[REG_PC] = 0x00000018;
4350 bios_region_read_allow();
4352 set_cpu_mode(MODE_IRQ);
4353 reg[CPU_HALT_STATE] = CPU_ACTIVE;
4354 reg[CHANGED_PC_STATUS] = 1;
4358 void execute_arm(u32 cycles)
4360 u32 pc = reg[REG_PC];
4363 u32 n_flag, z_flag, c_flag, v_flag;
4364 u32 pc_region = (pc >> 15);
4365 u8 *pc_address_block = memory_map_read[pc_region];
4367 s32 cycles_remaining;
4368 u32 cycles_per_instruction = global_cycles_per_instruction;
4369 cpu_alert_type cpu_alert;
4373 if(pc_address_block == NULL)
4374 pc_address_block = load_gamepak_page(pc_region & 0x3FF);
4378 cycles_remaining = cycles;
4382 if(reg[REG_CPSR] & 0x20)
4390 step_debug(pc, cycles_remaining);
4391 cycles_per_instruction = global_cycles_per_instruction;
4394 execute_arm_instruction();
4395 cycles_remaining -= cycles_per_instruction;
4396 } while(cycles_remaining > 0);
4399 cycles = update_gba();
4407 step_debug(pc, cycles_remaining);
4410 execute_thumb_instruction();
4411 cycles_remaining -= cycles_per_instruction;
4412 } while(cycles_remaining > 0);
4415 cycles = update_gba();
4420 if(cpu_alert == CPU_ALERT_IRQ)
4422 cycles = cycles_remaining;
4428 while(reg[CPU_HALT_STATE] != CPU_ACTIVE)
4430 cycles = update_gba();
4440 for(i = 0; i < 16; i++)
4445 reg[REG_SP] = 0x03007F00;
4446 reg[REG_PC] = 0x08000000;
4447 reg[REG_CPSR] = 0x0000001F;
4448 reg[CPU_HALT_STATE] = CPU_ACTIVE;
4449 reg[CPU_MODE] = MODE_USER;
4450 reg[CHANGED_PC_STATUS] = 0;
4452 reg_mode[MODE_USER][5] = 0x03007F00;
4453 reg_mode[MODE_IRQ][5] = 0x03007FA0;
4454 reg_mode[MODE_FIQ][5] = 0x03007FA0;
4455 reg_mode[MODE_SUPERVISOR][5] = 0x03007FE0;
4458 void move_reg(u32 *new_reg)
4462 for(i = 0; i < 32; i++)
4464 new_reg[i] = reg[i];
4471 #define cpu_savestate_builder(type) \
4472 void cpu_##type##_savestate(file_tag_type savestate_file) \
4474 file_##type(savestate_file, reg, 0x100); \
4475 file_##type##_array(savestate_file, spsr); \
4476 file_##type##_array(savestate_file, reg_mode); \
4479 cpu_savestate_builder(read);
4480 cpu_savestate_builder(write_mem);