1 /* CpuArch.h -- CPU specific code
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2 2022-07-15 : Igor Pavlov : Public domain */
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12 MY_CPU_LE means that CPU is LITTLE ENDIAN.
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13 MY_CPU_BE means that CPU is BIG ENDIAN.
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14 If MY_CPU_LE and MY_CPU_BE are not defined, we don't know about ENDIANNESS of platform.
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16 MY_CPU_LE_UNALIGN means that CPU is LITTLE ENDIAN and CPU supports unaligned memory accesses.
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18 MY_CPU_64BIT means that processor can work with 64-bit registers.
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19 MY_CPU_64BIT can be used to select fast code branch
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20 MY_CPU_64BIT doesn't mean that (sizeof(void *) == 8)
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23 #if defined(_M_X64) \
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24 || defined(_M_AMD64) \
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25 || defined(__x86_64__) \
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26 || defined(__AMD64__) \
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27 || defined(__amd64__)
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28 #define MY_CPU_AMD64
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30 #define MY_CPU_NAME "x32"
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31 #define MY_CPU_SIZEOF_POINTER 4
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33 #define MY_CPU_NAME "x64"
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34 #define MY_CPU_SIZEOF_POINTER 8
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36 #define MY_CPU_64BIT
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40 #if defined(_M_IX86) \
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41 || defined(__i386__)
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43 #define MY_CPU_NAME "x86"
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44 /* #define MY_CPU_32BIT */
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45 #define MY_CPU_SIZEOF_POINTER 4
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49 #if defined(_M_ARM64) \
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50 || defined(__AARCH64EL__) \
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51 || defined(__AARCH64EB__) \
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52 || defined(__aarch64__)
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53 #define MY_CPU_ARM64
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54 #define MY_CPU_NAME "arm64"
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55 #define MY_CPU_64BIT
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59 #if defined(_M_ARM) \
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60 || defined(_M_ARM_NT) \
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61 || defined(_M_ARMT) \
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62 || defined(__arm__) \
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63 || defined(__thumb__) \
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64 || defined(__ARMEL__) \
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65 || defined(__ARMEB__) \
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66 || defined(__THUMBEL__) \
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67 || defined(__THUMBEB__)
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70 #if defined(__thumb__) || defined(__THUMBEL__) || defined(_M_ARMT)
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71 #define MY_CPU_NAME "armt"
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73 #define MY_CPU_NAME "arm"
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75 /* #define MY_CPU_32BIT */
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76 #define MY_CPU_SIZEOF_POINTER 4
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80 #if defined(_M_IA64) \
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81 || defined(__ia64__)
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83 #define MY_CPU_NAME "ia64"
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84 #define MY_CPU_64BIT
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88 #if defined(__mips64) \
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89 || defined(__mips64__) \
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90 || (defined(__mips) && (__mips == 64 || __mips == 4 || __mips == 3))
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91 #define MY_CPU_NAME "mips64"
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92 #define MY_CPU_64BIT
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93 #elif defined(__mips__)
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94 #define MY_CPU_NAME "mips"
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95 /* #define MY_CPU_32BIT */
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99 #if defined(__ppc64__) \
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100 || defined(__powerpc64__) \
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101 || defined(__ppc__) \
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102 || defined(__powerpc__) \
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103 || defined(__PPC__) \
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106 #if defined(__ppc64__) \
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107 || defined(__powerpc64__) \
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108 || defined(_LP64) \
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109 || defined(__64BIT__)
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111 #define MY_CPU_NAME "ppc64-32"
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112 #define MY_CPU_SIZEOF_POINTER 4
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114 #define MY_CPU_NAME "ppc64"
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115 #define MY_CPU_SIZEOF_POINTER 8
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117 #define MY_CPU_64BIT
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119 #define MY_CPU_NAME "ppc"
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120 #define MY_CPU_SIZEOF_POINTER 4
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121 /* #define MY_CPU_32BIT */
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126 #if defined(__riscv) \
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127 || defined(__riscv__)
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128 #if __riscv_xlen == 32
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129 #define MY_CPU_NAME "riscv32"
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130 #elif __riscv_xlen == 64
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131 #define MY_CPU_NAME "riscv64"
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133 #define MY_CPU_NAME "riscv"
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138 #if defined(MY_CPU_X86) || defined(MY_CPU_AMD64)
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139 #define MY_CPU_X86_OR_AMD64
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142 #if defined(MY_CPU_ARM) || defined(MY_CPU_ARM64)
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143 #define MY_CPU_ARM_OR_ARM64
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150 #define MY_CPU_ARM_LE
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153 #ifdef MY_CPU_ARM64
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154 #define MY_CPU_ARM64_LE
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158 #define MY_CPU_IA64_LE
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164 #if defined(MY_CPU_X86_OR_AMD64) \
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165 || defined(MY_CPU_ARM_LE) \
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166 || defined(MY_CPU_ARM64_LE) \
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167 || defined(MY_CPU_IA64_LE) \
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168 || defined(__LITTLE_ENDIAN__) \
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169 || defined(__ARMEL__) \
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170 || defined(__THUMBEL__) \
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171 || defined(__AARCH64EL__) \
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172 || defined(__MIPSEL__) \
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173 || defined(__MIPSEL) \
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174 || defined(_MIPSEL) \
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175 || defined(__BFIN__) \
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176 || (defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__))
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180 #if defined(__BIG_ENDIAN__) \
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181 || defined(__ARMEB__) \
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182 || defined(__THUMBEB__) \
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183 || defined(__AARCH64EB__) \
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184 || defined(__MIPSEB__) \
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185 || defined(__MIPSEB) \
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186 || defined(_MIPSEB) \
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187 || defined(__m68k__) \
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188 || defined(__s390__) \
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189 || defined(__s390x__) \
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190 || defined(__zarch__) \
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191 || (defined(__BYTE_ORDER__) && (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__))
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196 #if defined(MY_CPU_LE) && defined(MY_CPU_BE)
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197 #error Stop_Compiling_Bad_Endian
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201 #if defined(MY_CPU_32BIT) && defined(MY_CPU_64BIT)
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202 #error Stop_Compiling_Bad_32_64_BIT
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205 #ifdef __SIZEOF_POINTER__
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206 #ifdef MY_CPU_SIZEOF_POINTER
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207 #if MY_CPU_SIZEOF_POINTER != __SIZEOF_POINTER__
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208 #error Stop_Compiling_Bad_MY_CPU_PTR_SIZE
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211 #define MY_CPU_SIZEOF_POINTER __SIZEOF_POINTER__
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215 #if defined(MY_CPU_SIZEOF_POINTER) && (MY_CPU_SIZEOF_POINTER == 4)
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216 #if defined (_LP64)
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217 #error Stop_Compiling_Bad_MY_CPU_PTR_SIZE
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222 #if _MSC_VER >= 1300
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223 #define MY_CPU_pragma_pack_push_1 __pragma(pack(push, 1))
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224 #define MY_CPU_pragma_pop __pragma(pack(pop))
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226 #define MY_CPU_pragma_pack_push_1
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227 #define MY_CPU_pragma_pop
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231 #define MY_CPU_pragma_pack_push_1 _Pragma("pack(1)")
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232 #define MY_CPU_pragma_pop _Pragma("pack()")
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234 #define MY_CPU_pragma_pack_push_1 _Pragma("pack(push, 1)")
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235 #define MY_CPU_pragma_pop _Pragma("pack(pop)")
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240 #ifndef MY_CPU_NAME
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242 #define MY_CPU_NAME "LE"
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243 #elif defined(MY_CPU_BE)
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244 #define MY_CPU_NAME "BE"
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247 #define MY_CPU_NAME ""
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257 #if defined(MY_CPU_X86_OR_AMD64) \
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258 || defined(MY_CPU_ARM64)
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259 #define MY_CPU_LE_UNALIGN
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260 #define MY_CPU_LE_UNALIGN_64
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261 #elif defined(__ARM_FEATURE_UNALIGNED)
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262 /* gcc9 for 32-bit arm can use LDRD instruction that requires 32-bit alignment.
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263 So we can't use unaligned 64-bit operations. */
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264 #define MY_CPU_LE_UNALIGN
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269 #ifdef MY_CPU_LE_UNALIGN
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271 #define GetUi16(p) (*(const UInt16 *)(const void *)(p))
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272 #define GetUi32(p) (*(const UInt32 *)(const void *)(p))
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273 #ifdef MY_CPU_LE_UNALIGN_64
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274 #define GetUi64(p) (*(const UInt64 *)(const void *)(p))
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277 #define SetUi16(p, v) { *(UInt16 *)(void *)(p) = (v); }
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278 #define SetUi32(p, v) { *(UInt32 *)(void *)(p) = (v); }
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279 #ifdef MY_CPU_LE_UNALIGN_64
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280 #define SetUi64(p, v) { *(UInt64 *)(void *)(p) = (v); }
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285 #define GetUi16(p) ( (UInt16) ( \
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286 ((const Byte *)(p))[0] | \
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287 ((UInt16)((const Byte *)(p))[1] << 8) ))
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289 #define GetUi32(p) ( \
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290 ((const Byte *)(p))[0] | \
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291 ((UInt32)((const Byte *)(p))[1] << 8) | \
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292 ((UInt32)((const Byte *)(p))[2] << 16) | \
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293 ((UInt32)((const Byte *)(p))[3] << 24))
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295 #define SetUi16(p, v) { Byte *_ppp_ = (Byte *)(p); UInt32 _vvv_ = (v); \
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296 _ppp_[0] = (Byte)_vvv_; \
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297 _ppp_[1] = (Byte)(_vvv_ >> 8); }
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299 #define SetUi32(p, v) { Byte *_ppp_ = (Byte *)(p); UInt32 _vvv_ = (v); \
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300 _ppp_[0] = (Byte)_vvv_; \
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301 _ppp_[1] = (Byte)(_vvv_ >> 8); \
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302 _ppp_[2] = (Byte)(_vvv_ >> 16); \
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303 _ppp_[3] = (Byte)(_vvv_ >> 24); }
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308 #ifndef MY_CPU_LE_UNALIGN_64
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310 #define GetUi64(p) (GetUi32(p) | ((UInt64)GetUi32(((const Byte *)(p)) + 4) << 32))
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312 #define SetUi64(p, v) { Byte *_ppp2_ = (Byte *)(p); UInt64 _vvv2_ = (v); \
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313 SetUi32(_ppp2_ , (UInt32)_vvv2_); \
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314 SetUi32(_ppp2_ + 4, (UInt32)(_vvv2_ >> 32)); }
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321 #ifdef __has_builtin
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322 #define MY__has_builtin(x) __has_builtin(x)
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324 #define MY__has_builtin(x) 0
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327 #if defined(MY_CPU_LE_UNALIGN) && /* defined(_WIN64) && */ defined(_MSC_VER) && (_MSC_VER >= 1300)
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329 /* Note: we use bswap instruction, that is unsupported in 386 cpu */
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331 #include <stdlib.h>
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333 #pragma intrinsic(_byteswap_ushort)
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334 #pragma intrinsic(_byteswap_ulong)
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335 #pragma intrinsic(_byteswap_uint64)
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337 /* #define GetBe16(p) _byteswap_ushort(*(const UInt16 *)(const Byte *)(p)) */
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338 #define GetBe32(p) _byteswap_ulong (*(const UInt32 *)(const void *)(p))
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339 #define GetBe64(p) _byteswap_uint64(*(const UInt64 *)(const void *)(p))
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341 #define SetBe32(p, v) (*(UInt32 *)(void *)(p)) = _byteswap_ulong(v)
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343 #elif defined(MY_CPU_LE_UNALIGN) && ( \
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344 (defined(__GNUC__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 3))) \
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345 || (defined(__clang__) && MY__has_builtin(__builtin_bswap16)) )
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347 /* #define GetBe16(p) __builtin_bswap16(*(const UInt16 *)(const void *)(p)) */
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348 #define GetBe32(p) __builtin_bswap32(*(const UInt32 *)(const void *)(p))
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349 #define GetBe64(p) __builtin_bswap64(*(const UInt64 *)(const void *)(p))
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351 #define SetBe32(p, v) (*(UInt32 *)(void *)(p)) = __builtin_bswap32(v)
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355 #define GetBe32(p) ( \
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356 ((UInt32)((const Byte *)(p))[0] << 24) | \
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357 ((UInt32)((const Byte *)(p))[1] << 16) | \
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358 ((UInt32)((const Byte *)(p))[2] << 8) | \
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359 ((const Byte *)(p))[3] )
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361 #define GetBe64(p) (((UInt64)GetBe32(p) << 32) | GetBe32(((const Byte *)(p)) + 4))
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363 #define SetBe32(p, v) { Byte *_ppp_ = (Byte *)(p); UInt32 _vvv_ = (v); \
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364 _ppp_[0] = (Byte)(_vvv_ >> 24); \
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365 _ppp_[1] = (Byte)(_vvv_ >> 16); \
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366 _ppp_[2] = (Byte)(_vvv_ >> 8); \
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367 _ppp_[3] = (Byte)_vvv_; }
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374 #define GetBe16(p) ( (UInt16) ( \
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375 ((UInt16)((const Byte *)(p))[0] << 8) | \
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376 ((const Byte *)(p))[1] ))
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382 #ifdef MY_CPU_X86_OR_AMD64
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401 void MyCPUID(UInt32 function, UInt32 *a, UInt32 *b, UInt32 *c, UInt32 *d);
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403 BoolInt x86cpuid_CheckAndRead(Cx86cpuid *p);
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404 int x86cpuid_GetFirm(const Cx86cpuid *p);
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406 #define x86cpuid_GetFamily(ver) (((ver >> 16) & 0xFF0) | ((ver >> 8) & 0xF))
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407 #define x86cpuid_GetModel(ver) (((ver >> 12) & 0xF0) | ((ver >> 4) & 0xF))
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408 #define x86cpuid_GetStepping(ver) (ver & 0xF)
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410 BoolInt CPU_Is_InOrder(void);
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412 BoolInt CPU_IsSupported_AES(void);
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413 BoolInt CPU_IsSupported_AVX2(void);
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414 BoolInt CPU_IsSupported_VAES_AVX2(void);
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415 BoolInt CPU_IsSupported_SSSE3(void);
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416 BoolInt CPU_IsSupported_SSE41(void);
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417 BoolInt CPU_IsSupported_SHA(void);
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418 BoolInt CPU_IsSupported_PageGB(void);
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420 #elif defined(MY_CPU_ARM_OR_ARM64)
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422 BoolInt CPU_IsSupported_CRC32(void);
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423 BoolInt CPU_IsSupported_NEON(void);
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425 #if defined(_WIN32)
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426 BoolInt CPU_IsSupported_CRYPTO(void);
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427 #define CPU_IsSupported_SHA1 CPU_IsSupported_CRYPTO
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428 #define CPU_IsSupported_SHA2 CPU_IsSupported_CRYPTO
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429 #define CPU_IsSupported_AES CPU_IsSupported_CRYPTO
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431 BoolInt CPU_IsSupported_SHA1(void);
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432 BoolInt CPU_IsSupported_SHA2(void);
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433 BoolInt CPU_IsSupported_AES(void);
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438 #if defined(__APPLE__)
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439 int My_sysctlbyname_Get(const char *name, void *buf, size_t *bufSize);
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440 int My_sysctlbyname_Get_UInt32(const char *name, UInt32 *val);
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