deps/lightrec/constprop.c

   1 // SPDX-License-Identifier: LGPL-2.1-or-later
   2 /*
   3  * Copyright (C) 2022 Paul Cercueil <paul@crapouillou.net>
   4  */
   5
   6 #include "constprop.h"
   7 #include "disassembler.h"
   8 #include "lightrec-private.h"
   9
  10 #include <stdbool.h>
  11 #include <string.h>
  12
  13 static u32 get_min_value(const struct constprop_data *d)
  14 {
  15         /* Min value: all sign bits to 1, all unknown bits but MSB to 0 */
  16         return (d->value & d->known) | d->sign | (~d->known & BIT(31));
  17 }
  18
  19 static u32 get_max_value(const struct constprop_data *d)
  20 {
  21         /* Max value: all sign bits to 0, all unknown bits to 1 */
  22         return ((d->value & d->known) | ~d->known) & ~d->sign;
  23 }
  24
  25 static u32 lightrec_same_sign(const struct constprop_data *d1,
  26                               const struct constprop_data *d2)
  27 {
  28         u32 min1, min2, max1, max2, a, b, c, d;
  29
  30         min1 = get_min_value(d1);
  31         max1 = get_max_value(d1);
  32         min2 = get_min_value(d2);
  33         max2 = get_max_value(d2);
  34
  35         a = min1 + min2;
  36         b = min1 + max2;
  37         c = max1 + min2;
  38         d = max1 + max2;
  39
  40         return ((a & b & c & d) | (~a & ~b & ~c & ~d)) & BIT(31);
  41 }
  42
  43 static u32 lightrec_get_sign_mask(const struct constprop_data *d)
  44 {
  45         u32 imm;
  46
  47         if (d->sign)
  48                 return d->sign;
  49
  50         imm = (d->value & BIT(31)) ? d->value : ~d->value;
  51         imm = ~(imm & d->known);
  52         if (imm)
  53                 imm = 32 - clz32(imm);
  54
  55         return imm < 32 ? GENMASK(31, imm) : 0;
  56 }
  57
  58 static void lightrec_propagate_addi(u32 rs, u32 rd,
  59                                     const struct constprop_data *d,
  60                                     struct constprop_data *v)
  61 {
  62         u32 end, bit, sum, min, mask, imm, value;
  63         struct constprop_data result = {
  64                 .value = v[rd].value,
  65                 .known = v[rd].known,
  66                 .sign = v[rd].sign,
  67         };
  68         bool carry = false;
  69
  70         /* clear unknown bits to ease processing */
  71         v[rs].value &= v[rs].known;
  72         value = d->value & d->known;
  73
  74         mask = ~(lightrec_get_sign_mask(d) & lightrec_get_sign_mask(&v[rs]));
  75         end = mask ? 32 - clz32(mask) : 0;
  76
  77         for (bit = 0; bit < 32; bit++) {
  78                 if (v[rs].known & d->known & BIT(bit)) {
  79                         /* the bits are known - compute the resulting bit and
  80                          * the carry */
  81                         sum = ((u32)carry << bit) + (v[rs].value & BIT(bit))
  82                                 + (value & BIT(bit));
  83
  84                         if (sum & BIT(bit))
  85                                 result.value |= BIT(bit);
  86                         else
  87                                 result.value &= ~BIT(bit);
  88
  89                         result.known |= BIT(bit);
  90                         result.sign &= ~BIT(bit);
  91                         carry = sum & BIT(bit + 1);
  92                         continue;
  93                 }
  94
  95                 if (bit >= end) {
  96                         /* We're past the last significant bits of the values
  97                          * (extra sign bits excepted).
  98                          * The destination register will be sign-extended
  99                          * starting from here (if no carry) or from the next
 100                          * bit (if carry).
 101                          * If the source registers are not sign-extended and we
 102                          * have no carry, the algorithm is done here. */
 103
 104                         if ((v[rs].sign | d->sign) & BIT(bit)) {
 105                                 mask = GENMASK(31, bit);
 106
 107                                 if (lightrec_same_sign(&v[rs], d)) {
 108                                         /* Theorical minimum and maximum values
 109                                          * have the same sign; therefore the
 110                                          * sign bits are known. */
 111                                         min = get_min_value(&v[rs])
 112                                                 + get_min_value(d);
 113                                         result.value = (min & mask)
 114                                                 | (result.value & ~mask);
 115                                         result.known |= mask << carry;
 116                                         result.sign = 0;
 117                                 } else {
 118                                         /* min/max have different signs. */
 119                                         result.sign = mask << 1;
 120                                         result.known &= ~mask;
 121                                 }
 122                                 break;
 123                         } else if (!carry) {
 124                                 /* Past end bit, no carry; we're done here. */
 125                                 break;
 126                         }
 127                 }
 128
 129                 result.known &= ~BIT(bit);
 130                 result.sign &= ~BIT(bit);
 131
 132                 /* Found an unknown bit in one of the registers.
 133                  * If the carry and the bit in the other register are both zero,
 134                  * we can continue the algorithm. */
 135                 if (!carry && (((d->known & ~value)
 136                                 | (v[rs].known & ~v[rs].value)) & BIT(bit)))
 137                         continue;
 138
 139                 /* We have an unknown bit in one of the source registers, and we
 140                  * may generate a carry: there's nothing to do. Everything from
 141                  * this bit till the next known 0 bit or sign bit will be marked
 142                  * as unknown. The algorithm can then restart at the following
 143                  * bit. */
 144
 145                 imm = (v[rs].known & d->known & ~v[rs].value & ~value)
 146                         | v[rs].sign | d->sign;
 147
 148                 imm &= GENMASK(31, bit);
 149                 imm = imm ? ctz32(imm) : 31;
 150                 mask = GENMASK(imm, bit);
 151                 result.known &= ~mask;
 152                 result.sign &= ~mask;
 153
 154                 bit = imm;
 155                 carry = false;
 156         }
 157
 158         v[rd] = result;
 159 }
 160
 161 static void lightrec_propagate_sub(u32 rs, u32 rt, u32 rd,
 162                                    struct constprop_data *v)
 163 {
 164         struct constprop_data d = {
 165                 .value = ~v[rt].value,
 166                 .known = v[rt].known,
 167                 .sign = v[rt].sign,
 168         };
 169         u32 imm, mask, bit;
 170
 171         /* Negate the known Rt value, then propagate as a regular ADD. */
 172
 173         for (bit = 0; bit < 32; bit++) {
 174                 if (!(d.known & BIT(bit))) {
 175                         /* Unknown bit - mark bits unknown up to the next known 0 */
 176
 177                         imm = (d.known & ~d.value) | d.sign;
 178                         imm &= GENMASK(31, bit);
 179                         imm = imm ? ctz32(imm) : 31;
 180                         mask = GENMASK(imm, bit);
 181                         d.known &= ~mask;
 182                         d.sign &= ~mask;
 183                         break;
 184                 }
 185
 186                 if (!(d.value & BIT(bit))) {
 187                         /* Bit is 0: we can set our carry, and the algorithm is done. */
 188                         d.value |= BIT(bit);
 189                         break;
 190                 }
 191
 192                 /* Bit is 1 - set to 0 and continue algorithm */
 193                 d.value &= ~BIT(bit);
 194         }
 195
 196         lightrec_propagate_addi(rs, rd, &d, v);
 197 }
 198
 199 static void lightrec_propagate_slt(u32 rs, u32 rd, bool is_signed,
 200                                    const struct constprop_data *d,
 201                                    struct constprop_data *v)
 202 {
 203         unsigned int bit;
 204
 205         if (is_signed && (v[rs].known & d->known
 206                           & (v[rs].value ^ d->value) & BIT(31))) {
 207                 /* If doing a signed comparison and the two bits 31 are known
 208                  * to be opposite, we can deduce the value. */
 209                 v[rd].value = v[rs].value >> 31;
 210                 v[rd].known = 0xffffffff;
 211                 v[rd].sign = 0;
 212                 return;
 213         }
 214
 215         for (bit = 32; bit > 0; bit--) {
 216                 if (!(v[rs].known & d->known & BIT(bit - 1))) {
 217                         /* One bit is unknown and we cannot figure out which
 218                          * value is smaller. We still know that the upper 31
 219                          * bits are zero. */
 220                         v[rd].value = 0;
 221                         v[rd].known = 0xfffffffe;
 222                         v[rd].sign = 0;
 223                         break;
 224                 }
 225
 226                 /* The two bits are equal - continue to the next bit. */
 227                 if (~(v[rs].value ^ d->value) & BIT(bit - 1))
 228                         continue;
 229
 230                 /* The two bits aren't equal; we can therefore deduce which
 231                  * value is smaller. */
 232                 v[rd].value = !(v[rs].value & BIT(bit - 1));
 233                 v[rd].known = 0xffffffff;
 234                 v[rd].sign = 0;
 235                 break;
 236         }
 237
 238         if (bit == 0) {
 239                 /* rs == rt and all bits are known */
 240                 v[rd].value = 0;
 241                 v[rd].known = 0xffffffff;
 242                 v[rd].sign = 0;
 243         }
 244 }
 245
 246 void lightrec_consts_propagate(const struct opcode *list,
 247                                unsigned int idx,
 248                                struct constprop_data *v)
 249 {
 250         union code c;
 251         u32 imm;
 252
 253         if (idx == 0)
 254                 return;
 255
 256         /* Register $zero is always, well, zero */
 257         v[0].value = 0;
 258         v[0].sign = 0;
 259         v[0].known = 0xffffffff;
 260
 261         if (op_flag_sync(list[idx].flags)) {
 262                 memset(&v[1], 0, sizeof(*v) * 31);
 263                 return;
 264         }
 265
 266         if (idx > 1 && !op_flag_sync(list[idx - 1].flags)) {
 267                 c = list[idx - 2].c;
 268
 269                 switch (c.i.op) {
 270                 case OP_BNE:
 271                         /* After a BNE $zero + delay slot, we know that the
 272                          * branch wasn't taken, and therefore the other register
 273                          * is zero. */
 274                         if (c.i.rs == 0) {
 275                                 v[c.i.rt].value = 0;
 276                                 v[c.i.rt].sign = 0;
 277                                 v[c.i.rt].known = 0xffffffff;
 278                         } else if (c.i.rt == 0) {
 279                                 v[c.i.rs].value = 0;
 280                                 v[c.i.rs].sign = 0;
 281                                 v[c.i.rs].known = 0xffffffff;
 282                         }
 283                         break;
 284                 case OP_BLEZ:
 285                         v[c.i.rs].value &= ~BIT(31);
 286                         v[c.i.rs].known |= BIT(31);
 287                         fallthrough;
 288                 case OP_BEQ:
 289                         /* TODO: handle non-zero? */
 290                         break;
 291                 case OP_REGIMM:
 292                         switch (c.r.rt) {
 293                         case OP_REGIMM_BLTZ:
 294                         case OP_REGIMM_BLTZAL:
 295                                 v[c.i.rs].value &= ~BIT(31);
 296                                 v[c.i.rs].known |= BIT(31);
 297                                 break;
 298                         case OP_REGIMM_BGEZ:
 299                         case OP_REGIMM_BGEZAL:
 300                                 v[c.i.rs].value |= BIT(31);
 301                                 v[c.i.rs].known |= BIT(31);
 302                                 /* TODO: handle non-zero? */
 303                                 break;
 304                         }
 305                         break;
 306                 default:
 307                         break;
 308                 }
 309         }
 310
 311         c = list[idx - 1].c;
 312
 313         switch (c.i.op) {
 314         case OP_SPECIAL:
 315                 switch (c.r.op) {
 316                 case OP_SPECIAL_SLL:
 317                         v[c.r.rd].value = v[c.r.rt].value << c.r.imm;
 318                         v[c.r.rd].known = (v[c.r.rt].known << c.r.imm)
 319                                 | (BIT(c.r.imm) - 1);
 320                         v[c.r.rd].sign = v[c.r.rt].sign << c.r.imm;
 321                         break;
 322
 323                 case OP_SPECIAL_SRL:
 324                         v[c.r.rd].value = v[c.r.rt].value >> c.r.imm;
 325                         v[c.r.rd].known = (v[c.r.rt].known >> c.r.imm)
 326                                 | (BIT(c.r.imm) - 1 << 32 - c.r.imm);
 327                         v[c.r.rd].sign = c.r.imm ? 0 : v[c.r.rt].sign;
 328                         break;
 329
 330                 case OP_SPECIAL_SRA:
 331                         v[c.r.rd].value = (s32)v[c.r.rt].value >> c.r.imm;
 332                         v[c.r.rd].known = (s32)v[c.r.rt].known >> c.r.imm;
 333                         v[c.r.rd].sign = (s32)v[c.r.rt].sign >> c.r.imm;
 334                         break;
 335
 336                 case OP_SPECIAL_SLLV:
 337                         if ((v[c.r.rs].known & 0x1f) == 0x1f) {
 338                                 imm = v[c.r.rs].value & 0x1f;
 339                                 v[c.r.rd].value = v[c.r.rt].value << imm;
 340                                 v[c.r.rd].known = (v[c.r.rt].known << imm)
 341                                         | (BIT(imm) - 1);
 342                                 v[c.r.rd].sign = v[c.r.rt].sign << imm;
 343                         } else {
 344                                 v[c.r.rd].known = 0;
 345                                 v[c.r.rd].sign = 0;
 346                         }
 347                         break;
 348
 349                 case OP_SPECIAL_SRLV:
 350                         if ((v[c.r.rs].known & 0x1f) == 0x1f) {
 351                                 imm = v[c.r.rs].value & 0x1f;
 352                                 v[c.r.rd].value = v[c.r.rt].value >> imm;
 353                                 v[c.r.rd].known = (v[c.r.rt].known >> imm)
 354                                         | (BIT(imm) - 1 << 32 - imm);
 355                                 if (imm)
 356                                         v[c.r.rd].sign = 0;
 357                         } else {
 358                                 v[c.r.rd].known = 0;
 359                                 v[c.r.rd].sign = 0;
 360                         }
 361                         break;
 362
 363                 case OP_SPECIAL_SRAV:
 364                         if ((v[c.r.rs].known & 0x1f) == 0x1f) {
 365                                 imm = v[c.r.rs].value & 0x1f;
 366                                 v[c.r.rd].value = (s32)v[c.r.rt].value >> imm;
 367                                 v[c.r.rd].known = (s32)v[c.r.rt].known >> imm;
 368                                 v[c.r.rd].sign = (s32)v[c.r.rt].sign >> imm;
 369                         } else {
 370                                 v[c.r.rd].known = 0;
 371                                 v[c.r.rd].sign = 0;
 372                         }
 373                         break;
 374
 375                 case OP_SPECIAL_ADD:
 376                 case OP_SPECIAL_ADDU:
 377                         if (is_known_zero(v, c.r.rs))
 378                                 v[c.r.rd] = v[c.r.rt];
 379                         else if (is_known_zero(v, c.r.rt))
 380                                 v[c.r.rd] = v[c.r.rs];
 381                         else
 382                                 lightrec_propagate_addi(c.r.rs, c.r.rd, &v[c.r.rt], v);
 383                         break;
 384
 385                 case OP_SPECIAL_SUB:
 386                 case OP_SPECIAL_SUBU:
 387                         if (c.r.rs == c.r.rt) {
 388                                 v[c.r.rd].value = 0;
 389                                 v[c.r.rd].known = 0xffffffff;
 390                                 v[c.r.rd].sign = 0;
 391                         } else {
 392                                 lightrec_propagate_sub(c.r.rs, c.r.rt, c.r.rd, v);
 393                         }
 394                         break;
 395
 396                 case OP_SPECIAL_AND:
 397                         v[c.r.rd].known = (v[c.r.rt].known & v[c.r.rs].known)
 398                                 | (~v[c.r.rt].value & v[c.r.rt].known)
 399                                 | (~v[c.r.rs].value & v[c.r.rs].known);
 400                         v[c.r.rd].value = v[c.r.rt].value & v[c.r.rs].value & v[c.r.rd].known;
 401                         v[c.r.rd].sign = v[c.r.rt].sign & v[c.r.rs].sign;
 402                         break;
 403
 404                 case OP_SPECIAL_OR:
 405                         v[c.r.rd].known = (v[c.r.rt].known & v[c.r.rs].known)
 406                                 | (v[c.r.rt].value & v[c.r.rt].known)
 407                                 | (v[c.r.rs].value & v[c.r.rs].known);
 408                         v[c.r.rd].value = (v[c.r.rt].value | v[c.r.rs].value) & v[c.r.rd].known;
 409                         v[c.r.rd].sign = v[c.r.rt].sign & v[c.r.rs].sign;
 410                         break;
 411
 412                 case OP_SPECIAL_XOR:
 413                         v[c.r.rd].value = v[c.r.rt].value ^ v[c.r.rs].value;
 414                         v[c.r.rd].known = v[c.r.rt].known & v[c.r.rs].known;
 415                         v[c.r.rd].sign = v[c.r.rt].sign & v[c.r.rs].sign;
 416                         break;
 417
 418                 case OP_SPECIAL_NOR:
 419                         v[c.r.rd].known = (v[c.r.rt].known & v[c.r.rs].known)
 420                                 | (v[c.r.rt].value & v[c.r.rt].known)
 421                                 | (v[c.r.rs].value & v[c.r.rs].known);
 422                         v[c.r.rd].value = ~(v[c.r.rt].value | v[c.r.rs].value) & v[c.r.rd].known;
 423                         v[c.r.rd].sign = v[c.r.rt].sign & v[c.r.rs].sign;
 424                         break;
 425
 426                 case OP_SPECIAL_SLT:
 427                 case OP_SPECIAL_SLTU:
 428                         lightrec_propagate_slt(c.r.rs, c.r.rd,
 429                                                c.r.op ==  OP_SPECIAL_SLT,
 430                                                &v[c.r.rt], v);
 431                         break;
 432
 433                 case OP_SPECIAL_MULT:
 434                 case OP_SPECIAL_MULTU:
 435                 case OP_SPECIAL_DIV:
 436                 case OP_SPECIAL_DIVU:
 437                         if (OPT_FLAG_MULT_DIV && c.r.rd) {
 438                                 v[c.r.rd].known = 0;
 439                                 v[c.r.rd].sign = 0;
 440                         }
 441                         if (OPT_FLAG_MULT_DIV && c.r.imm) {
 442                                 v[c.r.imm].known = 0;
 443                                 v[c.r.imm].sign = 0;
 444                         }
 445                         break;
 446
 447                 case OP_SPECIAL_MFLO:
 448                 case OP_SPECIAL_MFHI:
 449                         v[c.r.rd].known = 0;
 450                         v[c.r.rd].sign = 0;
 451                         break;
 452                 default:
 453                         break;
 454                 }
 455                 break;
 456
 457         case OP_META_MULT2:
 458         case OP_META_MULTU2:
 459                 if (OPT_FLAG_MULT_DIV && c.r.rd) {
 460                         if (c.r.op < 32) {
 461                                 v[c.r.rd].value = v[c.r.rs].value << c.r.op;
 462                                 v[c.r.rd].known = (v[c.r.rs].known << c.r.op)
 463                                         | (BIT(c.r.op) - 1);
 464                                 v[c.r.rd].sign = v[c.r.rs].sign << c.r.op;
 465                         } else {
 466                                 v[c.r.rd].value = 0;
 467                                 v[c.r.rd].known = 0xffffffff;
 468                                 v[c.r.rd].sign = 0;
 469                         }
 470                 }
 471
 472                 if (OPT_FLAG_MULT_DIV && c.r.imm) {
 473                         if (c.r.op >= 32) {
 474                                 v[c.r.imm].value = v[c.r.rs].value << c.r.op - 32;
 475                                 v[c.r.imm].known = (v[c.r.rs].known << c.r.op - 32)
 476                                         | (BIT(c.r.op - 32) - 1);
 477                                 v[c.r.imm].sign = v[c.r.rs].sign << c.r.op - 32;
 478                         } else if (c.i.op == OP_META_MULT2) {
 479                                 v[c.r.imm].value = (s32)v[c.r.rs].value >> 32 - c.r.op;
 480                                 v[c.r.imm].known = (s32)v[c.r.rs].known >> 32 - c.r.op;
 481                                 v[c.r.imm].sign = (s32)v[c.r.rs].sign >> 32 - c.r.op;
 482                         } else {
 483                                 v[c.r.imm].value = v[c.r.rs].value >> 32 - c.r.op;
 484                                 v[c.r.imm].known = v[c.r.rs].known >> 32 - c.r.op;
 485                                 v[c.r.imm].sign = v[c.r.rs].sign >> 32 - c.r.op;
 486                         }
 487                 }
 488                 break;
 489
 490         case OP_REGIMM:
 491                 break;
 492
 493         case OP_ADDI:
 494         case OP_ADDIU:
 495                 if (c.i.imm) {
 496                         struct constprop_data d = {
 497                                 .value = (s32)(s16)c.i.imm,
 498                                 .known = 0xffffffff,
 499                                 .sign = 0,
 500                         };
 501
 502                         lightrec_propagate_addi(c.i.rs, c.i.rt, &d, v);
 503                 } else {
 504                         /* immediate is zero - that's just a register copy. */
 505                         v[c.i.rt] = v[c.i.rs];
 506                 }
 507                 break;
 508
 509         case OP_SLTI:
 510         case OP_SLTIU:
 511                 {
 512                         struct constprop_data d = {
 513                                 .value = (s32)(s16)c.i.imm,
 514                                 .known = 0xffffffff,
 515                                 .sign = 0,
 516                         };
 517
 518                         lightrec_propagate_slt(c.i.rs, c.i.rt,
 519                                                c.i.op == OP_SLTI, &d, v);
 520                 }
 521                 break;
 522
 523         case OP_ANDI:
 524                 v[c.i.rt].value = v[c.i.rs].value & c.i.imm;
 525                 v[c.i.rt].known = v[c.i.rs].known | ~c.i.imm;
 526                 v[c.i.rt].sign = 0;
 527                 break;
 528
 529         case OP_ORI:
 530                 v[c.i.rt].value = v[c.i.rs].value | c.i.imm;
 531                 v[c.i.rt].known = v[c.i.rs].known | c.i.imm;
 532                 v[c.i.rt].sign = (v[c.i.rs].sign & 0xffff) ? 0xffff0000 : v[c.i.rs].sign;
 533                 break;
 534
 535         case OP_XORI:
 536                 v[c.i.rt].value = v[c.i.rs].value ^ c.i.imm;
 537                 v[c.i.rt].known = v[c.i.rs].known;
 538                 v[c.i.rt].sign = (v[c.i.rs].sign & 0xffff) ? 0xffff0000 : v[c.i.rs].sign;
 539                 break;
 540
 541         case OP_LUI:
 542                 v[c.i.rt].value = c.i.imm << 16;
 543                 v[c.i.rt].known = 0xffffffff;
 544                 v[c.i.rt].sign = 0;
 545                 break;
 546
 547         case OP_CP0:
 548                 switch (c.r.rs) {
 549                 case OP_CP0_MFC0:
 550                 case OP_CP0_CFC0:
 551                         v[c.r.rt].known = 0;
 552                         v[c.r.rt].sign = 0;
 553                         break;
 554                 default:
 555                         break;
 556                 }
 557                 break;
 558
 559         case OP_CP2:
 560                 if (c.r.op == OP_CP2_BASIC) {
 561                         switch (c.r.rs) {
 562                         case OP_CP2_BASIC_MFC2:
 563                                 switch (c.r.rd) {
 564                                 case 1:
 565                                 case 3:
 566                                 case 5:
 567                                 case 8:
 568                                 case 9:
 569                                 case 10:
 570                                 case 11:
 571                                         /* Signed 16-bit */
 572                                         v[c.r.rt].known = 0;
 573                                         v[c.r.rt].sign = 0xffff8000;
 574                                         break;
 575                                 case 7:
 576                                 case 16:
 577                                 case 17:
 578                                 case 18:
 579                                 case 19:
 580                                         /* Unsigned 16-bit */
 581                                         v[c.r.rt].value = 0;
 582                                         v[c.r.rt].known = 0xffff0000;
 583                                         v[c.r.rt].sign = 0;
 584                                         break;
 585                                 default:
 586                                         /* 32-bit */
 587                                         v[c.r.rt].known = 0;
 588                                         v[c.r.rt].sign = 0;
 589                                         break;
 590                                 }
 591                                 break;
 592                         case OP_CP2_BASIC_CFC2:
 593                                 switch (c.r.rd) {
 594                                 case 4:
 595                                 case 12:
 596                                 case 20:
 597                                 case 26:
 598                                 case 27:
 599                                 case 29:
 600                                 case 30:
 601                                         /* Signed 16-bit */
 602                                         v[c.r.rt].known = 0;
 603                                         v[c.r.rt].sign = 0xffff8000;
 604                                         break;
 605                                 default:
 606                                         /* 32-bit */
 607                                         v[c.r.rt].known = 0;
 608                                         v[c.r.rt].sign = 0;
 609                                         break;
 610                                 }
 611                                 break;
 612                         }
 613                 }
 614                 break;
 615         case OP_LB:
 616                 v[c.i.rt].known = 0;
 617                 v[c.i.rt].sign = 0xffffff80;
 618                 break;
 619         case OP_LH:
 620                 v[c.i.rt].known = 0;
 621                 v[c.i.rt].sign = 0xffff8000;
 622                 break;
 623         case OP_LBU:
 624                 v[c.i.rt].value = 0;
 625                 v[c.i.rt].known = 0xffffff00;
 626                 v[c.i.rt].sign = 0;
 627                 break;
 628         case OP_LHU:
 629                 v[c.i.rt].value = 0;
 630                 v[c.i.rt].known = 0xffff0000;
 631                 v[c.i.rt].sign = 0;
 632                 break;
 633         case OP_LWL:
 634         case OP_LWR:
 635                 /* LWL/LWR don't write the full register if the address is
 636                  * unaligned, so we only need to know the low 2 bits */
 637                 if (v[c.i.rs].known & 0x3) {
 638                         imm = (v[c.i.rs].value & 0x3) * 8;
 639
 640                         if (c.i.op == OP_LWL) {
 641                                 imm = BIT(24 - imm) - 1;
 642                                 v[c.i.rt].sign &= ~imm;
 643                         } else {
 644                                 imm = imm ? GENMASK(31, 32 - imm) : 0;
 645                                 v[c.i.rt].sign = 0;
 646                         }
 647                         v[c.i.rt].known &= ~imm;
 648                         break;
 649                 }
 650                 fallthrough;
 651         case OP_LW:
 652                 v[c.i.rt].known = 0;
 653                 v[c.i.rt].sign = 0;
 654                 break;
 655         case OP_META_MOV:
 656                 v[c.r.rd] = v[c.r.rs];
 657                 break;
 658         case OP_META_EXTC:
 659                 v[c.i.rt].value = (s32)(s8)v[c.i.rs].value;
 660                 if (v[c.i.rs].known & BIT(7)) {
 661                         v[c.i.rt].known = v[c.i.rs].known | 0xffffff00;
 662                         v[c.i.rt].sign = 0;
 663                 } else {
 664                         v[c.i.rt].known = v[c.i.rs].known & 0x7f;
 665                         v[c.i.rt].sign = 0xffffff80;
 666                 }
 667                 break;
 668
 669         case OP_META_EXTS:
 670                 v[c.i.rt].value = (s32)(s16)v[c.i.rs].value;
 671                 if (v[c.i.rs].known & BIT(15)) {
 672                         v[c.i.rt].known = v[c.i.rs].known | 0xffff0000;
 673                         v[c.i.rt].sign = 0;
 674                 } else {
 675                         v[c.i.rt].known = v[c.i.rs].known & 0x7fff;
 676                         v[c.i.rt].sign = 0xffff8000;
 677                 }
 678                 break;
 679
 680         default:
 681                 break;
 682         }
 683
 684         /* Reset register 0 which may have been used as a target */
 685         v[0].value = 0;
 686         v[0].sign = 0;
 687         v[0].known = 0xffffffff;
 688 }
 689
 690 enum psx_map
 691 lightrec_get_constprop_map(const struct lightrec_state *state,
 692                            const struct constprop_data *v, u8 reg, s16 imm)
 693 {
 694         const struct lightrec_mem_map *map;
 695         unsigned int i;
 696         u32 min, max;
 697
 698         min = get_min_value(&v[reg]) + imm;
 699         max = get_max_value(&v[reg]) + imm;
 700
 701         /* Handle the case where max + imm overflows */
 702         if ((min & 0xe0000000) != (max & 0xe0000000))
 703                 return PSX_MAP_UNKNOWN;
 704
 705         pr_debug("Min: 0x%08x max: 0x%08x Known: 0x%08x Sign: 0x%08x\n",
 706                  min, max, v[reg].known, v[reg].sign);
 707
 708         min = kunseg(min);
 709         max = kunseg(max);
 710
 711         for (i = 0; i < state->nb_maps; i++) {
 712                 map = &state->maps[i];
 713
 714                 if (min >= map->pc && min < map->pc + map->length
 715                     && max >= map->pc && max < map->pc + map->length)
 716                         return (enum psx_map) i;
 717         }
 718
 719         return PSX_MAP_UNKNOWN;
 720 }