lightrec: Increase size of hw registers area
[pcsx_rearmed.git] / deps / lightrec / disassembler.h
1 /* SPDX-License-Identifier: LGPL-2.1-or-later */
2 /*
3  * Copyright (C) 2014-2021 Paul Cercueil <paul@crapouillou.net>
4  */
5
6 #ifndef __DISASSEMBLER_H__
7 #define __DISASSEMBLER_H__
8
9 #include "debug.h"
10 #include "lightrec.h"
11 #include "lightrec-config.h"
12
13 #ifndef __packed
14 #define __packed __attribute__((packed))
15 #endif
16
17 #define BIT(x) (1ULL << (x))
18
19 /* Flags for all opcodes */
20 #define LIGHTREC_NO_DS          BIT(0)
21 #define LIGHTREC_SYNC           BIT(1)
22
23 /* Flags for load/store opcodes */
24 #define LIGHTREC_SMC            BIT(2)
25 #define LIGHTREC_NO_INVALIDATE  BIT(3)
26 #define LIGHTREC_NO_MASK        BIT(4)
27 #define LIGHTREC_LOAD_DELAY     BIT(5)
28
29 /* I/O mode for load/store opcodes */
30 #define LIGHTREC_IO_MODE_LSB    6
31 #define LIGHTREC_IO_MODE(x)     ((x) << LIGHTREC_IO_MODE_LSB)
32 #define LIGHTREC_IO_UNKNOWN     0x0
33 #define LIGHTREC_IO_DIRECT      0x1
34 #define LIGHTREC_IO_HW          0x2
35 #define LIGHTREC_IO_RAM         0x3
36 #define LIGHTREC_IO_BIOS        0x4
37 #define LIGHTREC_IO_SCRATCH     0x5
38 #define LIGHTREC_IO_DIRECT_HW   0x6
39 #define LIGHTREC_IO_MASK        LIGHTREC_IO_MODE(0x7)
40 #define LIGHTREC_FLAGS_GET_IO_MODE(x) \
41         (((x) & LIGHTREC_IO_MASK) >> LIGHTREC_IO_MODE_LSB)
42
43 /* Flags for branches */
44 #define LIGHTREC_EMULATE_BRANCH BIT(2)
45 #define LIGHTREC_LOCAL_BRANCH   BIT(3)
46
47 /* Flags for div/mult opcodes */
48 #define LIGHTREC_NO_LO          BIT(2)
49 #define LIGHTREC_NO_HI          BIT(3)
50 #define LIGHTREC_NO_DIV_CHECK   BIT(4)
51
52 #define LIGHTREC_REG_RS_LSB     26
53 #define LIGHTREC_REG_RS(x)      ((x) << LIGHTREC_REG_RS_LSB)
54 #define LIGHTREC_REG_RS_MASK    LIGHTREC_REG_RS(0x3)
55 #define LIGHTREC_FLAGS_GET_RS(x) \
56         (((x) & LIGHTREC_REG_RS_MASK) >> LIGHTREC_REG_RS_LSB)
57
58 #define LIGHTREC_REG_RT_LSB     28
59 #define LIGHTREC_REG_RT(x)      ((x) << LIGHTREC_REG_RT_LSB)
60 #define LIGHTREC_REG_RT_MASK    LIGHTREC_REG_RT(0x3)
61 #define LIGHTREC_FLAGS_GET_RT(x) \
62         (((x) & LIGHTREC_REG_RT_MASK) >> LIGHTREC_REG_RT_LSB)
63
64 #define LIGHTREC_REG_RD_LSB     30
65 #define LIGHTREC_REG_RD(x)      ((x) << LIGHTREC_REG_RD_LSB)
66 #define LIGHTREC_REG_RD_MASK    LIGHTREC_REG_RD(0x3)
67 #define LIGHTREC_FLAGS_GET_RD(x) \
68         (((x) & LIGHTREC_REG_RD_MASK) >> LIGHTREC_REG_RD_LSB)
69
70 #define LIGHTREC_REG_NOOP       0x0
71 #define LIGHTREC_REG_UNLOAD     0x1
72 #define LIGHTREC_REG_DISCARD    0x2
73 #define LIGHTREC_REG_CLEAN      0x3
74
75 struct block;
76
77 enum standard_opcodes {
78         OP_SPECIAL              = 0x00,
79         OP_REGIMM               = 0x01,
80         OP_J                    = 0x02,
81         OP_JAL                  = 0x03,
82         OP_BEQ                  = 0x04,
83         OP_BNE                  = 0x05,
84         OP_BLEZ                 = 0x06,
85         OP_BGTZ                 = 0x07,
86         OP_ADDI                 = 0x08,
87         OP_ADDIU                = 0x09,
88         OP_SLTI                 = 0x0a,
89         OP_SLTIU                = 0x0b,
90         OP_ANDI                 = 0x0c,
91         OP_ORI                  = 0x0d,
92         OP_XORI                 = 0x0e,
93         OP_LUI                  = 0x0f,
94         OP_CP0                  = 0x10,
95         OP_CP2                  = 0x12,
96         OP_LB                   = 0x20,
97         OP_LH                   = 0x21,
98         OP_LWL                  = 0x22,
99         OP_LW                   = 0x23,
100         OP_LBU                  = 0x24,
101         OP_LHU                  = 0x25,
102         OP_LWR                  = 0x26,
103         OP_SB                   = 0x28,
104         OP_SH                   = 0x29,
105         OP_SWL                  = 0x2a,
106         OP_SW                   = 0x2b,
107         OP_SWR                  = 0x2e,
108         OP_LWC2                 = 0x32,
109         OP_SWC2                 = 0x3a,
110
111         OP_META                 = 0x3b,
112
113         OP_META_MULT2           = 0x19,
114         OP_META_MULTU2          = 0x1a,
115 };
116
117 enum special_opcodes {
118         OP_SPECIAL_SLL          = 0x00,
119         OP_SPECIAL_SRL          = 0x02,
120         OP_SPECIAL_SRA          = 0x03,
121         OP_SPECIAL_SLLV         = 0x04,
122         OP_SPECIAL_SRLV         = 0x06,
123         OP_SPECIAL_SRAV         = 0x07,
124         OP_SPECIAL_JR           = 0x08,
125         OP_SPECIAL_JALR         = 0x09,
126         OP_SPECIAL_SYSCALL      = 0x0c,
127         OP_SPECIAL_BREAK        = 0x0d,
128         OP_SPECIAL_MFHI         = 0x10,
129         OP_SPECIAL_MTHI         = 0x11,
130         OP_SPECIAL_MFLO         = 0x12,
131         OP_SPECIAL_MTLO         = 0x13,
132         OP_SPECIAL_MULT         = 0x18,
133         OP_SPECIAL_MULTU        = 0x19,
134         OP_SPECIAL_DIV          = 0x1a,
135         OP_SPECIAL_DIVU         = 0x1b,
136         OP_SPECIAL_ADD          = 0x20,
137         OP_SPECIAL_ADDU         = 0x21,
138         OP_SPECIAL_SUB          = 0x22,
139         OP_SPECIAL_SUBU         = 0x23,
140         OP_SPECIAL_AND          = 0x24,
141         OP_SPECIAL_OR           = 0x25,
142         OP_SPECIAL_XOR          = 0x26,
143         OP_SPECIAL_NOR          = 0x27,
144         OP_SPECIAL_SLT          = 0x2a,
145         OP_SPECIAL_SLTU         = 0x2b,
146 };
147
148 enum regimm_opcodes {
149         OP_REGIMM_BLTZ          = 0x00,
150         OP_REGIMM_BGEZ          = 0x01,
151         OP_REGIMM_BLTZAL        = 0x10,
152         OP_REGIMM_BGEZAL        = 0x11,
153 };
154
155 enum cp0_opcodes {
156         OP_CP0_MFC0             = 0x00,
157         OP_CP0_CFC0             = 0x02,
158         OP_CP0_MTC0             = 0x04,
159         OP_CP0_CTC0             = 0x06,
160         OP_CP0_RFE              = 0x10,
161 };
162
163 enum cp2_opcodes {
164         OP_CP2_BASIC            = 0x00,
165         OP_CP2_RTPS             = 0x01,
166         OP_CP2_NCLIP            = 0x06,
167         OP_CP2_OP               = 0x0c,
168         OP_CP2_DPCS             = 0x10,
169         OP_CP2_INTPL            = 0x11,
170         OP_CP2_MVMVA            = 0x12,
171         OP_CP2_NCDS             = 0x13,
172         OP_CP2_CDP              = 0x14,
173         OP_CP2_NCDT             = 0x16,
174         OP_CP2_NCCS             = 0x1b,
175         OP_CP2_CC               = 0x1c,
176         OP_CP2_NCS              = 0x1e,
177         OP_CP2_NCT              = 0x20,
178         OP_CP2_SQR              = 0x28,
179         OP_CP2_DCPL             = 0x29,
180         OP_CP2_DPCT             = 0x2a,
181         OP_CP2_AVSZ3            = 0x2d,
182         OP_CP2_AVSZ4            = 0x2e,
183         OP_CP2_RTPT             = 0x30,
184         OP_CP2_GPF              = 0x3d,
185         OP_CP2_GPL              = 0x3e,
186         OP_CP2_NCCT             = 0x3f,
187 };
188
189 enum cp2_basic_opcodes {
190         OP_CP2_BASIC_MFC2       = 0x00,
191         OP_CP2_BASIC_CFC2       = 0x02,
192         OP_CP2_BASIC_MTC2       = 0x04,
193         OP_CP2_BASIC_CTC2       = 0x06,
194 };
195
196 enum meta_opcodes {
197         OP_META_MOV             = 0x00,
198
199         OP_META_EXTC            = 0x01,
200         OP_META_EXTS            = 0x02,
201
202         OP_META_COM             = 0x03,
203 };
204
205 struct opcode_r {
206 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
207         u32 zero :6;
208         u32 rs   :5;
209         u32 rt   :5;
210         u32 rd   :5;
211         u32 imm  :5;
212         u32 op   :6;
213 #else
214         u32 op   :6;
215         u32 imm  :5;
216         u32 rd   :5;
217         u32 rt   :5;
218         u32 rs   :5;
219         u32 zero :6;
220 #endif
221 } __packed;
222
223 struct opcode_i {
224 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
225         u32 op  :6;
226         u32 rs  :5;
227         u32 rt  :5;
228         u32 imm :16;
229 #else
230         u32 imm :16;
231         u32 rt  :5;
232         u32 rs  :5;
233         u32 op  :6;
234 #endif
235 } __packed;
236
237 struct opcode_j {
238 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
239         u32 op  :6;
240         u32 imm :26;
241 #else
242         u32 imm :26;
243         u32 op  :6;
244 #endif
245 } __packed;
246
247 struct opcode_m {
248 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
249         u32 meta :6;
250         u32 rs   :5;
251         u32 rt   :5;
252         u32 rd   :5;
253         u32 imm  :6;
254         u32 op   :5;
255 #else
256         u32 op   :5;
257         u32 imm  :6;
258         u32 rd   :5;
259         u32 rt   :5;
260         u32 rs   :5;
261         u32 meta :6;
262 #endif
263 };
264
265 union code {
266         /* Keep in sync with struct opcode */
267         u32 opcode;
268         struct opcode_r r;
269         struct opcode_i i;
270         struct opcode_j j;
271         struct opcode_m m;
272 };
273
274 struct opcode {
275         /* Keep this union at the first position */
276         union {
277                 union code c;
278
279                 /* Keep in sync with union code */
280                 u32 opcode;
281                 struct opcode_r r;
282                 struct opcode_i i;
283                 struct opcode_j j;
284                 struct opcode_m m;
285         };
286         u32 flags;
287 };
288
289 struct opcode_list {
290         u16 nb_ops;
291         struct opcode ops[];
292 };
293
294 void lightrec_print_disassembly(const struct block *block, const u32 *code);
295
296 static inline _Bool op_flag_no_ds(u32 flags)
297 {
298         return OPT_SWITCH_DELAY_SLOTS && (flags & LIGHTREC_NO_DS);
299 }
300
301 static inline _Bool op_flag_sync(u32 flags)
302 {
303         return OPT_LOCAL_BRANCHES && (flags & LIGHTREC_SYNC);
304 }
305
306 static inline _Bool op_flag_smc(u32 flags)
307 {
308         return OPT_FLAG_IO && (flags & LIGHTREC_SMC);
309 }
310
311 static inline _Bool op_flag_no_invalidate(u32 flags)
312 {
313         return OPT_FLAG_IO && (flags & LIGHTREC_NO_INVALIDATE);
314 }
315
316 static inline _Bool op_flag_no_mask(u32 flags)
317 {
318         return OPT_FLAG_IO && (flags & LIGHTREC_NO_MASK);
319 }
320
321 static inline _Bool op_flag_load_delay(u32 flags)
322 {
323         return OPT_HANDLE_LOAD_DELAYS && (flags & LIGHTREC_LOAD_DELAY);
324 }
325
326 static inline _Bool op_flag_emulate_branch(u32 flags)
327 {
328         return OPT_DETECT_IMPOSSIBLE_BRANCHES &&
329                 (flags & LIGHTREC_EMULATE_BRANCH);
330 }
331
332 static inline _Bool op_flag_local_branch(u32 flags)
333 {
334         return OPT_LOCAL_BRANCHES && (flags & LIGHTREC_LOCAL_BRANCH);
335 }
336
337 static inline _Bool op_flag_no_lo(u32 flags)
338 {
339         return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_LO);
340 }
341
342 static inline _Bool op_flag_no_hi(u32 flags)
343 {
344         return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_HI);
345 }
346
347 static inline _Bool op_flag_no_div_check(u32 flags)
348 {
349         return OPT_FLAG_MULT_DIV && (flags & LIGHTREC_NO_DIV_CHECK);
350 }
351
352 #endif /* __DISASSEMBLER_H__ */