1 // SPDX-License-Identifier: LGPL-2.1-or-later
3 * Copyright (C) 2014-2021 Paul Cercueil <paul@crapouillou.net>
6 #include "lightrec-config.h"
7 #include "disassembler.h"
9 #include "memmanager.h"
10 #include "optimizer.h"
18 #define IF_OPT(opt, ptr) ((opt) ? (ptr) : NULL)
20 struct optimizer_list {
21 void (**optimizers)(struct opcode *);
22 unsigned int nb_optimizers;
25 static bool is_nop(union code op);
27 bool is_unconditional_jump(union code c)
31 return c.r.op == OP_SPECIAL_JR || c.r.op == OP_SPECIAL_JALR;
37 return c.i.rs == c.i.rt;
39 return (c.r.rt == OP_REGIMM_BGEZ ||
40 c.r.rt == OP_REGIMM_BGEZAL) && c.i.rs == 0;
46 bool is_syscall(union code c)
48 return (c.i.op == OP_SPECIAL && c.r.op == OP_SPECIAL_SYSCALL) ||
49 (c.i.op == OP_CP0 && (c.r.rs == OP_CP0_MTC0 ||
50 c.r.rs == OP_CP0_CTC0) &&
51 (c.r.rd == 12 || c.r.rd == 13));
54 static u64 opcode_read_mask(union code op)
59 case OP_SPECIAL_SYSCALL:
60 case OP_SPECIAL_BREAK:
79 return BIT(op.r.rs) | BIT(op.r.rt);
90 if (op.r.op == OP_CP2_BASIC) {
92 case OP_CP2_BASIC_MTC2:
93 case OP_CP2_BASIC_CTC2:
105 if (op.i.rs == op.i.rt)
116 return BIT(op.i.rs) | BIT(op.i.rt);
122 static u64 mult_div_write_mask(union code op)
126 if (!OPT_FLAG_MULT_DIV)
127 return BIT(REG_LO) | BIT(REG_HI);
130 flags = BIT(op.r.rd);
134 flags |= BIT(op.r.imm);
136 flags |= BIT(REG_HI);
141 static u64 opcode_write_mask(union code op)
146 return mult_div_write_mask(op);
150 case OP_SPECIAL_SYSCALL:
151 case OP_SPECIAL_BREAK:
153 case OP_SPECIAL_MULT:
154 case OP_SPECIAL_MULTU:
156 case OP_SPECIAL_DIVU:
157 return mult_div_write_mask(op);
158 case OP_SPECIAL_MTHI:
160 case OP_SPECIAL_MTLO:
196 if (op.r.op == OP_CP2_BASIC) {
198 case OP_CP2_BASIC_MFC2:
199 case OP_CP2_BASIC_CFC2:
208 case OP_REGIMM_BLTZAL:
209 case OP_REGIMM_BGEZAL:
221 bool opcode_reads_register(union code op, u8 reg)
223 return opcode_read_mask(op) & BIT(reg);
226 bool opcode_writes_register(union code op, u8 reg)
228 return opcode_write_mask(op) & BIT(reg);
231 static int find_prev_writer(const struct opcode *list, unsigned int offset, u8 reg)
236 if (op_flag_sync(list[offset].flags))
239 for (i = offset; i > 0; i--) {
242 if (opcode_writes_register(c, reg)) {
243 if (i > 1 && has_delay_slot(list[i - 2].c))
249 if (op_flag_sync(list[i - 1].flags) ||
251 opcode_reads_register(c, reg))
258 static int find_next_reader(const struct opcode *list, unsigned int offset, u8 reg)
263 if (op_flag_sync(list[offset].flags))
266 for (i = offset; ; i++) {
269 if (opcode_reads_register(c, reg)) {
270 if (i > 0 && has_delay_slot(list[i - 1].c))
276 if (op_flag_sync(list[i].flags) ||
277 has_delay_slot(c) || opcode_writes_register(c, reg))
284 static bool reg_is_dead(const struct opcode *list, unsigned int offset, u8 reg)
288 if (op_flag_sync(list[offset].flags))
291 for (i = offset + 1; ; i++) {
292 if (opcode_reads_register(list[i].c, reg))
295 if (opcode_writes_register(list[i].c, reg))
298 if (has_delay_slot(list[i].c)) {
299 if (op_flag_no_ds(list[i].flags) ||
300 opcode_reads_register(list[i + 1].c, reg))
303 return opcode_writes_register(list[i + 1].c, reg);
308 static bool reg_is_read(const struct opcode *list,
309 unsigned int a, unsigned int b, u8 reg)
311 /* Return true if reg is read in one of the opcodes of the interval
314 if (!is_nop(list[a].c) && opcode_reads_register(list[a].c, reg))
321 static bool reg_is_written(const struct opcode *list,
322 unsigned int a, unsigned int b, u8 reg)
324 /* Return true if reg is written in one of the opcodes of the interval
328 if (!is_nop(list[a].c) && opcode_writes_register(list[a].c, reg))
335 static bool reg_is_read_or_written(const struct opcode *list,
336 unsigned int a, unsigned int b, u8 reg)
338 return reg_is_read(list, a, b, reg) || reg_is_written(list, a, b, reg);
341 static bool opcode_is_load(union code op)
358 static bool opcode_is_store(union code op)
373 static u8 opcode_get_io_size(union code op)
389 bool opcode_is_io(union code op)
391 return opcode_is_load(op) || opcode_is_store(op);
395 static bool is_nop(union code op)
397 if (opcode_writes_register(op, 0)) {
400 return op.r.rs != OP_CP0_MFC0;
418 return op.r.rd == op.r.rt && op.r.rd == op.r.rs;
420 case OP_SPECIAL_ADDU:
421 return (op.r.rd == op.r.rt && op.r.rs == 0) ||
422 (op.r.rd == op.r.rs && op.r.rt == 0);
424 case OP_SPECIAL_SUBU:
425 return op.r.rd == op.r.rs && op.r.rt == 0;
427 if (op.r.rd == op.r.rt)
428 return op.r.rd == op.r.rs || op.r.rs == 0;
430 return (op.r.rd == op.r.rs) && op.r.rt == 0;
434 return op.r.rd == op.r.rt && op.r.imm == 0;
435 case OP_SPECIAL_MFHI:
436 case OP_SPECIAL_MFLO:
444 return op.i.rt == op.i.rs && op.i.imm == 0;
446 return (op.i.rs == 0 || op.i.imm == 1);
448 return (op.i.op == OP_REGIMM_BLTZ ||
449 op.i.op == OP_REGIMM_BLTZAL) &&
450 (op.i.rs == 0 || op.i.imm == 1);
452 return (op.i.rs == op.i.rt || op.i.imm == 1);
458 bool load_in_delay_slot(union code op)
472 if (op.r.op == OP_CP2_BASIC) {
474 case OP_CP2_BASIC_MFC2:
475 case OP_CP2_BASIC_CFC2:
498 static u32 lightrec_propagate_consts(const struct opcode *op,
499 const struct opcode *prev,
502 union code c = prev->c;
504 /* Register $zero is always, well, zero */
508 if (op_flag_sync(op->flags))
515 if (known & BIT(c.r.rt)) {
516 known |= BIT(c.r.rd);
517 v[c.r.rd] = v[c.r.rt] << c.r.imm;
519 known &= ~BIT(c.r.rd);
523 if (known & BIT(c.r.rt)) {
524 known |= BIT(c.r.rd);
525 v[c.r.rd] = v[c.r.rt] >> c.r.imm;
527 known &= ~BIT(c.r.rd);
531 if (known & BIT(c.r.rt)) {
532 known |= BIT(c.r.rd);
533 v[c.r.rd] = (s32)v[c.r.rt] >> c.r.imm;
535 known &= ~BIT(c.r.rd);
538 case OP_SPECIAL_SLLV:
539 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
540 known |= BIT(c.r.rd);
541 v[c.r.rd] = v[c.r.rt] << (v[c.r.rs] & 0x1f);
543 known &= ~BIT(c.r.rd);
546 case OP_SPECIAL_SRLV:
547 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
548 known |= BIT(c.r.rd);
549 v[c.r.rd] = v[c.r.rt] >> (v[c.r.rs] & 0x1f);
551 known &= ~BIT(c.r.rd);
554 case OP_SPECIAL_SRAV:
555 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
556 known |= BIT(c.r.rd);
557 v[c.r.rd] = (s32)v[c.r.rt]
558 >> (v[c.r.rs] & 0x1f);
560 known &= ~BIT(c.r.rd);
564 case OP_SPECIAL_ADDU:
565 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
566 known |= BIT(c.r.rd);
567 v[c.r.rd] = (s32)v[c.r.rt] + (s32)v[c.r.rs];
569 known &= ~BIT(c.r.rd);
573 case OP_SPECIAL_SUBU:
574 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
575 known |= BIT(c.r.rd);
576 v[c.r.rd] = v[c.r.rt] - v[c.r.rs];
578 known &= ~BIT(c.r.rd);
582 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
583 known |= BIT(c.r.rd);
584 v[c.r.rd] = v[c.r.rt] & v[c.r.rs];
586 known &= ~BIT(c.r.rd);
590 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
591 known |= BIT(c.r.rd);
592 v[c.r.rd] = v[c.r.rt] | v[c.r.rs];
594 known &= ~BIT(c.r.rd);
598 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
599 known |= BIT(c.r.rd);
600 v[c.r.rd] = v[c.r.rt] ^ v[c.r.rs];
602 known &= ~BIT(c.r.rd);
606 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
607 known |= BIT(c.r.rd);
608 v[c.r.rd] = ~(v[c.r.rt] | v[c.r.rs]);
610 known &= ~BIT(c.r.rd);
614 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
615 known |= BIT(c.r.rd);
616 v[c.r.rd] = (s32)v[c.r.rs] < (s32)v[c.r.rt];
618 known &= ~BIT(c.r.rd);
621 case OP_SPECIAL_SLTU:
622 if (known & BIT(c.r.rt) && known & BIT(c.r.rs)) {
623 known |= BIT(c.r.rd);
624 v[c.r.rd] = v[c.r.rs] < v[c.r.rt];
626 known &= ~BIT(c.r.rd);
629 case OP_SPECIAL_MULT:
630 case OP_SPECIAL_MULTU:
632 case OP_SPECIAL_DIVU:
633 if (OPT_FLAG_MULT_DIV && c.r.rd)
634 known &= ~BIT(c.r.rd);
635 if (OPT_FLAG_MULT_DIV && c.r.imm)
636 known &= ~BIT(c.r.imm);
638 case OP_SPECIAL_MFLO:
639 case OP_SPECIAL_MFHI:
640 known &= ~BIT(c.r.rd);
648 if (OPT_FLAG_MULT_DIV && (known & BIT(c.r.rs))) {
650 known |= BIT(c.r.rd);
653 v[c.r.rd] = v[c.r.rs] << c.r.op;
659 known |= BIT(c.r.imm);
662 v[c.r.imm] = v[c.r.rs] << (c.r.op - 32);
663 else if (c.i.op == OP_META_MULT2)
664 v[c.r.imm] = (s32) v[c.r.rs] >> (32 - c.r.op);
666 v[c.r.imm] = v[c.r.rs] >> (32 - c.r.op);
669 if (OPT_FLAG_MULT_DIV && c.r.rd)
670 known &= ~BIT(c.r.rd);
671 if (OPT_FLAG_MULT_DIV && c.r.imm)
672 known &= ~BIT(c.r.imm);
679 if (known & BIT(c.i.rs)) {
680 known |= BIT(c.i.rt);
681 v[c.i.rt] = v[c.i.rs] + (s32)(s16)c.i.imm;
683 known &= ~BIT(c.i.rt);
687 if (known & BIT(c.i.rs)) {
688 known |= BIT(c.i.rt);
689 v[c.i.rt] = (s32)v[c.i.rs] < (s32)(s16)c.i.imm;
691 known &= ~BIT(c.i.rt);
695 if (known & BIT(c.i.rs)) {
696 known |= BIT(c.i.rt);
697 v[c.i.rt] = v[c.i.rs] < (u32)(s32)(s16)c.i.imm;
699 known &= ~BIT(c.i.rt);
703 if (known & BIT(c.i.rs)) {
704 known |= BIT(c.i.rt);
705 v[c.i.rt] = v[c.i.rs] & c.i.imm;
707 known &= ~BIT(c.i.rt);
711 if (known & BIT(c.i.rs)) {
712 known |= BIT(c.i.rt);
713 v[c.i.rt] = v[c.i.rs] | c.i.imm;
715 known &= ~BIT(c.i.rt);
719 if (known & BIT(c.i.rs)) {
720 known |= BIT(c.i.rt);
721 v[c.i.rt] = v[c.i.rs] ^ c.i.imm;
723 known &= ~BIT(c.i.rt);
727 known |= BIT(c.i.rt);
728 v[c.i.rt] = c.i.imm << 16;
734 known &= ~BIT(c.r.rt);
739 if (c.r.op == OP_CP2_BASIC) {
741 case OP_CP2_BASIC_MFC2:
742 case OP_CP2_BASIC_CFC2:
743 known &= ~BIT(c.r.rt);
756 known &= ~BIT(c.i.rt);
759 if (known & BIT(c.r.rs)) {
760 known |= BIT(c.r.rd);
761 v[c.r.rd] = v[c.r.rs];
763 known &= ~BIT(c.r.rd);
773 static void lightrec_optimize_sll_sra(struct opcode *list, unsigned int offset)
775 struct opcode *prev, *prev2 = NULL, *curr = &list[offset];
776 struct opcode *to_change, *to_nop;
779 if (curr->r.imm != 24 && curr->r.imm != 16)
782 idx = find_prev_writer(list, offset, curr->r.rt);
788 if (prev->i.op != OP_SPECIAL || prev->r.op != OP_SPECIAL_SLL ||
789 prev->r.imm != curr->r.imm || prev->r.rd != curr->r.rt)
792 if (prev->r.rd != prev->r.rt && curr->r.rd != curr->r.rt) {
797 if (!reg_is_dead(list, offset, curr->r.rt) ||
798 reg_is_read_or_written(list, idx, offset, curr->r.rd))
801 /* If rY is dead after the SRL, and rZ is not used after the SLL,
802 * we can change rY to rZ */
804 pr_debug("Detected SLL/SRA with middle temp register\n");
805 prev->r.rd = curr->r.rd;
806 curr->r.rt = prev->r.rd;
809 /* We got a SLL/SRA combo. If imm #16, that's a cast to u16.
810 * If imm #24 that's a cast to u8.
812 * First of all, make sure that the target register of the SLL is not
813 * read before the SRA. */
815 if (prev->r.rd == prev->r.rt) {
822 /* rX is used after the SRA - we cannot convert it. */
823 if (prev->r.rd != curr->r.rd && !reg_is_dead(list, offset, prev->r.rd))
833 idx2 = find_prev_writer(list, idx, prev->r.rt);
835 /* Note that PSX games sometimes do casts after
836 * a LHU or LBU; in this case we can change the
837 * load opcode to a LH or LB, and the cast can
838 * be changed to a MOV or a simple NOP. */
842 if (curr->r.rd != prev2->i.rt &&
843 !reg_is_dead(list, offset, prev2->i.rt))
845 else if (curr->r.imm == 16 && prev2->i.op == OP_LHU)
847 else if (curr->r.imm == 24 && prev2->i.op == OP_LBU)
853 if (curr->r.rd == prev2->i.rt) {
854 to_change->opcode = 0;
855 } else if (reg_is_dead(list, offset, prev2->i.rt) &&
856 !reg_is_read_or_written(list, idx2 + 1, offset, curr->r.rd)) {
857 /* The target register of the SRA is dead after the
858 * LBU/LHU; we can change the target register of the
859 * LBU/LHU to the one of the SRA. */
860 prev2->i.rt = curr->r.rd;
861 to_change->opcode = 0;
863 to_change->i.op = OP_META_MOV;
864 to_change->r.rd = curr->r.rd;
865 to_change->r.rs = prev2->i.rt;
868 if (to_nop->r.imm == 24)
869 pr_debug("Convert LBU+SLL+SRA to LB\n");
871 pr_debug("Convert LHU+SLL+SRA to LH\n");
876 pr_debug("Convert SLL/SRA #%u to EXT%c\n",
878 prev->r.imm == 24 ? 'C' : 'S');
880 if (to_change == prev) {
881 to_change->i.rs = prev->r.rt;
882 to_change->i.rt = curr->r.rd;
884 to_change->i.rt = curr->r.rd;
885 to_change->i.rs = prev->r.rt;
888 if (to_nop->r.imm == 24)
889 to_change->i.op = OP_META_EXTC;
891 to_change->i.op = OP_META_EXTS;
897 static void lightrec_remove_useless_lui(struct block *block, unsigned int offset,
898 u32 known, u32 *values)
900 struct opcode *list = block->opcode_list,
901 *op = &block->opcode_list[offset];
904 if (!op_flag_sync(op->flags) && (known & BIT(op->i.rt)) &&
905 values[op->i.rt] == op->i.imm << 16) {
906 pr_debug("Converting duplicated LUI to NOP\n");
911 if (op->i.imm != 0 || op->i.rt == 0)
914 reader = find_next_reader(list, offset + 1, op->i.rt);
918 if (opcode_writes_register(list[reader].c, op->i.rt) ||
919 reg_is_dead(list, reader, op->i.rt)) {
920 pr_debug("Removing useless LUI 0x0\n");
922 if (list[reader].i.rs == op->i.rt)
923 list[reader].i.rs = 0;
924 if (list[reader].i.op == OP_SPECIAL &&
925 list[reader].i.rt == op->i.rt)
926 list[reader].i.rt = 0;
931 static void lightrec_modify_lui(struct block *block, unsigned int offset)
933 union code c, *lui = &block->opcode_list[offset].c;
934 bool stop = false, stop_next = false;
937 for (i = offset + 1; !stop && i < block->nb_ops; i++) {
938 c = block->opcode_list[i].c;
941 if ((opcode_is_store(c) && c.i.rt == lui->i.rt)
942 || (!opcode_is_load(c) && opcode_reads_register(c, lui->i.rt)))
945 if (opcode_writes_register(c, lui->i.rt)) {
946 pr_debug("Convert LUI at offset 0x%x to kuseg\n",
948 lui->i.imm = kunseg(lui->i.imm << 16) >> 16;
952 if (has_delay_slot(c))
957 static int lightrec_transform_branches(struct lightrec_state *state,
964 for (i = 0; i < block->nb_ops; i++) {
965 op = &block->opcode_list[i];
969 /* Transform J opcode into BEQ $zero, $zero if possible. */
970 offset = (s32)((block->pc & 0xf0000000) >> 2 | op->j.imm)
971 - (s32)(block->pc >> 2) - (s32)i - 1;
973 if (offset == (s16)offset) {
974 pr_debug("Transform J into BEQ $zero, $zero\n");
990 static inline bool is_power_of_two(u32 value)
992 return popcount32(value) == 1;
995 static int lightrec_transform_ops(struct lightrec_state *state, struct block *block)
997 struct opcode *list = block->opcode_list;
998 struct opcode *prev, *op = NULL;
1000 u32 values[32] = { 0 };
1004 for (i = 0; i < block->nb_ops; i++) {
1009 known = lightrec_propagate_consts(op, prev, known, values);
1011 /* Transform all opcodes detected as useless to real NOPs
1012 * (0x0: SLL r0, r0, #0) */
1013 if (op->opcode != 0 && is_nop(op->c)) {
1014 pr_debug("Converting useless opcode 0x%08x to NOP\n",
1024 if (op->i.rs == op->i.rt) {
1027 } else if (op->i.rs == 0) {
1028 op->i.rs = op->i.rt;
1034 if (op->i.rs == 0) {
1035 op->i.rs = op->i.rt;
1041 if (!prev || !has_delay_slot(prev->c))
1042 lightrec_modify_lui(block, i);
1043 lightrec_remove_useless_lui(block, i, known, values);
1046 /* Transform ORI/ADDI/ADDIU with imm #0 or ORR/ADD/ADDU/SUB/SUBU
1047 * with register $zero to the MOV meta-opcode */
1051 if (op->i.imm == 0) {
1052 pr_debug("Convert ORI/ADDI/ADDIU #0 to MOV\n");
1053 op->i.op = OP_META_MOV;
1054 op->r.rd = op->i.rt;
1059 case OP_SPECIAL_SRA:
1060 if (op->r.imm == 0) {
1061 pr_debug("Convert SRA #0 to MOV\n");
1062 op->i.op = OP_META_MOV;
1063 op->r.rs = op->r.rt;
1067 lightrec_optimize_sll_sra(block->opcode_list, i);
1069 case OP_SPECIAL_SLL:
1070 case OP_SPECIAL_SRL:
1071 if (op->r.imm == 0) {
1072 pr_debug("Convert SLL/SRL #0 to MOV\n");
1073 op->i.op = OP_META_MOV;
1074 op->r.rs = op->r.rt;
1077 case OP_SPECIAL_MULT:
1078 case OP_SPECIAL_MULTU:
1079 if ((known & BIT(op->r.rs)) &&
1080 is_power_of_two(values[op->r.rs])) {
1082 op->c.i.rs = op->c.i.rt;
1084 } else if (!(known & BIT(op->r.rt)) ||
1085 !is_power_of_two(values[op->r.rt])) {
1089 pr_debug("Multiply by power-of-two: %u\n",
1092 if (op->r.op == OP_SPECIAL_MULT)
1093 op->i.op = OP_META_MULT2;
1095 op->i.op = OP_META_MULTU2;
1097 op->r.op = ffs32(values[op->r.rt]);
1100 case OP_SPECIAL_ADD:
1101 case OP_SPECIAL_ADDU:
1102 if (op->r.rs == 0) {
1103 pr_debug("Convert OR/ADD $zero to MOV\n");
1104 op->i.op = OP_META_MOV;
1105 op->r.rs = op->r.rt;
1108 case OP_SPECIAL_SUB:
1109 case OP_SPECIAL_SUBU:
1110 if (op->r.rt == 0) {
1111 pr_debug("Convert OR/ADD/SUB $zero to MOV\n");
1112 op->i.op = OP_META_MOV;
1127 static bool lightrec_can_switch_delay_slot(union code op, union code next_op)
1132 case OP_SPECIAL_JALR:
1133 if (opcode_reads_register(next_op, op.r.rd) ||
1134 opcode_writes_register(next_op, op.r.rd))
1138 if (opcode_writes_register(next_op, op.r.rs))
1148 if (opcode_reads_register(next_op, 31) ||
1149 opcode_writes_register(next_op, 31))
1155 if (op.i.rt && opcode_writes_register(next_op, op.i.rt))
1160 if (op.i.rs && opcode_writes_register(next_op, op.i.rs))
1165 case OP_REGIMM_BLTZAL:
1166 case OP_REGIMM_BGEZAL:
1167 if (opcode_reads_register(next_op, 31) ||
1168 opcode_writes_register(next_op, 31))
1171 case OP_REGIMM_BLTZ:
1172 case OP_REGIMM_BGEZ:
1173 if (op.i.rs && opcode_writes_register(next_op, op.i.rs))
1185 static int lightrec_switch_delay_slots(struct lightrec_state *state, struct block *block)
1187 struct opcode *list, *next = &block->opcode_list[0];
1189 union code op, next_op;
1192 for (i = 0; i < block->nb_ops - 1; i++) {
1194 next = &block->opcode_list[i + 1];
1198 if (!has_delay_slot(op) || op_flag_no_ds(list->flags) ||
1199 op_flag_emulate_branch(list->flags) ||
1200 op.opcode == 0 || next_op.opcode == 0)
1203 if (i && has_delay_slot(block->opcode_list[i - 1].c) &&
1204 !op_flag_no_ds(block->opcode_list[i - 1].flags))
1207 if (op_flag_sync(next->flags))
1210 if (!lightrec_can_switch_delay_slot(list->c, next_op))
1213 pr_debug("Swap branch and delay slot opcodes "
1214 "at offsets 0x%x / 0x%x\n",
1215 i << 2, (i + 1) << 2);
1217 flags = next->flags | (list->flags & LIGHTREC_SYNC);
1220 next->flags = (list->flags | LIGHTREC_NO_DS) & ~LIGHTREC_SYNC;
1221 list->flags = flags | LIGHTREC_NO_DS;
1227 static int shrink_opcode_list(struct lightrec_state *state, struct block *block, u16 new_size)
1229 struct opcode_list *list, *old_list;
1231 if (new_size >= block->nb_ops) {
1232 pr_err("Invalid shrink size (%u vs %u)\n",
1233 new_size, block->nb_ops);
1237 list = lightrec_malloc(state, MEM_FOR_IR,
1238 sizeof(*list) + sizeof(struct opcode) * new_size);
1240 pr_err("Unable to allocate memory\n");
1244 old_list = container_of(block->opcode_list, struct opcode_list, ops);
1245 memcpy(list->ops, old_list->ops, sizeof(struct opcode) * new_size);
1247 lightrec_free_opcode_list(state, block->opcode_list);
1248 list->nb_ops = new_size;
1249 block->nb_ops = new_size;
1250 block->opcode_list = list->ops;
1252 pr_debug("Shrunk opcode list of block PC 0x%08x to %u opcodes\n",
1253 block->pc, new_size);
1258 static int lightrec_detect_impossible_branches(struct lightrec_state *state,
1259 struct block *block)
1261 struct opcode *op, *list = block->opcode_list, *next = &list[0];
1266 for (i = 0; i < block->nb_ops - 1; i++) {
1268 next = &list[i + 1];
1270 if (!has_delay_slot(op->c) ||
1271 (!load_in_delay_slot(next->c) &&
1272 !has_delay_slot(next->c) &&
1273 !(next->i.op == OP_CP0 && next->r.rs == OP_CP0_RFE)))
1276 if (op->c.opcode == next->c.opcode) {
1277 /* The delay slot is the exact same opcode as the branch
1278 * opcode: this is effectively a NOP */
1283 offset = i + 1 + (s16)op->i.imm;
1284 if (load_in_delay_slot(next->c) &&
1285 (offset >= 0 && offset < block->nb_ops) &&
1286 !opcode_reads_register(list[offset].c, next->c.i.rt)) {
1287 /* The 'impossible' branch is a local branch - we can
1288 * verify here that the first opcode of the target does
1289 * not use the target register of the delay slot */
1291 pr_debug("Branch at offset 0x%x has load delay slot, "
1292 "but is local and dest opcode does not read "
1293 "dest register\n", i << 2);
1297 op->flags |= LIGHTREC_EMULATE_BRANCH;
1300 pr_debug("First opcode of block PC 0x%08x is an impossible branch\n",
1303 /* If the first opcode is an 'impossible' branch, we
1304 * only keep the first two opcodes of the block (the
1305 * branch itself + its delay slot) */
1306 if (block->nb_ops > 2)
1307 ret = shrink_opcode_list(state, block, 2);
1315 static int lightrec_local_branches(struct lightrec_state *state, struct block *block)
1317 struct opcode *list;
1321 for (i = 0; i < block->nb_ops; i++) {
1322 list = &block->opcode_list[i];
1324 if (should_emulate(list))
1327 switch (list->i.op) {
1333 offset = i + 1 + (s16)list->i.imm;
1334 if (offset >= 0 && offset < block->nb_ops)
1341 pr_debug("Found local branch to offset 0x%x\n", offset << 2);
1343 if (should_emulate(&block->opcode_list[offset])) {
1344 pr_debug("Branch target must be emulated - skip\n");
1348 if (offset && has_delay_slot(block->opcode_list[offset - 1].c)) {
1349 pr_debug("Branch target is a delay slot - skip\n");
1353 pr_debug("Adding sync at offset 0x%x\n", offset << 2);
1355 block->opcode_list[offset].flags |= LIGHTREC_SYNC;
1356 list->flags |= LIGHTREC_LOCAL_BRANCH;
1362 bool has_delay_slot(union code op)
1368 case OP_SPECIAL_JALR:
1386 bool should_emulate(const struct opcode *list)
1388 return op_flag_emulate_branch(list->flags) && has_delay_slot(list->c);
1391 static bool op_writes_rd(union code c)
1402 static void lightrec_add_reg_op(struct opcode *op, u8 reg, u32 reg_op)
1404 if (op_writes_rd(op->c) && reg == op->r.rd)
1405 op->flags |= LIGHTREC_REG_RD(reg_op);
1406 else if (op->i.rs == reg)
1407 op->flags |= LIGHTREC_REG_RS(reg_op);
1408 else if (op->i.rt == reg)
1409 op->flags |= LIGHTREC_REG_RT(reg_op);
1411 pr_debug("Cannot add unload/clean/discard flag: "
1412 "opcode does not touch register %s!\n",
1413 lightrec_reg_name(reg));
1416 static void lightrec_add_unload(struct opcode *op, u8 reg)
1418 lightrec_add_reg_op(op, reg, LIGHTREC_REG_UNLOAD);
1421 static void lightrec_add_discard(struct opcode *op, u8 reg)
1423 lightrec_add_reg_op(op, reg, LIGHTREC_REG_DISCARD);
1426 static void lightrec_add_clean(struct opcode *op, u8 reg)
1428 lightrec_add_reg_op(op, reg, LIGHTREC_REG_CLEAN);
1432 lightrec_early_unload_sync(struct opcode *list, s16 *last_r, s16 *last_w)
1437 for (reg = 0; reg < 34; reg++) {
1438 offset = s16_max(last_w[reg], last_r[reg]);
1441 lightrec_add_unload(&list[offset], reg);
1444 memset(last_r, 0xff, sizeof(*last_r) * 34);
1445 memset(last_w, 0xff, sizeof(*last_w) * 34);
1448 static int lightrec_early_unload(struct lightrec_state *state, struct block *block)
1452 s16 last_r[34], last_w[34], last_sync = 0, next_sync = 0;
1453 u64 mask_r, mask_w, dirty = 0, loaded = 0;
1456 memset(last_r, 0xff, sizeof(last_r));
1457 memset(last_w, 0xff, sizeof(last_w));
1461 * - the register is dirty, and is read again after a branch opcode
1464 * - the register is dirty or loaded, and is not read again
1465 * - the register is dirty or loaded, and is written again after a branch opcode
1466 * - the next opcode has the SYNC flag set
1469 * - the register is dirty or loaded, and is written again
1472 for (i = 0; i < block->nb_ops; i++) {
1473 op = &block->opcode_list[i];
1475 if (op_flag_sync(op->flags) || should_emulate(op)) {
1476 /* The next opcode has the SYNC flag set, or is a branch
1477 * that should be emulated: unload all registers. */
1478 lightrec_early_unload_sync(block->opcode_list, last_r, last_w);
1483 if (next_sync == i) {
1485 pr_debug("Last sync: 0x%x\n", last_sync << 2);
1488 if (has_delay_slot(op->c)) {
1489 next_sync = i + 1 + !op_flag_no_ds(op->flags);
1490 pr_debug("Next sync: 0x%x\n", next_sync << 2);
1493 mask_r = opcode_read_mask(op->c);
1494 mask_w = opcode_write_mask(op->c);
1496 for (reg = 0; reg < 34; reg++) {
1497 if (mask_r & BIT(reg)) {
1498 if (dirty & BIT(reg) && last_w[reg] < last_sync) {
1499 /* The register is dirty, and is read
1500 * again after a branch: clean it */
1502 lightrec_add_clean(&block->opcode_list[last_w[reg]], reg);
1510 if (mask_w & BIT(reg)) {
1511 if ((dirty & BIT(reg) && last_w[reg] < last_sync) ||
1512 (loaded & BIT(reg) && last_r[reg] < last_sync)) {
1513 /* The register is dirty or loaded, and
1514 * is written again after a branch:
1517 offset = s16_max(last_w[reg], last_r[reg]);
1518 lightrec_add_unload(&block->opcode_list[offset], reg);
1520 loaded &= ~BIT(reg);
1521 } else if (!(mask_r & BIT(reg)) &&
1522 ((dirty & BIT(reg) && last_w[reg] > last_sync) ||
1523 (loaded & BIT(reg) && last_r[reg] > last_sync))) {
1524 /* The register is dirty or loaded, and
1525 * is written again: discard it */
1527 offset = s16_max(last_w[reg], last_r[reg]);
1528 lightrec_add_discard(&block->opcode_list[offset], reg);
1530 loaded &= ~BIT(reg);
1542 /* Unload all registers that are dirty or loaded at the end of block. */
1543 lightrec_early_unload_sync(block->opcode_list, last_r, last_w);
1548 static int lightrec_flag_io(struct lightrec_state *state, struct block *block)
1550 struct opcode *prev = NULL, *list = NULL;
1551 enum psx_map psx_map;
1553 u32 values[32] = { 0 };
1555 u32 val, kunseg_val;
1558 for (i = 0; i < block->nb_ops; i++) {
1560 list = &block->opcode_list[i];
1563 known = lightrec_propagate_consts(list, prev, known, values);
1565 switch (list->i.op) {
1569 if (OPT_FLAG_STORES) {
1570 /* Mark all store operations that target $sp or $gp
1571 * as not requiring code invalidation. This is based
1572 * on the heuristic that stores using one of these
1573 * registers as address will never hit a code page. */
1574 if (list->i.rs >= 28 && list->i.rs <= 29 &&
1575 !state->maps[PSX_MAP_KERNEL_USER_RAM].ops) {
1576 pr_debug("Flaging opcode 0x%08x as not "
1577 "requiring invalidation\n",
1579 list->flags |= LIGHTREC_NO_INVALIDATE;
1580 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_DIRECT);
1583 /* Detect writes whose destination address is inside the
1584 * current block, using constant propagation. When these
1585 * occur, we mark the blocks as not compilable. */
1586 if ((known & BIT(list->i.rs)) &&
1587 kunseg(values[list->i.rs]) >= kunseg(block->pc) &&
1588 kunseg(values[list->i.rs]) < (kunseg(block->pc) +
1589 block->nb_ops * 4)) {
1590 pr_debug("Self-modifying block detected\n");
1591 block_set_flags(block, BLOCK_NEVER_COMPILE);
1592 list->flags |= LIGHTREC_SMC;
1607 if (OPT_FLAG_IO && (known & BIT(list->i.rs))) {
1608 val = values[list->i.rs] + (s16) list->i.imm;
1609 kunseg_val = kunseg(val);
1610 psx_map = lightrec_get_map_idx(state, kunseg_val);
1612 list->flags &= ~LIGHTREC_IO_MASK;
1613 no_mask = val == kunseg_val;
1616 case PSX_MAP_KERNEL_USER_RAM:
1618 list->flags |= LIGHTREC_NO_MASK;
1620 case PSX_MAP_MIRROR1:
1621 case PSX_MAP_MIRROR2:
1622 case PSX_MAP_MIRROR3:
1623 pr_debug("Flaging opcode %u as RAM access\n", i);
1624 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_RAM);
1625 if (no_mask && state->mirrors_mapped)
1626 list->flags |= LIGHTREC_NO_MASK;
1629 pr_debug("Flaging opcode %u as BIOS access\n", i);
1630 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_BIOS);
1632 list->flags |= LIGHTREC_NO_MASK;
1634 case PSX_MAP_SCRATCH_PAD:
1635 pr_debug("Flaging opcode %u as scratchpad access\n", i);
1636 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_SCRATCH);
1638 list->flags |= LIGHTREC_NO_MASK;
1640 /* Consider that we're never going to run code from
1641 * the scratchpad. */
1642 list->flags |= LIGHTREC_NO_INVALIDATE;
1644 case PSX_MAP_HW_REGISTERS:
1645 if (state->ops.hw_direct &&
1646 state->ops.hw_direct(kunseg_val,
1647 opcode_is_store(list->c),
1648 opcode_get_io_size(list->c))) {
1649 pr_debug("Flagging opcode %u as direct I/O access\n",
1651 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_DIRECT_HW);
1654 list->flags |= LIGHTREC_NO_MASK;
1659 pr_debug("Flagging opcode %u as I/O access\n",
1661 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_HW);
1674 static u8 get_mfhi_mflo_reg(const struct block *block, u16 offset,
1675 const struct opcode *last,
1676 u32 mask, bool sync, bool mflo, bool another)
1678 const struct opcode *op, *next = &block->opcode_list[offset];
1680 u8 reg2, reg = mflo ? REG_LO : REG_HI;
1684 for (i = offset; i < block->nb_ops; i++) {
1686 next = &block->opcode_list[i + 1];
1689 /* If any other opcode writes or reads to the register
1690 * we'd use, then we cannot use it anymore. */
1691 mask |= opcode_read_mask(op->c);
1692 mask |= opcode_write_mask(op->c);
1694 if (op_flag_sync(op->flags))
1703 /* TODO: handle backwards branches too */
1704 if (!last && op_flag_local_branch(op->flags) &&
1705 (s16)op->c.i.imm >= 0) {
1706 branch_offset = i + 1 + (s16)op->c.i.imm
1707 - !!op_flag_no_ds(op->flags);
1709 reg = get_mfhi_mflo_reg(block, branch_offset, NULL,
1710 mask, sync, mflo, false);
1711 reg2 = get_mfhi_mflo_reg(block, offset + 1, next,
1712 mask, sync, mflo, false);
1713 if (reg > 0 && reg == reg2)
1719 return mflo ? REG_LO : REG_HI;
1721 case OP_META_MULTU2:
1725 case OP_SPECIAL_MULT:
1726 case OP_SPECIAL_MULTU:
1727 case OP_SPECIAL_DIV:
1728 case OP_SPECIAL_DIVU:
1730 case OP_SPECIAL_MTHI:
1734 case OP_SPECIAL_MTLO:
1742 if (!sync && !op_flag_no_ds(op->flags) &&
1743 (next->i.op == OP_SPECIAL) &&
1744 ((!mflo && next->r.op == OP_SPECIAL_MFHI) ||
1745 (mflo && next->r.op == OP_SPECIAL_MFLO)))
1749 case OP_SPECIAL_JALR:
1751 case OP_SPECIAL_MFHI:
1755 /* Must use REG_HI if there is another MFHI target*/
1756 reg2 = get_mfhi_mflo_reg(block, i + 1, next,
1757 0, sync, mflo, true);
1758 if (reg2 > 0 && reg2 != REG_HI)
1761 if (!sync && !(old_mask & BIT(op->r.rd)))
1767 case OP_SPECIAL_MFLO:
1771 /* Must use REG_LO if there is another MFLO target*/
1772 reg2 = get_mfhi_mflo_reg(block, i + 1, next,
1773 0, sync, mflo, true);
1774 if (reg2 > 0 && reg2 != REG_LO)
1777 if (!sync && !(old_mask & BIT(op->r.rd)))
1796 static void lightrec_replace_lo_hi(struct block *block, u16 offset,
1802 /* This function will remove the following MFLO/MFHI. It must be called
1803 * only if get_mfhi_mflo_reg() returned a non-zero value. */
1805 for (i = offset; i < last; i++) {
1806 struct opcode *op = &block->opcode_list[i];
1814 /* TODO: handle backwards branches too */
1815 if (op_flag_local_branch(op->flags) && (s16)op->c.i.imm >= 0) {
1816 branch_offset = i + 1 + (s16)op->c.i.imm
1817 - !!op_flag_no_ds(op->flags);
1819 lightrec_replace_lo_hi(block, branch_offset, last, lo);
1820 lightrec_replace_lo_hi(block, i + 1, branch_offset, lo);
1825 if (lo && op->r.op == OP_SPECIAL_MFLO) {
1826 pr_debug("Removing MFLO opcode at offset 0x%x\n",
1830 } else if (!lo && op->r.op == OP_SPECIAL_MFHI) {
1831 pr_debug("Removing MFHI opcode at offset 0x%x\n",
1844 static bool lightrec_always_skip_div_check(void)
1853 static int lightrec_flag_mults_divs(struct lightrec_state *state, struct block *block)
1855 struct opcode *prev, *list = NULL;
1859 u32 values[32] = { 0 };
1861 for (i = 0; i < block->nb_ops - 1; i++) {
1863 list = &block->opcode_list[i];
1866 known = lightrec_propagate_consts(list, prev, known, values);
1868 switch (list->i.op) {
1870 switch (list->r.op) {
1871 case OP_SPECIAL_DIV:
1872 case OP_SPECIAL_DIVU:
1873 /* If we are dividing by a non-zero constant, don't
1874 * emit the div-by-zero check. */
1875 if (lightrec_always_skip_div_check() ||
1876 ((known & BIT(list->c.r.rt)) && values[list->c.r.rt]))
1877 list->flags |= LIGHTREC_NO_DIV_CHECK;
1879 case OP_SPECIAL_MULT:
1880 case OP_SPECIAL_MULTU:
1887 case OP_META_MULTU2:
1893 /* Don't support opcodes in delay slots */
1894 if ((i && has_delay_slot(block->opcode_list[i - 1].c)) ||
1895 op_flag_no_ds(list->flags)) {
1899 reg_lo = get_mfhi_mflo_reg(block, i + 1, NULL, 0, false, true, false);
1901 pr_debug("Mark MULT(U)/DIV(U) opcode at offset 0x%x as"
1902 " not writing LO\n", i << 2);
1903 list->flags |= LIGHTREC_NO_LO;
1906 reg_hi = get_mfhi_mflo_reg(block, i + 1, NULL, 0, false, false, false);
1908 pr_debug("Mark MULT(U)/DIV(U) opcode at offset 0x%x as"
1909 " not writing HI\n", i << 2);
1910 list->flags |= LIGHTREC_NO_HI;
1913 if (!reg_lo && !reg_hi) {
1914 pr_debug("Both LO/HI unused in this block, they will "
1915 "probably be used in parent block - removing "
1917 list->flags &= ~(LIGHTREC_NO_LO | LIGHTREC_NO_HI);
1920 if (reg_lo > 0 && reg_lo != REG_LO) {
1921 pr_debug("Found register %s to hold LO (rs = %u, rt = %u)\n",
1922 lightrec_reg_name(reg_lo), list->r.rs, list->r.rt);
1924 lightrec_replace_lo_hi(block, i + 1, block->nb_ops, true);
1925 list->r.rd = reg_lo;
1930 if (reg_hi > 0 && reg_hi != REG_HI) {
1931 pr_debug("Found register %s to hold HI (rs = %u, rt = %u)\n",
1932 lightrec_reg_name(reg_hi), list->r.rs, list->r.rt);
1934 lightrec_replace_lo_hi(block, i + 1, block->nb_ops, false);
1935 list->r.imm = reg_hi;
1944 static bool remove_div_sequence(struct block *block, unsigned int offset)
1947 unsigned int i, found = 0;
1950 * Scan for the zero-checking sequence that GCC automatically introduced
1951 * after most DIV/DIVU opcodes. This sequence checks the value of the
1952 * divisor, and if zero, executes a BREAK opcode, causing the BIOS
1953 * handler to crash the PS1.
1955 * For DIV opcodes, this sequence additionally checks that the signed
1956 * operation does not overflow.
1958 * With the assumption that the games never crashed the PS1, we can
1959 * therefore assume that the games never divided by zero or overflowed,
1960 * and these sequences can be removed.
1963 for (i = offset; i < block->nb_ops; i++) {
1964 op = &block->opcode_list[i];
1967 if (op->i.op == OP_SPECIAL &&
1968 (op->r.op == OP_SPECIAL_DIV || op->r.op == OP_SPECIAL_DIVU))
1971 if ((op->opcode & 0xfc1fffff) == 0x14000002) {
1972 /* BNE ???, zero, +8 */
1977 } else if (found == 1 && !op->opcode) {
1980 } else if (found == 2 && op->opcode == 0x0007000d) {
1983 } else if (found == 3 && op->opcode == 0x2401ffff) {
1986 } else if (found == 4 && (op->opcode & 0xfc1fffff) == 0x14010004) {
1987 /* BNE ???, at, +16 */
1989 } else if (found == 5 && op->opcode == 0x3c018000) {
1990 /* LUI at, 0x8000 */
1992 } else if (found == 6 && (op->opcode & 0x141fffff) == 0x14010002) {
1993 /* BNE ???, at, +16 */
1995 } else if (found == 7 && !op->opcode) {
1998 } else if (found == 8 && op->opcode == 0x0006000d) {
2011 pr_debug("Removing DIV%s sequence at offset 0x%x\n",
2012 found == 9 ? "" : "U", offset << 2);
2014 for (i = 0; i < found; i++)
2015 block->opcode_list[offset + i].opcode = 0;
2023 static int lightrec_remove_div_by_zero_check_sequence(struct lightrec_state *state,
2024 struct block *block)
2029 for (i = 0; i < block->nb_ops; i++) {
2030 op = &block->opcode_list[i];
2032 if (op->i.op == OP_SPECIAL &&
2033 (op->r.op == OP_SPECIAL_DIVU || op->r.op == OP_SPECIAL_DIV) &&
2034 remove_div_sequence(block, i + 1))
2035 op->flags |= LIGHTREC_NO_DIV_CHECK;
2041 static const u32 memset_code[] = {
2042 0x10a00006, // beqz a1, 2f
2043 0x24a2ffff, // addiu v0,a1,-1
2044 0x2403ffff, // li v1,-1
2045 0xac800000, // 1: sw zero,0(a0)
2046 0x2442ffff, // addiu v0,v0,-1
2047 0x1443fffd, // bne v0,v1, 1b
2048 0x24840004, // addiu a0,a0,4
2049 0x03e00008, // 2: jr ra
2053 static int lightrec_replace_memset(struct lightrec_state *state, struct block *block)
2058 for (i = 0; i < block->nb_ops; i++) {
2059 c = block->opcode_list[i].c;
2061 if (c.opcode != memset_code[i])
2064 if (i == ARRAY_SIZE(memset_code) - 1) {
2066 pr_debug("Block at PC 0x%x is a memset\n", block->pc);
2067 block_set_flags(block,
2068 BLOCK_IS_MEMSET | BLOCK_NEVER_COMPILE);
2070 /* Return non-zero to skip other optimizers. */
2078 static int (*lightrec_optimizers[])(struct lightrec_state *state, struct block *) = {
2079 IF_OPT(OPT_REMOVE_DIV_BY_ZERO_SEQ, &lightrec_remove_div_by_zero_check_sequence),
2080 IF_OPT(OPT_REPLACE_MEMSET, &lightrec_replace_memset),
2081 IF_OPT(OPT_DETECT_IMPOSSIBLE_BRANCHES, &lightrec_detect_impossible_branches),
2082 IF_OPT(OPT_TRANSFORM_OPS, &lightrec_transform_branches),
2083 IF_OPT(OPT_LOCAL_BRANCHES, &lightrec_local_branches),
2084 IF_OPT(OPT_TRANSFORM_OPS, &lightrec_transform_ops),
2085 IF_OPT(OPT_SWITCH_DELAY_SLOTS, &lightrec_switch_delay_slots),
2086 IF_OPT(OPT_FLAG_IO || OPT_FLAG_STORES, &lightrec_flag_io),
2087 IF_OPT(OPT_FLAG_MULT_DIV, &lightrec_flag_mults_divs),
2088 IF_OPT(OPT_EARLY_UNLOAD, &lightrec_early_unload),
2091 int lightrec_optimize(struct lightrec_state *state, struct block *block)
2096 for (i = 0; i < ARRAY_SIZE(lightrec_optimizers); i++) {
2097 if (lightrec_optimizers[i]) {
2098 ret = (*lightrec_optimizers[i])(state, block);