1 // SPDX-License-Identifier: LGPL-2.1-or-later
3 * Copyright (C) 2014-2021 Paul Cercueil <paul@crapouillou.net>
7 #include "lightrec-config.h"
8 #include "disassembler.h"
10 #include "memmanager.h"
11 #include "optimizer.h"
19 #define IF_OPT(opt, ptr) ((opt) ? (ptr) : NULL)
21 struct optimizer_list {
22 void (**optimizers)(struct opcode *);
23 unsigned int nb_optimizers;
26 static bool is_nop(union code op);
28 bool is_unconditional_jump(union code c)
32 return c.r.op == OP_SPECIAL_JR || c.r.op == OP_SPECIAL_JALR;
38 return c.i.rs == c.i.rt;
40 return (c.r.rt == OP_REGIMM_BGEZ ||
41 c.r.rt == OP_REGIMM_BGEZAL) && c.i.rs == 0;
47 bool is_syscall(union code c)
49 return (c.i.op == OP_SPECIAL && c.r.op == OP_SPECIAL_SYSCALL) ||
50 (c.i.op == OP_CP0 && (c.r.rs == OP_CP0_MTC0 ||
51 c.r.rs == OP_CP0_CTC0) &&
52 (c.r.rd == 12 || c.r.rd == 13));
55 static u64 opcode_read_mask(union code op)
60 case OP_SPECIAL_SYSCALL:
61 case OP_SPECIAL_BREAK:
80 return BIT(op.r.rs) | BIT(op.r.rt);
91 if (op.r.op == OP_CP2_BASIC) {
93 case OP_CP2_BASIC_MTC2:
94 case OP_CP2_BASIC_CTC2:
106 if (op.i.rs == op.i.rt)
117 return BIT(op.i.rs) | BIT(op.i.rt);
125 static u64 mult_div_write_mask(union code op)
129 if (!OPT_FLAG_MULT_DIV)
130 return BIT(REG_LO) | BIT(REG_HI);
133 flags = BIT(op.r.rd);
137 flags |= BIT(op.r.imm);
139 flags |= BIT(REG_HI);
144 u64 opcode_write_mask(union code op)
149 return mult_div_write_mask(op);
155 case OP_SPECIAL_SYSCALL:
156 case OP_SPECIAL_BREAK:
158 case OP_SPECIAL_MULT:
159 case OP_SPECIAL_MULTU:
161 case OP_SPECIAL_DIVU:
162 return mult_div_write_mask(op);
163 case OP_SPECIAL_MTHI:
165 case OP_SPECIAL_MTLO:
201 if (op.r.op == OP_CP2_BASIC) {
203 case OP_CP2_BASIC_MFC2:
204 case OP_CP2_BASIC_CFC2:
213 case OP_REGIMM_BLTZAL:
214 case OP_REGIMM_BGEZAL:
224 bool opcode_reads_register(union code op, u8 reg)
226 return opcode_read_mask(op) & BIT(reg);
229 bool opcode_writes_register(union code op, u8 reg)
231 return opcode_write_mask(op) & BIT(reg);
234 static int find_prev_writer(const struct opcode *list, unsigned int offset, u8 reg)
239 if (op_flag_sync(list[offset].flags))
242 for (i = offset; i > 0; i--) {
245 if (opcode_writes_register(c, reg)) {
246 if (i > 1 && has_delay_slot(list[i - 2].c))
252 if (op_flag_sync(list[i - 1].flags) ||
254 opcode_reads_register(c, reg))
261 static int find_next_reader(const struct opcode *list, unsigned int offset, u8 reg)
266 if (op_flag_sync(list[offset].flags))
269 for (i = offset; ; i++) {
272 if (opcode_reads_register(c, reg))
275 if (op_flag_sync(list[i].flags)
276 || (op_flag_no_ds(list[i].flags) && has_delay_slot(c))
277 || is_delay_slot(list, i)
278 || opcode_writes_register(c, reg))
285 static bool reg_is_dead(const struct opcode *list, unsigned int offset, u8 reg)
289 if (op_flag_sync(list[offset].flags) || is_delay_slot(list, offset))
292 for (i = offset + 1; ; i++) {
293 if (opcode_reads_register(list[i].c, reg))
296 if (opcode_writes_register(list[i].c, reg))
299 if (has_delay_slot(list[i].c)) {
300 if (op_flag_no_ds(list[i].flags) ||
301 opcode_reads_register(list[i + 1].c, reg))
304 return opcode_writes_register(list[i + 1].c, reg);
309 static bool reg_is_read(const struct opcode *list,
310 unsigned int a, unsigned int b, u8 reg)
312 /* Return true if reg is read in one of the opcodes of the interval
315 if (!is_nop(list[a].c) && opcode_reads_register(list[a].c, reg))
322 static bool reg_is_written(const struct opcode *list,
323 unsigned int a, unsigned int b, u8 reg)
325 /* Return true if reg is written in one of the opcodes of the interval
329 if (!is_nop(list[a].c) && opcode_writes_register(list[a].c, reg))
336 static bool reg_is_read_or_written(const struct opcode *list,
337 unsigned int a, unsigned int b, u8 reg)
339 return reg_is_read(list, a, b, reg) || reg_is_written(list, a, b, reg);
342 bool opcode_is_mfc(union code op)
356 if (op.r.op == OP_CP2_BASIC) {
358 case OP_CP2_BASIC_MFC2:
359 case OP_CP2_BASIC_CFC2:
374 bool opcode_is_load(union code op)
391 static bool opcode_is_store(union code op)
406 static u8 opcode_get_io_size(union code op)
422 bool opcode_is_io(union code op)
424 return opcode_is_load(op) || opcode_is_store(op);
428 static bool is_nop(union code op)
430 if (opcode_writes_register(op, 0)) {
433 return op.r.rs != OP_CP0_MFC0;
451 return op.r.rd == op.r.rt && op.r.rd == op.r.rs;
453 case OP_SPECIAL_ADDU:
454 return (op.r.rd == op.r.rt && op.r.rs == 0) ||
455 (op.r.rd == op.r.rs && op.r.rt == 0);
457 case OP_SPECIAL_SUBU:
458 return op.r.rd == op.r.rs && op.r.rt == 0;
460 if (op.r.rd == op.r.rt)
461 return op.r.rd == op.r.rs || op.r.rs == 0;
463 return (op.r.rd == op.r.rs) && op.r.rt == 0;
467 return op.r.rd == op.r.rt && op.r.imm == 0;
468 case OP_SPECIAL_MFHI:
469 case OP_SPECIAL_MFLO:
477 return op.i.rt == op.i.rs && op.i.imm == 0;
479 return (op.i.rs == 0 || op.i.imm == 1);
481 return (op.i.op == OP_REGIMM_BLTZ ||
482 op.i.op == OP_REGIMM_BLTZAL) &&
483 (op.i.rs == 0 || op.i.imm == 1);
485 return (op.i.rs == op.i.rt || op.i.imm == 1);
491 static void lightrec_optimize_sll_sra(struct opcode *list, unsigned int offset,
492 struct constprop_data *v)
494 struct opcode *ldop = NULL, *curr = &list[offset], *next;
495 struct opcode *to_change, *to_nop;
498 if (curr->r.imm != 24 && curr->r.imm != 16)
501 if (is_delay_slot(list, offset))
504 idx = find_next_reader(list, offset + 1, curr->r.rd);
510 if (next->i.op != OP_SPECIAL || next->r.op != OP_SPECIAL_SRA ||
511 next->r.imm != curr->r.imm || next->r.rt != curr->r.rd)
514 if (curr->r.rd != curr->r.rt && next->r.rd != next->r.rt) {
519 if (!reg_is_dead(list, idx, curr->r.rd) ||
520 reg_is_read_or_written(list, offset, idx, next->r.rd))
523 /* If rY is dead after the SRL, and rZ is not used after the SLL,
524 * we can change rY to rZ */
526 pr_debug("Detected SLL/SRA with middle temp register\n");
527 curr->r.rd = next->r.rd;
528 next->r.rt = curr->r.rd;
531 /* We got a SLL/SRA combo. If imm #16, that's a cast to s16.
532 * If imm #24 that's a cast to s8.
534 * First of all, make sure that the target register of the SLL is not
535 * read after the SRA. */
537 if (curr->r.rd == curr->r.rt) {
544 /* rX is used after the SRA - we cannot convert it. */
545 if (curr->r.rd != next->r.rd && !reg_is_dead(list, idx, curr->r.rd))
555 idx2 = find_prev_writer(list, offset, curr->r.rt);
557 /* Note that PSX games sometimes do casts after
558 * a LHU or LBU; in this case we can change the
559 * load opcode to a LH or LB, and the cast can
560 * be changed to a MOV or a simple NOP. */
564 if (next->r.rd != ldop->i.rt &&
565 !reg_is_dead(list, idx, ldop->i.rt))
567 else if (curr->r.imm == 16 && ldop->i.op == OP_LHU)
569 else if (curr->r.imm == 24 && ldop->i.op == OP_LBU)
575 if (next->r.rd == ldop->i.rt) {
576 to_change->opcode = 0;
577 } else if (reg_is_dead(list, idx, ldop->i.rt) &&
578 !reg_is_read_or_written(list, idx2 + 1, idx, next->r.rd)) {
579 /* The target register of the SRA is dead after the
580 * LBU/LHU; we can change the target register of the
581 * LBU/LHU to the one of the SRA. */
582 v[ldop->i.rt].known = 0;
583 v[ldop->i.rt].sign = 0;
584 ldop->i.rt = next->r.rd;
585 to_change->opcode = 0;
587 to_change->i.op = OP_META;
588 to_change->m.op = OP_META_MOV;
589 to_change->m.rd = next->r.rd;
590 to_change->m.rs = ldop->i.rt;
593 if (to_nop->r.imm == 24)
594 pr_debug("Convert LBU+SLL+SRA to LB\n");
596 pr_debug("Convert LHU+SLL+SRA to LH\n");
598 v[ldop->i.rt].known = 0;
599 v[ldop->i.rt].sign = 0xffffff80 << (24 - curr->r.imm);
604 pr_debug("Convert SLL/SRA #%u to EXT%c\n",
605 curr->r.imm, curr->r.imm == 24 ? 'C' : 'S');
607 to_change->m.rs = curr->r.rt;
608 to_change->m.op = to_nop->r.imm == 24 ? OP_META_EXTC : OP_META_EXTS;
609 to_change->i.op = OP_META;
616 lightrec_remove_useless_lui(struct block *block, unsigned int offset,
617 const struct constprop_data *v)
619 struct opcode *list = block->opcode_list,
620 *op = &block->opcode_list[offset];
623 if (!op_flag_sync(op->flags) && is_known(v, op->i.rt) &&
624 v[op->i.rt].value == op->i.imm << 16) {
625 pr_debug("Converting duplicated LUI to NOP\n");
630 if (op->i.imm != 0 || op->i.rt == 0 || offset == block->nb_ops - 1)
633 reader = find_next_reader(list, offset + 1, op->i.rt);
637 if (opcode_writes_register(list[reader].c, op->i.rt) ||
638 reg_is_dead(list, reader, op->i.rt)) {
639 pr_debug("Removing useless LUI 0x0\n");
641 if (list[reader].i.rs == op->i.rt)
642 list[reader].i.rs = 0;
643 if (list[reader].i.op == OP_SPECIAL &&
644 list[reader].i.rt == op->i.rt)
645 list[reader].i.rt = 0;
650 static void lightrec_lui_to_movi(struct block *block, unsigned int offset)
652 struct opcode *ori, *lui = &block->opcode_list[offset];
655 if (lui->i.op != OP_LUI)
658 next = find_next_reader(block->opcode_list, offset + 1, lui->i.rt);
660 ori = &block->opcode_list[next];
666 if (ori->i.rs == ori->i.rt && ori->i.imm) {
667 ori->flags |= LIGHTREC_MOVI;
668 lui->flags |= LIGHTREC_MOVI;
675 static void lightrec_modify_lui(struct block *block, unsigned int offset)
677 union code c, *lui = &block->opcode_list[offset].c;
678 bool stop = false, stop_next = false;
681 for (i = offset + 1; !stop && i < block->nb_ops; i++) {
682 c = block->opcode_list[i].c;
685 if ((opcode_is_store(c) && c.i.rt == lui->i.rt)
686 || (!opcode_is_load(c) && opcode_reads_register(c, lui->i.rt)))
689 if (opcode_writes_register(c, lui->i.rt)) {
690 if (c.i.op == OP_LWL || c.i.op == OP_LWR) {
691 /* LWL/LWR only partially write their target register;
692 * therefore the LUI should not write a different value. */
696 pr_debug("Convert LUI at offset 0x%x to kuseg\n",
698 lui->i.imm = kunseg(lui->i.imm << 16) >> 16;
702 if (has_delay_slot(c))
707 static int lightrec_transform_branches(struct lightrec_state *state,
714 for (i = 0; i < block->nb_ops; i++) {
715 op = &block->opcode_list[i];
719 /* Transform J opcode into BEQ $zero, $zero if possible. */
720 offset = (s32)((block->pc & 0xf0000000) >> 2 | op->j.imm)
721 - (s32)(block->pc >> 2) - (s32)i - 1;
723 if (offset == (s16)offset) {
724 pr_debug("Transform J into BEQ $zero, $zero\n");
740 static inline bool is_power_of_two(u32 value)
742 return popcount32(value) == 1;
745 static void lightrec_patch_known_zero(struct opcode *op,
746 const struct constprop_data *v)
752 case OP_SPECIAL_JALR:
753 case OP_SPECIAL_MTHI:
754 case OP_SPECIAL_MTLO:
755 if (is_known_zero(v, op->r.rs))
759 if (is_known_zero(v, op->r.rs))
765 if (is_known_zero(v, op->r.rt))
768 case OP_SPECIAL_SYSCALL:
769 case OP_SPECIAL_BREAK:
770 case OP_SPECIAL_MFHI:
771 case OP_SPECIAL_MFLO:
779 if (is_known_zero(v, op->r.rt))
787 if (op->r.op == OP_CP2_BASIC) {
789 case OP_CP2_BASIC_MTC2:
790 case OP_CP2_BASIC_CTC2:
791 if (is_known_zero(v, op->r.rt))
801 if (is_known_zero(v, op->i.rt))
817 if (is_known_zero(v, op->m.rs))
825 if (is_known_zero(v, op->i.rt))
837 if (is_known(v, op->i.rs)
838 && kunseg(v[op->i.rs].value) == 0)
846 static void lightrec_reset_syncs(struct block *block)
848 struct opcode *op, *list = block->opcode_list;
852 for (i = 0; i < block->nb_ops; i++)
853 list[i].flags &= ~LIGHTREC_SYNC;
855 for (i = 0; i < block->nb_ops; i++) {
858 if (has_delay_slot(op->c)) {
859 if (op_flag_local_branch(op->flags)) {
860 offset = i + 1 - op_flag_no_ds(op->flags) + (s16)op->i.imm;
861 list[offset].flags |= LIGHTREC_SYNC;
864 if (op_flag_emulate_branch(op->flags) && i + 2 < block->nb_ops)
865 list[i + 2].flags |= LIGHTREC_SYNC;
870 static int lightrec_transform_ops(struct lightrec_state *state, struct block *block)
872 struct opcode *op, *list = block->opcode_list;
873 struct constprop_data v[32] = LIGHTREC_CONSTPROP_INITIALIZER;
878 for (i = 0; i < block->nb_ops; i++) {
881 lightrec_consts_propagate(block, i, v);
883 lightrec_patch_known_zero(op, v);
885 /* Transform all opcodes detected as useless to real NOPs
886 * (0x0: SLL r0, r0, #0) */
887 if (op->opcode != 0 && is_nop(op->c)) {
888 pr_debug("Converting useless opcode 0x%08x to NOP\n",
898 if (op->i.rs == op->i.rt ||
899 (is_known(v, op->i.rs) && is_known(v, op->i.rt) &&
900 v[op->i.rs].value == v[op->i.rt].value)) {
901 if (op->i.rs != op->i.rt)
902 pr_debug("Found always-taken BEQ\n");
906 } else if (v[op->i.rs].known & v[op->i.rt].known &
907 (v[op->i.rs].value ^ v[op->i.rt].value)) {
908 pr_debug("Found never-taken BEQ\n");
910 local = op_flag_local_branch(op->flags);
915 lightrec_reset_syncs(block);
916 } else if (op->i.rs == 0) {
923 if (v[op->i.rs].known & v[op->i.rt].known &
924 (v[op->i.rs].value ^ v[op->i.rt].value)) {
925 pr_debug("Found always-taken BNE\n");
930 } else if (is_known(v, op->i.rs) && is_known(v, op->i.rt) &&
931 v[op->i.rs].value == v[op->i.rt].value) {
932 pr_debug("Found never-taken BNE\n");
934 local = op_flag_local_branch(op->flags);
939 lightrec_reset_syncs(block);
940 } else if (op->i.rs == 0) {
947 if (v[op->i.rs].known & BIT(31) &&
948 v[op->i.rs].value & BIT(31)) {
949 pr_debug("Found always-taken BLEZ\n");
958 if (v[op->i.rs].known & BIT(31) &&
959 v[op->i.rs].value & BIT(31)) {
960 pr_debug("Found never-taken BGTZ\n");
962 local = op_flag_local_branch(op->flags);
967 lightrec_reset_syncs(block);
972 if (i == 0 || !has_delay_slot(list[i - 1].c))
973 lightrec_modify_lui(block, i);
974 lightrec_remove_useless_lui(block, i, v);
975 if (i == 0 || !has_delay_slot(list[i - 1].c))
976 lightrec_lui_to_movi(block, i);
979 /* Transform ORI/ADDI/ADDIU with imm #0 or ORR/ADD/ADDU/SUB/SUBU
980 * with register $zero to the MOV meta-opcode */
984 if (op->i.imm == 0) {
985 pr_debug("Convert ORI/ADDI/ADDIU #0 to MOV\n");
987 op->m.op = OP_META_MOV;
992 if (bits_are_known_zero(v, op->i.rs, ~op->i.imm)) {
993 pr_debug("Found useless ANDI 0x%x\n", op->i.imm);
995 if (op->i.rs == op->i.rt) {
999 op->m.op = OP_META_MOV;
1006 case OP_REGIMM_BLTZ:
1007 case OP_REGIMM_BGEZ:
1008 if (!(v[op->r.rs].known & BIT(31)))
1011 if (!!(v[op->r.rs].value & BIT(31))
1012 ^ (op->r.rt == OP_REGIMM_BGEZ)) {
1013 pr_debug("Found always-taken BLTZ/BGEZ\n");
1018 pr_debug("Found never-taken BLTZ/BGEZ\n");
1020 local = op_flag_local_branch(op->flags);
1025 lightrec_reset_syncs(block);
1028 case OP_REGIMM_BLTZAL:
1029 case OP_REGIMM_BGEZAL:
1030 /* TODO: Detect always-taken and replace with JAL */
1036 case OP_SPECIAL_SRAV:
1037 if ((v[op->r.rs].known & 0x1f) != 0x1f)
1040 pr_debug("Convert SRAV to SRA\n");
1041 op->r.imm = v[op->r.rs].value & 0x1f;
1042 op->r.op = OP_SPECIAL_SRA;
1045 case OP_SPECIAL_SRA:
1046 if (op->r.imm == 0) {
1047 pr_debug("Convert SRA #0 to MOV\n");
1048 op->m.rs = op->r.rt;
1049 op->m.op = OP_META_MOV;
1055 case OP_SPECIAL_SLLV:
1056 if ((v[op->r.rs].known & 0x1f) != 0x1f)
1059 pr_debug("Convert SLLV to SLL\n");
1060 op->r.imm = v[op->r.rs].value & 0x1f;
1061 op->r.op = OP_SPECIAL_SLL;
1064 case OP_SPECIAL_SLL:
1065 if (op->r.imm == 0) {
1066 pr_debug("Convert SLL #0 to MOV\n");
1067 op->m.rs = op->r.rt;
1068 op->m.op = OP_META_MOV;
1072 lightrec_optimize_sll_sra(block->opcode_list, i, v);
1075 case OP_SPECIAL_SRLV:
1076 if ((v[op->r.rs].known & 0x1f) != 0x1f)
1079 pr_debug("Convert SRLV to SRL\n");
1080 op->r.imm = v[op->r.rs].value & 0x1f;
1081 op->r.op = OP_SPECIAL_SRL;
1084 case OP_SPECIAL_SRL:
1085 if (op->r.imm == 0) {
1086 pr_debug("Convert SRL #0 to MOV\n");
1087 op->m.rs = op->r.rt;
1088 op->m.op = OP_META_MOV;
1093 case OP_SPECIAL_MULT:
1094 case OP_SPECIAL_MULTU:
1095 if (is_known(v, op->r.rs) &&
1096 is_power_of_two(v[op->r.rs].value)) {
1098 op->c.i.rs = op->c.i.rt;
1100 } else if (!is_known(v, op->r.rt) ||
1101 !is_power_of_two(v[op->r.rt].value)) {
1105 pr_debug("Multiply by power-of-two: %u\n",
1108 if (op->r.op == OP_SPECIAL_MULT)
1109 op->i.op = OP_META_MULT2;
1111 op->i.op = OP_META_MULTU2;
1113 op->r.op = ctz32(v[op->r.rt].value);
1115 case OP_SPECIAL_NOR:
1116 if (op->r.rs == 0 || op->r.rt == 0) {
1117 pr_debug("Convert NOR $zero to COM\n");
1119 op->m.op = OP_META_COM;
1121 op->m.rs = op->r.rt;
1125 case OP_SPECIAL_ADD:
1126 case OP_SPECIAL_ADDU:
1127 if (op->r.rs == 0) {
1128 pr_debug("Convert OR/ADD $zero to MOV\n");
1129 op->m.rs = op->r.rt;
1130 op->m.op = OP_META_MOV;
1134 case OP_SPECIAL_SUB:
1135 case OP_SPECIAL_SUBU:
1136 if (op->r.rt == 0) {
1137 pr_debug("Convert OR/ADD/SUB $zero to MOV\n");
1138 op->m.op = OP_META_MOV;
1154 static bool lightrec_can_switch_delay_slot(union code op, union code next_op)
1159 case OP_SPECIAL_JALR:
1160 if (opcode_reads_register(next_op, op.r.rd) ||
1161 opcode_writes_register(next_op, op.r.rd))
1165 if (opcode_writes_register(next_op, op.r.rs))
1175 if (opcode_reads_register(next_op, 31) ||
1176 opcode_writes_register(next_op, 31))
1182 if (op.i.rt && opcode_writes_register(next_op, op.i.rt))
1187 if (op.i.rs && opcode_writes_register(next_op, op.i.rs))
1192 case OP_REGIMM_BLTZAL:
1193 case OP_REGIMM_BGEZAL:
1194 if (opcode_reads_register(next_op, 31) ||
1195 opcode_writes_register(next_op, 31))
1198 case OP_REGIMM_BLTZ:
1199 case OP_REGIMM_BGEZ:
1200 if (op.i.rs && opcode_writes_register(next_op, op.i.rs))
1212 static int lightrec_switch_delay_slots(struct lightrec_state *state, struct block *block)
1214 struct opcode *list, *next = &block->opcode_list[0];
1216 union code op, next_op;
1219 for (i = 0; i < block->nb_ops - 1; i++) {
1221 next = &block->opcode_list[i + 1];
1225 if (!has_delay_slot(op) || op_flag_no_ds(list->flags) ||
1226 op_flag_emulate_branch(list->flags) ||
1227 op.opcode == 0 || next_op.opcode == 0)
1230 if (is_delay_slot(block->opcode_list, i))
1233 if (op_flag_sync(next->flags))
1236 if (op_flag_load_delay(next->flags) && opcode_is_load(next_op))
1239 if (!lightrec_can_switch_delay_slot(list->c, next_op))
1242 pr_debug("Swap branch and delay slot opcodes "
1243 "at offsets 0x%x / 0x%x\n",
1244 i << 2, (i + 1) << 2);
1246 flags = next->flags | (list->flags & LIGHTREC_SYNC);
1249 next->flags = (list->flags | LIGHTREC_NO_DS) & ~LIGHTREC_SYNC;
1250 list->flags = flags | LIGHTREC_NO_DS;
1256 static int lightrec_detect_impossible_branches(struct lightrec_state *state,
1257 struct block *block)
1259 struct opcode *op, *list = block->opcode_list, *next = &list[0];
1263 for (i = 0; i < block->nb_ops - 1; i++) {
1265 next = &list[i + 1];
1267 if (!has_delay_slot(op->c) ||
1268 (!has_delay_slot(next->c) &&
1269 !opcode_is_mfc(next->c) &&
1270 !(next->i.op == OP_CP0 && next->r.rs == OP_CP0_RFE)))
1273 if (op->c.opcode == next->c.opcode) {
1274 /* The delay slot is the exact same opcode as the branch
1275 * opcode: this is effectively a NOP */
1280 op->flags |= LIGHTREC_EMULATE_BRANCH;
1282 if (OPT_LOCAL_BRANCHES && i + 2 < block->nb_ops) {
1283 /* The interpreter will only emulate the branch, then
1284 * return to the compiled code. Add a SYNC after the
1285 * branch + delay slot in the case where the branch
1287 list[i + 2].flags |= LIGHTREC_SYNC;
1294 static bool is_local_branch(const struct block *block, unsigned int idx)
1296 const struct opcode *op = &block->opcode_list[idx];
1299 switch (op->c.i.op) {
1305 offset = idx + 1 + (s16)op->c.i.imm;
1306 if (offset >= 0 && offset < block->nb_ops)
1314 static int lightrec_handle_load_delays(struct lightrec_state *state,
1315 struct block *block)
1317 struct opcode *op, *list = block->opcode_list;
1321 for (i = 0; i < block->nb_ops; i++) {
1324 if (!opcode_is_load(op->c) || !op->c.i.rt || op->c.i.op == OP_LWC2)
1327 if (!is_delay_slot(list, i)) {
1328 /* Only handle load delays in delay slots.
1329 * PSX games never abused load delay slots otherwise. */
1333 if (is_local_branch(block, i - 1)) {
1334 imm = (s16)list[i - 1].c.i.imm;
1336 if (!opcode_reads_register(list[i + imm].c, op->c.i.rt)) {
1337 /* The target opcode of the branch is inside
1338 * the block, and it does not read the register
1339 * written to by the load opcode; we can ignore
1340 * the load delay. */
1345 op->flags |= LIGHTREC_LOAD_DELAY;
1351 static int lightrec_swap_load_delays(struct lightrec_state *state,
1352 struct block *block)
1356 bool in_ds = false, skip_next = false;
1359 if (block->nb_ops < 2)
1362 for (i = 0; i < block->nb_ops - 2; i++) {
1363 c = block->opcode_list[i].c;
1367 } else if (!in_ds && opcode_is_load(c) && c.i.op != OP_LWC2) {
1368 next = block->opcode_list[i + 1].c;
1370 switch (next.i.op) {
1381 if (opcode_reads_register(next, c.i.rt)
1382 && !opcode_writes_register(next, c.i.rs)) {
1383 pr_debug("Swapping opcodes at offset 0x%x to "
1384 "respect load delay\n", i << 2);
1386 op = block->opcode_list[i];
1387 block->opcode_list[i] = block->opcode_list[i + 1];
1388 block->opcode_list[i + 1] = op;
1393 in_ds = has_delay_slot(c);
1399 static int lightrec_local_branches(struct lightrec_state *state, struct block *block)
1401 const struct opcode *ds;
1402 struct opcode *list;
1406 for (i = 0; i < block->nb_ops; i++) {
1407 list = &block->opcode_list[i];
1409 if (should_emulate(list) || !is_local_branch(block, i))
1412 offset = i + 1 + (s16)list->c.i.imm;
1414 pr_debug("Found local branch to offset 0x%x\n", offset << 2);
1416 ds = get_delay_slot(block->opcode_list, i);
1417 if (op_flag_load_delay(ds->flags) && opcode_is_load(ds->c)) {
1418 pr_debug("Branch delay slot has a load delay - skip\n");
1422 if (should_emulate(&block->opcode_list[offset])) {
1423 pr_debug("Branch target must be emulated - skip\n");
1427 if (offset && has_delay_slot(block->opcode_list[offset - 1].c)) {
1428 pr_debug("Branch target is a delay slot - skip\n");
1432 list->flags |= LIGHTREC_LOCAL_BRANCH;
1435 lightrec_reset_syncs(block);
1440 bool has_delay_slot(union code op)
1446 case OP_SPECIAL_JALR:
1464 bool is_delay_slot(const struct opcode *list, unsigned int offset)
1467 && !op_flag_no_ds(list[offset - 1].flags)
1468 && has_delay_slot(list[offset - 1].c);
1471 bool should_emulate(const struct opcode *list)
1473 return op_flag_emulate_branch(list->flags) && has_delay_slot(list->c);
1476 static bool op_writes_rd(union code c)
1487 static void lightrec_add_reg_op(struct opcode *op, u8 reg, u32 reg_op)
1489 if (op_writes_rd(op->c) && reg == op->r.rd)
1490 op->flags |= LIGHTREC_REG_RD(reg_op);
1491 else if (op->i.rs == reg)
1492 op->flags |= LIGHTREC_REG_RS(reg_op);
1493 else if (op->i.rt == reg)
1494 op->flags |= LIGHTREC_REG_RT(reg_op);
1496 pr_debug("Cannot add unload/clean/discard flag: "
1497 "opcode does not touch register %s!\n",
1498 lightrec_reg_name(reg));
1501 static void lightrec_add_unload(struct opcode *op, u8 reg)
1503 lightrec_add_reg_op(op, reg, LIGHTREC_REG_UNLOAD);
1506 static void lightrec_add_discard(struct opcode *op, u8 reg)
1508 lightrec_add_reg_op(op, reg, LIGHTREC_REG_DISCARD);
1511 static void lightrec_add_clean(struct opcode *op, u8 reg)
1513 lightrec_add_reg_op(op, reg, LIGHTREC_REG_CLEAN);
1517 lightrec_early_unload_sync(struct opcode *list, s16 *last_r, s16 *last_w)
1522 for (reg = 0; reg < 34; reg++) {
1523 offset = s16_max(last_w[reg], last_r[reg]);
1526 lightrec_add_unload(&list[offset], reg);
1529 memset(last_r, 0xff, sizeof(*last_r) * 34);
1530 memset(last_w, 0xff, sizeof(*last_w) * 34);
1533 static int lightrec_early_unload(struct lightrec_state *state, struct block *block)
1537 s16 last_r[34], last_w[34], last_sync = 0, next_sync = 0;
1538 u64 mask_r, mask_w, dirty = 0, loaded = 0;
1539 u8 reg, load_delay_reg = 0;
1541 memset(last_r, 0xff, sizeof(last_r));
1542 memset(last_w, 0xff, sizeof(last_w));
1546 * - the register is dirty, and is read again after a branch opcode
1549 * - the register is dirty or loaded, and is not read again
1550 * - the register is dirty or loaded, and is written again after a branch opcode
1551 * - the next opcode has the SYNC flag set
1554 * - the register is dirty or loaded, and is written again
1557 for (i = 0; i < block->nb_ops; i++) {
1558 op = &block->opcode_list[i];
1560 if (OPT_HANDLE_LOAD_DELAYS && load_delay_reg) {
1561 /* Handle delayed register write from load opcodes in
1563 last_w[load_delay_reg] = i;
1567 if (op_flag_sync(op->flags) || should_emulate(op)) {
1568 /* The next opcode has the SYNC flag set, or is a branch
1569 * that should be emulated: unload all registers. */
1570 lightrec_early_unload_sync(block->opcode_list, last_r, last_w);
1575 if (next_sync == i) {
1577 pr_debug("Last sync: 0x%x\n", last_sync << 2);
1580 if (has_delay_slot(op->c)) {
1581 next_sync = i + 1 + !op_flag_no_ds(op->flags);
1582 pr_debug("Next sync: 0x%x\n", next_sync << 2);
1585 mask_r = opcode_read_mask(op->c);
1586 mask_w = opcode_write_mask(op->c);
1588 if (op_flag_load_delay(op->flags) && opcode_is_load(op->c)) {
1589 /* If we have a load opcode in a delay slot, its target
1590 * register is actually not written there but at a
1591 * later point, in the dispatcher. Prevent the algorithm
1592 * from discarding its previous value. */
1593 load_delay_reg = op->c.i.rt;
1594 mask_w &= ~BIT(op->c.i.rt);
1597 for (reg = 0; reg < 34; reg++) {
1598 if (mask_r & BIT(reg)) {
1599 if (dirty & BIT(reg) && last_w[reg] < last_sync) {
1600 /* The register is dirty, and is read
1601 * again after a branch: clean it */
1603 lightrec_add_clean(&block->opcode_list[last_w[reg]], reg);
1611 if (mask_w & BIT(reg)) {
1612 if ((dirty & BIT(reg) && last_w[reg] < last_sync) ||
1613 (loaded & BIT(reg) && last_r[reg] < last_sync)) {
1614 /* The register is dirty or loaded, and
1615 * is written again after a branch:
1618 offset = s16_max(last_w[reg], last_r[reg]);
1619 lightrec_add_unload(&block->opcode_list[offset], reg);
1621 loaded &= ~BIT(reg);
1622 } else if (!(mask_r & BIT(reg)) &&
1623 ((dirty & BIT(reg) && last_w[reg] > last_sync) ||
1624 (loaded & BIT(reg) && last_r[reg] > last_sync))) {
1625 /* The register is dirty or loaded, and
1626 * is written again: discard it */
1628 offset = s16_max(last_w[reg], last_r[reg]);
1629 lightrec_add_discard(&block->opcode_list[offset], reg);
1631 loaded &= ~BIT(reg);
1643 /* Unload all registers that are dirty or loaded at the end of block. */
1644 lightrec_early_unload_sync(block->opcode_list, last_r, last_w);
1649 static int lightrec_flag_io(struct lightrec_state *state, struct block *block)
1651 struct opcode *list;
1652 enum psx_map psx_map;
1653 struct constprop_data v[32] = LIGHTREC_CONSTPROP_INITIALIZER;
1655 u32 val, kunseg_val;
1658 for (i = 0; i < block->nb_ops; i++) {
1659 list = &block->opcode_list[i];
1661 lightrec_consts_propagate(block, i, v);
1663 switch (list->i.op) {
1667 /* Mark all store operations that target $sp or $gp
1668 * as not requiring code invalidation. This is based
1669 * on the heuristic that stores using one of these
1670 * registers as address will never hit a code page. */
1671 if (list->i.rs >= 28 && list->i.rs <= 29 &&
1672 !state->maps[PSX_MAP_KERNEL_USER_RAM].ops) {
1673 pr_debug("Flaging opcode 0x%08x as not requiring invalidation\n",
1675 list->flags |= LIGHTREC_NO_INVALIDATE;
1678 /* Detect writes whose destination address is inside the
1679 * current block, using constant propagation. When these
1680 * occur, we mark the blocks as not compilable. */
1681 if (is_known(v, list->i.rs) &&
1682 kunseg(v[list->i.rs].value) >= kunseg(block->pc) &&
1683 kunseg(v[list->i.rs].value) < (kunseg(block->pc) + block->nb_ops * 4)) {
1684 pr_debug("Self-modifying block detected\n");
1685 block_set_flags(block, BLOCK_NEVER_COMPILE);
1686 list->flags |= LIGHTREC_SMC;
1700 if (v[list->i.rs].known | v[list->i.rs].sign) {
1701 psx_map = lightrec_get_constprop_map(state, v,
1705 if (psx_map != PSX_MAP_UNKNOWN && !is_known(v, list->i.rs))
1706 pr_debug("Detected map thanks to bit-level const propagation!\n");
1708 list->flags &= ~LIGHTREC_IO_MASK;
1710 val = v[list->i.rs].value + (s16) list->i.imm;
1711 kunseg_val = kunseg(val);
1713 no_mask = (v[list->i.rs].known & ~v[list->i.rs].value
1714 & 0xe0000000) == 0xe0000000;
1717 case PSX_MAP_KERNEL_USER_RAM:
1719 list->flags |= LIGHTREC_NO_MASK;
1721 case PSX_MAP_MIRROR1:
1722 case PSX_MAP_MIRROR2:
1723 case PSX_MAP_MIRROR3:
1724 pr_debug("Flaging opcode %u as RAM access\n", i);
1725 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_RAM);
1726 if (no_mask && state->mirrors_mapped)
1727 list->flags |= LIGHTREC_NO_MASK;
1730 pr_debug("Flaging opcode %u as BIOS access\n", i);
1731 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_BIOS);
1733 list->flags |= LIGHTREC_NO_MASK;
1735 case PSX_MAP_SCRATCH_PAD:
1736 pr_debug("Flaging opcode %u as scratchpad access\n", i);
1737 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_SCRATCH);
1739 list->flags |= LIGHTREC_NO_MASK;
1741 /* Consider that we're never going to run code from
1742 * the scratchpad. */
1743 list->flags |= LIGHTREC_NO_INVALIDATE;
1745 case PSX_MAP_HW_REGISTERS:
1746 if (state->ops.hw_direct &&
1747 state->ops.hw_direct(kunseg_val,
1748 opcode_is_store(list->c),
1749 opcode_get_io_size(list->c))) {
1750 pr_debug("Flagging opcode %u as direct I/O access\n",
1752 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_DIRECT_HW);
1755 list->flags |= LIGHTREC_NO_MASK;
1757 pr_debug("Flagging opcode %u as I/O access\n",
1759 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_HW);
1767 if (!LIGHTREC_FLAGS_GET_IO_MODE(list->flags)
1768 && list->i.rs >= 28 && list->i.rs <= 29
1769 && !state->maps[PSX_MAP_KERNEL_USER_RAM].ops) {
1770 /* Assume that all I/O operations that target
1771 * $sp or $gp will always only target a mapped
1772 * memory (RAM, BIOS, scratchpad). */
1773 if (state->opt_flags & LIGHTREC_OPT_SP_GP_HIT_RAM)
1774 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_RAM);
1776 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_DIRECT);
1788 static u8 get_mfhi_mflo_reg(const struct block *block, u16 offset,
1789 const struct opcode *last,
1790 u32 mask, bool sync, bool mflo, bool another)
1792 const struct opcode *op, *next = &block->opcode_list[offset];
1794 u8 reg2, reg = mflo ? REG_LO : REG_HI;
1798 for (i = offset; i < block->nb_ops; i++) {
1800 next = &block->opcode_list[i + 1];
1803 /* If any other opcode writes or reads to the register
1804 * we'd use, then we cannot use it anymore. */
1805 mask |= opcode_read_mask(op->c);
1806 mask |= opcode_write_mask(op->c);
1808 if (op_flag_sync(op->flags))
1817 /* TODO: handle backwards branches too */
1818 if (!last && op_flag_local_branch(op->flags) &&
1819 (s16)op->c.i.imm >= 0) {
1820 branch_offset = i + 1 + (s16)op->c.i.imm
1821 - !!op_flag_no_ds(op->flags);
1823 reg = get_mfhi_mflo_reg(block, branch_offset, NULL,
1824 mask, sync, mflo, false);
1825 reg2 = get_mfhi_mflo_reg(block, offset + 1, next,
1826 mask, sync, mflo, false);
1827 if (reg > 0 && reg == reg2)
1833 return mflo ? REG_LO : REG_HI;
1835 case OP_META_MULTU2:
1839 case OP_SPECIAL_MULT:
1840 case OP_SPECIAL_MULTU:
1841 case OP_SPECIAL_DIV:
1842 case OP_SPECIAL_DIVU:
1844 case OP_SPECIAL_MTHI:
1848 case OP_SPECIAL_MTLO:
1856 if (!sync && !op_flag_no_ds(op->flags) &&
1857 (next->i.op == OP_SPECIAL) &&
1858 ((!mflo && next->r.op == OP_SPECIAL_MFHI) ||
1859 (mflo && next->r.op == OP_SPECIAL_MFLO)))
1863 case OP_SPECIAL_JALR:
1865 case OP_SPECIAL_MFHI:
1869 /* Must use REG_HI if there is another MFHI target*/
1870 reg2 = get_mfhi_mflo_reg(block, i + 1, next,
1871 0, sync, mflo, true);
1872 if (reg2 > 0 && reg2 != REG_HI)
1875 if (!sync && !(old_mask & BIT(op->r.rd)))
1881 case OP_SPECIAL_MFLO:
1885 /* Must use REG_LO if there is another MFLO target*/
1886 reg2 = get_mfhi_mflo_reg(block, i + 1, next,
1887 0, sync, mflo, true);
1888 if (reg2 > 0 && reg2 != REG_LO)
1891 if (!sync && !(old_mask & BIT(op->r.rd)))
1910 static void lightrec_replace_lo_hi(struct block *block, u16 offset,
1916 /* This function will remove the following MFLO/MFHI. It must be called
1917 * only if get_mfhi_mflo_reg() returned a non-zero value. */
1919 for (i = offset; i < last; i++) {
1920 struct opcode *op = &block->opcode_list[i];
1928 /* TODO: handle backwards branches too */
1929 if (op_flag_local_branch(op->flags) && (s16)op->c.i.imm >= 0) {
1930 branch_offset = i + 1 + (s16)op->c.i.imm
1931 - !!op_flag_no_ds(op->flags);
1933 lightrec_replace_lo_hi(block, branch_offset, last, lo);
1934 lightrec_replace_lo_hi(block, i + 1, branch_offset, lo);
1939 if (lo && op->r.op == OP_SPECIAL_MFLO) {
1940 pr_debug("Removing MFLO opcode at offset 0x%x\n",
1944 } else if (!lo && op->r.op == OP_SPECIAL_MFHI) {
1945 pr_debug("Removing MFHI opcode at offset 0x%x\n",
1958 static bool lightrec_always_skip_div_check(void)
1967 static int lightrec_flag_mults_divs(struct lightrec_state *state, struct block *block)
1969 struct opcode *list = NULL;
1970 struct constprop_data v[32] = LIGHTREC_CONSTPROP_INITIALIZER;
1974 for (i = 0; i < block->nb_ops - 1; i++) {
1975 list = &block->opcode_list[i];
1977 lightrec_consts_propagate(block, i, v);
1979 switch (list->i.op) {
1981 switch (list->r.op) {
1982 case OP_SPECIAL_DIV:
1983 case OP_SPECIAL_DIVU:
1984 /* If we are dividing by a non-zero constant, don't
1985 * emit the div-by-zero check. */
1986 if (lightrec_always_skip_div_check() ||
1987 (v[list->r.rt].known & v[list->r.rt].value)) {
1988 list->flags |= LIGHTREC_NO_DIV_CHECK;
1991 case OP_SPECIAL_MULT:
1992 case OP_SPECIAL_MULTU:
1999 case OP_META_MULTU2:
2005 /* Don't support opcodes in delay slots */
2006 if (is_delay_slot(block->opcode_list, i) ||
2007 op_flag_no_ds(list->flags)) {
2011 reg_lo = get_mfhi_mflo_reg(block, i + 1, NULL, 0, false, true, false);
2013 pr_debug("Mark MULT(U)/DIV(U) opcode at offset 0x%x as"
2014 " not writing LO\n", i << 2);
2015 list->flags |= LIGHTREC_NO_LO;
2018 reg_hi = get_mfhi_mflo_reg(block, i + 1, NULL, 0, false, false, false);
2020 pr_debug("Mark MULT(U)/DIV(U) opcode at offset 0x%x as"
2021 " not writing HI\n", i << 2);
2022 list->flags |= LIGHTREC_NO_HI;
2025 if (!reg_lo && !reg_hi) {
2026 pr_debug("Both LO/HI unused in this block, they will "
2027 "probably be used in parent block - removing "
2029 list->flags &= ~(LIGHTREC_NO_LO | LIGHTREC_NO_HI);
2032 if (reg_lo > 0 && reg_lo != REG_LO) {
2033 pr_debug("Found register %s to hold LO (rs = %u, rt = %u)\n",
2034 lightrec_reg_name(reg_lo), list->r.rs, list->r.rt);
2036 lightrec_replace_lo_hi(block, i + 1, block->nb_ops, true);
2037 list->r.rd = reg_lo;
2042 if (reg_hi > 0 && reg_hi != REG_HI) {
2043 pr_debug("Found register %s to hold HI (rs = %u, rt = %u)\n",
2044 lightrec_reg_name(reg_hi), list->r.rs, list->r.rt);
2046 lightrec_replace_lo_hi(block, i + 1, block->nb_ops, false);
2047 list->r.imm = reg_hi;
2056 static bool remove_div_sequence(struct block *block, unsigned int offset)
2059 unsigned int i, found = 0;
2062 * Scan for the zero-checking sequence that GCC automatically introduced
2063 * after most DIV/DIVU opcodes. This sequence checks the value of the
2064 * divisor, and if zero, executes a BREAK opcode, causing the BIOS
2065 * handler to crash the PS1.
2067 * For DIV opcodes, this sequence additionally checks that the signed
2068 * operation does not overflow.
2070 * With the assumption that the games never crashed the PS1, we can
2071 * therefore assume that the games never divided by zero or overflowed,
2072 * and these sequences can be removed.
2075 for (i = offset; i < block->nb_ops; i++) {
2076 op = &block->opcode_list[i];
2079 if (op->i.op == OP_SPECIAL &&
2080 (op->r.op == OP_SPECIAL_DIV || op->r.op == OP_SPECIAL_DIVU))
2083 if ((op->opcode & 0xfc1fffff) == 0x14000002) {
2084 /* BNE ???, zero, +8 */
2089 } else if (found == 1 && !op->opcode) {
2092 } else if (found == 2 && op->opcode == 0x0007000d) {
2095 } else if (found == 3 && op->opcode == 0x2401ffff) {
2098 } else if (found == 4 && (op->opcode & 0xfc1fffff) == 0x14010004) {
2099 /* BNE ???, at, +16 */
2101 } else if (found == 5 && op->opcode == 0x3c018000) {
2102 /* LUI at, 0x8000 */
2104 } else if (found == 6 && (op->opcode & 0x141fffff) == 0x14010002) {
2105 /* BNE ???, at, +16 */
2107 } else if (found == 7 && !op->opcode) {
2110 } else if (found == 8 && op->opcode == 0x0006000d) {
2123 pr_debug("Removing DIV%s sequence at offset 0x%x\n",
2124 found == 9 ? "" : "U", offset << 2);
2126 for (i = 0; i < found; i++)
2127 block->opcode_list[offset + i].opcode = 0;
2135 static int lightrec_remove_div_by_zero_check_sequence(struct lightrec_state *state,
2136 struct block *block)
2141 for (i = 0; i < block->nb_ops; i++) {
2142 op = &block->opcode_list[i];
2144 if (op->i.op == OP_SPECIAL &&
2145 (op->r.op == OP_SPECIAL_DIVU || op->r.op == OP_SPECIAL_DIV) &&
2146 remove_div_sequence(block, i + 1))
2147 op->flags |= LIGHTREC_NO_DIV_CHECK;
2153 static const u32 memset_code[] = {
2154 0x10a00006, // beqz a1, 2f
2155 0x24a2ffff, // addiu v0,a1,-1
2156 0x2403ffff, // li v1,-1
2157 0xac800000, // 1: sw zero,0(a0)
2158 0x2442ffff, // addiu v0,v0,-1
2159 0x1443fffd, // bne v0,v1, 1b
2160 0x24840004, // addiu a0,a0,4
2161 0x03e00008, // 2: jr ra
2165 static int lightrec_replace_memset(struct lightrec_state *state, struct block *block)
2170 for (i = 0; i < block->nb_ops; i++) {
2171 c = block->opcode_list[i].c;
2173 if (c.opcode != memset_code[i])
2176 if (i == ARRAY_SIZE(memset_code) - 1) {
2178 pr_debug("Block at PC 0x%x is a memset\n", block->pc);
2179 block_set_flags(block,
2180 BLOCK_IS_MEMSET | BLOCK_NEVER_COMPILE);
2182 /* Return non-zero to skip other optimizers. */
2190 static int lightrec_test_preload_pc(struct lightrec_state *state, struct block *block)
2196 for (i = 0; i < block->nb_ops; i++) {
2197 c = block->opcode_list[i].c;
2198 flags = block->opcode_list[i].flags;
2200 if (op_flag_sync(flags))
2206 block->flags |= BLOCK_PRELOAD_PC;
2211 case OP_REGIMM_BLTZAL:
2212 case OP_REGIMM_BGEZAL:
2213 block->flags |= BLOCK_PRELOAD_PC;
2223 if (!op_flag_local_branch(flags)) {
2224 block->flags |= BLOCK_PRELOAD_PC;
2230 case OP_SPECIAL_JALR:
2232 block->flags |= BLOCK_PRELOAD_PC;
2236 case OP_SPECIAL_SYSCALL:
2237 case OP_SPECIAL_BREAK:
2238 block->flags |= BLOCK_PRELOAD_PC;
2250 static int (*lightrec_optimizers[])(struct lightrec_state *state, struct block *) = {
2251 IF_OPT(OPT_REMOVE_DIV_BY_ZERO_SEQ, &lightrec_remove_div_by_zero_check_sequence),
2252 IF_OPT(OPT_REPLACE_MEMSET, &lightrec_replace_memset),
2253 IF_OPT(OPT_DETECT_IMPOSSIBLE_BRANCHES, &lightrec_detect_impossible_branches),
2254 IF_OPT(OPT_HANDLE_LOAD_DELAYS, &lightrec_handle_load_delays),
2255 IF_OPT(OPT_HANDLE_LOAD_DELAYS, &lightrec_swap_load_delays),
2256 IF_OPT(OPT_TRANSFORM_OPS, &lightrec_transform_branches),
2257 IF_OPT(OPT_LOCAL_BRANCHES, &lightrec_local_branches),
2258 IF_OPT(OPT_TRANSFORM_OPS, &lightrec_transform_ops),
2259 IF_OPT(OPT_SWITCH_DELAY_SLOTS, &lightrec_switch_delay_slots),
2260 IF_OPT(OPT_FLAG_IO, &lightrec_flag_io),
2261 IF_OPT(OPT_FLAG_MULT_DIV, &lightrec_flag_mults_divs),
2262 IF_OPT(OPT_EARLY_UNLOAD, &lightrec_early_unload),
2263 IF_OPT(OPT_PRELOAD_PC, &lightrec_test_preload_pc),
2266 int lightrec_optimize(struct lightrec_state *state, struct block *block)
2271 for (i = 0; i < ARRAY_SIZE(lightrec_optimizers); i++) {
2272 if (lightrec_optimizers[i]) {
2273 ret = (*lightrec_optimizers[i])(state, block);