1 // SPDX-License-Identifier: LGPL-2.1-or-later
3 * Copyright (C) 2014-2021 Paul Cercueil <paul@crapouillou.net>
7 #include "lightrec-config.h"
8 #include "disassembler.h"
10 #include "memmanager.h"
11 #include "optimizer.h"
19 #define IF_OPT(opt, ptr) ((opt) ? (ptr) : NULL)
21 struct optimizer_list {
22 void (**optimizers)(struct opcode *);
23 unsigned int nb_optimizers;
26 static bool is_nop(union code op);
28 bool is_unconditional_jump(union code c)
32 return c.r.op == OP_SPECIAL_JR || c.r.op == OP_SPECIAL_JALR;
38 return c.i.rs == c.i.rt;
40 return (c.r.rt == OP_REGIMM_BGEZ ||
41 c.r.rt == OP_REGIMM_BGEZAL) && c.i.rs == 0;
47 bool is_syscall(union code c)
49 return (c.i.op == OP_SPECIAL && c.r.op == OP_SPECIAL_SYSCALL) ||
50 (c.i.op == OP_CP0 && (c.r.rs == OP_CP0_MTC0 ||
51 c.r.rs == OP_CP0_CTC0) &&
52 (c.r.rd == 12 || c.r.rd == 13));
55 static u64 opcode_read_mask(union code op)
60 case OP_SPECIAL_SYSCALL:
61 case OP_SPECIAL_BREAK:
80 return BIT(op.r.rs) | BIT(op.r.rt);
91 if (op.r.op == OP_CP2_BASIC) {
93 case OP_CP2_BASIC_MTC2:
94 case OP_CP2_BASIC_CTC2:
106 if (op.i.rs == op.i.rt)
119 return BIT(op.i.rs) | BIT(op.i.rt);
127 static u64 mult_div_write_mask(union code op)
131 if (!OPT_FLAG_MULT_DIV)
132 return BIT(REG_LO) | BIT(REG_HI);
135 flags = BIT(op.r.rd);
139 flags |= BIT(op.r.imm);
141 flags |= BIT(REG_HI);
146 u64 opcode_write_mask(union code op)
151 return mult_div_write_mask(op);
157 case OP_SPECIAL_SYSCALL:
158 case OP_SPECIAL_BREAK:
160 case OP_SPECIAL_MULT:
161 case OP_SPECIAL_MULTU:
163 case OP_SPECIAL_DIVU:
164 return mult_div_write_mask(op);
165 case OP_SPECIAL_MTHI:
167 case OP_SPECIAL_MTLO:
204 if (op.r.op == OP_CP2_BASIC) {
206 case OP_CP2_BASIC_MFC2:
207 case OP_CP2_BASIC_CFC2:
216 case OP_REGIMM_BLTZAL:
217 case OP_REGIMM_BGEZAL:
227 bool opcode_reads_register(union code op, u8 reg)
229 return opcode_read_mask(op) & BIT(reg);
232 bool opcode_writes_register(union code op, u8 reg)
234 return opcode_write_mask(op) & BIT(reg);
237 static int find_prev_writer(const struct opcode *list, unsigned int offset, u8 reg)
242 if (op_flag_sync(list[offset].flags))
245 for (i = offset; i > 0; i--) {
248 if (opcode_writes_register(c, reg)) {
249 if (i > 1 && has_delay_slot(list[i - 2].c))
255 if (op_flag_sync(list[i - 1].flags) ||
257 opcode_reads_register(c, reg))
264 static int find_next_reader(const struct opcode *list, unsigned int offset, u8 reg)
269 if (op_flag_sync(list[offset].flags))
272 for (i = offset; ; i++) {
275 if (opcode_reads_register(c, reg))
278 if (op_flag_sync(list[i].flags)
279 || (op_flag_no_ds(list[i].flags) && has_delay_slot(c))
280 || is_delay_slot(list, i)
281 || opcode_writes_register(c, reg))
288 static bool reg_is_dead(const struct opcode *list, unsigned int offset, u8 reg)
292 if (op_flag_sync(list[offset].flags) || is_delay_slot(list, offset))
295 for (i = offset + 1; ; i++) {
296 if (opcode_reads_register(list[i].c, reg))
299 if (opcode_writes_register(list[i].c, reg))
302 if (is_syscall(list[i].c))
305 if (has_delay_slot(list[i].c)) {
306 if (op_flag_no_ds(list[i].flags) ||
307 opcode_reads_register(list[i + 1].c, reg))
310 return opcode_writes_register(list[i + 1].c, reg);
315 static bool reg_is_read(const struct opcode *list,
316 unsigned int a, unsigned int b, u8 reg)
318 /* Return true if reg is read in one of the opcodes of the interval
321 if (!is_nop(list[a].c) && opcode_reads_register(list[a].c, reg))
328 static bool reg_is_written(const struct opcode *list,
329 unsigned int a, unsigned int b, u8 reg)
331 /* Return true if reg is written in one of the opcodes of the interval
335 if (!is_nop(list[a].c) && opcode_writes_register(list[a].c, reg))
342 static bool reg_is_read_or_written(const struct opcode *list,
343 unsigned int a, unsigned int b, u8 reg)
345 return reg_is_read(list, a, b, reg) || reg_is_written(list, a, b, reg);
348 static bool opcode_is_mfc(union code op)
362 if (op.r.op == OP_CP2_BASIC) {
364 case OP_CP2_BASIC_MFC2:
365 case OP_CP2_BASIC_CFC2:
380 static bool opcode_is_load(union code op)
398 static bool opcode_is_store(union code op)
414 bool opcode_has_load_delay(union code op)
416 return (opcode_is_load(op) && op.i.rt && op.i.op != OP_LWC2)
417 || opcode_is_mfc(op);
420 static u8 opcode_get_io_size(union code op)
436 bool opcode_is_io(union code op)
438 return opcode_is_load(op) || opcode_is_store(op);
442 static bool is_nop(union code op)
444 if (opcode_writes_register(op, 0)) {
447 return op.r.rs != OP_CP0_MFC0;
466 return op.r.rd == op.r.rt && op.r.rd == op.r.rs;
468 case OP_SPECIAL_ADDU:
469 return (op.r.rd == op.r.rt && op.r.rs == 0) ||
470 (op.r.rd == op.r.rs && op.r.rt == 0);
472 case OP_SPECIAL_SUBU:
473 return op.r.rd == op.r.rs && op.r.rt == 0;
475 if (op.r.rd == op.r.rt)
476 return op.r.rd == op.r.rs || op.r.rs == 0;
478 return (op.r.rd == op.r.rs) && op.r.rt == 0;
482 return op.r.rd == op.r.rt && op.r.imm == 0;
483 case OP_SPECIAL_MFHI:
484 case OP_SPECIAL_MFLO:
492 return op.i.rt == op.i.rs && op.i.imm == 0;
494 return (op.i.rs == 0 || op.i.imm == 1);
496 return (op.i.op == OP_REGIMM_BLTZ ||
497 op.i.op == OP_REGIMM_BLTZAL) &&
498 (op.i.rs == 0 || op.i.imm == 1);
500 return (op.i.rs == op.i.rt || op.i.imm == 1);
506 static void lightrec_optimize_sll_sra(struct opcode *list, unsigned int offset,
507 struct constprop_data *v)
509 struct opcode *ldop = NULL, *curr = &list[offset], *next;
510 struct opcode *to_change, *to_nop;
513 if (curr->r.imm != 24 && curr->r.imm != 16)
516 if (is_delay_slot(list, offset))
519 idx = find_next_reader(list, offset + 1, curr->r.rd);
525 if (next->i.op != OP_SPECIAL || next->r.op != OP_SPECIAL_SRA ||
526 next->r.imm != curr->r.imm || next->r.rt != curr->r.rd)
529 if (curr->r.rd != curr->r.rt && next->r.rd != next->r.rt) {
534 if (!reg_is_dead(list, idx, curr->r.rd) ||
535 reg_is_read_or_written(list, offset, idx, next->r.rd))
538 /* If rY is dead after the SRL, and rZ is not used after the SLL,
539 * we can change rY to rZ */
541 pr_debug("Detected SLL/SRA with middle temp register\n");
542 curr->r.rd = next->r.rd;
543 next->r.rt = curr->r.rd;
546 /* We got a SLL/SRA combo. If imm #16, that's a cast to s16.
547 * If imm #24 that's a cast to s8.
549 * First of all, make sure that the target register of the SLL is not
550 * read after the SRA. */
552 if (curr->r.rd == curr->r.rt) {
559 /* rX is used after the SRA - we cannot convert it. */
560 if (curr->r.rd != next->r.rd && !reg_is_dead(list, idx, curr->r.rd))
570 idx2 = find_prev_writer(list, offset, curr->r.rt);
572 /* Note that PSX games sometimes do casts after
573 * a LHU or LBU; in this case we can change the
574 * load opcode to a LH or LB, and the cast can
575 * be changed to a MOV or a simple NOP. */
579 if (next->r.rd != ldop->i.rt &&
580 !reg_is_dead(list, idx, ldop->i.rt))
582 else if (curr->r.imm == 16 && ldop->i.op == OP_LHU)
584 else if (curr->r.imm == 24 && ldop->i.op == OP_LBU)
590 if (next->r.rd == ldop->i.rt) {
591 to_change->opcode = 0;
592 } else if (reg_is_dead(list, idx, ldop->i.rt) &&
593 !reg_is_read_or_written(list, idx2 + 1, idx, next->r.rd)) {
594 /* The target register of the SRA is dead after the
595 * LBU/LHU; we can change the target register of the
596 * LBU/LHU to the one of the SRA. */
597 v[ldop->i.rt].known = 0;
598 v[ldop->i.rt].sign = 0;
599 ldop->i.rt = next->r.rd;
600 to_change->opcode = 0;
602 to_change->i.op = OP_META;
603 to_change->m.op = OP_META_MOV;
604 to_change->m.rd = next->r.rd;
605 to_change->m.rs = ldop->i.rt;
608 if (to_nop->r.imm == 24)
609 pr_debug("Convert LBU+SLL+SRA to LB\n");
611 pr_debug("Convert LHU+SLL+SRA to LH\n");
613 v[ldop->i.rt].known = 0;
614 v[ldop->i.rt].sign = 0xffffff80 << (24 - curr->r.imm);
619 pr_debug("Convert SLL/SRA #%u to EXT%c\n",
620 curr->r.imm, curr->r.imm == 24 ? 'C' : 'S');
622 to_change->m.rs = curr->r.rt;
623 to_change->m.op = to_nop->r.imm == 24 ? OP_META_EXTC : OP_META_EXTS;
624 to_change->i.op = OP_META;
631 lightrec_remove_useless_lui(struct block *block, unsigned int offset,
632 const struct constprop_data *v)
634 struct opcode *list = block->opcode_list,
635 *op = &block->opcode_list[offset];
638 if (!op_flag_sync(op->flags) && is_known(v, op->i.rt) &&
639 v[op->i.rt].value == op->i.imm << 16) {
640 pr_debug("Converting duplicated LUI to NOP\n");
645 if (op->i.imm != 0 || op->i.rt == 0 || offset == block->nb_ops - 1)
648 reader = find_next_reader(list, offset + 1, op->i.rt);
652 if (opcode_writes_register(list[reader].c, op->i.rt) ||
653 reg_is_dead(list, reader, op->i.rt)) {
654 pr_debug("Removing useless LUI 0x0\n");
656 if (list[reader].i.rs == op->i.rt)
657 list[reader].i.rs = 0;
658 if (list[reader].i.op == OP_SPECIAL &&
659 list[reader].i.rt == op->i.rt)
660 list[reader].i.rt = 0;
665 static void lightrec_lui_to_movi(struct block *block, unsigned int offset)
667 struct opcode *ori, *lui = &block->opcode_list[offset];
670 if (lui->i.op != OP_LUI)
673 next = find_next_reader(block->opcode_list, offset + 1, lui->i.rt);
675 ori = &block->opcode_list[next];
681 if (ori->i.rs == ori->i.rt && ori->i.imm) {
682 ori->flags |= LIGHTREC_MOVI;
683 lui->flags |= LIGHTREC_MOVI;
690 static void lightrec_modify_lui(struct block *block, unsigned int offset)
692 union code c, *lui = &block->opcode_list[offset].c;
693 bool stop = false, stop_next = false;
696 for (i = offset + 1; !stop && i < block->nb_ops; i++) {
697 c = block->opcode_list[i].c;
700 if ((opcode_is_store(c) && c.i.rt == lui->i.rt)
701 || (!opcode_is_load(c) && opcode_reads_register(c, lui->i.rt)))
704 if (opcode_writes_register(c, lui->i.rt)) {
705 if (c.i.op == OP_LWL || c.i.op == OP_LWR) {
706 /* LWL/LWR only partially write their target register;
707 * therefore the LUI should not write a different value. */
711 pr_debug("Convert LUI at offset 0x%x to kuseg\n",
713 lui->i.imm = kunseg(lui->i.imm << 16) >> 16;
717 if (has_delay_slot(c))
722 static int lightrec_transform_branches(struct lightrec_state *state,
729 for (i = 0; i < block->nb_ops; i++) {
730 op = &block->opcode_list[i];
734 /* Transform J opcode into BEQ $zero, $zero if possible. */
735 offset = (s32)((block->pc & 0xf0000000) >> 2 | op->j.imm)
736 - (s32)(block->pc >> 2) - (s32)i - 1;
738 if (offset == (s16)offset) {
739 pr_debug("Transform J into BEQ $zero, $zero\n");
755 static inline bool is_power_of_two(u32 value)
757 return popcount32(value) == 1;
760 static void lightrec_patch_known_zero(struct opcode *op,
761 const struct constprop_data *v)
767 case OP_SPECIAL_JALR:
768 case OP_SPECIAL_MTHI:
769 case OP_SPECIAL_MTLO:
770 if (is_known_zero(v, op->r.rs))
774 if (is_known_zero(v, op->r.rs))
780 if (is_known_zero(v, op->r.rt))
783 case OP_SPECIAL_SYSCALL:
784 case OP_SPECIAL_BREAK:
785 case OP_SPECIAL_MFHI:
786 case OP_SPECIAL_MFLO:
794 if (is_known_zero(v, op->r.rt))
802 if (op->r.op == OP_CP2_BASIC) {
804 case OP_CP2_BASIC_MTC2:
805 case OP_CP2_BASIC_CTC2:
806 if (is_known_zero(v, op->r.rt))
816 if (is_known_zero(v, op->i.rt))
832 if (is_known_zero(v, op->m.rs))
841 if (is_known_zero(v, op->i.rt))
854 if (is_known(v, op->i.rs)
855 && kunseg(v[op->i.rs].value) == 0)
863 static void lightrec_reset_syncs(struct block *block)
865 struct opcode *op, *list = block->opcode_list;
869 for (i = 0; i < block->nb_ops; i++)
870 list[i].flags &= ~LIGHTREC_SYNC;
872 for (i = 0; i < block->nb_ops; i++) {
875 if (has_delay_slot(op->c)) {
876 if (op_flag_local_branch(op->flags)) {
877 offset = i + 1 - op_flag_no_ds(op->flags) + (s16)op->i.imm;
878 list[offset].flags |= LIGHTREC_SYNC;
881 if (op_flag_emulate_branch(op->flags) && i + 2 < block->nb_ops)
882 list[i + 2].flags |= LIGHTREC_SYNC;
887 static void maybe_remove_load_delay(struct opcode *op)
889 if (op_flag_load_delay(op->flags) && opcode_is_load(op->c))
890 op->flags &= ~LIGHTREC_LOAD_DELAY;
893 static int lightrec_transform_ops(struct lightrec_state *state, struct block *block)
895 struct opcode *op, *list = block->opcode_list;
896 struct constprop_data v[32] = LIGHTREC_CONSTPROP_INITIALIZER;
902 for (i = 0; i < block->nb_ops; i++) {
905 lightrec_consts_propagate(block, i, v);
907 lightrec_patch_known_zero(op, v);
909 /* Transform all opcodes detected as useless to real NOPs
910 * (0x0: SLL r0, r0, #0) */
911 if (op->opcode != 0 && is_nop(op->c)) {
912 pr_debug("Converting useless opcode 0x%08x to NOP\n",
922 if (op->i.rs == op->i.rt ||
923 (is_known(v, op->i.rs) && is_known(v, op->i.rt) &&
924 v[op->i.rs].value == v[op->i.rt].value)) {
925 if (op->i.rs != op->i.rt)
926 pr_debug("Found always-taken BEQ\n");
930 } else if (v[op->i.rs].known & v[op->i.rt].known &
931 (v[op->i.rs].value ^ v[op->i.rt].value)) {
932 pr_debug("Found never-taken BEQ\n");
934 if (!op_flag_no_ds(op->flags))
935 maybe_remove_load_delay(&list[i + 1]);
937 local = op_flag_local_branch(op->flags);
942 lightrec_reset_syncs(block);
943 } else if (op->i.rs == 0) {
950 if (v[op->i.rs].known & v[op->i.rt].known &
951 (v[op->i.rs].value ^ v[op->i.rt].value)) {
952 pr_debug("Found always-taken BNE\n");
957 } else if (is_known(v, op->i.rs) && is_known(v, op->i.rt) &&
958 v[op->i.rs].value == v[op->i.rt].value) {
959 pr_debug("Found never-taken BNE\n");
961 if (!op_flag_no_ds(op->flags))
962 maybe_remove_load_delay(&list[i + 1]);
964 local = op_flag_local_branch(op->flags);
969 lightrec_reset_syncs(block);
970 } else if (op->i.rs == 0) {
977 if (v[op->i.rs].known & BIT(31) &&
978 v[op->i.rs].value & BIT(31)) {
979 pr_debug("Found always-taken BLEZ\n");
988 if (v[op->i.rs].known & BIT(31) &&
989 v[op->i.rs].value & BIT(31)) {
990 pr_debug("Found never-taken BGTZ\n");
992 if (!op_flag_no_ds(op->flags))
993 maybe_remove_load_delay(&list[i + 1]);
995 local = op_flag_local_branch(op->flags);
1000 lightrec_reset_syncs(block);
1005 if (i == 0 || !has_delay_slot(list[i - 1].c))
1006 lightrec_modify_lui(block, i);
1007 lightrec_remove_useless_lui(block, i, v);
1008 if (i == 0 || !has_delay_slot(list[i - 1].c))
1009 lightrec_lui_to_movi(block, i);
1012 /* Transform ORI/ADDI/ADDIU with imm #0 or ORR/ADD/ADDU/SUB/SUBU
1013 * with register $zero to the MOV meta-opcode */
1017 if (op->i.imm == 0) {
1018 pr_debug("Convert ORI/ADDI/ADDIU #0 to MOV\n");
1019 op->m.rd = op->i.rt;
1020 op->m.op = OP_META_MOV;
1025 if (bits_are_known_zero(v, op->i.rs, ~op->i.imm)) {
1026 pr_debug("Found useless ANDI 0x%x\n", op->i.imm);
1028 if (op->i.rs == op->i.rt) {
1031 op->m.rd = op->i.rt;
1032 op->m.op = OP_META_MOV;
1039 if (i == 0 || !has_delay_slot(list[i - 1].c)) {
1040 idx = find_next_reader(list, i + 1, op->i.rt);
1041 if (idx > 0 && list[idx].i.op == (op->i.op ^ 0x4)
1042 && list[idx].i.rs == op->i.rs
1043 && list[idx].i.rt == op->i.rt
1044 && abs((s16)op->i.imm - (s16)list[idx].i.imm) == 3) {
1045 /* Replace a LWL/LWR combo with a META_LWU */
1046 if (op->i.op == OP_LWL)
1048 op->i.op = OP_META_LWU;
1049 list[idx].opcode = 0;
1050 pr_debug("Convert LWL/LWR to LWU\n");
1056 if (i == 0 || !has_delay_slot(list[i - 1].c)) {
1057 idx = find_next_reader(list, i + 1, op->i.rt);
1058 if (idx > 0 && list[idx].i.op == (op->i.op ^ 0x4)
1059 && list[idx].i.rs == op->i.rs
1060 && list[idx].i.rt == op->i.rt
1061 && abs((s16)op->i.imm - (s16)list[idx].i.imm) == 3) {
1062 /* Replace a SWL/SWR combo with a META_SWU */
1063 if (op->i.op == OP_SWL)
1065 op->i.op = OP_META_SWU;
1066 list[idx].opcode = 0;
1067 pr_debug("Convert SWL/SWR to SWU\n");
1073 case OP_REGIMM_BLTZ:
1074 case OP_REGIMM_BGEZ:
1075 if (!(v[op->r.rs].known & BIT(31)))
1078 if (!!(v[op->r.rs].value & BIT(31))
1079 ^ (op->r.rt == OP_REGIMM_BGEZ)) {
1080 pr_debug("Found always-taken BLTZ/BGEZ\n");
1085 pr_debug("Found never-taken BLTZ/BGEZ\n");
1087 if (!op_flag_no_ds(op->flags))
1088 maybe_remove_load_delay(&list[i + 1]);
1090 local = op_flag_local_branch(op->flags);
1095 lightrec_reset_syncs(block);
1098 case OP_REGIMM_BLTZAL:
1099 case OP_REGIMM_BGEZAL:
1100 /* TODO: Detect always-taken and replace with JAL */
1106 case OP_SPECIAL_SRAV:
1107 if ((v[op->r.rs].known & 0x1f) != 0x1f)
1110 pr_debug("Convert SRAV to SRA\n");
1111 op->r.imm = v[op->r.rs].value & 0x1f;
1112 op->r.op = OP_SPECIAL_SRA;
1115 case OP_SPECIAL_SRA:
1116 if (op->r.imm == 0) {
1117 pr_debug("Convert SRA #0 to MOV\n");
1118 op->m.rs = op->r.rt;
1119 op->m.op = OP_META_MOV;
1125 case OP_SPECIAL_SLLV:
1126 if ((v[op->r.rs].known & 0x1f) != 0x1f)
1129 pr_debug("Convert SLLV to SLL\n");
1130 op->r.imm = v[op->r.rs].value & 0x1f;
1131 op->r.op = OP_SPECIAL_SLL;
1134 case OP_SPECIAL_SLL:
1135 if (op->r.imm == 0) {
1136 pr_debug("Convert SLL #0 to MOV\n");
1137 op->m.rs = op->r.rt;
1138 op->m.op = OP_META_MOV;
1142 lightrec_optimize_sll_sra(block->opcode_list, i, v);
1145 case OP_SPECIAL_SRLV:
1146 if ((v[op->r.rs].known & 0x1f) != 0x1f)
1149 pr_debug("Convert SRLV to SRL\n");
1150 op->r.imm = v[op->r.rs].value & 0x1f;
1151 op->r.op = OP_SPECIAL_SRL;
1154 case OP_SPECIAL_SRL:
1155 if (op->r.imm == 0) {
1156 pr_debug("Convert SRL #0 to MOV\n");
1157 op->m.rs = op->r.rt;
1158 op->m.op = OP_META_MOV;
1163 case OP_SPECIAL_MULT:
1164 case OP_SPECIAL_MULTU:
1165 if (is_known(v, op->r.rs) &&
1166 is_power_of_two(v[op->r.rs].value)) {
1168 op->c.i.rs = op->c.i.rt;
1170 } else if (!is_known(v, op->r.rt) ||
1171 !is_power_of_two(v[op->r.rt].value)) {
1175 pr_debug("Multiply by power-of-two: %u\n",
1178 if (op->r.op == OP_SPECIAL_MULT)
1179 op->i.op = OP_META_MULT2;
1181 op->i.op = OP_META_MULTU2;
1183 op->r.op = ctz32(v[op->r.rt].value);
1185 case OP_SPECIAL_NOR:
1186 if (op->r.rs == 0 || op->r.rt == 0) {
1187 pr_debug("Convert NOR $zero to COM\n");
1189 op->m.op = OP_META_COM;
1191 op->m.rs = op->r.rt;
1195 case OP_SPECIAL_ADD:
1196 case OP_SPECIAL_ADDU:
1197 if (op->r.rs == 0) {
1198 pr_debug("Convert OR/ADD $zero to MOV\n");
1199 op->m.rs = op->r.rt;
1200 op->m.op = OP_META_MOV;
1204 case OP_SPECIAL_SUB:
1205 case OP_SPECIAL_SUBU:
1206 if (op->r.rt == 0) {
1207 pr_debug("Convert OR/ADD/SUB $zero to MOV\n");
1208 op->m.op = OP_META_MOV;
1224 static bool lightrec_can_switch_delay_slot(union code op, union code next_op)
1229 case OP_SPECIAL_JALR:
1230 if (opcode_reads_register(next_op, op.r.rd) ||
1231 opcode_writes_register(next_op, op.r.rd))
1235 if (opcode_writes_register(next_op, op.r.rs))
1245 if (opcode_reads_register(next_op, 31) ||
1246 opcode_writes_register(next_op, 31))
1252 if (op.i.rt && opcode_writes_register(next_op, op.i.rt))
1257 if (op.i.rs && opcode_writes_register(next_op, op.i.rs))
1262 case OP_REGIMM_BLTZAL:
1263 case OP_REGIMM_BGEZAL:
1264 if (opcode_reads_register(next_op, 31) ||
1265 opcode_writes_register(next_op, 31))
1268 case OP_REGIMM_BLTZ:
1269 case OP_REGIMM_BGEZ:
1270 if (op.i.rs && opcode_writes_register(next_op, op.i.rs))
1282 static int lightrec_switch_delay_slots(struct lightrec_state *state, struct block *block)
1284 struct opcode *list, *next = &block->opcode_list[0];
1286 union code op, next_op;
1289 for (i = 0; i < block->nb_ops - 1; i++) {
1291 next = &block->opcode_list[i + 1];
1295 if (!has_delay_slot(op) || op_flag_no_ds(list->flags) ||
1296 op_flag_emulate_branch(list->flags) ||
1297 op.opcode == 0 || next_op.opcode == 0)
1300 if (is_delay_slot(block->opcode_list, i))
1303 if (op_flag_sync(next->flags))
1306 if (op_flag_load_delay(next->flags) && opcode_is_load(next_op))
1309 if (!lightrec_can_switch_delay_slot(list->c, next_op))
1312 pr_debug("Swap branch and delay slot opcodes "
1313 "at offsets 0x%x / 0x%x\n",
1314 i << 2, (i + 1) << 2);
1316 flags = next->flags | (list->flags & LIGHTREC_SYNC);
1319 next->flags = (list->flags | LIGHTREC_NO_DS) & ~LIGHTREC_SYNC;
1320 list->flags = flags | LIGHTREC_NO_DS;
1326 static int lightrec_detect_impossible_branches(struct lightrec_state *state,
1327 struct block *block)
1329 struct opcode *op, *list = block->opcode_list, *next = &list[0];
1333 for (i = 0; i < block->nb_ops - 1; i++) {
1335 next = &list[i + 1];
1337 if (!has_delay_slot(op->c) ||
1338 (!has_delay_slot(next->c) &&
1339 !opcode_is_mfc(next->c) &&
1340 !(next->i.op == OP_CP0 && next->r.rs == OP_CP0_RFE)))
1343 if (op->c.opcode == next->c.opcode) {
1344 /* The delay slot is the exact same opcode as the branch
1345 * opcode: this is effectively a NOP */
1350 op->flags |= LIGHTREC_EMULATE_BRANCH;
1352 if (OPT_LOCAL_BRANCHES && i + 2 < block->nb_ops) {
1353 /* The interpreter will only emulate the branch, then
1354 * return to the compiled code. Add a SYNC after the
1355 * branch + delay slot in the case where the branch
1357 list[i + 2].flags |= LIGHTREC_SYNC;
1364 static bool is_local_branch(const struct block *block, unsigned int idx)
1366 const struct opcode *op = &block->opcode_list[idx];
1369 switch (op->c.i.op) {
1375 offset = idx + 1 + (s16)op->c.i.imm;
1376 if (offset >= 0 && offset < block->nb_ops)
1384 static int lightrec_handle_load_delays(struct lightrec_state *state,
1385 struct block *block)
1387 struct opcode *op, *list = block->opcode_list;
1391 for (i = 0; i < block->nb_ops; i++) {
1394 if (!opcode_has_load_delay(op->c))
1397 if (!is_delay_slot(list, i)) {
1398 /* Only handle load delays in delay slots.
1399 * PSX games never abused load delay slots otherwise. */
1403 if (is_local_branch(block, i - 1)) {
1404 imm = (s16)list[i - 1].c.i.imm;
1406 if (!opcode_reads_register(list[i + imm].c, op->c.i.rt)) {
1407 /* The target opcode of the branch is inside
1408 * the block, and it does not read the register
1409 * written to by the load opcode; we can ignore
1410 * the load delay. */
1415 op->flags |= LIGHTREC_LOAD_DELAY;
1421 static int lightrec_swap_load_delays(struct lightrec_state *state,
1422 struct block *block)
1426 bool in_ds = false, skip_next = false;
1429 if (block->nb_ops < 2)
1432 for (i = 0; i < block->nb_ops - 2; i++) {
1433 c = block->opcode_list[i].c;
1437 } else if (!in_ds && opcode_is_load(c) && c.i.op != OP_LWC2) {
1438 next = block->opcode_list[i + 1].c;
1440 switch (next.i.op) {
1451 if (opcode_reads_register(next, c.i.rt)
1452 && !opcode_writes_register(next, c.i.rs)) {
1453 pr_debug("Swapping opcodes at offset 0x%x to "
1454 "respect load delay\n", i << 2);
1456 op = block->opcode_list[i];
1457 block->opcode_list[i] = block->opcode_list[i + 1];
1458 block->opcode_list[i + 1] = op;
1463 in_ds = has_delay_slot(c);
1469 static int lightrec_local_branches(struct lightrec_state *state, struct block *block)
1471 const struct opcode *ds;
1472 struct opcode *list;
1476 for (i = 0; i < block->nb_ops; i++) {
1477 list = &block->opcode_list[i];
1479 if (should_emulate(list) || !is_local_branch(block, i))
1482 offset = i + 1 + (s16)list->c.i.imm;
1484 pr_debug("Found local branch to offset 0x%x\n", offset << 2);
1486 ds = get_delay_slot(block->opcode_list, i);
1487 if (op_flag_load_delay(ds->flags) && opcode_is_load(ds->c)) {
1488 pr_debug("Branch delay slot has a load delay - skip\n");
1492 if (should_emulate(&block->opcode_list[offset])) {
1493 pr_debug("Branch target must be emulated - skip\n");
1497 if (offset && has_delay_slot(block->opcode_list[offset - 1].c)) {
1498 pr_debug("Branch target is a delay slot - skip\n");
1502 list->flags |= LIGHTREC_LOCAL_BRANCH;
1505 lightrec_reset_syncs(block);
1510 bool has_delay_slot(union code op)
1516 case OP_SPECIAL_JALR:
1534 bool is_delay_slot(const struct opcode *list, unsigned int offset)
1537 && !op_flag_no_ds(list[offset - 1].flags)
1538 && has_delay_slot(list[offset - 1].c);
1541 bool should_emulate(const struct opcode *list)
1543 return op_flag_emulate_branch(list->flags) && has_delay_slot(list->c);
1546 static bool op_writes_rd(union code c)
1557 static void lightrec_add_reg_op(struct opcode *op, u8 reg, u32 reg_op)
1559 if (op_writes_rd(op->c) && reg == op->r.rd)
1560 op->flags |= LIGHTREC_REG_RD(reg_op);
1561 else if (op->i.rs == reg)
1562 op->flags |= LIGHTREC_REG_RS(reg_op);
1563 else if (op->i.rt == reg)
1564 op->flags |= LIGHTREC_REG_RT(reg_op);
1566 pr_debug("Cannot add unload/clean/discard flag: "
1567 "opcode does not touch register %s!\n",
1568 lightrec_reg_name(reg));
1571 static void lightrec_add_unload(struct opcode *op, u8 reg)
1573 lightrec_add_reg_op(op, reg, LIGHTREC_REG_UNLOAD);
1576 static void lightrec_add_discard(struct opcode *op, u8 reg)
1578 lightrec_add_reg_op(op, reg, LIGHTREC_REG_DISCARD);
1581 static void lightrec_add_clean(struct opcode *op, u8 reg)
1583 lightrec_add_reg_op(op, reg, LIGHTREC_REG_CLEAN);
1587 lightrec_early_unload_sync(struct opcode *list, s16 *last_r, s16 *last_w)
1592 for (reg = 0; reg < 34; reg++) {
1593 offset = s16_max(last_w[reg], last_r[reg]);
1596 lightrec_add_unload(&list[offset], reg);
1599 memset(last_r, 0xff, sizeof(*last_r) * 34);
1600 memset(last_w, 0xff, sizeof(*last_w) * 34);
1603 static int lightrec_early_unload(struct lightrec_state *state, struct block *block)
1607 s16 last_r[34], last_w[34], last_sync = 0, next_sync = 0;
1608 u64 mask_r, mask_w, dirty = 0, loaded = 0;
1609 u8 reg, load_delay_reg = 0;
1611 memset(last_r, 0xff, sizeof(last_r));
1612 memset(last_w, 0xff, sizeof(last_w));
1616 * - the register is dirty, and is read again after a branch opcode
1619 * - the register is dirty or loaded, and is not read again
1620 * - the register is dirty or loaded, and is written again after a branch opcode
1621 * - the next opcode has the SYNC flag set
1624 * - the register is dirty or loaded, and is written again
1627 for (i = 0; i < block->nb_ops; i++) {
1628 op = &block->opcode_list[i];
1630 if (OPT_HANDLE_LOAD_DELAYS && load_delay_reg) {
1631 /* Handle delayed register write from load opcodes in
1633 last_w[load_delay_reg] = i;
1637 if (op_flag_sync(op->flags) || should_emulate(op)) {
1638 /* The next opcode has the SYNC flag set, or is a branch
1639 * that should be emulated: unload all registers. */
1640 lightrec_early_unload_sync(block->opcode_list, last_r, last_w);
1645 if (next_sync == i) {
1647 pr_debug("Last sync: 0x%x\n", last_sync << 2);
1650 if (has_delay_slot(op->c)) {
1651 next_sync = i + 1 + !op_flag_no_ds(op->flags);
1652 pr_debug("Next sync: 0x%x\n", next_sync << 2);
1655 mask_r = opcode_read_mask(op->c);
1656 mask_w = opcode_write_mask(op->c);
1658 if (op_flag_load_delay(op->flags) && opcode_is_load(op->c)) {
1659 /* If we have a load opcode in a delay slot, its target
1660 * register is actually not written there but at a
1661 * later point, in the dispatcher. Prevent the algorithm
1662 * from discarding its previous value. */
1663 load_delay_reg = op->c.i.rt;
1664 mask_w &= ~BIT(op->c.i.rt);
1667 for (reg = 0; reg < 34; reg++) {
1668 if (mask_r & BIT(reg)) {
1669 if (dirty & BIT(reg) && last_w[reg] < last_sync) {
1670 /* The register is dirty, and is read
1671 * again after a branch: clean it */
1673 lightrec_add_clean(&block->opcode_list[last_w[reg]], reg);
1681 if (mask_w & BIT(reg)) {
1682 if ((dirty & BIT(reg) && last_w[reg] < last_sync) ||
1683 (loaded & BIT(reg) && last_r[reg] < last_sync)) {
1684 /* The register is dirty or loaded, and
1685 * is written again after a branch:
1688 offset = s16_max(last_w[reg], last_r[reg]);
1689 lightrec_add_unload(&block->opcode_list[offset], reg);
1691 loaded &= ~BIT(reg);
1692 } else if (!(mask_r & BIT(reg)) &&
1693 ((dirty & BIT(reg) && last_w[reg] > last_sync) ||
1694 (loaded & BIT(reg) && last_r[reg] > last_sync))) {
1695 /* The register is dirty or loaded, and
1696 * is written again: discard it */
1698 offset = s16_max(last_w[reg], last_r[reg]);
1699 lightrec_add_discard(&block->opcode_list[offset], reg);
1701 loaded &= ~BIT(reg);
1713 /* Unload all registers that are dirty or loaded at the end of block. */
1714 lightrec_early_unload_sync(block->opcode_list, last_r, last_w);
1719 static int lightrec_flag_io(struct lightrec_state *state, struct block *block)
1721 struct opcode *list;
1722 enum psx_map psx_map;
1723 struct constprop_data v[32] = LIGHTREC_CONSTPROP_INITIALIZER;
1725 u32 val, kunseg_val;
1728 for (i = 0; i < block->nb_ops; i++) {
1729 list = &block->opcode_list[i];
1731 lightrec_consts_propagate(block, i, v);
1733 switch (list->i.op) {
1737 /* Mark all store operations that target $sp or $gp
1738 * as not requiring code invalidation. This is based
1739 * on the heuristic that stores using one of these
1740 * registers as address will never hit a code page. */
1741 if (list->i.rs >= 28 && list->i.rs <= 29 &&
1742 !state->maps[PSX_MAP_KERNEL_USER_RAM].ops) {
1743 pr_debug("Flaging opcode 0x%08x as not requiring invalidation\n",
1745 list->flags |= LIGHTREC_NO_INVALIDATE;
1748 /* Detect writes whose destination address is inside the
1749 * current block, using constant propagation. When these
1750 * occur, we mark the blocks as not compilable. */
1751 if (is_known(v, list->i.rs) &&
1752 kunseg(v[list->i.rs].value) >= kunseg(block->pc) &&
1753 kunseg(v[list->i.rs].value) < (kunseg(block->pc) + block->nb_ops * 4)) {
1754 pr_debug("Self-modifying block detected\n");
1755 block_set_flags(block, BLOCK_NEVER_COMPILE);
1756 list->flags |= LIGHTREC_SMC;
1770 if (v[list->i.rs].known | v[list->i.rs].sign) {
1771 psx_map = lightrec_get_constprop_map(state, v,
1775 if (psx_map != PSX_MAP_UNKNOWN && !is_known(v, list->i.rs))
1776 pr_debug("Detected map thanks to bit-level const propagation!\n");
1778 list->flags &= ~LIGHTREC_IO_MASK;
1780 val = v[list->i.rs].value + (s16) list->i.imm;
1781 kunseg_val = kunseg(val);
1783 no_mask = (v[list->i.rs].known & ~v[list->i.rs].value
1784 & 0xe0000000) == 0xe0000000;
1787 case PSX_MAP_KERNEL_USER_RAM:
1789 list->flags |= LIGHTREC_NO_MASK;
1791 case PSX_MAP_MIRROR1:
1792 case PSX_MAP_MIRROR2:
1793 case PSX_MAP_MIRROR3:
1794 pr_debug("Flaging opcode %u as RAM access\n", i);
1795 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_RAM);
1796 if (no_mask && state->mirrors_mapped)
1797 list->flags |= LIGHTREC_NO_MASK;
1800 pr_debug("Flaging opcode %u as BIOS access\n", i);
1801 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_BIOS);
1803 list->flags |= LIGHTREC_NO_MASK;
1805 case PSX_MAP_SCRATCH_PAD:
1806 pr_debug("Flaging opcode %u as scratchpad access\n", i);
1807 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_SCRATCH);
1809 list->flags |= LIGHTREC_NO_MASK;
1811 /* Consider that we're never going to run code from
1812 * the scratchpad. */
1813 list->flags |= LIGHTREC_NO_INVALIDATE;
1815 case PSX_MAP_HW_REGISTERS:
1816 if (state->ops.hw_direct &&
1817 state->ops.hw_direct(kunseg_val,
1818 opcode_is_store(list->c),
1819 opcode_get_io_size(list->c))) {
1820 pr_debug("Flagging opcode %u as direct I/O access\n",
1822 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_DIRECT_HW);
1825 list->flags |= LIGHTREC_NO_MASK;
1827 pr_debug("Flagging opcode %u as I/O access\n",
1829 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_HW);
1837 if (!LIGHTREC_FLAGS_GET_IO_MODE(list->flags)
1838 && list->i.rs >= 28 && list->i.rs <= 29
1839 && !state->maps[PSX_MAP_KERNEL_USER_RAM].ops) {
1840 /* Assume that all I/O operations that target
1841 * $sp or $gp will always only target a mapped
1842 * memory (RAM, BIOS, scratchpad). */
1843 if (state->opt_flags & LIGHTREC_OPT_SP_GP_HIT_RAM)
1844 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_RAM);
1846 list->flags |= LIGHTREC_IO_MODE(LIGHTREC_IO_DIRECT);
1858 static u8 get_mfhi_mflo_reg(const struct block *block, u16 offset,
1859 const struct opcode *last,
1860 u32 mask, bool sync, bool mflo, bool another)
1862 const struct opcode *op, *next = &block->opcode_list[offset];
1864 u8 reg2, reg = mflo ? REG_LO : REG_HI;
1868 for (i = offset; i < block->nb_ops; i++) {
1870 next = &block->opcode_list[i + 1];
1873 /* If any other opcode writes or reads to the register
1874 * we'd use, then we cannot use it anymore. */
1875 mask |= opcode_read_mask(op->c);
1876 mask |= opcode_write_mask(op->c);
1878 if (op_flag_sync(op->flags))
1887 /* TODO: handle backwards branches too */
1888 if (!last && op_flag_local_branch(op->flags) &&
1889 (s16)op->c.i.imm >= 0) {
1890 branch_offset = i + 1 + (s16)op->c.i.imm
1891 - !!op_flag_no_ds(op->flags);
1893 reg = get_mfhi_mflo_reg(block, branch_offset, NULL,
1894 mask, sync, mflo, false);
1895 reg2 = get_mfhi_mflo_reg(block, offset + 1, next,
1896 mask, sync, mflo, false);
1897 if (reg > 0 && reg == reg2)
1903 return mflo ? REG_LO : REG_HI;
1905 case OP_META_MULTU2:
1909 case OP_SPECIAL_MULT:
1910 case OP_SPECIAL_MULTU:
1911 case OP_SPECIAL_DIV:
1912 case OP_SPECIAL_DIVU:
1914 case OP_SPECIAL_MTHI:
1918 case OP_SPECIAL_MTLO:
1926 if (!sync && !op_flag_no_ds(op->flags) &&
1927 (next->i.op == OP_SPECIAL) &&
1928 ((!mflo && next->r.op == OP_SPECIAL_MFHI) ||
1929 (mflo && next->r.op == OP_SPECIAL_MFLO)))
1933 case OP_SPECIAL_JALR:
1935 case OP_SPECIAL_MFHI:
1939 /* Must use REG_HI if there is another MFHI target*/
1940 reg2 = get_mfhi_mflo_reg(block, i + 1, next,
1941 0, sync, mflo, true);
1942 if (reg2 > 0 && reg2 != REG_HI)
1945 if (!sync && !(old_mask & BIT(op->r.rd)))
1951 case OP_SPECIAL_MFLO:
1955 /* Must use REG_LO if there is another MFLO target*/
1956 reg2 = get_mfhi_mflo_reg(block, i + 1, next,
1957 0, sync, mflo, true);
1958 if (reg2 > 0 && reg2 != REG_LO)
1961 if (!sync && !(old_mask & BIT(op->r.rd)))
1980 static void lightrec_replace_lo_hi(struct block *block, u16 offset,
1986 /* This function will remove the following MFLO/MFHI. It must be called
1987 * only if get_mfhi_mflo_reg() returned a non-zero value. */
1989 for (i = offset; i < last; i++) {
1990 struct opcode *op = &block->opcode_list[i];
1998 /* TODO: handle backwards branches too */
1999 if (op_flag_local_branch(op->flags) && (s16)op->c.i.imm >= 0) {
2000 branch_offset = i + 1 + (s16)op->c.i.imm
2001 - !!op_flag_no_ds(op->flags);
2003 lightrec_replace_lo_hi(block, branch_offset, last, lo);
2004 lightrec_replace_lo_hi(block, i + 1, branch_offset, lo);
2009 if (lo && op->r.op == OP_SPECIAL_MFLO) {
2010 pr_debug("Removing MFLO opcode at offset 0x%x\n",
2014 } else if (!lo && op->r.op == OP_SPECIAL_MFHI) {
2015 pr_debug("Removing MFHI opcode at offset 0x%x\n",
2028 static bool lightrec_always_skip_div_check(void)
2037 static int lightrec_flag_mults_divs(struct lightrec_state *state, struct block *block)
2039 struct opcode *list = NULL;
2040 struct constprop_data v[32] = LIGHTREC_CONSTPROP_INITIALIZER;
2044 for (i = 0; i < block->nb_ops - 1; i++) {
2045 list = &block->opcode_list[i];
2047 lightrec_consts_propagate(block, i, v);
2049 switch (list->i.op) {
2051 switch (list->r.op) {
2052 case OP_SPECIAL_DIV:
2053 case OP_SPECIAL_DIVU:
2054 /* If we are dividing by a non-zero constant, don't
2055 * emit the div-by-zero check. */
2056 if (lightrec_always_skip_div_check() ||
2057 (v[list->r.rt].known & v[list->r.rt].value)) {
2058 list->flags |= LIGHTREC_NO_DIV_CHECK;
2061 case OP_SPECIAL_MULT:
2062 case OP_SPECIAL_MULTU:
2069 case OP_META_MULTU2:
2075 /* Don't support opcodes in delay slots */
2076 if (is_delay_slot(block->opcode_list, i) ||
2077 op_flag_no_ds(list->flags)) {
2081 reg_lo = get_mfhi_mflo_reg(block, i + 1, NULL, 0, false, true, false);
2083 pr_debug("Mark MULT(U)/DIV(U) opcode at offset 0x%x as"
2084 " not writing LO\n", i << 2);
2085 list->flags |= LIGHTREC_NO_LO;
2088 reg_hi = get_mfhi_mflo_reg(block, i + 1, NULL, 0, false, false, false);
2090 pr_debug("Mark MULT(U)/DIV(U) opcode at offset 0x%x as"
2091 " not writing HI\n", i << 2);
2092 list->flags |= LIGHTREC_NO_HI;
2095 if (!reg_lo && !reg_hi) {
2096 pr_debug("Both LO/HI unused in this block, they will "
2097 "probably be used in parent block - removing "
2099 list->flags &= ~(LIGHTREC_NO_LO | LIGHTREC_NO_HI);
2102 if (reg_lo > 0 && reg_lo != REG_LO) {
2103 pr_debug("Found register %s to hold LO (rs = %u, rt = %u)\n",
2104 lightrec_reg_name(reg_lo), list->r.rs, list->r.rt);
2106 lightrec_replace_lo_hi(block, i + 1, block->nb_ops, true);
2107 list->r.rd = reg_lo;
2112 if (reg_hi > 0 && reg_hi != REG_HI) {
2113 pr_debug("Found register %s to hold HI (rs = %u, rt = %u)\n",
2114 lightrec_reg_name(reg_hi), list->r.rs, list->r.rt);
2116 lightrec_replace_lo_hi(block, i + 1, block->nb_ops, false);
2117 list->r.imm = reg_hi;
2126 static bool remove_div_sequence(struct block *block, unsigned int offset)
2129 unsigned int i, found = 0;
2132 * Scan for the zero-checking sequence that GCC automatically introduced
2133 * after most DIV/DIVU opcodes. This sequence checks the value of the
2134 * divisor, and if zero, executes a BREAK opcode, causing the BIOS
2135 * handler to crash the PS1.
2137 * For DIV opcodes, this sequence additionally checks that the signed
2138 * operation does not overflow.
2140 * With the assumption that the games never crashed the PS1, we can
2141 * therefore assume that the games never divided by zero or overflowed,
2142 * and these sequences can be removed.
2145 for (i = offset; i < block->nb_ops; i++) {
2146 op = &block->opcode_list[i];
2149 if (op->i.op == OP_SPECIAL &&
2150 (op->r.op == OP_SPECIAL_DIV || op->r.op == OP_SPECIAL_DIVU))
2153 if ((op->opcode & 0xfc1fffff) == 0x14000002) {
2154 /* BNE ???, zero, +8 */
2159 } else if (found == 1 && !op->opcode) {
2162 } else if (found == 2 && op->opcode == 0x0007000d) {
2165 } else if (found == 3 && op->opcode == 0x2401ffff) {
2168 } else if (found == 4 && (op->opcode & 0xfc1fffff) == 0x14010004) {
2169 /* BNE ???, at, +16 */
2171 } else if (found == 5 && op->opcode == 0x3c018000) {
2172 /* LUI at, 0x8000 */
2174 } else if (found == 6 && (op->opcode & 0x141fffff) == 0x14010002) {
2175 /* BNE ???, at, +16 */
2177 } else if (found == 7 && !op->opcode) {
2180 } else if (found == 8 && op->opcode == 0x0006000d) {
2193 pr_debug("Removing DIV%s sequence at offset 0x%x\n",
2194 found == 9 ? "" : "U", offset << 2);
2196 for (i = 0; i < found; i++)
2197 block->opcode_list[offset + i].opcode = 0;
2205 static int lightrec_remove_div_by_zero_check_sequence(struct lightrec_state *state,
2206 struct block *block)
2211 for (i = 0; i < block->nb_ops; i++) {
2212 op = &block->opcode_list[i];
2214 if (op->i.op == OP_SPECIAL &&
2215 (op->r.op == OP_SPECIAL_DIVU || op->r.op == OP_SPECIAL_DIV) &&
2216 remove_div_sequence(block, i + 1))
2217 op->flags |= LIGHTREC_NO_DIV_CHECK;
2223 static const u32 memset_code[] = {
2224 0x10a00006, // beqz a1, 2f
2225 0x24a2ffff, // addiu v0,a1,-1
2226 0x2403ffff, // li v1,-1
2227 0xac800000, // 1: sw zero,0(a0)
2228 0x2442ffff, // addiu v0,v0,-1
2229 0x1443fffd, // bne v0,v1, 1b
2230 0x24840004, // addiu a0,a0,4
2231 0x03e00008, // 2: jr ra
2235 static int lightrec_replace_memset(struct lightrec_state *state, struct block *block)
2240 for (i = 0; i < block->nb_ops; i++) {
2241 c = block->opcode_list[i].c;
2243 if (c.opcode != memset_code[i])
2246 if (i == ARRAY_SIZE(memset_code) - 1) {
2248 pr_debug("Block at PC 0x%x is a memset\n", block->pc);
2249 block_set_flags(block,
2250 BLOCK_IS_MEMSET | BLOCK_NEVER_COMPILE);
2252 /* Return non-zero to skip other optimizers. */
2260 static int lightrec_test_preload_pc(struct lightrec_state *state, struct block *block)
2266 for (i = 0; i < block->nb_ops; i++) {
2267 c = block->opcode_list[i].c;
2268 flags = block->opcode_list[i].flags;
2270 if (op_flag_sync(flags))
2276 block->flags |= BLOCK_PRELOAD_PC;
2281 case OP_REGIMM_BLTZAL:
2282 case OP_REGIMM_BGEZAL:
2283 block->flags |= BLOCK_PRELOAD_PC;
2293 if (!op_flag_local_branch(flags)) {
2294 block->flags |= BLOCK_PRELOAD_PC;
2300 case OP_SPECIAL_JALR:
2302 block->flags |= BLOCK_PRELOAD_PC;
2306 case OP_SPECIAL_SYSCALL:
2307 case OP_SPECIAL_BREAK:
2308 block->flags |= BLOCK_PRELOAD_PC;
2320 static int (*lightrec_optimizers[])(struct lightrec_state *state, struct block *) = {
2321 IF_OPT(OPT_REMOVE_DIV_BY_ZERO_SEQ, &lightrec_remove_div_by_zero_check_sequence),
2322 IF_OPT(OPT_REPLACE_MEMSET, &lightrec_replace_memset),
2323 IF_OPT(OPT_DETECT_IMPOSSIBLE_BRANCHES, &lightrec_detect_impossible_branches),
2324 IF_OPT(OPT_HANDLE_LOAD_DELAYS, &lightrec_handle_load_delays),
2325 IF_OPT(OPT_HANDLE_LOAD_DELAYS, &lightrec_swap_load_delays),
2326 IF_OPT(OPT_TRANSFORM_OPS, &lightrec_transform_branches),
2327 IF_OPT(OPT_LOCAL_BRANCHES, &lightrec_local_branches),
2328 IF_OPT(OPT_TRANSFORM_OPS, &lightrec_transform_ops),
2329 IF_OPT(OPT_SWITCH_DELAY_SLOTS, &lightrec_switch_delay_slots),
2330 IF_OPT(OPT_FLAG_IO, &lightrec_flag_io),
2331 IF_OPT(OPT_FLAG_MULT_DIV, &lightrec_flag_mults_divs),
2332 IF_OPT(OPT_EARLY_UNLOAD, &lightrec_early_unload),
2333 IF_OPT(OPT_PRELOAD_PC, &lightrec_test_preload_pc),
2336 int lightrec_optimize(struct lightrec_state *state, struct block *block)
2341 for (i = 0; i < ARRAY_SIZE(lightrec_optimizers); i++) {
2342 if (lightrec_optimizers[i]) {
2343 ret = (*lightrec_optimizers[i])(state, block);