1 // Basic macros to emit ARM instructions and some utils
3 // (c) Copyright 2008-2009, Grazvydas "notaz" Ignotas
4 // Free for non-commercial use.
8 // XXX: tcache_ptr type for SVP and SH2 compilers differs..
9 #define EMIT_PTR(ptr, x) \
12 ptr = (void *)((u8 *)ptr + sizeof(u32)); \
16 #define EMIT(x) EMIT_PTR(tcache_ptr, x)
18 #define A_R4M (1 << 4)
19 #define A_R5M (1 << 5)
20 #define A_R6M (1 << 6)
21 #define A_R7M (1 << 7)
22 #define A_R8M (1 << 8)
23 #define A_R9M (1 << 9)
24 #define A_R10M (1 << 10)
25 #define A_R11M (1 << 11)
26 #define A_R14M (1 << 14)
43 #define A_COND_CS A_COND_HS
44 #define A_COND_CC A_COND_LO
46 /* unified conditions */
47 #define DCOND_EQ A_COND_EQ
48 #define DCOND_NE A_COND_NE
49 #define DCOND_MI A_COND_MI
50 #define DCOND_PL A_COND_PL
51 #define DCOND_HI A_COND_HI
52 #define DCOND_HS A_COND_HS
53 #define DCOND_LO A_COND_LO
54 #define DCOND_GE A_COND_GE
55 #define DCOND_GT A_COND_GT
56 #define DCOND_LT A_COND_LT
57 #define DCOND_LS A_COND_LS
58 #define DCOND_LE A_COND_LE
59 #define DCOND_VS A_COND_VS
60 #define DCOND_VC A_COND_VC
62 /* addressing mode 1 */
68 #define A_AM1_IMM(ror2,imm8) (((ror2)<<8) | (imm8) | 0x02000000)
69 #define A_AM1_REG_XIMM(shift_imm,shift_op,rm) (((shift_imm)<<7) | ((shift_op)<<5) | (rm))
70 #define A_AM1_REG_XREG(rs,shift_op,rm) (((rs)<<8) | ((shift_op)<<5) | 0x10 | (rm))
72 /* data processing op */
89 #define EOP_C_DOP_X(cond,op,s,rn,rd,shifter_op) \
90 EMIT(((cond)<<28) | ((op)<< 21) | ((s)<<20) | ((rn)<<16) | ((rd)<<12) | (shifter_op))
92 #define EOP_C_DOP_IMM( cond,op,s,rn,rd,ror2,imm8) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_IMM(ror2,imm8))
93 #define EOP_C_DOP_REG_XIMM(cond,op,s,rn,rd,shift_imm,shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XIMM(shift_imm,shift_op,rm))
94 #define EOP_C_DOP_REG_XREG(cond,op,s,rn,rd,rs, shift_op,rm) EOP_C_DOP_X(cond,op,s,rn,rd,A_AM1_REG_XREG(rs, shift_op,rm))
96 #define EOP_MOV_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,0, 0,rd,ror2,imm8)
97 #define EOP_MVN_IMM(rd, ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_MVN,0, 0,rd,ror2,imm8)
98 #define EOP_ORR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ORR,0,rn,rd,ror2,imm8)
99 #define EOP_EOR_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_EOR,0,rn,rd,ror2,imm8)
100 #define EOP_ADD_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_ADD,0,rn,rd,ror2,imm8)
101 #define EOP_BIC_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_BIC,0,rn,rd,ror2,imm8)
102 #define EOP_AND_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,0,rn,rd,ror2,imm8)
103 #define EOP_SUB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_SUB,0,rn,rd,ror2,imm8)
104 #define EOP_TST_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_TST,1,rn, 0,ror2,imm8)
105 #define EOP_CMP_IMM( rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_CMP,1,rn, 0,ror2,imm8)
106 #define EOP_RSB_IMM(rd,rn,ror2,imm8) EOP_C_DOP_IMM(A_COND_AL,A_OP_RSB,0,rn,rd,ror2,imm8)
108 #define EOP_MOV_IMM_C(cond,rd, ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_MOV,0, 0,rd,ror2,imm8)
109 #define EOP_ORR_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_ORR,0,rn,rd,ror2,imm8)
110 #define EOP_RSB_IMM_C(cond,rd,rn,ror2,imm8) EOP_C_DOP_IMM(cond,A_OP_RSB,0,rn,rd,ror2,imm8)
112 #define EOP_MOV_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MOV,s, 0,rd,shift_imm,shift_op,rm)
113 #define EOP_MVN_REG(cond,s,rd, rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_MVN,s, 0,rd,shift_imm,shift_op,rm)
114 #define EOP_ORR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ORR,s,rn,rd,shift_imm,shift_op,rm)
115 #define EOP_ADD_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADD,s,rn,rd,shift_imm,shift_op,rm)
116 #define EOP_ADC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_ADC,s,rn,rd,shift_imm,shift_op,rm)
117 #define EOP_SUB_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SUB,s,rn,rd,shift_imm,shift_op,rm)
118 #define EOP_SBC_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_SBC,s,rn,rd,shift_imm,shift_op,rm)
119 #define EOP_AND_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_AND,s,rn,rd,shift_imm,shift_op,rm)
120 #define EOP_EOR_REG(cond,s,rd,rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_EOR,s,rn,rd,shift_imm,shift_op,rm)
121 #define EOP_CMP_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_CMP,1,rn, 0,shift_imm,shift_op,rm)
122 #define EOP_TST_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TST,1,rn, 0,shift_imm,shift_op,rm)
123 #define EOP_TEQ_REG(cond, rn,rm,shift_op,shift_imm) EOP_C_DOP_REG_XIMM(cond,A_OP_TEQ,1,rn, 0,shift_imm,shift_op,rm)
125 #define EOP_MOV_REG2(s,rd, rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_MOV,s, 0,rd,rs,shift_op,rm)
126 #define EOP_ADD_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_ADD,s,rn,rd,rs,shift_op,rm)
127 #define EOP_SUB_REG2(s,rd,rn,rm,shift_op,rs) EOP_C_DOP_REG_XREG(A_COND_AL,A_OP_SUB,s,rn,rd,rs,shift_op,rm)
129 #define EOP_MOV_REG_SIMPLE(rd,rm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,0)
130 #define EOP_MOV_REG_LSL(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSL,shift_imm)
131 #define EOP_MOV_REG_LSR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_LSR,shift_imm)
132 #define EOP_MOV_REG_ASR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ASR,shift_imm)
133 #define EOP_MOV_REG_ROR(rd, rm,shift_imm) EOP_MOV_REG(A_COND_AL,0,rd,rm,A_AM1_ROR,shift_imm)
135 #define EOP_ORR_REG_SIMPLE(rd,rm) EOP_ORR_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
136 #define EOP_ORR_REG_LSL(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
137 #define EOP_ORR_REG_LSR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
138 #define EOP_ORR_REG_ASR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ASR,shift_imm)
139 #define EOP_ORR_REG_ROR(rd,rn,rm,shift_imm) EOP_ORR_REG(A_COND_AL,0,rd,rn,rm,A_AM1_ROR,shift_imm)
141 #define EOP_ADD_REG_SIMPLE(rd,rm) EOP_ADD_REG(A_COND_AL,0,rd,rd,rm,A_AM1_LSL,0)
142 #define EOP_ADD_REG_LSL(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSL,shift_imm)
143 #define EOP_ADD_REG_LSR(rd,rn,rm,shift_imm) EOP_ADD_REG(A_COND_AL,0,rd,rn,rm,A_AM1_LSR,shift_imm)
145 #define EOP_TST_REG_SIMPLE(rn,rm) EOP_TST_REG(A_COND_AL, rn, 0,A_AM1_LSL,rm)
147 #define EOP_MOV_REG2_LSL(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_LSL,rs)
148 #define EOP_MOV_REG2_ROR(rd, rm,rs) EOP_MOV_REG2(0,rd, rm,A_AM1_ROR,rs)
149 #define EOP_ADD_REG2_LSL(rd,rn,rm,rs) EOP_ADD_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
150 #define EOP_SUB_REG2_LSL(rd,rn,rm,rs) EOP_SUB_REG2(0,rd,rn,rm,A_AM1_LSL,rs)
152 /* addressing mode 2 */
153 #define EOP_C_AM2_IMM(cond,u,b,l,rn,rd,offset_12) \
154 EMIT(((cond)<<28) | 0x05000000 | ((u)<<23) | ((b)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | (offset_12))
156 /* addressing mode 3 */
157 #define EOP_C_AM3(cond,u,r,l,rn,rd,s,h,immed_reg) \
158 EMIT(((cond)<<28) | 0x01000090 | ((u)<<23) | ((r)<<22) | ((l)<<20) | ((rn)<<16) | ((rd)<<12) | \
159 ((s)<<6) | ((h)<<5) | (immed_reg))
161 #define EOP_C_AM3_IMM(cond,u,l,rn,rd,s,h,offset_8) EOP_C_AM3(cond,u,1,l,rn,rd,s,h,(((offset_8)&0xf0)<<4)|((offset_8)&0xf))
163 #define EOP_C_AM3_REG(cond,u,l,rn,rd,s,h,rm) EOP_C_AM3(cond,u,0,l,rn,rd,s,h,rm)
166 #define EOP_LDR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,offset_12)
167 #define EOP_LDR_NEGIMM(rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,0,0,1,rn,rd,offset_12)
168 #define EOP_LDR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,1,rn,rd,0)
169 #define EOP_STR_IMM( rd,rn,offset_12) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,offset_12)
170 #define EOP_STR_SIMPLE(rd,rn) EOP_C_AM2_IMM(A_COND_AL,1,0,0,rn,rd,0)
172 #define EOP_LDRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,offset_8)
173 #define EOP_LDRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,1,rn,rd,0,1,0)
174 #define EOP_LDRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,1,rn,rd,0,1,rm)
175 #define EOP_STRH_IMM( rd,rn,offset_8) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,offset_8)
176 #define EOP_STRH_SIMPLE(rd,rn) EOP_C_AM3_IMM(A_COND_AL,1,0,rn,rd,0,1,0)
177 #define EOP_STRH_REG( rd,rn,rm) EOP_C_AM3_REG(A_COND_AL,1,0,rn,rd,0,1,rm)
180 #define EOP_XXM(cond,p,u,s,w,l,rn,list) \
181 EMIT(((cond)<<28) | (1<<27) | ((p)<<24) | ((u)<<23) | ((s)<<22) | ((w)<<21) | ((l)<<20) | ((rn)<<16) | (list))
183 #define EOP_STMFD_ST(list) EOP_XXM(A_COND_AL,1,0,0,1,0,13,list)
184 #define EOP_LDMFD_ST(list) EOP_XXM(A_COND_AL,0,1,0,1,1,13,list)
187 #define EOP_C_BX(cond,rm) \
188 EMIT(((cond)<<28) | 0x012fff10 | (rm))
190 #define EOP_BX(rm) EOP_C_BX(A_COND_AL,rm)
192 #define EOP_C_B_PTR(ptr,cond,l,signed_immed_24) \
193 EMIT_PTR(ptr, ((cond)<<28) | 0x0a000000 | ((l)<<24) | (signed_immed_24))
195 #define EOP_C_B(cond,l,signed_immed_24) \
196 EOP_C_B_PTR(tcache_ptr,cond,l,signed_immed_24)
198 #define EOP_B( signed_immed_24) EOP_C_B(A_COND_AL,0,signed_immed_24)
199 #define EOP_BL(signed_immed_24) EOP_C_B(A_COND_AL,1,signed_immed_24)
202 #define EOP_C_MUL(cond,s,rd,rs,rm) \
203 EMIT(((cond)<<28) | ((s)<<20) | ((rd)<<16) | ((rs)<<8) | 0x90 | (rm))
205 #define EOP_C_UMULL(cond,s,rdhi,rdlo,rs,rm) \
206 EMIT(((cond)<<28) | 0x00800000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
208 #define EOP_C_SMULL(cond,s,rdhi,rdlo,rs,rm) \
209 EMIT(((cond)<<28) | 0x00c00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
211 #define EOP_C_SMLAL(cond,s,rdhi,rdlo,rs,rm) \
212 EMIT(((cond)<<28) | 0x00e00000 | ((s)<<20) | ((rdhi)<<16) | ((rdlo)<<12) | ((rs)<<8) | 0x90 | (rm))
214 #define EOP_MUL(rd,rm,rs) EOP_C_MUL(A_COND_AL,0,rd,rs,rm) // note: rd != rm
216 #define EOP_C_MRS(cond,rd) \
217 EMIT(((cond)<<28) | 0x010f0000 | ((rd)<<12))
219 #define EOP_C_MSR_IMM(cond,ror2,imm) \
220 EMIT(((cond)<<28) | 0x0328f000 | ((ror2)<<8) | (imm)) // cpsr_f
222 #define EOP_C_MSR_REG(cond,rm) \
223 EMIT(((cond)<<28) | 0x0128f000 | (rm)) // cpsr_f
225 #define EOP_MRS(rd) EOP_C_MRS(A_COND_AL,rd)
226 #define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
227 #define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)
230 static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int imm)
240 for (v = imm, ror2 = 0; v != 0 || op == A_OP_MOV; v >>= 8, ror2 -= 8/2) {
241 /* shift down to get 'best' rot2 */
242 for (; v && !(v & 3); v >>= 2)
245 EOP_C_DOP_IMM(cond, op, s, rn, rd, ror2 & 0x0f, v & 0xff);
247 if (op == A_OP_MOV) {
254 #define emith_op_imm(cond, s, op, r, imm) \
255 emith_op_imm2(cond, s, op, r, r, imm)
258 #define emith_top_imm(cond, op, r, imm) { \
260 for (ror2 = 0, v = imm; v && !(v & 3); v >>= 2) \
262 EOP_C_DOP_IMM(cond, op, 1, r, 0, ror2 & 0x0f, v & 0xff); \
265 #define is_offset_24(val) \
266 ((val) >= (int)0xff000000 && (val) <= 0x00ffffff)
268 static int emith_xbranch(int cond, void *target, int is_call)
270 int val = (u32 *)target - (u32 *)tcache_ptr - 2;
271 int direct = is_offset_24(val);
272 u32 *start_ptr = (u32 *)tcache_ptr;
276 EOP_C_B(cond,is_call,val & 0xffffff); // b, bl target
281 // elprintf(EL_SVP, "emitting indirect jmp %08x->%08x", tcache_ptr, target);
283 EOP_ADD_IMM(14,15,0,8); // add lr,pc,#8
284 EOP_C_AM2_IMM(cond,1,0,1,15,15,0); // ldrcc pc,[pc]
285 EOP_MOV_REG_SIMPLE(15,15); // mov pc, pc
288 // should never happen
289 elprintf(EL_STATUS|EL_SVP|EL_ANOMALY, "indirect jmp %08x->%08x", target, tcache_ptr);
294 return (u32 *)tcache_ptr - start_ptr;
298 // fake "simple" or "short" jump - using cond insns instead
299 #define EMITH_SJMP_START(cond) \
302 #define EMITH_SJMP_END(cond) \
305 #define emith_move_r_r(d, s) \
306 EOP_MOV_REG_SIMPLE(d, s)
308 #define emith_mvn_r_r(d, s) \
309 EOP_MVN_REG(A_COND_AL,0,d,s,A_AM1_LSL,0)
311 #define emith_or_r_r_r_lsl(d, s1, s2, lslimm) \
312 EOP_ORR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
314 #define emith_eor_r_r_r_lsl(d, s1, s2, lslimm) \
315 EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSL,lslimm)
317 #define emith_eor_r_r_r_lsr(d, s1, s2, lsrimm) \
318 EOP_EOR_REG(A_COND_AL,0,d,s1,s2,A_AM1_LSR,lsrimm)
320 #define emith_or_r_r_lsl(d, s, lslimm) \
321 emith_or_r_r_r_lsl(d, d, s, lslimm)
323 #define emith_eor_r_r_lsr(d, s, lsrimm) \
324 emith_eor_r_r_r_lsr(d, d, s, lsrimm)
326 #define emith_or_r_r_r(d, s1, s2) \
327 emith_or_r_r_r_lsl(d, s1, s2, 0)
329 #define emith_eor_r_r_r(d, s1, s2) \
330 emith_eor_r_r_r_lsl(d, s1, s2, 0)
332 #define emith_add_r_r(d, s) \
333 EOP_ADD_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
335 #define emith_sub_r_r(d, s) \
336 EOP_SUB_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
338 #define emith_and_r_r(d, s) \
339 EOP_AND_REG(A_COND_AL,0,d,d,s,A_AM1_LSL,0)
341 #define emith_or_r_r(d, s) \
342 emith_or_r_r_r(d, d, s)
344 #define emith_eor_r_r(d, s) \
345 emith_eor_r_r_r(d, d, s)
347 #define emith_tst_r_r(d, s) \
348 EOP_TST_REG(A_COND_AL,d,s,A_AM1_LSL,0)
350 #define emith_teq_r_r(d, s) \
351 EOP_TEQ_REG(A_COND_AL,d,s,A_AM1_LSL,0)
353 #define emith_cmp_r_r(d, s) \
354 EOP_CMP_REG(A_COND_AL,d,s,A_AM1_LSL,0)
356 #define emith_addf_r_r(d, s) \
357 EOP_ADD_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
359 #define emith_subf_r_r(d, s) \
360 EOP_SUB_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
362 #define emith_adcf_r_r(d, s) \
363 EOP_ADC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
365 #define emith_sbcf_r_r(d, s) \
366 EOP_SBC_REG(A_COND_AL,1,d,d,s,A_AM1_LSL,0)
368 #define emith_move_r_imm(r, imm) \
369 emith_op_imm(A_COND_AL, 0, A_OP_MOV, r, imm)
371 #define emith_add_r_imm(r, imm) \
372 emith_op_imm(A_COND_AL, 0, A_OP_ADD, r, imm)
374 #define emith_sub_r_imm(r, imm) \
375 emith_op_imm(A_COND_AL, 0, A_OP_SUB, r, imm)
377 #define emith_bic_r_imm(r, imm) \
378 emith_op_imm(A_COND_AL, 0, A_OP_BIC, r, imm)
380 #define emith_and_r_imm(r, imm) \
381 emith_op_imm(A_COND_AL, 0, A_OP_AND, r, imm)
383 #define emith_or_r_imm(r, imm) \
384 emith_op_imm(A_COND_AL, 0, A_OP_ORR, r, imm)
386 #define emith_eor_r_imm(r, imm) \
387 emith_op_imm(A_COND_AL, 0, A_OP_EOR, r, imm)
389 // note: only use 8bit imm for these
390 #define emith_tst_r_imm(r, imm) \
391 emith_top_imm(A_COND_AL, A_OP_TST, r, imm)
393 #define emith_cmp_r_imm(r, imm) \
394 emith_top_imm(A_COND_AL, A_OP_CMP, r, imm)
396 #define emith_subf_r_imm(r, imm) \
397 emith_op_imm(A_COND_AL, 1, A_OP_SUB, r, imm)
399 #define emith_add_r_imm_c(cond, r, imm) \
400 emith_op_imm(cond, 0, A_OP_ADD, r, imm)
402 #define emith_sub_r_imm_c(cond, r, imm) \
403 emith_op_imm(cond, 0, A_OP_SUB, r, imm)
405 #define emith_or_r_imm_c(cond, r, imm) \
406 emith_op_imm(cond, 0, A_OP_ORR, r, imm)
408 #define emith_eor_r_imm_c(cond, r, imm) \
409 emith_op_imm(cond, 0, A_OP_EOR, r, imm)
411 #define emith_bic_r_imm_c(cond, r, imm) \
412 emith_op_imm(cond, 0, A_OP_BIC, r, imm)
414 #define emith_move_r_imm_s8(r, imm) { \
416 EOP_MVN_IMM(r, 0, ((imm) ^ 0xff)); \
418 EOP_MOV_IMM(r, 0, imm); \
421 #define emith_and_r_r_imm(d, s, imm) \
422 emith_op_imm2(A_COND_AL, 0, A_OP_AND, d, s, imm)
424 #define emith_neg_r_r(d, s) \
425 EOP_RSB_IMM(d, s, 0, 0)
427 #define emith_lsl(d, s, cnt) \
428 EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSL,cnt)
430 #define emith_lsr(d, s, cnt) \
431 EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_LSR,cnt)
433 #define emith_ror(d, s, cnt) \
434 EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,cnt)
436 #define emith_rol(d, s, cnt) \
437 EOP_MOV_REG(A_COND_AL,0,d,s,A_AM1_ROR,32-(cnt)); \
439 #define emith_lslf(d, s, cnt) \
440 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSL,cnt)
442 #define emith_lsrf(d, s, cnt) \
443 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_LSR,cnt)
445 #define emith_asrf(d, s, cnt) \
446 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ASR,cnt)
448 // note: only C flag updated correctly
449 #define emith_rolf(d, s, cnt) { \
450 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,32-(cnt)); \
451 /* we don't have ROL so we shift to get the right carry */ \
452 EOP_TST_REG(A_COND_AL,d,d,A_AM1_LSR,1); \
455 #define emith_rorf(d, s, cnt) \
456 EOP_MOV_REG(A_COND_AL,1,d,s,A_AM1_ROR,cnt)
458 #define emith_rolcf(d) \
461 #define emith_rorcf(d) \
462 EOP_MOV_REG(A_COND_AL,1,d,d,A_AM1_ROR,0) /* ROR #0 -> RRX */
464 #define emith_negcf_r_r(d, s) \
465 EOP_C_DOP_IMM(A_COND_AL,A_OP_RSC,1,s,d,0,0)
467 #define emith_mul(d, s1, s2) { \
468 if ((d) != (s1)) /* rd != rm limitation */ \
469 EOP_MUL(d, s1, s2); \
471 EOP_MUL(d, s2, s1); \
474 #define emith_mul_u64(dlo, dhi, s1, s2) \
475 EOP_C_UMULL(A_COND_AL,0,dhi,dlo,s1,s2)
477 #define emith_mul_s64(dlo, dhi, s1, s2) \
478 EOP_C_SMULL(A_COND_AL,0,dhi,dlo,s1,s2)
480 #define emith_mula_s64(dlo, dhi, s1, s2) \
481 EOP_C_SMLAL(A_COND_AL,0,dhi,dlo,s1,s2)
484 #define emith_ctx_read(r, offs) \
485 EOP_LDR_IMM(r, CONTEXT_REG, offs)
487 #define emith_ctx_write(r, offs) \
488 EOP_STR_IMM(r, CONTEXT_REG, offs)
490 #define emith_clear_msb_c(cond, d, s, count) { \
492 if ((count) <= 8) { \
494 t = (0xff << t) & 0xff; \
495 EOP_BIC_IMM(d,s,8/2,t); \
496 EOP_C_DOP_IMM(cond,A_OP_BIC,0,s,d,8/2,t); \
497 } else if ((count) >= 24) { \
500 EOP_AND_IMM(d,s,0,t); \
501 EOP_C_DOP_IMM(cond,A_OP_AND,0,s,d,0,t); \
503 EOP_MOV_REG(cond,0,d,s,A_AM1_LSL,count); \
504 EOP_MOV_REG(cond,0,d,d,A_AM1_LSR,count); \
508 #define emith_clear_msb(d, s, count) \
509 emith_clear_msb_c(A_COND_AL, d, s, count)
511 #define emith_sext(d, s, bits) { \
512 EOP_MOV_REG_LSL(d,s,32 - (bits)); \
513 EOP_MOV_REG_ASR(d,d,32 - (bits)); \
516 #define JMP_POS(ptr) \
518 tcache_ptr += sizeof(u32)
520 #define JMP_EMIT(cond, ptr) { \
521 int val = (u32 *)tcache_ptr - (u32 *)(ptr) - 2; \
522 EOP_C_B_PTR(ptr, cond, 0, val & 0xffffff); \
526 // put bit0 of r0 to carry
527 #define emith_set_carry(r0) \
528 EOP_TST_REG(A_COND_AL,r0,r0,A_AM1_LSR,1) /* shift out to carry */ \
530 // put bit0 of r0 to carry (for subtraction, inverted on ARM)
531 #define emith_set_carry_sub(r0) { \
532 int t = rcache_get_tmp(); \
533 EOP_EOR_IMM(t,r0,0,1); /* invert */ \
534 EOP_MOV_REG(A_COND_AL,1,t,t,A_AM1_LSR,1); /* shift out to carry */ \
535 rcache_free_tmp(t); \
538 #define host_arg2reg(rd, arg) \
542 #define emith_pass_arg_r(arg, reg) \
543 EOP_MOV_REG_SIMPLE(arg, reg)
545 #define emith_pass_arg_imm(arg, imm) \
546 emith_move_r_imm(arg, imm)
548 #define emith_call_cond(cond, target) \
549 emith_xbranch(cond, target, 1)
551 #define emith_jump_cond(cond, target) \
552 emith_xbranch(cond, target, 0)
554 #define emith_call(target) \
555 emith_call_cond(A_COND_AL, target)
557 #define emith_jump(target) \
558 emith_jump_cond(A_COND_AL, target)
560 /* SH2 drc specific */
561 #define emith_sh2_test_t() { \
562 int r = rcache_get_reg(SHR_SR, RC_GR_READ); \
563 EOP_TST_IMM(r, 0, 1); \
566 #define emith_sh2_dtbf_loop() { \
568 int tmp_ = rcache_get_tmp(); \
569 cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
570 rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW); \
571 emith_sub_r_imm(rn, 1); /* sub rn, #1 */ \
572 emith_bic_r_imm(cr, 1); /* bic cr, #1 */ \
573 emith_sub_r_imm(cr, (cycles+1) << 12); /* sub cr, #(cycles+1)<<12 */ \
575 emith_asrf(tmp_, cr, 2+12); /* movs tmp_, cr, asr #2+12 */\
576 EOP_MOV_IMM_C(A_COND_MI,tmp_,0,0); /* movmi tmp_, #0 */ \
577 emith_lsl(cr, cr, 20); /* mov cr, cr, lsl #20 */ \
578 emith_lsr(cr, cr, 20); /* mov cr, cr, lsr #20 */ \
579 emith_subf_r_r(rn, tmp_); /* subs rn, tmp_ */ \
580 EOP_RSB_IMM_C(A_COND_LS,tmp_,rn,0,0); /* rsbls tmp_, rn, #0 */ \
581 EOP_ORR_REG(A_COND_LS,0,cr,cr,tmp_,A_AM1_LSL,12+2); /* orrls cr,tmp_,lsl #12+2 */\
582 EOP_ORR_IMM_C(A_COND_LS,cr,cr,0,1); /* orrls cr, #1 */ \
583 EOP_MOV_IMM_C(A_COND_LS,rn,0,0); /* movls rn, #0 */ \
584 rcache_free_tmp(tmp_); \
587 #define emith_write_sr(srcr) { \
588 int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
589 emith_lsr(srr, srr, 12); \
590 emith_or_r_r_r_lsl(srr, srr, srcr, 20); \
591 emith_ror(srr, srr, 20); \
594 #define emith_carry_to_t(srr, is_sub) { \
595 if (is_sub) { /* has inverted C on ARM */ \
596 emith_or_r_imm_c(A_COND_CC, srr, 1); \
597 emith_bic_r_imm_c(A_COND_CS, srr, 1); \
599 emith_or_r_imm_c(A_COND_CS, srr, 1); \
600 emith_bic_r_imm_c(A_COND_CC, srr, 1); \
606 * t = carry(Rn += Rm)
608 * t = carry(Rn -= Rm)
611 #define emith_sh2_div1_step(rn, rm, sr) { \
613 emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
614 JMP_POS(jmp0); /* beq do_sub */ \
615 emith_addf_r_r(rn, rm); \
616 emith_eor_r_imm_c(A_COND_CS, sr, T); \
617 JMP_POS(jmp1); /* b done */ \
618 JMP_EMIT(A_COND_EQ, jmp0); /* do_sub: */ \
619 emith_subf_r_r(rn, rm); \
620 emith_eor_r_imm_c(A_COND_CC, sr, T); \
621 JMP_EMIT(A_COND_AL, jmp1); /* done: */ \