1 /* cpuctrl.c for GP2X (CPU/LCD/RAM-Tuner Version 2.0)
2 Copyright (C) 2006 god_at_hell
3 original CPU-Overclocker (c) by Hermes/PS2Reality
4 the gamma-routine was provided by theoddbot
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 /****************************************************************************************************************************************/
26 /****************************************************************************************************************************************/
31 #include "gp2xminilib.h"
33 #define SYS_CLK_FREQ 7372800
35 //from minimal library rlyeh
37 extern unsigned long gp2x_dev[4];
38 extern unsigned short *gp2x_memregs;
43 unsigned short SYSCLKENREG,SYSCSETREG,FPLLVSETREG,DUALINT920,DUALINT940,DUALCTRL940,DISPCSETREG,MEMTIMEX0;
44 unsigned short MEMTIMEX1,MEMREFX,MLC_GAMM_BYPATH,MLC_GAMMA_A,MLC_GAMMA_D,YBNKLVL;
48 volatile unsigned short *MEM_REG;
49 unsigned MDIV,PDIV,SCALE;
50 volatile unsigned *arm940code;
54 MEM_REG=&gp2x_memregs[0];
57 void save_system_regs()
59 system_reg.SYSCSETREG=MEM_REG[0x91c>>1];
60 system_reg.FPLLVSETREG=MEM_REG[0x912>>1];
61 system_reg.SYSCLKENREG=MEM_REG[0x904>>1];
62 system_reg.DUALINT920=MEM_REG[0x3B40>>1];
63 system_reg.DUALINT940=MEM_REG[0x3B42>>1];
64 system_reg.DUALCTRL940=MEM_REG[0x3B48>>1];
65 system_reg.DISPCSETREG=MEM_REG[0x924>>1];
66 system_reg.MEMTIMEX0=MEM_REG[0x3802>>1];
67 system_reg.MEMTIMEX1=MEM_REG[0x3804>>1];
68 system_reg.MEMREFX=MEM_REG[0x3808>>1];
69 system_reg.MLC_GAMM_BYPATH=MEM_REG[0x2880>>1];
70 system_reg.MLC_GAMMA_A=MEM_REG[0x295C>>1];
71 system_reg.MLC_GAMMA_D=MEM_REG[0x295E>>1];
72 system_reg.YBNKLVL=MEM_REG[0x283A>>1];
75 void load_system_regs()
77 MEM_REG[0x91c>>1]=system_reg.SYSCSETREG;
78 MEM_REG[0x910>>1]=system_reg.FPLLVSETREG;
79 MEM_REG[0x3B40>>1]=system_reg.DUALINT920;
80 MEM_REG[0x3B42>>1]=system_reg.DUALINT940;
81 MEM_REG[0x3B48>>1]=system_reg.DUALCTRL940;
82 MEM_REG[0x904>>1]=system_reg.SYSCLKENREG;
83 /* Set UPLLSETVREG to 0x4F02, which gives 80MHz */
84 MEM_REG[0x0914>>1] = 0x4F02;
85 /* Wait for clock change to start */
86 while (MEM_REG[0x0902>>1] & 2);
87 /* Wait for clock change to be verified */
88 while (MEM_REG[0x0916>>1] != 0x4F02);
89 MEM_REG[0x3802>>1]=system_reg.MEMTIMEX0;
90 MEM_REG[0x3804>>1]=system_reg.MEMTIMEX1;
91 MEM_REG[0x3808>>1]=system_reg.MEMREFX;
92 MEM_REG[0x2880>>1]=system_reg.MLC_GAMM_BYPATH;
93 MEM_REG[0x295C>>1]=system_reg.MLC_GAMMA_A;
94 MEM_REG[0x295E>>1]=system_reg.MLC_GAMMA_D;
95 MEM_REG[0x283A>>1]=system_reg.YBNKLVL;
99 void set_FCLK(unsigned MHZ)
101 printf ("set CPU-Frequency = %uMHz\r\n",MHZ);
103 unsigned mdiv,pdiv=3,scale=0;
105 mdiv=(MHZ*pdiv)/SYS_CLK_FREQ;
106 //printf ("Old value = %04X\r",MEM_REG[0x924>>1]," ");
107 //printf ("APLL = %04X\r",MEM_REG[0x91A>>1]," ");
108 mdiv=((mdiv-8)<<8) & 0xff00;
109 pdiv=((pdiv-2)<<2) & 0xfc;
111 v=mdiv | pdiv | scale;
117 return MEM_REG[0x910>>1];
120 void set_add_FLCDCLK(int addclock)
122 //Set LCD controller to use FPLL
123 printf ("...set to FPLL-Clockgen...\r\n");
124 printf ("set Timing-Prescaler = %i\r\n",addclock);
125 MEM_REG[0x924>>1]= 0x5A00 + ((addclock)<<8);
126 //If you change the initial timing, don't forget to shift your intervall-borders in "cpu_speed.c"
129 void set_add_ULCDCLK(int addclock)
131 //Set LCD controller to use UPLL
132 printf ("...set to UPLL-Clockgen...\r\n");
133 printf ("set Timing-Prescaler = %i\r\n",addclock);
134 MEM_REG[0x0924>>1] = 0x8900 + ((addclock)<<8);
135 //If you change the initial timing, don't forget to shift your intervall-borders in "cpu_speed.c"
138 unsigned get_LCDClk()
140 if (MEM_REG[0x0924>>1] < 0x7A01) return((MEM_REG[0x0924>>1] - 0x5A00)>>8);
141 else return((MEM_REG[0x0924>>1] - 0x8900)>>8);
146 if (MEM_REG[0x0924>>1] < 0x7A01) return(0);
150 unsigned get_freq_UCLK()
153 unsigned reg,mdiv,pdiv,scale;
154 i = MEM_REG[0x900>>1];
157 reg=MEM_REG[0x916>>1];
158 mdiv = ((reg & 0xff00) >> 8) + 8;
159 pdiv = ((reg & 0xfc) >> 2) + 2;
161 return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale));
164 unsigned get_freq_ACLK()
167 unsigned reg,mdiv,pdiv,scale;
168 i = MEM_REG[0x900>>1];
171 reg=MEM_REG[0x918>>1];
172 mdiv = ((reg & 0xff00) >> 8) + 8;
173 pdiv = ((reg & 0xfc) >> 2) + 2;
175 return ((SYS_CLK_FREQ * mdiv)/(pdiv << scale));
178 unsigned get_freq_920_CLK()
181 unsigned reg,mdiv,pdiv,scale;
182 reg=MEM_REG[0x912>>1];
183 mdiv = ((reg & 0xff00) >> 8) + 8;
184 pdiv = ((reg & 0xfc) >> 2) + 2;
189 i = (MEM_REG[0x91c>>1] & 7)+1;
190 return ((SYS_CLK_FREQ * mdiv)/(pdiv << scale))/i;
193 unsigned get_freq_940_CLK()
196 unsigned reg,mdiv,pdiv,scale;
197 reg=MEM_REG[0x912>>1];
198 mdiv = ((reg & 0xff00) >> 8) + 8;
199 pdiv = ((reg & 0xfc) >> 2) + 2;
201 i = ((MEM_REG[0x91c>>1]>>3) & 7)+1;
202 return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale))/i;
205 unsigned get_freq_DCLK()
208 unsigned reg,mdiv,pdiv,scale;
209 reg=MEM_REG[0x912>>1];
210 mdiv = ((reg & 0xff00) >> 8) + 8;
211 pdiv = ((reg & 0xfc) >> 2) + 2;
213 i = ((MEM_REG[0x91c>>1]>>6) & 7)+1;
214 return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale))/i;
217 void set_920_Div(unsigned short div)
219 printf ("set divider for CPU-Clock = %u\r\n",div+1);
221 v = MEM_REG[0x91c>>1] & (~0x3);
222 MEM_REG[0x91c>>1] = (div & 0x7) | v;
225 unsigned short get_920_Div()
227 return (MEM_REG[0x91c>>1] & 0x7);
230 void set_940_Div(unsigned short div)
233 v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 3)));
234 MEM_REG[0x91c>>1] = ((div & 0x7) << 3) | v;
237 unsigned short get_940_Div()
239 return ((MEM_REG[0x91c>>1] >> 3) & 0x7);
242 void set_DCLK_Div( unsigned short div )
244 printf ("set divider for RAM-Clock = %u\r\n",div+1);
246 v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 6)));
247 MEM_REG[0x91c>>1] = ((div & 0x7) << 6) | v;
250 unsigned short get_DCLK_Div()
252 return ((MEM_REG[0x91c>>1] >> 6) & 0x7);
255 unsigned short Disable_Int_920()
258 ret=MEM_REG[0x3B40>>1];
259 MEM_REG[0x3B40>>1]=0;
260 MEM_REG[0x3B44>>1]=0xffff;
264 unsigned short Disable_Int_940()
267 ret=MEM_REG[0x3B42>>1];
268 MEM_REG[0x3B42>>1]=0;
269 MEM_REG[0x3B46>>1]=0xffff;
273 unsigned get_state940()
275 return MEM_REG[0x904>>1];
279 void Enable_Int_920(unsigned short flag)
281 MEM_REG[0x3B40>>1]=flag;
284 void Enable_Int_940(unsigned short flag)
286 MEM_REG[0x3B42>>1]=flag;
292 MEM_REG[0x3B48>>1]|= (1 << 7);
293 MEM_REG[0x904>>1]&=0xfffe;
296 void Load_940_code(unsigned *code,int size)
300 arm940code=(unsigned short *)mmap(0, 0x100000, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_dev[2], 0x03000000);
302 cp=(unsigned *) code;
303 for (i = 0; i < size/4; i ++)
305 arm940code[i] = cp[i];
307 for (i = 0; i < 64; i ++)
309 arm940code[0x3FC0+i] = 0;
311 MEM_REG[0x3B48>>1]=(MEM_REG[0x3B48>>1] & 0xFF00) | 0x03; // allow 940
316 MEM_REG[0x904>>1]&=0xfffe;
321 MEM_REG[0x904>>1]|=1;
333 return ((MEM_REG[0x3804>>1] >> 12) & 0x1);
338 return ((MEM_REG[0x3804>>1] >> 8) & 0xF);
343 return ((MEM_REG[0x3804>>1] >> 4) & 0xF);
348 return (MEM_REG[0x3804>>1] & 0xF);
353 return ((MEM_REG[0x3802>>1] >> 12) & 0xF);
358 return ((MEM_REG[0x3802>>1] >> 8) & 0xF);
363 return ((MEM_REG[0x3802>>1] >> 4) & 0xF);
368 return (MEM_REG[0x3802>>1] & 0xF);
371 unsigned get_REFPERD()
373 return MEM_REG[0x3808>>1];
379 void set_CAS(unsigned short timing)
381 printf ("set CAS = %u\r\n",timing+2);
383 v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0x1 << 12)));
384 MEM_REG[0x3804>>1] = ((timing & 0x1) << 12) | v;
387 void set_tRC(unsigned short timing)
389 printf ("set tRC = %u\r\n",timing+1);
391 v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF << 8)));
392 MEM_REG[0x3804>>1] = ((timing & 0xF) << 8) | v;
395 void set_tRAS(unsigned short timing)
397 printf ("set tRAS = %u\r\n",timing+1);
399 v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF << 4)));
400 MEM_REG[0x3804>>1] = ((timing & 0xF) << 4) | v;
403 void set_tWR(unsigned short timing)
405 printf ("set tWR = %u\r\n",timing+1);
407 v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF)));
408 MEM_REG[0x3804>>1] = (timing & 0xF) | v;
411 void set_tMRD(unsigned short timing)
413 printf ("set tMRD = %u\r\n",timing+1);
415 v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 12)));
416 MEM_REG[0x3802>>1] = ((timing & 0xF) << 12) | v;
419 void set_tRFC(unsigned short timing)
421 printf ("set tRFC = %u\r\n",timing+1);
423 v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 8)));
424 MEM_REG[0x3802>>1] = ((timing & 0xF) << 8) | v;
427 void set_tRP(unsigned short timing)
429 printf ("set tRP = %u\r\n",timing+1);
431 v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 4)));
432 MEM_REG[0x3802>>1] = ((timing & 0xF) << 4) | v;
435 void set_tRCD(unsigned short timing)
437 printf ("set tRCD = %u\r\n",timing+1);
439 v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF)));
440 MEM_REG[0x3802>>1] = (timing & 0xF) | v;
443 void set_REFPERD(unsigned short timing)
445 printf ("set Refresh Period = %u\r\n",timing+1);
446 MEM_REG[0x3808>>1] = timing;
454 void set_gamma(float gamma)
456 printf ("set gamma = %f\r\n",gamma);
461 MEM_REG[0x2880>>1]&=~(1<<12);
463 MEM_REG[0x295C>>1]=0;
468 g =(unsigned char)(255.0*pow(i/255.0,gamma));
470 MEM_REG[0x295E>>1]= s;
471 MEM_REG[0x295E>>1]= g;
475 unsigned get_YBNKLVL()
477 return (MEM_REG[0x283A>>1] & 0x3FF);
480 void set_YBNKLVL(unsigned short val)
482 unsigned short temp = (unsigned short)(MEM_REG[0x3808>>1] & (~(0x3FF)));
483 MEM_REG[0x3808>>1] = (val & 0x3FF) | temp;