1 /* cpuctrl.c for GP2X (CPU/LCD/RAM-Tuner Version 2.0)
2 Copyright (C) 2006 god_at_hell
3 original CPU-Overclocker (c) by Hermes/PS2Reality
4 the gamma-routine was provided by theoddbot
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 /****************************************************************************************************************************************/
26 /****************************************************************************************************************************************/
28 //#include <sys/mman.h>
31 //#include "gp2xminilib.h"
33 #define SYS_CLK_FREQ 7372800
35 //from minimal library rlyeh
37 //extern unsigned long gp2x_dev[4];
38 extern unsigned short *gp2x_memregs;
43 unsigned short SYSCLKENREG,SYSCSETREG,FPLLVSETREG,DUALINT920,DUALINT940,DUALCTRL940,DISPCSETREG,MEMTIMEX0;
44 unsigned short MEMTIMEX1,MEMREFX,MLC_GAMM_BYPATH,MLC_GAMMA_A,MLC_GAMMA_D,YBNKLVL;
48 volatile unsigned short *MEM_REG;
49 unsigned MDIV,PDIV,SCALE;
50 volatile unsigned *arm940code;
54 MEM_REG=&gp2x_memregs[0];
57 void save_system_regs()
59 system_reg.SYSCSETREG=MEM_REG[0x91c>>1];
60 system_reg.FPLLVSETREG=MEM_REG[0x912>>1];
61 system_reg.SYSCLKENREG=MEM_REG[0x904>>1];
62 system_reg.DUALINT920=MEM_REG[0x3B40>>1];
63 system_reg.DUALINT940=MEM_REG[0x3B42>>1];
64 system_reg.DUALCTRL940=MEM_REG[0x3B48>>1];
65 system_reg.DISPCSETREG=MEM_REG[0x924>>1];
66 system_reg.MEMTIMEX0=MEM_REG[0x3802>>1];
67 system_reg.MEMTIMEX1=MEM_REG[0x3804>>1];
68 system_reg.MEMREFX=MEM_REG[0x3808>>1];
69 system_reg.MLC_GAMM_BYPATH=MEM_REG[0x2880>>1];
70 system_reg.MLC_GAMMA_A=MEM_REG[0x295C>>1];
71 system_reg.MLC_GAMMA_D=MEM_REG[0x295E>>1];
72 system_reg.YBNKLVL=MEM_REG[0x283A>>1];
75 void load_system_regs()
77 MEM_REG[0x91c>>1]=system_reg.SYSCSETREG;
78 MEM_REG[0x910>>1]=system_reg.FPLLVSETREG;
79 MEM_REG[0x3B40>>1]=system_reg.DUALINT920;
80 MEM_REG[0x3B42>>1]=system_reg.DUALINT940;
81 MEM_REG[0x3B48>>1]=system_reg.DUALCTRL940;
82 MEM_REG[0x904>>1]=system_reg.SYSCLKENREG;
83 /* Set UPLLSETVREG to 0x4F02, which gives 80MHz */
84 MEM_REG[0x0914>>1] = 0x4F02;
85 /* Wait for clock change to start */
86 while (MEM_REG[0x0902>>1] & 2);
87 /* Wait for clock change to be verified */
88 while (MEM_REG[0x0916>>1] != 0x4F02);
89 MEM_REG[0x3802>>1]=system_reg.MEMTIMEX0;
90 MEM_REG[0x3804>>1]=system_reg.MEMTIMEX1;
91 MEM_REG[0x3808>>1]=system_reg.MEMREFX;
92 MEM_REG[0x2880>>1]=system_reg.MLC_GAMM_BYPATH;
93 MEM_REG[0x295C>>1]=system_reg.MLC_GAMMA_A;
94 MEM_REG[0x295E>>1]=system_reg.MLC_GAMMA_D;
95 MEM_REG[0x283A>>1]=system_reg.YBNKLVL;
99 void set_FCLK(unsigned MHZ)
101 printf ("set CPU-Frequency = %uMHz\r\n",MHZ);
103 unsigned mdiv,pdiv=3,scale=0;
105 mdiv=(MHZ*pdiv)/SYS_CLK_FREQ;
106 //printf ("Old value = %04X\r",MEM_REG[0x924>>1]," ");
107 //printf ("APLL = %04X\r",MEM_REG[0x91A>>1]," ");
108 mdiv=((mdiv-8)<<8) & 0xff00;
109 pdiv=((pdiv-2)<<2) & 0xfc;
111 v=mdiv | pdiv | scale;
117 return MEM_REG[0x910>>1];
121 void set_add_FLCDCLK(int addclock)
123 //Set LCD controller to use FPLL
124 printf ("...set to FPLL-Clockgen...\r\n");
125 printf ("set Timing-Prescaler = %i\r\n",addclock);
126 MEM_REG[0x924>>1]= 0x5A00 + ((addclock)<<8);
127 //If you change the initial timing, don't forget to shift your intervall-borders in "cpu_speed.c"
130 void set_add_ULCDCLK(int addclock)
132 //Set LCD controller to use UPLL
133 printf ("...set to UPLL-Clockgen...\r\n");
134 printf ("set Timing-Prescaler = %i\r\n",addclock);
135 MEM_REG[0x0924>>1] = 0x8900 + ((addclock)<<8);
136 //If you change the initial timing, don't forget to shift your intervall-borders in "cpu_speed.c"
139 unsigned get_LCDClk()
141 if (MEM_REG[0x0924>>1] < 0x7A01) return((MEM_REG[0x0924>>1] - 0x5A00)>>8);
142 else return((MEM_REG[0x0924>>1] - 0x8900)>>8);
147 if (MEM_REG[0x0924>>1] < 0x7A01) return(0);
151 unsigned get_freq_UCLK()
154 unsigned reg,mdiv,pdiv,scale;
155 i = MEM_REG[0x900>>1];
158 reg=MEM_REG[0x916>>1];
159 mdiv = ((reg & 0xff00) >> 8) + 8;
160 pdiv = ((reg & 0xfc) >> 2) + 2;
162 return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale));
165 unsigned get_freq_ACLK()
168 unsigned reg,mdiv,pdiv,scale;
169 i = MEM_REG[0x900>>1];
172 reg=MEM_REG[0x918>>1];
173 mdiv = ((reg & 0xff00) >> 8) + 8;
174 pdiv = ((reg & 0xfc) >> 2) + 2;
176 return ((SYS_CLK_FREQ * mdiv)/(pdiv << scale));
179 unsigned get_freq_920_CLK()
182 unsigned reg,mdiv,pdiv,scale;
183 reg=MEM_REG[0x912>>1];
184 mdiv = ((reg & 0xff00) >> 8) + 8;
185 pdiv = ((reg & 0xfc) >> 2) + 2;
190 i = (MEM_REG[0x91c>>1] & 7)+1;
191 return ((SYS_CLK_FREQ * mdiv)/(pdiv << scale))/i;
194 unsigned get_freq_940_CLK()
197 unsigned reg,mdiv,pdiv,scale;
198 reg=MEM_REG[0x912>>1];
199 mdiv = ((reg & 0xff00) >> 8) + 8;
200 pdiv = ((reg & 0xfc) >> 2) + 2;
202 i = ((MEM_REG[0x91c>>1]>>3) & 7)+1;
203 return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale))/i;
206 unsigned get_freq_DCLK()
209 unsigned reg,mdiv,pdiv,scale;
210 reg=MEM_REG[0x912>>1];
211 mdiv = ((reg & 0xff00) >> 8) + 8;
212 pdiv = ((reg & 0xfc) >> 2) + 2;
214 i = ((MEM_REG[0x91c>>1]>>6) & 7)+1;
215 return ((SYS_CLK_FREQ * mdiv) / (pdiv << scale))/i;
218 void set_920_Div(unsigned short div)
220 printf ("set divider for CPU-Clock = %u\r\n",div+1);
222 v = MEM_REG[0x91c>>1] & (~0x3);
223 MEM_REG[0x91c>>1] = (div & 0x7) | v;
226 unsigned short get_920_Div()
228 return (MEM_REG[0x91c>>1] & 0x7);
231 void set_940_Div(unsigned short div)
234 v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 3)));
235 MEM_REG[0x91c>>1] = ((div & 0x7) << 3) | v;
238 unsigned short get_940_Div()
240 return ((MEM_REG[0x91c>>1] >> 3) & 0x7);
243 void set_DCLK_Div( unsigned short div )
245 printf ("set divider for RAM-Clock = %u\r\n",div+1);
247 v = (unsigned short)( MEM_REG[0x91c>>1] & (~(0x7 << 6)));
248 MEM_REG[0x91c>>1] = ((div & 0x7) << 6) | v;
251 unsigned short get_DCLK_Div()
253 return ((MEM_REG[0x91c>>1] >> 6) & 0x7);
256 unsigned short Disable_Int_920()
259 ret=MEM_REG[0x3B40>>1];
260 MEM_REG[0x3B40>>1]=0;
261 MEM_REG[0x3B44>>1]=0xffff;
265 unsigned short Disable_Int_940()
268 ret=MEM_REG[0x3B42>>1];
269 MEM_REG[0x3B42>>1]=0;
270 MEM_REG[0x3B46>>1]=0xffff;
274 unsigned get_state940()
276 return MEM_REG[0x904>>1];
280 void Enable_Int_920(unsigned short flag)
282 MEM_REG[0x3B40>>1]=flag;
285 void Enable_Int_940(unsigned short flag)
287 MEM_REG[0x3B42>>1]=flag;
293 MEM_REG[0x3B48>>1]|= (1 << 7);
294 MEM_REG[0x904>>1]&=0xfffe;
297 void Load_940_code(unsigned *code,int size)
301 arm940code=(unsigned short *)mmap(0, 0x100000, PROT_READ|PROT_WRITE, MAP_SHARED, gp2x_dev[2], 0x03000000);
303 cp=(unsigned *) code;
304 for (i = 0; i < size/4; i ++)
306 arm940code[i] = cp[i];
308 for (i = 0; i < 64; i ++)
310 arm940code[0x3FC0+i] = 0;
312 MEM_REG[0x3B48>>1]=(MEM_REG[0x3B48>>1] & 0xFF00) | 0x03; // allow 940
317 MEM_REG[0x904>>1]&=0xfffe;
322 MEM_REG[0x904>>1]|=1;
335 return ((MEM_REG[0x3804>>1] >> 12) & 0x1);
340 return ((MEM_REG[0x3804>>1] >> 8) & 0xF);
345 return ((MEM_REG[0x3804>>1] >> 4) & 0xF);
350 return (MEM_REG[0x3804>>1] & 0xF);
355 return ((MEM_REG[0x3802>>1] >> 12) & 0xF);
360 return ((MEM_REG[0x3802>>1] >> 8) & 0xF);
365 return ((MEM_REG[0x3802>>1] >> 4) & 0xF);
370 return (MEM_REG[0x3802>>1] & 0xF);
373 unsigned get_REFPERD()
375 return MEM_REG[0x3808>>1];
381 void set_CAS(unsigned short timing)
383 printf ("set CAS = %u\r\n",timing+2);
385 v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0x1 << 12)));
386 MEM_REG[0x3804>>1] = ((timing & 0x1) << 12) | v;
389 void set_tRC(unsigned short timing)
391 printf ("set tRC = %u\r\n",timing+1);
393 v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF << 8)));
394 MEM_REG[0x3804>>1] = ((timing & 0xF) << 8) | v;
397 void set_tRAS(unsigned short timing)
399 printf ("set tRAS = %u\r\n",timing+1);
401 v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF << 4)));
402 MEM_REG[0x3804>>1] = ((timing & 0xF) << 4) | v;
405 void set_tWR(unsigned short timing)
407 printf ("set tWR = %u\r\n",timing+1);
409 v = (unsigned short)(MEM_REG[0x3804>>1] & (~(0xF)));
410 MEM_REG[0x3804>>1] = (timing & 0xF) | v;
413 void set_tMRD(unsigned short timing)
415 printf ("set tMRD = %u\r\n",timing+1);
417 v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 12)));
418 MEM_REG[0x3802>>1] = ((timing & 0xF) << 12) | v;
421 void set_tRFC(unsigned short timing)
423 printf ("set tRFC = %u\r\n",timing+1);
425 v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 8)));
426 MEM_REG[0x3802>>1] = ((timing & 0xF) << 8) | v;
429 void set_tRP(unsigned short timing)
431 printf ("set tRP = %u\r\n",timing+1);
433 v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF << 4)));
434 MEM_REG[0x3802>>1] = ((timing & 0xF) << 4) | v;
437 void set_tRCD(unsigned short timing)
439 printf ("set tRCD = %u\r\n",timing+1);
441 v = (unsigned short)(MEM_REG[0x3802>>1] & (~(0xF)));
442 MEM_REG[0x3802>>1] = (timing & 0xF) | v;
445 void set_REFPERD(unsigned short timing)
447 printf ("set Refresh Period = %u\r\n",timing+1);
448 MEM_REG[0x3808>>1] = timing;
456 void set_gamma(float gamma)
458 printf ("set gamma = %f\r\n",gamma);
463 MEM_REG[0x2880>>1]&=~(1<<12);
465 MEM_REG[0x295C>>1]=0;
470 g =(unsigned char)(255.0*pow(i/255.0,gamma));
472 MEM_REG[0x295E>>1]= s;
473 MEM_REG[0x295E>>1]= g;
477 unsigned get_YBNKLVL()
479 return (MEM_REG[0x283A>>1] & 0x3FF);
482 void set_YBNKLVL(unsigned short val)
484 unsigned short temp = (unsigned short)(MEM_REG[0x3808>>1] & (~(0x3FF)));
485 MEM_REG[0x3808>>1] = (val & 0x3FF) | temp;