libpcsxcore/lightrec/plugin.c

   1 #include <errno.h>
   2 #include <stdbool.h>
   3 #include <stdio.h>
   4 #include <unistd.h>
   5 #include <signal.h>
   6 #include <assert.h>
   7
   8 #if P_HAVE_MMAP
   9 #include <sys/mman.h>
  10 #endif
  11
  12 #include "lightrec.h"
  13 #include "internals.h"
  14 #include "../cdrom.h"
  15 #include "../gpu.h"
  16 #include "../gte.h"
  17 #include "../mdec.h"
  18 #include "../psxdma.h"
  19 #include "../psxhw.h"
  20 #include "../psxmem.h"
  21 #include "../r3000a.h"
  22 #include "../psxinterpreter.h"
  23 #include "../psxhle.h"
  24 #include "../psxevents.h"
  25
  26 #include "../frontend/main.h"
  27
  28 #include "mem.h"
  29 #include "plugin.h"
  30
  31 #if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
  32 #error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
  33 #endif
  34
  35 #define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
  36
  37 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
  38 #       define LE32TOH(x)       __builtin_bswap32(x)
  39 #       define HTOLE32(x)       __builtin_bswap32(x)
  40 #       define LE16TOH(x)       __builtin_bswap16(x)
  41 #       define HTOLE16(x)       __builtin_bswap16(x)
  42 #else
  43 #       define LE32TOH(x)       (x)
  44 #       define HTOLE32(x)       (x)
  45 #       define LE16TOH(x)       (x)
  46 #       define HTOLE16(x)       (x)
  47 #endif
  48
  49 #ifdef __GNUC__
  50 #       define likely(x)       __builtin_expect(!!(x),1)
  51 #       define unlikely(x)     __builtin_expect(!!(x),0)
  52 #else
  53 #       define likely(x)       (x)
  54 #       define unlikely(x)     (x)
  55 #endif
  56
  57 psxRegisters psxRegs;
  58 Rcnt rcnts[4];
  59
  60 void* code_buffer;
  61
  62 static struct lightrec_state *lightrec_state;
  63
  64 static char *name = "retroarch.exe";
  65
  66 static bool use_lightrec_interpreter;
  67 static bool use_pcsx_interpreter;
  68 static bool block_stepping;
  69
  70 extern u32 lightrec_hacks;
  71
  72 enum my_cp2_opcodes {
  73         OP_CP2_RTPS             = 0x01,
  74         OP_CP2_NCLIP            = 0x06,
  75         OP_CP2_OP               = 0x0c,
  76         OP_CP2_DPCS             = 0x10,
  77         OP_CP2_INTPL            = 0x11,
  78         OP_CP2_MVMVA            = 0x12,
  79         OP_CP2_NCDS             = 0x13,
  80         OP_CP2_CDP              = 0x14,
  81         OP_CP2_NCDT             = 0x16,
  82         OP_CP2_NCCS             = 0x1b,
  83         OP_CP2_CC               = 0x1c,
  84         OP_CP2_NCS              = 0x1e,
  85         OP_CP2_NCT              = 0x20,
  86         OP_CP2_SQR              = 0x28,
  87         OP_CP2_DCPL             = 0x29,
  88         OP_CP2_DPCT             = 0x2a,
  89         OP_CP2_AVSZ3            = 0x2d,
  90         OP_CP2_AVSZ4            = 0x2e,
  91         OP_CP2_RTPT             = 0x30,
  92         OP_CP2_GPF              = 0x3d,
  93         OP_CP2_GPL              = 0x3e,
  94         OP_CP2_NCCT             = 0x3f,
  95 };
  96
  97 static void (*cp2_ops[])(struct psxCP2Regs *) = {
  98         [OP_CP2_RTPS] = gteRTPS,
  99         [OP_CP2_RTPS] = gteRTPS,
 100         [OP_CP2_NCLIP] = gteNCLIP,
 101         [OP_CP2_OP] = gteOP,
 102         [OP_CP2_DPCS] = gteDPCS,
 103         [OP_CP2_INTPL] = gteINTPL,
 104         [OP_CP2_MVMVA] = gteMVMVA,
 105         [OP_CP2_NCDS] = gteNCDS,
 106         [OP_CP2_CDP] = gteCDP,
 107         [OP_CP2_NCDT] = gteNCDT,
 108         [OP_CP2_NCCS] = gteNCCS,
 109         [OP_CP2_CC] = gteCC,
 110         [OP_CP2_NCS] = gteNCS,
 111         [OP_CP2_NCT] = gteNCT,
 112         [OP_CP2_SQR] = gteSQR,
 113         [OP_CP2_DCPL] = gteDCPL,
 114         [OP_CP2_DPCT] = gteDPCT,
 115         [OP_CP2_AVSZ3] = gteAVSZ3,
 116         [OP_CP2_AVSZ4] = gteAVSZ4,
 117         [OP_CP2_RTPT] = gteRTPT,
 118         [OP_CP2_GPF] = gteGPF,
 119         [OP_CP2_GPL] = gteGPL,
 120         [OP_CP2_NCCT] = gteNCCT,
 121 };
 122
 123 static char cache_buf[64 * 1024];
 124
 125 static void cop2_op(struct lightrec_state *state, u32 func)
 126 {
 127         struct lightrec_registers *regs = lightrec_get_registers(state);
 128
 129         psxRegs.code = func;
 130
 131         if (unlikely(!cp2_ops[func & 0x3f])) {
 132                 fprintf(stderr, "Invalid CP2 function %u\n", func);
 133         } else {
 134                 /* This works because regs->cp2c comes right after regs->cp2d,
 135                  * so it can be cast to a pcsxCP2Regs pointer. */
 136                 cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
 137         }
 138 }
 139
 140 static bool has_interrupt(void)
 141 {
 142         struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
 143
 144         return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
 145                 (regs->cp0[12] & 0x401) == 0x401) ||
 146                 (regs->cp0[12] & regs->cp0[13] & 0x0300);
 147 }
 148
 149 static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
 150 {
 151         psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
 152         lightrec_reset_cycle_count(state, 0);
 153 }
 154
 155 static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
 156 {
 157         s32 cycles_left = next_interupt - psxRegs.cycle;
 158
 159         if (block_stepping || cycles_left <= 0 || has_interrupt())
 160                 lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
 161         else {
 162                 lightrec_set_target_cycle_count(state, cycles_left * 1024);
 163         }
 164 }
 165
 166 static void hw_write_byte(struct lightrec_state *state,
 167                           u32 op, void *host, u32 mem, u32 val)
 168 {
 169         lightrec_tansition_to_pcsx(state);
 170
 171         psxHwWrite8(mem, val);
 172
 173         lightrec_tansition_from_pcsx(state);
 174 }
 175
 176 static void hw_write_half(struct lightrec_state *state,
 177                           u32 op, void *host, u32 mem, u32 val)
 178 {
 179         lightrec_tansition_to_pcsx(state);
 180
 181         psxHwWrite16(mem, val);
 182
 183         lightrec_tansition_from_pcsx(state);
 184 }
 185
 186 static void hw_write_word(struct lightrec_state *state,
 187                           u32 op, void *host, u32 mem, u32 val)
 188 {
 189         lightrec_tansition_to_pcsx(state);
 190
 191         psxHwWrite32(mem, val);
 192
 193         lightrec_tansition_from_pcsx(state);
 194 }
 195
 196 static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
 197 {
 198         u8 val;
 199
 200         lightrec_tansition_to_pcsx(state);
 201
 202         val = psxHwRead8(mem);
 203
 204         lightrec_tansition_from_pcsx(state);
 205
 206         return val;
 207 }
 208
 209 static u16 hw_read_half(struct lightrec_state *state,
 210                         u32 op, void *host, u32 mem)
 211 {
 212         u16 val;
 213
 214         lightrec_tansition_to_pcsx(state);
 215
 216         val = psxHwRead16(mem);
 217
 218         lightrec_tansition_from_pcsx(state);
 219
 220         return val;
 221 }
 222
 223 static u32 hw_read_word(struct lightrec_state *state,
 224                         u32 op, void *host, u32 mem)
 225 {
 226         u32 val;
 227
 228         lightrec_tansition_to_pcsx(state);
 229
 230         val = psxHwRead32(mem);
 231
 232         lightrec_tansition_from_pcsx(state);
 233
 234         return val;
 235 }
 236
 237 static struct lightrec_mem_map_ops hw_regs_ops = {
 238         .sb = hw_write_byte,
 239         .sh = hw_write_half,
 240         .sw = hw_write_word,
 241         .lb = hw_read_byte,
 242         .lh = hw_read_half,
 243         .lw = hw_read_word,
 244 };
 245
 246 static u32 cache_ctrl;
 247
 248 static void cache_ctrl_write_word(struct lightrec_state *state,
 249                                   u32 op, void *host, u32 mem, u32 val)
 250 {
 251         cache_ctrl = val;
 252 }
 253
 254 static u32 cache_ctrl_read_word(struct lightrec_state *state,
 255                                 u32 op, void *host, u32 mem)
 256 {
 257         return cache_ctrl;
 258 }
 259
 260 static struct lightrec_mem_map_ops cache_ctrl_ops = {
 261         .sw = cache_ctrl_write_word,
 262         .lw = cache_ctrl_read_word,
 263 };
 264
 265 static struct lightrec_mem_map lightrec_map[] = {
 266         [PSX_MAP_KERNEL_USER_RAM] = {
 267                 /* Kernel and user memory */
 268                 .pc = 0x00000000,
 269                 .length = 0x200000,
 270         },
 271         [PSX_MAP_BIOS] = {
 272                 /* BIOS */
 273                 .pc = 0x1fc00000,
 274                 .length = 0x80000,
 275         },
 276         [PSX_MAP_SCRATCH_PAD] = {
 277                 /* Scratch pad */
 278                 .pc = 0x1f800000,
 279                 .length = 0x400,
 280         },
 281         [PSX_MAP_PARALLEL_PORT] = {
 282                 /* Parallel port */
 283                 .pc = 0x1f000000,
 284                 .length = 0x10000,
 285         },
 286         [PSX_MAP_HW_REGISTERS] = {
 287                 /* Hardware registers */
 288                 .pc = 0x1f801000,
 289                 .length = 0x8000,
 290                 .ops = &hw_regs_ops,
 291         },
 292         [PSX_MAP_CACHE_CONTROL] = {
 293                 /* Cache control */
 294                 .pc = 0x5ffe0130,
 295                 .length = 4,
 296                 .ops = &cache_ctrl_ops,
 297         },
 298
 299         /* Mirrors of the kernel/user memory */
 300         [PSX_MAP_MIRROR1] = {
 301                 .pc = 0x00200000,
 302                 .length = 0x200000,
 303                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 304         },
 305         [PSX_MAP_MIRROR2] = {
 306                 .pc = 0x00400000,
 307                 .length = 0x200000,
 308                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 309         },
 310         [PSX_MAP_MIRROR3] = {
 311                 .pc = 0x00600000,
 312                 .length = 0x200000,
 313                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 314         },
 315
 316         /* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
 317         [PSX_MAP_PPORT_MIRROR] = {
 318                 .pc = 0x1fa00000,
 319                 .length = 0x10000,
 320                 .mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
 321         },
 322
 323         /* Code buffer */
 324         [PSX_MAP_CODE_BUFFER] = {
 325                 .length = CODE_BUFFER_SIZE,
 326         },
 327 };
 328
 329 static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
 330 {
 331         if (enable)
 332                 memcpy(psxM, cache_buf, sizeof(cache_buf));
 333         else
 334                 memcpy(cache_buf, psxM, sizeof(cache_buf));
 335 }
 336
 337 static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
 338 {
 339         if (is_write && size != 32) {
 340                 // force32 so must go through handlers
 341                 if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
 342                         return false;
 343                 if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
 344                         return false;
 345         }
 346
 347         switch (size) {
 348         case 8:
 349                 switch (kaddr) {
 350                 case 0x1f801040:
 351                 case 0x1f801050:
 352                 case 0x1f801800:
 353                 case 0x1f801801:
 354                 case 0x1f801802:
 355                 case 0x1f801803:
 356                         return false;
 357                 default:
 358                         return true;
 359                 }
 360         case 16:
 361                 switch (kaddr) {
 362                 case 0x1f801040:
 363                 case 0x1f801044:
 364                 case 0x1f801048:
 365                 case 0x1f80104a:
 366                 case 0x1f80104e:
 367                 case 0x1f801050:
 368                 case 0x1f801054:
 369                 case 0x1f80105a:
 370                 case 0x1f80105e:
 371                 case 0x1f801100:
 372                 case 0x1f801104:
 373                 case 0x1f801108:
 374                 case 0x1f801110:
 375                 case 0x1f801114:
 376                 case 0x1f801118:
 377                 case 0x1f801120:
 378                 case 0x1f801124:
 379                 case 0x1f801128:
 380                         return false;
 381                 case 0x1f801070:
 382                 case 0x1f801074:
 383                         return !is_write;
 384                 default:
 385                         return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 386                 }
 387         default:
 388                 switch (kaddr) {
 389                 case 0x1f801040:
 390                 case 0x1f801050:
 391                 case 0x1f801100:
 392                 case 0x1f801104:
 393                 case 0x1f801108:
 394                 case 0x1f801110:
 395                 case 0x1f801114:
 396                 case 0x1f801118:
 397                 case 0x1f801120:
 398                 case 0x1f801124:
 399                 case 0x1f801128:
 400                 case 0x1f801810:
 401                 case 0x1f801814:
 402                 case 0x1f801820:
 403                 case 0x1f801824:
 404                         return false;
 405                 case 0x1f801070:
 406                 case 0x1f801074:
 407                 case 0x1f801088:
 408                 case 0x1f801098:
 409                 case 0x1f8010a8:
 410                 case 0x1f8010b8:
 411                 case 0x1f8010c8:
 412                 case 0x1f8010e8:
 413                 case 0x1f8010f4:
 414                         return !is_write;
 415                 default:
 416                         return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 417                 }
 418         }
 419 }
 420
 421 #if defined(HW_DOL) || defined(HW_RVL)
 422 static void lightrec_code_inv(void *ptr, uint32_t len)
 423 {
 424         extern void DCFlushRange(void *ptr, u32 len);
 425         extern void ICInvalidateRange(void *ptr, u32 len);
 426
 427         DCFlushRange(ptr, len);
 428         ICInvalidateRange(ptr, len);
 429 }
 430 #elif defined(HW_WUP)
 431 static void lightrec_code_inv(void *ptr, uint32_t len)
 432 {
 433         wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
 434 }
 435 #endif
 436
 437 static const struct lightrec_ops lightrec_ops = {
 438         .cop2_op = cop2_op,
 439         .enable_ram = lightrec_enable_ram,
 440         .hw_direct = lightrec_can_hw_direct,
 441 #if defined(HW_DOL) || defined(HW_RVL) || defined(HW_WUP)
 442         .code_inv = lightrec_code_inv,
 443 #endif
 444 };
 445
 446 static int lightrec_plugin_init(void)
 447 {
 448         lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
 449         lightrec_map[PSX_MAP_BIOS].address = psxR;
 450         lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
 451         lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
 452         lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
 453
 454         if (!LIGHTREC_CUSTOM_MAP) {
 455 #if P_HAVE_MMAP
 456                 code_buffer = mmap(0, CODE_BUFFER_SIZE,
 457                                    PROT_EXEC | PROT_READ | PROT_WRITE,
 458                                    MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 459                 if (code_buffer == MAP_FAILED)
 460                         return -ENOMEM;
 461 #else
 462                 code_buffer = malloc(CODE_BUFFER_SIZE);
 463                 if (!code_buffer)
 464                         return -ENOMEM;
 465 #endif
 466         }
 467
 468         if (LIGHTREC_CUSTOM_MAP) {
 469                 lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
 470                 lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
 471                 lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
 472         }
 473
 474         lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
 475
 476         use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
 477
 478         lightrec_state = lightrec_init(name,
 479                         lightrec_map, ARRAY_SIZE(lightrec_map),
 480                         &lightrec_ops);
 481
 482         // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
 483         //              (uintptr_t) psxM,
 484         //              (uintptr_t) psxP,
 485         //              (uintptr_t) psxR,
 486         //              (uintptr_t) psxH);
 487
 488 #ifndef _WIN32
 489         signal(SIGPIPE, exit);
 490 #endif
 491         return 0;
 492 }
 493
 494 static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
 495 static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);
 496
 497 static void lightrec_plugin_execute_internal(bool block_only)
 498 {
 499         struct lightrec_registers *regs;
 500         u32 flags, cycles_pcsx;
 501
 502         regs = lightrec_get_registers(lightrec_state);
 503         gen_interupt((psxCP0Regs *)regs->cp0);
 504         if (!block_only && stop)
 505                 return;
 506
 507         cycles_pcsx = next_interupt - psxRegs.cycle;
 508         assert((s32)cycles_pcsx > 0);
 509
 510         // step during early boot so that 0x80030000 fastboot hack works
 511         block_stepping = block_only;
 512         if (block_only)
 513                 cycles_pcsx = 0;
 514
 515         if (use_pcsx_interpreter) {
 516                 intExecuteBlock(0);
 517         } else {
 518                 u32 cycles_lightrec = cycles_pcsx * 1024;
 519                 if (unlikely(use_lightrec_interpreter)) {
 520                         psxRegs.pc = lightrec_run_interpreter(lightrec_state,
 521                                                               psxRegs.pc,
 522                                                               cycles_lightrec);
 523                 } else {
 524                         psxRegs.pc = lightrec_execute(lightrec_state,
 525                                                       psxRegs.pc, cycles_lightrec);
 526                 }
 527
 528                 lightrec_tansition_to_pcsx(lightrec_state);
 529
 530                 flags = lightrec_exit_flags(lightrec_state);
 531
 532                 if (flags & LIGHTREC_EXIT_SEGFAULT) {
 533                         fprintf(stderr, "Exiting at cycle 0x%08x\n",
 534                                 psxRegs.cycle);
 535                         exit(1);
 536                 }
 537
 538                 if (flags & LIGHTREC_EXIT_SYSCALL)
 539                         psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
 540                 if (flags & LIGHTREC_EXIT_BREAK)
 541                         psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
 542                 else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
 543                         u32 op = intFakeFetch(psxRegs.pc);
 544                         u32 hlec = op & 0x03ffffff;
 545                         if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
 546                                 lightrec_plugin_sync_regs_to_pcsx(0);
 547                                 psxHLEt[hlec]();
 548                                 lightrec_plugin_sync_regs_from_pcsx(0);
 549                         }
 550                         else
 551                                 psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
 552                 }
 553         }
 554
 555         if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
 556                 /* Handle software interrupts */
 557                 regs->cp0[13] &= ~0x7c;
 558                 psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
 559         }
 560 }
 561
 562 static void lightrec_plugin_execute(void)
 563 {
 564         while (!stop)
 565                 lightrec_plugin_execute_internal(false);
 566 }
 567
 568 static void lightrec_plugin_execute_block(enum blockExecCaller caller)
 569 {
 570         lightrec_plugin_execute_internal(true);
 571 }
 572
 573 static void lightrec_plugin_clear(u32 addr, u32 size)
 574 {
 575         if ((addr == 0 && size == UINT32_MAX)
 576             || (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
 577                 lightrec_invalidate_all(lightrec_state);
 578         else
 579                 /* size * 4: PCSX uses DMA units */
 580                 lightrec_invalidate(lightrec_state, addr, size * 4);
 581 }
 582
 583 static void lightrec_plugin_notify(enum R3000Anote note, void *data)
 584 {
 585         switch (note)
 586         {
 587         case R3000ACPU_NOTIFY_CACHE_ISOLATED:
 588         case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
 589                 /* not used, lightrec calls lightrec_enable_ram() instead */
 590                 break;
 591         case R3000ACPU_NOTIFY_BEFORE_SAVE:
 592                 /* non-null 'data' means this is HLE related sync */
 593                 lightrec_plugin_sync_regs_to_pcsx(data == NULL);
 594                 break;
 595         case R3000ACPU_NOTIFY_AFTER_LOAD:
 596                 lightrec_plugin_sync_regs_from_pcsx(data == NULL);
 597                 if (data == NULL)
 598                         lightrec_invalidate_all(lightrec_state);
 599                 break;
 600         }
 601 }
 602
 603 static void lightrec_plugin_apply_config()
 604 {
 605         static u32 cycles_per_op_old;
 606         u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
 607                 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
 608         u32 cycles_per_op = cycle_mult * 1024 / 100;
 609         assert(cycles_per_op);
 610
 611         if (cycles_per_op_old && cycles_per_op_old != cycles_per_op) {
 612                 SysPrintf("lightrec: reinit block cache for cycles_per_op %.2f\n",
 613                         cycles_per_op / 1024.f);
 614                 lightrec_plugin_clear_block_caches(lightrec_state);
 615         }
 616         cycles_per_op_old = cycles_per_op;
 617         lightrec_set_cycles_per_opcode(lightrec_state, cycles_per_op);
 618 }
 619
 620 static void lightrec_plugin_shutdown(void)
 621 {
 622         lightrec_destroy(lightrec_state);
 623
 624         if (!LIGHTREC_CUSTOM_MAP) {
 625 #if P_HAVE_MMAP
 626                 munmap(code_buffer, CODE_BUFFER_SIZE);
 627 #else
 628                 free(code_buffer);
 629 #endif
 630         }
 631 }
 632
 633 static void lightrec_plugin_reset(void)
 634 {
 635         struct lightrec_registers *regs;
 636
 637         regs = lightrec_get_registers(lightrec_state);
 638
 639         /* Invalidate all blocks */
 640         lightrec_invalidate_all(lightrec_state);
 641
 642         /* Reset registers */
 643         memset(regs, 0, sizeof(*regs));
 644
 645         regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
 646         regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
 647
 648         lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
 649 }
 650
 651 static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
 652 {
 653         struct lightrec_registers *regs;
 654
 655         regs = lightrec_get_registers(lightrec_state);
 656         memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
 657         memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
 658         if (need_cp2)
 659                 memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 660 }
 661
 662 static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
 663 {
 664         struct lightrec_registers *regs;
 665
 666         regs = lightrec_get_registers(lightrec_state);
 667         memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
 668         memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
 669         if (need_cp2)
 670                 memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 671 }
 672
 673 R3000Acpu psxRec =
 674 {
 675         lightrec_plugin_init,
 676         lightrec_plugin_reset,
 677         lightrec_plugin_execute,
 678         lightrec_plugin_execute_block,
 679         lightrec_plugin_clear,
 680         lightrec_plugin_notify,
 681         lightrec_plugin_apply_config,
 682         lightrec_plugin_shutdown,
 683 };