libpcsxcore/lightrec/plugin.c

   1 #include <errno.h>
   2 #include <stdbool.h>
   3 #include <stdio.h>
   4 #include <unistd.h>
   5 #include <signal.h>
   6 #include <assert.h>
   7
   8 #if P_HAVE_MMAP
   9 #include <sys/mman.h>
  10 #endif
  11
  12 #include "lightrec.h"
  13 #include "../cdrom.h"
  14 #include "../gpu.h"
  15 #include "../gte.h"
  16 #include "../mdec.h"
  17 #include "../psxdma.h"
  18 #include "../psxhw.h"
  19 #include "../psxmem.h"
  20 #include "../r3000a.h"
  21 #include "../psxinterpreter.h"
  22 #include "../psxhle.h"
  23 #include "../psxevents.h"
  24
  25 #include "../frontend/main.h"
  26
  27 #include "mem.h"
  28 #include "plugin.h"
  29
  30 #if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
  31 #error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
  32 #endif
  33
  34 #define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
  35
  36 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
  37 #       define LE32TOH(x)       __builtin_bswap32(x)
  38 #       define HTOLE32(x)       __builtin_bswap32(x)
  39 #       define LE16TOH(x)       __builtin_bswap16(x)
  40 #       define HTOLE16(x)       __builtin_bswap16(x)
  41 #else
  42 #       define LE32TOH(x)       (x)
  43 #       define HTOLE32(x)       (x)
  44 #       define LE16TOH(x)       (x)
  45 #       define HTOLE16(x)       (x)
  46 #endif
  47
  48 #ifdef __GNUC__
  49 #       define likely(x)       __builtin_expect(!!(x),1)
  50 #       define unlikely(x)     __builtin_expect(!!(x),0)
  51 #else
  52 #       define likely(x)       (x)
  53 #       define unlikely(x)     (x)
  54 #endif
  55
  56 psxRegisters psxRegs;
  57 Rcnt rcnts[4];
  58
  59 void* code_buffer;
  60
  61 static struct lightrec_state *lightrec_state;
  62
  63 static char *name = "retroarch.exe";
  64
  65 static bool use_lightrec_interpreter;
  66 static bool use_pcsx_interpreter;
  67 static bool block_stepping;
  68
  69 extern u32 lightrec_hacks;
  70
  71 extern void lightrec_code_inv(void *ptr, uint32_t len);
  72
  73 enum my_cp2_opcodes {
  74         OP_CP2_RTPS             = 0x01,
  75         OP_CP2_NCLIP            = 0x06,
  76         OP_CP2_OP               = 0x0c,
  77         OP_CP2_DPCS             = 0x10,
  78         OP_CP2_INTPL            = 0x11,
  79         OP_CP2_MVMVA            = 0x12,
  80         OP_CP2_NCDS             = 0x13,
  81         OP_CP2_CDP              = 0x14,
  82         OP_CP2_NCDT             = 0x16,
  83         OP_CP2_NCCS             = 0x1b,
  84         OP_CP2_CC               = 0x1c,
  85         OP_CP2_NCS              = 0x1e,
  86         OP_CP2_NCT              = 0x20,
  87         OP_CP2_SQR              = 0x28,
  88         OP_CP2_DCPL             = 0x29,
  89         OP_CP2_DPCT             = 0x2a,
  90         OP_CP2_AVSZ3            = 0x2d,
  91         OP_CP2_AVSZ4            = 0x2e,
  92         OP_CP2_RTPT             = 0x30,
  93         OP_CP2_GPF              = 0x3d,
  94         OP_CP2_GPL              = 0x3e,
  95         OP_CP2_NCCT             = 0x3f,
  96 };
  97
  98 static void (*cp2_ops[])(struct psxCP2Regs *) = {
  99         [OP_CP2_RTPS] = gteRTPS,
 100         [OP_CP2_RTPS] = gteRTPS,
 101         [OP_CP2_NCLIP] = gteNCLIP,
 102         [OP_CP2_OP] = gteOP,
 103         [OP_CP2_DPCS] = gteDPCS,
 104         [OP_CP2_INTPL] = gteINTPL,
 105         [OP_CP2_MVMVA] = gteMVMVA,
 106         [OP_CP2_NCDS] = gteNCDS,
 107         [OP_CP2_CDP] = gteCDP,
 108         [OP_CP2_NCDT] = gteNCDT,
 109         [OP_CP2_NCCS] = gteNCCS,
 110         [OP_CP2_CC] = gteCC,
 111         [OP_CP2_NCS] = gteNCS,
 112         [OP_CP2_NCT] = gteNCT,
 113         [OP_CP2_SQR] = gteSQR,
 114         [OP_CP2_DCPL] = gteDCPL,
 115         [OP_CP2_DPCT] = gteDPCT,
 116         [OP_CP2_AVSZ3] = gteAVSZ3,
 117         [OP_CP2_AVSZ4] = gteAVSZ4,
 118         [OP_CP2_RTPT] = gteRTPT,
 119         [OP_CP2_GPF] = gteGPF,
 120         [OP_CP2_GPL] = gteGPL,
 121         [OP_CP2_NCCT] = gteNCCT,
 122 };
 123
 124 static char cache_buf[64 * 1024];
 125
 126 static void cop2_op(struct lightrec_state *state, u32 func)
 127 {
 128         struct lightrec_registers *regs = lightrec_get_registers(state);
 129
 130         psxRegs.code = func;
 131
 132         if (unlikely(!cp2_ops[func & 0x3f])) {
 133                 fprintf(stderr, "Invalid CP2 function %u\n", func);
 134         } else {
 135                 /* This works because regs->cp2c comes right after regs->cp2d,
 136                  * so it can be cast to a pcsxCP2Regs pointer. */
 137                 cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
 138         }
 139 }
 140
 141 static bool has_interrupt(void)
 142 {
 143         struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
 144
 145         return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
 146                 (regs->cp0[12] & 0x401) == 0x401) ||
 147                 (regs->cp0[12] & regs->cp0[13] & 0x0300);
 148 }
 149
 150 static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
 151 {
 152         psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
 153         lightrec_reset_cycle_count(state, 0);
 154 }
 155
 156 static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
 157 {
 158         s32 cycles_left = next_interupt - psxRegs.cycle;
 159
 160         if (block_stepping || cycles_left <= 0 || has_interrupt())
 161                 lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
 162         else {
 163                 lightrec_set_target_cycle_count(state, cycles_left * 1024);
 164         }
 165 }
 166
 167 static void hw_write_byte(struct lightrec_state *state,
 168                           u32 op, void *host, u32 mem, u32 val)
 169 {
 170         lightrec_tansition_to_pcsx(state);
 171
 172         psxHwWrite8(mem, val);
 173
 174         lightrec_tansition_from_pcsx(state);
 175 }
 176
 177 static void hw_write_half(struct lightrec_state *state,
 178                           u32 op, void *host, u32 mem, u32 val)
 179 {
 180         lightrec_tansition_to_pcsx(state);
 181
 182         psxHwWrite16(mem, val);
 183
 184         lightrec_tansition_from_pcsx(state);
 185 }
 186
 187 static void hw_write_word(struct lightrec_state *state,
 188                           u32 op, void *host, u32 mem, u32 val)
 189 {
 190         lightrec_tansition_to_pcsx(state);
 191
 192         psxHwWrite32(mem, val);
 193
 194         lightrec_tansition_from_pcsx(state);
 195 }
 196
 197 static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
 198 {
 199         u8 val;
 200
 201         lightrec_tansition_to_pcsx(state);
 202
 203         val = psxHwRead8(mem);
 204
 205         lightrec_tansition_from_pcsx(state);
 206
 207         return val;
 208 }
 209
 210 static u16 hw_read_half(struct lightrec_state *state,
 211                         u32 op, void *host, u32 mem)
 212 {
 213         u16 val;
 214
 215         lightrec_tansition_to_pcsx(state);
 216
 217         val = psxHwRead16(mem);
 218
 219         lightrec_tansition_from_pcsx(state);
 220
 221         return val;
 222 }
 223
 224 static u32 hw_read_word(struct lightrec_state *state,
 225                         u32 op, void *host, u32 mem)
 226 {
 227         u32 val;
 228
 229         lightrec_tansition_to_pcsx(state);
 230
 231         val = psxHwRead32(mem);
 232
 233         lightrec_tansition_from_pcsx(state);
 234
 235         return val;
 236 }
 237
 238 static struct lightrec_mem_map_ops hw_regs_ops = {
 239         .sb = hw_write_byte,
 240         .sh = hw_write_half,
 241         .sw = hw_write_word,
 242         .lb = hw_read_byte,
 243         .lh = hw_read_half,
 244         .lw = hw_read_word,
 245 };
 246
 247 static u32 cache_ctrl;
 248
 249 static void cache_ctrl_write_word(struct lightrec_state *state,
 250                                   u32 op, void *host, u32 mem, u32 val)
 251 {
 252         cache_ctrl = val;
 253 }
 254
 255 static u32 cache_ctrl_read_word(struct lightrec_state *state,
 256                                 u32 op, void *host, u32 mem)
 257 {
 258         return cache_ctrl;
 259 }
 260
 261 static struct lightrec_mem_map_ops cache_ctrl_ops = {
 262         .sw = cache_ctrl_write_word,
 263         .lw = cache_ctrl_read_word,
 264 };
 265
 266 static struct lightrec_mem_map lightrec_map[] = {
 267         [PSX_MAP_KERNEL_USER_RAM] = {
 268                 /* Kernel and user memory */
 269                 .pc = 0x00000000,
 270                 .length = 0x200000,
 271         },
 272         [PSX_MAP_BIOS] = {
 273                 /* BIOS */
 274                 .pc = 0x1fc00000,
 275                 .length = 0x80000,
 276         },
 277         [PSX_MAP_SCRATCH_PAD] = {
 278                 /* Scratch pad */
 279                 .pc = 0x1f800000,
 280                 .length = 0x400,
 281         },
 282         [PSX_MAP_PARALLEL_PORT] = {
 283                 /* Parallel port */
 284                 .pc = 0x1f000000,
 285                 .length = 0x10000,
 286         },
 287         [PSX_MAP_HW_REGISTERS] = {
 288                 /* Hardware registers */
 289                 .pc = 0x1f801000,
 290                 .length = 0x8000,
 291                 .ops = &hw_regs_ops,
 292         },
 293         [PSX_MAP_CACHE_CONTROL] = {
 294                 /* Cache control */
 295                 .pc = 0x5ffe0130,
 296                 .length = 4,
 297                 .ops = &cache_ctrl_ops,
 298         },
 299
 300         /* Mirrors of the kernel/user memory */
 301         [PSX_MAP_MIRROR1] = {
 302                 .pc = 0x00200000,
 303                 .length = 0x200000,
 304                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 305         },
 306         [PSX_MAP_MIRROR2] = {
 307                 .pc = 0x00400000,
 308                 .length = 0x200000,
 309                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 310         },
 311         [PSX_MAP_MIRROR3] = {
 312                 .pc = 0x00600000,
 313                 .length = 0x200000,
 314                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 315         },
 316
 317         /* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
 318         [PSX_MAP_PPORT_MIRROR] = {
 319                 .pc = 0x1fa00000,
 320                 .length = 0x10000,
 321                 .mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
 322         },
 323
 324         /* Code buffer */
 325         [PSX_MAP_CODE_BUFFER] = {
 326                 .length = CODE_BUFFER_SIZE,
 327         },
 328 };
 329
 330 static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
 331 {
 332         if (enable)
 333                 memcpy(psxM, cache_buf, sizeof(cache_buf));
 334         else
 335                 memcpy(cache_buf, psxM, sizeof(cache_buf));
 336 }
 337
 338 static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
 339 {
 340         if (is_write && size != 32) {
 341                 // force32 so must go through handlers
 342                 if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
 343                         return false;
 344                 if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
 345                         return false;
 346         }
 347
 348         switch (size) {
 349         case 8:
 350                 switch (kaddr) {
 351                 case 0x1f801040:
 352                 case 0x1f801050:
 353                 case 0x1f801800:
 354                 case 0x1f801801:
 355                 case 0x1f801802:
 356                 case 0x1f801803:
 357                         return false;
 358                 default:
 359                         return true;
 360                 }
 361         case 16:
 362                 switch (kaddr) {
 363                 case 0x1f801040:
 364                 case 0x1f801044:
 365                 case 0x1f801048:
 366                 case 0x1f80104a:
 367                 case 0x1f80104e:
 368                 case 0x1f801050:
 369                 case 0x1f801054:
 370                 case 0x1f80105a:
 371                 case 0x1f80105e:
 372                 case 0x1f801100:
 373                 case 0x1f801104:
 374                 case 0x1f801108:
 375                 case 0x1f801110:
 376                 case 0x1f801114:
 377                 case 0x1f801118:
 378                 case 0x1f801120:
 379                 case 0x1f801124:
 380                 case 0x1f801128:
 381                         return false;
 382                 case 0x1f801070:
 383                 case 0x1f801074:
 384                         return !is_write;
 385                 default:
 386                         return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 387                 }
 388         default:
 389                 switch (kaddr) {
 390                 case 0x1f801040:
 391                 case 0x1f801050:
 392                 case 0x1f801100:
 393                 case 0x1f801104:
 394                 case 0x1f801108:
 395                 case 0x1f801110:
 396                 case 0x1f801114:
 397                 case 0x1f801118:
 398                 case 0x1f801120:
 399                 case 0x1f801124:
 400                 case 0x1f801128:
 401                 case 0x1f801810:
 402                 case 0x1f801814:
 403                 case 0x1f801820:
 404                 case 0x1f801824:
 405                         return false;
 406                 case 0x1f801070:
 407                 case 0x1f801074:
 408                 case 0x1f801088:
 409                 case 0x1f801098:
 410                 case 0x1f8010a8:
 411                 case 0x1f8010b8:
 412                 case 0x1f8010c8:
 413                 case 0x1f8010e8:
 414                 case 0x1f8010f4:
 415                         return !is_write;
 416                 default:
 417                         return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 418                 }
 419         }
 420 }
 421
 422 static const struct lightrec_ops lightrec_ops = {
 423         .cop2_op = cop2_op,
 424         .enable_ram = lightrec_enable_ram,
 425         .hw_direct = lightrec_can_hw_direct,
 426         .code_inv = LIGHTREC_CODE_INV ? lightrec_code_inv : NULL,
 427 };
 428
 429 static int lightrec_plugin_init(void)
 430 {
 431         lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
 432         lightrec_map[PSX_MAP_BIOS].address = psxR;
 433         lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
 434         lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
 435         lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
 436
 437         if (!LIGHTREC_CUSTOM_MAP) {
 438 #if P_HAVE_MMAP
 439                 code_buffer = mmap(0, CODE_BUFFER_SIZE,
 440                                    PROT_EXEC | PROT_READ | PROT_WRITE,
 441                                    MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 442                 if (code_buffer == MAP_FAILED)
 443                         return -ENOMEM;
 444 #else
 445                 code_buffer = malloc(CODE_BUFFER_SIZE);
 446                 if (!code_buffer)
 447                         return -ENOMEM;
 448 #endif
 449         }
 450
 451         if (LIGHTREC_CUSTOM_MAP) {
 452                 lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
 453                 lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
 454                 lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
 455         }
 456
 457         lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
 458
 459         use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
 460
 461         lightrec_state = lightrec_init(name,
 462                         lightrec_map, ARRAY_SIZE(lightrec_map),
 463                         &lightrec_ops);
 464
 465         // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
 466         //              (uintptr_t) psxM,
 467         //              (uintptr_t) psxP,
 468         //              (uintptr_t) psxR,
 469         //              (uintptr_t) psxH);
 470
 471 #ifndef _WIN32
 472         signal(SIGPIPE, exit);
 473 #endif
 474         return 0;
 475 }
 476
 477 static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
 478 static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);
 479
 480 static void lightrec_plugin_execute_internal(bool block_only)
 481 {
 482         struct lightrec_registers *regs;
 483         u32 flags, cycles_pcsx;
 484
 485         regs = lightrec_get_registers(lightrec_state);
 486         gen_interupt((psxCP0Regs *)regs->cp0);
 487         if (!block_only && stop)
 488                 return;
 489
 490         cycles_pcsx = next_interupt - psxRegs.cycle;
 491         assert((s32)cycles_pcsx > 0);
 492
 493         // step during early boot so that 0x80030000 fastboot hack works
 494         block_stepping = block_only;
 495         if (block_only)
 496                 cycles_pcsx = 0;
 497
 498         if (use_pcsx_interpreter) {
 499                 intExecuteBlock(0);
 500         } else {
 501                 u32 cycles_lightrec = cycles_pcsx * 1024;
 502                 if (unlikely(use_lightrec_interpreter)) {
 503                         psxRegs.pc = lightrec_run_interpreter(lightrec_state,
 504                                                               psxRegs.pc,
 505                                                               cycles_lightrec);
 506                 } else {
 507                         psxRegs.pc = lightrec_execute(lightrec_state,
 508                                                       psxRegs.pc, cycles_lightrec);
 509                 }
 510
 511                 lightrec_tansition_to_pcsx(lightrec_state);
 512
 513                 flags = lightrec_exit_flags(lightrec_state);
 514
 515                 if (flags & LIGHTREC_EXIT_SEGFAULT) {
 516                         fprintf(stderr, "Exiting at cycle 0x%08x\n",
 517                                 psxRegs.cycle);
 518                         exit(1);
 519                 }
 520
 521                 if (flags & LIGHTREC_EXIT_SYSCALL)
 522                         psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
 523                 if (flags & LIGHTREC_EXIT_BREAK)
 524                         psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
 525                 else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
 526                         u32 op = intFakeFetch(psxRegs.pc);
 527                         u32 hlec = op & 0x03ffffff;
 528                         if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
 529                                 lightrec_plugin_sync_regs_to_pcsx(0);
 530                                 psxHLEt[hlec]();
 531                                 lightrec_plugin_sync_regs_from_pcsx(0);
 532                         }
 533                         else
 534                                 psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
 535                 }
 536         }
 537
 538         if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
 539                 /* Handle software interrupts */
 540                 regs->cp0[13] &= ~0x7c;
 541                 psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
 542         }
 543 }
 544
 545 static void lightrec_plugin_execute(void)
 546 {
 547         while (!stop)
 548                 lightrec_plugin_execute_internal(false);
 549 }
 550
 551 static void lightrec_plugin_execute_block(enum blockExecCaller caller)
 552 {
 553         lightrec_plugin_execute_internal(true);
 554 }
 555
 556 static void lightrec_plugin_clear(u32 addr, u32 size)
 557 {
 558         if ((addr == 0 && size == UINT32_MAX)
 559             || (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
 560                 lightrec_invalidate_all(lightrec_state);
 561         else
 562                 /* size * 4: PCSX uses DMA units */
 563                 lightrec_invalidate(lightrec_state, addr, size * 4);
 564 }
 565
 566 static void lightrec_plugin_notify(enum R3000Anote note, void *data)
 567 {
 568         switch (note)
 569         {
 570         case R3000ACPU_NOTIFY_CACHE_ISOLATED:
 571         case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
 572                 /* not used, lightrec calls lightrec_enable_ram() instead */
 573                 break;
 574         case R3000ACPU_NOTIFY_BEFORE_SAVE:
 575                 /* non-null 'data' means this is HLE related sync */
 576                 lightrec_plugin_sync_regs_to_pcsx(data == NULL);
 577                 break;
 578         case R3000ACPU_NOTIFY_AFTER_LOAD:
 579                 lightrec_plugin_sync_regs_from_pcsx(data == NULL);
 580                 if (data == NULL)
 581                         lightrec_invalidate_all(lightrec_state);
 582                 break;
 583         }
 584 }
 585
 586 static void lightrec_plugin_apply_config()
 587 {
 588         static u32 cycles_per_op_old;
 589         u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
 590                 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
 591         u32 cycles_per_op = cycle_mult * 1024 / 100;
 592         assert(cycles_per_op);
 593
 594         if (cycles_per_op_old && cycles_per_op_old != cycles_per_op) {
 595                 SysPrintf("lightrec: reinit block cache for cycles_per_op %.2f\n",
 596                         cycles_per_op / 1024.f);
 597         }
 598         cycles_per_op_old = cycles_per_op;
 599         lightrec_set_cycles_per_opcode(lightrec_state, cycles_per_op);
 600 }
 601
 602 static void lightrec_plugin_shutdown(void)
 603 {
 604         lightrec_destroy(lightrec_state);
 605
 606         if (!LIGHTREC_CUSTOM_MAP) {
 607 #if P_HAVE_MMAP
 608                 munmap(code_buffer, CODE_BUFFER_SIZE);
 609 #else
 610                 free(code_buffer);
 611 #endif
 612         }
 613 }
 614
 615 static void lightrec_plugin_reset(void)
 616 {
 617         struct lightrec_registers *regs;
 618
 619         regs = lightrec_get_registers(lightrec_state);
 620
 621         /* Invalidate all blocks */
 622         lightrec_invalidate_all(lightrec_state);
 623
 624         /* Reset registers */
 625         memset(regs, 0, sizeof(*regs));
 626
 627         regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
 628         regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
 629
 630         lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
 631 }
 632
 633 static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
 634 {
 635         struct lightrec_registers *regs;
 636
 637         regs = lightrec_get_registers(lightrec_state);
 638         memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
 639         memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
 640         if (need_cp2)
 641                 memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 642 }
 643
 644 static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
 645 {
 646         struct lightrec_registers *regs;
 647
 648         regs = lightrec_get_registers(lightrec_state);
 649         memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
 650         memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
 651         if (need_cp2)
 652                 memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 653 }
 654
 655 R3000Acpu psxRec =
 656 {
 657         lightrec_plugin_init,
 658         lightrec_plugin_reset,
 659         lightrec_plugin_execute,
 660         lightrec_plugin_execute_block,
 661         lightrec_plugin_clear,
 662         lightrec_plugin_notify,
 663         lightrec_plugin_apply_config,
 664         lightrec_plugin_shutdown,
 665 };