libpcsxcore/lightrec/plugin.c

   1 #include <lightrec.h>
   2 #include <errno.h>
   3 #include <stdbool.h>
   4 #include <stdio.h>
   5 #include <unistd.h>
   6 #include <signal.h>
   7 #include <assert.h>
   8
   9 #if P_HAVE_MMAP
  10 #include <sys/mman.h>
  11 #endif
  12
  13 #include "../cdrom.h"
  14 #include "../gpu.h"
  15 #include "../gte.h"
  16 #include "../mdec.h"
  17 #include "../psxdma.h"
  18 #include "../psxhw.h"
  19 #include "../psxmem.h"
  20 #include "../r3000a.h"
  21 #include "../psxinterpreter.h"
  22 #include "../psxhle.h"
  23 #include "../new_dynarec/events.h"
  24
  25 #include "../frontend/main.h"
  26
  27 #include "mem.h"
  28 #include "plugin.h"
  29
  30 #if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
  31 #error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
  32 #endif
  33
  34 #define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
  35
  36 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
  37 #       define LE32TOH(x)       __builtin_bswap32(x)
  38 #       define HTOLE32(x)       __builtin_bswap32(x)
  39 #       define LE16TOH(x)       __builtin_bswap16(x)
  40 #       define HTOLE16(x)       __builtin_bswap16(x)
  41 #else
  42 #       define LE32TOH(x)       (x)
  43 #       define HTOLE32(x)       (x)
  44 #       define LE16TOH(x)       (x)
  45 #       define HTOLE16(x)       (x)
  46 #endif
  47
  48 #ifdef __GNUC__
  49 #       define likely(x)       __builtin_expect(!!(x),1)
  50 #       define unlikely(x)     __builtin_expect(!!(x),0)
  51 #else
  52 #       define likely(x)       (x)
  53 #       define unlikely(x)     (x)
  54 #endif
  55
  56 psxRegisters psxRegs;
  57 Rcnt rcnts[4];
  58
  59 void* code_buffer;
  60
  61 static struct lightrec_state *lightrec_state;
  62
  63 static char *name = "retroarch.exe";
  64
  65 static bool use_lightrec_interpreter;
  66 static bool use_pcsx_interpreter;
  67 static bool block_stepping;
  68
  69 enum my_cp2_opcodes {
  70         OP_CP2_RTPS             = 0x01,
  71         OP_CP2_NCLIP            = 0x06,
  72         OP_CP2_OP               = 0x0c,
  73         OP_CP2_DPCS             = 0x10,
  74         OP_CP2_INTPL            = 0x11,
  75         OP_CP2_MVMVA            = 0x12,
  76         OP_CP2_NCDS             = 0x13,
  77         OP_CP2_CDP              = 0x14,
  78         OP_CP2_NCDT             = 0x16,
  79         OP_CP2_NCCS             = 0x1b,
  80         OP_CP2_CC               = 0x1c,
  81         OP_CP2_NCS              = 0x1e,
  82         OP_CP2_NCT              = 0x20,
  83         OP_CP2_SQR              = 0x28,
  84         OP_CP2_DCPL             = 0x29,
  85         OP_CP2_DPCT             = 0x2a,
  86         OP_CP2_AVSZ3            = 0x2d,
  87         OP_CP2_AVSZ4            = 0x2e,
  88         OP_CP2_RTPT             = 0x30,
  89         OP_CP2_GPF              = 0x3d,
  90         OP_CP2_GPL              = 0x3e,
  91         OP_CP2_NCCT             = 0x3f,
  92 };
  93
  94 static void (*cp2_ops[])(struct psxCP2Regs *) = {
  95         [OP_CP2_RTPS] = gteRTPS,
  96         [OP_CP2_RTPS] = gteRTPS,
  97         [OP_CP2_NCLIP] = gteNCLIP,
  98         [OP_CP2_OP] = gteOP,
  99         [OP_CP2_DPCS] = gteDPCS,
 100         [OP_CP2_INTPL] = gteINTPL,
 101         [OP_CP2_MVMVA] = gteMVMVA,
 102         [OP_CP2_NCDS] = gteNCDS,
 103         [OP_CP2_CDP] = gteCDP,
 104         [OP_CP2_NCDT] = gteNCDT,
 105         [OP_CP2_NCCS] = gteNCCS,
 106         [OP_CP2_CC] = gteCC,
 107         [OP_CP2_NCS] = gteNCS,
 108         [OP_CP2_NCT] = gteNCT,
 109         [OP_CP2_SQR] = gteSQR,
 110         [OP_CP2_DCPL] = gteDCPL,
 111         [OP_CP2_DPCT] = gteDPCT,
 112         [OP_CP2_AVSZ3] = gteAVSZ3,
 113         [OP_CP2_AVSZ4] = gteAVSZ4,
 114         [OP_CP2_RTPT] = gteRTPT,
 115         [OP_CP2_GPF] = gteGPF,
 116         [OP_CP2_GPL] = gteGPL,
 117         [OP_CP2_NCCT] = gteNCCT,
 118 };
 119
 120 static char cache_buf[64 * 1024];
 121
 122 static void cop2_op(struct lightrec_state *state, u32 func)
 123 {
 124         struct lightrec_registers *regs = lightrec_get_registers(state);
 125
 126         psxRegs.code = func;
 127
 128         if (unlikely(!cp2_ops[func & 0x3f])) {
 129                 fprintf(stderr, "Invalid CP2 function %u\n", func);
 130         } else {
 131                 /* This works because regs->cp2c comes right after regs->cp2d,
 132                  * so it can be cast to a pcsxCP2Regs pointer. */
 133                 cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
 134         }
 135 }
 136
 137 static bool has_interrupt(void)
 138 {
 139         struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
 140
 141         return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
 142                 (regs->cp0[12] & 0x401) == 0x401) ||
 143                 (regs->cp0[12] & regs->cp0[13] & 0x0300);
 144 }
 145
 146 static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
 147 {
 148         psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
 149         lightrec_reset_cycle_count(state, 0);
 150 }
 151
 152 static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
 153 {
 154         s32 cycles_left = next_interupt - psxRegs.cycle;
 155
 156         if (block_stepping || cycles_left <= 0 || has_interrupt())
 157                 lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
 158         else {
 159                 lightrec_set_target_cycle_count(state, cycles_left * 1024);
 160         }
 161 }
 162
 163 static void hw_write_byte(struct lightrec_state *state,
 164                           u32 op, void *host, u32 mem, u8 val)
 165 {
 166         lightrec_tansition_to_pcsx(state);
 167
 168         psxHwWrite8(mem, val);
 169
 170         lightrec_tansition_from_pcsx(state);
 171 }
 172
 173 static void hw_write_half(struct lightrec_state *state,
 174                           u32 op, void *host, u32 mem, u16 val)
 175 {
 176         lightrec_tansition_to_pcsx(state);
 177
 178         psxHwWrite16(mem, val);
 179
 180         lightrec_tansition_from_pcsx(state);
 181 }
 182
 183 static void hw_write_word(struct lightrec_state *state,
 184                           u32 op, void *host, u32 mem, u32 val)
 185 {
 186         lightrec_tansition_to_pcsx(state);
 187
 188         psxHwWrite32(mem, val);
 189
 190         lightrec_tansition_from_pcsx(state);
 191 }
 192
 193 static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
 194 {
 195         u8 val;
 196
 197         lightrec_tansition_to_pcsx(state);
 198
 199         val = psxHwRead8(mem);
 200
 201         lightrec_tansition_from_pcsx(state);
 202
 203         return val;
 204 }
 205
 206 static u16 hw_read_half(struct lightrec_state *state,
 207                         u32 op, void *host, u32 mem)
 208 {
 209         u16 val;
 210
 211         lightrec_tansition_to_pcsx(state);
 212
 213         val = psxHwRead16(mem);
 214
 215         lightrec_tansition_from_pcsx(state);
 216
 217         return val;
 218 }
 219
 220 static u32 hw_read_word(struct lightrec_state *state,
 221                         u32 op, void *host, u32 mem)
 222 {
 223         u32 val;
 224
 225         lightrec_tansition_to_pcsx(state);
 226
 227         val = psxHwRead32(mem);
 228
 229         lightrec_tansition_from_pcsx(state);
 230
 231         return val;
 232 }
 233
 234 static struct lightrec_mem_map_ops hw_regs_ops = {
 235         .sb = hw_write_byte,
 236         .sh = hw_write_half,
 237         .sw = hw_write_word,
 238         .lb = hw_read_byte,
 239         .lh = hw_read_half,
 240         .lw = hw_read_word,
 241 };
 242
 243 static u32 cache_ctrl;
 244
 245 static void cache_ctrl_write_word(struct lightrec_state *state,
 246                                   u32 op, void *host, u32 mem, u32 val)
 247 {
 248         cache_ctrl = val;
 249 }
 250
 251 static u32 cache_ctrl_read_word(struct lightrec_state *state,
 252                                 u32 op, void *host, u32 mem)
 253 {
 254         return cache_ctrl;
 255 }
 256
 257 static struct lightrec_mem_map_ops cache_ctrl_ops = {
 258         .sw = cache_ctrl_write_word,
 259         .lw = cache_ctrl_read_word,
 260 };
 261
 262 static struct lightrec_mem_map lightrec_map[] = {
 263         [PSX_MAP_KERNEL_USER_RAM] = {
 264                 /* Kernel and user memory */
 265                 .pc = 0x00000000,
 266                 .length = 0x200000,
 267         },
 268         [PSX_MAP_BIOS] = {
 269                 /* BIOS */
 270                 .pc = 0x1fc00000,
 271                 .length = 0x80000,
 272         },
 273         [PSX_MAP_SCRATCH_PAD] = {
 274                 /* Scratch pad */
 275                 .pc = 0x1f800000,
 276                 .length = 0x400,
 277         },
 278         [PSX_MAP_PARALLEL_PORT] = {
 279                 /* Parallel port */
 280                 .pc = 0x1f000000,
 281                 .length = 0x10000,
 282         },
 283         [PSX_MAP_HW_REGISTERS] = {
 284                 /* Hardware registers */
 285                 .pc = 0x1f801000,
 286                 .length = 0x8000,
 287                 .ops = &hw_regs_ops,
 288         },
 289         [PSX_MAP_CACHE_CONTROL] = {
 290                 /* Cache control */
 291                 .pc = 0x5ffe0130,
 292                 .length = 4,
 293                 .ops = &cache_ctrl_ops,
 294         },
 295
 296         /* Mirrors of the kernel/user memory */
 297         [PSX_MAP_MIRROR1] = {
 298                 .pc = 0x00200000,
 299                 .length = 0x200000,
 300                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 301         },
 302         [PSX_MAP_MIRROR2] = {
 303                 .pc = 0x00400000,
 304                 .length = 0x200000,
 305                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 306         },
 307         [PSX_MAP_MIRROR3] = {
 308                 .pc = 0x00600000,
 309                 .length = 0x200000,
 310                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 311         },
 312
 313         /* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
 314         [PSX_MAP_PPORT_MIRROR] = {
 315                 .pc = 0x1fa00000,
 316                 .length = 0x10000,
 317                 .mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
 318         },
 319
 320         /* Code buffer */
 321         [PSX_MAP_CODE_BUFFER] = {
 322                 .length = CODE_BUFFER_SIZE,
 323         },
 324 };
 325
 326 static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
 327 {
 328         if (enable)
 329                 memcpy(psxM, cache_buf, sizeof(cache_buf));
 330         else
 331                 memcpy(cache_buf, psxM, sizeof(cache_buf));
 332 }
 333
 334 static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
 335 {
 336         switch (size) {
 337         case 8:
 338                 switch (kaddr) {
 339                 case 0x1f801040:
 340                 case 0x1f801050:
 341                 case 0x1f801800:
 342                 case 0x1f801801:
 343                 case 0x1f801802:
 344                 case 0x1f801803:
 345                         return false;
 346                 default:
 347                         return true;
 348                 }
 349         case 16:
 350                 switch (kaddr) {
 351                 case 0x1f801040:
 352                 case 0x1f801044:
 353                 case 0x1f801048:
 354                 case 0x1f80104a:
 355                 case 0x1f80104e:
 356                 case 0x1f801050:
 357                 case 0x1f801054:
 358                 case 0x1f80105a:
 359                 case 0x1f80105e:
 360                 case 0x1f801100:
 361                 case 0x1f801104:
 362                 case 0x1f801108:
 363                 case 0x1f801110:
 364                 case 0x1f801114:
 365                 case 0x1f801118:
 366                 case 0x1f801120:
 367                 case 0x1f801124:
 368                 case 0x1f801128:
 369                         return false;
 370                 case 0x1f801070:
 371                 case 0x1f801074:
 372                         return !is_write;
 373                 default:
 374                         return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 375                 }
 376         default:
 377                 switch (kaddr) {
 378                 case 0x1f801040:
 379                 case 0x1f801050:
 380                 case 0x1f801100:
 381                 case 0x1f801104:
 382                 case 0x1f801108:
 383                 case 0x1f801110:
 384                 case 0x1f801114:
 385                 case 0x1f801118:
 386                 case 0x1f801120:
 387                 case 0x1f801124:
 388                 case 0x1f801128:
 389                 case 0x1f801810:
 390                 case 0x1f801814:
 391                 case 0x1f801820:
 392                 case 0x1f801824:
 393                         return false;
 394                 case 0x1f801070:
 395                 case 0x1f801074:
 396                 case 0x1f801088:
 397                 case 0x1f801098:
 398                 case 0x1f8010a8:
 399                 case 0x1f8010b8:
 400                 case 0x1f8010c8:
 401                 case 0x1f8010e8:
 402                 case 0x1f8010f4:
 403                         return !is_write;
 404                 default:
 405                         return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 406                 }
 407         }
 408 }
 409
 410 #if defined(HW_DOL) || defined(HW_RVL)
 411 static void lightrec_code_inv(void *ptr, uint32_t len)
 412 {
 413         extern void DCFlushRange(void *ptr, u32 len);
 414         extern void ICInvalidateRange(void *ptr, u32 len);
 415
 416         DCFlushRange(ptr, len);
 417         ICInvalidateRange(ptr, len);
 418 }
 419 #elif defined(HW_WUP)
 420 static void lightrec_code_inv(void *ptr, uint32_t len)
 421 {
 422         wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
 423 }
 424 #endif
 425
 426 static const struct lightrec_ops lightrec_ops = {
 427         .cop2_op = cop2_op,
 428         .enable_ram = lightrec_enable_ram,
 429         .hw_direct = lightrec_can_hw_direct,
 430 #if defined(HW_DOL) || defined(HW_RVL) || defined(HW_WUP)
 431         .code_inv = lightrec_code_inv,
 432 #endif
 433 };
 434
 435 static int lightrec_plugin_init(void)
 436 {
 437         lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
 438         lightrec_map[PSX_MAP_BIOS].address = psxR;
 439         lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
 440         lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
 441         lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
 442
 443         if (!LIGHTREC_CUSTOM_MAP) {
 444 #if P_HAVE_MMAP
 445                 code_buffer = mmap(0, CODE_BUFFER_SIZE,
 446                                    PROT_EXEC | PROT_READ | PROT_WRITE,
 447                                    MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 448                 if (code_buffer == MAP_FAILED)
 449                         return -ENOMEM;
 450 #else
 451                 code_buffer = malloc(CODE_BUFFER_SIZE);
 452                 if (!code_buffer)
 453                         return -ENOMEM;
 454 #endif
 455         }
 456
 457         if (LIGHTREC_CUSTOM_MAP) {
 458                 lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
 459                 lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
 460                 lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
 461         }
 462
 463         lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
 464
 465         use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
 466
 467         lightrec_state = lightrec_init(name,
 468                         lightrec_map, ARRAY_SIZE(lightrec_map),
 469                         &lightrec_ops);
 470
 471         // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
 472         //              (uintptr_t) psxM,
 473         //              (uintptr_t) psxP,
 474         //              (uintptr_t) psxR,
 475         //              (uintptr_t) psxH);
 476
 477 #ifndef _WIN32
 478         signal(SIGPIPE, exit);
 479 #endif
 480         return 0;
 481 }
 482
 483 static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
 484 static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);
 485
 486 static void lightrec_plugin_execute_internal(bool block_only)
 487 {
 488         struct lightrec_registers *regs;
 489         u32 flags, cycles_pcsx;
 490
 491         regs = lightrec_get_registers(lightrec_state);
 492         gen_interupt((psxCP0Regs *)regs->cp0);
 493         cycles_pcsx = next_interupt - psxRegs.cycle;
 494         assert((s32)cycles_pcsx > 0);
 495
 496         // step during early boot so that 0x80030000 fastboot hack works
 497         block_stepping = block_only;
 498         if (block_only)
 499                 cycles_pcsx = 0;
 500
 501         if (use_pcsx_interpreter) {
 502                 intExecuteBlock(0);
 503         } else {
 504                 u32 cycles_lightrec = cycles_pcsx * 1024;
 505                 if (unlikely(use_lightrec_interpreter)) {
 506                         psxRegs.pc = lightrec_run_interpreter(lightrec_state,
 507                                                               psxRegs.pc,
 508                                                               cycles_lightrec);
 509                 } else {
 510                         psxRegs.pc = lightrec_execute(lightrec_state,
 511                                                       psxRegs.pc, cycles_lightrec);
 512                 }
 513
 514                 lightrec_tansition_to_pcsx(lightrec_state);
 515
 516                 flags = lightrec_exit_flags(lightrec_state);
 517
 518                 if (flags & LIGHTREC_EXIT_SEGFAULT) {
 519                         fprintf(stderr, "Exiting at cycle 0x%08x\n",
 520                                 psxRegs.cycle);
 521                         exit(1);
 522                 }
 523
 524                 if (flags & LIGHTREC_EXIT_SYSCALL)
 525                         psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
 526                 else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
 527                         u32 op = intFakeFetch(psxRegs.pc);
 528                         u32 hlec = op & 0x03ffffff;
 529                         if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
 530                                 lightrec_plugin_sync_regs_to_pcsx(0);
 531                                 psxHLEt[hlec]();
 532                                 lightrec_plugin_sync_regs_from_pcsx(0);
 533                         }
 534                         else
 535                                 psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
 536                 }
 537         }
 538
 539         if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
 540                 /* Handle software interrupts */
 541                 regs->cp0[13] &= ~0x7c;
 542                 psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
 543         }
 544 }
 545
 546 static void lightrec_plugin_execute(void)
 547 {
 548         extern int stop;
 549
 550         while (!stop)
 551                 lightrec_plugin_execute_internal(false);
 552 }
 553
 554 static void lightrec_plugin_execute_block(enum blockExecCaller caller)
 555 {
 556         lightrec_plugin_execute_internal(true);
 557 }
 558
 559 static void lightrec_plugin_clear(u32 addr, u32 size)
 560 {
 561         if (addr == 0 && size == UINT32_MAX)
 562                 lightrec_invalidate_all(lightrec_state);
 563         else
 564                 /* size * 4: PCSX uses DMA units */
 565                 lightrec_invalidate(lightrec_state, addr, size * 4);
 566 }
 567
 568 static void lightrec_plugin_notify(enum R3000Anote note, void *data)
 569 {
 570         switch (note)
 571         {
 572         case R3000ACPU_NOTIFY_CACHE_ISOLATED:
 573         case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
 574                 /* not used, lightrec calls lightrec_enable_ram() instead */
 575                 break;
 576         case R3000ACPU_NOTIFY_BEFORE_SAVE:
 577                 /* non-null 'data' means this is HLE related sync */
 578                 lightrec_plugin_sync_regs_to_pcsx(data == NULL);
 579                 break;
 580         case R3000ACPU_NOTIFY_AFTER_LOAD:
 581                 lightrec_plugin_sync_regs_from_pcsx(data == NULL);
 582                 if (data == NULL)
 583                         lightrec_invalidate_all(lightrec_state);
 584                 break;
 585         }
 586 }
 587
 588 static void lightrec_plugin_apply_config()
 589 {
 590         u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
 591                 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
 592         assert(cycle_mult);
 593
 594         lightrec_set_cycles_per_opcode(lightrec_state, cycle_mult * 1024 / 100);
 595 }
 596
 597 static void lightrec_plugin_shutdown(void)
 598 {
 599         lightrec_destroy(lightrec_state);
 600
 601         if (!LIGHTREC_CUSTOM_MAP) {
 602 #if P_HAVE_MMAP
 603                 munmap(code_buffer, CODE_BUFFER_SIZE);
 604 #else
 605                 free(code_buffer);
 606 #endif
 607         }
 608 }
 609
 610 static void lightrec_plugin_reset(void)
 611 {
 612         struct lightrec_registers *regs;
 613
 614         regs = lightrec_get_registers(lightrec_state);
 615
 616         /* Invalidate all blocks */
 617         lightrec_invalidate_all(lightrec_state);
 618
 619         /* Reset registers */
 620         memset(regs, 0, sizeof(*regs));
 621
 622         regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
 623         regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
 624 }
 625
 626 static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
 627 {
 628         struct lightrec_registers *regs;
 629
 630         regs = lightrec_get_registers(lightrec_state);
 631         memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
 632         memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
 633         if (need_cp2)
 634                 memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 635 }
 636
 637 static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
 638 {
 639         struct lightrec_registers *regs;
 640
 641         regs = lightrec_get_registers(lightrec_state);
 642         memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
 643         memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
 644         if (need_cp2)
 645                 memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 646 }
 647
 648 R3000Acpu psxRec =
 649 {
 650         lightrec_plugin_init,
 651         lightrec_plugin_reset,
 652         lightrec_plugin_execute,
 653         lightrec_plugin_execute_block,
 654         lightrec_plugin_clear,
 655         lightrec_plugin_notify,
 656         lightrec_plugin_apply_config,
 657         lightrec_plugin_shutdown,
 658 };