libpcsxcore/lightrec/plugin.c

   1 #include <errno.h>
   2 #include <stdbool.h>
   3 #include <stdio.h>
   4 #include <unistd.h>
   5 #include <signal.h>
   6 #include <assert.h>
   7
   8 #if P_HAVE_MMAP
   9 #include <sys/mman.h>
  10 #endif
  11
  12 #include "lightrec.h"
  13 #include "../cdrom.h"
  14 #include "../gpu.h"
  15 #include "../gte.h"
  16 #include "../mdec.h"
  17 #include "../psxdma.h"
  18 #include "../psxhw.h"
  19 #include "../psxmem.h"
  20 #include "../r3000a.h"
  21 #include "../psxinterpreter.h"
  22 #include "../psxhle.h"
  23 #include "../psxevents.h"
  24
  25 #include "../frontend/main.h"
  26
  27 #include "mem.h"
  28 #include "plugin.h"
  29
  30 #if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
  31 #error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
  32 #endif
  33
  34 #define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
  35
  36 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
  37 #       define LE32TOH(x)       __builtin_bswap32(x)
  38 #       define HTOLE32(x)       __builtin_bswap32(x)
  39 #       define LE16TOH(x)       __builtin_bswap16(x)
  40 #       define HTOLE16(x)       __builtin_bswap16(x)
  41 #else
  42 #       define LE32TOH(x)       (x)
  43 #       define HTOLE32(x)       (x)
  44 #       define LE16TOH(x)       (x)
  45 #       define HTOLE16(x)       (x)
  46 #endif
  47
  48 #ifdef __GNUC__
  49 #       define likely(x)       __builtin_expect(!!(x),1)
  50 #       define unlikely(x)     __builtin_expect(!!(x),0)
  51 #else
  52 #       define likely(x)       (x)
  53 #       define unlikely(x)     (x)
  54 #endif
  55
  56 #ifndef LIGHTREC_PROG_NAME
  57 #  ifdef __linux__
  58 #    define LIGHTREC_PROG_NAME "/proc/self/exe"
  59 #  else
  60 #    define LIGHTREC_PROG_NAME "retroarch.exe"
  61 #  endif
  62 #endif
  63
  64 psxRegisters psxRegs;
  65 Rcnt rcnts[4];
  66
  67 void* code_buffer;
  68
  69 static struct lightrec_state *lightrec_state;
  70
  71 static bool use_lightrec_interpreter;
  72 static bool use_pcsx_interpreter;
  73 static bool block_stepping;
  74
  75 extern u32 lightrec_hacks;
  76
  77 extern void lightrec_code_inv(void *ptr, uint32_t len);
  78
  79 enum my_cp2_opcodes {
  80         OP_CP2_RTPS             = 0x01,
  81         OP_CP2_NCLIP            = 0x06,
  82         OP_CP2_OP               = 0x0c,
  83         OP_CP2_DPCS             = 0x10,
  84         OP_CP2_INTPL            = 0x11,
  85         OP_CP2_MVMVA            = 0x12,
  86         OP_CP2_NCDS             = 0x13,
  87         OP_CP2_CDP              = 0x14,
  88         OP_CP2_NCDT             = 0x16,
  89         OP_CP2_NCCS             = 0x1b,
  90         OP_CP2_CC               = 0x1c,
  91         OP_CP2_NCS              = 0x1e,
  92         OP_CP2_NCT              = 0x20,
  93         OP_CP2_SQR              = 0x28,
  94         OP_CP2_DCPL             = 0x29,
  95         OP_CP2_DPCT             = 0x2a,
  96         OP_CP2_AVSZ3            = 0x2d,
  97         OP_CP2_AVSZ4            = 0x2e,
  98         OP_CP2_RTPT             = 0x30,
  99         OP_CP2_GPF              = 0x3d,
 100         OP_CP2_GPL              = 0x3e,
 101         OP_CP2_NCCT             = 0x3f,
 102 };
 103
 104 static void (*cp2_ops[])(struct psxCP2Regs *) = {
 105         [OP_CP2_RTPS] = gteRTPS,
 106         [OP_CP2_RTPS] = gteRTPS,
 107         [OP_CP2_NCLIP] = gteNCLIP,
 108         [OP_CP2_OP] = gteOP,
 109         [OP_CP2_DPCS] = gteDPCS,
 110         [OP_CP2_INTPL] = gteINTPL,
 111         [OP_CP2_MVMVA] = gteMVMVA,
 112         [OP_CP2_NCDS] = gteNCDS,
 113         [OP_CP2_CDP] = gteCDP,
 114         [OP_CP2_NCDT] = gteNCDT,
 115         [OP_CP2_NCCS] = gteNCCS,
 116         [OP_CP2_CC] = gteCC,
 117         [OP_CP2_NCS] = gteNCS,
 118         [OP_CP2_NCT] = gteNCT,
 119         [OP_CP2_SQR] = gteSQR,
 120         [OP_CP2_DCPL] = gteDCPL,
 121         [OP_CP2_DPCT] = gteDPCT,
 122         [OP_CP2_AVSZ3] = gteAVSZ3,
 123         [OP_CP2_AVSZ4] = gteAVSZ4,
 124         [OP_CP2_RTPT] = gteRTPT,
 125         [OP_CP2_GPF] = gteGPF,
 126         [OP_CP2_GPL] = gteGPL,
 127         [OP_CP2_NCCT] = gteNCCT,
 128 };
 129
 130 static char cache_buf[64 * 1024];
 131
 132 static void cop2_op(struct lightrec_state *state, u32 func)
 133 {
 134         struct lightrec_registers *regs = lightrec_get_registers(state);
 135
 136         psxRegs.code = func;
 137
 138         if (unlikely(!cp2_ops[func & 0x3f])) {
 139                 fprintf(stderr, "Invalid CP2 function %u\n", func);
 140         } else {
 141                 /* This works because regs->cp2c comes right after regs->cp2d,
 142                  * so it can be cast to a pcsxCP2Regs pointer. */
 143                 cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
 144         }
 145 }
 146
 147 static bool has_interrupt(void)
 148 {
 149         struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
 150
 151         return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
 152                 (regs->cp0[12] & 0x401) == 0x401) ||
 153                 (regs->cp0[12] & regs->cp0[13] & 0x0300);
 154 }
 155
 156 static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
 157 {
 158         psxRegs.cycle += lightrec_current_cycle_count(state) / 1024;
 159         lightrec_reset_cycle_count(state, 0);
 160 }
 161
 162 static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
 163 {
 164         s32 cycles_left = next_interupt - psxRegs.cycle;
 165
 166         if (block_stepping || cycles_left <= 0 || has_interrupt())
 167                 lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
 168         else {
 169                 lightrec_set_target_cycle_count(state, cycles_left * 1024);
 170         }
 171 }
 172
 173 static void hw_write_byte(struct lightrec_state *state,
 174                           u32 op, void *host, u32 mem, u32 val)
 175 {
 176         lightrec_tansition_to_pcsx(state);
 177
 178         psxHwWrite8(mem, val);
 179
 180         lightrec_tansition_from_pcsx(state);
 181 }
 182
 183 static void hw_write_half(struct lightrec_state *state,
 184                           u32 op, void *host, u32 mem, u32 val)
 185 {
 186         lightrec_tansition_to_pcsx(state);
 187
 188         psxHwWrite16(mem, val);
 189
 190         lightrec_tansition_from_pcsx(state);
 191 }
 192
 193 static void hw_write_word(struct lightrec_state *state,
 194                           u32 op, void *host, u32 mem, u32 val)
 195 {
 196         lightrec_tansition_to_pcsx(state);
 197
 198         psxHwWrite32(mem, val);
 199
 200         lightrec_tansition_from_pcsx(state);
 201 }
 202
 203 static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
 204 {
 205         u8 val;
 206
 207         lightrec_tansition_to_pcsx(state);
 208
 209         val = psxHwRead8(mem);
 210
 211         lightrec_tansition_from_pcsx(state);
 212
 213         return val;
 214 }
 215
 216 static u16 hw_read_half(struct lightrec_state *state,
 217                         u32 op, void *host, u32 mem)
 218 {
 219         u16 val;
 220
 221         lightrec_tansition_to_pcsx(state);
 222
 223         val = psxHwRead16(mem);
 224
 225         lightrec_tansition_from_pcsx(state);
 226
 227         return val;
 228 }
 229
 230 static u32 hw_read_word(struct lightrec_state *state,
 231                         u32 op, void *host, u32 mem)
 232 {
 233         u32 val;
 234
 235         lightrec_tansition_to_pcsx(state);
 236
 237         val = psxHwRead32(mem);
 238
 239         lightrec_tansition_from_pcsx(state);
 240
 241         return val;
 242 }
 243
 244 static struct lightrec_mem_map_ops hw_regs_ops = {
 245         .sb = hw_write_byte,
 246         .sh = hw_write_half,
 247         .sw = hw_write_word,
 248         .lb = hw_read_byte,
 249         .lh = hw_read_half,
 250         .lw = hw_read_word,
 251 };
 252
 253 static u32 cache_ctrl;
 254
 255 static void cache_ctrl_write_word(struct lightrec_state *state,
 256                                   u32 op, void *host, u32 mem, u32 val)
 257 {
 258         cache_ctrl = val;
 259 }
 260
 261 static u32 cache_ctrl_read_word(struct lightrec_state *state,
 262                                 u32 op, void *host, u32 mem)
 263 {
 264         return cache_ctrl;
 265 }
 266
 267 static struct lightrec_mem_map_ops cache_ctrl_ops = {
 268         .sw = cache_ctrl_write_word,
 269         .lw = cache_ctrl_read_word,
 270 };
 271
 272 static struct lightrec_mem_map lightrec_map[] = {
 273         [PSX_MAP_KERNEL_USER_RAM] = {
 274                 /* Kernel and user memory */
 275                 .pc = 0x00000000,
 276                 .length = 0x200000,
 277         },
 278         [PSX_MAP_BIOS] = {
 279                 /* BIOS */
 280                 .pc = 0x1fc00000,
 281                 .length = 0x80000,
 282         },
 283         [PSX_MAP_SCRATCH_PAD] = {
 284                 /* Scratch pad */
 285                 .pc = 0x1f800000,
 286                 .length = 0x400,
 287         },
 288         [PSX_MAP_PARALLEL_PORT] = {
 289                 /* Parallel port */
 290                 .pc = 0x1f000000,
 291                 .length = 0x10000,
 292         },
 293         [PSX_MAP_HW_REGISTERS] = {
 294                 /* Hardware registers */
 295                 .pc = 0x1f801000,
 296                 .length = 0x8000,
 297                 .ops = &hw_regs_ops,
 298         },
 299         [PSX_MAP_CACHE_CONTROL] = {
 300                 /* Cache control */
 301                 .pc = 0x5ffe0130,
 302                 .length = 4,
 303                 .ops = &cache_ctrl_ops,
 304         },
 305
 306         /* Mirrors of the kernel/user memory */
 307         [PSX_MAP_MIRROR1] = {
 308                 .pc = 0x00200000,
 309                 .length = 0x200000,
 310                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 311         },
 312         [PSX_MAP_MIRROR2] = {
 313                 .pc = 0x00400000,
 314                 .length = 0x200000,
 315                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 316         },
 317         [PSX_MAP_MIRROR3] = {
 318                 .pc = 0x00600000,
 319                 .length = 0x200000,
 320                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 321         },
 322
 323         /* Mirror of the parallel port. Only used by the PS2/PS3 BIOS */
 324         [PSX_MAP_PPORT_MIRROR] = {
 325                 .pc = 0x1fa00000,
 326                 .length = 0x10000,
 327                 .mirror_of = &lightrec_map[PSX_MAP_PARALLEL_PORT],
 328         },
 329
 330         /* Code buffer */
 331         [PSX_MAP_CODE_BUFFER] = {
 332                 .length = CODE_BUFFER_SIZE,
 333         },
 334 };
 335
 336 static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
 337 {
 338         if (enable)
 339                 memcpy(psxM, cache_buf, sizeof(cache_buf));
 340         else
 341                 memcpy(cache_buf, psxM, sizeof(cache_buf));
 342 }
 343
 344 static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
 345 {
 346         if (is_write && size != 32) {
 347                 // force32 so must go through handlers
 348                 if (0x1f801000 <= kaddr && kaddr < 0x1f801024)
 349                         return false;
 350                 if ((kaddr & 0x1fffff80) == 0x1f801080) // dma
 351                         return false;
 352         }
 353
 354         switch (size) {
 355         case 8:
 356                 switch (kaddr) {
 357                 case 0x1f801040:
 358                 case 0x1f801050:
 359                 case 0x1f801800:
 360                 case 0x1f801801:
 361                 case 0x1f801802:
 362                 case 0x1f801803:
 363                         return false;
 364                 default:
 365                         return true;
 366                 }
 367         case 16:
 368                 switch (kaddr) {
 369                 case 0x1f801040:
 370                 case 0x1f801044:
 371                 case 0x1f801048:
 372                 case 0x1f80104a:
 373                 case 0x1f80104e:
 374                 case 0x1f801050:
 375                 case 0x1f801054:
 376                 case 0x1f80105a:
 377                 case 0x1f80105e:
 378                 case 0x1f801100:
 379                 case 0x1f801104:
 380                 case 0x1f801108:
 381                 case 0x1f801110:
 382                 case 0x1f801114:
 383                 case 0x1f801118:
 384                 case 0x1f801120:
 385                 case 0x1f801124:
 386                 case 0x1f801128:
 387                         return false;
 388                 case 0x1f801070:
 389                 case 0x1f801074:
 390                         return !is_write;
 391                 default:
 392                         return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 393                 }
 394         default:
 395                 switch (kaddr) {
 396                 case 0x1f801040:
 397                 case 0x1f801050:
 398                 case 0x1f801100:
 399                 case 0x1f801104:
 400                 case 0x1f801108:
 401                 case 0x1f801110:
 402                 case 0x1f801114:
 403                 case 0x1f801118:
 404                 case 0x1f801120:
 405                 case 0x1f801124:
 406                 case 0x1f801128:
 407                 case 0x1f801810:
 408                 case 0x1f801814:
 409                 case 0x1f801820:
 410                 case 0x1f801824:
 411                         return false;
 412                 case 0x1f801070:
 413                 case 0x1f801074:
 414                 case 0x1f801088:
 415                 case 0x1f801098:
 416                 case 0x1f8010a8:
 417                 case 0x1f8010b8:
 418                 case 0x1f8010c8:
 419                 case 0x1f8010e8:
 420                 case 0x1f8010f4:
 421                         return !is_write;
 422                 default:
 423                         return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 424                 }
 425         }
 426 }
 427
 428 static const struct lightrec_ops lightrec_ops = {
 429         .cop2_op = cop2_op,
 430         .enable_ram = lightrec_enable_ram,
 431         .hw_direct = lightrec_can_hw_direct,
 432         .code_inv = LIGHTREC_CODE_INV ? lightrec_code_inv : NULL,
 433 };
 434
 435 static int lightrec_plugin_init(void)
 436 {
 437         lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
 438         lightrec_map[PSX_MAP_BIOS].address = psxR;
 439         lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
 440         lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
 441         lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
 442
 443         if (!LIGHTREC_CUSTOM_MAP) {
 444 #if P_HAVE_MMAP
 445                 code_buffer = mmap(0, CODE_BUFFER_SIZE,
 446                                    PROT_EXEC | PROT_READ | PROT_WRITE,
 447                                    MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 448                 if (code_buffer == MAP_FAILED)
 449                         return -ENOMEM;
 450 #else
 451                 code_buffer = malloc(CODE_BUFFER_SIZE);
 452                 if (!code_buffer)
 453                         return -ENOMEM;
 454 #endif
 455         }
 456
 457         if (LIGHTREC_CUSTOM_MAP) {
 458                 lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
 459                 lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
 460                 lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
 461         }
 462
 463         lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
 464
 465         use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
 466
 467         lightrec_state = lightrec_init(LIGHTREC_PROG_NAME,
 468                         lightrec_map, ARRAY_SIZE(lightrec_map),
 469                         &lightrec_ops);
 470
 471         // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
 472         //              (uintptr_t) psxM,
 473         //              (uintptr_t) psxP,
 474         //              (uintptr_t) psxR,
 475         //              (uintptr_t) psxH);
 476
 477 #ifndef _WIN32
 478         signal(SIGPIPE, exit);
 479 #endif
 480         return 0;
 481 }
 482
 483 static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2);
 484 static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2);
 485
 486 static void lightrec_plugin_execute_internal(bool block_only)
 487 {
 488         struct lightrec_registers *regs;
 489         u32 flags, cycles_pcsx;
 490
 491         regs = lightrec_get_registers(lightrec_state);
 492         gen_interupt((psxCP0Regs *)regs->cp0);
 493         if (!block_only && stop)
 494                 return;
 495
 496         cycles_pcsx = next_interupt - psxRegs.cycle;
 497         assert((s32)cycles_pcsx > 0);
 498
 499         // step during early boot so that 0x80030000 fastboot hack works
 500         block_stepping = block_only;
 501         if (block_only)
 502                 cycles_pcsx = 0;
 503
 504         if (use_pcsx_interpreter) {
 505                 intExecuteBlock(0);
 506         } else {
 507                 u32 cycles_lightrec = cycles_pcsx * 1024;
 508                 if (unlikely(use_lightrec_interpreter)) {
 509                         psxRegs.pc = lightrec_run_interpreter(lightrec_state,
 510                                                               psxRegs.pc,
 511                                                               cycles_lightrec);
 512                 } else {
 513                         psxRegs.pc = lightrec_execute(lightrec_state,
 514                                                       psxRegs.pc, cycles_lightrec);
 515                 }
 516
 517                 lightrec_tansition_to_pcsx(lightrec_state);
 518
 519                 flags = lightrec_exit_flags(lightrec_state);
 520
 521                 if (flags & LIGHTREC_EXIT_SEGFAULT) {
 522                         fprintf(stderr, "Exiting at cycle 0x%08x\n",
 523                                 psxRegs.cycle);
 524                         exit(1);
 525                 }
 526
 527                 if (flags & LIGHTREC_EXIT_SYSCALL)
 528                         psxException(R3000E_Syscall << 2, 0, (psxCP0Regs *)regs->cp0);
 529                 if (flags & LIGHTREC_EXIT_BREAK)
 530                         psxException(R3000E_Bp << 2, 0, (psxCP0Regs *)regs->cp0);
 531                 else if (flags & LIGHTREC_EXIT_UNKNOWN_OP) {
 532                         u32 op = intFakeFetch(psxRegs.pc);
 533                         u32 hlec = op & 0x03ffffff;
 534                         if ((op >> 26) == 0x3b && hlec < ARRAY_SIZE(psxHLEt) && Config.HLE) {
 535                                 lightrec_plugin_sync_regs_to_pcsx(0);
 536                                 psxHLEt[hlec]();
 537                                 lightrec_plugin_sync_regs_from_pcsx(0);
 538                         }
 539                         else
 540                                 psxException(R3000E_RI << 2, 0, (psxCP0Regs *)regs->cp0);
 541                 }
 542         }
 543
 544         if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
 545                 /* Handle software interrupts */
 546                 regs->cp0[13] &= ~0x7c;
 547                 psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
 548         }
 549 }
 550
 551 static void lightrec_plugin_execute(void)
 552 {
 553         while (!stop)
 554                 lightrec_plugin_execute_internal(false);
 555 }
 556
 557 static void lightrec_plugin_execute_block(enum blockExecCaller caller)
 558 {
 559         lightrec_plugin_execute_internal(true);
 560 }
 561
 562 static void lightrec_plugin_clear(u32 addr, u32 size)
 563 {
 564         if ((addr == 0 && size == UINT32_MAX)
 565             || (lightrec_hacks & LIGHTREC_OPT_INV_DMA_ONLY))
 566                 lightrec_invalidate_all(lightrec_state);
 567         else
 568                 /* size * 4: PCSX uses DMA units */
 569                 lightrec_invalidate(lightrec_state, addr, size * 4);
 570 }
 571
 572 static void lightrec_plugin_notify(enum R3000Anote note, void *data)
 573 {
 574         switch (note)
 575         {
 576         case R3000ACPU_NOTIFY_CACHE_ISOLATED:
 577         case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
 578                 /* not used, lightrec calls lightrec_enable_ram() instead */
 579                 break;
 580         case R3000ACPU_NOTIFY_BEFORE_SAVE:
 581                 /* non-null 'data' means this is HLE related sync */
 582                 lightrec_plugin_sync_regs_to_pcsx(data == NULL);
 583                 break;
 584         case R3000ACPU_NOTIFY_AFTER_LOAD:
 585                 lightrec_plugin_sync_regs_from_pcsx(data == NULL);
 586                 if (data == NULL)
 587                         lightrec_invalidate_all(lightrec_state);
 588                 break;
 589         }
 590 }
 591
 592 static void lightrec_plugin_apply_config()
 593 {
 594         static u32 cycles_per_op_old;
 595         u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
 596                 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
 597         u32 cycles_per_op = cycle_mult * 1024 / 100;
 598         assert(cycles_per_op);
 599
 600         if (cycles_per_op_old && cycles_per_op_old != cycles_per_op) {
 601                 SysPrintf("lightrec: reinit block cache for cycles_per_op %.2f\n",
 602                         cycles_per_op / 1024.f);
 603         }
 604         cycles_per_op_old = cycles_per_op;
 605         lightrec_set_cycles_per_opcode(lightrec_state, cycles_per_op);
 606 }
 607
 608 static void lightrec_plugin_shutdown(void)
 609 {
 610         lightrec_destroy(lightrec_state);
 611
 612         if (!LIGHTREC_CUSTOM_MAP) {
 613 #if P_HAVE_MMAP
 614                 munmap(code_buffer, CODE_BUFFER_SIZE);
 615 #else
 616                 free(code_buffer);
 617 #endif
 618         }
 619 }
 620
 621 static void lightrec_plugin_reset(void)
 622 {
 623         struct lightrec_registers *regs;
 624
 625         regs = lightrec_get_registers(lightrec_state);
 626
 627         /* Invalidate all blocks */
 628         lightrec_invalidate_all(lightrec_state);
 629
 630         /* Reset registers */
 631         memset(regs, 0, sizeof(*regs));
 632
 633         regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
 634         regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
 635
 636         lightrec_set_unsafe_opt_flags(lightrec_state, lightrec_hacks);
 637 }
 638
 639 static void lightrec_plugin_sync_regs_from_pcsx(bool need_cp2)
 640 {
 641         struct lightrec_registers *regs;
 642
 643         regs = lightrec_get_registers(lightrec_state);
 644         memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
 645         memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
 646         if (need_cp2)
 647                 memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 648 }
 649
 650 static void lightrec_plugin_sync_regs_to_pcsx(bool need_cp2)
 651 {
 652         struct lightrec_registers *regs;
 653
 654         regs = lightrec_get_registers(lightrec_state);
 655         memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
 656         memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
 657         if (need_cp2)
 658                 memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 659 }
 660
 661 R3000Acpu psxRec =
 662 {
 663         lightrec_plugin_init,
 664         lightrec_plugin_reset,
 665         lightrec_plugin_execute,
 666         lightrec_plugin_execute_block,
 667         lightrec_plugin_clear,
 668         lightrec_plugin_notify,
 669         lightrec_plugin_apply_config,
 670         lightrec_plugin_shutdown,
 671 };