libpcsxcore/lightrec/plugin.c

   1 #include <lightrec.h>
   2 #include <stdbool.h>
   3 #include <stdio.h>
   4 #include <unistd.h>
   5 #include <signal.h>
   6
   7 #include "../cdrom.h"
   8 #include "../gpu.h"
   9 #include "../gte.h"
  10 #include "../mdec.h"
  11 #include "../psxdma.h"
  12 #include "../psxhw.h"
  13 #include "../psxmem.h"
  14 #include "../r3000a.h"
  15
  16 #include "../frontend/main.h"
  17
  18 #include "mem.h"
  19 #include "plugin.h"
  20
  21 #if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
  22 #error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
  23 #endif
  24
  25 #define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
  26
  27 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
  28 #       define LE32TOH(x)       __builtin_bswap32(x)
  29 #       define HTOLE32(x)       __builtin_bswap32(x)
  30 #       define LE16TOH(x)       __builtin_bswap16(x)
  31 #       define HTOLE16(x)       __builtin_bswap16(x)
  32 #else
  33 #       define LE32TOH(x)       (x)
  34 #       define HTOLE32(x)       (x)
  35 #       define LE16TOH(x)       (x)
  36 #       define HTOLE16(x)       (x)
  37 #endif
  38
  39 #ifdef __GNUC__
  40 #       define likely(x)       __builtin_expect(!!(x),1)
  41 #       define unlikely(x)     __builtin_expect(!!(x),0)
  42 #else
  43 #       define likely(x)       (x)
  44 #       define unlikely(x)     (x)
  45 #endif
  46
  47 psxRegisters psxRegs;
  48 Rcnt rcnts[4];
  49
  50 static struct lightrec_state *lightrec_state;
  51
  52 static char *name = "retroarch.exe";
  53
  54 static bool use_lightrec_interpreter;
  55 static bool use_pcsx_interpreter;
  56 static bool booting;
  57
  58 enum my_cp2_opcodes {
  59         OP_CP2_RTPS             = 0x01,
  60         OP_CP2_NCLIP            = 0x06,
  61         OP_CP2_OP               = 0x0c,
  62         OP_CP2_DPCS             = 0x10,
  63         OP_CP2_INTPL            = 0x11,
  64         OP_CP2_MVMVA            = 0x12,
  65         OP_CP2_NCDS             = 0x13,
  66         OP_CP2_CDP              = 0x14,
  67         OP_CP2_NCDT             = 0x16,
  68         OP_CP2_NCCS             = 0x1b,
  69         OP_CP2_CC               = 0x1c,
  70         OP_CP2_NCS              = 0x1e,
  71         OP_CP2_NCT              = 0x20,
  72         OP_CP2_SQR              = 0x28,
  73         OP_CP2_DCPL             = 0x29,
  74         OP_CP2_DPCT             = 0x2a,
  75         OP_CP2_AVSZ3            = 0x2d,
  76         OP_CP2_AVSZ4            = 0x2e,
  77         OP_CP2_RTPT             = 0x30,
  78         OP_CP2_GPF              = 0x3d,
  79         OP_CP2_GPL              = 0x3e,
  80         OP_CP2_NCCT             = 0x3f,
  81 };
  82
  83 static void (*cp2_ops[])(struct psxCP2Regs *) = {
  84         [OP_CP2_RTPS] = gteRTPS,
  85         [OP_CP2_RTPS] = gteRTPS,
  86         [OP_CP2_NCLIP] = gteNCLIP,
  87         [OP_CP2_OP] = gteOP,
  88         [OP_CP2_DPCS] = gteDPCS,
  89         [OP_CP2_INTPL] = gteINTPL,
  90         [OP_CP2_MVMVA] = gteMVMVA,
  91         [OP_CP2_NCDS] = gteNCDS,
  92         [OP_CP2_CDP] = gteCDP,
  93         [OP_CP2_NCDT] = gteNCDT,
  94         [OP_CP2_NCCS] = gteNCCS,
  95         [OP_CP2_CC] = gteCC,
  96         [OP_CP2_NCS] = gteNCS,
  97         [OP_CP2_NCT] = gteNCT,
  98         [OP_CP2_SQR] = gteSQR,
  99         [OP_CP2_DCPL] = gteDCPL,
 100         [OP_CP2_DPCT] = gteDPCT,
 101         [OP_CP2_AVSZ3] = gteAVSZ3,
 102         [OP_CP2_AVSZ4] = gteAVSZ4,
 103         [OP_CP2_RTPT] = gteRTPT,
 104         [OP_CP2_GPF] = gteGPF,
 105         [OP_CP2_GPL] = gteGPL,
 106         [OP_CP2_NCCT] = gteNCCT,
 107 };
 108
 109 static char cache_buf[64 * 1024];
 110
 111 static void cop2_op(struct lightrec_state *state, u32 func)
 112 {
 113         struct lightrec_registers *regs = lightrec_get_registers(state);
 114
 115         psxRegs.code = func;
 116
 117         if (unlikely(!cp2_ops[func & 0x3f])) {
 118                 fprintf(stderr, "Invalid CP2 function %u\n", func);
 119         } else {
 120                 /* This works because regs->cp2c comes right after regs->cp2d,
 121                  * so it can be cast to a pcsxCP2Regs pointer. */
 122                 cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
 123         }
 124 }
 125
 126 static bool has_interrupt(void)
 127 {
 128         struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
 129
 130         return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
 131                 (regs->cp0[12] & 0x401) == 0x401) ||
 132                 (regs->cp0[12] & regs->cp0[13] & 0x0300);
 133 }
 134
 135 static void lightrec_restore_state(struct lightrec_state *state)
 136 {
 137         lightrec_reset_cycle_count(state, psxRegs.cycle);
 138
 139         if (booting || has_interrupt())
 140                 lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
 141         else
 142                 lightrec_set_target_cycle_count(state, next_interupt);
 143 }
 144
 145 static void hw_write_byte(struct lightrec_state *state,
 146                           u32 op, void *host, u32 mem, u8 val)
 147 {
 148         psxRegs.cycle = lightrec_current_cycle_count(state);
 149
 150         psxHwWrite8(mem, val);
 151
 152         lightrec_restore_state(state);
 153 }
 154
 155 static void hw_write_half(struct lightrec_state *state,
 156                           u32 op, void *host, u32 mem, u16 val)
 157 {
 158         psxRegs.cycle = lightrec_current_cycle_count(state);
 159
 160         psxHwWrite16(mem, val);
 161
 162         lightrec_restore_state(state);
 163 }
 164
 165 static void hw_write_word(struct lightrec_state *state,
 166                           u32 op, void *host, u32 mem, u32 val)
 167 {
 168         psxRegs.cycle = lightrec_current_cycle_count(state);
 169
 170         psxHwWrite32(mem, val);
 171
 172         lightrec_restore_state(state);
 173 }
 174
 175 static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
 176 {
 177         u8 val;
 178
 179         psxRegs.cycle = lightrec_current_cycle_count(state);
 180
 181         val = psxHwRead8(mem);
 182
 183         lightrec_restore_state(state);
 184
 185         return val;
 186 }
 187
 188 static u16 hw_read_half(struct lightrec_state *state,
 189                         u32 op, void *host, u32 mem)
 190 {
 191         u16 val;
 192
 193         psxRegs.cycle = lightrec_current_cycle_count(state);
 194
 195         val = psxHwRead16(mem);
 196
 197         lightrec_restore_state(state);
 198
 199         return val;
 200 }
 201
 202 static u32 hw_read_word(struct lightrec_state *state,
 203                         u32 op, void *host, u32 mem)
 204 {
 205         u32 val;
 206
 207         psxRegs.cycle = lightrec_current_cycle_count(state);
 208
 209         val = psxHwRead32(mem);
 210
 211         lightrec_restore_state(state);
 212
 213         return val;
 214 }
 215
 216 static struct lightrec_mem_map_ops hw_regs_ops = {
 217         .sb = hw_write_byte,
 218         .sh = hw_write_half,
 219         .sw = hw_write_word,
 220         .lb = hw_read_byte,
 221         .lh = hw_read_half,
 222         .lw = hw_read_word,
 223 };
 224
 225 static u32 cache_ctrl;
 226
 227 static void cache_ctrl_write_word(struct lightrec_state *state,
 228                                   u32 op, void *host, u32 mem, u32 val)
 229 {
 230         cache_ctrl = val;
 231 }
 232
 233 static u32 cache_ctrl_read_word(struct lightrec_state *state,
 234                                 u32 op, void *host, u32 mem)
 235 {
 236         return cache_ctrl;
 237 }
 238
 239 static struct lightrec_mem_map_ops cache_ctrl_ops = {
 240         .sw = cache_ctrl_write_word,
 241         .lw = cache_ctrl_read_word,
 242 };
 243
 244 static struct lightrec_mem_map lightrec_map[] = {
 245         [PSX_MAP_KERNEL_USER_RAM] = {
 246                 /* Kernel and user memory */
 247                 .pc = 0x00000000,
 248                 .length = 0x200000,
 249         },
 250         [PSX_MAP_BIOS] = {
 251                 /* BIOS */
 252                 .pc = 0x1fc00000,
 253                 .length = 0x80000,
 254         },
 255         [PSX_MAP_SCRATCH_PAD] = {
 256                 /* Scratch pad */
 257                 .pc = 0x1f800000,
 258                 .length = 0x400,
 259         },
 260         [PSX_MAP_PARALLEL_PORT] = {
 261                 /* Parallel port */
 262                 .pc = 0x1f000000,
 263                 .length = 0x10000,
 264         },
 265         [PSX_MAP_HW_REGISTERS] = {
 266                 /* Hardware registers */
 267                 .pc = 0x1f801000,
 268                 .length = 0x2000,
 269                 .ops = &hw_regs_ops,
 270         },
 271         [PSX_MAP_CACHE_CONTROL] = {
 272                 /* Cache control */
 273                 .pc = 0x5ffe0130,
 274                 .length = 4,
 275                 .ops = &cache_ctrl_ops,
 276         },
 277
 278         /* Mirrors of the kernel/user memory */
 279         [PSX_MAP_MIRROR1] = {
 280                 .pc = 0x00200000,
 281                 .length = 0x200000,
 282                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 283         },
 284         [PSX_MAP_MIRROR2] = {
 285                 .pc = 0x00400000,
 286                 .length = 0x200000,
 287                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 288         },
 289         [PSX_MAP_MIRROR3] = {
 290                 .pc = 0x00600000,
 291                 .length = 0x200000,
 292                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 293         },
 294         [PSX_MAP_CODE_BUFFER] = {
 295                 .length = CODE_BUFFER_SIZE,
 296         },
 297 };
 298
 299 static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
 300 {
 301         if (enable)
 302                 memcpy(psxM, cache_buf, sizeof(cache_buf));
 303         else
 304                 memcpy(cache_buf, psxM, sizeof(cache_buf));
 305 }
 306
 307 static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
 308 {
 309         switch (size) {
 310         case 8:
 311                 switch (kaddr) {
 312                 case 0x1f801040:
 313                 case 0x1f801050:
 314                 case 0x1f801800:
 315                 case 0x1f801801:
 316                 case 0x1f801802:
 317                 case 0x1f801803:
 318                         return false;
 319                 default:
 320                         return true;
 321                 }
 322         case 16:
 323                 switch (kaddr) {
 324                 case 0x1f801040:
 325                 case 0x1f801044:
 326                 case 0x1f801048:
 327                 case 0x1f80104a:
 328                 case 0x1f80104e:
 329                 case 0x1f801050:
 330                 case 0x1f801054:
 331                 case 0x1f80105a:
 332                 case 0x1f80105e:
 333                 case 0x1f801100:
 334                 case 0x1f801104:
 335                 case 0x1f801108:
 336                 case 0x1f801110:
 337                 case 0x1f801114:
 338                 case 0x1f801118:
 339                 case 0x1f801120:
 340                 case 0x1f801124:
 341                 case 0x1f801128:
 342                         return false;
 343                 case 0x1f801070:
 344                 case 0x1f801074:
 345                         return !is_write;
 346                 default:
 347                         return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 348                 }
 349         default:
 350                 switch (kaddr) {
 351                 case 0x1f801040:
 352                 case 0x1f801050:
 353                 case 0x1f801100:
 354                 case 0x1f801104:
 355                 case 0x1f801108:
 356                 case 0x1f801110:
 357                 case 0x1f801114:
 358                 case 0x1f801118:
 359                 case 0x1f801120:
 360                 case 0x1f801124:
 361                 case 0x1f801128:
 362                 case 0x1f801810:
 363                 case 0x1f801814:
 364                 case 0x1f801820:
 365                 case 0x1f801824:
 366                         return false;
 367                 case 0x1f801070:
 368                 case 0x1f801074:
 369                 case 0x1f801088:
 370                 case 0x1f801098:
 371                 case 0x1f8010a8:
 372                 case 0x1f8010b8:
 373                 case 0x1f8010c8:
 374                 case 0x1f8010e8:
 375                 case 0x1f8010f4:
 376                         return !is_write;
 377                 default:
 378                         return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 379                 }
 380         }
 381 }
 382
 383 static const struct lightrec_ops lightrec_ops = {
 384         .cop2_op = cop2_op,
 385         .enable_ram = lightrec_enable_ram,
 386         .hw_direct = lightrec_can_hw_direct,
 387 };
 388
 389 static int lightrec_plugin_init(void)
 390 {
 391         lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
 392         lightrec_map[PSX_MAP_BIOS].address = psxR;
 393         lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
 394         lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
 395         lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
 396
 397         if (LIGHTREC_CUSTOM_MAP) {
 398                 lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
 399                 lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
 400                 lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
 401                 lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
 402         }
 403
 404         use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
 405
 406         lightrec_state = lightrec_init(name,
 407                         lightrec_map, ARRAY_SIZE(lightrec_map),
 408                         &lightrec_ops);
 409
 410         // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
 411         //              (uintptr_t) psxM,
 412         //              (uintptr_t) psxP,
 413         //              (uintptr_t) psxR,
 414         //              (uintptr_t) psxH);
 415
 416 #ifndef _WIN32
 417         signal(SIGPIPE, exit);
 418 #endif
 419         return 0;
 420 }
 421
 422 static void lightrec_dump_regs(struct lightrec_state *state)
 423 {
 424         struct lightrec_registers *regs = lightrec_get_registers(state);
 425
 426         if (unlikely(booting))
 427                 memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
 428         psxRegs.CP0.n.Status = regs->cp0[12];
 429         psxRegs.CP0.n.Cause = regs->cp0[13];
 430 }
 431
 432 static void lightrec_restore_regs(struct lightrec_state *state)
 433 {
 434         struct lightrec_registers *regs = lightrec_get_registers(state);
 435
 436         if (unlikely(booting))
 437                 memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
 438         regs->cp0[12] = psxRegs.CP0.n.Status;
 439         regs->cp0[13] = psxRegs.CP0.n.Cause;
 440         regs->cp0[14] = psxRegs.CP0.n.EPC;
 441 }
 442
 443 extern void intExecuteBlock();
 444 extern void gen_interupt();
 445
 446 static void lightrec_plugin_execute_internal(bool block_only)
 447 {
 448         u32 flags;
 449
 450         gen_interupt();
 451
 452         // step during early boot so that 0x80030000 fastboot hack works
 453         booting = block_only;
 454         if (block_only)
 455                 next_interupt = psxRegs.cycle;
 456
 457         if (use_pcsx_interpreter) {
 458                 intExecuteBlock();
 459         } else {
 460                 lightrec_reset_cycle_count(lightrec_state, psxRegs.cycle);
 461                 lightrec_restore_regs(lightrec_state);
 462
 463                 if (unlikely(use_lightrec_interpreter)) {
 464                         psxRegs.pc = lightrec_run_interpreter(lightrec_state,
 465                                                               psxRegs.pc,
 466                                                               next_interupt);
 467                 } else {
 468                         psxRegs.pc = lightrec_execute(lightrec_state,
 469                                                       psxRegs.pc, next_interupt);
 470                 }
 471
 472                 psxRegs.cycle = lightrec_current_cycle_count(lightrec_state);
 473
 474                 lightrec_dump_regs(lightrec_state);
 475                 flags = lightrec_exit_flags(lightrec_state);
 476
 477                 if (flags & LIGHTREC_EXIT_SEGFAULT) {
 478                         fprintf(stderr, "Exiting at cycle 0x%08x\n",
 479                                 psxRegs.cycle);
 480                         exit(1);
 481                 }
 482
 483                 if (flags & LIGHTREC_EXIT_SYSCALL)
 484                         psxException(0x20, 0);
 485         }
 486
 487         if ((psxRegs.CP0.n.Cause & psxRegs.CP0.n.Status & 0x300) &&
 488                         (psxRegs.CP0.n.Status & 0x1)) {
 489                 /* Handle software interrupts */
 490                 psxRegs.CP0.n.Cause &= ~0x7c;
 491                 psxException(psxRegs.CP0.n.Cause, 0);
 492         }
 493 }
 494
 495 static void lightrec_plugin_execute(void)
 496 {
 497         extern int stop;
 498
 499         if (!booting)
 500                 lightrec_plugin_sync_regs_from_pcsx();
 501
 502         while (!stop)
 503                 lightrec_plugin_execute_internal(false);
 504
 505         lightrec_plugin_sync_regs_to_pcsx();
 506 }
 507
 508 static void lightrec_plugin_execute_block(void)
 509 {
 510         lightrec_plugin_execute_internal(true);
 511 }
 512
 513 static void lightrec_plugin_clear(u32 addr, u32 size)
 514 {
 515         if (addr == 0 && size == UINT32_MAX)
 516                 lightrec_invalidate_all(lightrec_state);
 517         else
 518                 /* size * 4: PCSX uses DMA units */
 519                 lightrec_invalidate(lightrec_state, addr, size * 4);
 520 }
 521
 522 static void lightrec_plugin_notify(int note, void *data)
 523 {
 524         /*
 525         To change once proper icache emulation is emulated
 526         switch (note)
 527         {
 528                 case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
 529                         lightrec_plugin_clear(0, 0x200000/4);
 530                         break;
 531                 case R3000ACPU_NOTIFY_CACHE_ISOLATED:
 532                 // Sent from psxDma3().
 533                 case R3000ACPU_NOTIFY_DMA3_EXE_LOAD:
 534                 default:
 535                         break;
 536         }*/
 537 }
 538
 539 static void lightrec_plugin_apply_config()
 540 {
 541 }
 542
 543 static void lightrec_plugin_shutdown(void)
 544 {
 545         lightrec_destroy(lightrec_state);
 546 }
 547
 548 static void lightrec_plugin_reset(void)
 549 {
 550         struct lightrec_registers *regs;
 551
 552         regs = lightrec_get_registers(lightrec_state);
 553
 554         /* Invalidate all blocks */
 555         lightrec_invalidate_all(lightrec_state);
 556
 557         /* Reset registers */
 558         memset(regs, 0, sizeof(*regs));
 559
 560         regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
 561         regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
 562 }
 563
 564 void lightrec_plugin_sync_regs_from_pcsx(void)
 565 {
 566         struct lightrec_registers *regs;
 567
 568         regs = lightrec_get_registers(lightrec_state);
 569         memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 570         memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
 571         memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
 572
 573         lightrec_invalidate_all(lightrec_state);
 574 }
 575
 576 void lightrec_plugin_sync_regs_to_pcsx(void)
 577 {
 578         struct lightrec_registers *regs;
 579
 580         regs = lightrec_get_registers(lightrec_state);
 581         memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 582         memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
 583         memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
 584 }
 585
 586 R3000Acpu psxRec =
 587 {
 588         lightrec_plugin_init,
 589         lightrec_plugin_reset,
 590         lightrec_plugin_execute,
 591         lightrec_plugin_execute_block,
 592         lightrec_plugin_clear,
 593         lightrec_plugin_notify,
 594         lightrec_plugin_apply_config,
 595         lightrec_plugin_shutdown,
 596 };