libpcsxcore/lightrec/plugin.c

   1 #include <lightrec.h>
   2 #include <stdbool.h>
   3 #include <stdio.h>
   4 #include <unistd.h>
   5 #include <signal.h>
   6
   7 #include "../cdrom.h"
   8 #include "../gpu.h"
   9 #include "../gte.h"
  10 #include "../mdec.h"
  11 #include "../psxdma.h"
  12 #include "../psxhw.h"
  13 #include "../psxmem.h"
  14 #include "../r3000a.h"
  15 #include "../new_dynarec/events.h"
  16
  17 #include "../frontend/main.h"
  18
  19 #include "mem.h"
  20 #include "plugin.h"
  21
  22 #if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
  23 #error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
  24 #endif
  25
  26 #define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
  27
  28 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
  29 #       define LE32TOH(x)       __builtin_bswap32(x)
  30 #       define HTOLE32(x)       __builtin_bswap32(x)
  31 #       define LE16TOH(x)       __builtin_bswap16(x)
  32 #       define HTOLE16(x)       __builtin_bswap16(x)
  33 #else
  34 #       define LE32TOH(x)       (x)
  35 #       define HTOLE32(x)       (x)
  36 #       define LE16TOH(x)       (x)
  37 #       define HTOLE16(x)       (x)
  38 #endif
  39
  40 #ifdef __GNUC__
  41 #       define likely(x)       __builtin_expect(!!(x),1)
  42 #       define unlikely(x)     __builtin_expect(!!(x),0)
  43 #else
  44 #       define likely(x)       (x)
  45 #       define unlikely(x)     (x)
  46 #endif
  47
  48 psxRegisters psxRegs;
  49 Rcnt rcnts[4];
  50
  51 static struct lightrec_state *lightrec_state;
  52
  53 static char *name = "retroarch.exe";
  54
  55 static bool use_lightrec_interpreter;
  56 static bool use_pcsx_interpreter;
  57 static bool block_stepping;
  58
  59 enum my_cp2_opcodes {
  60         OP_CP2_RTPS             = 0x01,
  61         OP_CP2_NCLIP            = 0x06,
  62         OP_CP2_OP               = 0x0c,
  63         OP_CP2_DPCS             = 0x10,
  64         OP_CP2_INTPL            = 0x11,
  65         OP_CP2_MVMVA            = 0x12,
  66         OP_CP2_NCDS             = 0x13,
  67         OP_CP2_CDP              = 0x14,
  68         OP_CP2_NCDT             = 0x16,
  69         OP_CP2_NCCS             = 0x1b,
  70         OP_CP2_CC               = 0x1c,
  71         OP_CP2_NCS              = 0x1e,
  72         OP_CP2_NCT              = 0x20,
  73         OP_CP2_SQR              = 0x28,
  74         OP_CP2_DCPL             = 0x29,
  75         OP_CP2_DPCT             = 0x2a,
  76         OP_CP2_AVSZ3            = 0x2d,
  77         OP_CP2_AVSZ4            = 0x2e,
  78         OP_CP2_RTPT             = 0x30,
  79         OP_CP2_GPF              = 0x3d,
  80         OP_CP2_GPL              = 0x3e,
  81         OP_CP2_NCCT             = 0x3f,
  82 };
  83
  84 static void (*cp2_ops[])(struct psxCP2Regs *) = {
  85         [OP_CP2_RTPS] = gteRTPS,
  86         [OP_CP2_RTPS] = gteRTPS,
  87         [OP_CP2_NCLIP] = gteNCLIP,
  88         [OP_CP2_OP] = gteOP,
  89         [OP_CP2_DPCS] = gteDPCS,
  90         [OP_CP2_INTPL] = gteINTPL,
  91         [OP_CP2_MVMVA] = gteMVMVA,
  92         [OP_CP2_NCDS] = gteNCDS,
  93         [OP_CP2_CDP] = gteCDP,
  94         [OP_CP2_NCDT] = gteNCDT,
  95         [OP_CP2_NCCS] = gteNCCS,
  96         [OP_CP2_CC] = gteCC,
  97         [OP_CP2_NCS] = gteNCS,
  98         [OP_CP2_NCT] = gteNCT,
  99         [OP_CP2_SQR] = gteSQR,
 100         [OP_CP2_DCPL] = gteDCPL,
 101         [OP_CP2_DPCT] = gteDPCT,
 102         [OP_CP2_AVSZ3] = gteAVSZ3,
 103         [OP_CP2_AVSZ4] = gteAVSZ4,
 104         [OP_CP2_RTPT] = gteRTPT,
 105         [OP_CP2_GPF] = gteGPF,
 106         [OP_CP2_GPL] = gteGPL,
 107         [OP_CP2_NCCT] = gteNCCT,
 108 };
 109
 110 static char cache_buf[64 * 1024];
 111
 112 static void cop2_op(struct lightrec_state *state, u32 func)
 113 {
 114         struct lightrec_registers *regs = lightrec_get_registers(state);
 115
 116         psxRegs.code = func;
 117
 118         if (unlikely(!cp2_ops[func & 0x3f])) {
 119                 fprintf(stderr, "Invalid CP2 function %u\n", func);
 120         } else {
 121                 /* This works because regs->cp2c comes right after regs->cp2d,
 122                  * so it can be cast to a pcsxCP2Regs pointer. */
 123                 cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
 124         }
 125 }
 126
 127 static bool has_interrupt(void)
 128 {
 129         struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
 130
 131         return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
 132                 (regs->cp0[12] & 0x401) == 0x401) ||
 133                 (regs->cp0[12] & regs->cp0[13] & 0x0300);
 134 }
 135
 136 static void lightrec_restore_state(struct lightrec_state *state)
 137 {
 138         lightrec_reset_cycle_count(state, psxRegs.cycle);
 139
 140         if (block_stepping || has_interrupt())
 141                 lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
 142         else
 143                 lightrec_set_target_cycle_count(state, next_interupt);
 144 }
 145
 146 static void hw_write_byte(struct lightrec_state *state,
 147                           u32 op, void *host, u32 mem, u8 val)
 148 {
 149         psxRegs.cycle = lightrec_current_cycle_count(state);
 150
 151         psxHwWrite8(mem, val);
 152
 153         lightrec_restore_state(state);
 154 }
 155
 156 static void hw_write_half(struct lightrec_state *state,
 157                           u32 op, void *host, u32 mem, u16 val)
 158 {
 159         psxRegs.cycle = lightrec_current_cycle_count(state);
 160
 161         psxHwWrite16(mem, val);
 162
 163         lightrec_restore_state(state);
 164 }
 165
 166 static void hw_write_word(struct lightrec_state *state,
 167                           u32 op, void *host, u32 mem, u32 val)
 168 {
 169         psxRegs.cycle = lightrec_current_cycle_count(state);
 170
 171         psxHwWrite32(mem, val);
 172
 173         lightrec_restore_state(state);
 174 }
 175
 176 static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
 177 {
 178         u8 val;
 179
 180         psxRegs.cycle = lightrec_current_cycle_count(state);
 181
 182         val = psxHwRead8(mem);
 183
 184         lightrec_restore_state(state);
 185
 186         return val;
 187 }
 188
 189 static u16 hw_read_half(struct lightrec_state *state,
 190                         u32 op, void *host, u32 mem)
 191 {
 192         u16 val;
 193
 194         psxRegs.cycle = lightrec_current_cycle_count(state);
 195
 196         val = psxHwRead16(mem);
 197
 198         lightrec_restore_state(state);
 199
 200         return val;
 201 }
 202
 203 static u32 hw_read_word(struct lightrec_state *state,
 204                         u32 op, void *host, u32 mem)
 205 {
 206         u32 val;
 207
 208         psxRegs.cycle = lightrec_current_cycle_count(state);
 209
 210         val = psxHwRead32(mem);
 211
 212         lightrec_restore_state(state);
 213
 214         return val;
 215 }
 216
 217 static struct lightrec_mem_map_ops hw_regs_ops = {
 218         .sb = hw_write_byte,
 219         .sh = hw_write_half,
 220         .sw = hw_write_word,
 221         .lb = hw_read_byte,
 222         .lh = hw_read_half,
 223         .lw = hw_read_word,
 224 };
 225
 226 static u32 cache_ctrl;
 227
 228 static void cache_ctrl_write_word(struct lightrec_state *state,
 229                                   u32 op, void *host, u32 mem, u32 val)
 230 {
 231         cache_ctrl = val;
 232 }
 233
 234 static u32 cache_ctrl_read_word(struct lightrec_state *state,
 235                                 u32 op, void *host, u32 mem)
 236 {
 237         return cache_ctrl;
 238 }
 239
 240 static struct lightrec_mem_map_ops cache_ctrl_ops = {
 241         .sw = cache_ctrl_write_word,
 242         .lw = cache_ctrl_read_word,
 243 };
 244
 245 static struct lightrec_mem_map lightrec_map[] = {
 246         [PSX_MAP_KERNEL_USER_RAM] = {
 247                 /* Kernel and user memory */
 248                 .pc = 0x00000000,
 249                 .length = 0x200000,
 250         },
 251         [PSX_MAP_BIOS] = {
 252                 /* BIOS */
 253                 .pc = 0x1fc00000,
 254                 .length = 0x80000,
 255         },
 256         [PSX_MAP_SCRATCH_PAD] = {
 257                 /* Scratch pad */
 258                 .pc = 0x1f800000,
 259                 .length = 0x400,
 260         },
 261         [PSX_MAP_PARALLEL_PORT] = {
 262                 /* Parallel port */
 263                 .pc = 0x1f000000,
 264                 .length = 0x10000,
 265         },
 266         [PSX_MAP_HW_REGISTERS] = {
 267                 /* Hardware registers */
 268                 .pc = 0x1f801000,
 269                 .length = 0x2000,
 270                 .ops = &hw_regs_ops,
 271         },
 272         [PSX_MAP_CACHE_CONTROL] = {
 273                 /* Cache control */
 274                 .pc = 0x5ffe0130,
 275                 .length = 4,
 276                 .ops = &cache_ctrl_ops,
 277         },
 278
 279         /* Mirrors of the kernel/user memory */
 280         [PSX_MAP_MIRROR1] = {
 281                 .pc = 0x00200000,
 282                 .length = 0x200000,
 283                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 284         },
 285         [PSX_MAP_MIRROR2] = {
 286                 .pc = 0x00400000,
 287                 .length = 0x200000,
 288                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 289         },
 290         [PSX_MAP_MIRROR3] = {
 291                 .pc = 0x00600000,
 292                 .length = 0x200000,
 293                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 294         },
 295         [PSX_MAP_CODE_BUFFER] = {
 296                 .length = CODE_BUFFER_SIZE,
 297         },
 298 };
 299
 300 static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
 301 {
 302         if (enable)
 303                 memcpy(psxM, cache_buf, sizeof(cache_buf));
 304         else
 305                 memcpy(cache_buf, psxM, sizeof(cache_buf));
 306 }
 307
 308 static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
 309 {
 310         switch (size) {
 311         case 8:
 312                 switch (kaddr) {
 313                 case 0x1f801040:
 314                 case 0x1f801050:
 315                 case 0x1f801800:
 316                 case 0x1f801801:
 317                 case 0x1f801802:
 318                 case 0x1f801803:
 319                         return false;
 320                 default:
 321                         return true;
 322                 }
 323         case 16:
 324                 switch (kaddr) {
 325                 case 0x1f801040:
 326                 case 0x1f801044:
 327                 case 0x1f801048:
 328                 case 0x1f80104a:
 329                 case 0x1f80104e:
 330                 case 0x1f801050:
 331                 case 0x1f801054:
 332                 case 0x1f80105a:
 333                 case 0x1f80105e:
 334                 case 0x1f801100:
 335                 case 0x1f801104:
 336                 case 0x1f801108:
 337                 case 0x1f801110:
 338                 case 0x1f801114:
 339                 case 0x1f801118:
 340                 case 0x1f801120:
 341                 case 0x1f801124:
 342                 case 0x1f801128:
 343                         return false;
 344                 case 0x1f801070:
 345                 case 0x1f801074:
 346                         return !is_write;
 347                 default:
 348                         return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 349                 }
 350         default:
 351                 switch (kaddr) {
 352                 case 0x1f801040:
 353                 case 0x1f801050:
 354                 case 0x1f801100:
 355                 case 0x1f801104:
 356                 case 0x1f801108:
 357                 case 0x1f801110:
 358                 case 0x1f801114:
 359                 case 0x1f801118:
 360                 case 0x1f801120:
 361                 case 0x1f801124:
 362                 case 0x1f801128:
 363                 case 0x1f801810:
 364                 case 0x1f801814:
 365                 case 0x1f801820:
 366                 case 0x1f801824:
 367                         return false;
 368                 case 0x1f801070:
 369                 case 0x1f801074:
 370                 case 0x1f801088:
 371                 case 0x1f801098:
 372                 case 0x1f8010a8:
 373                 case 0x1f8010b8:
 374                 case 0x1f8010c8:
 375                 case 0x1f8010e8:
 376                 case 0x1f8010f4:
 377                         return !is_write;
 378                 default:
 379                         return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 380                 }
 381         }
 382 }
 383
 384 static const struct lightrec_ops lightrec_ops = {
 385         .cop2_op = cop2_op,
 386         .enable_ram = lightrec_enable_ram,
 387         .hw_direct = lightrec_can_hw_direct,
 388 };
 389
 390 static int lightrec_plugin_init(void)
 391 {
 392         lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
 393         lightrec_map[PSX_MAP_BIOS].address = psxR;
 394         lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
 395         lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
 396         lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
 397
 398         if (LIGHTREC_CUSTOM_MAP) {
 399                 lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
 400                 lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
 401                 lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
 402                 lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
 403         }
 404
 405         use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
 406
 407         lightrec_state = lightrec_init(name,
 408                         lightrec_map, ARRAY_SIZE(lightrec_map),
 409                         &lightrec_ops);
 410
 411         // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
 412         //              (uintptr_t) psxM,
 413         //              (uintptr_t) psxP,
 414         //              (uintptr_t) psxR,
 415         //              (uintptr_t) psxH);
 416
 417 #ifndef _WIN32
 418         signal(SIGPIPE, exit);
 419 #endif
 420         return 0;
 421 }
 422
 423 extern void intExecuteBlock();
 424
 425 static void lightrec_plugin_execute_internal(bool block_only)
 426 {
 427         struct lightrec_registers *regs;
 428         u32 flags;
 429
 430         regs = lightrec_get_registers(lightrec_state);
 431         gen_interupt((psxCP0Regs *)regs->cp0);
 432
 433         // step during early boot so that 0x80030000 fastboot hack works
 434         block_stepping = block_only;
 435         if (block_only)
 436                 next_interupt = psxRegs.cycle;
 437
 438         if (use_pcsx_interpreter) {
 439                 intExecuteBlock();
 440         } else {
 441                 lightrec_reset_cycle_count(lightrec_state, psxRegs.cycle);
 442
 443                 if (unlikely(use_lightrec_interpreter)) {
 444                         psxRegs.pc = lightrec_run_interpreter(lightrec_state,
 445                                                               psxRegs.pc,
 446                                                               next_interupt);
 447                 } else {
 448                         psxRegs.pc = lightrec_execute(lightrec_state,
 449                                                       psxRegs.pc, next_interupt);
 450                 }
 451
 452                 psxRegs.cycle = lightrec_current_cycle_count(lightrec_state);
 453
 454                 flags = lightrec_exit_flags(lightrec_state);
 455
 456                 if (flags & LIGHTREC_EXIT_SEGFAULT) {
 457                         fprintf(stderr, "Exiting at cycle 0x%08x\n",
 458                                 psxRegs.cycle);
 459                         exit(1);
 460                 }
 461
 462                 if (flags & LIGHTREC_EXIT_SYSCALL)
 463                         psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
 464         }
 465
 466         if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
 467                 /* Handle software interrupts */
 468                 regs->cp0[13] &= ~0x7c;
 469                 psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
 470         }
 471 }
 472
 473 static void lightrec_plugin_execute(void)
 474 {
 475         extern int stop;
 476
 477         while (!stop)
 478                 lightrec_plugin_execute_internal(false);
 479 }
 480
 481 static void lightrec_plugin_execute_block(enum blockExecCaller caller)
 482 {
 483         lightrec_plugin_execute_internal(true);
 484 }
 485
 486 static void lightrec_plugin_clear(u32 addr, u32 size)
 487 {
 488         if (addr == 0 && size == UINT32_MAX)
 489                 lightrec_invalidate_all(lightrec_state);
 490         else
 491                 /* size * 4: PCSX uses DMA units */
 492                 lightrec_invalidate(lightrec_state, addr, size * 4);
 493 }
 494
 495 static void lightrec_plugin_sync_regs_to_pcsx(void);
 496 static void lightrec_plugin_sync_regs_from_pcsx(void);
 497
 498 static void lightrec_plugin_notify(enum R3000Anote note, void *data)
 499 {
 500         switch (note)
 501         {
 502         case R3000ACPU_NOTIFY_CACHE_ISOLATED:
 503         case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
 504                 /* not used, lightrec calls lightrec_enable_ram() instead */
 505                 break;
 506         case R3000ACPU_NOTIFY_BEFORE_SAVE:
 507                 lightrec_plugin_sync_regs_to_pcsx();
 508                 break;
 509         case R3000ACPU_NOTIFY_AFTER_LOAD:
 510                 lightrec_plugin_sync_regs_from_pcsx();
 511                 break;
 512         }
 513 }
 514
 515 static void lightrec_plugin_apply_config()
 516 {
 517 }
 518
 519 static void lightrec_plugin_shutdown(void)
 520 {
 521         lightrec_destroy(lightrec_state);
 522 }
 523
 524 static void lightrec_plugin_reset(void)
 525 {
 526         struct lightrec_registers *regs;
 527
 528         regs = lightrec_get_registers(lightrec_state);
 529
 530         /* Invalidate all blocks */
 531         lightrec_invalidate_all(lightrec_state);
 532
 533         /* Reset registers */
 534         memset(regs, 0, sizeof(*regs));
 535
 536         regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
 537         regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
 538 }
 539
 540 static void lightrec_plugin_sync_regs_from_pcsx(void)
 541 {
 542         struct lightrec_registers *regs;
 543
 544         regs = lightrec_get_registers(lightrec_state);
 545         memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 546         memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
 547         memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
 548
 549         lightrec_invalidate_all(lightrec_state);
 550 }
 551
 552 static void lightrec_plugin_sync_regs_to_pcsx(void)
 553 {
 554         struct lightrec_registers *regs;
 555
 556         regs = lightrec_get_registers(lightrec_state);
 557         memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 558         memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
 559         memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
 560 }
 561
 562 R3000Acpu psxRec =
 563 {
 564         lightrec_plugin_init,
 565         lightrec_plugin_reset,
 566         lightrec_plugin_execute,
 567         lightrec_plugin_execute_block,
 568         lightrec_plugin_clear,
 569         lightrec_plugin_notify,
 570         lightrec_plugin_apply_config,
 571         lightrec_plugin_shutdown,
 572 };