libpcsxcore/lightrec/plugin.c

   1 #include <lightrec.h>
   2 #include <errno.h>
   3 #include <stdbool.h>
   4 #include <stdio.h>
   5 #include <unistd.h>
   6 #include <signal.h>
   7 #include <assert.h>
   8
   9 #if P_HAVE_MMAP
  10 #include <sys/mman.h>
  11 #endif
  12
  13 #include "../cdrom.h"
  14 #include "../gpu.h"
  15 #include "../gte.h"
  16 #include "../mdec.h"
  17 #include "../psxdma.h"
  18 #include "../psxhw.h"
  19 #include "../psxmem.h"
  20 #include "../r3000a.h"
  21 #include "../psxinterpreter.h"
  22 #include "../new_dynarec/events.h"
  23
  24 #include "../frontend/main.h"
  25
  26 #include "mem.h"
  27 #include "plugin.h"
  28
  29 #if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
  30 #error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
  31 #endif
  32
  33 #define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
  34
  35 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
  36 #       define LE32TOH(x)       __builtin_bswap32(x)
  37 #       define HTOLE32(x)       __builtin_bswap32(x)
  38 #       define LE16TOH(x)       __builtin_bswap16(x)
  39 #       define HTOLE16(x)       __builtin_bswap16(x)
  40 #else
  41 #       define LE32TOH(x)       (x)
  42 #       define HTOLE32(x)       (x)
  43 #       define LE16TOH(x)       (x)
  44 #       define HTOLE16(x)       (x)
  45 #endif
  46
  47 #ifdef __GNUC__
  48 #       define likely(x)       __builtin_expect(!!(x),1)
  49 #       define unlikely(x)     __builtin_expect(!!(x),0)
  50 #else
  51 #       define likely(x)       (x)
  52 #       define unlikely(x)     (x)
  53 #endif
  54
  55 psxRegisters psxRegs;
  56 Rcnt rcnts[4];
  57
  58 void* code_buffer;
  59
  60 static struct lightrec_state *lightrec_state;
  61
  62 static char *name = "retroarch.exe";
  63
  64 static bool use_lightrec_interpreter;
  65 static bool use_pcsx_interpreter;
  66 static bool block_stepping;
  67 static u32 cycle_mult_to_pcsx; // 22.10 fractional
  68 static u32 cycle_mult_from_pcsx;
  69
  70 enum my_cp2_opcodes {
  71         OP_CP2_RTPS             = 0x01,
  72         OP_CP2_NCLIP            = 0x06,
  73         OP_CP2_OP               = 0x0c,
  74         OP_CP2_DPCS             = 0x10,
  75         OP_CP2_INTPL            = 0x11,
  76         OP_CP2_MVMVA            = 0x12,
  77         OP_CP2_NCDS             = 0x13,
  78         OP_CP2_CDP              = 0x14,
  79         OP_CP2_NCDT             = 0x16,
  80         OP_CP2_NCCS             = 0x1b,
  81         OP_CP2_CC               = 0x1c,
  82         OP_CP2_NCS              = 0x1e,
  83         OP_CP2_NCT              = 0x20,
  84         OP_CP2_SQR              = 0x28,
  85         OP_CP2_DCPL             = 0x29,
  86         OP_CP2_DPCT             = 0x2a,
  87         OP_CP2_AVSZ3            = 0x2d,
  88         OP_CP2_AVSZ4            = 0x2e,
  89         OP_CP2_RTPT             = 0x30,
  90         OP_CP2_GPF              = 0x3d,
  91         OP_CP2_GPL              = 0x3e,
  92         OP_CP2_NCCT             = 0x3f,
  93 };
  94
  95 static void (*cp2_ops[])(struct psxCP2Regs *) = {
  96         [OP_CP2_RTPS] = gteRTPS,
  97         [OP_CP2_RTPS] = gteRTPS,
  98         [OP_CP2_NCLIP] = gteNCLIP,
  99         [OP_CP2_OP] = gteOP,
 100         [OP_CP2_DPCS] = gteDPCS,
 101         [OP_CP2_INTPL] = gteINTPL,
 102         [OP_CP2_MVMVA] = gteMVMVA,
 103         [OP_CP2_NCDS] = gteNCDS,
 104         [OP_CP2_CDP] = gteCDP,
 105         [OP_CP2_NCDT] = gteNCDT,
 106         [OP_CP2_NCCS] = gteNCCS,
 107         [OP_CP2_CC] = gteCC,
 108         [OP_CP2_NCS] = gteNCS,
 109         [OP_CP2_NCT] = gteNCT,
 110         [OP_CP2_SQR] = gteSQR,
 111         [OP_CP2_DCPL] = gteDCPL,
 112         [OP_CP2_DPCT] = gteDPCT,
 113         [OP_CP2_AVSZ3] = gteAVSZ3,
 114         [OP_CP2_AVSZ4] = gteAVSZ4,
 115         [OP_CP2_RTPT] = gteRTPT,
 116         [OP_CP2_GPF] = gteGPF,
 117         [OP_CP2_GPL] = gteGPL,
 118         [OP_CP2_NCCT] = gteNCCT,
 119 };
 120
 121 static char cache_buf[64 * 1024];
 122
 123 static void cop2_op(struct lightrec_state *state, u32 func)
 124 {
 125         struct lightrec_registers *regs = lightrec_get_registers(state);
 126
 127         psxRegs.code = func;
 128
 129         if (unlikely(!cp2_ops[func & 0x3f])) {
 130                 fprintf(stderr, "Invalid CP2 function %u\n", func);
 131         } else {
 132                 /* This works because regs->cp2c comes right after regs->cp2d,
 133                  * so it can be cast to a pcsxCP2Regs pointer. */
 134                 cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
 135         }
 136 }
 137
 138 static bool has_interrupt(void)
 139 {
 140         struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
 141
 142         return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
 143                 (regs->cp0[12] & 0x401) == 0x401) ||
 144                 (regs->cp0[12] & regs->cp0[13] & 0x0300);
 145 }
 146
 147 static u32 cycles_pcsx_to_lightrec(u32 c)
 148 {
 149         assert((u64)c * cycle_mult_from_pcsx <= (u32)-1);
 150         return c * cycle_mult_from_pcsx >> 10;
 151 }
 152
 153 static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
 154 {
 155         psxRegs.cycle += lightrec_current_cycle_count(state) * cycle_mult_to_pcsx >> 10;
 156         lightrec_reset_cycle_count(state, 0);
 157 }
 158
 159 static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
 160 {
 161         s32 cycles_left = next_interupt - psxRegs.cycle;
 162
 163         if (block_stepping || cycles_left <= 0 || has_interrupt())
 164                 lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
 165         else {
 166                 lightrec_set_target_cycle_count(state,
 167                         cycles_pcsx_to_lightrec(cycles_left));
 168         }
 169 }
 170
 171 static void hw_write_byte(struct lightrec_state *state,
 172                           u32 op, void *host, u32 mem, u8 val)
 173 {
 174         lightrec_tansition_to_pcsx(state);
 175
 176         psxHwWrite8(mem, val);
 177
 178         lightrec_tansition_from_pcsx(state);
 179 }
 180
 181 static void hw_write_half(struct lightrec_state *state,
 182                           u32 op, void *host, u32 mem, u16 val)
 183 {
 184         lightrec_tansition_to_pcsx(state);
 185
 186         psxHwWrite16(mem, val);
 187
 188         lightrec_tansition_from_pcsx(state);
 189 }
 190
 191 static void hw_write_word(struct lightrec_state *state,
 192                           u32 op, void *host, u32 mem, u32 val)
 193 {
 194         lightrec_tansition_to_pcsx(state);
 195
 196         psxHwWrite32(mem, val);
 197
 198         lightrec_tansition_from_pcsx(state);
 199 }
 200
 201 static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
 202 {
 203         u8 val;
 204
 205         lightrec_tansition_to_pcsx(state);
 206
 207         val = psxHwRead8(mem);
 208
 209         lightrec_tansition_from_pcsx(state);
 210
 211         return val;
 212 }
 213
 214 static u16 hw_read_half(struct lightrec_state *state,
 215                         u32 op, void *host, u32 mem)
 216 {
 217         u16 val;
 218
 219         lightrec_tansition_to_pcsx(state);
 220
 221         val = psxHwRead16(mem);
 222
 223         lightrec_tansition_from_pcsx(state);
 224
 225         return val;
 226 }
 227
 228 static u32 hw_read_word(struct lightrec_state *state,
 229                         u32 op, void *host, u32 mem)
 230 {
 231         u32 val;
 232
 233         lightrec_tansition_to_pcsx(state);
 234
 235         val = psxHwRead32(mem);
 236
 237         lightrec_tansition_from_pcsx(state);
 238
 239         return val;
 240 }
 241
 242 static struct lightrec_mem_map_ops hw_regs_ops = {
 243         .sb = hw_write_byte,
 244         .sh = hw_write_half,
 245         .sw = hw_write_word,
 246         .lb = hw_read_byte,
 247         .lh = hw_read_half,
 248         .lw = hw_read_word,
 249 };
 250
 251 static u32 cache_ctrl;
 252
 253 static void cache_ctrl_write_word(struct lightrec_state *state,
 254                                   u32 op, void *host, u32 mem, u32 val)
 255 {
 256         cache_ctrl = val;
 257 }
 258
 259 static u32 cache_ctrl_read_word(struct lightrec_state *state,
 260                                 u32 op, void *host, u32 mem)
 261 {
 262         return cache_ctrl;
 263 }
 264
 265 static struct lightrec_mem_map_ops cache_ctrl_ops = {
 266         .sw = cache_ctrl_write_word,
 267         .lw = cache_ctrl_read_word,
 268 };
 269
 270 static struct lightrec_mem_map lightrec_map[] = {
 271         [PSX_MAP_KERNEL_USER_RAM] = {
 272                 /* Kernel and user memory */
 273                 .pc = 0x00000000,
 274                 .length = 0x200000,
 275         },
 276         [PSX_MAP_BIOS] = {
 277                 /* BIOS */
 278                 .pc = 0x1fc00000,
 279                 .length = 0x80000,
 280         },
 281         [PSX_MAP_SCRATCH_PAD] = {
 282                 /* Scratch pad */
 283                 .pc = 0x1f800000,
 284                 .length = 0x400,
 285         },
 286         [PSX_MAP_PARALLEL_PORT] = {
 287                 /* Parallel port */
 288                 .pc = 0x1f000000,
 289                 .length = 0x10000,
 290         },
 291         [PSX_MAP_HW_REGISTERS] = {
 292                 /* Hardware registers */
 293                 .pc = 0x1f801000,
 294                 .length = 0x8000,
 295                 .ops = &hw_regs_ops,
 296         },
 297         [PSX_MAP_CACHE_CONTROL] = {
 298                 /* Cache control */
 299                 .pc = 0x5ffe0130,
 300                 .length = 4,
 301                 .ops = &cache_ctrl_ops,
 302         },
 303
 304         /* Mirrors of the kernel/user memory */
 305         [PSX_MAP_MIRROR1] = {
 306                 .pc = 0x00200000,
 307                 .length = 0x200000,
 308                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 309         },
 310         [PSX_MAP_MIRROR2] = {
 311                 .pc = 0x00400000,
 312                 .length = 0x200000,
 313                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 314         },
 315         [PSX_MAP_MIRROR3] = {
 316                 .pc = 0x00600000,
 317                 .length = 0x200000,
 318                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 319         },
 320         [PSX_MAP_CODE_BUFFER] = {
 321                 .length = CODE_BUFFER_SIZE,
 322         },
 323 };
 324
 325 static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
 326 {
 327         if (enable)
 328                 memcpy(psxM, cache_buf, sizeof(cache_buf));
 329         else
 330                 memcpy(cache_buf, psxM, sizeof(cache_buf));
 331 }
 332
 333 static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
 334 {
 335         switch (size) {
 336         case 8:
 337                 switch (kaddr) {
 338                 case 0x1f801040:
 339                 case 0x1f801050:
 340                 case 0x1f801800:
 341                 case 0x1f801801:
 342                 case 0x1f801802:
 343                 case 0x1f801803:
 344                         return false;
 345                 default:
 346                         return true;
 347                 }
 348         case 16:
 349                 switch (kaddr) {
 350                 case 0x1f801040:
 351                 case 0x1f801044:
 352                 case 0x1f801048:
 353                 case 0x1f80104a:
 354                 case 0x1f80104e:
 355                 case 0x1f801050:
 356                 case 0x1f801054:
 357                 case 0x1f80105a:
 358                 case 0x1f80105e:
 359                 case 0x1f801100:
 360                 case 0x1f801104:
 361                 case 0x1f801108:
 362                 case 0x1f801110:
 363                 case 0x1f801114:
 364                 case 0x1f801118:
 365                 case 0x1f801120:
 366                 case 0x1f801124:
 367                 case 0x1f801128:
 368                         return false;
 369                 case 0x1f801070:
 370                 case 0x1f801074:
 371                         return !is_write;
 372                 default:
 373                         return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 374                 }
 375         default:
 376                 switch (kaddr) {
 377                 case 0x1f801040:
 378                 case 0x1f801050:
 379                 case 0x1f801100:
 380                 case 0x1f801104:
 381                 case 0x1f801108:
 382                 case 0x1f801110:
 383                 case 0x1f801114:
 384                 case 0x1f801118:
 385                 case 0x1f801120:
 386                 case 0x1f801124:
 387                 case 0x1f801128:
 388                 case 0x1f801810:
 389                 case 0x1f801814:
 390                 case 0x1f801820:
 391                 case 0x1f801824:
 392                         return false;
 393                 case 0x1f801070:
 394                 case 0x1f801074:
 395                 case 0x1f801088:
 396                 case 0x1f801098:
 397                 case 0x1f8010a8:
 398                 case 0x1f8010b8:
 399                 case 0x1f8010c8:
 400                 case 0x1f8010e8:
 401                 case 0x1f8010f4:
 402                         return !is_write;
 403                 default:
 404                         return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 405                 }
 406         }
 407 }
 408
 409 #if defined(HW_DOL) || defined(HW_RVL)
 410 static void lightrec_code_inv(void *ptr, uint32_t len)
 411 {
 412         extern void DCFlushRange(void *ptr, u32 len);
 413         extern void ICInvalidateRange(void *ptr, u32 len);
 414
 415         DCFlushRange(ptr, len);
 416         ICInvalidateRange(ptr, len);
 417 }
 418 #elif defined(HW_WUP)
 419 static void lightrec_code_inv(void *ptr, uint32_t len)
 420 {
 421         wiiu_clear_cache(ptr, (void *)((uintptr_t)ptr + len));
 422 }
 423 #endif
 424
 425 static const struct lightrec_ops lightrec_ops = {
 426         .cop2_op = cop2_op,
 427         .enable_ram = lightrec_enable_ram,
 428         .hw_direct = lightrec_can_hw_direct,
 429 #if defined(HW_DOL) || defined(HW_RVL) || defined(HW_WUP)
 430         .code_inv = lightrec_code_inv,
 431 #endif
 432 };
 433
 434 static int lightrec_plugin_init(void)
 435 {
 436         lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
 437         lightrec_map[PSX_MAP_BIOS].address = psxR;
 438         lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
 439         lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
 440         lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
 441
 442         if (!LIGHTREC_CUSTOM_MAP) {
 443 #if P_HAVE_MMAP
 444                 code_buffer = mmap(0, CODE_BUFFER_SIZE,
 445                                    PROT_EXEC | PROT_READ | PROT_WRITE,
 446                                    MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
 447                 if (code_buffer == MAP_FAILED)
 448                         return -ENOMEM;
 449 #else
 450                 code_buffer = malloc(CODE_BUFFER_SIZE);
 451                 if (!code_buffer)
 452                         return -ENOMEM;
 453 #endif
 454         }
 455
 456         if (LIGHTREC_CUSTOM_MAP) {
 457                 lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
 458                 lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
 459                 lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
 460         }
 461
 462         lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
 463
 464         use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
 465
 466         lightrec_state = lightrec_init(name,
 467                         lightrec_map, ARRAY_SIZE(lightrec_map),
 468                         &lightrec_ops);
 469
 470         // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
 471         //              (uintptr_t) psxM,
 472         //              (uintptr_t) psxP,
 473         //              (uintptr_t) psxR,
 474         //              (uintptr_t) psxH);
 475
 476 #ifndef _WIN32
 477         signal(SIGPIPE, exit);
 478 #endif
 479         return 0;
 480 }
 481
 482 static void lightrec_plugin_execute_internal(bool block_only)
 483 {
 484         struct lightrec_registers *regs;
 485         u32 flags, cycles_pcsx;
 486
 487         regs = lightrec_get_registers(lightrec_state);
 488         gen_interupt((psxCP0Regs *)regs->cp0);
 489         cycles_pcsx = next_interupt - psxRegs.cycle;
 490         assert((s32)cycles_pcsx > 0);
 491
 492         // step during early boot so that 0x80030000 fastboot hack works
 493         block_stepping = block_only;
 494         if (block_only)
 495                 cycles_pcsx = 0;
 496
 497         if (use_pcsx_interpreter) {
 498                 intExecuteBlock(0);
 499         } else {
 500                 u32 cycles_lightrec = cycles_pcsx_to_lightrec(cycles_pcsx);
 501                 if (unlikely(use_lightrec_interpreter)) {
 502                         psxRegs.pc = lightrec_run_interpreter(lightrec_state,
 503                                                               psxRegs.pc,
 504                                                               cycles_lightrec);
 505                 } else {
 506                         psxRegs.pc = lightrec_execute(lightrec_state,
 507                                                       psxRegs.pc, cycles_lightrec);
 508                 }
 509
 510                 lightrec_tansition_to_pcsx(lightrec_state);
 511
 512                 flags = lightrec_exit_flags(lightrec_state);
 513
 514                 if (flags & LIGHTREC_EXIT_SEGFAULT) {
 515                         fprintf(stderr, "Exiting at cycle 0x%08x\n",
 516                                 psxRegs.cycle);
 517                         exit(1);
 518                 }
 519
 520                 if (flags & LIGHTREC_EXIT_SYSCALL)
 521                         psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
 522         }
 523
 524         if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
 525                 /* Handle software interrupts */
 526                 regs->cp0[13] &= ~0x7c;
 527                 psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
 528         }
 529 }
 530
 531 static void lightrec_plugin_execute(void)
 532 {
 533         extern int stop;
 534
 535         while (!stop)
 536                 lightrec_plugin_execute_internal(false);
 537 }
 538
 539 static void lightrec_plugin_execute_block(enum blockExecCaller caller)
 540 {
 541         lightrec_plugin_execute_internal(true);
 542 }
 543
 544 static void lightrec_plugin_clear(u32 addr, u32 size)
 545 {
 546         if (addr == 0 && size == UINT32_MAX)
 547                 lightrec_invalidate_all(lightrec_state);
 548         else
 549                 /* size * 4: PCSX uses DMA units */
 550                 lightrec_invalidate(lightrec_state, addr, size * 4);
 551 }
 552
 553 static void lightrec_plugin_sync_regs_to_pcsx(void);
 554 static void lightrec_plugin_sync_regs_from_pcsx(void);
 555
 556 static void lightrec_plugin_notify(enum R3000Anote note, void *data)
 557 {
 558         switch (note)
 559         {
 560         case R3000ACPU_NOTIFY_CACHE_ISOLATED:
 561         case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
 562                 /* not used, lightrec calls lightrec_enable_ram() instead */
 563                 break;
 564         case R3000ACPU_NOTIFY_BEFORE_SAVE:
 565                 lightrec_plugin_sync_regs_to_pcsx();
 566                 break;
 567         case R3000ACPU_NOTIFY_AFTER_LOAD:
 568                 lightrec_plugin_sync_regs_from_pcsx();
 569                 break;
 570         }
 571 }
 572
 573 static void lightrec_plugin_apply_config()
 574 {
 575         u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
 576                 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
 577         assert(cycle_mult);
 578         cycle_mult_to_pcsx = (cycle_mult * 1024 + 199) / 200;
 579         cycle_mult_from_pcsx = (200 * 1024 + cycle_mult/2) / cycle_mult;
 580 }
 581
 582 static void lightrec_plugin_shutdown(void)
 583 {
 584         lightrec_destroy(lightrec_state);
 585
 586         if (!LIGHTREC_CUSTOM_MAP) {
 587 #if P_HAVE_MMAP
 588                 munmap(code_buffer, CODE_BUFFER_SIZE);
 589 #else
 590                 free(code_buffer);
 591 #endif
 592         }
 593 }
 594
 595 static void lightrec_plugin_reset(void)
 596 {
 597         struct lightrec_registers *regs;
 598
 599         regs = lightrec_get_registers(lightrec_state);
 600
 601         /* Invalidate all blocks */
 602         lightrec_invalidate_all(lightrec_state);
 603
 604         /* Reset registers */
 605         memset(regs, 0, sizeof(*regs));
 606
 607         regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
 608         regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
 609 }
 610
 611 static void lightrec_plugin_sync_regs_from_pcsx(void)
 612 {
 613         struct lightrec_registers *regs;
 614
 615         regs = lightrec_get_registers(lightrec_state);
 616         memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 617         memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
 618         memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
 619
 620         lightrec_invalidate_all(lightrec_state);
 621 }
 622
 623 static void lightrec_plugin_sync_regs_to_pcsx(void)
 624 {
 625         struct lightrec_registers *regs;
 626
 627         regs = lightrec_get_registers(lightrec_state);
 628         memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 629         memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
 630         memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
 631 }
 632
 633 R3000Acpu psxRec =
 634 {
 635         lightrec_plugin_init,
 636         lightrec_plugin_reset,
 637         lightrec_plugin_execute,
 638         lightrec_plugin_execute_block,
 639         lightrec_plugin_clear,
 640         lightrec_plugin_notify,
 641         lightrec_plugin_apply_config,
 642         lightrec_plugin_shutdown,
 643 };