libpcsxcore/lightrec/plugin.c

   1 #include <lightrec.h>
   2 #include <stdbool.h>
   3 #include <stdio.h>
   4 #include <unistd.h>
   5 #include <signal.h>
   6 #include <assert.h>
   7
   8 #include "../cdrom.h"
   9 #include "../gpu.h"
  10 #include "../gte.h"
  11 #include "../mdec.h"
  12 #include "../psxdma.h"
  13 #include "../psxhw.h"
  14 #include "../psxmem.h"
  15 #include "../r3000a.h"
  16 #include "../psxinterpreter.h"
  17 #include "../new_dynarec/events.h"
  18
  19 #include "../frontend/main.h"
  20
  21 #include "mem.h"
  22 #include "plugin.h"
  23
  24 #if (defined(__arm__) || defined(__aarch64__)) && !defined(ALLOW_LIGHTREC_ON_ARM)
  25 #error "Lightrec should not be used on ARM (please specify DYNAREC=ari64 to make)"
  26 #endif
  27
  28 #define ARRAY_SIZE(x) (sizeof(x) ? sizeof(x) / sizeof((x)[0]) : 0)
  29
  30 #if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
  31 #       define LE32TOH(x)       __builtin_bswap32(x)
  32 #       define HTOLE32(x)       __builtin_bswap32(x)
  33 #       define LE16TOH(x)       __builtin_bswap16(x)
  34 #       define HTOLE16(x)       __builtin_bswap16(x)
  35 #else
  36 #       define LE32TOH(x)       (x)
  37 #       define HTOLE32(x)       (x)
  38 #       define LE16TOH(x)       (x)
  39 #       define HTOLE16(x)       (x)
  40 #endif
  41
  42 #ifdef __GNUC__
  43 #       define likely(x)       __builtin_expect(!!(x),1)
  44 #       define unlikely(x)     __builtin_expect(!!(x),0)
  45 #else
  46 #       define likely(x)       (x)
  47 #       define unlikely(x)     (x)
  48 #endif
  49
  50 psxRegisters psxRegs;
  51 Rcnt rcnts[4];
  52
  53 static struct lightrec_state *lightrec_state;
  54
  55 static char *name = "retroarch.exe";
  56
  57 static bool use_lightrec_interpreter;
  58 static bool use_pcsx_interpreter;
  59 static bool block_stepping;
  60 static u32 cycle_mult_to_pcsx; // 22.10 fractional
  61 static u32 cycle_mult_from_pcsx;
  62
  63 enum my_cp2_opcodes {
  64         OP_CP2_RTPS             = 0x01,
  65         OP_CP2_NCLIP            = 0x06,
  66         OP_CP2_OP               = 0x0c,
  67         OP_CP2_DPCS             = 0x10,
  68         OP_CP2_INTPL            = 0x11,
  69         OP_CP2_MVMVA            = 0x12,
  70         OP_CP2_NCDS             = 0x13,
  71         OP_CP2_CDP              = 0x14,
  72         OP_CP2_NCDT             = 0x16,
  73         OP_CP2_NCCS             = 0x1b,
  74         OP_CP2_CC               = 0x1c,
  75         OP_CP2_NCS              = 0x1e,
  76         OP_CP2_NCT              = 0x20,
  77         OP_CP2_SQR              = 0x28,
  78         OP_CP2_DCPL             = 0x29,
  79         OP_CP2_DPCT             = 0x2a,
  80         OP_CP2_AVSZ3            = 0x2d,
  81         OP_CP2_AVSZ4            = 0x2e,
  82         OP_CP2_RTPT             = 0x30,
  83         OP_CP2_GPF              = 0x3d,
  84         OP_CP2_GPL              = 0x3e,
  85         OP_CP2_NCCT             = 0x3f,
  86 };
  87
  88 static void (*cp2_ops[])(struct psxCP2Regs *) = {
  89         [OP_CP2_RTPS] = gteRTPS,
  90         [OP_CP2_RTPS] = gteRTPS,
  91         [OP_CP2_NCLIP] = gteNCLIP,
  92         [OP_CP2_OP] = gteOP,
  93         [OP_CP2_DPCS] = gteDPCS,
  94         [OP_CP2_INTPL] = gteINTPL,
  95         [OP_CP2_MVMVA] = gteMVMVA,
  96         [OP_CP2_NCDS] = gteNCDS,
  97         [OP_CP2_CDP] = gteCDP,
  98         [OP_CP2_NCDT] = gteNCDT,
  99         [OP_CP2_NCCS] = gteNCCS,
 100         [OP_CP2_CC] = gteCC,
 101         [OP_CP2_NCS] = gteNCS,
 102         [OP_CP2_NCT] = gteNCT,
 103         [OP_CP2_SQR] = gteSQR,
 104         [OP_CP2_DCPL] = gteDCPL,
 105         [OP_CP2_DPCT] = gteDPCT,
 106         [OP_CP2_AVSZ3] = gteAVSZ3,
 107         [OP_CP2_AVSZ4] = gteAVSZ4,
 108         [OP_CP2_RTPT] = gteRTPT,
 109         [OP_CP2_GPF] = gteGPF,
 110         [OP_CP2_GPL] = gteGPL,
 111         [OP_CP2_NCCT] = gteNCCT,
 112 };
 113
 114 static char cache_buf[64 * 1024];
 115
 116 static void cop2_op(struct lightrec_state *state, u32 func)
 117 {
 118         struct lightrec_registers *regs = lightrec_get_registers(state);
 119
 120         psxRegs.code = func;
 121
 122         if (unlikely(!cp2_ops[func & 0x3f])) {
 123                 fprintf(stderr, "Invalid CP2 function %u\n", func);
 124         } else {
 125                 /* This works because regs->cp2c comes right after regs->cp2d,
 126                  * so it can be cast to a pcsxCP2Regs pointer. */
 127                 cp2_ops[func & 0x3f]((psxCP2Regs *) regs->cp2d);
 128         }
 129 }
 130
 131 static bool has_interrupt(void)
 132 {
 133         struct lightrec_registers *regs = lightrec_get_registers(lightrec_state);
 134
 135         return ((psxHu32(0x1070) & psxHu32(0x1074)) &&
 136                 (regs->cp0[12] & 0x401) == 0x401) ||
 137                 (regs->cp0[12] & regs->cp0[13] & 0x0300);
 138 }
 139
 140 static u32 cycles_pcsx_to_lightrec(u32 c)
 141 {
 142         assert((u64)c * cycle_mult_from_pcsx <= (u32)-1);
 143         return c * cycle_mult_from_pcsx >> 10;
 144 }
 145
 146 static void lightrec_tansition_to_pcsx(struct lightrec_state *state)
 147 {
 148         psxRegs.cycle += lightrec_current_cycle_count(state) * cycle_mult_to_pcsx >> 10;
 149         lightrec_reset_cycle_count(state, 0);
 150 }
 151
 152 static void lightrec_tansition_from_pcsx(struct lightrec_state *state)
 153 {
 154         s32 cycles_left = next_interupt - psxRegs.cycle;
 155
 156         if (block_stepping || cycles_left <= 0 || has_interrupt())
 157                 lightrec_set_exit_flags(state, LIGHTREC_EXIT_CHECK_INTERRUPT);
 158         else {
 159                 lightrec_set_target_cycle_count(state,
 160                         cycles_pcsx_to_lightrec(cycles_left));
 161         }
 162 }
 163
 164 static void hw_write_byte(struct lightrec_state *state,
 165                           u32 op, void *host, u32 mem, u8 val)
 166 {
 167         lightrec_tansition_to_pcsx(state);
 168
 169         psxHwWrite8(mem, val);
 170
 171         lightrec_tansition_from_pcsx(state);
 172 }
 173
 174 static void hw_write_half(struct lightrec_state *state,
 175                           u32 op, void *host, u32 mem, u16 val)
 176 {
 177         lightrec_tansition_to_pcsx(state);
 178
 179         psxHwWrite16(mem, val);
 180
 181         lightrec_tansition_from_pcsx(state);
 182 }
 183
 184 static void hw_write_word(struct lightrec_state *state,
 185                           u32 op, void *host, u32 mem, u32 val)
 186 {
 187         lightrec_tansition_to_pcsx(state);
 188
 189         psxHwWrite32(mem, val);
 190
 191         lightrec_tansition_from_pcsx(state);
 192 }
 193
 194 static u8 hw_read_byte(struct lightrec_state *state, u32 op, void *host, u32 mem)
 195 {
 196         u8 val;
 197
 198         lightrec_tansition_to_pcsx(state);
 199
 200         val = psxHwRead8(mem);
 201
 202         lightrec_tansition_from_pcsx(state);
 203
 204         return val;
 205 }
 206
 207 static u16 hw_read_half(struct lightrec_state *state,
 208                         u32 op, void *host, u32 mem)
 209 {
 210         u16 val;
 211
 212         lightrec_tansition_to_pcsx(state);
 213
 214         val = psxHwRead16(mem);
 215
 216         lightrec_tansition_from_pcsx(state);
 217
 218         return val;
 219 }
 220
 221 static u32 hw_read_word(struct lightrec_state *state,
 222                         u32 op, void *host, u32 mem)
 223 {
 224         u32 val;
 225
 226         lightrec_tansition_to_pcsx(state);
 227
 228         val = psxHwRead32(mem);
 229
 230         lightrec_tansition_from_pcsx(state);
 231
 232         return val;
 233 }
 234
 235 static struct lightrec_mem_map_ops hw_regs_ops = {
 236         .sb = hw_write_byte,
 237         .sh = hw_write_half,
 238         .sw = hw_write_word,
 239         .lb = hw_read_byte,
 240         .lh = hw_read_half,
 241         .lw = hw_read_word,
 242 };
 243
 244 static u32 cache_ctrl;
 245
 246 static void cache_ctrl_write_word(struct lightrec_state *state,
 247                                   u32 op, void *host, u32 mem, u32 val)
 248 {
 249         cache_ctrl = val;
 250 }
 251
 252 static u32 cache_ctrl_read_word(struct lightrec_state *state,
 253                                 u32 op, void *host, u32 mem)
 254 {
 255         return cache_ctrl;
 256 }
 257
 258 static struct lightrec_mem_map_ops cache_ctrl_ops = {
 259         .sw = cache_ctrl_write_word,
 260         .lw = cache_ctrl_read_word,
 261 };
 262
 263 static struct lightrec_mem_map lightrec_map[] = {
 264         [PSX_MAP_KERNEL_USER_RAM] = {
 265                 /* Kernel and user memory */
 266                 .pc = 0x00000000,
 267                 .length = 0x200000,
 268         },
 269         [PSX_MAP_BIOS] = {
 270                 /* BIOS */
 271                 .pc = 0x1fc00000,
 272                 .length = 0x80000,
 273         },
 274         [PSX_MAP_SCRATCH_PAD] = {
 275                 /* Scratch pad */
 276                 .pc = 0x1f800000,
 277                 .length = 0x400,
 278         },
 279         [PSX_MAP_PARALLEL_PORT] = {
 280                 /* Parallel port */
 281                 .pc = 0x1f000000,
 282                 .length = 0x10000,
 283         },
 284         [PSX_MAP_HW_REGISTERS] = {
 285                 /* Hardware registers */
 286                 .pc = 0x1f801000,
 287                 .length = 0x2000,
 288                 .ops = &hw_regs_ops,
 289         },
 290         [PSX_MAP_CACHE_CONTROL] = {
 291                 /* Cache control */
 292                 .pc = 0x5ffe0130,
 293                 .length = 4,
 294                 .ops = &cache_ctrl_ops,
 295         },
 296
 297         /* Mirrors of the kernel/user memory */
 298         [PSX_MAP_MIRROR1] = {
 299                 .pc = 0x00200000,
 300                 .length = 0x200000,
 301                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 302         },
 303         [PSX_MAP_MIRROR2] = {
 304                 .pc = 0x00400000,
 305                 .length = 0x200000,
 306                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 307         },
 308         [PSX_MAP_MIRROR3] = {
 309                 .pc = 0x00600000,
 310                 .length = 0x200000,
 311                 .mirror_of = &lightrec_map[PSX_MAP_KERNEL_USER_RAM],
 312         },
 313         [PSX_MAP_CODE_BUFFER] = {
 314                 .length = CODE_BUFFER_SIZE,
 315         },
 316 };
 317
 318 static void lightrec_enable_ram(struct lightrec_state *state, bool enable)
 319 {
 320         if (enable)
 321                 memcpy(psxM, cache_buf, sizeof(cache_buf));
 322         else
 323                 memcpy(cache_buf, psxM, sizeof(cache_buf));
 324 }
 325
 326 static bool lightrec_can_hw_direct(u32 kaddr, bool is_write, u8 size)
 327 {
 328         switch (size) {
 329         case 8:
 330                 switch (kaddr) {
 331                 case 0x1f801040:
 332                 case 0x1f801050:
 333                 case 0x1f801800:
 334                 case 0x1f801801:
 335                 case 0x1f801802:
 336                 case 0x1f801803:
 337                         return false;
 338                 default:
 339                         return true;
 340                 }
 341         case 16:
 342                 switch (kaddr) {
 343                 case 0x1f801040:
 344                 case 0x1f801044:
 345                 case 0x1f801048:
 346                 case 0x1f80104a:
 347                 case 0x1f80104e:
 348                 case 0x1f801050:
 349                 case 0x1f801054:
 350                 case 0x1f80105a:
 351                 case 0x1f80105e:
 352                 case 0x1f801100:
 353                 case 0x1f801104:
 354                 case 0x1f801108:
 355                 case 0x1f801110:
 356                 case 0x1f801114:
 357                 case 0x1f801118:
 358                 case 0x1f801120:
 359                 case 0x1f801124:
 360                 case 0x1f801128:
 361                         return false;
 362                 case 0x1f801070:
 363                 case 0x1f801074:
 364                         return !is_write;
 365                 default:
 366                         return kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 367                 }
 368         default:
 369                 switch (kaddr) {
 370                 case 0x1f801040:
 371                 case 0x1f801050:
 372                 case 0x1f801100:
 373                 case 0x1f801104:
 374                 case 0x1f801108:
 375                 case 0x1f801110:
 376                 case 0x1f801114:
 377                 case 0x1f801118:
 378                 case 0x1f801120:
 379                 case 0x1f801124:
 380                 case 0x1f801128:
 381                 case 0x1f801810:
 382                 case 0x1f801814:
 383                 case 0x1f801820:
 384                 case 0x1f801824:
 385                         return false;
 386                 case 0x1f801070:
 387                 case 0x1f801074:
 388                 case 0x1f801088:
 389                 case 0x1f801098:
 390                 case 0x1f8010a8:
 391                 case 0x1f8010b8:
 392                 case 0x1f8010c8:
 393                 case 0x1f8010e8:
 394                 case 0x1f8010f4:
 395                         return !is_write;
 396                 default:
 397                         return !is_write || kaddr < 0x1f801c00 || kaddr >= 0x1f801e00;
 398                 }
 399         }
 400 }
 401
 402 static const struct lightrec_ops lightrec_ops = {
 403         .cop2_op = cop2_op,
 404         .enable_ram = lightrec_enable_ram,
 405         .hw_direct = lightrec_can_hw_direct,
 406 };
 407
 408 static int lightrec_plugin_init(void)
 409 {
 410         lightrec_map[PSX_MAP_KERNEL_USER_RAM].address = psxM;
 411         lightrec_map[PSX_MAP_BIOS].address = psxR;
 412         lightrec_map[PSX_MAP_SCRATCH_PAD].address = psxH;
 413         lightrec_map[PSX_MAP_HW_REGISTERS].address = psxH + 0x1000;
 414         lightrec_map[PSX_MAP_PARALLEL_PORT].address = psxP;
 415
 416         if (LIGHTREC_CUSTOM_MAP) {
 417                 lightrec_map[PSX_MAP_MIRROR1].address = psxM + 0x200000;
 418                 lightrec_map[PSX_MAP_MIRROR2].address = psxM + 0x400000;
 419                 lightrec_map[PSX_MAP_MIRROR3].address = psxM + 0x600000;
 420                 lightrec_map[PSX_MAP_CODE_BUFFER].address = code_buffer;
 421         }
 422
 423         use_lightrec_interpreter = !!getenv("LIGHTREC_INTERPRETER");
 424
 425         lightrec_state = lightrec_init(name,
 426                         lightrec_map, ARRAY_SIZE(lightrec_map),
 427                         &lightrec_ops);
 428
 429         // fprintf(stderr, "M=0x%lx, P=0x%lx, R=0x%lx, H=0x%lx\n",
 430         //              (uintptr_t) psxM,
 431         //              (uintptr_t) psxP,
 432         //              (uintptr_t) psxR,
 433         //              (uintptr_t) psxH);
 434
 435 #ifndef _WIN32
 436         signal(SIGPIPE, exit);
 437 #endif
 438         return 0;
 439 }
 440
 441 static void lightrec_plugin_execute_internal(bool block_only)
 442 {
 443         struct lightrec_registers *regs;
 444         u32 flags, cycles_pcsx;
 445
 446         regs = lightrec_get_registers(lightrec_state);
 447         gen_interupt((psxCP0Regs *)regs->cp0);
 448         cycles_pcsx = next_interupt - psxRegs.cycle;
 449         assert((s32)cycles_pcsx > 0);
 450
 451         // step during early boot so that 0x80030000 fastboot hack works
 452         block_stepping = block_only;
 453         if (block_only)
 454                 cycles_pcsx = 0;
 455
 456         if (use_pcsx_interpreter) {
 457                 intExecuteBlock(0);
 458         } else {
 459                 u32 cycles_lightrec = cycles_pcsx_to_lightrec(cycles_pcsx);
 460                 if (unlikely(use_lightrec_interpreter)) {
 461                         psxRegs.pc = lightrec_run_interpreter(lightrec_state,
 462                                                               psxRegs.pc,
 463                                                               cycles_lightrec);
 464                 } else {
 465                         psxRegs.pc = lightrec_execute(lightrec_state,
 466                                                       psxRegs.pc, cycles_lightrec);
 467                 }
 468
 469                 lightrec_tansition_to_pcsx(lightrec_state);
 470
 471                 flags = lightrec_exit_flags(lightrec_state);
 472
 473                 if (flags & LIGHTREC_EXIT_SEGFAULT) {
 474                         fprintf(stderr, "Exiting at cycle 0x%08x\n",
 475                                 psxRegs.cycle);
 476                         exit(1);
 477                 }
 478
 479                 if (flags & LIGHTREC_EXIT_SYSCALL)
 480                         psxException(0x20, 0, (psxCP0Regs *)regs->cp0);
 481         }
 482
 483         if ((regs->cp0[13] & regs->cp0[12] & 0x300) && (regs->cp0[12] & 0x1)) {
 484                 /* Handle software interrupts */
 485                 regs->cp0[13] &= ~0x7c;
 486                 psxException(regs->cp0[13], 0, (psxCP0Regs *)regs->cp0);
 487         }
 488 }
 489
 490 static void lightrec_plugin_execute(void)
 491 {
 492         extern int stop;
 493
 494         while (!stop)
 495                 lightrec_plugin_execute_internal(false);
 496 }
 497
 498 static void lightrec_plugin_execute_block(enum blockExecCaller caller)
 499 {
 500         lightrec_plugin_execute_internal(true);
 501 }
 502
 503 static void lightrec_plugin_clear(u32 addr, u32 size)
 504 {
 505         if (addr == 0 && size == UINT32_MAX)
 506                 lightrec_invalidate_all(lightrec_state);
 507         else
 508                 /* size * 4: PCSX uses DMA units */
 509                 lightrec_invalidate(lightrec_state, addr, size * 4);
 510 }
 511
 512 static void lightrec_plugin_sync_regs_to_pcsx(void);
 513 static void lightrec_plugin_sync_regs_from_pcsx(void);
 514
 515 static void lightrec_plugin_notify(enum R3000Anote note, void *data)
 516 {
 517         switch (note)
 518         {
 519         case R3000ACPU_NOTIFY_CACHE_ISOLATED:
 520         case R3000ACPU_NOTIFY_CACHE_UNISOLATED:
 521                 /* not used, lightrec calls lightrec_enable_ram() instead */
 522                 break;
 523         case R3000ACPU_NOTIFY_BEFORE_SAVE:
 524                 lightrec_plugin_sync_regs_to_pcsx();
 525                 break;
 526         case R3000ACPU_NOTIFY_AFTER_LOAD:
 527                 lightrec_plugin_sync_regs_from_pcsx();
 528                 break;
 529         }
 530 }
 531
 532 static void lightrec_plugin_apply_config()
 533 {
 534         u32 cycle_mult = Config.cycle_multiplier_override && Config.cycle_multiplier == CYCLE_MULT_DEFAULT
 535                 ? Config.cycle_multiplier_override : Config.cycle_multiplier;
 536         assert(cycle_mult);
 537         cycle_mult_to_pcsx = (cycle_mult * 1024 + 199) / 200;
 538         cycle_mult_from_pcsx = (200 * 1024 + cycle_mult/2) / cycle_mult;
 539 }
 540
 541 static void lightrec_plugin_shutdown(void)
 542 {
 543         lightrec_destroy(lightrec_state);
 544 }
 545
 546 static void lightrec_plugin_reset(void)
 547 {
 548         struct lightrec_registers *regs;
 549
 550         regs = lightrec_get_registers(lightrec_state);
 551
 552         /* Invalidate all blocks */
 553         lightrec_invalidate_all(lightrec_state);
 554
 555         /* Reset registers */
 556         memset(regs, 0, sizeof(*regs));
 557
 558         regs->cp0[12] = 0x10900000; // COP0 enabled | BEV = 1 | TS = 1
 559         regs->cp0[15] = 0x00000002; // PRevID = Revision ID, same as R3000A
 560 }
 561
 562 static void lightrec_plugin_sync_regs_from_pcsx(void)
 563 {
 564         struct lightrec_registers *regs;
 565
 566         regs = lightrec_get_registers(lightrec_state);
 567         memcpy(regs->cp2d, &psxRegs.CP2, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 568         memcpy(regs->cp0, &psxRegs.CP0, sizeof(regs->cp0));
 569         memcpy(regs->gpr, &psxRegs.GPR, sizeof(regs->gpr));
 570
 571         lightrec_invalidate_all(lightrec_state);
 572 }
 573
 574 static void lightrec_plugin_sync_regs_to_pcsx(void)
 575 {
 576         struct lightrec_registers *regs;
 577
 578         regs = lightrec_get_registers(lightrec_state);
 579         memcpy(&psxRegs.CP2, regs->cp2d, sizeof(regs->cp2d) + sizeof(regs->cp2c));
 580         memcpy(&psxRegs.CP0, regs->cp0, sizeof(regs->cp0));
 581         memcpy(&psxRegs.GPR, regs->gpr, sizeof(regs->gpr));
 582 }
 583
 584 R3000Acpu psxRec =
 585 {
 586         lightrec_plugin_init,
 587         lightrec_plugin_reset,
 588         lightrec_plugin_execute,
 589         lightrec_plugin_execute_block,
 590         lightrec_plugin_clear,
 591         lightrec_plugin_notify,
 592         lightrec_plugin_apply_config,
 593         lightrec_plugin_shutdown,
 594 };