1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus/PCSX - assem_arm.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "../../gte.h"
24 #include "../../gte.h"
26 #include "../../gte_arm.h"
27 #include "../../gte_neon.h"
29 #include "arm_features.h"
31 #if defined(BASE_ADDR_FIXED)
32 #elif defined(BASE_ADDR_DYNAMIC)
33 char *translation_cache;
35 char translation_cache[1 << TARGET_SIZE_2] __attribute__((aligned(4096)));
39 #define CALLER_SAVE_REGS 0x100f
41 #define CALLER_SAVE_REGS 0x120f
44 #define unused __attribute__((unused))
46 extern int cycle_count;
47 extern int last_count;
49 extern int pending_exception;
50 extern int branch_target;
51 extern uint64_t readmem_dword;
52 extern void *dynarec_local;
53 extern u_int mini_ht[32][2];
55 void indirect_jump_indexed();
68 void jump_vaddr_r10();
69 void jump_vaddr_r12();
71 const u_int jump_vaddr_reg[16] = {
89 void invalidate_addr_r0();
90 void invalidate_addr_r1();
91 void invalidate_addr_r2();
92 void invalidate_addr_r3();
93 void invalidate_addr_r4();
94 void invalidate_addr_r5();
95 void invalidate_addr_r6();
96 void invalidate_addr_r7();
97 void invalidate_addr_r8();
98 void invalidate_addr_r9();
99 void invalidate_addr_r10();
100 void invalidate_addr_r12();
102 const u_int invalidate_addr_reg[16] = {
103 (int)invalidate_addr_r0,
104 (int)invalidate_addr_r1,
105 (int)invalidate_addr_r2,
106 (int)invalidate_addr_r3,
107 (int)invalidate_addr_r4,
108 (int)invalidate_addr_r5,
109 (int)invalidate_addr_r6,
110 (int)invalidate_addr_r7,
111 (int)invalidate_addr_r8,
112 (int)invalidate_addr_r9,
113 (int)invalidate_addr_r10,
115 (int)invalidate_addr_r12,
120 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
124 static void set_jump_target(int addr,u_int target)
126 u_char *ptr=(u_char *)addr;
127 u_int *ptr2=(u_int *)ptr;
129 assert((target-(u_int)ptr2-8)<1024);
131 assert((target&3)==0);
132 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
133 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
135 else if(ptr[3]==0x72) {
136 // generated by emit_jno_unlikely
137 if((target-(u_int)ptr2-8)<1024) {
139 assert((target&3)==0);
140 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
142 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
144 assert((target&3)==0);
145 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
147 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
150 assert((ptr[3]&0x0e)==0xa);
151 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
155 // This optionally copies the instruction from the target of the branch into
156 // the space before the branch. Works, but the difference in speed is
157 // usually insignificant.
159 static void set_jump_target_fillslot(int addr,u_int target,int copy)
161 u_char *ptr=(u_char *)addr;
162 u_int *ptr2=(u_int *)ptr;
163 assert(!copy||ptr2[-1]==0xe28dd000);
166 assert((target-(u_int)ptr2-8)<4096);
167 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
170 assert((ptr[3]&0x0e)==0xa);
171 u_int target_insn=*(u_int *)target;
172 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
175 if((target_insn&0x0c100000)==0x04100000) { // Load
178 if(target_insn&0x08000000) {
182 ptr2[-1]=target_insn;
185 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
191 static void add_literal(int addr,int val)
193 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
194 literals[literalcount][0]=addr;
195 literals[literalcount][1]=val;
199 // from a pointer to external jump stub (which was produced by emit_extjump2)
200 // find where the jumping insn is
201 static void *find_extjump_insn(void *stub)
203 int *ptr=(int *)(stub+4);
204 assert((*ptr&0x0fff0000)==0x059f0000); // ldr rx, [pc, #ofs]
205 u_int offset=*ptr&0xfff;
206 void **l_ptr=(void *)ptr+offset+8;
210 // find where external branch is liked to using addr of it's stub:
211 // get address that insn one after stub loads (dyna_linker arg1),
212 // treat it as a pointer to branch insn,
213 // return addr where that branch jumps to
214 static int get_pointer(void *stub)
216 //printf("get_pointer(%x)\n",(int)stub);
217 int *i_ptr=find_extjump_insn(stub);
218 assert((*i_ptr&0x0f000000)==0x0a000000);
219 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
222 // Find the "clean" entry point from a "dirty" entry point
223 // by skipping past the call to verify_code
224 static u_int get_clean_addr(int addr)
226 int *ptr=(int *)addr;
232 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
233 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
235 if((*ptr&0xFF000000)==0xea000000) {
236 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
241 static int verify_dirty(u_int *ptr)
245 // get from literal pool
246 assert((*ptr&0xFFFF0000)==0xe59f0000);
248 u_int source=*(u_int*)((void *)ptr+offset+8);
250 assert((*ptr&0xFFFF0000)==0xe59f0000);
252 u_int copy=*(u_int*)((void *)ptr+offset+8);
254 assert((*ptr&0xFFFF0000)==0xe59f0000);
256 u_int len=*(u_int*)((void *)ptr+offset+8);
261 assert((*ptr&0xFFF00000)==0xe3000000);
262 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
263 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
264 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
267 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
268 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
269 //printf("verify_dirty: %x %x %x\n",source,copy,len);
270 return !memcmp((void *)source,(void *)copy,len);
273 // This doesn't necessarily find all clean entry points, just
274 // guarantees that it's not dirty
275 static int isclean(int addr)
278 u_int *ptr=((u_int *)addr)+4;
280 u_int *ptr=((u_int *)addr)+6;
282 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
283 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
284 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
285 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
286 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
290 // get source that block at addr was compiled from (host pointers)
291 static void get_bounds(int addr,u_int *start,u_int *end)
293 u_int *ptr=(u_int *)addr;
296 // get from literal pool
297 assert((*ptr&0xFFFF0000)==0xe59f0000);
299 u_int source=*(u_int*)((void *)ptr+offset+8);
301 //assert((*ptr&0xFFFF0000)==0xe59f0000);
303 //u_int copy=*(u_int*)((void *)ptr+offset+8);
305 assert((*ptr&0xFFFF0000)==0xe59f0000);
307 u_int len=*(u_int*)((void *)ptr+offset+8);
312 assert((*ptr&0xFFF00000)==0xe3000000);
313 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
314 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
315 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
318 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
319 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
324 /* Register allocation */
326 // Note: registers are allocated clean (unmodified state)
327 // if you intend to modify the register, you must call dirty_reg().
328 static void alloc_reg(struct regstat *cur,int i,signed char reg)
331 int preferred_reg = (reg&7);
332 if(reg==CCREG) preferred_reg=HOST_CCREG;
333 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
335 // Don't allocate unused registers
336 if((cur->u>>reg)&1) return;
338 // see if it's already allocated
339 for(hr=0;hr<HOST_REGS;hr++)
341 if(cur->regmap[hr]==reg) return;
344 // Keep the same mapping if the register was already allocated in a loop
345 preferred_reg = loop_reg(i,reg,preferred_reg);
347 // Try to allocate the preferred register
348 if(cur->regmap[preferred_reg]==-1) {
349 cur->regmap[preferred_reg]=reg;
350 cur->dirty&=~(1<<preferred_reg);
351 cur->isconst&=~(1<<preferred_reg);
354 r=cur->regmap[preferred_reg];
355 if(r<64&&((cur->u>>r)&1)) {
356 cur->regmap[preferred_reg]=reg;
357 cur->dirty&=~(1<<preferred_reg);
358 cur->isconst&=~(1<<preferred_reg);
361 if(r>=64&&((cur->uu>>(r&63))&1)) {
362 cur->regmap[preferred_reg]=reg;
363 cur->dirty&=~(1<<preferred_reg);
364 cur->isconst&=~(1<<preferred_reg);
368 // Clear any unneeded registers
369 // We try to keep the mapping consistent, if possible, because it
370 // makes branches easier (especially loops). So we try to allocate
371 // first (see above) before removing old mappings. If this is not
372 // possible then go ahead and clear out the registers that are no
374 for(hr=0;hr<HOST_REGS;hr++)
379 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
383 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
387 // Try to allocate any available register, but prefer
388 // registers that have not been used recently.
390 for(hr=0;hr<HOST_REGS;hr++) {
391 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
392 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
394 cur->dirty&=~(1<<hr);
395 cur->isconst&=~(1<<hr);
401 // Try to allocate any available register
402 for(hr=0;hr<HOST_REGS;hr++) {
403 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
405 cur->dirty&=~(1<<hr);
406 cur->isconst&=~(1<<hr);
411 // Ok, now we have to evict someone
412 // Pick a register we hopefully won't need soon
413 u_char hsn[MAXREG+1];
414 memset(hsn,10,sizeof(hsn));
416 lsn(hsn,i,&preferred_reg);
417 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
418 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
420 // Don't evict the cycle count at entry points, otherwise the entry
421 // stub will have to write it.
422 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
423 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
426 // Alloc preferred register if available
427 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
428 for(hr=0;hr<HOST_REGS;hr++) {
429 // Evict both parts of a 64-bit register
430 if((cur->regmap[hr]&63)==r) {
432 cur->dirty&=~(1<<hr);
433 cur->isconst&=~(1<<hr);
436 cur->regmap[preferred_reg]=reg;
439 for(r=1;r<=MAXREG;r++)
441 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
442 for(hr=0;hr<HOST_REGS;hr++) {
443 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
444 if(cur->regmap[hr]==r+64) {
446 cur->dirty&=~(1<<hr);
447 cur->isconst&=~(1<<hr);
452 for(hr=0;hr<HOST_REGS;hr++) {
453 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
454 if(cur->regmap[hr]==r) {
456 cur->dirty&=~(1<<hr);
457 cur->isconst&=~(1<<hr);
468 for(r=1;r<=MAXREG;r++)
471 for(hr=0;hr<HOST_REGS;hr++) {
472 if(cur->regmap[hr]==r+64) {
474 cur->dirty&=~(1<<hr);
475 cur->isconst&=~(1<<hr);
479 for(hr=0;hr<HOST_REGS;hr++) {
480 if(cur->regmap[hr]==r) {
482 cur->dirty&=~(1<<hr);
483 cur->isconst&=~(1<<hr);
490 SysPrintf("This shouldn't happen (alloc_reg)");exit(1);
493 static void alloc_reg64(struct regstat *cur,int i,signed char reg)
495 int preferred_reg = 8+(reg&1);
498 // allocate the lower 32 bits
499 alloc_reg(cur,i,reg);
501 // Don't allocate unused registers
502 if((cur->uu>>reg)&1) return;
504 // see if the upper half is already allocated
505 for(hr=0;hr<HOST_REGS;hr++)
507 if(cur->regmap[hr]==reg+64) return;
510 // Keep the same mapping if the register was already allocated in a loop
511 preferred_reg = loop_reg(i,reg,preferred_reg);
513 // Try to allocate the preferred register
514 if(cur->regmap[preferred_reg]==-1) {
515 cur->regmap[preferred_reg]=reg|64;
516 cur->dirty&=~(1<<preferred_reg);
517 cur->isconst&=~(1<<preferred_reg);
520 r=cur->regmap[preferred_reg];
521 if(r<64&&((cur->u>>r)&1)) {
522 cur->regmap[preferred_reg]=reg|64;
523 cur->dirty&=~(1<<preferred_reg);
524 cur->isconst&=~(1<<preferred_reg);
527 if(r>=64&&((cur->uu>>(r&63))&1)) {
528 cur->regmap[preferred_reg]=reg|64;
529 cur->dirty&=~(1<<preferred_reg);
530 cur->isconst&=~(1<<preferred_reg);
534 // Clear any unneeded registers
535 // We try to keep the mapping consistent, if possible, because it
536 // makes branches easier (especially loops). So we try to allocate
537 // first (see above) before removing old mappings. If this is not
538 // possible then go ahead and clear out the registers that are no
540 for(hr=HOST_REGS-1;hr>=0;hr--)
545 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
549 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
553 // Try to allocate any available register, but prefer
554 // registers that have not been used recently.
556 for(hr=0;hr<HOST_REGS;hr++) {
557 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
558 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
559 cur->regmap[hr]=reg|64;
560 cur->dirty&=~(1<<hr);
561 cur->isconst&=~(1<<hr);
567 // Try to allocate any available register
568 for(hr=0;hr<HOST_REGS;hr++) {
569 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
570 cur->regmap[hr]=reg|64;
571 cur->dirty&=~(1<<hr);
572 cur->isconst&=~(1<<hr);
577 // Ok, now we have to evict someone
578 // Pick a register we hopefully won't need soon
579 u_char hsn[MAXREG+1];
580 memset(hsn,10,sizeof(hsn));
582 lsn(hsn,i,&preferred_reg);
583 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
584 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
586 // Don't evict the cycle count at entry points, otherwise the entry
587 // stub will have to write it.
588 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
589 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
592 // Alloc preferred register if available
593 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
594 for(hr=0;hr<HOST_REGS;hr++) {
595 // Evict both parts of a 64-bit register
596 if((cur->regmap[hr]&63)==r) {
598 cur->dirty&=~(1<<hr);
599 cur->isconst&=~(1<<hr);
602 cur->regmap[preferred_reg]=reg|64;
605 for(r=1;r<=MAXREG;r++)
607 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
608 for(hr=0;hr<HOST_REGS;hr++) {
609 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
610 if(cur->regmap[hr]==r+64) {
611 cur->regmap[hr]=reg|64;
612 cur->dirty&=~(1<<hr);
613 cur->isconst&=~(1<<hr);
618 for(hr=0;hr<HOST_REGS;hr++) {
619 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
620 if(cur->regmap[hr]==r) {
621 cur->regmap[hr]=reg|64;
622 cur->dirty&=~(1<<hr);
623 cur->isconst&=~(1<<hr);
634 for(r=1;r<=MAXREG;r++)
637 for(hr=0;hr<HOST_REGS;hr++) {
638 if(cur->regmap[hr]==r+64) {
639 cur->regmap[hr]=reg|64;
640 cur->dirty&=~(1<<hr);
641 cur->isconst&=~(1<<hr);
645 for(hr=0;hr<HOST_REGS;hr++) {
646 if(cur->regmap[hr]==r) {
647 cur->regmap[hr]=reg|64;
648 cur->dirty&=~(1<<hr);
649 cur->isconst&=~(1<<hr);
656 SysPrintf("This shouldn't happen");exit(1);
659 // Allocate a temporary register. This is done without regard to
660 // dirty status or whether the register we request is on the unneeded list
661 // Note: This will only allocate one register, even if called multiple times
662 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
665 int preferred_reg = -1;
667 // see if it's already allocated
668 for(hr=0;hr<HOST_REGS;hr++)
670 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
673 // Try to allocate any available register
674 for(hr=HOST_REGS-1;hr>=0;hr--) {
675 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
677 cur->dirty&=~(1<<hr);
678 cur->isconst&=~(1<<hr);
683 // Find an unneeded register
684 for(hr=HOST_REGS-1;hr>=0;hr--)
690 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
692 cur->dirty&=~(1<<hr);
693 cur->isconst&=~(1<<hr);
700 if((cur->uu>>(r&63))&1) {
701 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
703 cur->dirty&=~(1<<hr);
704 cur->isconst&=~(1<<hr);
712 // Ok, now we have to evict someone
713 // Pick a register we hopefully won't need soon
714 // TODO: we might want to follow unconditional jumps here
715 // TODO: get rid of dupe code and make this into a function
716 u_char hsn[MAXREG+1];
717 memset(hsn,10,sizeof(hsn));
719 lsn(hsn,i,&preferred_reg);
720 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
722 // Don't evict the cycle count at entry points, otherwise the entry
723 // stub will have to write it.
724 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
725 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
728 for(r=1;r<=MAXREG;r++)
730 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
731 for(hr=0;hr<HOST_REGS;hr++) {
732 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
733 if(cur->regmap[hr]==r+64) {
735 cur->dirty&=~(1<<hr);
736 cur->isconst&=~(1<<hr);
741 for(hr=0;hr<HOST_REGS;hr++) {
742 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
743 if(cur->regmap[hr]==r) {
745 cur->dirty&=~(1<<hr);
746 cur->isconst&=~(1<<hr);
757 for(r=1;r<=MAXREG;r++)
760 for(hr=0;hr<HOST_REGS;hr++) {
761 if(cur->regmap[hr]==r+64) {
763 cur->dirty&=~(1<<hr);
764 cur->isconst&=~(1<<hr);
768 for(hr=0;hr<HOST_REGS;hr++) {
769 if(cur->regmap[hr]==r) {
771 cur->dirty&=~(1<<hr);
772 cur->isconst&=~(1<<hr);
779 SysPrintf("This shouldn't happen");exit(1);
782 // Allocate a specific ARM register.
783 static void alloc_arm_reg(struct regstat *cur,int i,signed char reg,int hr)
788 // see if it's already allocated (and dealloc it)
789 for(n=0;n<HOST_REGS;n++)
791 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
792 dirty=(cur->dirty>>n)&1;
798 cur->dirty&=~(1<<hr);
799 cur->dirty|=dirty<<hr;
800 cur->isconst&=~(1<<hr);
803 // Alloc cycle count into dedicated register
804 static void alloc_cc(struct regstat *cur,int i)
806 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
814 static unused char regname[16][4] = {
832 static void output_w32(u_int word)
834 *((u_int *)out)=word;
838 static u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
843 return((rn<<16)|(rd<<12)|rm);
846 static u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
851 assert((shift&1)==0);
852 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
855 static u_int genimm(u_int imm,u_int *encoded)
863 *encoded=((i&30)<<7)|imm;
866 imm=(imm>>2)|(imm<<30);i-=2;
871 static void genimm_checked(u_int imm,u_int *encoded)
873 u_int ret=genimm(imm,encoded);
878 static u_int genjmp(u_int addr)
880 int offset=addr-(int)out-8;
881 if(offset<-33554432||offset>=33554432) {
883 SysPrintf("genjmp: out of range: %08x\n", offset);
888 return ((u_int)offset>>2)&0xffffff;
891 static void emit_mov(int rs,int rt)
893 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
894 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
897 static void emit_movs(int rs,int rt)
899 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
900 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
903 static void emit_add(int rs1,int rs2,int rt)
905 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
906 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
909 static void emit_adds(int rs1,int rs2,int rt)
911 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
912 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
915 static void emit_adcs(int rs1,int rs2,int rt)
917 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
918 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
921 static void emit_sbc(int rs1,int rs2,int rt)
923 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
924 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
927 static void emit_sbcs(int rs1,int rs2,int rt)
929 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
930 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
933 static void emit_neg(int rs, int rt)
935 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
936 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
939 static void emit_negs(int rs, int rt)
941 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
942 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
945 static void emit_sub(int rs1,int rs2,int rt)
947 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
948 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
951 static void emit_subs(int rs1,int rs2,int rt)
953 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
954 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
957 static void emit_zeroreg(int rt)
959 assem_debug("mov %s,#0\n",regname[rt]);
960 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
963 static void emit_loadlp(u_int imm,u_int rt)
965 add_literal((int)out,imm);
966 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
967 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
970 static void emit_movw(u_int imm,u_int rt)
973 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
974 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
977 static void emit_movt(u_int imm,u_int rt)
979 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
980 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
983 static void emit_movimm(u_int imm,u_int rt)
986 if(genimm(imm,&armval)) {
987 assem_debug("mov %s,#%d\n",regname[rt],imm);
988 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
989 }else if(genimm(~imm,&armval)) {
990 assem_debug("mvn %s,#%d\n",regname[rt],imm);
991 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
992 }else if(imm<65536) {
994 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
995 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
996 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
997 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1003 emit_loadlp(imm,rt);
1005 emit_movw(imm&0x0000FFFF,rt);
1006 emit_movt(imm&0xFFFF0000,rt);
1011 static void emit_pcreladdr(u_int rt)
1013 assem_debug("add %s,pc,#?\n",regname[rt]);
1014 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1017 static void emit_loadreg(int r, int hr)
1020 SysPrintf("64bit load in 32bit mode!\n");
1027 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1028 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1029 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1030 if(r==CCREG) addr=(int)&cycle_count;
1031 if(r==CSREG) addr=(int)&Status;
1032 if(r==FSREG) addr=(int)&FCR31;
1033 if(r==INVCP) addr=(int)&invc_ptr;
1034 u_int offset = addr-(u_int)&dynarec_local;
1035 assert(offset<4096);
1036 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1037 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1041 static void emit_storereg(int r, int hr)
1044 SysPrintf("64bit store in 32bit mode!\n");
1048 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1049 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1050 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1051 if(r==CCREG) addr=(int)&cycle_count;
1052 if(r==FSREG) addr=(int)&FCR31;
1053 u_int offset = addr-(u_int)&dynarec_local;
1054 assert(offset<4096);
1055 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1056 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1059 static void emit_test(int rs, int rt)
1061 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1062 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1065 static void emit_testimm(int rs,int imm)
1068 assem_debug("tst %s,#%d\n",regname[rs],imm);
1069 genimm_checked(imm,&armval);
1070 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1073 static void emit_testeqimm(int rs,int imm)
1076 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1077 genimm_checked(imm,&armval);
1078 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1081 static void emit_not(int rs,int rt)
1083 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1084 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1087 static void emit_mvnmi(int rs,int rt)
1089 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1090 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1093 static void emit_and(u_int rs1,u_int rs2,u_int rt)
1095 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1096 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1099 static void emit_or(u_int rs1,u_int rs2,u_int rt)
1101 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1102 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1105 static void emit_or_and_set_flags(int rs1,int rs2,int rt)
1107 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1108 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1111 static void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1116 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1117 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1120 static void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1125 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1126 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1129 static void emit_xor(u_int rs1,u_int rs2,u_int rt)
1131 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1132 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1135 static void emit_addimm(u_int rs,int imm,u_int rt)
1141 if(genimm(imm,&armval)) {
1142 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1143 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1144 }else if(genimm(-imm,&armval)) {
1145 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-imm);
1146 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1148 }else if(rt!=rs&&(u_int)imm<65536) {
1149 emit_movw(imm&0x0000ffff,rt);
1151 }else if(rt!=rs&&(u_int)-imm<65536) {
1152 emit_movw(-imm&0x0000ffff,rt);
1155 }else if((u_int)-imm<65536) {
1156 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1157 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1158 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1159 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1162 int shift = (ffs(imm) - 1) & ~1;
1163 int imm8 = imm & (0xff << shift);
1164 genimm_checked(imm8,&armval);
1165 assem_debug("add %s,%s,#0x%x\n",regname[rt],regname[rs],imm8);
1166 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1173 else if(rs!=rt) emit_mov(rs,rt);
1176 static void emit_addimm_and_set_flags(int imm,int rt)
1178 assert(imm>-65536&&imm<65536);
1180 if(genimm(imm,&armval)) {
1181 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1182 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1183 }else if(genimm(-imm,&armval)) {
1184 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1185 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1187 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1188 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1189 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1190 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1192 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1193 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1194 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1195 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1199 static void emit_addimm_no_flags(u_int imm,u_int rt)
1201 emit_addimm(rt,imm,rt);
1204 static void emit_addnop(u_int r)
1207 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1208 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1211 static void emit_adcimm(u_int rs,int imm,u_int rt)
1214 genimm_checked(imm,&armval);
1215 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1216 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1219 static void emit_rscimm(int rs,int imm,u_int rt)
1223 genimm_checked(imm,&armval);
1224 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1225 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1228 static void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1230 // TODO: if(genimm(imm,&armval)) ...
1232 emit_movimm(imm,HOST_TEMPREG);
1233 emit_adds(HOST_TEMPREG,rsl,rtl);
1234 emit_adcimm(rsh,0,rth);
1237 static void emit_andimm(int rs,int imm,int rt)
1242 }else if(genimm(imm,&armval)) {
1243 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1244 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1245 }else if(genimm(~imm,&armval)) {
1246 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1247 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1248 }else if(imm==65535) {
1250 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1251 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1252 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1253 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1255 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1256 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1259 assert(imm>0&&imm<65535);
1261 assem_debug("mov r14,#%d\n",imm&0xFF00);
1262 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1263 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1264 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1266 emit_movw(imm,HOST_TEMPREG);
1268 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1269 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1273 static void emit_orimm(int rs,int imm,int rt)
1277 if(rs!=rt) emit_mov(rs,rt);
1278 }else if(genimm(imm,&armval)) {
1279 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1280 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1282 assert(imm>0&&imm<65536);
1283 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1284 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1285 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1286 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1290 static void emit_xorimm(int rs,int imm,int rt)
1294 if(rs!=rt) emit_mov(rs,rt);
1295 }else if(genimm(imm,&armval)) {
1296 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1297 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1299 assert(imm>0&&imm<65536);
1300 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1301 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1302 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1303 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1307 static void emit_shlimm(int rs,u_int imm,int rt)
1312 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1313 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1316 static void emit_lsls_imm(int rs,int imm,int rt)
1320 assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1321 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1324 static unused void emit_lslpls_imm(int rs,int imm,int rt)
1328 assem_debug("lslpls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1329 output_w32(0x51b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1332 static void emit_shrimm(int rs,u_int imm,int rt)
1336 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1337 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1340 static void emit_sarimm(int rs,u_int imm,int rt)
1344 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1345 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1348 static void emit_rorimm(int rs,u_int imm,int rt)
1352 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1353 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1356 static void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1358 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1362 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1363 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1364 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1365 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1368 static void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1370 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1374 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1375 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1376 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1377 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1380 static void emit_signextend16(int rs,int rt)
1383 emit_shlimm(rs,16,rt);
1384 emit_sarimm(rt,16,rt);
1386 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1387 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1391 static void emit_signextend8(int rs,int rt)
1394 emit_shlimm(rs,24,rt);
1395 emit_sarimm(rt,24,rt);
1397 assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
1398 output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
1402 static void emit_shl(u_int rs,u_int shift,u_int rt)
1408 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1409 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1412 static void emit_shr(u_int rs,u_int shift,u_int rt)
1417 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1418 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1421 static void emit_sar(u_int rs,u_int shift,u_int rt)
1426 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1427 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1430 static void emit_orrshl(u_int rs,u_int shift,u_int rt)
1435 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1436 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1439 static void emit_orrshr(u_int rs,u_int shift,u_int rt)
1444 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1445 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1448 static void emit_cmpimm(int rs,int imm)
1451 if(genimm(imm,&armval)) {
1452 assem_debug("cmp %s,#%d\n",regname[rs],imm);
1453 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1454 }else if(genimm(-imm,&armval)) {
1455 assem_debug("cmn %s,#%d\n",regname[rs],imm);
1456 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1459 emit_movimm(imm,HOST_TEMPREG);
1460 assem_debug("cmp %s,r14\n",regname[rs]);
1461 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1464 emit_movimm(-imm,HOST_TEMPREG);
1465 assem_debug("cmn %s,r14\n",regname[rs]);
1466 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1470 static void emit_cmovne_imm(int imm,int rt)
1472 assem_debug("movne %s,#%d\n",regname[rt],imm);
1474 genimm_checked(imm,&armval);
1475 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1478 static void emit_cmovl_imm(int imm,int rt)
1480 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1482 genimm_checked(imm,&armval);
1483 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1486 static void emit_cmovb_imm(int imm,int rt)
1488 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1490 genimm_checked(imm,&armval);
1491 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1494 static void emit_cmovs_imm(int imm,int rt)
1496 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1498 genimm_checked(imm,&armval);
1499 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1502 static void emit_cmove_reg(int rs,int rt)
1504 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1505 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1508 static void emit_cmovne_reg(int rs,int rt)
1510 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1511 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1514 static void emit_cmovl_reg(int rs,int rt)
1516 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1517 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1520 static void emit_cmovs_reg(int rs,int rt)
1522 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1523 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1526 static void emit_slti32(int rs,int imm,int rt)
1528 if(rs!=rt) emit_zeroreg(rt);
1529 emit_cmpimm(rs,imm);
1530 if(rs==rt) emit_movimm(0,rt);
1531 emit_cmovl_imm(1,rt);
1534 static void emit_sltiu32(int rs,int imm,int rt)
1536 if(rs!=rt) emit_zeroreg(rt);
1537 emit_cmpimm(rs,imm);
1538 if(rs==rt) emit_movimm(0,rt);
1539 emit_cmovb_imm(1,rt);
1542 static void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1545 emit_slti32(rsl,imm,rt);
1549 emit_cmovne_imm(0,rt);
1550 emit_cmovs_imm(1,rt);
1554 emit_cmpimm(rsh,-1);
1555 emit_cmovne_imm(0,rt);
1556 emit_cmovl_imm(1,rt);
1560 static void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1563 emit_sltiu32(rsl,imm,rt);
1567 emit_cmovne_imm(0,rt);
1571 emit_cmpimm(rsh,-1);
1572 emit_cmovne_imm(1,rt);
1576 static void emit_cmp(int rs,int rt)
1578 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1579 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1582 static void emit_set_gz32(int rs, int rt)
1584 //assem_debug("set_gz32\n");
1587 emit_cmovl_imm(0,rt);
1590 static void emit_set_nz32(int rs, int rt)
1592 //assem_debug("set_nz32\n");
1593 if(rs!=rt) emit_movs(rs,rt);
1594 else emit_test(rs,rs);
1595 emit_cmovne_imm(1,rt);
1598 static void emit_set_gz64_32(int rsh, int rsl, int rt)
1600 //assem_debug("set_gz64\n");
1601 emit_set_gz32(rsl,rt);
1603 emit_cmovne_imm(1,rt);
1604 emit_cmovs_imm(0,rt);
1607 static void emit_set_nz64_32(int rsh, int rsl, int rt)
1609 //assem_debug("set_nz64\n");
1610 emit_or_and_set_flags(rsh,rsl,rt);
1611 emit_cmovne_imm(1,rt);
1614 static void emit_set_if_less32(int rs1, int rs2, int rt)
1616 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1617 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1619 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1620 emit_cmovl_imm(1,rt);
1623 static void emit_set_if_carry32(int rs1, int rs2, int rt)
1625 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1626 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1628 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1629 emit_cmovb_imm(1,rt);
1632 static void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1634 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1639 emit_sbcs(u1,u2,HOST_TEMPREG);
1640 emit_cmovl_imm(1,rt);
1643 static void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1645 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1650 emit_sbcs(u1,u2,HOST_TEMPREG);
1651 emit_cmovb_imm(1,rt);
1654 static void emit_call(int a)
1656 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1657 u_int offset=genjmp(a);
1658 output_w32(0xeb000000|offset);
1661 static void emit_jmp(int a)
1663 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1664 u_int offset=genjmp(a);
1665 output_w32(0xea000000|offset);
1668 static void emit_jne(int a)
1670 assem_debug("bne %x\n",a);
1671 u_int offset=genjmp(a);
1672 output_w32(0x1a000000|offset);
1675 static void emit_jeq(int a)
1677 assem_debug("beq %x\n",a);
1678 u_int offset=genjmp(a);
1679 output_w32(0x0a000000|offset);
1682 static void emit_js(int a)
1684 assem_debug("bmi %x\n",a);
1685 u_int offset=genjmp(a);
1686 output_w32(0x4a000000|offset);
1689 static void emit_jns(int a)
1691 assem_debug("bpl %x\n",a);
1692 u_int offset=genjmp(a);
1693 output_w32(0x5a000000|offset);
1696 static void emit_jl(int a)
1698 assem_debug("blt %x\n",a);
1699 u_int offset=genjmp(a);
1700 output_w32(0xba000000|offset);
1703 static void emit_jge(int a)
1705 assem_debug("bge %x\n",a);
1706 u_int offset=genjmp(a);
1707 output_w32(0xaa000000|offset);
1710 static void emit_jno(int a)
1712 assem_debug("bvc %x\n",a);
1713 u_int offset=genjmp(a);
1714 output_w32(0x7a000000|offset);
1717 static void emit_jc(int a)
1719 assem_debug("bcs %x\n",a);
1720 u_int offset=genjmp(a);
1721 output_w32(0x2a000000|offset);
1724 static void emit_jcc(int a)
1726 assem_debug("bcc %x\n",a);
1727 u_int offset=genjmp(a);
1728 output_w32(0x3a000000|offset);
1731 static void emit_callreg(u_int r)
1734 assem_debug("blx %s\n",regname[r]);
1735 output_w32(0xe12fff30|r);
1738 static void emit_jmpreg(u_int r)
1740 assem_debug("mov pc,%s\n",regname[r]);
1741 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1744 static void emit_readword_indexed(int offset, int rs, int rt)
1746 assert(offset>-4096&&offset<4096);
1747 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1749 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1751 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1755 static void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1757 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1758 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1761 static void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
1763 assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1764 output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
1767 static void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
1769 assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1770 output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
1773 static void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
1775 assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1776 output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
1779 static void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
1781 assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1782 output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
1785 static void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
1787 assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1788 output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
1791 static void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1793 if(map<0) emit_readword_indexed(addr, rs, rt);
1796 emit_readword_dualindexedx4(rs, map, rt);
1800 static void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1803 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1804 emit_readword_indexed(addr+4, rs, rl);
1807 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1808 emit_addimm(map,1,map);
1809 emit_readword_indexed_tlb(addr, rs, map, rl);
1813 static void emit_movsbl_indexed(int offset, int rs, int rt)
1815 assert(offset>-256&&offset<256);
1816 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1818 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1820 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1824 static void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1826 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1829 emit_shlimm(map,2,map);
1830 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1831 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1833 assert(addr>-256&&addr<256);
1834 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1835 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1836 emit_movsbl_indexed(addr, rt, rt);
1841 static void emit_movswl_indexed(int offset, int rs, int rt)
1843 assert(offset>-256&&offset<256);
1844 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1846 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1848 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1852 static void emit_movzbl_indexed(int offset, int rs, int rt)
1854 assert(offset>-4096&&offset<4096);
1855 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1857 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1859 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1863 static void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1865 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1866 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1869 static void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1871 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1874 emit_movzbl_dualindexedx4(rs, map, rt);
1876 emit_addimm(rs,addr,rt);
1877 emit_movzbl_dualindexedx4(rt, map, rt);
1882 static void emit_movzwl_indexed(int offset, int rs, int rt)
1884 assert(offset>-256&&offset<256);
1885 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1887 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1889 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1893 static void emit_ldrd(int offset, int rs, int rt)
1895 assert(offset>-256&&offset<256);
1896 assem_debug("ldrd %s,%s+%d\n",regname[rt],regname[rs],offset);
1898 output_w32(0xe1c000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1900 output_w32(0xe14000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1904 static void emit_readword(int addr, int rt)
1906 u_int offset = addr-(u_int)&dynarec_local;
1907 assert(offset<4096);
1908 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1909 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1912 static unused void emit_movsbl(int addr, int rt)
1914 u_int offset = addr-(u_int)&dynarec_local;
1916 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1917 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1920 static unused void emit_movswl(int addr, int rt)
1922 u_int offset = addr-(u_int)&dynarec_local;
1924 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1925 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1928 static unused void emit_movzbl(int addr, int rt)
1930 u_int offset = addr-(u_int)&dynarec_local;
1931 assert(offset<4096);
1932 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1933 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1936 static unused void emit_movzwl(int addr, int rt)
1938 u_int offset = addr-(u_int)&dynarec_local;
1940 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1941 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1944 static void emit_writeword_indexed(int rt, int offset, int rs)
1946 assert(offset>-4096&&offset<4096);
1947 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1949 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1951 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1955 static void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1957 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1958 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1961 static void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1963 if(map<0) emit_writeword_indexed(rt, addr, rs);
1966 emit_writeword_dualindexedx4(rt, rs, map);
1970 static void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1973 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1974 emit_writeword_indexed(rl, addr+4, rs);
1977 if(temp!=rs) emit_addimm(map,1,temp);
1978 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
1979 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
1981 emit_addimm(rs,4,rs);
1982 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
1987 static void emit_writehword_indexed(int rt, int offset, int rs)
1989 assert(offset>-256&&offset<256);
1990 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
1992 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1994 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1998 static void emit_writebyte_indexed(int rt, int offset, int rs)
2000 assert(offset>-4096&&offset<4096);
2001 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
2003 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
2005 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
2009 static void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
2011 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2012 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
2015 static void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2017 if(map<0) emit_writebyte_indexed(rt, addr, rs);
2020 emit_writebyte_dualindexedx4(rt, rs, map);
2022 emit_addimm(rs,addr,temp);
2023 emit_writebyte_dualindexedx4(rt, temp, map);
2028 static void emit_strcc_dualindexed(int rs1, int rs2, int rt)
2030 assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2031 output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
2034 static void emit_strccb_dualindexed(int rs1, int rs2, int rt)
2036 assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2037 output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
2040 static void emit_strcch_dualindexed(int rs1, int rs2, int rt)
2042 assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2043 output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
2046 static void emit_writeword(int rt, int addr)
2048 u_int offset = addr-(u_int)&dynarec_local;
2049 assert(offset<4096);
2050 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2051 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2054 static unused void emit_writehword(int rt, int addr)
2056 u_int offset = addr-(u_int)&dynarec_local;
2058 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2059 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2062 static unused void emit_writebyte(int rt, int addr)
2064 u_int offset = addr-(u_int)&dynarec_local;
2065 assert(offset<4096);
2066 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2067 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2070 static void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2072 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2077 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2080 static void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2082 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2087 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2090 static void emit_clz(int rs,int rt)
2092 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2093 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2096 static void emit_subcs(int rs1,int rs2,int rt)
2098 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2099 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2102 static void emit_shrcc_imm(int rs,u_int imm,int rt)
2106 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2107 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2110 static void emit_shrne_imm(int rs,u_int imm,int rt)
2114 assem_debug("lsrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2115 output_w32(0x11a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2118 static void emit_negmi(int rs, int rt)
2120 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2121 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2124 static void emit_negsmi(int rs, int rt)
2126 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2127 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2130 static void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2132 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2133 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2136 static void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2138 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2139 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2142 static void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2144 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2145 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2148 static void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2150 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2151 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2154 static void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2156 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2157 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2160 static void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2162 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2163 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2166 static void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2168 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2169 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2172 static void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2174 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2175 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2178 static void emit_teq(int rs, int rt)
2180 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2181 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2184 static void emit_rsbimm(int rs, int imm, int rt)
2187 genimm_checked(imm,&armval);
2188 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2189 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2192 // Load 2 immediates optimizing for small code size
2193 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2195 emit_movimm(imm1,rt1);
2197 if(genimm(imm2-imm1,&armval)) {
2198 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2199 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2200 }else if(genimm(imm1-imm2,&armval)) {
2201 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2202 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2204 else emit_movimm(imm2,rt2);
2207 // Conditionally select one of two immediates, optimizing for small code size
2208 // This will only be called if HAVE_CMOV_IMM is defined
2209 static void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2212 if(genimm(imm2-imm1,&armval)) {
2213 emit_movimm(imm1,rt);
2214 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2215 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2216 }else if(genimm(imm1-imm2,&armval)) {
2217 emit_movimm(imm1,rt);
2218 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2219 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2223 emit_movimm(imm1,rt);
2224 add_literal((int)out,imm2);
2225 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2226 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2228 emit_movw(imm1&0x0000FFFF,rt);
2229 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2230 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2231 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2233 emit_movt(imm1&0xFFFF0000,rt);
2234 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2235 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2236 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2242 // special case for checking invalid_code
2243 static void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2245 assert(imm<128&&imm>=0);
2247 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2248 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2249 emit_cmpimm(HOST_TEMPREG,imm);
2252 static void emit_callne(int a)
2254 assem_debug("blne %x\n",a);
2255 u_int offset=genjmp(a);
2256 output_w32(0x1b000000|offset);
2259 // Used to preload hash table entries
2260 static unused void emit_prefetchreg(int r)
2262 assem_debug("pld %s\n",regname[r]);
2263 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2266 // Special case for mini_ht
2267 static void emit_ldreq_indexed(int rs, u_int offset, int rt)
2269 assert(offset<4096);
2270 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2271 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2274 static unused void emit_bicne_imm(int rs,int imm,int rt)
2277 genimm_checked(imm,&armval);
2278 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2279 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2282 static unused void emit_biccs_imm(int rs,int imm,int rt)
2285 genimm_checked(imm,&armval);
2286 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2287 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2290 static unused void emit_bicvc_imm(int rs,int imm,int rt)
2293 genimm_checked(imm,&armval);
2294 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2295 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2298 static unused void emit_bichi_imm(int rs,int imm,int rt)
2301 genimm_checked(imm,&armval);
2302 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2303 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2306 static unused void emit_orrvs_imm(int rs,int imm,int rt)
2309 genimm_checked(imm,&armval);
2310 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2311 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2314 static void emit_orrne_imm(int rs,int imm,int rt)
2317 genimm_checked(imm,&armval);
2318 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2319 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2322 static void emit_andne_imm(int rs,int imm,int rt)
2325 genimm_checked(imm,&armval);
2326 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2327 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2330 static unused void emit_addpl_imm(int rs,int imm,int rt)
2333 genimm_checked(imm,&armval);
2334 assem_debug("addpl %s,%s,#%d\n",regname[rt],regname[rs],imm);
2335 output_w32(0x52800000|rd_rn_rm(rt,rs,0)|armval);
2338 static void emit_jno_unlikely(int a)
2341 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2342 output_w32(0x72800000|rd_rn_rm(15,15,0));
2345 static void save_regs_all(u_int reglist)
2348 if(!reglist) return;
2349 assem_debug("stmia fp,{");
2352 assem_debug("r%d,",i);
2354 output_w32(0xe88b0000|reglist);
2357 static void restore_regs_all(u_int reglist)
2360 if(!reglist) return;
2361 assem_debug("ldmia fp,{");
2364 assem_debug("r%d,",i);
2366 output_w32(0xe89b0000|reglist);
2369 // Save registers before function call
2370 static void save_regs(u_int reglist)
2372 reglist&=CALLER_SAVE_REGS; // only save the caller-save registers, r0-r3, r12
2373 save_regs_all(reglist);
2376 // Restore registers after function call
2377 static void restore_regs(u_int reglist)
2379 reglist&=CALLER_SAVE_REGS;
2380 restore_regs_all(reglist);
2383 /* Stubs/epilogue */
2385 static void literal_pool(int n)
2387 if(!literalcount) return;
2389 if((int)out-literals[0][0]<4096-n) return;
2393 for(i=0;i<literalcount;i++)
2395 u_int l_addr=(u_int)out;
2398 if(literals[j][1]==literals[i][1]) {
2399 //printf("dup %08x\n",literals[i][1]);
2400 l_addr=literals[j][0];
2404 ptr=(u_int *)literals[i][0];
2405 u_int offset=l_addr-(u_int)ptr-8;
2406 assert(offset<4096);
2407 assert(!(offset&3));
2409 if(l_addr==(u_int)out) {
2410 literals[i][0]=l_addr; // remember for dupes
2411 output_w32(literals[i][1]);
2417 static void literal_pool_jumpover(int n)
2419 if(!literalcount) return;
2421 if((int)out-literals[0][0]<4096-n) return;
2426 set_jump_target(jaddr,(int)out);
2429 static void emit_extjump2(u_int addr, int target, int linker)
2431 u_char *ptr=(u_char *)addr;
2432 assert((ptr[3]&0x0e)==0xa);
2435 emit_loadlp(target,0);
2436 emit_loadlp(addr,1);
2437 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2438 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2440 #ifdef DEBUG_CYCLE_COUNT
2441 emit_readword((int)&last_count,ECX);
2442 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2443 emit_readword((int)&next_interupt,ECX);
2444 emit_writeword(HOST_CCREG,(int)&Count);
2445 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2446 emit_writeword(ECX,(int)&last_count);
2452 static void emit_extjump(int addr, int target)
2454 emit_extjump2(addr, target, (int)dyna_linker);
2457 static void emit_extjump_ds(int addr, int target)
2459 emit_extjump2(addr, target, (int)dyna_linker_ds);
2462 // put rt_val into rt, potentially making use of rs with value rs_val
2463 static void emit_movimm_from(u_int rs_val,int rs,u_int rt_val,int rt)
2467 if(genimm(rt_val,&armval)) {
2468 assem_debug("mov %s,#%d\n",regname[rt],rt_val);
2469 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
2472 if(genimm(~rt_val,&armval)) {
2473 assem_debug("mvn %s,#%d\n",regname[rt],rt_val);
2474 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
2478 if(genimm(diff,&armval)) {
2479 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],diff);
2480 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
2482 }else if(genimm(-diff,&armval)) {
2483 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-diff);
2484 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
2487 emit_movimm(rt_val,rt);
2490 // return 1 if above function can do it's job cheaply
2491 static int is_similar_value(u_int v1,u_int v2)
2495 if(v1==v2) return 1;
2497 for(xs=diff;xs!=0&&(xs&3)==0;xs>>=2)
2499 if(xs<0x100) return 1;
2500 for(xs=-diff;xs!=0&&(xs&3)==0;xs>>=2)
2502 if(xs<0x100) return 1;
2507 static void pass_args(int a0, int a1)
2511 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2513 else if(a0!=0&&a1==0) {
2515 if (a0>=0) emit_mov(a0,0);
2518 if(a0>=0&&a0!=0) emit_mov(a0,0);
2519 if(a1>=0&&a1!=1) emit_mov(a1,1);
2523 static void mov_loadtype_adj(int type,int rs,int rt)
2526 case LOADB_STUB: emit_signextend8(rs,rt); break;
2527 case LOADBU_STUB: emit_andimm(rs,0xff,rt); break;
2528 case LOADH_STUB: emit_signextend16(rs,rt); break;
2529 case LOADHU_STUB: emit_andimm(rs,0xffff,rt); break;
2530 case LOADW_STUB: if(rs!=rt) emit_mov(rs,rt); break;
2535 #include "../backends/psx/pcsxmem.h"
2536 #include "../backends/psx/pcsxmem_inline.c"
2538 static void do_readstub(int n)
2540 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2542 set_jump_target(stubs[n][1],(int)out);
2543 int type=stubs[n][0];
2546 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2547 u_int reglist=stubs[n][7];
2548 signed char *i_regmap=i_regs->regmap;
2550 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2551 rt=get_reg(i_regmap,FTEMP);
2553 rt=get_reg(i_regmap,rt1[i]);
2556 int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
2558 for(r=0;r<=12;r++) {
2559 if(((1<<r)&0x13ff)&&((1<<r)®list)==0) {
2563 if(rt>=0&&rt1[i]!=0)
2570 if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
2572 emit_readword((int)&mem_rtab,temp);
2573 emit_shrimm(rs,12,temp2);
2574 emit_readword_dualindexedx4(temp,temp2,temp2);
2575 emit_lsls_imm(temp2,1,temp2);
2576 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2578 case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
2579 case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
2580 case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
2581 case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
2582 case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
2586 restore_jump=(int)out;
2587 emit_jcc(0); // jump to reg restore
2590 emit_jcc(stubs[n][2]); // return address
2595 if(type==LOADB_STUB||type==LOADBU_STUB)
2596 handler=(int)jump_handler_read8;
2597 if(type==LOADH_STUB||type==LOADHU_STUB)
2598 handler=(int)jump_handler_read16;
2599 if(type==LOADW_STUB)
2600 handler=(int)jump_handler_read32;
2602 pass_args(rs,temp2);
2603 int cc=get_reg(i_regmap,CCREG);
2605 emit_loadreg(CCREG,2);
2606 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2608 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2609 mov_loadtype_adj(type,0,rt);
2612 set_jump_target(restore_jump,(int)out);
2613 restore_regs(reglist);
2614 emit_jmp(stubs[n][2]); // return address
2617 // return memhandler, or get directly accessable address and return 0
2618 static u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
2621 l1=((u_int *)table)[addr>>12];
2622 if((l1&(1<<31))==0) {
2629 if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
2630 l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2631 else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
2632 l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
2634 l2=((u_int *)l1)[(addr&0xfff)/4];
2635 if((l2&(1<<31))==0) {
2637 *addr_host=v+(addr&0xfff);
2644 static void inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2646 int rs=get_reg(regmap,target);
2647 int rt=get_reg(regmap,target);
2648 if(rs<0) rs=get_reg(regmap,-1);
2650 u_int handler,host_addr=0,is_dynamic,far_call=0;
2651 int cc=get_reg(regmap,CCREG);
2652 if(pcsx_direct_read(type,addr,CLOCK_ADJUST(adj+1),cc,target?rs:-1,rt))
2654 handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
2659 emit_movimm_from(addr,rs,host_addr,rs);
2661 case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
2662 case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
2663 case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
2664 case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
2665 case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
2670 is_dynamic=pcsxmem_is_handler_dynamic(addr);
2672 if(type==LOADB_STUB||type==LOADBU_STUB)
2673 handler=(int)jump_handler_read8;
2674 if(type==LOADH_STUB||type==LOADHU_STUB)
2675 handler=(int)jump_handler_read16;
2676 if(type==LOADW_STUB)
2677 handler=(int)jump_handler_read32;
2680 // call a memhandler
2681 if(rt>=0&&rt1[i]!=0)
2685 emit_movimm(addr,0);
2688 int offset=(int)handler-(int)out-8;
2689 if(offset<-33554432||offset>=33554432) {
2690 // unreachable memhandler, a plugin func perhaps
2691 emit_movimm(handler,12);
2695 emit_loadreg(CCREG,2);
2697 emit_movimm(((u_int *)mem_rtab)[addr>>12]<<1,1);
2698 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2701 emit_readword((int)&last_count,3);
2702 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2704 emit_writeword(2,(int)&Count);
2712 if(rt>=0&&rt1[i]!=0) {
2714 case LOADB_STUB: emit_signextend8(0,rt); break;
2715 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2716 case LOADH_STUB: emit_signextend16(0,rt); break;
2717 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2718 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2722 restore_regs(reglist);
2725 static void do_writestub(int n)
2727 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2729 set_jump_target(stubs[n][1],(int)out);
2730 int type=stubs[n][0];
2733 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2734 u_int reglist=stubs[n][7];
2735 signed char *i_regmap=i_regs->regmap;
2737 if(itype[i]==C1LS||itype[i]==C2LS) {
2738 rt=get_reg(i_regmap,r=FTEMP);
2740 rt=get_reg(i_regmap,r=rs2[i]);
2744 int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
2745 int reglist2=reglist|(1<<rs)|(1<<rt);
2746 for(rtmp=0;rtmp<=12;rtmp++) {
2747 if(((1<<rtmp)&0x13ff)&&((1<<rtmp)®list2)==0) {
2754 for(rtmp=0;rtmp<=3;rtmp++)
2755 if(rtmp!=rs&&rtmp!=rt)
2758 if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
2760 emit_readword((int)&mem_wtab,temp);
2761 emit_shrimm(rs,12,temp2);
2762 emit_readword_dualindexedx4(temp,temp2,temp2);
2763 emit_lsls_imm(temp2,1,temp2);
2765 case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
2766 case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
2767 case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
2771 restore_jump=(int)out;
2772 emit_jcc(0); // jump to reg restore
2775 emit_jcc(stubs[n][2]); // return address (invcode check)
2781 case STOREB_STUB: handler=(int)jump_handler_write8; break;
2782 case STOREH_STUB: handler=(int)jump_handler_write16; break;
2783 case STOREW_STUB: handler=(int)jump_handler_write32; break;
2789 int cc=get_reg(i_regmap,CCREG);
2791 emit_loadreg(CCREG,2);
2792 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2793 // returns new cycle_count
2795 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
2797 emit_storereg(CCREG,2);
2799 set_jump_target(restore_jump,(int)out);
2800 restore_regs(reglist);
2805 static void inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2807 int rs=get_reg(regmap,-1);
2808 int rt=get_reg(regmap,target);
2811 u_int handler,host_addr=0;
2812 handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
2815 emit_movimm_from(addr,rs,host_addr,rs);
2817 case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
2818 case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
2819 case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
2825 // call a memhandler
2828 int cc=get_reg(regmap,CCREG);
2830 emit_loadreg(CCREG,2);
2831 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2832 emit_movimm(handler,3);
2833 // returns new cycle_count
2834 emit_call((int)jump_handler_write_h);
2835 emit_addimm(0,-CLOCK_ADJUST(adj+1),cc<0?2:cc);
2837 emit_storereg(CCREG,2);
2838 restore_regs(reglist);
2841 static void do_unalignedwritestub(int n)
2843 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
2845 set_jump_target(stubs[n][1],(int)out);
2848 struct regstat *i_regs=(struct regstat *)stubs[n][4];
2849 int addr=stubs[n][5];
2850 u_int reglist=stubs[n][7];
2851 signed char *i_regmap=i_regs->regmap;
2852 int temp2=get_reg(i_regmap,FTEMP);
2854 rt=get_reg(i_regmap,rs2[i]);
2857 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
2859 reglist&=~(1<<temp2);
2862 // don't bother with it and call write handler
2865 int cc=get_reg(i_regmap,CCREG);
2867 emit_loadreg(CCREG,2);
2868 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2869 emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
2870 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
2872 emit_storereg(CCREG,2);
2873 restore_regs(reglist);
2874 emit_jmp(stubs[n][2]); // return address
2876 emit_andimm(addr,0xfffffffc,temp2);
2877 emit_writeword(temp2,(int)&address);
2880 emit_shrimm(addr,16,1);
2881 int cc=get_reg(i_regmap,CCREG);
2883 emit_loadreg(CCREG,2);
2885 emit_movimm((u_int)readmem,0);
2886 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2887 emit_call((int)&indirect_jump_indexed);
2888 restore_regs(reglist);
2890 emit_readword((int)&readmem_dword,temp2);
2891 int temp=addr; //hmh
2892 emit_shlimm(addr,3,temp);
2893 emit_andimm(temp,24,temp);
2894 #ifdef BIG_ENDIAN_MIPS
2895 if (opcode[i]==0x2e) // SWR
2897 if (opcode[i]==0x2a) // SWL
2899 emit_xorimm(temp,24,temp);
2900 emit_movimm(-1,HOST_TEMPREG);
2901 if (opcode[i]==0x2a) { // SWL
2902 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
2903 emit_orrshr(rt,temp,temp2);
2905 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
2906 emit_orrshl(rt,temp,temp2);
2908 emit_readword((int)&address,addr);
2909 emit_writeword(temp2,(int)&word);
2910 //save_regs(reglist); // don't need to, no state changes
2911 emit_shrimm(addr,16,1);
2912 emit_movimm((u_int)writemem,0);
2913 //emit_call((int)&indirect_jump_indexed);
2915 emit_readword_dualindexedx4(0,1,15);
2916 emit_readword((int)&Count,HOST_TEMPREG);
2917 emit_readword((int)&next_interupt,2);
2918 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2919 emit_writeword(2,(int)&last_count);
2920 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2922 emit_storereg(CCREG,HOST_TEMPREG);
2924 restore_regs(reglist);
2925 emit_jmp(stubs[n][2]); // return address
2929 static void do_invstub(int n)
2932 u_int reglist=stubs[n][3];
2933 set_jump_target(stubs[n][1],(int)out);
2935 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
2936 emit_call((int)&invalidate_addr);
2937 restore_regs(reglist);
2938 emit_jmp(stubs[n][2]); // return address
2941 int do_dirty_stub(int i)
2943 assem_debug("do_dirty_stub %x\n",start+i*4);
2944 u_int addr=(u_int)source;
2945 // Careful about the code output here, verify_dirty needs to parse it.
2947 emit_loadlp(addr,1);
2948 emit_loadlp((int)copy,2);
2949 emit_loadlp(slen*4,3);
2951 emit_movw(addr&0x0000FFFF,1);
2952 emit_movw(((u_int)copy)&0x0000FFFF,2);
2953 emit_movt(addr&0xFFFF0000,1);
2954 emit_movt(((u_int)copy)&0xFFFF0000,2);
2955 emit_movw(slen*4,3);
2957 emit_movimm(start+i*4,0);
2958 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
2961 if(entry==(int)out) entry=instr_addr[i];
2962 emit_jmp(instr_addr[i]);
2966 static void do_dirty_stub_ds()
2968 // Careful about the code output here, verify_dirty needs to parse it.
2970 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
2971 emit_loadlp((int)copy,2);
2972 emit_loadlp(slen*4,3);
2974 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
2975 emit_movw(((u_int)copy)&0x0000FFFF,2);
2976 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
2977 emit_movt(((u_int)copy)&0xFFFF0000,2);
2978 emit_movw(slen*4,3);
2980 emit_movimm(start+1,0);
2981 emit_call((int)&verify_code_ds);
2984 static void do_cop1stub(int n)
2987 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
2988 set_jump_target(stubs[n][1],(int)out);
2990 // int rs=stubs[n][4];
2991 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2994 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2995 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
2997 //else {printf("fp exception in delay slot\n");}
2998 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
2999 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3000 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3001 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3002 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3007 static void shift_assemble_arm(int i,struct regstat *i_regs)
3010 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3012 signed char s,t,shift;
3013 t=get_reg(i_regs->regmap,rt1[i]);
3014 s=get_reg(i_regs->regmap,rs1[i]);
3015 shift=get_reg(i_regs->regmap,rs2[i]);
3024 if(s!=t) emit_mov(s,t);
3028 emit_andimm(shift,31,HOST_TEMPREG);
3029 if(opcode2[i]==4) // SLLV
3031 emit_shl(s,HOST_TEMPREG,t);
3033 if(opcode2[i]==6) // SRLV
3035 emit_shr(s,HOST_TEMPREG,t);
3037 if(opcode2[i]==7) // SRAV
3039 emit_sar(s,HOST_TEMPREG,t);
3043 } else { // DSLLV/DSRLV/DSRAV
3044 signed char sh,sl,th,tl,shift;
3045 th=get_reg(i_regs->regmap,rt1[i]|64);
3046 tl=get_reg(i_regs->regmap,rt1[i]);
3047 sh=get_reg(i_regs->regmap,rs1[i]|64);
3048 sl=get_reg(i_regs->regmap,rs1[i]);
3049 shift=get_reg(i_regs->regmap,rs2[i]);
3054 if(th>=0) emit_zeroreg(th);
3059 if(sl!=tl) emit_mov(sl,tl);
3060 if(th>=0&&sh!=th) emit_mov(sh,th);
3064 // FIXME: What if shift==tl ?
3066 int temp=get_reg(i_regs->regmap,-1);
3068 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3071 emit_andimm(shift,31,HOST_TEMPREG);
3072 if(opcode2[i]==0x14) // DSLLV
3074 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3075 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3076 emit_orrshr(sl,HOST_TEMPREG,th);
3077 emit_andimm(shift,31,HOST_TEMPREG);
3078 emit_testimm(shift,32);
3079 emit_shl(sl,HOST_TEMPREG,tl);
3080 if(th>=0) emit_cmovne_reg(tl,th);
3081 emit_cmovne_imm(0,tl);
3083 if(opcode2[i]==0x16) // DSRLV
3086 emit_shr(sl,HOST_TEMPREG,tl);
3087 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3088 emit_orrshl(sh,HOST_TEMPREG,tl);
3089 emit_andimm(shift,31,HOST_TEMPREG);
3090 emit_testimm(shift,32);
3091 emit_shr(sh,HOST_TEMPREG,th);
3092 emit_cmovne_reg(th,tl);
3093 if(real_th>=0) emit_cmovne_imm(0,th);
3095 if(opcode2[i]==0x17) // DSRAV
3098 emit_shr(sl,HOST_TEMPREG,tl);
3099 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3102 emit_sarimm(th,31,temp);
3104 emit_orrshl(sh,HOST_TEMPREG,tl);
3105 emit_andimm(shift,31,HOST_TEMPREG);
3106 emit_testimm(shift,32);
3107 emit_sar(sh,HOST_TEMPREG,th);
3108 emit_cmovne_reg(th,tl);
3109 if(real_th>=0) emit_cmovne_reg(temp,th);
3117 static void speculate_mov(int rs,int rt)
3120 smrv_strong_next|=1<<rt;
3125 static void speculate_mov_weak(int rs,int rt)
3128 smrv_weak_next|=1<<rt;
3133 static void speculate_register_values(int i)
3136 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3137 // gp,sp are likely to stay the same throughout the block
3138 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3139 smrv_weak_next=~smrv_strong_next;
3140 //printf(" llr %08x\n", smrv[4]);
3142 smrv_strong=smrv_strong_next;
3143 smrv_weak=smrv_weak_next;
3146 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3147 else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
3148 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3149 else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
3151 smrv_strong_next&=~(1<<rt1[i]);
3152 smrv_weak_next&=~(1<<rt1[i]);
3156 smrv_strong_next&=~(1<<rt1[i]);
3157 smrv_weak_next&=~(1<<rt1[i]);
3160 if(rt1[i]&&is_const(®s[i],rt1[i])) {
3161 int value,hr=get_reg(regs[i].regmap,rt1[i]);
3163 if(get_final_value(hr,i,&value))
3165 else smrv[rt1[i]]=constmap[i][hr];
3166 smrv_strong_next|=1<<rt1[i];
3170 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3171 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3175 if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
3176 // special case for BIOS
3177 smrv[rt1[i]]=0xa0000000;
3178 smrv_strong_next|=1<<rt1[i];
3185 smrv_strong_next&=~(1<<rt1[i]);
3186 smrv_weak_next&=~(1<<rt1[i]);
3190 if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
3191 smrv_strong_next&=~(1<<rt1[i]);
3192 smrv_weak_next&=~(1<<rt1[i]);
3196 if (opcode[i]==0x32) { // LWC2
3197 smrv_strong_next&=~(1<<rt1[i]);
3198 smrv_weak_next&=~(1<<rt1[i]);
3204 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
3205 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
3217 static int get_ptr_mem_type(u_int a)
3219 if(a < 0x00200000) {
3220 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
3221 // return wrong, must use memhandler for BIOS self-test to pass
3222 // 007 does similar stuff from a00 mirror, weird stuff
3226 if(0x1f800000 <= a && a < 0x1f801000)
3228 if(0x80200000 <= a && a < 0x80800000)
3230 if(0xa0000000 <= a && a < 0xa0200000)
3235 static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
3239 if(((smrv_strong|smrv_weak)>>mr)&1) {
3240 type=get_ptr_mem_type(smrv[mr]);
3241 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
3244 // use the mirror we are running on
3245 type=get_ptr_mem_type(start);
3246 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
3249 if(type==MTYPE_8020) { // RAM 80200000+ mirror
3250 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3251 addr=*addr_reg_override=HOST_TEMPREG;
3254 else if(type==MTYPE_0000) { // RAM 0 mirror
3255 emit_orimm(addr,0x80000000,HOST_TEMPREG);
3256 addr=*addr_reg_override=HOST_TEMPREG;
3259 else if(type==MTYPE_A000) { // RAM A mirror
3260 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
3261 addr=*addr_reg_override=HOST_TEMPREG;
3264 else if(type==MTYPE_1F80) { // scratchpad
3265 if (psxH == (void *)0x1f800000) {
3266 emit_addimm(addr,-0x1f800000,HOST_TEMPREG);
3267 emit_cmpimm(HOST_TEMPREG,0x1000);
3272 // do usual RAM check, jump will go to the right handler
3279 emit_cmpimm(addr,RAM_SIZE);
3281 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3282 // Hint to branch predictor that the branch is unlikely to be taken
3284 emit_jno_unlikely(0);
3289 emit_addimm(addr,ram_offset,HOST_TEMPREG);
3290 addr=*addr_reg_override=HOST_TEMPREG;
3297 #define shift_assemble shift_assemble_arm
3299 static void loadlr_assemble_arm(int i,struct regstat *i_regs)
3301 int s,th,tl,temp,temp2,addr,map=-1;
3304 int memtarget=0,c=0;
3305 int fastload_reg_override=0;
3307 th=get_reg(i_regs->regmap,rt1[i]|64);
3308 tl=get_reg(i_regs->regmap,rt1[i]);
3309 s=get_reg(i_regs->regmap,rs1[i]);
3310 temp=get_reg(i_regs->regmap,-1);
3311 temp2=get_reg(i_regs->regmap,FTEMP);
3312 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3315 for(hr=0;hr<HOST_REGS;hr++) {
3316 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3319 if(offset||s<0||c) addr=temp2;
3322 c=(i_regs->wasconst>>s)&1;
3324 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3329 map=get_reg(i_regs->regmap,ROREG);
3330 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3332 emit_shlimm(addr,3,temp);
3333 if (opcode[i]==0x22||opcode[i]==0x26) {
3334 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3336 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3338 jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override);
3341 if(ram_offset&&memtarget) {
3342 emit_addimm(temp2,ram_offset,HOST_TEMPREG);
3343 fastload_reg_override=HOST_TEMPREG;
3345 if (opcode[i]==0x22||opcode[i]==0x26) {
3346 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3348 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3351 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3354 if(fastload_reg_override) a=fastload_reg_override;
3355 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3356 emit_readword_indexed_tlb(0,a,map,temp2);
3357 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3360 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3363 emit_andimm(temp,24,temp);
3364 #ifdef BIG_ENDIAN_MIPS
3365 if (opcode[i]==0x26) // LWR
3367 if (opcode[i]==0x22) // LWL
3369 emit_xorimm(temp,24,temp);
3370 emit_movimm(-1,HOST_TEMPREG);
3371 if (opcode[i]==0x26) {
3372 emit_shr(temp2,temp,temp2);
3373 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3375 emit_shl(temp2,temp,temp2);
3376 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3378 emit_or(temp2,tl,tl);
3380 //emit_storereg(rt1[i],tl); // DEBUG
3382 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3383 // FIXME: little endian, fastload_reg_override
3384 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3386 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3387 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3388 emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2);
3389 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3392 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3396 emit_testimm(temp,32);
3397 emit_andimm(temp,24,temp);
3398 if (opcode[i]==0x1A) { // LDL
3399 emit_rsbimm(temp,32,HOST_TEMPREG);
3400 emit_shl(temp2h,temp,temp2h);
3401 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3402 emit_movimm(-1,HOST_TEMPREG);
3403 emit_shl(temp2,temp,temp2);
3404 emit_cmove_reg(temp2h,th);
3405 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3406 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3407 emit_orreq(temp2,tl,tl);
3408 emit_orrne(temp2,th,th);
3410 if (opcode[i]==0x1B) { // LDR
3411 emit_xorimm(temp,24,temp);
3412 emit_rsbimm(temp,32,HOST_TEMPREG);
3413 emit_shr(temp2,temp,temp2);
3414 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3415 emit_movimm(-1,HOST_TEMPREG);
3416 emit_shr(temp2h,temp,temp2h);
3417 emit_cmovne_reg(temp2,tl);
3418 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3419 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3420 emit_orrne(temp2h,th,th);
3421 emit_orreq(temp2h,tl,tl);
3426 #define loadlr_assemble loadlr_assemble_arm
3428 static void cop0_assemble(int i,struct regstat *i_regs)
3430 if(opcode2[i]==0) // MFC0
3432 signed char t=get_reg(i_regs->regmap,rt1[i]);
3433 char copr=(source[i]>>11)&0x1f;
3434 //assert(t>=0); // Why does this happen? OOT is weird
3435 if(t>=0&&rt1[i]!=0) {
3436 emit_readword((int)®_cop0+copr*4,t);
3439 else if(opcode2[i]==4) // MTC0
3441 signed char s=get_reg(i_regs->regmap,rs1[i]);
3442 char copr=(source[i]>>11)&0x1f;
3444 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3445 if(copr==9||copr==11||copr==12||copr==13) {
3446 emit_readword((int)&last_count,HOST_TEMPREG);
3447 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3448 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3449 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3450 emit_writeword(HOST_CCREG,(int)&Count);
3452 // What a mess. The status register (12) can enable interrupts,
3453 // so needs a special case to handle a pending interrupt.
3454 // The interrupt must be taken immediately, because a subsequent
3455 // instruction might disable interrupts again.
3456 if(copr==12||copr==13) {
3458 // burn cycles to cause cc_interrupt, which will
3459 // reschedule next_interupt. Relies on CCREG from above.
3460 assem_debug("MTC0 DS %d\n", copr);
3461 emit_writeword(HOST_CCREG,(int)&last_count);
3462 emit_movimm(0,HOST_CCREG);
3463 emit_storereg(CCREG,HOST_CCREG);
3464 emit_loadreg(rs1[i],1);
3465 emit_movimm(copr,0);
3466 emit_call((int)pcsx_mtc0_ds);
3467 emit_loadreg(rs1[i],s);
3470 emit_movimm(start+i*4+4,HOST_TEMPREG);
3471 emit_writeword(HOST_TEMPREG,(int)&pcaddr);
3472 emit_movimm(0,HOST_TEMPREG);
3473 emit_writeword(HOST_TEMPREG,(int)&pending_exception);
3475 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3478 emit_loadreg(rs1[i],1);
3481 emit_movimm(copr,0);
3482 emit_call((int)pcsx_mtc0);
3483 if(copr==9||copr==11||copr==12||copr==13) {
3484 emit_readword((int)&Count,HOST_CCREG);
3485 emit_readword((int)&next_interupt,HOST_TEMPREG);
3486 emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3487 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3488 emit_writeword(HOST_TEMPREG,(int)&last_count);
3489 emit_storereg(CCREG,HOST_CCREG);
3491 if(copr==12||copr==13) {
3492 assert(!is_delayslot);
3493 emit_readword((int)&pending_exception,14);
3495 emit_jne((int)&do_interrupt);
3497 emit_loadreg(rs1[i],s);
3498 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3499 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3504 assert(opcode2[i]==0x10);
3505 if((source[i]&0x3f)==0x10) // RFE
3507 emit_readword((int)&Status,0);
3508 emit_andimm(0,0x3c,1);
3509 emit_andimm(0,~0xf,0);
3510 emit_orrshr_imm(1,2,0);
3511 emit_writeword(0,(int)&Status);
3516 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3526 emit_readword((int)®_cop2d[copr],tl);
3527 emit_signextend16(tl,tl);
3528 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3535 emit_readword((int)®_cop2d[copr],tl);
3536 emit_andimm(tl,0xffff,tl);
3537 emit_writeword(tl,(int)®_cop2d[copr]);
3540 emit_readword((int)®_cop2d[14],tl); // SXY2
3541 emit_writeword(tl,(int)®_cop2d[copr]);
3545 emit_readword((int)®_cop2d[9],temp);
3546 emit_testimm(temp,0x8000); // do we need this?
3547 emit_andimm(temp,0xf80,temp);
3548 emit_andne_imm(temp,0,temp);
3549 emit_shrimm(temp,7,tl);
3550 emit_readword((int)®_cop2d[10],temp);
3551 emit_testimm(temp,0x8000);
3552 emit_andimm(temp,0xf80,temp);
3553 emit_andne_imm(temp,0,temp);
3554 emit_orrshr_imm(temp,2,tl);
3555 emit_readword((int)®_cop2d[11],temp);
3556 emit_testimm(temp,0x8000);
3557 emit_andimm(temp,0xf80,temp);
3558 emit_andne_imm(temp,0,temp);
3559 emit_orrshl_imm(temp,3,tl);
3560 emit_writeword(tl,(int)®_cop2d[copr]);
3563 emit_readword((int)®_cop2d[copr],tl);
3568 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3572 emit_readword((int)®_cop2d[13],temp); // SXY1
3573 emit_writeword(sl,(int)®_cop2d[copr]);
3574 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3575 emit_readword((int)®_cop2d[14],temp); // SXY2
3576 emit_writeword(sl,(int)®_cop2d[14]);
3577 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3580 emit_andimm(sl,0x001f,temp);
3581 emit_shlimm(temp,7,temp);
3582 emit_writeword(temp,(int)®_cop2d[9]);
3583 emit_andimm(sl,0x03e0,temp);
3584 emit_shlimm(temp,2,temp);
3585 emit_writeword(temp,(int)®_cop2d[10]);
3586 emit_andimm(sl,0x7c00,temp);
3587 emit_shrimm(temp,3,temp);
3588 emit_writeword(temp,(int)®_cop2d[11]);
3589 emit_writeword(sl,(int)®_cop2d[28]);
3593 emit_mvnmi(temp,temp);
3595 emit_clz(temp,temp);
3597 emit_movs(temp,HOST_TEMPREG);
3598 emit_movimm(0,temp);
3599 emit_jeq((int)out+4*4);
3600 emit_addpl_imm(temp,1,temp);
3601 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3602 emit_jns((int)out-2*4);
3604 emit_writeword(sl,(int)®_cop2d[30]);
3605 emit_writeword(temp,(int)®_cop2d[31]);
3610 emit_writeword(sl,(int)®_cop2d[copr]);
3615 static void cop2_assemble(int i,struct regstat *i_regs)
3617 u_int copr=(source[i]>>11)&0x1f;
3618 signed char temp=get_reg(i_regs->regmap,-1);
3619 if (opcode2[i]==0) { // MFC2
3620 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3621 if(tl>=0&&rt1[i]!=0)
3622 cop2_get_dreg(copr,tl,temp);
3624 else if (opcode2[i]==4) { // MTC2
3625 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3626 cop2_put_dreg(copr,sl,temp);
3628 else if (opcode2[i]==2) // CFC2
3630 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3631 if(tl>=0&&rt1[i]!=0)
3632 emit_readword((int)®_cop2c[copr],tl);
3634 else if (opcode2[i]==6) // CTC2
3636 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3645 emit_signextend16(sl,temp);
3648 //value = value & 0x7ffff000;
3649 //if (value & 0x7f87e000) value |= 0x80000000;
3650 emit_shrimm(sl,12,temp);
3651 emit_shlimm(temp,12,temp);
3652 emit_testimm(temp,0x7f000000);
3653 emit_testeqimm(temp,0x00870000);
3654 emit_testeqimm(temp,0x0000e000);
3655 emit_orrne_imm(temp,0x80000000,temp);
3661 emit_writeword(temp,(int)®_cop2c[copr]);
3666 static void c2op_prologue(u_int op,u_int reglist)
3668 save_regs_all(reglist);
3671 emit_call((int)pcnt_gte_start);
3673 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs
3676 static void c2op_epilogue(u_int op,u_int reglist)
3680 emit_call((int)pcnt_gte_end);
3682 restore_regs_all(reglist);
3685 static void c2op_call_MACtoIR(int lm,int need_flags)
3688 emit_call((int)(lm?gteMACtoIR_lm1:gteMACtoIR_lm0));
3690 emit_call((int)(lm?gteMACtoIR_lm1_nf:gteMACtoIR_lm0_nf));
3693 static void c2op_call_rgb_func(void *func,int lm,int need_ir,int need_flags)
3695 emit_call((int)func);
3696 // func is C code and trashes r0
3697 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3698 if(need_flags||need_ir)
3699 c2op_call_MACtoIR(lm,need_flags);
3700 emit_call((int)(need_flags?gteMACtoRGB:gteMACtoRGB_nf));
3703 static void c2op_assemble(int i,struct regstat *i_regs)
3705 u_int c2op=source[i]&0x3f;
3706 u_int hr,reglist_full=0,reglist;
3707 int need_flags,need_ir;
3708 for(hr=0;hr<HOST_REGS;hr++) {
3709 if(i_regs->regmap[hr]>=0) reglist_full|=1<<hr;
3711 reglist=reglist_full&CALLER_SAVE_REGS;
3713 if (gte_handlers[c2op]!=NULL) {
3714 need_flags=!(gte_unneeded[i+1]>>63); // +1 because of how liveness detection works
3715 need_ir=(gte_unneeded[i+1]&0xe00)!=0xe00;
3716 assem_debug("gte op %08x, unneeded %016llx, need_flags %d, need_ir %d\n",
3717 source[i],gte_unneeded[i+1],need_flags,need_ir);
3718 if(new_dynarec_hacks&NDHACK_GTE_NO_FLAGS)
3720 int shift = (source[i] >> 19) & 1;
3721 int lm = (source[i] >> 10) & 1;
3726 int v = (source[i] >> 15) & 3;
3727 int cv = (source[i] >> 13) & 3;
3728 int mx = (source[i] >> 17) & 3;
3729 reglist=reglist_full&(CALLER_SAVE_REGS|0xf0); // +{r4-r7}
3730 c2op_prologue(c2op,reglist);
3731 /* r4,r5 = VXYZ(v) packed; r6 = &MX11(mx); r7 = &CV1(cv) */
3735 emit_movzwl_indexed(9*4,0,4); // gteIR
3736 emit_movzwl_indexed(10*4,0,6);
3737 emit_movzwl_indexed(11*4,0,5);
3738 emit_orrshl_imm(6,16,4);
3741 emit_addimm(0,32*4+mx*8*4,6);
3743 emit_readword((int)&zeromem_ptr,6);
3745 emit_addimm(0,32*4+(cv*8+5)*4,7);
3747 emit_readword((int)&zeromem_ptr,7);
3749 emit_movimm(source[i],1); // opcode
3750 emit_call((int)gteMVMVA_part_neon);
3753 emit_call((int)gteMACtoIR_flags_neon);
3757 emit_call((int)gteMVMVA_part_cv3sh12_arm);
3759 emit_movimm(shift,1);
3760 emit_call((int)(need_flags?gteMVMVA_part_arm:gteMVMVA_part_nf_arm));
3762 if(need_flags||need_ir)
3763 c2op_call_MACtoIR(lm,need_flags);
3765 #else /* if not HAVE_ARMV5 */
3766 c2op_prologue(c2op,reglist);
3767 emit_movimm(source[i],1); // opcode
3768 emit_writeword(1,(int)&psxRegs.code);
3769 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
3774 c2op_prologue(c2op,reglist);
3775 emit_call((int)(shift?gteOP_part_shift:gteOP_part_noshift));
3776 if(need_flags||need_ir) {
3777 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3778 c2op_call_MACtoIR(lm,need_flags);
3782 c2op_prologue(c2op,reglist);
3783 c2op_call_rgb_func(shift?gteDPCS_part_shift:gteDPCS_part_noshift,lm,need_ir,need_flags);
3786 c2op_prologue(c2op,reglist);
3787 c2op_call_rgb_func(shift?gteINTPL_part_shift:gteINTPL_part_noshift,lm,need_ir,need_flags);
3790 c2op_prologue(c2op,reglist);
3791 emit_call((int)(shift?gteSQR_part_shift:gteSQR_part_noshift));
3792 if(need_flags||need_ir) {
3793 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3794 c2op_call_MACtoIR(lm,need_flags);
3798 c2op_prologue(c2op,reglist);
3799 c2op_call_rgb_func(gteDCPL_part,lm,need_ir,need_flags);
3802 c2op_prologue(c2op,reglist);
3803 c2op_call_rgb_func(shift?gteGPF_part_shift:gteGPF_part_noshift,lm,need_ir,need_flags);
3806 c2op_prologue(c2op,reglist);
3807 c2op_call_rgb_func(shift?gteGPL_part_shift:gteGPL_part_noshift,lm,need_ir,need_flags);
3811 c2op_prologue(c2op,reglist);
3813 emit_movimm(source[i],1); // opcode
3814 emit_writeword(1,(int)&psxRegs.code);
3816 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
3819 c2op_epilogue(c2op,reglist);
3823 static void cop1_unusable(int i,struct regstat *i_regs)
3825 // XXX: should just just do the exception instead
3829 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3834 static void cop1_assemble(int i,struct regstat *i_regs)
3836 cop1_unusable(i, i_regs);
3839 static void fconv_assemble_arm(int i,struct regstat *i_regs)
3841 cop1_unusable(i, i_regs);
3843 #define fconv_assemble fconv_assemble_arm
3845 static void fcomp_assemble(int i,struct regstat *i_regs)
3847 cop1_unusable(i, i_regs);
3850 static void float_assemble(int i,struct regstat *i_regs)
3852 cop1_unusable(i, i_regs);
3855 static void multdiv_assemble_arm(int i,struct regstat *i_regs)
3862 // case 0x1D: DMULTU
3867 if((opcode2[i]&4)==0) // 32-bit
3869 if(opcode2[i]==0x18) // MULT
3871 signed char m1=get_reg(i_regs->regmap,rs1[i]);
3872 signed char m2=get_reg(i_regs->regmap,rs2[i]);
3873 signed char hi=get_reg(i_regs->regmap,HIREG);
3874 signed char lo=get_reg(i_regs->regmap,LOREG);
3879 emit_smull(m1,m2,hi,lo);
3881 if(opcode2[i]==0x19) // MULTU
3883 signed char m1=get_reg(i_regs->regmap,rs1[i]);
3884 signed char m2=get_reg(i_regs->regmap,rs2[i]);
3885 signed char hi=get_reg(i_regs->regmap,HIREG);
3886 signed char lo=get_reg(i_regs->regmap,LOREG);
3891 emit_umull(m1,m2,hi,lo);
3893 if(opcode2[i]==0x1A) // DIV
3895 signed char d1=get_reg(i_regs->regmap,rs1[i]);
3896 signed char d2=get_reg(i_regs->regmap,rs2[i]);
3899 signed char quotient=get_reg(i_regs->regmap,LOREG);
3900 signed char remainder=get_reg(i_regs->regmap,HIREG);
3901 assert(quotient>=0);
3902 assert(remainder>=0);
3903 emit_movs(d1,remainder);
3904 emit_movimm(0xffffffff,quotient);
3905 emit_negmi(quotient,quotient); // .. quotient and ..
3906 emit_negmi(remainder,remainder); // .. remainder for div0 case (will be negated back after jump)
3907 emit_movs(d2,HOST_TEMPREG);
3908 emit_jeq((int)out+52); // Division by zero
3909 emit_negsmi(HOST_TEMPREG,HOST_TEMPREG);
3911 emit_clz(HOST_TEMPREG,quotient);
3912 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
3914 emit_movimm(0,quotient);
3915 emit_addpl_imm(quotient,1,quotient);
3916 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3917 emit_jns((int)out-2*4);
3919 emit_orimm(quotient,1<<31,quotient);
3920 emit_shr(quotient,quotient,quotient);
3921 emit_cmp(remainder,HOST_TEMPREG);
3922 emit_subcs(remainder,HOST_TEMPREG,remainder);
3923 emit_adcs(quotient,quotient,quotient);
3924 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
3925 emit_jcc((int)out-16); // -4
3927 emit_negmi(quotient,quotient);
3929 emit_negmi(remainder,remainder);
3931 if(opcode2[i]==0x1B) // DIVU
3933 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
3934 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
3937 signed char quotient=get_reg(i_regs->regmap,LOREG);
3938 signed char remainder=get_reg(i_regs->regmap,HIREG);
3939 assert(quotient>=0);
3940 assert(remainder>=0);
3941 emit_mov(d1,remainder);
3942 emit_movimm(0xffffffff,quotient); // div0 case
3944 emit_jeq((int)out+40); // Division by zero
3946 emit_clz(d2,HOST_TEMPREG);
3947 emit_movimm(1<<31,quotient);
3948 emit_shl(d2,HOST_TEMPREG,d2);
3950 emit_movimm(0,HOST_TEMPREG);
3951 emit_addpl_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3952 emit_lslpls_imm(d2,1,d2);
3953 emit_jns((int)out-2*4);
3954 emit_movimm(1<<31,quotient);
3956 emit_shr(quotient,HOST_TEMPREG,quotient);
3957 emit_cmp(remainder,d2);
3958 emit_subcs(remainder,d2,remainder);
3959 emit_adcs(quotient,quotient,quotient);
3960 emit_shrcc_imm(d2,1,d2);
3961 emit_jcc((int)out-16); // -4
3969 // Multiply by zero is zero.
3970 // MIPS does not have a divide by zero exception.
3971 // The result is undefined, we return zero.
3972 signed char hr=get_reg(i_regs->regmap,HIREG);
3973 signed char lr=get_reg(i_regs->regmap,LOREG);
3974 if(hr>=0) emit_zeroreg(hr);
3975 if(lr>=0) emit_zeroreg(lr);
3978 #define multdiv_assemble multdiv_assemble_arm
3980 static void do_preload_rhash(int r) {
3981 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
3982 // register. On ARM the hash can be done with a single instruction (below)
3985 static void do_preload_rhtbl(int ht) {
3986 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
3989 static void do_rhash(int rs,int rh) {
3990 emit_andimm(rs,0xf8,rh);
3993 static void do_miniht_load(int ht,int rh) {
3994 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
3995 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
3998 static void do_miniht_jump(int rs,int rh,int ht) {
4000 emit_ldreq_indexed(ht,4,15);
4001 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4003 emit_jmp(jump_vaddr_reg[7]);
4005 emit_jmp(jump_vaddr_reg[rs]);
4009 static void do_miniht_insert(u_int return_address,int rt,int temp) {
4011 emit_movimm(return_address,rt); // PC into link register
4012 add_to_linker((int)out,return_address,1);
4013 emit_pcreladdr(temp);
4014 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4015 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4017 emit_movw(return_address&0x0000FFFF,rt);
4018 add_to_linker((int)out,return_address,1);
4019 emit_pcreladdr(temp);
4020 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4021 emit_movt(return_address&0xFFFF0000,rt);
4022 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4026 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4028 //if(dirty_pre==dirty) return;
4030 for(hr=0;hr<HOST_REGS;hr++) {
4031 if(hr!=EXCLUDE_REG) {
4033 if(((~u)>>(reg&63))&1) {
4035 if(((dirty_pre&~dirty)>>hr)&1) {
4037 emit_storereg(reg,hr);
4038 if( ((is32_pre&~uu)>>reg)&1 ) {
4039 emit_sarimm(hr,31,HOST_TEMPREG);
4040 emit_storereg(reg|64,HOST_TEMPREG);
4044 emit_storereg(reg,hr);
4054 /* using strd could possibly help but you'd have to allocate registers in pairs
4055 static void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4059 for(hr=HOST_REGS-1;hr>=0;hr--) {
4060 if(hr!=EXCLUDE_REG) {
4061 if(pre[hr]!=entry[hr]) {
4064 if(get_reg(entry,pre[hr])<0) {
4066 if(!((u>>pre[hr])&1)) {
4067 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4068 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4069 emit_sarimm(hr,31,hr+1);
4070 emit_strdreg(pre[hr],hr);
4073 emit_storereg(pre[hr],hr);
4075 emit_storereg(pre[hr],hr);
4076 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4077 emit_sarimm(hr,31,hr);
4078 emit_storereg(pre[hr]|64,hr);
4083 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4084 emit_storereg(pre[hr],hr);
4094 for(hr=0;hr<HOST_REGS;hr++) {
4095 if(hr!=EXCLUDE_REG) {
4096 if(pre[hr]!=entry[hr]) {
4099 if((nr=get_reg(entry,pre[hr]))>=0) {
4107 #define wb_invalidate wb_invalidate_arm
4110 static void mark_clear_cache(void *target)
4112 u_long offset = (char *)target - (char *)BASE_ADDR;
4113 u_int mask = 1u << ((offset >> 12) & 31);
4114 if (!(needs_clear_cache[offset >> 17] & mask)) {
4115 char *start = (char *)((u_long)target & ~4095ul);
4116 start_tcache_write(start, start + 4096);
4117 needs_clear_cache[offset >> 17] |= mask;
4121 // Clearing the cache is rather slow on ARM Linux, so mark the areas
4122 // that need to be cleared, and then only clear these areas once.
4123 static void do_clear_cache()
4126 for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
4128 u_int bitmap=needs_clear_cache[i];
4134 start=(u_int)BASE_ADDR+i*131072+j*4096;
4142 end_tcache_write((void *)start,(void *)end);
4148 needs_clear_cache[i]=0;
4153 // CPU-architecture-specific initialization
4154 static void arch_init() {
4157 // vim:shiftwidth=2:expandtab