1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus/PCSX - assem_arm.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
26 #include "../gte_arm.h"
27 #include "../gte_neon.h"
29 #include "arm_features.h"
32 char translation_cache[1 << TARGET_SIZE_2] __attribute__((aligned(4096)));
36 #define CALLER_SAVE_REGS 0x100f
38 #define CALLER_SAVE_REGS 0x120f
41 #define unused __attribute__((unused))
43 extern int cycle_count;
44 extern int last_count;
46 extern int pending_exception;
47 extern int branch_target;
48 extern uint64_t readmem_dword;
49 extern void *dynarec_local;
50 extern u_int mini_ht[32][2];
52 void indirect_jump_indexed();
65 void jump_vaddr_r10();
66 void jump_vaddr_r12();
68 const u_int jump_vaddr_reg[16] = {
86 void invalidate_addr_r0();
87 void invalidate_addr_r1();
88 void invalidate_addr_r2();
89 void invalidate_addr_r3();
90 void invalidate_addr_r4();
91 void invalidate_addr_r5();
92 void invalidate_addr_r6();
93 void invalidate_addr_r7();
94 void invalidate_addr_r8();
95 void invalidate_addr_r9();
96 void invalidate_addr_r10();
97 void invalidate_addr_r12();
99 const u_int invalidate_addr_reg[16] = {
100 (int)invalidate_addr_r0,
101 (int)invalidate_addr_r1,
102 (int)invalidate_addr_r2,
103 (int)invalidate_addr_r3,
104 (int)invalidate_addr_r4,
105 (int)invalidate_addr_r5,
106 (int)invalidate_addr_r6,
107 (int)invalidate_addr_r7,
108 (int)invalidate_addr_r8,
109 (int)invalidate_addr_r9,
110 (int)invalidate_addr_r10,
112 (int)invalidate_addr_r12,
117 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
121 static void set_jump_target(int addr,u_int target)
123 u_char *ptr=(u_char *)addr;
124 u_int *ptr2=(u_int *)ptr;
126 assert((target-(u_int)ptr2-8)<1024);
128 assert((target&3)==0);
129 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
130 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
132 else if(ptr[3]==0x72) {
133 // generated by emit_jno_unlikely
134 if((target-(u_int)ptr2-8)<1024) {
136 assert((target&3)==0);
137 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
139 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
141 assert((target&3)==0);
142 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
144 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
147 assert((ptr[3]&0x0e)==0xa);
148 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
152 // This optionally copies the instruction from the target of the branch into
153 // the space before the branch. Works, but the difference in speed is
154 // usually insignificant.
156 static void set_jump_target_fillslot(int addr,u_int target,int copy)
158 u_char *ptr=(u_char *)addr;
159 u_int *ptr2=(u_int *)ptr;
160 assert(!copy||ptr2[-1]==0xe28dd000);
163 assert((target-(u_int)ptr2-8)<4096);
164 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
167 assert((ptr[3]&0x0e)==0xa);
168 u_int target_insn=*(u_int *)target;
169 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
172 if((target_insn&0x0c100000)==0x04100000) { // Load
175 if(target_insn&0x08000000) {
179 ptr2[-1]=target_insn;
182 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
188 static void add_literal(int addr,int val)
190 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
191 literals[literalcount][0]=addr;
192 literals[literalcount][1]=val;
196 // from a pointer to external jump stub (which was produced by emit_extjump2)
197 // find where the jumping insn is
198 static void *find_extjump_insn(void *stub)
200 int *ptr=(int *)(stub+4);
201 assert((*ptr&0x0fff0000)==0x059f0000); // ldr rx, [pc, #ofs]
202 u_int offset=*ptr&0xfff;
203 void **l_ptr=(void *)ptr+offset+8;
207 // find where external branch is liked to using addr of it's stub:
208 // get address that insn one after stub loads (dyna_linker arg1),
209 // treat it as a pointer to branch insn,
210 // return addr where that branch jumps to
211 static int get_pointer(void *stub)
213 //printf("get_pointer(%x)\n",(int)stub);
214 int *i_ptr=find_extjump_insn(stub);
215 assert((*i_ptr&0x0f000000)==0x0a000000);
216 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
219 // Find the "clean" entry point from a "dirty" entry point
220 // by skipping past the call to verify_code
221 static u_int get_clean_addr(int addr)
223 int *ptr=(int *)addr;
229 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
230 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
232 if((*ptr&0xFF000000)==0xea000000) {
233 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
238 static int verify_dirty(u_int *ptr)
241 // get from literal pool
242 assert((*ptr&0xFFFF0000)==0xe59f0000);
243 u_int offset=*ptr&0xfff;
244 u_int *l_ptr=(void *)ptr+offset+8;
245 u_int source=l_ptr[0];
251 assert((*ptr&0xFFF00000)==0xe3000000);
252 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
253 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
254 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
257 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
258 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
259 //printf("verify_dirty: %x %x %x\n",source,copy,len);
260 return !memcmp((void *)source,(void *)copy,len);
263 // This doesn't necessarily find all clean entry points, just
264 // guarantees that it's not dirty
265 static int isclean(int addr)
268 u_int *ptr=((u_int *)addr)+4;
270 u_int *ptr=((u_int *)addr)+6;
272 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
273 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
274 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
275 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
276 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
280 // get source that block at addr was compiled from (host pointers)
281 static void get_bounds(int addr,u_int *start,u_int *end)
283 u_int *ptr=(u_int *)addr;
285 // get from literal pool
286 assert((*ptr&0xFFFF0000)==0xe59f0000);
287 u_int offset=*ptr&0xfff;
288 u_int *l_ptr=(void *)ptr+offset+8;
289 u_int source=l_ptr[0];
290 //u_int copy=l_ptr[1];
295 assert((*ptr&0xFFF00000)==0xe3000000);
296 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
297 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
298 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
301 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
302 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
307 /* Register allocation */
309 // Note: registers are allocated clean (unmodified state)
310 // if you intend to modify the register, you must call dirty_reg().
311 static void alloc_reg(struct regstat *cur,int i,signed char reg)
314 int preferred_reg = (reg&7);
315 if(reg==CCREG) preferred_reg=HOST_CCREG;
316 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
318 // Don't allocate unused registers
319 if((cur->u>>reg)&1) return;
321 // see if it's already allocated
322 for(hr=0;hr<HOST_REGS;hr++)
324 if(cur->regmap[hr]==reg) return;
327 // Keep the same mapping if the register was already allocated in a loop
328 preferred_reg = loop_reg(i,reg,preferred_reg);
330 // Try to allocate the preferred register
331 if(cur->regmap[preferred_reg]==-1) {
332 cur->regmap[preferred_reg]=reg;
333 cur->dirty&=~(1<<preferred_reg);
334 cur->isconst&=~(1<<preferred_reg);
337 r=cur->regmap[preferred_reg];
338 if(r<64&&((cur->u>>r)&1)) {
339 cur->regmap[preferred_reg]=reg;
340 cur->dirty&=~(1<<preferred_reg);
341 cur->isconst&=~(1<<preferred_reg);
344 if(r>=64&&((cur->uu>>(r&63))&1)) {
345 cur->regmap[preferred_reg]=reg;
346 cur->dirty&=~(1<<preferred_reg);
347 cur->isconst&=~(1<<preferred_reg);
351 // Clear any unneeded registers
352 // We try to keep the mapping consistent, if possible, because it
353 // makes branches easier (especially loops). So we try to allocate
354 // first (see above) before removing old mappings. If this is not
355 // possible then go ahead and clear out the registers that are no
357 for(hr=0;hr<HOST_REGS;hr++)
362 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
366 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
370 // Try to allocate any available register, but prefer
371 // registers that have not been used recently.
373 for(hr=0;hr<HOST_REGS;hr++) {
374 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
375 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
377 cur->dirty&=~(1<<hr);
378 cur->isconst&=~(1<<hr);
384 // Try to allocate any available register
385 for(hr=0;hr<HOST_REGS;hr++) {
386 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
388 cur->dirty&=~(1<<hr);
389 cur->isconst&=~(1<<hr);
394 // Ok, now we have to evict someone
395 // Pick a register we hopefully won't need soon
396 u_char hsn[MAXREG+1];
397 memset(hsn,10,sizeof(hsn));
399 lsn(hsn,i,&preferred_reg);
400 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
401 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
403 // Don't evict the cycle count at entry points, otherwise the entry
404 // stub will have to write it.
405 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
406 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
409 // Alloc preferred register if available
410 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
411 for(hr=0;hr<HOST_REGS;hr++) {
412 // Evict both parts of a 64-bit register
413 if((cur->regmap[hr]&63)==r) {
415 cur->dirty&=~(1<<hr);
416 cur->isconst&=~(1<<hr);
419 cur->regmap[preferred_reg]=reg;
422 for(r=1;r<=MAXREG;r++)
424 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
425 for(hr=0;hr<HOST_REGS;hr++) {
426 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
427 if(cur->regmap[hr]==r+64) {
429 cur->dirty&=~(1<<hr);
430 cur->isconst&=~(1<<hr);
435 for(hr=0;hr<HOST_REGS;hr++) {
436 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
437 if(cur->regmap[hr]==r) {
439 cur->dirty&=~(1<<hr);
440 cur->isconst&=~(1<<hr);
451 for(r=1;r<=MAXREG;r++)
454 for(hr=0;hr<HOST_REGS;hr++) {
455 if(cur->regmap[hr]==r+64) {
457 cur->dirty&=~(1<<hr);
458 cur->isconst&=~(1<<hr);
462 for(hr=0;hr<HOST_REGS;hr++) {
463 if(cur->regmap[hr]==r) {
465 cur->dirty&=~(1<<hr);
466 cur->isconst&=~(1<<hr);
473 SysPrintf("This shouldn't happen (alloc_reg)");exit(1);
476 static void alloc_reg64(struct regstat *cur,int i,signed char reg)
478 int preferred_reg = 8+(reg&1);
481 // allocate the lower 32 bits
482 alloc_reg(cur,i,reg);
484 // Don't allocate unused registers
485 if((cur->uu>>reg)&1) return;
487 // see if the upper half is already allocated
488 for(hr=0;hr<HOST_REGS;hr++)
490 if(cur->regmap[hr]==reg+64) return;
493 // Keep the same mapping if the register was already allocated in a loop
494 preferred_reg = loop_reg(i,reg,preferred_reg);
496 // Try to allocate the preferred register
497 if(cur->regmap[preferred_reg]==-1) {
498 cur->regmap[preferred_reg]=reg|64;
499 cur->dirty&=~(1<<preferred_reg);
500 cur->isconst&=~(1<<preferred_reg);
503 r=cur->regmap[preferred_reg];
504 if(r<64&&((cur->u>>r)&1)) {
505 cur->regmap[preferred_reg]=reg|64;
506 cur->dirty&=~(1<<preferred_reg);
507 cur->isconst&=~(1<<preferred_reg);
510 if(r>=64&&((cur->uu>>(r&63))&1)) {
511 cur->regmap[preferred_reg]=reg|64;
512 cur->dirty&=~(1<<preferred_reg);
513 cur->isconst&=~(1<<preferred_reg);
517 // Clear any unneeded registers
518 // We try to keep the mapping consistent, if possible, because it
519 // makes branches easier (especially loops). So we try to allocate
520 // first (see above) before removing old mappings. If this is not
521 // possible then go ahead and clear out the registers that are no
523 for(hr=HOST_REGS-1;hr>=0;hr--)
528 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
532 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
536 // Try to allocate any available register, but prefer
537 // registers that have not been used recently.
539 for(hr=0;hr<HOST_REGS;hr++) {
540 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
541 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
542 cur->regmap[hr]=reg|64;
543 cur->dirty&=~(1<<hr);
544 cur->isconst&=~(1<<hr);
550 // Try to allocate any available register
551 for(hr=0;hr<HOST_REGS;hr++) {
552 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
553 cur->regmap[hr]=reg|64;
554 cur->dirty&=~(1<<hr);
555 cur->isconst&=~(1<<hr);
560 // Ok, now we have to evict someone
561 // Pick a register we hopefully won't need soon
562 u_char hsn[MAXREG+1];
563 memset(hsn,10,sizeof(hsn));
565 lsn(hsn,i,&preferred_reg);
566 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
567 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
569 // Don't evict the cycle count at entry points, otherwise the entry
570 // stub will have to write it.
571 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
572 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
575 // Alloc preferred register if available
576 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
577 for(hr=0;hr<HOST_REGS;hr++) {
578 // Evict both parts of a 64-bit register
579 if((cur->regmap[hr]&63)==r) {
581 cur->dirty&=~(1<<hr);
582 cur->isconst&=~(1<<hr);
585 cur->regmap[preferred_reg]=reg|64;
588 for(r=1;r<=MAXREG;r++)
590 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
591 for(hr=0;hr<HOST_REGS;hr++) {
592 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
593 if(cur->regmap[hr]==r+64) {
594 cur->regmap[hr]=reg|64;
595 cur->dirty&=~(1<<hr);
596 cur->isconst&=~(1<<hr);
601 for(hr=0;hr<HOST_REGS;hr++) {
602 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
603 if(cur->regmap[hr]==r) {
604 cur->regmap[hr]=reg|64;
605 cur->dirty&=~(1<<hr);
606 cur->isconst&=~(1<<hr);
617 for(r=1;r<=MAXREG;r++)
620 for(hr=0;hr<HOST_REGS;hr++) {
621 if(cur->regmap[hr]==r+64) {
622 cur->regmap[hr]=reg|64;
623 cur->dirty&=~(1<<hr);
624 cur->isconst&=~(1<<hr);
628 for(hr=0;hr<HOST_REGS;hr++) {
629 if(cur->regmap[hr]==r) {
630 cur->regmap[hr]=reg|64;
631 cur->dirty&=~(1<<hr);
632 cur->isconst&=~(1<<hr);
639 SysPrintf("This shouldn't happen");exit(1);
642 // Allocate a temporary register. This is done without regard to
643 // dirty status or whether the register we request is on the unneeded list
644 // Note: This will only allocate one register, even if called multiple times
645 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
648 int preferred_reg = -1;
650 // see if it's already allocated
651 for(hr=0;hr<HOST_REGS;hr++)
653 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
656 // Try to allocate any available register
657 for(hr=HOST_REGS-1;hr>=0;hr--) {
658 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
660 cur->dirty&=~(1<<hr);
661 cur->isconst&=~(1<<hr);
666 // Find an unneeded register
667 for(hr=HOST_REGS-1;hr>=0;hr--)
673 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
675 cur->dirty&=~(1<<hr);
676 cur->isconst&=~(1<<hr);
683 if((cur->uu>>(r&63))&1) {
684 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
686 cur->dirty&=~(1<<hr);
687 cur->isconst&=~(1<<hr);
695 // Ok, now we have to evict someone
696 // Pick a register we hopefully won't need soon
697 // TODO: we might want to follow unconditional jumps here
698 // TODO: get rid of dupe code and make this into a function
699 u_char hsn[MAXREG+1];
700 memset(hsn,10,sizeof(hsn));
702 lsn(hsn,i,&preferred_reg);
703 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
705 // Don't evict the cycle count at entry points, otherwise the entry
706 // stub will have to write it.
707 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
708 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
711 for(r=1;r<=MAXREG;r++)
713 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
714 for(hr=0;hr<HOST_REGS;hr++) {
715 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
716 if(cur->regmap[hr]==r+64) {
718 cur->dirty&=~(1<<hr);
719 cur->isconst&=~(1<<hr);
724 for(hr=0;hr<HOST_REGS;hr++) {
725 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
726 if(cur->regmap[hr]==r) {
728 cur->dirty&=~(1<<hr);
729 cur->isconst&=~(1<<hr);
740 for(r=1;r<=MAXREG;r++)
743 for(hr=0;hr<HOST_REGS;hr++) {
744 if(cur->regmap[hr]==r+64) {
746 cur->dirty&=~(1<<hr);
747 cur->isconst&=~(1<<hr);
751 for(hr=0;hr<HOST_REGS;hr++) {
752 if(cur->regmap[hr]==r) {
754 cur->dirty&=~(1<<hr);
755 cur->isconst&=~(1<<hr);
762 SysPrintf("This shouldn't happen");exit(1);
765 // Allocate a specific ARM register.
766 static void alloc_arm_reg(struct regstat *cur,int i,signed char reg,int hr)
771 // see if it's already allocated (and dealloc it)
772 for(n=0;n<HOST_REGS;n++)
774 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
775 dirty=(cur->dirty>>n)&1;
781 cur->dirty&=~(1<<hr);
782 cur->dirty|=dirty<<hr;
783 cur->isconst&=~(1<<hr);
786 // Alloc cycle count into dedicated register
787 static void alloc_cc(struct regstat *cur,int i)
789 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
797 static unused char regname[16][4] = {
815 static void output_w32(u_int word)
817 *((u_int *)out)=word;
821 static u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
826 return((rn<<16)|(rd<<12)|rm);
829 static u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
834 assert((shift&1)==0);
835 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
838 static u_int genimm(u_int imm,u_int *encoded)
846 *encoded=((i&30)<<7)|imm;
849 imm=(imm>>2)|(imm<<30);i-=2;
854 static void genimm_checked(u_int imm,u_int *encoded)
856 u_int ret=genimm(imm,encoded);
861 static u_int genjmp(u_int addr)
863 int offset=addr-(int)out-8;
864 if(offset<-33554432||offset>=33554432) {
866 SysPrintf("genjmp: out of range: %08x\n", offset);
871 return ((u_int)offset>>2)&0xffffff;
874 static void emit_mov(int rs,int rt)
876 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
877 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
880 static void emit_movs(int rs,int rt)
882 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
883 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
886 static void emit_add(int rs1,int rs2,int rt)
888 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
889 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
892 static void emit_adds(int rs1,int rs2,int rt)
894 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
895 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
898 static void emit_adcs(int rs1,int rs2,int rt)
900 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
901 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
904 static void emit_sbc(int rs1,int rs2,int rt)
906 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
907 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
910 static void emit_sbcs(int rs1,int rs2,int rt)
912 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
913 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
916 static void emit_neg(int rs, int rt)
918 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
919 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
922 static void emit_negs(int rs, int rt)
924 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
925 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
928 static void emit_sub(int rs1,int rs2,int rt)
930 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
931 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
934 static void emit_subs(int rs1,int rs2,int rt)
936 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
937 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
940 static void emit_zeroreg(int rt)
942 assem_debug("mov %s,#0\n",regname[rt]);
943 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
946 static void emit_loadlp(u_int imm,u_int rt)
948 add_literal((int)out,imm);
949 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
950 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
953 static void emit_movw(u_int imm,u_int rt)
956 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
957 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
960 static void emit_movt(u_int imm,u_int rt)
962 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
963 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
966 static void emit_movimm(u_int imm,u_int rt)
969 if(genimm(imm,&armval)) {
970 assem_debug("mov %s,#%d\n",regname[rt],imm);
971 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
972 }else if(genimm(~imm,&armval)) {
973 assem_debug("mvn %s,#%d\n",regname[rt],imm);
974 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
975 }else if(imm<65536) {
977 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
978 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
979 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
980 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
988 emit_movw(imm&0x0000FFFF,rt);
989 emit_movt(imm&0xFFFF0000,rt);
994 static void emit_pcreladdr(u_int rt)
996 assem_debug("add %s,pc,#?\n",regname[rt]);
997 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1000 static void emit_loadreg(int r, int hr)
1003 SysPrintf("64bit load in 32bit mode!\n");
1010 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1011 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1012 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1013 if(r==CCREG) addr=(int)&cycle_count;
1014 if(r==CSREG) addr=(int)&Status;
1015 if(r==FSREG) addr=(int)&FCR31;
1016 if(r==INVCP) addr=(int)&invc_ptr;
1017 u_int offset = addr-(u_int)&dynarec_local;
1018 assert(offset<4096);
1019 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1020 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1024 static void emit_storereg(int r, int hr)
1027 SysPrintf("64bit store in 32bit mode!\n");
1031 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1032 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1033 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1034 if(r==CCREG) addr=(int)&cycle_count;
1035 if(r==FSREG) addr=(int)&FCR31;
1036 u_int offset = addr-(u_int)&dynarec_local;
1037 assert(offset<4096);
1038 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1039 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1042 static void emit_test(int rs, int rt)
1044 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1045 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1048 static void emit_testimm(int rs,int imm)
1051 assem_debug("tst %s,#%d\n",regname[rs],imm);
1052 genimm_checked(imm,&armval);
1053 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1056 static void emit_testeqimm(int rs,int imm)
1059 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1060 genimm_checked(imm,&armval);
1061 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1064 static void emit_not(int rs,int rt)
1066 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1067 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1070 static void emit_mvnmi(int rs,int rt)
1072 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1073 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1076 static void emit_and(u_int rs1,u_int rs2,u_int rt)
1078 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1079 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1082 static void emit_or(u_int rs1,u_int rs2,u_int rt)
1084 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1085 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1088 static void emit_or_and_set_flags(int rs1,int rs2,int rt)
1090 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1091 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1094 static void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1099 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1100 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1103 static void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1108 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1109 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1112 static void emit_xor(u_int rs1,u_int rs2,u_int rt)
1114 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1115 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1118 static void emit_addimm(u_int rs,int imm,u_int rt)
1124 if(genimm(imm,&armval)) {
1125 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1126 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1127 }else if(genimm(-imm,&armval)) {
1128 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-imm);
1129 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1131 }else if(rt!=rs&&(u_int)imm<65536) {
1132 emit_movw(imm&0x0000ffff,rt);
1134 }else if(rt!=rs&&(u_int)-imm<65536) {
1135 emit_movw(-imm&0x0000ffff,rt);
1138 }else if((u_int)-imm<65536) {
1139 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1140 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1141 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1142 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1145 int shift = (ffs(imm) - 1) & ~1;
1146 int imm8 = imm & (0xff << shift);
1147 genimm_checked(imm8,&armval);
1148 assem_debug("add %s,%s,#0x%x\n",regname[rt],regname[rs],imm8);
1149 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1156 else if(rs!=rt) emit_mov(rs,rt);
1159 static void emit_addimm_and_set_flags(int imm,int rt)
1161 assert(imm>-65536&&imm<65536);
1163 if(genimm(imm,&armval)) {
1164 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1165 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1166 }else if(genimm(-imm,&armval)) {
1167 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1168 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1170 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1171 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1172 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1173 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1175 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1176 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1177 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1178 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1182 static void emit_addimm_no_flags(u_int imm,u_int rt)
1184 emit_addimm(rt,imm,rt);
1187 static void emit_addnop(u_int r)
1190 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1191 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1194 static void emit_adcimm(u_int rs,int imm,u_int rt)
1197 genimm_checked(imm,&armval);
1198 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1199 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1202 static void emit_rscimm(int rs,int imm,u_int rt)
1206 genimm_checked(imm,&armval);
1207 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1208 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1211 static void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1213 // TODO: if(genimm(imm,&armval)) ...
1215 emit_movimm(imm,HOST_TEMPREG);
1216 emit_adds(HOST_TEMPREG,rsl,rtl);
1217 emit_adcimm(rsh,0,rth);
1220 static void emit_andimm(int rs,int imm,int rt)
1225 }else if(genimm(imm,&armval)) {
1226 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1227 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1228 }else if(genimm(~imm,&armval)) {
1229 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1230 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1231 }else if(imm==65535) {
1233 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1234 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1235 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1236 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1238 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1239 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1242 assert(imm>0&&imm<65535);
1244 assem_debug("mov r14,#%d\n",imm&0xFF00);
1245 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1246 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1247 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1249 emit_movw(imm,HOST_TEMPREG);
1251 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1252 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1256 static void emit_orimm(int rs,int imm,int rt)
1260 if(rs!=rt) emit_mov(rs,rt);
1261 }else if(genimm(imm,&armval)) {
1262 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1263 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1265 assert(imm>0&&imm<65536);
1266 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1267 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1268 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1269 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1273 static void emit_xorimm(int rs,int imm,int rt)
1277 if(rs!=rt) emit_mov(rs,rt);
1278 }else if(genimm(imm,&armval)) {
1279 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1280 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1282 assert(imm>0&&imm<65536);
1283 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1284 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1285 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1286 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1290 static void emit_shlimm(int rs,u_int imm,int rt)
1295 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1296 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1299 static void emit_lsls_imm(int rs,int imm,int rt)
1303 assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1304 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1307 static unused void emit_lslpls_imm(int rs,int imm,int rt)
1311 assem_debug("lslpls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1312 output_w32(0x51b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1315 static void emit_shrimm(int rs,u_int imm,int rt)
1319 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1320 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1323 static void emit_sarimm(int rs,u_int imm,int rt)
1327 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1328 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1331 static void emit_rorimm(int rs,u_int imm,int rt)
1335 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1336 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1339 static void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1341 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1345 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1346 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1347 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1348 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1351 static void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1353 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1357 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1358 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1359 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1360 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1363 static void emit_signextend16(int rs,int rt)
1366 emit_shlimm(rs,16,rt);
1367 emit_sarimm(rt,16,rt);
1369 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1370 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1374 static void emit_signextend8(int rs,int rt)
1377 emit_shlimm(rs,24,rt);
1378 emit_sarimm(rt,24,rt);
1380 assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
1381 output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
1385 static void emit_shl(u_int rs,u_int shift,u_int rt)
1391 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1392 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1395 static void emit_shr(u_int rs,u_int shift,u_int rt)
1400 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1401 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1404 static void emit_sar(u_int rs,u_int shift,u_int rt)
1409 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1410 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1413 static void emit_orrshl(u_int rs,u_int shift,u_int rt)
1418 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1419 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1422 static void emit_orrshr(u_int rs,u_int shift,u_int rt)
1427 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1428 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1431 static void emit_cmpimm(int rs,int imm)
1434 if(genimm(imm,&armval)) {
1435 assem_debug("cmp %s,#%d\n",regname[rs],imm);
1436 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1437 }else if(genimm(-imm,&armval)) {
1438 assem_debug("cmn %s,#%d\n",regname[rs],imm);
1439 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1442 emit_movimm(imm,HOST_TEMPREG);
1443 assem_debug("cmp %s,r14\n",regname[rs]);
1444 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1447 emit_movimm(-imm,HOST_TEMPREG);
1448 assem_debug("cmn %s,r14\n",regname[rs]);
1449 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1453 static void emit_cmovne_imm(int imm,int rt)
1455 assem_debug("movne %s,#%d\n",regname[rt],imm);
1457 genimm_checked(imm,&armval);
1458 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1461 static void emit_cmovl_imm(int imm,int rt)
1463 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1465 genimm_checked(imm,&armval);
1466 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1469 static void emit_cmovb_imm(int imm,int rt)
1471 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1473 genimm_checked(imm,&armval);
1474 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1477 static void emit_cmovs_imm(int imm,int rt)
1479 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1481 genimm_checked(imm,&armval);
1482 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1485 static void emit_cmove_reg(int rs,int rt)
1487 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1488 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1491 static void emit_cmovne_reg(int rs,int rt)
1493 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1494 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1497 static void emit_cmovl_reg(int rs,int rt)
1499 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1500 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1503 static void emit_cmovs_reg(int rs,int rt)
1505 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1506 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1509 static void emit_slti32(int rs,int imm,int rt)
1511 if(rs!=rt) emit_zeroreg(rt);
1512 emit_cmpimm(rs,imm);
1513 if(rs==rt) emit_movimm(0,rt);
1514 emit_cmovl_imm(1,rt);
1517 static void emit_sltiu32(int rs,int imm,int rt)
1519 if(rs!=rt) emit_zeroreg(rt);
1520 emit_cmpimm(rs,imm);
1521 if(rs==rt) emit_movimm(0,rt);
1522 emit_cmovb_imm(1,rt);
1525 static void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1528 emit_slti32(rsl,imm,rt);
1532 emit_cmovne_imm(0,rt);
1533 emit_cmovs_imm(1,rt);
1537 emit_cmpimm(rsh,-1);
1538 emit_cmovne_imm(0,rt);
1539 emit_cmovl_imm(1,rt);
1543 static void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1546 emit_sltiu32(rsl,imm,rt);
1550 emit_cmovne_imm(0,rt);
1554 emit_cmpimm(rsh,-1);
1555 emit_cmovne_imm(1,rt);
1559 static void emit_cmp(int rs,int rt)
1561 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1562 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1565 static void emit_set_gz32(int rs, int rt)
1567 //assem_debug("set_gz32\n");
1570 emit_cmovl_imm(0,rt);
1573 static void emit_set_nz32(int rs, int rt)
1575 //assem_debug("set_nz32\n");
1576 if(rs!=rt) emit_movs(rs,rt);
1577 else emit_test(rs,rs);
1578 emit_cmovne_imm(1,rt);
1581 static void emit_set_gz64_32(int rsh, int rsl, int rt)
1583 //assem_debug("set_gz64\n");
1584 emit_set_gz32(rsl,rt);
1586 emit_cmovne_imm(1,rt);
1587 emit_cmovs_imm(0,rt);
1590 static void emit_set_nz64_32(int rsh, int rsl, int rt)
1592 //assem_debug("set_nz64\n");
1593 emit_or_and_set_flags(rsh,rsl,rt);
1594 emit_cmovne_imm(1,rt);
1597 static void emit_set_if_less32(int rs1, int rs2, int rt)
1599 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1600 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1602 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1603 emit_cmovl_imm(1,rt);
1606 static void emit_set_if_carry32(int rs1, int rs2, int rt)
1608 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1609 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1611 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1612 emit_cmovb_imm(1,rt);
1615 static void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1617 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1622 emit_sbcs(u1,u2,HOST_TEMPREG);
1623 emit_cmovl_imm(1,rt);
1626 static void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1628 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1633 emit_sbcs(u1,u2,HOST_TEMPREG);
1634 emit_cmovb_imm(1,rt);
1637 static void emit_call(int a)
1639 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1640 u_int offset=genjmp(a);
1641 output_w32(0xeb000000|offset);
1644 static void emit_jmp(int a)
1646 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1647 u_int offset=genjmp(a);
1648 output_w32(0xea000000|offset);
1651 static void emit_jne(int a)
1653 assem_debug("bne %x\n",a);
1654 u_int offset=genjmp(a);
1655 output_w32(0x1a000000|offset);
1658 static void emit_jeq(int a)
1660 assem_debug("beq %x\n",a);
1661 u_int offset=genjmp(a);
1662 output_w32(0x0a000000|offset);
1665 static void emit_js(int a)
1667 assem_debug("bmi %x\n",a);
1668 u_int offset=genjmp(a);
1669 output_w32(0x4a000000|offset);
1672 static void emit_jns(int a)
1674 assem_debug("bpl %x\n",a);
1675 u_int offset=genjmp(a);
1676 output_w32(0x5a000000|offset);
1679 static void emit_jl(int a)
1681 assem_debug("blt %x\n",a);
1682 u_int offset=genjmp(a);
1683 output_w32(0xba000000|offset);
1686 static void emit_jge(int a)
1688 assem_debug("bge %x\n",a);
1689 u_int offset=genjmp(a);
1690 output_w32(0xaa000000|offset);
1693 static void emit_jno(int a)
1695 assem_debug("bvc %x\n",a);
1696 u_int offset=genjmp(a);
1697 output_w32(0x7a000000|offset);
1700 static void emit_jc(int a)
1702 assem_debug("bcs %x\n",a);
1703 u_int offset=genjmp(a);
1704 output_w32(0x2a000000|offset);
1707 static void emit_jcc(int a)
1709 assem_debug("bcc %x\n",a);
1710 u_int offset=genjmp(a);
1711 output_w32(0x3a000000|offset);
1714 static void emit_callreg(u_int r)
1717 assem_debug("blx %s\n",regname[r]);
1718 output_w32(0xe12fff30|r);
1721 static void emit_jmpreg(u_int r)
1723 assem_debug("mov pc,%s\n",regname[r]);
1724 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1727 static void emit_readword_indexed(int offset, int rs, int rt)
1729 assert(offset>-4096&&offset<4096);
1730 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1732 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1734 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1738 static void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1740 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1741 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1744 static void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
1746 assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1747 output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
1750 static void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
1752 assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1753 output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
1756 static void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
1758 assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1759 output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
1762 static void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
1764 assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1765 output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
1768 static void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
1770 assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1771 output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
1774 static void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1776 if(map<0) emit_readword_indexed(addr, rs, rt);
1779 emit_readword_dualindexedx4(rs, map, rt);
1783 static void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1786 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1787 emit_readword_indexed(addr+4, rs, rl);
1790 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1791 emit_addimm(map,1,map);
1792 emit_readword_indexed_tlb(addr, rs, map, rl);
1796 static void emit_movsbl_indexed(int offset, int rs, int rt)
1798 assert(offset>-256&&offset<256);
1799 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1801 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1803 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1807 static void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1809 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1812 emit_shlimm(map,2,map);
1813 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1814 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1816 assert(addr>-256&&addr<256);
1817 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1818 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1819 emit_movsbl_indexed(addr, rt, rt);
1824 static void emit_movswl_indexed(int offset, int rs, int rt)
1826 assert(offset>-256&&offset<256);
1827 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1829 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1831 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1835 static void emit_movzbl_indexed(int offset, int rs, int rt)
1837 assert(offset>-4096&&offset<4096);
1838 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1840 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1842 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1846 static void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1848 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1849 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1852 static void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1854 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1857 emit_movzbl_dualindexedx4(rs, map, rt);
1859 emit_addimm(rs,addr,rt);
1860 emit_movzbl_dualindexedx4(rt, map, rt);
1865 static void emit_movzwl_indexed(int offset, int rs, int rt)
1867 assert(offset>-256&&offset<256);
1868 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1870 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1872 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1876 static void emit_ldrd(int offset, int rs, int rt)
1878 assert(offset>-256&&offset<256);
1879 assem_debug("ldrd %s,%s+%d\n",regname[rt],regname[rs],offset);
1881 output_w32(0xe1c000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1883 output_w32(0xe14000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1887 static void emit_readword(int addr, int rt)
1889 u_int offset = addr-(u_int)&dynarec_local;
1890 assert(offset<4096);
1891 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1892 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1895 static unused void emit_movsbl(int addr, int rt)
1897 u_int offset = addr-(u_int)&dynarec_local;
1899 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1900 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1903 static unused void emit_movswl(int addr, int rt)
1905 u_int offset = addr-(u_int)&dynarec_local;
1907 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1908 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1911 static unused void emit_movzbl(int addr, int rt)
1913 u_int offset = addr-(u_int)&dynarec_local;
1914 assert(offset<4096);
1915 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1916 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1919 static unused void emit_movzwl(int addr, int rt)
1921 u_int offset = addr-(u_int)&dynarec_local;
1923 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1924 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1927 static void emit_writeword_indexed(int rt, int offset, int rs)
1929 assert(offset>-4096&&offset<4096);
1930 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1932 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1934 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
1938 static void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
1940 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1941 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
1944 static void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
1946 if(map<0) emit_writeword_indexed(rt, addr, rs);
1949 emit_writeword_dualindexedx4(rt, rs, map);
1953 static void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
1956 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
1957 emit_writeword_indexed(rl, addr+4, rs);
1960 if(temp!=rs) emit_addimm(map,1,temp);
1961 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
1962 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
1964 emit_addimm(rs,4,rs);
1965 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
1970 static void emit_writehword_indexed(int rt, int offset, int rs)
1972 assert(offset>-256&&offset<256);
1973 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
1975 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1977 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1981 static void emit_writebyte_indexed(int rt, int offset, int rs)
1983 assert(offset>-4096&&offset<4096);
1984 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
1986 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
1988 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
1992 static void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
1994 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1995 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1998 static void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2000 if(map<0) emit_writebyte_indexed(rt, addr, rs);
2003 emit_writebyte_dualindexedx4(rt, rs, map);
2005 emit_addimm(rs,addr,temp);
2006 emit_writebyte_dualindexedx4(rt, temp, map);
2011 static void emit_strcc_dualindexed(int rs1, int rs2, int rt)
2013 assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2014 output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
2017 static void emit_strccb_dualindexed(int rs1, int rs2, int rt)
2019 assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2020 output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
2023 static void emit_strcch_dualindexed(int rs1, int rs2, int rt)
2025 assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2026 output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
2029 static void emit_writeword(int rt, int addr)
2031 u_int offset = addr-(u_int)&dynarec_local;
2032 assert(offset<4096);
2033 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2034 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2037 static unused void emit_writehword(int rt, int addr)
2039 u_int offset = addr-(u_int)&dynarec_local;
2041 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2042 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2045 static unused void emit_writebyte(int rt, int addr)
2047 u_int offset = addr-(u_int)&dynarec_local;
2048 assert(offset<4096);
2049 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2050 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2053 static void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2055 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2060 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2063 static void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2065 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2070 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2073 static void emit_clz(int rs,int rt)
2075 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2076 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2079 static void emit_subcs(int rs1,int rs2,int rt)
2081 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2082 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2085 static void emit_shrcc_imm(int rs,u_int imm,int rt)
2089 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2090 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2093 static void emit_shrne_imm(int rs,u_int imm,int rt)
2097 assem_debug("lsrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2098 output_w32(0x11a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2101 static void emit_negmi(int rs, int rt)
2103 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2104 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2107 static void emit_negsmi(int rs, int rt)
2109 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2110 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2113 static void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2115 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2116 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2119 static void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2121 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2122 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2125 static void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2127 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2128 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2131 static void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2133 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2134 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2137 static void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2139 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2140 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2143 static void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2145 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2146 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2149 static void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2151 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2152 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2155 static void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2157 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2158 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2161 static void emit_teq(int rs, int rt)
2163 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2164 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2167 static void emit_rsbimm(int rs, int imm, int rt)
2170 genimm_checked(imm,&armval);
2171 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2172 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2175 // Load 2 immediates optimizing for small code size
2176 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2178 emit_movimm(imm1,rt1);
2180 if(genimm(imm2-imm1,&armval)) {
2181 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2182 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2183 }else if(genimm(imm1-imm2,&armval)) {
2184 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2185 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2187 else emit_movimm(imm2,rt2);
2190 // Conditionally select one of two immediates, optimizing for small code size
2191 // This will only be called if HAVE_CMOV_IMM is defined
2192 static void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2195 if(genimm(imm2-imm1,&armval)) {
2196 emit_movimm(imm1,rt);
2197 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2198 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2199 }else if(genimm(imm1-imm2,&armval)) {
2200 emit_movimm(imm1,rt);
2201 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2202 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2206 emit_movimm(imm1,rt);
2207 add_literal((int)out,imm2);
2208 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2209 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2211 emit_movw(imm1&0x0000FFFF,rt);
2212 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2213 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2214 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2216 emit_movt(imm1&0xFFFF0000,rt);
2217 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2218 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2219 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2225 // special case for checking invalid_code
2226 static void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2228 assert(imm<128&&imm>=0);
2230 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2231 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2232 emit_cmpimm(HOST_TEMPREG,imm);
2235 static void emit_callne(int a)
2237 assem_debug("blne %x\n",a);
2238 u_int offset=genjmp(a);
2239 output_w32(0x1b000000|offset);
2242 // Used to preload hash table entries
2243 static unused void emit_prefetchreg(int r)
2245 assem_debug("pld %s\n",regname[r]);
2246 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2249 // Special case for mini_ht
2250 static void emit_ldreq_indexed(int rs, u_int offset, int rt)
2252 assert(offset<4096);
2253 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2254 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2257 static unused void emit_bicne_imm(int rs,int imm,int rt)
2260 genimm_checked(imm,&armval);
2261 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2262 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2265 static unused void emit_biccs_imm(int rs,int imm,int rt)
2268 genimm_checked(imm,&armval);
2269 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2270 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2273 static unused void emit_bicvc_imm(int rs,int imm,int rt)
2276 genimm_checked(imm,&armval);
2277 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2278 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2281 static unused void emit_bichi_imm(int rs,int imm,int rt)
2284 genimm_checked(imm,&armval);
2285 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2286 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2289 static unused void emit_orrvs_imm(int rs,int imm,int rt)
2292 genimm_checked(imm,&armval);
2293 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2294 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2297 static void emit_orrne_imm(int rs,int imm,int rt)
2300 genimm_checked(imm,&armval);
2301 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2302 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2305 static void emit_andne_imm(int rs,int imm,int rt)
2308 genimm_checked(imm,&armval);
2309 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2310 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2313 static unused void emit_addpl_imm(int rs,int imm,int rt)
2316 genimm_checked(imm,&armval);
2317 assem_debug("addpl %s,%s,#%d\n",regname[rt],regname[rs],imm);
2318 output_w32(0x52800000|rd_rn_rm(rt,rs,0)|armval);
2321 static void emit_jno_unlikely(int a)
2324 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2325 output_w32(0x72800000|rd_rn_rm(15,15,0));
2328 static void save_regs_all(u_int reglist)
2331 if(!reglist) return;
2332 assem_debug("stmia fp,{");
2335 assem_debug("r%d,",i);
2337 output_w32(0xe88b0000|reglist);
2340 static void restore_regs_all(u_int reglist)
2343 if(!reglist) return;
2344 assem_debug("ldmia fp,{");
2347 assem_debug("r%d,",i);
2349 output_w32(0xe89b0000|reglist);
2352 // Save registers before function call
2353 static void save_regs(u_int reglist)
2355 reglist&=CALLER_SAVE_REGS; // only save the caller-save registers, r0-r3, r12
2356 save_regs_all(reglist);
2359 // Restore registers after function call
2360 static void restore_regs(u_int reglist)
2362 reglist&=CALLER_SAVE_REGS;
2363 restore_regs_all(reglist);
2366 /* Stubs/epilogue */
2368 static void literal_pool(int n)
2370 if(!literalcount) return;
2372 if((int)out-literals[0][0]<4096-n) return;
2376 for(i=0;i<literalcount;i++)
2378 u_int l_addr=(u_int)out;
2381 if(literals[j][1]==literals[i][1]) {
2382 //printf("dup %08x\n",literals[i][1]);
2383 l_addr=literals[j][0];
2387 ptr=(u_int *)literals[i][0];
2388 u_int offset=l_addr-(u_int)ptr-8;
2389 assert(offset<4096);
2390 assert(!(offset&3));
2392 if(l_addr==(u_int)out) {
2393 literals[i][0]=l_addr; // remember for dupes
2394 output_w32(literals[i][1]);
2400 static void literal_pool_jumpover(int n)
2402 if(!literalcount) return;
2404 if((int)out-literals[0][0]<4096-n) return;
2409 set_jump_target(jaddr,(int)out);
2412 static void emit_extjump2(u_int addr, int target, int linker)
2414 u_char *ptr=(u_char *)addr;
2415 assert((ptr[3]&0x0e)==0xa);
2418 emit_loadlp(target,0);
2419 emit_loadlp(addr,1);
2420 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2421 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2423 #ifdef DEBUG_CYCLE_COUNT
2424 emit_readword((int)&last_count,ECX);
2425 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2426 emit_readword((int)&next_interupt,ECX);
2427 emit_writeword(HOST_CCREG,(int)&Count);
2428 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2429 emit_writeword(ECX,(int)&last_count);
2435 static void emit_extjump(int addr, int target)
2437 emit_extjump2(addr, target, (int)dyna_linker);
2440 static void emit_extjump_ds(int addr, int target)
2442 emit_extjump2(addr, target, (int)dyna_linker_ds);
2445 // put rt_val into rt, potentially making use of rs with value rs_val
2446 static void emit_movimm_from(u_int rs_val,int rs,u_int rt_val,int rt)
2450 if(genimm(rt_val,&armval)) {
2451 assem_debug("mov %s,#%d\n",regname[rt],rt_val);
2452 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
2455 if(genimm(~rt_val,&armval)) {
2456 assem_debug("mvn %s,#%d\n",regname[rt],rt_val);
2457 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
2461 if(genimm(diff,&armval)) {
2462 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],diff);
2463 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
2465 }else if(genimm(-diff,&armval)) {
2466 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-diff);
2467 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
2470 emit_movimm(rt_val,rt);
2473 // return 1 if above function can do it's job cheaply
2474 static int is_similar_value(u_int v1,u_int v2)
2478 if(v1==v2) return 1;
2480 for(xs=diff;xs!=0&&(xs&3)==0;xs>>=2)
2482 if(xs<0x100) return 1;
2483 for(xs=-diff;xs!=0&&(xs&3)==0;xs>>=2)
2485 if(xs<0x100) return 1;
2490 static void pass_args(int a0, int a1)
2494 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2496 else if(a0!=0&&a1==0) {
2498 if (a0>=0) emit_mov(a0,0);
2501 if(a0>=0&&a0!=0) emit_mov(a0,0);
2502 if(a1>=0&&a1!=1) emit_mov(a1,1);
2506 static void mov_loadtype_adj(int type,int rs,int rt)
2509 case LOADB_STUB: emit_signextend8(rs,rt); break;
2510 case LOADBU_STUB: emit_andimm(rs,0xff,rt); break;
2511 case LOADH_STUB: emit_signextend16(rs,rt); break;
2512 case LOADHU_STUB: emit_andimm(rs,0xffff,rt); break;
2513 case LOADW_STUB: if(rs!=rt) emit_mov(rs,rt); break;
2518 #include "pcsxmem.h"
2519 #include "pcsxmem_inline.c"
2521 static void do_readstub(int n)
2523 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2525 set_jump_target(stubs[n][1],(int)out);
2526 int type=stubs[n][0];
2529 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2530 u_int reglist=stubs[n][7];
2531 signed char *i_regmap=i_regs->regmap;
2533 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2534 rt=get_reg(i_regmap,FTEMP);
2536 rt=get_reg(i_regmap,rt1[i]);
2539 int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
2541 for(r=0;r<=12;r++) {
2542 if(((1<<r)&0x13ff)&&((1<<r)®list)==0) {
2546 if(rt>=0&&rt1[i]!=0)
2553 if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
2555 emit_readword((int)&mem_rtab,temp);
2556 emit_shrimm(rs,12,temp2);
2557 emit_readword_dualindexedx4(temp,temp2,temp2);
2558 emit_lsls_imm(temp2,1,temp2);
2559 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2561 case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
2562 case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
2563 case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
2564 case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
2565 case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
2569 restore_jump=(int)out;
2570 emit_jcc(0); // jump to reg restore
2573 emit_jcc(stubs[n][2]); // return address
2578 if(type==LOADB_STUB||type==LOADBU_STUB)
2579 handler=(int)jump_handler_read8;
2580 if(type==LOADH_STUB||type==LOADHU_STUB)
2581 handler=(int)jump_handler_read16;
2582 if(type==LOADW_STUB)
2583 handler=(int)jump_handler_read32;
2585 pass_args(rs,temp2);
2586 int cc=get_reg(i_regmap,CCREG);
2588 emit_loadreg(CCREG,2);
2589 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2591 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2592 mov_loadtype_adj(type,0,rt);
2595 set_jump_target(restore_jump,(int)out);
2596 restore_regs(reglist);
2597 emit_jmp(stubs[n][2]); // return address
2600 // return memhandler, or get directly accessable address and return 0
2601 static u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
2604 l1=((u_int *)table)[addr>>12];
2605 if((l1&(1<<31))==0) {
2612 if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
2613 l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2614 else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
2615 l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
2617 l2=((u_int *)l1)[(addr&0xfff)/4];
2618 if((l2&(1<<31))==0) {
2620 *addr_host=v+(addr&0xfff);
2627 static void inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2629 int rs=get_reg(regmap,target);
2630 int rt=get_reg(regmap,target);
2631 if(rs<0) rs=get_reg(regmap,-1);
2633 u_int handler,host_addr=0,is_dynamic,far_call=0;
2634 int cc=get_reg(regmap,CCREG);
2635 if(pcsx_direct_read(type,addr,CLOCK_ADJUST(adj+1),cc,target?rs:-1,rt))
2637 handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
2642 emit_movimm_from(addr,rs,host_addr,rs);
2644 case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
2645 case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
2646 case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
2647 case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
2648 case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
2653 is_dynamic=pcsxmem_is_handler_dynamic(addr);
2655 if(type==LOADB_STUB||type==LOADBU_STUB)
2656 handler=(int)jump_handler_read8;
2657 if(type==LOADH_STUB||type==LOADHU_STUB)
2658 handler=(int)jump_handler_read16;
2659 if(type==LOADW_STUB)
2660 handler=(int)jump_handler_read32;
2663 // call a memhandler
2664 if(rt>=0&&rt1[i]!=0)
2668 emit_movimm(addr,0);
2671 int offset=(int)handler-(int)out-8;
2672 if(offset<-33554432||offset>=33554432) {
2673 // unreachable memhandler, a plugin func perhaps
2674 emit_movimm(handler,12);
2678 emit_loadreg(CCREG,2);
2680 emit_movimm(((u_int *)mem_rtab)[addr>>12]<<1,1);
2681 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2684 emit_readword((int)&last_count,3);
2685 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2687 emit_writeword(2,(int)&Count);
2695 if(rt>=0&&rt1[i]!=0) {
2697 case LOADB_STUB: emit_signextend8(0,rt); break;
2698 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2699 case LOADH_STUB: emit_signextend16(0,rt); break;
2700 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2701 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2705 restore_regs(reglist);
2708 static void do_writestub(int n)
2710 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2712 set_jump_target(stubs[n][1],(int)out);
2713 int type=stubs[n][0];
2716 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2717 u_int reglist=stubs[n][7];
2718 signed char *i_regmap=i_regs->regmap;
2720 if(itype[i]==C1LS||itype[i]==C2LS) {
2721 rt=get_reg(i_regmap,r=FTEMP);
2723 rt=get_reg(i_regmap,r=rs2[i]);
2727 int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
2728 int reglist2=reglist|(1<<rs)|(1<<rt);
2729 for(rtmp=0;rtmp<=12;rtmp++) {
2730 if(((1<<rtmp)&0x13ff)&&((1<<rtmp)®list2)==0) {
2737 for(rtmp=0;rtmp<=3;rtmp++)
2738 if(rtmp!=rs&&rtmp!=rt)
2741 if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
2743 emit_readword((int)&mem_wtab,temp);
2744 emit_shrimm(rs,12,temp2);
2745 emit_readword_dualindexedx4(temp,temp2,temp2);
2746 emit_lsls_imm(temp2,1,temp2);
2748 case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
2749 case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
2750 case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
2754 restore_jump=(int)out;
2755 emit_jcc(0); // jump to reg restore
2758 emit_jcc(stubs[n][2]); // return address (invcode check)
2764 case STOREB_STUB: handler=(int)jump_handler_write8; break;
2765 case STOREH_STUB: handler=(int)jump_handler_write16; break;
2766 case STOREW_STUB: handler=(int)jump_handler_write32; break;
2772 int cc=get_reg(i_regmap,CCREG);
2774 emit_loadreg(CCREG,2);
2775 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2776 // returns new cycle_count
2778 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
2780 emit_storereg(CCREG,2);
2782 set_jump_target(restore_jump,(int)out);
2783 restore_regs(reglist);
2788 static void inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2790 int rs=get_reg(regmap,-1);
2791 int rt=get_reg(regmap,target);
2794 u_int handler,host_addr=0;
2795 handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
2798 emit_movimm_from(addr,rs,host_addr,rs);
2800 case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
2801 case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
2802 case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
2808 // call a memhandler
2811 int cc=get_reg(regmap,CCREG);
2813 emit_loadreg(CCREG,2);
2814 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2815 emit_movimm(handler,3);
2816 // returns new cycle_count
2817 emit_call((int)jump_handler_write_h);
2818 emit_addimm(0,-CLOCK_ADJUST(adj+1),cc<0?2:cc);
2820 emit_storereg(CCREG,2);
2821 restore_regs(reglist);
2824 static void do_unalignedwritestub(int n)
2826 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
2828 set_jump_target(stubs[n][1],(int)out);
2831 struct regstat *i_regs=(struct regstat *)stubs[n][4];
2832 int addr=stubs[n][5];
2833 u_int reglist=stubs[n][7];
2834 signed char *i_regmap=i_regs->regmap;
2835 int temp2=get_reg(i_regmap,FTEMP);
2837 rt=get_reg(i_regmap,rs2[i]);
2840 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
2842 reglist&=~(1<<temp2);
2845 // don't bother with it and call write handler
2848 int cc=get_reg(i_regmap,CCREG);
2850 emit_loadreg(CCREG,2);
2851 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2852 emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
2853 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
2855 emit_storereg(CCREG,2);
2856 restore_regs(reglist);
2857 emit_jmp(stubs[n][2]); // return address
2859 emit_andimm(addr,0xfffffffc,temp2);
2860 emit_writeword(temp2,(int)&address);
2863 emit_shrimm(addr,16,1);
2864 int cc=get_reg(i_regmap,CCREG);
2866 emit_loadreg(CCREG,2);
2868 emit_movimm((u_int)readmem,0);
2869 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2870 emit_call((int)&indirect_jump_indexed);
2871 restore_regs(reglist);
2873 emit_readword((int)&readmem_dword,temp2);
2874 int temp=addr; //hmh
2875 emit_shlimm(addr,3,temp);
2876 emit_andimm(temp,24,temp);
2877 #ifdef BIG_ENDIAN_MIPS
2878 if (opcode[i]==0x2e) // SWR
2880 if (opcode[i]==0x2a) // SWL
2882 emit_xorimm(temp,24,temp);
2883 emit_movimm(-1,HOST_TEMPREG);
2884 if (opcode[i]==0x2a) { // SWL
2885 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
2886 emit_orrshr(rt,temp,temp2);
2888 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
2889 emit_orrshl(rt,temp,temp2);
2891 emit_readword((int)&address,addr);
2892 emit_writeword(temp2,(int)&word);
2893 //save_regs(reglist); // don't need to, no state changes
2894 emit_shrimm(addr,16,1);
2895 emit_movimm((u_int)writemem,0);
2896 //emit_call((int)&indirect_jump_indexed);
2898 emit_readword_dualindexedx4(0,1,15);
2899 emit_readword((int)&Count,HOST_TEMPREG);
2900 emit_readword((int)&next_interupt,2);
2901 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2902 emit_writeword(2,(int)&last_count);
2903 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2905 emit_storereg(CCREG,HOST_TEMPREG);
2907 restore_regs(reglist);
2908 emit_jmp(stubs[n][2]); // return address
2912 static void do_invstub(int n)
2915 u_int reglist=stubs[n][3];
2916 set_jump_target(stubs[n][1],(int)out);
2918 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
2919 emit_call((int)&invalidate_addr);
2920 restore_regs(reglist);
2921 emit_jmp(stubs[n][2]); // return address
2924 int do_dirty_stub(int i)
2926 assem_debug("do_dirty_stub %x\n",start+i*4);
2927 u_int addr=(u_int)source;
2928 // Careful about the code output here, verify_dirty needs to parse it.
2930 emit_loadlp(addr,1);
2931 emit_loadlp((int)copy,2);
2932 emit_loadlp(slen*4,3);
2934 emit_movw(addr&0x0000FFFF,1);
2935 emit_movw(((u_int)copy)&0x0000FFFF,2);
2936 emit_movt(addr&0xFFFF0000,1);
2937 emit_movt(((u_int)copy)&0xFFFF0000,2);
2938 emit_movw(slen*4,3);
2940 emit_movimm(start+i*4,0);
2941 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
2944 if(entry==(int)out) entry=instr_addr[i];
2945 emit_jmp(instr_addr[i]);
2949 static void do_dirty_stub_ds()
2951 // Careful about the code output here, verify_dirty needs to parse it.
2953 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
2954 emit_loadlp((int)copy,2);
2955 emit_loadlp(slen*4,3);
2957 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
2958 emit_movw(((u_int)copy)&0x0000FFFF,2);
2959 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
2960 emit_movt(((u_int)copy)&0xFFFF0000,2);
2961 emit_movw(slen*4,3);
2963 emit_movimm(start+1,0);
2964 emit_call((int)&verify_code_ds);
2967 static void do_cop1stub(int n)
2970 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
2971 set_jump_target(stubs[n][1],(int)out);
2973 // int rs=stubs[n][4];
2974 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2977 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2978 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
2980 //else {printf("fp exception in delay slot\n");}
2981 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
2982 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
2983 emit_movimm(start+(i-ds)*4,EAX); // Get PC
2984 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
2985 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
2990 static void shift_assemble_arm(int i,struct regstat *i_regs)
2993 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
2995 signed char s,t,shift;
2996 t=get_reg(i_regs->regmap,rt1[i]);
2997 s=get_reg(i_regs->regmap,rs1[i]);
2998 shift=get_reg(i_regs->regmap,rs2[i]);
3007 if(s!=t) emit_mov(s,t);
3011 emit_andimm(shift,31,HOST_TEMPREG);
3012 if(opcode2[i]==4) // SLLV
3014 emit_shl(s,HOST_TEMPREG,t);
3016 if(opcode2[i]==6) // SRLV
3018 emit_shr(s,HOST_TEMPREG,t);
3020 if(opcode2[i]==7) // SRAV
3022 emit_sar(s,HOST_TEMPREG,t);
3026 } else { // DSLLV/DSRLV/DSRAV
3027 signed char sh,sl,th,tl,shift;
3028 th=get_reg(i_regs->regmap,rt1[i]|64);
3029 tl=get_reg(i_regs->regmap,rt1[i]);
3030 sh=get_reg(i_regs->regmap,rs1[i]|64);
3031 sl=get_reg(i_regs->regmap,rs1[i]);
3032 shift=get_reg(i_regs->regmap,rs2[i]);
3037 if(th>=0) emit_zeroreg(th);
3042 if(sl!=tl) emit_mov(sl,tl);
3043 if(th>=0&&sh!=th) emit_mov(sh,th);
3047 // FIXME: What if shift==tl ?
3049 int temp=get_reg(i_regs->regmap,-1);
3051 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3054 emit_andimm(shift,31,HOST_TEMPREG);
3055 if(opcode2[i]==0x14) // DSLLV
3057 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3058 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3059 emit_orrshr(sl,HOST_TEMPREG,th);
3060 emit_andimm(shift,31,HOST_TEMPREG);
3061 emit_testimm(shift,32);
3062 emit_shl(sl,HOST_TEMPREG,tl);
3063 if(th>=0) emit_cmovne_reg(tl,th);
3064 emit_cmovne_imm(0,tl);
3066 if(opcode2[i]==0x16) // DSRLV
3069 emit_shr(sl,HOST_TEMPREG,tl);
3070 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3071 emit_orrshl(sh,HOST_TEMPREG,tl);
3072 emit_andimm(shift,31,HOST_TEMPREG);
3073 emit_testimm(shift,32);
3074 emit_shr(sh,HOST_TEMPREG,th);
3075 emit_cmovne_reg(th,tl);
3076 if(real_th>=0) emit_cmovne_imm(0,th);
3078 if(opcode2[i]==0x17) // DSRAV
3081 emit_shr(sl,HOST_TEMPREG,tl);
3082 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3085 emit_sarimm(th,31,temp);
3087 emit_orrshl(sh,HOST_TEMPREG,tl);
3088 emit_andimm(shift,31,HOST_TEMPREG);
3089 emit_testimm(shift,32);
3090 emit_sar(sh,HOST_TEMPREG,th);
3091 emit_cmovne_reg(th,tl);
3092 if(real_th>=0) emit_cmovne_reg(temp,th);
3100 static void speculate_mov(int rs,int rt)
3103 smrv_strong_next|=1<<rt;
3108 static void speculate_mov_weak(int rs,int rt)
3111 smrv_weak_next|=1<<rt;
3116 static void speculate_register_values(int i)
3119 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3120 // gp,sp are likely to stay the same throughout the block
3121 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3122 smrv_weak_next=~smrv_strong_next;
3123 //printf(" llr %08x\n", smrv[4]);
3125 smrv_strong=smrv_strong_next;
3126 smrv_weak=smrv_weak_next;
3129 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3130 else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
3131 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3132 else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
3134 smrv_strong_next&=~(1<<rt1[i]);
3135 smrv_weak_next&=~(1<<rt1[i]);
3139 smrv_strong_next&=~(1<<rt1[i]);
3140 smrv_weak_next&=~(1<<rt1[i]);
3143 if(rt1[i]&&is_const(®s[i],rt1[i])) {
3144 int value,hr=get_reg(regs[i].regmap,rt1[i]);
3146 if(get_final_value(hr,i,&value))
3148 else smrv[rt1[i]]=constmap[i][hr];
3149 smrv_strong_next|=1<<rt1[i];
3153 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3154 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3158 if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
3159 // special case for BIOS
3160 smrv[rt1[i]]=0xa0000000;
3161 smrv_strong_next|=1<<rt1[i];
3168 smrv_strong_next&=~(1<<rt1[i]);
3169 smrv_weak_next&=~(1<<rt1[i]);
3173 if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
3174 smrv_strong_next&=~(1<<rt1[i]);
3175 smrv_weak_next&=~(1<<rt1[i]);
3179 if (opcode[i]==0x32) { // LWC2
3180 smrv_strong_next&=~(1<<rt1[i]);
3181 smrv_weak_next&=~(1<<rt1[i]);
3187 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
3188 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
3200 static int get_ptr_mem_type(u_int a)
3202 if(a < 0x00200000) {
3203 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
3204 // return wrong, must use memhandler for BIOS self-test to pass
3205 // 007 does similar stuff from a00 mirror, weird stuff
3209 if(0x1f800000 <= a && a < 0x1f801000)
3211 if(0x80200000 <= a && a < 0x80800000)
3213 if(0xa0000000 <= a && a < 0xa0200000)
3218 static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
3222 if(((smrv_strong|smrv_weak)>>mr)&1) {
3223 type=get_ptr_mem_type(smrv[mr]);
3224 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
3227 // use the mirror we are running on
3228 type=get_ptr_mem_type(start);
3229 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
3232 if(type==MTYPE_8020) { // RAM 80200000+ mirror
3233 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3234 addr=*addr_reg_override=HOST_TEMPREG;
3237 else if(type==MTYPE_0000) { // RAM 0 mirror
3238 emit_orimm(addr,0x80000000,HOST_TEMPREG);
3239 addr=*addr_reg_override=HOST_TEMPREG;
3242 else if(type==MTYPE_A000) { // RAM A mirror
3243 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
3244 addr=*addr_reg_override=HOST_TEMPREG;
3247 else if(type==MTYPE_1F80) { // scratchpad
3248 if (psxH == (void *)0x1f800000) {
3249 emit_addimm(addr,-0x1f800000,HOST_TEMPREG);
3250 emit_cmpimm(HOST_TEMPREG,0x1000);
3255 // do usual RAM check, jump will go to the right handler
3262 emit_cmpimm(addr,RAM_SIZE);
3264 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3265 // Hint to branch predictor that the branch is unlikely to be taken
3267 emit_jno_unlikely(0);
3272 emit_addimm(addr,ram_offset,HOST_TEMPREG);
3273 addr=*addr_reg_override=HOST_TEMPREG;
3280 #define shift_assemble shift_assemble_arm
3282 static void loadlr_assemble_arm(int i,struct regstat *i_regs)
3284 int s,th,tl,temp,temp2,addr,map=-1;
3287 int memtarget=0,c=0;
3288 int fastload_reg_override=0;
3290 th=get_reg(i_regs->regmap,rt1[i]|64);
3291 tl=get_reg(i_regs->regmap,rt1[i]);
3292 s=get_reg(i_regs->regmap,rs1[i]);
3293 temp=get_reg(i_regs->regmap,-1);
3294 temp2=get_reg(i_regs->regmap,FTEMP);
3295 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3298 for(hr=0;hr<HOST_REGS;hr++) {
3299 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3302 if(offset||s<0||c) addr=temp2;
3305 c=(i_regs->wasconst>>s)&1;
3307 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3312 map=get_reg(i_regs->regmap,ROREG);
3313 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3315 emit_shlimm(addr,3,temp);
3316 if (opcode[i]==0x22||opcode[i]==0x26) {
3317 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3319 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3321 jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override);
3324 if(ram_offset&&memtarget) {
3325 emit_addimm(temp2,ram_offset,HOST_TEMPREG);
3326 fastload_reg_override=HOST_TEMPREG;
3328 if (opcode[i]==0x22||opcode[i]==0x26) {
3329 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3331 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3334 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3337 if(fastload_reg_override) a=fastload_reg_override;
3338 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3339 emit_readword_indexed_tlb(0,a,map,temp2);
3340 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3343 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3346 emit_andimm(temp,24,temp);
3347 #ifdef BIG_ENDIAN_MIPS
3348 if (opcode[i]==0x26) // LWR
3350 if (opcode[i]==0x22) // LWL
3352 emit_xorimm(temp,24,temp);
3353 emit_movimm(-1,HOST_TEMPREG);
3354 if (opcode[i]==0x26) {
3355 emit_shr(temp2,temp,temp2);
3356 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3358 emit_shl(temp2,temp,temp2);
3359 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3361 emit_or(temp2,tl,tl);
3363 //emit_storereg(rt1[i],tl); // DEBUG
3365 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3366 // FIXME: little endian, fastload_reg_override
3367 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3369 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3370 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3371 emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2);
3372 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3375 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3379 emit_testimm(temp,32);
3380 emit_andimm(temp,24,temp);
3381 if (opcode[i]==0x1A) { // LDL
3382 emit_rsbimm(temp,32,HOST_TEMPREG);
3383 emit_shl(temp2h,temp,temp2h);
3384 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3385 emit_movimm(-1,HOST_TEMPREG);
3386 emit_shl(temp2,temp,temp2);
3387 emit_cmove_reg(temp2h,th);
3388 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3389 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3390 emit_orreq(temp2,tl,tl);
3391 emit_orrne(temp2,th,th);
3393 if (opcode[i]==0x1B) { // LDR
3394 emit_xorimm(temp,24,temp);
3395 emit_rsbimm(temp,32,HOST_TEMPREG);
3396 emit_shr(temp2,temp,temp2);
3397 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3398 emit_movimm(-1,HOST_TEMPREG);
3399 emit_shr(temp2h,temp,temp2h);
3400 emit_cmovne_reg(temp2,tl);
3401 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3402 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3403 emit_orrne(temp2h,th,th);
3404 emit_orreq(temp2h,tl,tl);
3409 #define loadlr_assemble loadlr_assemble_arm
3411 static void cop0_assemble(int i,struct regstat *i_regs)
3413 if(opcode2[i]==0) // MFC0
3415 signed char t=get_reg(i_regs->regmap,rt1[i]);
3416 char copr=(source[i]>>11)&0x1f;
3417 //assert(t>=0); // Why does this happen? OOT is weird
3418 if(t>=0&&rt1[i]!=0) {
3419 emit_readword((int)®_cop0+copr*4,t);
3422 else if(opcode2[i]==4) // MTC0
3424 signed char s=get_reg(i_regs->regmap,rs1[i]);
3425 char copr=(source[i]>>11)&0x1f;
3427 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3428 if(copr==9||copr==11||copr==12||copr==13) {
3429 emit_readword((int)&last_count,HOST_TEMPREG);
3430 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3431 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3432 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3433 emit_writeword(HOST_CCREG,(int)&Count);
3435 // What a mess. The status register (12) can enable interrupts,
3436 // so needs a special case to handle a pending interrupt.
3437 // The interrupt must be taken immediately, because a subsequent
3438 // instruction might disable interrupts again.
3439 if(copr==12||copr==13) {
3441 // burn cycles to cause cc_interrupt, which will
3442 // reschedule next_interupt. Relies on CCREG from above.
3443 assem_debug("MTC0 DS %d\n", copr);
3444 emit_writeword(HOST_CCREG,(int)&last_count);
3445 emit_movimm(0,HOST_CCREG);
3446 emit_storereg(CCREG,HOST_CCREG);
3447 emit_loadreg(rs1[i],1);
3448 emit_movimm(copr,0);
3449 emit_call((int)pcsx_mtc0_ds);
3450 emit_loadreg(rs1[i],s);
3453 emit_movimm(start+i*4+4,HOST_TEMPREG);
3454 emit_writeword(HOST_TEMPREG,(int)&pcaddr);
3455 emit_movimm(0,HOST_TEMPREG);
3456 emit_writeword(HOST_TEMPREG,(int)&pending_exception);
3458 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3461 emit_loadreg(rs1[i],1);
3464 emit_movimm(copr,0);
3465 emit_call((int)pcsx_mtc0);
3466 if(copr==9||copr==11||copr==12||copr==13) {
3467 emit_readword((int)&Count,HOST_CCREG);
3468 emit_readword((int)&next_interupt,HOST_TEMPREG);
3469 emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3470 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3471 emit_writeword(HOST_TEMPREG,(int)&last_count);
3472 emit_storereg(CCREG,HOST_CCREG);
3474 if(copr==12||copr==13) {
3475 assert(!is_delayslot);
3476 emit_readword((int)&pending_exception,14);
3478 emit_jne((int)&do_interrupt);
3480 emit_loadreg(rs1[i],s);
3481 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3482 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3487 assert(opcode2[i]==0x10);
3488 if((source[i]&0x3f)==0x10) // RFE
3490 emit_readword((int)&Status,0);
3491 emit_andimm(0,0x3c,1);
3492 emit_andimm(0,~0xf,0);
3493 emit_orrshr_imm(1,2,0);
3494 emit_writeword(0,(int)&Status);
3499 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3509 emit_readword((int)®_cop2d[copr],tl);
3510 emit_signextend16(tl,tl);
3511 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3518 emit_readword((int)®_cop2d[copr],tl);
3519 emit_andimm(tl,0xffff,tl);
3520 emit_writeword(tl,(int)®_cop2d[copr]);
3523 emit_readword((int)®_cop2d[14],tl); // SXY2
3524 emit_writeword(tl,(int)®_cop2d[copr]);
3528 emit_readword((int)®_cop2d[9],temp);
3529 emit_testimm(temp,0x8000); // do we need this?
3530 emit_andimm(temp,0xf80,temp);
3531 emit_andne_imm(temp,0,temp);
3532 emit_shrimm(temp,7,tl);
3533 emit_readword((int)®_cop2d[10],temp);
3534 emit_testimm(temp,0x8000);
3535 emit_andimm(temp,0xf80,temp);
3536 emit_andne_imm(temp,0,temp);
3537 emit_orrshr_imm(temp,2,tl);
3538 emit_readword((int)®_cop2d[11],temp);
3539 emit_testimm(temp,0x8000);
3540 emit_andimm(temp,0xf80,temp);
3541 emit_andne_imm(temp,0,temp);
3542 emit_orrshl_imm(temp,3,tl);
3543 emit_writeword(tl,(int)®_cop2d[copr]);
3546 emit_readword((int)®_cop2d[copr],tl);
3551 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3555 emit_readword((int)®_cop2d[13],temp); // SXY1
3556 emit_writeword(sl,(int)®_cop2d[copr]);
3557 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3558 emit_readword((int)®_cop2d[14],temp); // SXY2
3559 emit_writeword(sl,(int)®_cop2d[14]);
3560 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3563 emit_andimm(sl,0x001f,temp);
3564 emit_shlimm(temp,7,temp);
3565 emit_writeword(temp,(int)®_cop2d[9]);
3566 emit_andimm(sl,0x03e0,temp);
3567 emit_shlimm(temp,2,temp);
3568 emit_writeword(temp,(int)®_cop2d[10]);
3569 emit_andimm(sl,0x7c00,temp);
3570 emit_shrimm(temp,3,temp);
3571 emit_writeword(temp,(int)®_cop2d[11]);
3572 emit_writeword(sl,(int)®_cop2d[28]);
3576 emit_mvnmi(temp,temp);
3578 emit_clz(temp,temp);
3580 emit_movs(temp,HOST_TEMPREG);
3581 emit_movimm(0,temp);
3582 emit_jeq((int)out+4*4);
3583 emit_addpl_imm(temp,1,temp);
3584 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3585 emit_jns((int)out-2*4);
3587 emit_writeword(sl,(int)®_cop2d[30]);
3588 emit_writeword(temp,(int)®_cop2d[31]);
3593 emit_writeword(sl,(int)®_cop2d[copr]);
3598 static void cop2_assemble(int i,struct regstat *i_regs)
3600 u_int copr=(source[i]>>11)&0x1f;
3601 signed char temp=get_reg(i_regs->regmap,-1);
3602 if (opcode2[i]==0) { // MFC2
3603 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3604 if(tl>=0&&rt1[i]!=0)
3605 cop2_get_dreg(copr,tl,temp);
3607 else if (opcode2[i]==4) { // MTC2
3608 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3609 cop2_put_dreg(copr,sl,temp);
3611 else if (opcode2[i]==2) // CFC2
3613 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3614 if(tl>=0&&rt1[i]!=0)
3615 emit_readword((int)®_cop2c[copr],tl);
3617 else if (opcode2[i]==6) // CTC2
3619 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3628 emit_signextend16(sl,temp);
3631 //value = value & 0x7ffff000;
3632 //if (value & 0x7f87e000) value |= 0x80000000;
3633 emit_shrimm(sl,12,temp);
3634 emit_shlimm(temp,12,temp);
3635 emit_testimm(temp,0x7f000000);
3636 emit_testeqimm(temp,0x00870000);
3637 emit_testeqimm(temp,0x0000e000);
3638 emit_orrne_imm(temp,0x80000000,temp);
3644 emit_writeword(temp,(int)®_cop2c[copr]);
3649 static void c2op_prologue(u_int op,u_int reglist)
3651 save_regs_all(reglist);
3654 emit_call((int)pcnt_gte_start);
3656 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs
3659 static void c2op_epilogue(u_int op,u_int reglist)
3663 emit_call((int)pcnt_gte_end);
3665 restore_regs_all(reglist);
3668 static void c2op_call_MACtoIR(int lm,int need_flags)
3671 emit_call((int)(lm?gteMACtoIR_lm1:gteMACtoIR_lm0));
3673 emit_call((int)(lm?gteMACtoIR_lm1_nf:gteMACtoIR_lm0_nf));
3676 static void c2op_call_rgb_func(void *func,int lm,int need_ir,int need_flags)
3678 emit_call((int)func);
3679 // func is C code and trashes r0
3680 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3681 if(need_flags||need_ir)
3682 c2op_call_MACtoIR(lm,need_flags);
3683 emit_call((int)(need_flags?gteMACtoRGB:gteMACtoRGB_nf));
3686 static void c2op_assemble(int i,struct regstat *i_regs)
3688 u_int c2op=source[i]&0x3f;
3689 u_int hr,reglist_full=0,reglist;
3690 int need_flags,need_ir;
3691 for(hr=0;hr<HOST_REGS;hr++) {
3692 if(i_regs->regmap[hr]>=0) reglist_full|=1<<hr;
3694 reglist=reglist_full&CALLER_SAVE_REGS;
3696 if (gte_handlers[c2op]!=NULL) {
3697 need_flags=!(gte_unneeded[i+1]>>63); // +1 because of how liveness detection works
3698 need_ir=(gte_unneeded[i+1]&0xe00)!=0xe00;
3699 assem_debug("gte op %08x, unneeded %016llx, need_flags %d, need_ir %d\n",
3700 source[i],gte_unneeded[i+1],need_flags,need_ir);
3701 if(new_dynarec_hacks&NDHACK_GTE_NO_FLAGS)
3703 int shift = (source[i] >> 19) & 1;
3704 int lm = (source[i] >> 10) & 1;
3709 int v = (source[i] >> 15) & 3;
3710 int cv = (source[i] >> 13) & 3;
3711 int mx = (source[i] >> 17) & 3;
3712 reglist=reglist_full&(CALLER_SAVE_REGS|0xf0); // +{r4-r7}
3713 c2op_prologue(c2op,reglist);
3714 /* r4,r5 = VXYZ(v) packed; r6 = &MX11(mx); r7 = &CV1(cv) */
3718 emit_movzwl_indexed(9*4,0,4); // gteIR
3719 emit_movzwl_indexed(10*4,0,6);
3720 emit_movzwl_indexed(11*4,0,5);
3721 emit_orrshl_imm(6,16,4);
3724 emit_addimm(0,32*4+mx*8*4,6);
3726 emit_readword((int)&zeromem_ptr,6);
3728 emit_addimm(0,32*4+(cv*8+5)*4,7);
3730 emit_readword((int)&zeromem_ptr,7);
3732 emit_movimm(source[i],1); // opcode
3733 emit_call((int)gteMVMVA_part_neon);
3736 emit_call((int)gteMACtoIR_flags_neon);
3740 emit_call((int)gteMVMVA_part_cv3sh12_arm);
3742 emit_movimm(shift,1);
3743 emit_call((int)(need_flags?gteMVMVA_part_arm:gteMVMVA_part_nf_arm));
3745 if(need_flags||need_ir)
3746 c2op_call_MACtoIR(lm,need_flags);
3748 #else /* if not HAVE_ARMV5 */
3749 c2op_prologue(c2op,reglist);
3750 emit_movimm(source[i],1); // opcode
3751 emit_writeword(1,(int)&psxRegs.code);
3752 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
3757 c2op_prologue(c2op,reglist);
3758 emit_call((int)(shift?gteOP_part_shift:gteOP_part_noshift));
3759 if(need_flags||need_ir) {
3760 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3761 c2op_call_MACtoIR(lm,need_flags);
3765 c2op_prologue(c2op,reglist);
3766 c2op_call_rgb_func(shift?gteDPCS_part_shift:gteDPCS_part_noshift,lm,need_ir,need_flags);
3769 c2op_prologue(c2op,reglist);
3770 c2op_call_rgb_func(shift?gteINTPL_part_shift:gteINTPL_part_noshift,lm,need_ir,need_flags);
3773 c2op_prologue(c2op,reglist);
3774 emit_call((int)(shift?gteSQR_part_shift:gteSQR_part_noshift));
3775 if(need_flags||need_ir) {
3776 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3777 c2op_call_MACtoIR(lm,need_flags);
3781 c2op_prologue(c2op,reglist);
3782 c2op_call_rgb_func(gteDCPL_part,lm,need_ir,need_flags);
3785 c2op_prologue(c2op,reglist);
3786 c2op_call_rgb_func(shift?gteGPF_part_shift:gteGPF_part_noshift,lm,need_ir,need_flags);
3789 c2op_prologue(c2op,reglist);
3790 c2op_call_rgb_func(shift?gteGPL_part_shift:gteGPL_part_noshift,lm,need_ir,need_flags);
3794 c2op_prologue(c2op,reglist);
3796 emit_movimm(source[i],1); // opcode
3797 emit_writeword(1,(int)&psxRegs.code);
3799 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
3802 c2op_epilogue(c2op,reglist);
3806 static void cop1_unusable(int i,struct regstat *i_regs)
3808 // XXX: should just just do the exception instead
3812 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3817 static void cop1_assemble(int i,struct regstat *i_regs)
3819 cop1_unusable(i, i_regs);
3822 static void fconv_assemble_arm(int i,struct regstat *i_regs)
3824 cop1_unusable(i, i_regs);
3826 #define fconv_assemble fconv_assemble_arm
3828 static void fcomp_assemble(int i,struct regstat *i_regs)
3830 cop1_unusable(i, i_regs);
3833 static void float_assemble(int i,struct regstat *i_regs)
3835 cop1_unusable(i, i_regs);
3838 static void multdiv_assemble_arm(int i,struct regstat *i_regs)
3845 // case 0x1D: DMULTU
3850 if((opcode2[i]&4)==0) // 32-bit
3852 if(opcode2[i]==0x18) // MULT
3854 signed char m1=get_reg(i_regs->regmap,rs1[i]);
3855 signed char m2=get_reg(i_regs->regmap,rs2[i]);
3856 signed char hi=get_reg(i_regs->regmap,HIREG);
3857 signed char lo=get_reg(i_regs->regmap,LOREG);
3862 emit_smull(m1,m2,hi,lo);
3864 if(opcode2[i]==0x19) // MULTU
3866 signed char m1=get_reg(i_regs->regmap,rs1[i]);
3867 signed char m2=get_reg(i_regs->regmap,rs2[i]);
3868 signed char hi=get_reg(i_regs->regmap,HIREG);
3869 signed char lo=get_reg(i_regs->regmap,LOREG);
3874 emit_umull(m1,m2,hi,lo);
3876 if(opcode2[i]==0x1A) // DIV
3878 signed char d1=get_reg(i_regs->regmap,rs1[i]);
3879 signed char d2=get_reg(i_regs->regmap,rs2[i]);
3882 signed char quotient=get_reg(i_regs->regmap,LOREG);
3883 signed char remainder=get_reg(i_regs->regmap,HIREG);
3884 assert(quotient>=0);
3885 assert(remainder>=0);
3886 emit_movs(d1,remainder);
3887 emit_movimm(0xffffffff,quotient);
3888 emit_negmi(quotient,quotient); // .. quotient and ..
3889 emit_negmi(remainder,remainder); // .. remainder for div0 case (will be negated back after jump)
3890 emit_movs(d2,HOST_TEMPREG);
3891 emit_jeq((int)out+52); // Division by zero
3892 emit_negsmi(HOST_TEMPREG,HOST_TEMPREG);
3894 emit_clz(HOST_TEMPREG,quotient);
3895 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
3897 emit_movimm(0,quotient);
3898 emit_addpl_imm(quotient,1,quotient);
3899 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3900 emit_jns((int)out-2*4);
3902 emit_orimm(quotient,1<<31,quotient);
3903 emit_shr(quotient,quotient,quotient);
3904 emit_cmp(remainder,HOST_TEMPREG);
3905 emit_subcs(remainder,HOST_TEMPREG,remainder);
3906 emit_adcs(quotient,quotient,quotient);
3907 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
3908 emit_jcc((int)out-16); // -4
3910 emit_negmi(quotient,quotient);
3912 emit_negmi(remainder,remainder);
3914 if(opcode2[i]==0x1B) // DIVU
3916 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
3917 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
3920 signed char quotient=get_reg(i_regs->regmap,LOREG);
3921 signed char remainder=get_reg(i_regs->regmap,HIREG);
3922 assert(quotient>=0);
3923 assert(remainder>=0);
3924 emit_mov(d1,remainder);
3925 emit_movimm(0xffffffff,quotient); // div0 case
3927 emit_jeq((int)out+40); // Division by zero
3929 emit_clz(d2,HOST_TEMPREG);
3930 emit_movimm(1<<31,quotient);
3931 emit_shl(d2,HOST_TEMPREG,d2);
3933 emit_movimm(0,HOST_TEMPREG);
3934 emit_addpl_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3935 emit_lslpls_imm(d2,1,d2);
3936 emit_jns((int)out-2*4);
3937 emit_movimm(1<<31,quotient);
3939 emit_shr(quotient,HOST_TEMPREG,quotient);
3940 emit_cmp(remainder,d2);
3941 emit_subcs(remainder,d2,remainder);
3942 emit_adcs(quotient,quotient,quotient);
3943 emit_shrcc_imm(d2,1,d2);
3944 emit_jcc((int)out-16); // -4
3952 // Multiply by zero is zero.
3953 // MIPS does not have a divide by zero exception.
3954 // The result is undefined, we return zero.
3955 signed char hr=get_reg(i_regs->regmap,HIREG);
3956 signed char lr=get_reg(i_regs->regmap,LOREG);
3957 if(hr>=0) emit_zeroreg(hr);
3958 if(lr>=0) emit_zeroreg(lr);
3961 #define multdiv_assemble multdiv_assemble_arm
3963 static void do_preload_rhash(int r) {
3964 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
3965 // register. On ARM the hash can be done with a single instruction (below)
3968 static void do_preload_rhtbl(int ht) {
3969 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
3972 static void do_rhash(int rs,int rh) {
3973 emit_andimm(rs,0xf8,rh);
3976 static void do_miniht_load(int ht,int rh) {
3977 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
3978 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
3981 static void do_miniht_jump(int rs,int rh,int ht) {
3983 emit_ldreq_indexed(ht,4,15);
3984 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3986 emit_jmp(jump_vaddr_reg[7]);
3988 emit_jmp(jump_vaddr_reg[rs]);
3992 static void do_miniht_insert(u_int return_address,int rt,int temp) {
3994 emit_movimm(return_address,rt); // PC into link register
3995 add_to_linker((int)out,return_address,1);
3996 emit_pcreladdr(temp);
3997 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
3998 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4000 emit_movw(return_address&0x0000FFFF,rt);
4001 add_to_linker((int)out,return_address,1);
4002 emit_pcreladdr(temp);
4003 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4004 emit_movt(return_address&0xFFFF0000,rt);
4005 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4009 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4011 //if(dirty_pre==dirty) return;
4013 for(hr=0;hr<HOST_REGS;hr++) {
4014 if(hr!=EXCLUDE_REG) {
4016 if(((~u)>>(reg&63))&1) {
4018 if(((dirty_pre&~dirty)>>hr)&1) {
4020 emit_storereg(reg,hr);
4021 if( ((is32_pre&~uu)>>reg)&1 ) {
4022 emit_sarimm(hr,31,HOST_TEMPREG);
4023 emit_storereg(reg|64,HOST_TEMPREG);
4027 emit_storereg(reg,hr);
4037 /* using strd could possibly help but you'd have to allocate registers in pairs
4038 static void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4042 for(hr=HOST_REGS-1;hr>=0;hr--) {
4043 if(hr!=EXCLUDE_REG) {
4044 if(pre[hr]!=entry[hr]) {
4047 if(get_reg(entry,pre[hr])<0) {
4049 if(!((u>>pre[hr])&1)) {
4050 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4051 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4052 emit_sarimm(hr,31,hr+1);
4053 emit_strdreg(pre[hr],hr);
4056 emit_storereg(pre[hr],hr);
4058 emit_storereg(pre[hr],hr);
4059 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4060 emit_sarimm(hr,31,hr);
4061 emit_storereg(pre[hr]|64,hr);
4066 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4067 emit_storereg(pre[hr],hr);
4077 for(hr=0;hr<HOST_REGS;hr++) {
4078 if(hr!=EXCLUDE_REG) {
4079 if(pre[hr]!=entry[hr]) {
4082 if((nr=get_reg(entry,pre[hr]))>=0) {
4090 #define wb_invalidate wb_invalidate_arm
4093 static void mark_clear_cache(void *target)
4095 u_long offset = (char *)target - (char *)BASE_ADDR;
4096 u_int mask = 1u << ((offset >> 12) & 31);
4097 if (!(needs_clear_cache[offset >> 17] & mask)) {
4098 char *start = (char *)((u_long)target & ~4095ul);
4099 start_tcache_write(start, start + 4096);
4100 needs_clear_cache[offset >> 17] |= mask;
4104 // Clearing the cache is rather slow on ARM Linux, so mark the areas
4105 // that need to be cleared, and then only clear these areas once.
4106 static void do_clear_cache()
4109 for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
4111 u_int bitmap=needs_clear_cache[i];
4117 start=(u_int)BASE_ADDR+i*131072+j*4096;
4125 end_tcache_write((void *)start,(void *)end);
4131 needs_clear_cache[i]=0;
4136 // CPU-architecture-specific initialization
4137 static void arch_init() {
4140 // vim:shiftwidth=2:expandtab