1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus/PCSX - assem_arm.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
26 #include "../gte_arm.h"
27 #include "../gte_neon.h"
29 #include "arm_features.h"
31 #if defined(BASE_ADDR_FIXED)
32 #elif defined(BASE_ADDR_DYNAMIC)
33 char *translation_cache;
35 char translation_cache[1 << TARGET_SIZE_2] __attribute__((aligned(4096)));
39 #define CALLER_SAVE_REGS 0x100f
41 #define CALLER_SAVE_REGS 0x120f
44 #define unused __attribute__((unused))
47 #pragma GCC diagnostic ignored "-Wunused-function"
48 #pragma GCC diagnostic ignored "-Wunused-variable"
49 #pragma GCC diagnostic ignored "-Wunused-but-set-variable"
52 extern int cycle_count;
53 extern int last_count;
55 extern int pending_exception;
56 extern int branch_target;
57 extern uint64_t readmem_dword;
58 extern void *dynarec_local;
59 extern u_int mini_ht[32][2];
61 void indirect_jump_indexed();
74 void jump_vaddr_r10();
75 void jump_vaddr_r12();
77 const u_int jump_vaddr_reg[16] = {
95 void invalidate_addr_r0();
96 void invalidate_addr_r1();
97 void invalidate_addr_r2();
98 void invalidate_addr_r3();
99 void invalidate_addr_r4();
100 void invalidate_addr_r5();
101 void invalidate_addr_r6();
102 void invalidate_addr_r7();
103 void invalidate_addr_r8();
104 void invalidate_addr_r9();
105 void invalidate_addr_r10();
106 void invalidate_addr_r12();
108 const u_int invalidate_addr_reg[16] = {
109 (int)invalidate_addr_r0,
110 (int)invalidate_addr_r1,
111 (int)invalidate_addr_r2,
112 (int)invalidate_addr_r3,
113 (int)invalidate_addr_r4,
114 (int)invalidate_addr_r5,
115 (int)invalidate_addr_r6,
116 (int)invalidate_addr_r7,
117 (int)invalidate_addr_r8,
118 (int)invalidate_addr_r9,
119 (int)invalidate_addr_r10,
121 (int)invalidate_addr_r12,
126 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
130 static void set_jump_target(void *addr, void *target_)
132 u_int target = (u_int)target_;
134 u_int *ptr2=(u_int *)ptr;
136 assert((target-(u_int)ptr2-8)<1024);
137 assert(((uintptr_t)addr&3)==0);
138 assert((target&3)==0);
139 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
140 //printf("target=%x addr=%p insn=%x\n",target,addr,*ptr2);
142 else if(ptr[3]==0x72) {
143 // generated by emit_jno_unlikely
144 if((target-(u_int)ptr2-8)<1024) {
145 assert(((uintptr_t)addr&3)==0);
146 assert((target&3)==0);
147 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
149 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
150 assert(((uintptr_t)addr&3)==0);
151 assert((target&3)==0);
152 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
154 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
157 assert((ptr[3]&0x0e)==0xa);
158 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
162 // This optionally copies the instruction from the target of the branch into
163 // the space before the branch. Works, but the difference in speed is
164 // usually insignificant.
166 static void set_jump_target_fillslot(int addr,u_int target,int copy)
168 u_char *ptr=(u_char *)addr;
169 u_int *ptr2=(u_int *)ptr;
170 assert(!copy||ptr2[-1]==0xe28dd000);
173 assert((target-(u_int)ptr2-8)<4096);
174 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
177 assert((ptr[3]&0x0e)==0xa);
178 u_int target_insn=*(u_int *)target;
179 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
182 if((target_insn&0x0c100000)==0x04100000) { // Load
185 if(target_insn&0x08000000) {
189 ptr2[-1]=target_insn;
192 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
198 static void add_literal(int addr,int val)
200 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
201 literals[literalcount][0]=addr;
202 literals[literalcount][1]=val;
206 // from a pointer to external jump stub (which was produced by emit_extjump2)
207 // find where the jumping insn is
208 static void *find_extjump_insn(void *stub)
210 int *ptr=(int *)(stub+4);
211 assert((*ptr&0x0fff0000)==0x059f0000); // ldr rx, [pc, #ofs]
212 u_int offset=*ptr&0xfff;
213 void **l_ptr=(void *)ptr+offset+8;
217 // find where external branch is liked to using addr of it's stub:
218 // get address that insn one after stub loads (dyna_linker arg1),
219 // treat it as a pointer to branch insn,
220 // return addr where that branch jumps to
221 static int get_pointer(void *stub)
223 //printf("get_pointer(%x)\n",(int)stub);
224 int *i_ptr=find_extjump_insn(stub);
225 assert((*i_ptr&0x0f000000)==0x0a000000);
226 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
229 // Find the "clean" entry point from a "dirty" entry point
230 // by skipping past the call to verify_code
231 static void *get_clean_addr(void *addr)
233 signed int *ptr = addr;
239 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
240 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
242 if((*ptr&0xFF000000)==0xea000000) {
243 return (char *)ptr+((*ptr<<8)>>6)+8; // follow jump
248 static int verify_dirty(u_int *ptr)
252 // get from literal pool
253 assert((*ptr&0xFFFF0000)==0xe59f0000);
255 u_int source=*(u_int*)((void *)ptr+offset+8);
257 assert((*ptr&0xFFFF0000)==0xe59f0000);
259 u_int copy=*(u_int*)((void *)ptr+offset+8);
261 assert((*ptr&0xFFFF0000)==0xe59f0000);
263 u_int len=*(u_int*)((void *)ptr+offset+8);
268 assert((*ptr&0xFFF00000)==0xe3000000);
269 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
270 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
271 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
274 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
275 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
276 //printf("verify_dirty: %x %x %x\n",source,copy,len);
277 return !memcmp((void *)source,(void *)copy,len);
280 // This doesn't necessarily find all clean entry points, just
281 // guarantees that it's not dirty
282 static int isclean(void *addr)
285 u_int *ptr=((u_int *)addr)+4;
287 u_int *ptr=((u_int *)addr)+6;
289 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
290 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
291 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
292 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
293 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
297 // get source that block at addr was compiled from (host pointers)
298 static void get_bounds(int addr,u_int *start,u_int *end)
300 u_int *ptr=(u_int *)addr;
303 // get from literal pool
304 assert((*ptr&0xFFFF0000)==0xe59f0000);
306 u_int source=*(u_int*)((void *)ptr+offset+8);
308 //assert((*ptr&0xFFFF0000)==0xe59f0000);
310 //u_int copy=*(u_int*)((void *)ptr+offset+8);
312 assert((*ptr&0xFFFF0000)==0xe59f0000);
314 u_int len=*(u_int*)((void *)ptr+offset+8);
319 assert((*ptr&0xFFF00000)==0xe3000000);
320 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
321 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
322 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
325 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
326 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
331 /* Register allocation */
333 // Note: registers are allocated clean (unmodified state)
334 // if you intend to modify the register, you must call dirty_reg().
335 static void alloc_reg(struct regstat *cur,int i,signed char reg)
338 int preferred_reg = (reg&7);
339 if(reg==CCREG) preferred_reg=HOST_CCREG;
340 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
342 // Don't allocate unused registers
343 if((cur->u>>reg)&1) return;
345 // see if it's already allocated
346 for(hr=0;hr<HOST_REGS;hr++)
348 if(cur->regmap[hr]==reg) return;
351 // Keep the same mapping if the register was already allocated in a loop
352 preferred_reg = loop_reg(i,reg,preferred_reg);
354 // Try to allocate the preferred register
355 if(cur->regmap[preferred_reg]==-1) {
356 cur->regmap[preferred_reg]=reg;
357 cur->dirty&=~(1<<preferred_reg);
358 cur->isconst&=~(1<<preferred_reg);
361 r=cur->regmap[preferred_reg];
362 if(r<64&&((cur->u>>r)&1)) {
363 cur->regmap[preferred_reg]=reg;
364 cur->dirty&=~(1<<preferred_reg);
365 cur->isconst&=~(1<<preferred_reg);
368 if(r>=64&&((cur->uu>>(r&63))&1)) {
369 cur->regmap[preferred_reg]=reg;
370 cur->dirty&=~(1<<preferred_reg);
371 cur->isconst&=~(1<<preferred_reg);
375 // Clear any unneeded registers
376 // We try to keep the mapping consistent, if possible, because it
377 // makes branches easier (especially loops). So we try to allocate
378 // first (see above) before removing old mappings. If this is not
379 // possible then go ahead and clear out the registers that are no
381 for(hr=0;hr<HOST_REGS;hr++)
386 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
390 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
394 // Try to allocate any available register, but prefer
395 // registers that have not been used recently.
397 for(hr=0;hr<HOST_REGS;hr++) {
398 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
399 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
401 cur->dirty&=~(1<<hr);
402 cur->isconst&=~(1<<hr);
408 // Try to allocate any available register
409 for(hr=0;hr<HOST_REGS;hr++) {
410 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
412 cur->dirty&=~(1<<hr);
413 cur->isconst&=~(1<<hr);
418 // Ok, now we have to evict someone
419 // Pick a register we hopefully won't need soon
420 u_char hsn[MAXREG+1];
421 memset(hsn,10,sizeof(hsn));
423 lsn(hsn,i,&preferred_reg);
424 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
425 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
427 // Don't evict the cycle count at entry points, otherwise the entry
428 // stub will have to write it.
429 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
430 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
433 // Alloc preferred register if available
434 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
435 for(hr=0;hr<HOST_REGS;hr++) {
436 // Evict both parts of a 64-bit register
437 if((cur->regmap[hr]&63)==r) {
439 cur->dirty&=~(1<<hr);
440 cur->isconst&=~(1<<hr);
443 cur->regmap[preferred_reg]=reg;
446 for(r=1;r<=MAXREG;r++)
448 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
449 for(hr=0;hr<HOST_REGS;hr++) {
450 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
451 if(cur->regmap[hr]==r+64) {
453 cur->dirty&=~(1<<hr);
454 cur->isconst&=~(1<<hr);
459 for(hr=0;hr<HOST_REGS;hr++) {
460 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
461 if(cur->regmap[hr]==r) {
463 cur->dirty&=~(1<<hr);
464 cur->isconst&=~(1<<hr);
475 for(r=1;r<=MAXREG;r++)
478 for(hr=0;hr<HOST_REGS;hr++) {
479 if(cur->regmap[hr]==r+64) {
481 cur->dirty&=~(1<<hr);
482 cur->isconst&=~(1<<hr);
486 for(hr=0;hr<HOST_REGS;hr++) {
487 if(cur->regmap[hr]==r) {
489 cur->dirty&=~(1<<hr);
490 cur->isconst&=~(1<<hr);
497 SysPrintf("This shouldn't happen (alloc_reg)");exit(1);
500 static void alloc_reg64(struct regstat *cur,int i,signed char reg)
502 int preferred_reg = 8+(reg&1);
505 // allocate the lower 32 bits
506 alloc_reg(cur,i,reg);
508 // Don't allocate unused registers
509 if((cur->uu>>reg)&1) return;
511 // see if the upper half is already allocated
512 for(hr=0;hr<HOST_REGS;hr++)
514 if(cur->regmap[hr]==reg+64) return;
517 // Keep the same mapping if the register was already allocated in a loop
518 preferred_reg = loop_reg(i,reg,preferred_reg);
520 // Try to allocate the preferred register
521 if(cur->regmap[preferred_reg]==-1) {
522 cur->regmap[preferred_reg]=reg|64;
523 cur->dirty&=~(1<<preferred_reg);
524 cur->isconst&=~(1<<preferred_reg);
527 r=cur->regmap[preferred_reg];
528 if(r<64&&((cur->u>>r)&1)) {
529 cur->regmap[preferred_reg]=reg|64;
530 cur->dirty&=~(1<<preferred_reg);
531 cur->isconst&=~(1<<preferred_reg);
534 if(r>=64&&((cur->uu>>(r&63))&1)) {
535 cur->regmap[preferred_reg]=reg|64;
536 cur->dirty&=~(1<<preferred_reg);
537 cur->isconst&=~(1<<preferred_reg);
541 // Clear any unneeded registers
542 // We try to keep the mapping consistent, if possible, because it
543 // makes branches easier (especially loops). So we try to allocate
544 // first (see above) before removing old mappings. If this is not
545 // possible then go ahead and clear out the registers that are no
547 for(hr=HOST_REGS-1;hr>=0;hr--)
552 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
556 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
560 // Try to allocate any available register, but prefer
561 // registers that have not been used recently.
563 for(hr=0;hr<HOST_REGS;hr++) {
564 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
565 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
566 cur->regmap[hr]=reg|64;
567 cur->dirty&=~(1<<hr);
568 cur->isconst&=~(1<<hr);
574 // Try to allocate any available register
575 for(hr=0;hr<HOST_REGS;hr++) {
576 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
577 cur->regmap[hr]=reg|64;
578 cur->dirty&=~(1<<hr);
579 cur->isconst&=~(1<<hr);
584 // Ok, now we have to evict someone
585 // Pick a register we hopefully won't need soon
586 u_char hsn[MAXREG+1];
587 memset(hsn,10,sizeof(hsn));
589 lsn(hsn,i,&preferred_reg);
590 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
591 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
593 // Don't evict the cycle count at entry points, otherwise the entry
594 // stub will have to write it.
595 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
596 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
599 // Alloc preferred register if available
600 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
601 for(hr=0;hr<HOST_REGS;hr++) {
602 // Evict both parts of a 64-bit register
603 if((cur->regmap[hr]&63)==r) {
605 cur->dirty&=~(1<<hr);
606 cur->isconst&=~(1<<hr);
609 cur->regmap[preferred_reg]=reg|64;
612 for(r=1;r<=MAXREG;r++)
614 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
615 for(hr=0;hr<HOST_REGS;hr++) {
616 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
617 if(cur->regmap[hr]==r+64) {
618 cur->regmap[hr]=reg|64;
619 cur->dirty&=~(1<<hr);
620 cur->isconst&=~(1<<hr);
625 for(hr=0;hr<HOST_REGS;hr++) {
626 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
627 if(cur->regmap[hr]==r) {
628 cur->regmap[hr]=reg|64;
629 cur->dirty&=~(1<<hr);
630 cur->isconst&=~(1<<hr);
641 for(r=1;r<=MAXREG;r++)
644 for(hr=0;hr<HOST_REGS;hr++) {
645 if(cur->regmap[hr]==r+64) {
646 cur->regmap[hr]=reg|64;
647 cur->dirty&=~(1<<hr);
648 cur->isconst&=~(1<<hr);
652 for(hr=0;hr<HOST_REGS;hr++) {
653 if(cur->regmap[hr]==r) {
654 cur->regmap[hr]=reg|64;
655 cur->dirty&=~(1<<hr);
656 cur->isconst&=~(1<<hr);
663 SysPrintf("This shouldn't happen");exit(1);
666 // Allocate a temporary register. This is done without regard to
667 // dirty status or whether the register we request is on the unneeded list
668 // Note: This will only allocate one register, even if called multiple times
669 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
672 int preferred_reg = -1;
674 // see if it's already allocated
675 for(hr=0;hr<HOST_REGS;hr++)
677 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
680 // Try to allocate any available register
681 for(hr=HOST_REGS-1;hr>=0;hr--) {
682 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
684 cur->dirty&=~(1<<hr);
685 cur->isconst&=~(1<<hr);
690 // Find an unneeded register
691 for(hr=HOST_REGS-1;hr>=0;hr--)
697 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
699 cur->dirty&=~(1<<hr);
700 cur->isconst&=~(1<<hr);
707 if((cur->uu>>(r&63))&1) {
708 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
710 cur->dirty&=~(1<<hr);
711 cur->isconst&=~(1<<hr);
719 // Ok, now we have to evict someone
720 // Pick a register we hopefully won't need soon
721 // TODO: we might want to follow unconditional jumps here
722 // TODO: get rid of dupe code and make this into a function
723 u_char hsn[MAXREG+1];
724 memset(hsn,10,sizeof(hsn));
726 lsn(hsn,i,&preferred_reg);
727 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
729 // Don't evict the cycle count at entry points, otherwise the entry
730 // stub will have to write it.
731 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
732 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
735 for(r=1;r<=MAXREG;r++)
737 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
738 for(hr=0;hr<HOST_REGS;hr++) {
739 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
740 if(cur->regmap[hr]==r+64) {
742 cur->dirty&=~(1<<hr);
743 cur->isconst&=~(1<<hr);
748 for(hr=0;hr<HOST_REGS;hr++) {
749 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
750 if(cur->regmap[hr]==r) {
752 cur->dirty&=~(1<<hr);
753 cur->isconst&=~(1<<hr);
764 for(r=1;r<=MAXREG;r++)
767 for(hr=0;hr<HOST_REGS;hr++) {
768 if(cur->regmap[hr]==r+64) {
770 cur->dirty&=~(1<<hr);
771 cur->isconst&=~(1<<hr);
775 for(hr=0;hr<HOST_REGS;hr++) {
776 if(cur->regmap[hr]==r) {
778 cur->dirty&=~(1<<hr);
779 cur->isconst&=~(1<<hr);
786 SysPrintf("This shouldn't happen");exit(1);
789 // Allocate a specific ARM register.
790 static void alloc_arm_reg(struct regstat *cur,int i,signed char reg,int hr)
795 // see if it's already allocated (and dealloc it)
796 for(n=0;n<HOST_REGS;n++)
798 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
799 dirty=(cur->dirty>>n)&1;
805 cur->dirty&=~(1<<hr);
806 cur->dirty|=dirty<<hr;
807 cur->isconst&=~(1<<hr);
810 // Alloc cycle count into dedicated register
811 static void alloc_cc(struct regstat *cur,int i)
813 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
821 static unused char regname[16][4] = {
839 static void output_w32(u_int word)
841 *((u_int *)out)=word;
845 static u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
850 return((rn<<16)|(rd<<12)|rm);
853 static u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
858 assert((shift&1)==0);
859 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
862 static u_int genimm(u_int imm,u_int *encoded)
870 *encoded=((i&30)<<7)|imm;
873 imm=(imm>>2)|(imm<<30);i-=2;
878 static void genimm_checked(u_int imm,u_int *encoded)
880 u_int ret=genimm(imm,encoded);
885 static u_int genjmp(u_int addr)
887 int offset=addr-(int)out-8;
888 if(offset<-33554432||offset>=33554432) {
890 SysPrintf("genjmp: out of range: %08x\n", offset);
895 return ((u_int)offset>>2)&0xffffff;
898 static void emit_mov(int rs,int rt)
900 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
901 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
904 static void emit_movs(int rs,int rt)
906 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
907 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
910 static void emit_add(int rs1,int rs2,int rt)
912 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
913 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
916 static void emit_adds(int rs1,int rs2,int rt)
918 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
919 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
922 static void emit_adcs(int rs1,int rs2,int rt)
924 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
925 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
928 static void emit_sbc(int rs1,int rs2,int rt)
930 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
931 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
934 static void emit_sbcs(int rs1,int rs2,int rt)
936 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
937 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
940 static void emit_neg(int rs, int rt)
942 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
943 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
946 static void emit_negs(int rs, int rt)
948 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
949 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
952 static void emit_sub(int rs1,int rs2,int rt)
954 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
955 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
958 static void emit_subs(int rs1,int rs2,int rt)
960 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
961 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
964 static void emit_zeroreg(int rt)
966 assem_debug("mov %s,#0\n",regname[rt]);
967 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
970 static void emit_loadlp(u_int imm,u_int rt)
972 add_literal((int)out,imm);
973 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
974 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
977 static void emit_movw(u_int imm,u_int rt)
980 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
981 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
984 static void emit_movt(u_int imm,u_int rt)
986 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
987 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
990 static void emit_movimm(u_int imm,u_int rt)
993 if(genimm(imm,&armval)) {
994 assem_debug("mov %s,#%d\n",regname[rt],imm);
995 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
996 }else if(genimm(~imm,&armval)) {
997 assem_debug("mvn %s,#%d\n",regname[rt],imm);
998 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
999 }else if(imm<65536) {
1001 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
1002 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
1003 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1004 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1010 emit_loadlp(imm,rt);
1012 emit_movw(imm&0x0000FFFF,rt);
1013 emit_movt(imm&0xFFFF0000,rt);
1018 static void emit_pcreladdr(u_int rt)
1020 assem_debug("add %s,pc,#?\n",regname[rt]);
1021 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1024 static void emit_loadreg(int r, int hr)
1027 SysPrintf("64bit load in 32bit mode!\n");
1034 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1035 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1036 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1037 if(r==CCREG) addr=(int)&cycle_count;
1038 if(r==CSREG) addr=(int)&Status;
1039 if(r==FSREG) addr=(int)&FCR31;
1040 if(r==INVCP) addr=(int)&invc_ptr;
1041 u_int offset = addr-(u_int)&dynarec_local;
1042 assert(offset<4096);
1043 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1044 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1048 static void emit_storereg(int r, int hr)
1051 SysPrintf("64bit store in 32bit mode!\n");
1055 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1056 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1057 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1058 if(r==CCREG) addr=(int)&cycle_count;
1059 if(r==FSREG) addr=(int)&FCR31;
1060 u_int offset = addr-(u_int)&dynarec_local;
1061 assert(offset<4096);
1062 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1063 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1066 static void emit_test(int rs, int rt)
1068 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1069 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1072 static void emit_testimm(int rs,int imm)
1075 assem_debug("tst %s,#%d\n",regname[rs],imm);
1076 genimm_checked(imm,&armval);
1077 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1080 static void emit_testeqimm(int rs,int imm)
1083 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1084 genimm_checked(imm,&armval);
1085 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1088 static void emit_not(int rs,int rt)
1090 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1091 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1094 static void emit_mvnmi(int rs,int rt)
1096 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1097 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1100 static void emit_and(u_int rs1,u_int rs2,u_int rt)
1102 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1103 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1106 static void emit_or(u_int rs1,u_int rs2,u_int rt)
1108 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1109 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1112 static void emit_or_and_set_flags(int rs1,int rs2,int rt)
1114 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1115 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1118 static void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1123 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1124 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1127 static void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1132 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1133 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1136 static void emit_xor(u_int rs1,u_int rs2,u_int rt)
1138 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1139 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1142 static void emit_addimm(u_int rs,int imm,u_int rt)
1148 if(genimm(imm,&armval)) {
1149 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1150 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1151 }else if(genimm(-imm,&armval)) {
1152 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-imm);
1153 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1155 }else if(rt!=rs&&(u_int)imm<65536) {
1156 emit_movw(imm&0x0000ffff,rt);
1158 }else if(rt!=rs&&(u_int)-imm<65536) {
1159 emit_movw(-imm&0x0000ffff,rt);
1162 }else if((u_int)-imm<65536) {
1163 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1164 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1165 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1166 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1169 int shift = (ffs(imm) - 1) & ~1;
1170 int imm8 = imm & (0xff << shift);
1171 genimm_checked(imm8,&armval);
1172 assem_debug("add %s,%s,#0x%x\n",regname[rt],regname[rs],imm8);
1173 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1180 else if(rs!=rt) emit_mov(rs,rt);
1183 static void emit_addimm_and_set_flags(int imm,int rt)
1185 assert(imm>-65536&&imm<65536);
1187 if(genimm(imm,&armval)) {
1188 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1189 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1190 }else if(genimm(-imm,&armval)) {
1191 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1192 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1194 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1195 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1196 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1197 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1199 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1200 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1201 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1202 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1206 static void emit_addimm_no_flags(u_int imm,u_int rt)
1208 emit_addimm(rt,imm,rt);
1211 static void emit_addnop(u_int r)
1214 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1215 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1218 static void emit_adcimm(u_int rs,int imm,u_int rt)
1221 genimm_checked(imm,&armval);
1222 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1223 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1226 static void emit_rscimm(int rs,int imm,u_int rt)
1230 genimm_checked(imm,&armval);
1231 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1232 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1235 static void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1237 // TODO: if(genimm(imm,&armval)) ...
1239 emit_movimm(imm,HOST_TEMPREG);
1240 emit_adds(HOST_TEMPREG,rsl,rtl);
1241 emit_adcimm(rsh,0,rth);
1244 static void emit_andimm(int rs,int imm,int rt)
1249 }else if(genimm(imm,&armval)) {
1250 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1251 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1252 }else if(genimm(~imm,&armval)) {
1253 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1254 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1255 }else if(imm==65535) {
1257 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1258 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1259 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1260 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1262 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1263 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1266 assert(imm>0&&imm<65535);
1268 assem_debug("mov r14,#%d\n",imm&0xFF00);
1269 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1270 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1271 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1273 emit_movw(imm,HOST_TEMPREG);
1275 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1276 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1280 static void emit_orimm(int rs,int imm,int rt)
1284 if(rs!=rt) emit_mov(rs,rt);
1285 }else if(genimm(imm,&armval)) {
1286 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1287 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1289 assert(imm>0&&imm<65536);
1290 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1291 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1292 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1293 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1297 static void emit_xorimm(int rs,int imm,int rt)
1301 if(rs!=rt) emit_mov(rs,rt);
1302 }else if(genimm(imm,&armval)) {
1303 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1304 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1306 assert(imm>0&&imm<65536);
1307 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1308 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1309 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1310 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1314 static void emit_shlimm(int rs,u_int imm,int rt)
1319 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1320 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1323 static void emit_lsls_imm(int rs,int imm,int rt)
1327 assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1328 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1331 static unused void emit_lslpls_imm(int rs,int imm,int rt)
1335 assem_debug("lslpls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1336 output_w32(0x51b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1339 static void emit_shrimm(int rs,u_int imm,int rt)
1343 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1344 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1347 static void emit_sarimm(int rs,u_int imm,int rt)
1351 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1352 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1355 static void emit_rorimm(int rs,u_int imm,int rt)
1359 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1360 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1363 static void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1365 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1369 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1370 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1371 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1372 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1375 static void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1377 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1381 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1382 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1383 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1384 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1387 static void emit_signextend16(int rs,int rt)
1390 emit_shlimm(rs,16,rt);
1391 emit_sarimm(rt,16,rt);
1393 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1394 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1398 static void emit_signextend8(int rs,int rt)
1401 emit_shlimm(rs,24,rt);
1402 emit_sarimm(rt,24,rt);
1404 assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
1405 output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
1409 static void emit_shl(u_int rs,u_int shift,u_int rt)
1415 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1416 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1419 static void emit_shr(u_int rs,u_int shift,u_int rt)
1424 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1425 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1428 static void emit_sar(u_int rs,u_int shift,u_int rt)
1433 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1434 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1437 static void emit_orrshl(u_int rs,u_int shift,u_int rt)
1442 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1443 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1446 static void emit_orrshr(u_int rs,u_int shift,u_int rt)
1451 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1452 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1455 static void emit_cmpimm(int rs,int imm)
1458 if(genimm(imm,&armval)) {
1459 assem_debug("cmp %s,#%d\n",regname[rs],imm);
1460 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1461 }else if(genimm(-imm,&armval)) {
1462 assem_debug("cmn %s,#%d\n",regname[rs],imm);
1463 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1466 emit_movimm(imm,HOST_TEMPREG);
1467 assem_debug("cmp %s,r14\n",regname[rs]);
1468 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1471 emit_movimm(-imm,HOST_TEMPREG);
1472 assem_debug("cmn %s,r14\n",regname[rs]);
1473 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1477 static void emit_cmovne_imm(int imm,int rt)
1479 assem_debug("movne %s,#%d\n",regname[rt],imm);
1481 genimm_checked(imm,&armval);
1482 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1485 static void emit_cmovl_imm(int imm,int rt)
1487 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1489 genimm_checked(imm,&armval);
1490 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1493 static void emit_cmovb_imm(int imm,int rt)
1495 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1497 genimm_checked(imm,&armval);
1498 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1501 static void emit_cmovs_imm(int imm,int rt)
1503 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1505 genimm_checked(imm,&armval);
1506 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1509 static void emit_cmove_reg(int rs,int rt)
1511 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1512 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1515 static void emit_cmovne_reg(int rs,int rt)
1517 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1518 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1521 static void emit_cmovl_reg(int rs,int rt)
1523 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1524 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1527 static void emit_cmovs_reg(int rs,int rt)
1529 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1530 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1533 static void emit_slti32(int rs,int imm,int rt)
1535 if(rs!=rt) emit_zeroreg(rt);
1536 emit_cmpimm(rs,imm);
1537 if(rs==rt) emit_movimm(0,rt);
1538 emit_cmovl_imm(1,rt);
1541 static void emit_sltiu32(int rs,int imm,int rt)
1543 if(rs!=rt) emit_zeroreg(rt);
1544 emit_cmpimm(rs,imm);
1545 if(rs==rt) emit_movimm(0,rt);
1546 emit_cmovb_imm(1,rt);
1549 static void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1552 emit_slti32(rsl,imm,rt);
1556 emit_cmovne_imm(0,rt);
1557 emit_cmovs_imm(1,rt);
1561 emit_cmpimm(rsh,-1);
1562 emit_cmovne_imm(0,rt);
1563 emit_cmovl_imm(1,rt);
1567 static void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1570 emit_sltiu32(rsl,imm,rt);
1574 emit_cmovne_imm(0,rt);
1578 emit_cmpimm(rsh,-1);
1579 emit_cmovne_imm(1,rt);
1583 static void emit_cmp(int rs,int rt)
1585 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1586 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1589 static void emit_set_gz32(int rs, int rt)
1591 //assem_debug("set_gz32\n");
1594 emit_cmovl_imm(0,rt);
1597 static void emit_set_nz32(int rs, int rt)
1599 //assem_debug("set_nz32\n");
1600 if(rs!=rt) emit_movs(rs,rt);
1601 else emit_test(rs,rs);
1602 emit_cmovne_imm(1,rt);
1605 static void emit_set_gz64_32(int rsh, int rsl, int rt)
1607 //assem_debug("set_gz64\n");
1608 emit_set_gz32(rsl,rt);
1610 emit_cmovne_imm(1,rt);
1611 emit_cmovs_imm(0,rt);
1614 static void emit_set_nz64_32(int rsh, int rsl, int rt)
1616 //assem_debug("set_nz64\n");
1617 emit_or_and_set_flags(rsh,rsl,rt);
1618 emit_cmovne_imm(1,rt);
1621 static void emit_set_if_less32(int rs1, int rs2, int rt)
1623 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1624 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1626 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1627 emit_cmovl_imm(1,rt);
1630 static void emit_set_if_carry32(int rs1, int rs2, int rt)
1632 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1633 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1635 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1636 emit_cmovb_imm(1,rt);
1639 static void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1641 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1646 emit_sbcs(u1,u2,HOST_TEMPREG);
1647 emit_cmovl_imm(1,rt);
1650 static void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1652 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1657 emit_sbcs(u1,u2,HOST_TEMPREG);
1658 emit_cmovb_imm(1,rt);
1662 extern void gen_interupt();
1663 extern void do_insn_cmp();
1664 #define FUNCNAME(f) { (intptr_t)f, " " #f }
1665 static const struct {
1668 } function_names[] = {
1669 FUNCNAME(cc_interrupt),
1670 FUNCNAME(gen_interupt),
1671 FUNCNAME(get_addr_ht),
1673 FUNCNAME(jump_handler_read8),
1674 FUNCNAME(jump_handler_read16),
1675 FUNCNAME(jump_handler_read32),
1676 FUNCNAME(jump_handler_write8),
1677 FUNCNAME(jump_handler_write16),
1678 FUNCNAME(jump_handler_write32),
1679 FUNCNAME(invalidate_addr),
1680 FUNCNAME(verify_code_vm),
1681 FUNCNAME(verify_code),
1682 FUNCNAME(jump_hlecall),
1683 FUNCNAME(jump_syscall_hle),
1684 FUNCNAME(new_dyna_leave),
1685 FUNCNAME(pcsx_mtc0),
1686 FUNCNAME(pcsx_mtc0_ds),
1687 FUNCNAME(do_insn_cmp),
1690 static const char *func_name(intptr_t a)
1693 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1694 if (function_names[i].addr == a)
1695 return function_names[i].name;
1699 #define func_name(x) ""
1702 static void emit_call(int a)
1704 assem_debug("bl %x (%x+%x)%s\n",a,(int)out,a-(int)out-8,func_name(a));
1705 u_int offset=genjmp(a);
1706 output_w32(0xeb000000|offset);
1709 static void emit_jmp(int a)
1711 assem_debug("b %x (%x+%x)%s\n",a,(int)out,a-(int)out-8,func_name(a));
1712 u_int offset=genjmp(a);
1713 output_w32(0xea000000|offset);
1716 static void emit_jne(int a)
1718 assem_debug("bne %x\n",a);
1719 u_int offset=genjmp(a);
1720 output_w32(0x1a000000|offset);
1723 static void emit_jeq(int a)
1725 assem_debug("beq %x\n",a);
1726 u_int offset=genjmp(a);
1727 output_w32(0x0a000000|offset);
1730 static void emit_js(int a)
1732 assem_debug("bmi %x\n",a);
1733 u_int offset=genjmp(a);
1734 output_w32(0x4a000000|offset);
1737 static void emit_jns(int a)
1739 assem_debug("bpl %x\n",a);
1740 u_int offset=genjmp(a);
1741 output_w32(0x5a000000|offset);
1744 static void emit_jl(int a)
1746 assem_debug("blt %x\n",a);
1747 u_int offset=genjmp(a);
1748 output_w32(0xba000000|offset);
1751 static void emit_jge(int a)
1753 assem_debug("bge %x\n",a);
1754 u_int offset=genjmp(a);
1755 output_w32(0xaa000000|offset);
1758 static void emit_jno(int a)
1760 assem_debug("bvc %x\n",a);
1761 u_int offset=genjmp(a);
1762 output_w32(0x7a000000|offset);
1765 static void emit_jc(int a)
1767 assem_debug("bcs %x\n",a);
1768 u_int offset=genjmp(a);
1769 output_w32(0x2a000000|offset);
1772 static void emit_jcc(int a)
1774 assem_debug("bcc %x\n",a);
1775 u_int offset=genjmp(a);
1776 output_w32(0x3a000000|offset);
1779 static void emit_callreg(u_int r)
1782 assem_debug("blx %s\n",regname[r]);
1783 output_w32(0xe12fff30|r);
1786 static void emit_jmpreg(u_int r)
1788 assem_debug("mov pc,%s\n",regname[r]);
1789 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1792 static void emit_readword_indexed(int offset, int rs, int rt)
1794 assert(offset>-4096&&offset<4096);
1795 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1797 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1799 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1803 static void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1805 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1806 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1809 static void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
1811 assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1812 output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
1815 static void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
1817 assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1818 output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
1821 static void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
1823 assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1824 output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
1827 static void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
1829 assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1830 output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
1833 static void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
1835 assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1836 output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
1839 static void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1841 if(map<0) emit_readword_indexed(addr, rs, rt);
1844 emit_readword_dualindexedx4(rs, map, rt);
1848 static void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1851 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1852 emit_readword_indexed(addr+4, rs, rl);
1855 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1856 emit_addimm(map,1,map);
1857 emit_readword_indexed_tlb(addr, rs, map, rl);
1861 static void emit_movsbl_indexed(int offset, int rs, int rt)
1863 assert(offset>-256&&offset<256);
1864 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1866 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1868 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1872 static void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1874 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1877 emit_shlimm(map,2,map);
1878 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1879 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1881 assert(addr>-256&&addr<256);
1882 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1883 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1884 emit_movsbl_indexed(addr, rt, rt);
1889 static void emit_movswl_indexed(int offset, int rs, int rt)
1891 assert(offset>-256&&offset<256);
1892 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1894 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1896 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1900 static void emit_movzbl_indexed(int offset, int rs, int rt)
1902 assert(offset>-4096&&offset<4096);
1903 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1905 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1907 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1911 static void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1913 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1914 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1917 static void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1919 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1922 emit_movzbl_dualindexedx4(rs, map, rt);
1924 emit_addimm(rs,addr,rt);
1925 emit_movzbl_dualindexedx4(rt, map, rt);
1930 static void emit_movzwl_indexed(int offset, int rs, int rt)
1932 assert(offset>-256&&offset<256);
1933 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1935 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1937 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1941 static void emit_ldrd(int offset, int rs, int rt)
1943 assert(offset>-256&&offset<256);
1944 assem_debug("ldrd %s,%s+%d\n",regname[rt],regname[rs],offset);
1946 output_w32(0xe1c000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1948 output_w32(0xe14000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1952 static void emit_readword(int addr, int rt)
1954 u_int offset = addr-(u_int)&dynarec_local;
1955 assert(offset<4096);
1956 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1957 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1960 static unused void emit_movsbl(int addr, int rt)
1962 u_int offset = addr-(u_int)&dynarec_local;
1964 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1965 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1968 static unused void emit_movswl(int addr, int rt)
1970 u_int offset = addr-(u_int)&dynarec_local;
1972 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1973 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1976 static unused void emit_movzbl(int addr, int rt)
1978 u_int offset = addr-(u_int)&dynarec_local;
1979 assert(offset<4096);
1980 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1981 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1984 static unused void emit_movzwl(int addr, int rt)
1986 u_int offset = addr-(u_int)&dynarec_local;
1988 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1989 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1992 static void emit_writeword_indexed(int rt, int offset, int rs)
1994 assert(offset>-4096&&offset<4096);
1995 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1997 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
1999 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
2003 static void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
2005 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2006 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
2009 static void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2011 if(map<0) emit_writeword_indexed(rt, addr, rs);
2014 emit_writeword_dualindexedx4(rt, rs, map);
2018 static void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
2021 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
2022 emit_writeword_indexed(rl, addr+4, rs);
2025 if(temp!=rs) emit_addimm(map,1,temp);
2026 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
2027 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
2029 emit_addimm(rs,4,rs);
2030 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
2035 static void emit_writehword_indexed(int rt, int offset, int rs)
2037 assert(offset>-256&&offset<256);
2038 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
2040 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
2042 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
2046 static void emit_writebyte_indexed(int rt, int offset, int rs)
2048 assert(offset>-4096&&offset<4096);
2049 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
2051 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
2053 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
2057 static void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
2059 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2060 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
2063 static void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2065 if(map<0) emit_writebyte_indexed(rt, addr, rs);
2068 emit_writebyte_dualindexedx4(rt, rs, map);
2070 emit_addimm(rs,addr,temp);
2071 emit_writebyte_dualindexedx4(rt, temp, map);
2076 static void emit_strcc_dualindexed(int rs1, int rs2, int rt)
2078 assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2079 output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
2082 static void emit_strccb_dualindexed(int rs1, int rs2, int rt)
2084 assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2085 output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
2088 static void emit_strcch_dualindexed(int rs1, int rs2, int rt)
2090 assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2091 output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
2094 static void emit_writeword(int rt, int addr)
2096 u_int offset = addr-(u_int)&dynarec_local;
2097 assert(offset<4096);
2098 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2099 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2102 static unused void emit_writehword(int rt, int addr)
2104 u_int offset = addr-(u_int)&dynarec_local;
2106 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2107 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2110 static unused void emit_writebyte(int rt, int addr)
2112 u_int offset = addr-(u_int)&dynarec_local;
2113 assert(offset<4096);
2114 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2115 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2118 static void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2120 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2125 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2128 static void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2130 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2135 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2138 static void emit_clz(int rs,int rt)
2140 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2141 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2144 static void emit_subcs(int rs1,int rs2,int rt)
2146 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2147 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2150 static void emit_shrcc_imm(int rs,u_int imm,int rt)
2154 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2155 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2158 static void emit_shrne_imm(int rs,u_int imm,int rt)
2162 assem_debug("lsrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2163 output_w32(0x11a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2166 static void emit_negmi(int rs, int rt)
2168 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2169 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2172 static void emit_negsmi(int rs, int rt)
2174 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2175 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2178 static void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2180 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2181 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2184 static void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2186 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2187 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2190 static void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2192 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2193 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2196 static void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2198 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2199 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2202 static void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2204 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2205 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2208 static void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2210 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2211 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2214 static void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2216 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2217 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2220 static void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2222 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2223 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2226 static void emit_teq(int rs, int rt)
2228 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2229 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2232 static void emit_rsbimm(int rs, int imm, int rt)
2235 genimm_checked(imm,&armval);
2236 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2237 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2240 // Load 2 immediates optimizing for small code size
2241 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2243 emit_movimm(imm1,rt1);
2245 if(genimm(imm2-imm1,&armval)) {
2246 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2247 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2248 }else if(genimm(imm1-imm2,&armval)) {
2249 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2250 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2252 else emit_movimm(imm2,rt2);
2255 // Conditionally select one of two immediates, optimizing for small code size
2256 // This will only be called if HAVE_CMOV_IMM is defined
2257 static void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2260 if(genimm(imm2-imm1,&armval)) {
2261 emit_movimm(imm1,rt);
2262 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2263 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2264 }else if(genimm(imm1-imm2,&armval)) {
2265 emit_movimm(imm1,rt);
2266 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2267 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2271 emit_movimm(imm1,rt);
2272 add_literal((int)out,imm2);
2273 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2274 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2276 emit_movw(imm1&0x0000FFFF,rt);
2277 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2278 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2279 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2281 emit_movt(imm1&0xFFFF0000,rt);
2282 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2283 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2284 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2290 // special case for checking invalid_code
2291 static void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2293 assert(imm<128&&imm>=0);
2295 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2296 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2297 emit_cmpimm(HOST_TEMPREG,imm);
2300 static void emit_callne(int a)
2302 assem_debug("blne %x\n",a);
2303 u_int offset=genjmp(a);
2304 output_w32(0x1b000000|offset);
2307 // Used to preload hash table entries
2308 static unused void emit_prefetchreg(int r)
2310 assem_debug("pld %s\n",regname[r]);
2311 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2314 // Special case for mini_ht
2315 static void emit_ldreq_indexed(int rs, u_int offset, int rt)
2317 assert(offset<4096);
2318 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2319 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2322 static unused void emit_bicne_imm(int rs,int imm,int rt)
2325 genimm_checked(imm,&armval);
2326 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2327 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2330 static unused void emit_biccs_imm(int rs,int imm,int rt)
2333 genimm_checked(imm,&armval);
2334 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2335 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2338 static unused void emit_bicvc_imm(int rs,int imm,int rt)
2341 genimm_checked(imm,&armval);
2342 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2343 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2346 static unused void emit_bichi_imm(int rs,int imm,int rt)
2349 genimm_checked(imm,&armval);
2350 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2351 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2354 static unused void emit_orrvs_imm(int rs,int imm,int rt)
2357 genimm_checked(imm,&armval);
2358 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2359 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2362 static void emit_orrne_imm(int rs,int imm,int rt)
2365 genimm_checked(imm,&armval);
2366 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2367 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2370 static void emit_andne_imm(int rs,int imm,int rt)
2373 genimm_checked(imm,&armval);
2374 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2375 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2378 static unused void emit_addpl_imm(int rs,int imm,int rt)
2381 genimm_checked(imm,&armval);
2382 assem_debug("addpl %s,%s,#%d\n",regname[rt],regname[rs],imm);
2383 output_w32(0x52800000|rd_rn_rm(rt,rs,0)|armval);
2386 static void emit_jno_unlikely(int a)
2389 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2390 output_w32(0x72800000|rd_rn_rm(15,15,0));
2393 static void save_regs_all(u_int reglist)
2396 if(!reglist) return;
2397 assem_debug("stmia fp,{");
2400 assem_debug("r%d,",i);
2402 output_w32(0xe88b0000|reglist);
2405 static void restore_regs_all(u_int reglist)
2408 if(!reglist) return;
2409 assem_debug("ldmia fp,{");
2412 assem_debug("r%d,",i);
2414 output_w32(0xe89b0000|reglist);
2417 // Save registers before function call
2418 static void save_regs(u_int reglist)
2420 reglist&=CALLER_SAVE_REGS; // only save the caller-save registers, r0-r3, r12
2421 save_regs_all(reglist);
2424 // Restore registers after function call
2425 static void restore_regs(u_int reglist)
2427 reglist&=CALLER_SAVE_REGS;
2428 restore_regs_all(reglist);
2431 /* Stubs/epilogue */
2433 static void literal_pool(int n)
2435 if(!literalcount) return;
2437 if((int)out-literals[0][0]<4096-n) return;
2441 for(i=0;i<literalcount;i++)
2443 u_int l_addr=(u_int)out;
2446 if(literals[j][1]==literals[i][1]) {
2447 //printf("dup %08x\n",literals[i][1]);
2448 l_addr=literals[j][0];
2452 ptr=(u_int *)literals[i][0];
2453 u_int offset=l_addr-(u_int)ptr-8;
2454 assert(offset<4096);
2455 assert(!(offset&3));
2457 if(l_addr==(u_int)out) {
2458 literals[i][0]=l_addr; // remember for dupes
2459 output_w32(literals[i][1]);
2465 static void literal_pool_jumpover(int n)
2467 if(!literalcount) return;
2469 if((int)out-literals[0][0]<4096-n) return;
2474 set_jump_target(jaddr, out);
2477 static void emit_extjump2(u_int addr, int target, int linker)
2479 u_char *ptr=(u_char *)addr;
2480 assert((ptr[3]&0x0e)==0xa);
2483 emit_loadlp(target,0);
2484 emit_loadlp(addr,1);
2485 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2486 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2488 #ifdef DEBUG_CYCLE_COUNT
2489 emit_readword((int)&last_count,ECX);
2490 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2491 emit_readword((int)&next_interupt,ECX);
2492 emit_writeword(HOST_CCREG,(int)&Count);
2493 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2494 emit_writeword(ECX,(int)&last_count);
2500 static void emit_extjump(int addr, int target)
2502 emit_extjump2(addr, target, (int)dyna_linker);
2505 static void emit_extjump_ds(int addr, int target)
2507 emit_extjump2(addr, target, (int)dyna_linker_ds);
2510 // put rt_val into rt, potentially making use of rs with value rs_val
2511 static void emit_movimm_from(u_int rs_val,int rs,u_int rt_val,int rt)
2515 if(genimm(rt_val,&armval)) {
2516 assem_debug("mov %s,#%d\n",regname[rt],rt_val);
2517 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
2520 if(genimm(~rt_val,&armval)) {
2521 assem_debug("mvn %s,#%d\n",regname[rt],rt_val);
2522 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
2526 if(genimm(diff,&armval)) {
2527 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],diff);
2528 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
2530 }else if(genimm(-diff,&armval)) {
2531 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-diff);
2532 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
2535 emit_movimm(rt_val,rt);
2538 // return 1 if above function can do it's job cheaply
2539 static int is_similar_value(u_int v1,u_int v2)
2543 if(v1==v2) return 1;
2545 for(xs=diff;xs!=0&&(xs&3)==0;xs>>=2)
2547 if(xs<0x100) return 1;
2548 for(xs=-diff;xs!=0&&(xs&3)==0;xs>>=2)
2550 if(xs<0x100) return 1;
2555 static void pass_args(int a0, int a1)
2559 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2561 else if(a0!=0&&a1==0) {
2563 if (a0>=0) emit_mov(a0,0);
2566 if(a0>=0&&a0!=0) emit_mov(a0,0);
2567 if(a1>=0&&a1!=1) emit_mov(a1,1);
2571 static void mov_loadtype_adj(int type,int rs,int rt)
2574 case LOADB_STUB: emit_signextend8(rs,rt); break;
2575 case LOADBU_STUB: emit_andimm(rs,0xff,rt); break;
2576 case LOADH_STUB: emit_signextend16(rs,rt); break;
2577 case LOADHU_STUB: emit_andimm(rs,0xffff,rt); break;
2578 case LOADW_STUB: if(rs!=rt) emit_mov(rs,rt); break;
2583 #include "pcsxmem.h"
2584 #include "pcsxmem_inline.c"
2586 static void do_readstub(int n)
2588 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2590 set_jump_target(stubs[n][1], out);
2591 int type=stubs[n][0];
2594 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2595 u_int reglist=stubs[n][7];
2596 signed char *i_regmap=i_regs->regmap;
2598 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2599 rt=get_reg(i_regmap,FTEMP);
2601 rt=get_reg(i_regmap,rt1[i]);
2604 int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0;
2605 void *restore_jump = NULL;
2607 for(r=0;r<=12;r++) {
2608 if(((1<<r)&0x13ff)&&((1<<r)®list)==0) {
2612 if(rt>=0&&rt1[i]!=0)
2619 if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
2621 emit_readword((int)&mem_rtab,temp);
2622 emit_shrimm(rs,12,temp2);
2623 emit_readword_dualindexedx4(temp,temp2,temp2);
2624 emit_lsls_imm(temp2,1,temp2);
2625 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2627 case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
2628 case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
2629 case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
2630 case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
2631 case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
2636 emit_jcc(0); // jump to reg restore
2639 emit_jcc(stubs[n][2]); // return address
2644 if(type==LOADB_STUB||type==LOADBU_STUB)
2645 handler=(int)jump_handler_read8;
2646 if(type==LOADH_STUB||type==LOADHU_STUB)
2647 handler=(int)jump_handler_read16;
2648 if(type==LOADW_STUB)
2649 handler=(int)jump_handler_read32;
2651 pass_args(rs,temp2);
2652 int cc=get_reg(i_regmap,CCREG);
2654 emit_loadreg(CCREG,2);
2655 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2657 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2658 mov_loadtype_adj(type,0,rt);
2661 set_jump_target(restore_jump, out);
2662 restore_regs(reglist);
2663 emit_jmp(stubs[n][2]); // return address
2666 // return memhandler, or get directly accessable address and return 0
2667 static u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
2670 l1=((u_int *)table)[addr>>12];
2671 if((l1&(1<<31))==0) {
2678 if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
2679 l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2680 else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
2681 l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
2683 l2=((u_int *)l1)[(addr&0xfff)/4];
2684 if((l2&(1<<31))==0) {
2686 *addr_host=v+(addr&0xfff);
2693 static void inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2695 int rs=get_reg(regmap,target);
2696 int rt=get_reg(regmap,target);
2697 if(rs<0) rs=get_reg(regmap,-1);
2699 u_int handler,host_addr=0,is_dynamic,far_call=0;
2700 int cc=get_reg(regmap,CCREG);
2701 if(pcsx_direct_read(type,addr,CLOCK_ADJUST(adj+1),cc,target?rs:-1,rt))
2703 handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
2708 emit_movimm_from(addr,rs,host_addr,rs);
2710 case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
2711 case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
2712 case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
2713 case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
2714 case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
2719 is_dynamic=pcsxmem_is_handler_dynamic(addr);
2721 if(type==LOADB_STUB||type==LOADBU_STUB)
2722 handler=(int)jump_handler_read8;
2723 if(type==LOADH_STUB||type==LOADHU_STUB)
2724 handler=(int)jump_handler_read16;
2725 if(type==LOADW_STUB)
2726 handler=(int)jump_handler_read32;
2729 // call a memhandler
2730 if(rt>=0&&rt1[i]!=0)
2734 emit_movimm(addr,0);
2737 int offset=(int)handler-(int)out-8;
2738 if(offset<-33554432||offset>=33554432) {
2739 // unreachable memhandler, a plugin func perhaps
2740 emit_movimm(handler,12);
2744 emit_loadreg(CCREG,2);
2746 emit_movimm(((u_int *)mem_rtab)[addr>>12]<<1,1);
2747 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2750 emit_readword((int)&last_count,3);
2751 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2753 emit_writeword(2,(int)&Count);
2761 if(rt>=0&&rt1[i]!=0) {
2763 case LOADB_STUB: emit_signextend8(0,rt); break;
2764 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
2765 case LOADH_STUB: emit_signextend16(0,rt); break;
2766 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
2767 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
2771 restore_regs(reglist);
2774 static void do_writestub(int n)
2776 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
2778 set_jump_target(stubs[n][1], out);
2779 int type=stubs[n][0];
2782 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2783 u_int reglist=stubs[n][7];
2784 signed char *i_regmap=i_regs->regmap;
2786 if(itype[i]==C1LS||itype[i]==C2LS) {
2787 rt=get_reg(i_regmap,r=FTEMP);
2789 rt=get_reg(i_regmap,r=rs2[i]);
2793 int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,ra;
2794 void *restore_jump = NULL;
2795 int reglist2=reglist|(1<<rs)|(1<<rt);
2796 for(rtmp=0;rtmp<=12;rtmp++) {
2797 if(((1<<rtmp)&0x13ff)&&((1<<rtmp)®list2)==0) {
2804 for(rtmp=0;rtmp<=3;rtmp++)
2805 if(rtmp!=rs&&rtmp!=rt)
2808 if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
2810 emit_readword((int)&mem_wtab,temp);
2811 emit_shrimm(rs,12,temp2);
2812 emit_readword_dualindexedx4(temp,temp2,temp2);
2813 emit_lsls_imm(temp2,1,temp2);
2815 case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
2816 case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
2817 case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
2822 emit_jcc(0); // jump to reg restore
2825 emit_jcc(stubs[n][2]); // return address (invcode check)
2831 case STOREB_STUB: handler=(int)jump_handler_write8; break;
2832 case STOREH_STUB: handler=(int)jump_handler_write16; break;
2833 case STOREW_STUB: handler=(int)jump_handler_write32; break;
2839 int cc=get_reg(i_regmap,CCREG);
2841 emit_loadreg(CCREG,2);
2842 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2843 // returns new cycle_count
2845 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
2847 emit_storereg(CCREG,2);
2849 set_jump_target(restore_jump, out);
2850 restore_regs(reglist);
2855 static void inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
2857 int rs=get_reg(regmap,-1);
2858 int rt=get_reg(regmap,target);
2861 u_int handler,host_addr=0;
2862 handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
2865 emit_movimm_from(addr,rs,host_addr,rs);
2867 case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
2868 case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
2869 case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
2875 // call a memhandler
2878 int cc=get_reg(regmap,CCREG);
2880 emit_loadreg(CCREG,2);
2881 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
2882 emit_movimm(handler,3);
2883 // returns new cycle_count
2884 emit_call((int)jump_handler_write_h);
2885 emit_addimm(0,-CLOCK_ADJUST(adj+1),cc<0?2:cc);
2887 emit_storereg(CCREG,2);
2888 restore_regs(reglist);
2891 static void do_unalignedwritestub(int n)
2893 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
2895 set_jump_target(stubs[n][1], out);
2898 struct regstat *i_regs=(struct regstat *)stubs[n][4];
2899 int addr=stubs[n][5];
2900 u_int reglist=stubs[n][7];
2901 signed char *i_regmap=i_regs->regmap;
2902 int temp2=get_reg(i_regmap,FTEMP);
2904 rt=get_reg(i_regmap,rs2[i]);
2907 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
2909 reglist&=~(1<<temp2);
2912 // don't bother with it and call write handler
2915 int cc=get_reg(i_regmap,CCREG);
2917 emit_loadreg(CCREG,2);
2918 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2919 emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
2920 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
2922 emit_storereg(CCREG,2);
2923 restore_regs(reglist);
2924 emit_jmp(stubs[n][2]); // return address
2926 emit_andimm(addr,0xfffffffc,temp2);
2927 emit_writeword(temp2,(int)&address);
2930 emit_shrimm(addr,16,1);
2931 int cc=get_reg(i_regmap,CCREG);
2933 emit_loadreg(CCREG,2);
2935 emit_movimm((u_int)readmem,0);
2936 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2937 emit_call((int)&indirect_jump_indexed);
2938 restore_regs(reglist);
2940 emit_readword((int)&readmem_dword,temp2);
2941 int temp=addr; //hmh
2942 emit_shlimm(addr,3,temp);
2943 emit_andimm(temp,24,temp);
2944 #ifdef BIG_ENDIAN_MIPS
2945 if (opcode[i]==0x2e) // SWR
2947 if (opcode[i]==0x2a) // SWL
2949 emit_xorimm(temp,24,temp);
2950 emit_movimm(-1,HOST_TEMPREG);
2951 if (opcode[i]==0x2a) { // SWL
2952 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
2953 emit_orrshr(rt,temp,temp2);
2955 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
2956 emit_orrshl(rt,temp,temp2);
2958 emit_readword((int)&address,addr);
2959 emit_writeword(temp2,(int)&word);
2960 //save_regs(reglist); // don't need to, no state changes
2961 emit_shrimm(addr,16,1);
2962 emit_movimm((u_int)writemem,0);
2963 //emit_call((int)&indirect_jump_indexed);
2965 emit_readword_dualindexedx4(0,1,15);
2966 emit_readword((int)&Count,HOST_TEMPREG);
2967 emit_readword((int)&next_interupt,2);
2968 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2969 emit_writeword(2,(int)&last_count);
2970 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2972 emit_storereg(CCREG,HOST_TEMPREG);
2974 restore_regs(reglist);
2975 emit_jmp(stubs[n][2]); // return address
2979 static void do_invstub(int n)
2982 u_int reglist=stubs[n][3];
2983 set_jump_target(stubs[n][1], out);
2985 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
2986 emit_call((int)&invalidate_addr);
2987 restore_regs(reglist);
2988 emit_jmp(stubs[n][2]); // return address
2991 void *do_dirty_stub(int i)
2993 assem_debug("do_dirty_stub %x\n",start+i*4);
2994 u_int addr=(u_int)source;
2995 // Careful about the code output here, verify_dirty needs to parse it.
2997 emit_loadlp(addr,1);
2998 emit_loadlp((int)copy,2);
2999 emit_loadlp(slen*4,3);
3001 emit_movw(addr&0x0000FFFF,1);
3002 emit_movw(((u_int)copy)&0x0000FFFF,2);
3003 emit_movt(addr&0xFFFF0000,1);
3004 emit_movt(((u_int)copy)&0xFFFF0000,2);
3005 emit_movw(slen*4,3);
3007 emit_movimm(start+i*4,0);
3008 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
3012 entry = instr_addr[i];
3013 emit_jmp(instr_addr[i]);
3017 static void do_dirty_stub_ds()
3019 // Careful about the code output here, verify_dirty needs to parse it.
3021 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3022 emit_loadlp((int)copy,2);
3023 emit_loadlp(slen*4,3);
3025 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3026 emit_movw(((u_int)copy)&0x0000FFFF,2);
3027 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3028 emit_movt(((u_int)copy)&0xFFFF0000,2);
3029 emit_movw(slen*4,3);
3031 emit_movimm(start+1,0);
3032 emit_call((int)&verify_code_ds);
3035 static void do_cop1stub(int n)
3038 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3039 set_jump_target(stubs[n][1], out);
3041 // int rs=stubs[n][4];
3042 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3045 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3046 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3048 //else {printf("fp exception in delay slot\n");}
3049 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3050 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3051 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3052 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3053 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3058 static void shift_assemble_arm(int i,struct regstat *i_regs)
3061 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3063 signed char s,t,shift;
3064 t=get_reg(i_regs->regmap,rt1[i]);
3065 s=get_reg(i_regs->regmap,rs1[i]);
3066 shift=get_reg(i_regs->regmap,rs2[i]);
3075 if(s!=t) emit_mov(s,t);
3079 emit_andimm(shift,31,HOST_TEMPREG);
3080 if(opcode2[i]==4) // SLLV
3082 emit_shl(s,HOST_TEMPREG,t);
3084 if(opcode2[i]==6) // SRLV
3086 emit_shr(s,HOST_TEMPREG,t);
3088 if(opcode2[i]==7) // SRAV
3090 emit_sar(s,HOST_TEMPREG,t);
3094 } else { // DSLLV/DSRLV/DSRAV
3095 signed char sh,sl,th,tl,shift;
3096 th=get_reg(i_regs->regmap,rt1[i]|64);
3097 tl=get_reg(i_regs->regmap,rt1[i]);
3098 sh=get_reg(i_regs->regmap,rs1[i]|64);
3099 sl=get_reg(i_regs->regmap,rs1[i]);
3100 shift=get_reg(i_regs->regmap,rs2[i]);
3105 if(th>=0) emit_zeroreg(th);
3110 if(sl!=tl) emit_mov(sl,tl);
3111 if(th>=0&&sh!=th) emit_mov(sh,th);
3115 // FIXME: What if shift==tl ?
3117 int temp=get_reg(i_regs->regmap,-1);
3119 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3122 emit_andimm(shift,31,HOST_TEMPREG);
3123 if(opcode2[i]==0x14) // DSLLV
3125 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3126 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3127 emit_orrshr(sl,HOST_TEMPREG,th);
3128 emit_andimm(shift,31,HOST_TEMPREG);
3129 emit_testimm(shift,32);
3130 emit_shl(sl,HOST_TEMPREG,tl);
3131 if(th>=0) emit_cmovne_reg(tl,th);
3132 emit_cmovne_imm(0,tl);
3134 if(opcode2[i]==0x16) // DSRLV
3137 emit_shr(sl,HOST_TEMPREG,tl);
3138 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3139 emit_orrshl(sh,HOST_TEMPREG,tl);
3140 emit_andimm(shift,31,HOST_TEMPREG);
3141 emit_testimm(shift,32);
3142 emit_shr(sh,HOST_TEMPREG,th);
3143 emit_cmovne_reg(th,tl);
3144 if(real_th>=0) emit_cmovne_imm(0,th);
3146 if(opcode2[i]==0x17) // DSRAV
3149 emit_shr(sl,HOST_TEMPREG,tl);
3150 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3153 emit_sarimm(th,31,temp);
3155 emit_orrshl(sh,HOST_TEMPREG,tl);
3156 emit_andimm(shift,31,HOST_TEMPREG);
3157 emit_testimm(shift,32);
3158 emit_sar(sh,HOST_TEMPREG,th);
3159 emit_cmovne_reg(th,tl);
3160 if(real_th>=0) emit_cmovne_reg(temp,th);
3168 static void speculate_mov(int rs,int rt)
3171 smrv_strong_next|=1<<rt;
3176 static void speculate_mov_weak(int rs,int rt)
3179 smrv_weak_next|=1<<rt;
3184 static void speculate_register_values(int i)
3187 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3188 // gp,sp are likely to stay the same throughout the block
3189 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3190 smrv_weak_next=~smrv_strong_next;
3191 //printf(" llr %08x\n", smrv[4]);
3193 smrv_strong=smrv_strong_next;
3194 smrv_weak=smrv_weak_next;
3197 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3198 else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
3199 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3200 else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
3202 smrv_strong_next&=~(1<<rt1[i]);
3203 smrv_weak_next&=~(1<<rt1[i]);
3207 smrv_strong_next&=~(1<<rt1[i]);
3208 smrv_weak_next&=~(1<<rt1[i]);
3211 if(rt1[i]&&is_const(®s[i],rt1[i])) {
3212 int value,hr=get_reg(regs[i].regmap,rt1[i]);
3214 if(get_final_value(hr,i,&value))
3216 else smrv[rt1[i]]=constmap[i][hr];
3217 smrv_strong_next|=1<<rt1[i];
3221 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3222 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3226 if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
3227 // special case for BIOS
3228 smrv[rt1[i]]=0xa0000000;
3229 smrv_strong_next|=1<<rt1[i];
3236 smrv_strong_next&=~(1<<rt1[i]);
3237 smrv_weak_next&=~(1<<rt1[i]);
3241 if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
3242 smrv_strong_next&=~(1<<rt1[i]);
3243 smrv_weak_next&=~(1<<rt1[i]);
3247 if (opcode[i]==0x32) { // LWC2
3248 smrv_strong_next&=~(1<<rt1[i]);
3249 smrv_weak_next&=~(1<<rt1[i]);
3255 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
3256 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
3268 static int get_ptr_mem_type(u_int a)
3270 if(a < 0x00200000) {
3271 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
3272 // return wrong, must use memhandler for BIOS self-test to pass
3273 // 007 does similar stuff from a00 mirror, weird stuff
3277 if(0x1f800000 <= a && a < 0x1f801000)
3279 if(0x80200000 <= a && a < 0x80800000)
3281 if(0xa0000000 <= a && a < 0xa0200000)
3286 static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
3290 if(((smrv_strong|smrv_weak)>>mr)&1) {
3291 type=get_ptr_mem_type(smrv[mr]);
3292 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
3295 // use the mirror we are running on
3296 type=get_ptr_mem_type(start);
3297 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
3300 if(type==MTYPE_8020) { // RAM 80200000+ mirror
3301 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3302 addr=*addr_reg_override=HOST_TEMPREG;
3305 else if(type==MTYPE_0000) { // RAM 0 mirror
3306 emit_orimm(addr,0x80000000,HOST_TEMPREG);
3307 addr=*addr_reg_override=HOST_TEMPREG;
3310 else if(type==MTYPE_A000) { // RAM A mirror
3311 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
3312 addr=*addr_reg_override=HOST_TEMPREG;
3315 else if(type==MTYPE_1F80) { // scratchpad
3316 if (psxH == (void *)0x1f800000) {
3317 emit_addimm(addr,-0x1f800000,HOST_TEMPREG);
3318 emit_cmpimm(HOST_TEMPREG,0x1000);
3323 // do usual RAM check, jump will go to the right handler
3330 emit_cmpimm(addr,RAM_SIZE);
3332 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3333 // Hint to branch predictor that the branch is unlikely to be taken
3335 emit_jno_unlikely(0);
3340 emit_addimm(addr,ram_offset,HOST_TEMPREG);
3341 addr=*addr_reg_override=HOST_TEMPREG;
3348 #define shift_assemble shift_assemble_arm
3350 static void loadlr_assemble_arm(int i,struct regstat *i_regs)
3352 int s,th,tl,temp,temp2,addr,map=-1;
3355 int memtarget=0,c=0;
3356 int fastload_reg_override=0;
3358 th=get_reg(i_regs->regmap,rt1[i]|64);
3359 tl=get_reg(i_regs->regmap,rt1[i]);
3360 s=get_reg(i_regs->regmap,rs1[i]);
3361 temp=get_reg(i_regs->regmap,-1);
3362 temp2=get_reg(i_regs->regmap,FTEMP);
3363 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3366 for(hr=0;hr<HOST_REGS;hr++) {
3367 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3370 if(offset||s<0||c) addr=temp2;
3373 c=(i_regs->wasconst>>s)&1;
3375 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3380 map=get_reg(i_regs->regmap,ROREG);
3381 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3383 emit_shlimm(addr,3,temp);
3384 if (opcode[i]==0x22||opcode[i]==0x26) {
3385 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3387 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3389 jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override);
3392 if(ram_offset&&memtarget) {
3393 emit_addimm(temp2,ram_offset,HOST_TEMPREG);
3394 fastload_reg_override=HOST_TEMPREG;
3396 if (opcode[i]==0x22||opcode[i]==0x26) {
3397 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3399 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3402 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
3405 if(fastload_reg_override) a=fastload_reg_override;
3406 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
3407 emit_readword_indexed_tlb(0,a,map,temp2);
3408 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3411 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
3414 emit_andimm(temp,24,temp);
3415 #ifdef BIG_ENDIAN_MIPS
3416 if (opcode[i]==0x26) // LWR
3418 if (opcode[i]==0x22) // LWL
3420 emit_xorimm(temp,24,temp);
3421 emit_movimm(-1,HOST_TEMPREG);
3422 if (opcode[i]==0x26) {
3423 emit_shr(temp2,temp,temp2);
3424 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3426 emit_shl(temp2,temp,temp2);
3427 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3429 emit_or(temp2,tl,tl);
3431 //emit_storereg(rt1[i],tl); // DEBUG
3433 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
3434 // FIXME: little endian, fastload_reg_override
3435 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
3437 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
3438 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
3439 emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2);
3440 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
3443 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
3447 emit_testimm(temp,32);
3448 emit_andimm(temp,24,temp);
3449 if (opcode[i]==0x1A) { // LDL
3450 emit_rsbimm(temp,32,HOST_TEMPREG);
3451 emit_shl(temp2h,temp,temp2h);
3452 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
3453 emit_movimm(-1,HOST_TEMPREG);
3454 emit_shl(temp2,temp,temp2);
3455 emit_cmove_reg(temp2h,th);
3456 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
3457 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
3458 emit_orreq(temp2,tl,tl);
3459 emit_orrne(temp2,th,th);
3461 if (opcode[i]==0x1B) { // LDR
3462 emit_xorimm(temp,24,temp);
3463 emit_rsbimm(temp,32,HOST_TEMPREG);
3464 emit_shr(temp2,temp,temp2);
3465 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
3466 emit_movimm(-1,HOST_TEMPREG);
3467 emit_shr(temp2h,temp,temp2h);
3468 emit_cmovne_reg(temp2,tl);
3469 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
3470 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
3471 emit_orrne(temp2h,th,th);
3472 emit_orreq(temp2h,tl,tl);
3477 #define loadlr_assemble loadlr_assemble_arm
3479 static void cop0_assemble(int i,struct regstat *i_regs)
3481 if(opcode2[i]==0) // MFC0
3483 signed char t=get_reg(i_regs->regmap,rt1[i]);
3484 char copr=(source[i]>>11)&0x1f;
3485 //assert(t>=0); // Why does this happen? OOT is weird
3486 if(t>=0&&rt1[i]!=0) {
3487 emit_readword((int)®_cop0+copr*4,t);
3490 else if(opcode2[i]==4) // MTC0
3492 signed char s=get_reg(i_regs->regmap,rs1[i]);
3493 char copr=(source[i]>>11)&0x1f;
3495 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
3496 if(copr==9||copr==11||copr==12||copr==13) {
3497 emit_readword((int)&last_count,HOST_TEMPREG);
3498 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3499 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3500 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3501 emit_writeword(HOST_CCREG,(int)&Count);
3503 // What a mess. The status register (12) can enable interrupts,
3504 // so needs a special case to handle a pending interrupt.
3505 // The interrupt must be taken immediately, because a subsequent
3506 // instruction might disable interrupts again.
3507 if(copr==12||copr==13) {
3509 // burn cycles to cause cc_interrupt, which will
3510 // reschedule next_interupt. Relies on CCREG from above.
3511 assem_debug("MTC0 DS %d\n", copr);
3512 emit_writeword(HOST_CCREG,(int)&last_count);
3513 emit_movimm(0,HOST_CCREG);
3514 emit_storereg(CCREG,HOST_CCREG);
3515 emit_loadreg(rs1[i],1);
3516 emit_movimm(copr,0);
3517 emit_call((int)pcsx_mtc0_ds);
3518 emit_loadreg(rs1[i],s);
3521 emit_movimm(start+i*4+4,HOST_TEMPREG);
3522 emit_writeword(HOST_TEMPREG,(int)&pcaddr);
3523 emit_movimm(0,HOST_TEMPREG);
3524 emit_writeword(HOST_TEMPREG,(int)&pending_exception);
3526 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
3529 emit_loadreg(rs1[i],1);
3532 emit_movimm(copr,0);
3533 emit_call((int)pcsx_mtc0);
3534 if(copr==9||copr==11||copr==12||copr==13) {
3535 emit_readword((int)&Count,HOST_CCREG);
3536 emit_readword((int)&next_interupt,HOST_TEMPREG);
3537 emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3538 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3539 emit_writeword(HOST_TEMPREG,(int)&last_count);
3540 emit_storereg(CCREG,HOST_CCREG);
3542 if(copr==12||copr==13) {
3543 assert(!is_delayslot);
3544 emit_readword((int)&pending_exception,14);
3546 emit_jne((int)&do_interrupt);
3548 emit_loadreg(rs1[i],s);
3549 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
3550 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
3555 assert(opcode2[i]==0x10);
3556 if((source[i]&0x3f)==0x10) // RFE
3558 emit_readword((int)&Status,0);
3559 emit_andimm(0,0x3c,1);
3560 emit_andimm(0,~0xf,0);
3561 emit_orrshr_imm(1,2,0);
3562 emit_writeword(0,(int)&Status);
3567 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3577 emit_readword((int)®_cop2d[copr],tl);
3578 emit_signextend16(tl,tl);
3579 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
3586 emit_readword((int)®_cop2d[copr],tl);
3587 emit_andimm(tl,0xffff,tl);
3588 emit_writeword(tl,(int)®_cop2d[copr]);
3591 emit_readword((int)®_cop2d[14],tl); // SXY2
3592 emit_writeword(tl,(int)®_cop2d[copr]);
3596 emit_readword((int)®_cop2d[9],temp);
3597 emit_testimm(temp,0x8000); // do we need this?
3598 emit_andimm(temp,0xf80,temp);
3599 emit_andne_imm(temp,0,temp);
3600 emit_shrimm(temp,7,tl);
3601 emit_readword((int)®_cop2d[10],temp);
3602 emit_testimm(temp,0x8000);
3603 emit_andimm(temp,0xf80,temp);
3604 emit_andne_imm(temp,0,temp);
3605 emit_orrshr_imm(temp,2,tl);
3606 emit_readword((int)®_cop2d[11],temp);
3607 emit_testimm(temp,0x8000);
3608 emit_andimm(temp,0xf80,temp);
3609 emit_andne_imm(temp,0,temp);
3610 emit_orrshl_imm(temp,3,tl);
3611 emit_writeword(tl,(int)®_cop2d[copr]);
3614 emit_readword((int)®_cop2d[copr],tl);
3619 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3623 emit_readword((int)®_cop2d[13],temp); // SXY1
3624 emit_writeword(sl,(int)®_cop2d[copr]);
3625 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
3626 emit_readword((int)®_cop2d[14],temp); // SXY2
3627 emit_writeword(sl,(int)®_cop2d[14]);
3628 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
3631 emit_andimm(sl,0x001f,temp);
3632 emit_shlimm(temp,7,temp);
3633 emit_writeword(temp,(int)®_cop2d[9]);
3634 emit_andimm(sl,0x03e0,temp);
3635 emit_shlimm(temp,2,temp);
3636 emit_writeword(temp,(int)®_cop2d[10]);
3637 emit_andimm(sl,0x7c00,temp);
3638 emit_shrimm(temp,3,temp);
3639 emit_writeword(temp,(int)®_cop2d[11]);
3640 emit_writeword(sl,(int)®_cop2d[28]);
3644 emit_mvnmi(temp,temp);
3646 emit_clz(temp,temp);
3648 emit_movs(temp,HOST_TEMPREG);
3649 emit_movimm(0,temp);
3650 emit_jeq((int)out+4*4);
3651 emit_addpl_imm(temp,1,temp);
3652 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3653 emit_jns((int)out-2*4);
3655 emit_writeword(sl,(int)®_cop2d[30]);
3656 emit_writeword(temp,(int)®_cop2d[31]);
3661 emit_writeword(sl,(int)®_cop2d[copr]);
3666 static void cop2_assemble(int i,struct regstat *i_regs)
3668 u_int copr=(source[i]>>11)&0x1f;
3669 signed char temp=get_reg(i_regs->regmap,-1);
3670 if (opcode2[i]==0) { // MFC2
3671 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3672 if(tl>=0&&rt1[i]!=0)
3673 cop2_get_dreg(copr,tl,temp);
3675 else if (opcode2[i]==4) { // MTC2
3676 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3677 cop2_put_dreg(copr,sl,temp);
3679 else if (opcode2[i]==2) // CFC2
3681 signed char tl=get_reg(i_regs->regmap,rt1[i]);
3682 if(tl>=0&&rt1[i]!=0)
3683 emit_readword((int)®_cop2c[copr],tl);
3685 else if (opcode2[i]==6) // CTC2
3687 signed char sl=get_reg(i_regs->regmap,rs1[i]);
3696 emit_signextend16(sl,temp);
3699 //value = value & 0x7ffff000;
3700 //if (value & 0x7f87e000) value |= 0x80000000;
3701 emit_shrimm(sl,12,temp);
3702 emit_shlimm(temp,12,temp);
3703 emit_testimm(temp,0x7f000000);
3704 emit_testeqimm(temp,0x00870000);
3705 emit_testeqimm(temp,0x0000e000);
3706 emit_orrne_imm(temp,0x80000000,temp);
3712 emit_writeword(temp,(int)®_cop2c[copr]);
3717 static void c2op_prologue(u_int op,u_int reglist)
3719 save_regs_all(reglist);
3722 emit_call((int)pcnt_gte_start);
3724 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs
3727 static void c2op_epilogue(u_int op,u_int reglist)
3731 emit_call((int)pcnt_gte_end);
3733 restore_regs_all(reglist);
3736 static void c2op_call_MACtoIR(int lm,int need_flags)
3739 emit_call((int)(lm?gteMACtoIR_lm1:gteMACtoIR_lm0));
3741 emit_call((int)(lm?gteMACtoIR_lm1_nf:gteMACtoIR_lm0_nf));
3744 static void c2op_call_rgb_func(void *func,int lm,int need_ir,int need_flags)
3746 emit_call((int)func);
3747 // func is C code and trashes r0
3748 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3749 if(need_flags||need_ir)
3750 c2op_call_MACtoIR(lm,need_flags);
3751 emit_call((int)(need_flags?gteMACtoRGB:gteMACtoRGB_nf));
3754 static void c2op_assemble(int i,struct regstat *i_regs)
3756 u_int c2op=source[i]&0x3f;
3757 u_int hr,reglist_full=0,reglist;
3758 int need_flags,need_ir;
3759 for(hr=0;hr<HOST_REGS;hr++) {
3760 if(i_regs->regmap[hr]>=0) reglist_full|=1<<hr;
3762 reglist=reglist_full&CALLER_SAVE_REGS;
3764 if (gte_handlers[c2op]!=NULL) {
3765 need_flags=!(gte_unneeded[i+1]>>63); // +1 because of how liveness detection works
3766 need_ir=(gte_unneeded[i+1]&0xe00)!=0xe00;
3767 assem_debug("gte op %08x, unneeded %016llx, need_flags %d, need_ir %d\n",
3768 source[i],gte_unneeded[i+1],need_flags,need_ir);
3769 if(new_dynarec_hacks&NDHACK_GTE_NO_FLAGS)
3771 int shift = (source[i] >> 19) & 1;
3772 int lm = (source[i] >> 10) & 1;
3777 int v = (source[i] >> 15) & 3;
3778 int cv = (source[i] >> 13) & 3;
3779 int mx = (source[i] >> 17) & 3;
3780 reglist=reglist_full&(CALLER_SAVE_REGS|0xf0); // +{r4-r7}
3781 c2op_prologue(c2op,reglist);
3782 /* r4,r5 = VXYZ(v) packed; r6 = &MX11(mx); r7 = &CV1(cv) */
3786 emit_movzwl_indexed(9*4,0,4); // gteIR
3787 emit_movzwl_indexed(10*4,0,6);
3788 emit_movzwl_indexed(11*4,0,5);
3789 emit_orrshl_imm(6,16,4);
3792 emit_addimm(0,32*4+mx*8*4,6);
3794 emit_readword((int)&zeromem_ptr,6);
3796 emit_addimm(0,32*4+(cv*8+5)*4,7);
3798 emit_readword((int)&zeromem_ptr,7);
3800 emit_movimm(source[i],1); // opcode
3801 emit_call((int)gteMVMVA_part_neon);
3804 emit_call((int)gteMACtoIR_flags_neon);
3808 emit_call((int)gteMVMVA_part_cv3sh12_arm);
3810 emit_movimm(shift,1);
3811 emit_call((int)(need_flags?gteMVMVA_part_arm:gteMVMVA_part_nf_arm));
3813 if(need_flags||need_ir)
3814 c2op_call_MACtoIR(lm,need_flags);
3816 #else /* if not HAVE_ARMV5 */
3817 c2op_prologue(c2op,reglist);
3818 emit_movimm(source[i],1); // opcode
3819 emit_writeword(1,(int)&psxRegs.code);
3820 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
3825 c2op_prologue(c2op,reglist);
3826 emit_call((int)(shift?gteOP_part_shift:gteOP_part_noshift));
3827 if(need_flags||need_ir) {
3828 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3829 c2op_call_MACtoIR(lm,need_flags);
3833 c2op_prologue(c2op,reglist);
3834 c2op_call_rgb_func(shift?gteDPCS_part_shift:gteDPCS_part_noshift,lm,need_ir,need_flags);
3837 c2op_prologue(c2op,reglist);
3838 c2op_call_rgb_func(shift?gteINTPL_part_shift:gteINTPL_part_noshift,lm,need_ir,need_flags);
3841 c2op_prologue(c2op,reglist);
3842 emit_call((int)(shift?gteSQR_part_shift:gteSQR_part_noshift));
3843 if(need_flags||need_ir) {
3844 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
3845 c2op_call_MACtoIR(lm,need_flags);
3849 c2op_prologue(c2op,reglist);
3850 c2op_call_rgb_func(gteDCPL_part,lm,need_ir,need_flags);
3853 c2op_prologue(c2op,reglist);
3854 c2op_call_rgb_func(shift?gteGPF_part_shift:gteGPF_part_noshift,lm,need_ir,need_flags);
3857 c2op_prologue(c2op,reglist);
3858 c2op_call_rgb_func(shift?gteGPL_part_shift:gteGPL_part_noshift,lm,need_ir,need_flags);
3862 c2op_prologue(c2op,reglist);
3864 emit_movimm(source[i],1); // opcode
3865 emit_writeword(1,(int)&psxRegs.code);
3867 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
3870 c2op_epilogue(c2op,reglist);
3874 static void cop1_unusable(int i,struct regstat *i_regs)
3876 // XXX: should just just do the exception instead
3880 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
3885 static void cop1_assemble(int i,struct regstat *i_regs)
3887 cop1_unusable(i, i_regs);
3890 static void fconv_assemble_arm(int i,struct regstat *i_regs)
3892 cop1_unusable(i, i_regs);
3894 #define fconv_assemble fconv_assemble_arm
3896 static void fcomp_assemble(int i,struct regstat *i_regs)
3898 cop1_unusable(i, i_regs);
3901 static void float_assemble(int i,struct regstat *i_regs)
3903 cop1_unusable(i, i_regs);
3906 static void multdiv_assemble_arm(int i,struct regstat *i_regs)
3913 // case 0x1D: DMULTU
3918 if((opcode2[i]&4)==0) // 32-bit
3920 if(opcode2[i]==0x18) // MULT
3922 signed char m1=get_reg(i_regs->regmap,rs1[i]);
3923 signed char m2=get_reg(i_regs->regmap,rs2[i]);
3924 signed char hi=get_reg(i_regs->regmap,HIREG);
3925 signed char lo=get_reg(i_regs->regmap,LOREG);
3930 emit_smull(m1,m2,hi,lo);
3932 if(opcode2[i]==0x19) // MULTU
3934 signed char m1=get_reg(i_regs->regmap,rs1[i]);
3935 signed char m2=get_reg(i_regs->regmap,rs2[i]);
3936 signed char hi=get_reg(i_regs->regmap,HIREG);
3937 signed char lo=get_reg(i_regs->regmap,LOREG);
3942 emit_umull(m1,m2,hi,lo);
3944 if(opcode2[i]==0x1A) // DIV
3946 signed char d1=get_reg(i_regs->regmap,rs1[i]);
3947 signed char d2=get_reg(i_regs->regmap,rs2[i]);
3950 signed char quotient=get_reg(i_regs->regmap,LOREG);
3951 signed char remainder=get_reg(i_regs->regmap,HIREG);
3952 assert(quotient>=0);
3953 assert(remainder>=0);
3954 emit_movs(d1,remainder);
3955 emit_movimm(0xffffffff,quotient);
3956 emit_negmi(quotient,quotient); // .. quotient and ..
3957 emit_negmi(remainder,remainder); // .. remainder for div0 case (will be negated back after jump)
3958 emit_movs(d2,HOST_TEMPREG);
3959 emit_jeq((int)out+52); // Division by zero
3960 emit_negsmi(HOST_TEMPREG,HOST_TEMPREG);
3962 emit_clz(HOST_TEMPREG,quotient);
3963 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
3965 emit_movimm(0,quotient);
3966 emit_addpl_imm(quotient,1,quotient);
3967 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3968 emit_jns((int)out-2*4);
3970 emit_orimm(quotient,1<<31,quotient);
3971 emit_shr(quotient,quotient,quotient);
3972 emit_cmp(remainder,HOST_TEMPREG);
3973 emit_subcs(remainder,HOST_TEMPREG,remainder);
3974 emit_adcs(quotient,quotient,quotient);
3975 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
3976 emit_jcc((int)out-16); // -4
3978 emit_negmi(quotient,quotient);
3980 emit_negmi(remainder,remainder);
3982 if(opcode2[i]==0x1B) // DIVU
3984 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
3985 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
3988 signed char quotient=get_reg(i_regs->regmap,LOREG);
3989 signed char remainder=get_reg(i_regs->regmap,HIREG);
3990 assert(quotient>=0);
3991 assert(remainder>=0);
3992 emit_mov(d1,remainder);
3993 emit_movimm(0xffffffff,quotient); // div0 case
3995 emit_jeq((int)out+40); // Division by zero
3997 emit_clz(d2,HOST_TEMPREG);
3998 emit_movimm(1<<31,quotient);
3999 emit_shl(d2,HOST_TEMPREG,d2);
4001 emit_movimm(0,HOST_TEMPREG);
4002 emit_addpl_imm(HOST_TEMPREG,1,HOST_TEMPREG);
4003 emit_lslpls_imm(d2,1,d2);
4004 emit_jns((int)out-2*4);
4005 emit_movimm(1<<31,quotient);
4007 emit_shr(quotient,HOST_TEMPREG,quotient);
4008 emit_cmp(remainder,d2);
4009 emit_subcs(remainder,d2,remainder);
4010 emit_adcs(quotient,quotient,quotient);
4011 emit_shrcc_imm(d2,1,d2);
4012 emit_jcc((int)out-16); // -4
4020 // Multiply by zero is zero.
4021 // MIPS does not have a divide by zero exception.
4022 // The result is undefined, we return zero.
4023 signed char hr=get_reg(i_regs->regmap,HIREG);
4024 signed char lr=get_reg(i_regs->regmap,LOREG);
4025 if(hr>=0) emit_zeroreg(hr);
4026 if(lr>=0) emit_zeroreg(lr);
4029 #define multdiv_assemble multdiv_assemble_arm
4031 static void do_preload_rhash(int r) {
4032 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
4033 // register. On ARM the hash can be done with a single instruction (below)
4036 static void do_preload_rhtbl(int ht) {
4037 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
4040 static void do_rhash(int rs,int rh) {
4041 emit_andimm(rs,0xf8,rh);
4044 static void do_miniht_load(int ht,int rh) {
4045 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
4046 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
4049 static void do_miniht_jump(int rs,int rh,int ht) {
4051 emit_ldreq_indexed(ht,4,15);
4052 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4054 emit_jmp(jump_vaddr_reg[7]);
4056 emit_jmp(jump_vaddr_reg[rs]);
4060 static void do_miniht_insert(u_int return_address,int rt,int temp) {
4062 emit_movimm(return_address,rt); // PC into link register
4063 add_to_linker((int)out,return_address,1);
4064 emit_pcreladdr(temp);
4065 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4066 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4068 emit_movw(return_address&0x0000FFFF,rt);
4069 add_to_linker((int)out,return_address,1);
4070 emit_pcreladdr(temp);
4071 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
4072 emit_movt(return_address&0xFFFF0000,rt);
4073 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
4077 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
4079 //if(dirty_pre==dirty) return;
4081 for(hr=0;hr<HOST_REGS;hr++) {
4082 if(hr!=EXCLUDE_REG) {
4084 if(((~u)>>(reg&63))&1) {
4086 if(((dirty_pre&~dirty)>>hr)&1) {
4088 emit_storereg(reg,hr);
4089 if( ((is32_pre&~uu)>>reg)&1 ) {
4090 emit_sarimm(hr,31,HOST_TEMPREG);
4091 emit_storereg(reg|64,HOST_TEMPREG);
4095 emit_storereg(reg,hr);
4105 /* using strd could possibly help but you'd have to allocate registers in pairs
4106 static void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
4110 for(hr=HOST_REGS-1;hr>=0;hr--) {
4111 if(hr!=EXCLUDE_REG) {
4112 if(pre[hr]!=entry[hr]) {
4115 if(get_reg(entry,pre[hr])<0) {
4117 if(!((u>>pre[hr])&1)) {
4118 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
4119 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4120 emit_sarimm(hr,31,hr+1);
4121 emit_strdreg(pre[hr],hr);
4124 emit_storereg(pre[hr],hr);
4126 emit_storereg(pre[hr],hr);
4127 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4128 emit_sarimm(hr,31,hr);
4129 emit_storereg(pre[hr]|64,hr);
4134 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4135 emit_storereg(pre[hr],hr);
4145 for(hr=0;hr<HOST_REGS;hr++) {
4146 if(hr!=EXCLUDE_REG) {
4147 if(pre[hr]!=entry[hr]) {
4150 if((nr=get_reg(entry,pre[hr]))>=0) {
4158 #define wb_invalidate wb_invalidate_arm
4161 static void mark_clear_cache(void *target)
4163 u_long offset = (char *)target - (char *)BASE_ADDR;
4164 u_int mask = 1u << ((offset >> 12) & 31);
4165 if (!(needs_clear_cache[offset >> 17] & mask)) {
4166 char *start = (char *)((u_long)target & ~4095ul);
4167 start_tcache_write(start, start + 4096);
4168 needs_clear_cache[offset >> 17] |= mask;
4172 // Clearing the cache is rather slow on ARM Linux, so mark the areas
4173 // that need to be cleared, and then only clear these areas once.
4174 static void do_clear_cache()
4177 for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
4179 u_int bitmap=needs_clear_cache[i];
4185 start=(u_int)BASE_ADDR+i*131072+j*4096;
4193 end_tcache_write((void *)start,(void *)end);
4199 needs_clear_cache[i]=0;
4204 // CPU-architecture-specific initialization
4205 static void arch_init() {
4208 // vim:shiftwidth=2:expandtab