1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus/PCSX - assem_arm.c *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2011 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
27 #include "../gte_arm.h"
28 #include "../gte_neon.h"
32 extern int cycle_count;
33 extern int last_count;
35 extern int pending_exception;
36 extern int branch_target;
37 extern uint64_t readmem_dword;
39 extern precomp_instr fake_pc;
41 extern void *dynarec_local;
42 extern u_int memory_map[1048576];
43 extern u_int mini_ht[32][2];
44 extern u_int rounding_modes[4];
46 void indirect_jump_indexed();
59 void jump_vaddr_r10();
60 void jump_vaddr_r12();
62 const u_int jump_vaddr_reg[16] = {
80 void invalidate_addr_r0();
81 void invalidate_addr_r1();
82 void invalidate_addr_r2();
83 void invalidate_addr_r3();
84 void invalidate_addr_r4();
85 void invalidate_addr_r5();
86 void invalidate_addr_r6();
87 void invalidate_addr_r7();
88 void invalidate_addr_r8();
89 void invalidate_addr_r9();
90 void invalidate_addr_r10();
91 void invalidate_addr_r12();
93 const u_int invalidate_addr_reg[16] = {
94 (int)invalidate_addr_r0,
95 (int)invalidate_addr_r1,
96 (int)invalidate_addr_r2,
97 (int)invalidate_addr_r3,
98 (int)invalidate_addr_r4,
99 (int)invalidate_addr_r5,
100 (int)invalidate_addr_r6,
101 (int)invalidate_addr_r7,
102 (int)invalidate_addr_r8,
103 (int)invalidate_addr_r9,
104 (int)invalidate_addr_r10,
106 (int)invalidate_addr_r12,
113 unsigned int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
117 void set_jump_target(int addr,u_int target)
119 u_char *ptr=(u_char *)addr;
120 u_int *ptr2=(u_int *)ptr;
122 assert((target-(u_int)ptr2-8)<1024);
124 assert((target&3)==0);
125 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
126 //printf("target=%x addr=%x insn=%x\n",target,addr,*ptr2);
128 else if(ptr[3]==0x72) {
129 // generated by emit_jno_unlikely
130 if((target-(u_int)ptr2-8)<1024) {
132 assert((target&3)==0);
133 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>2)|0xF00;
135 else if((target-(u_int)ptr2-8)<4096&&!((target-(u_int)ptr2-8)&15)) {
137 assert((target&3)==0);
138 *ptr2=(*ptr2&0xFFFFF000)|((target-(u_int)ptr2-8)>>4)|0xE00;
140 else *ptr2=(0x7A000000)|(((target-(u_int)ptr2-8)<<6)>>8);
143 assert((ptr[3]&0x0e)==0xa);
144 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
148 // This optionally copies the instruction from the target of the branch into
149 // the space before the branch. Works, but the difference in speed is
150 // usually insignificant.
151 void set_jump_target_fillslot(int addr,u_int target,int copy)
153 u_char *ptr=(u_char *)addr;
154 u_int *ptr2=(u_int *)ptr;
155 assert(!copy||ptr2[-1]==0xe28dd000);
158 assert((target-(u_int)ptr2-8)<4096);
159 *ptr2=(*ptr2&0xFFFFF000)|(target-(u_int)ptr2-8);
162 assert((ptr[3]&0x0e)==0xa);
163 u_int target_insn=*(u_int *)target;
164 if((target_insn&0x0e100000)==0) { // ALU, no immediate, no flags
167 if((target_insn&0x0c100000)==0x04100000) { // Load
170 if(target_insn&0x08000000) {
174 ptr2[-1]=target_insn;
177 *ptr2=(*ptr2&0xFF000000)|(((target-(u_int)ptr2-8)<<6)>>8);
182 add_literal(int addr,int val)
184 assert(literalcount<sizeof(literals)/sizeof(literals[0]));
185 literals[literalcount][0]=addr;
186 literals[literalcount][1]=val;
190 void *kill_pointer(void *stub)
192 int *ptr=(int *)(stub+4);
193 assert((*ptr&0x0ff00000)==0x05900000);
194 u_int offset=*ptr&0xfff;
195 int **l_ptr=(void *)ptr+offset+8;
197 set_jump_target((int)i_ptr,(int)stub);
201 // find where external branch is liked to using addr of it's stub:
202 // get address that insn one after stub loads (dyna_linker arg1),
203 // treat it as a pointer to branch insn,
204 // return addr where that branch jumps to
205 int get_pointer(void *stub)
207 //printf("get_pointer(%x)\n",(int)stub);
208 int *ptr=(int *)(stub+4);
209 assert((*ptr&0x0fff0000)==0x059f0000);
210 u_int offset=*ptr&0xfff;
211 int **l_ptr=(void *)ptr+offset+8;
213 assert((*i_ptr&0x0f000000)==0x0a000000);
214 return (int)i_ptr+((*i_ptr<<8)>>6)+8;
217 // Find the "clean" entry point from a "dirty" entry point
218 // by skipping past the call to verify_code
219 u_int get_clean_addr(int addr)
221 int *ptr=(int *)addr;
227 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
228 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
230 if((*ptr&0xFF000000)==0xea000000) {
231 return (int)ptr+((*ptr<<8)>>6)+8; // follow jump
236 int verify_dirty(int addr)
238 u_int *ptr=(u_int *)addr;
240 // get from literal pool
241 assert((*ptr&0xFFFF0000)==0xe59f0000);
242 u_int offset=*ptr&0xfff;
243 u_int *l_ptr=(void *)ptr+offset+8;
244 u_int source=l_ptr[0];
250 assert((*ptr&0xFFF00000)==0xe3000000);
251 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
252 u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
253 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
256 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
257 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
259 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
260 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
261 unsigned int page=source>>12;
262 unsigned int map_value=memory_map[page];
263 if(map_value>=0x80000000) return 0;
264 while(page<((source+len-1)>>12)) {
265 if((memory_map[++page]<<2)!=(map_value<<2)) return 0;
267 source = source+(map_value<<2);
270 //printf("verify_dirty: %x %x %x\n",source,copy,len);
271 return !memcmp((void *)source,(void *)copy,len);
274 // This doesn't necessarily find all clean entry points, just
275 // guarantees that it's not dirty
276 int isclean(int addr)
279 int *ptr=((u_int *)addr)+4;
281 int *ptr=((u_int *)addr)+6;
283 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
284 if((*ptr&0xFF000000)!=0xeb000000) return 1; // bl instruction
285 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code) return 0;
286 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_vm) return 0;
287 if((int)ptr+((*ptr<<8)>>6)+8==(int)verify_code_ds) return 0;
291 void get_bounds(int addr,u_int *start,u_int *end)
293 u_int *ptr=(u_int *)addr;
295 // get from literal pool
296 assert((*ptr&0xFFFF0000)==0xe59f0000);
297 u_int offset=*ptr&0xfff;
298 u_int *l_ptr=(void *)ptr+offset+8;
299 u_int source=l_ptr[0];
300 //u_int copy=l_ptr[1];
305 assert((*ptr&0xFFF00000)==0xe3000000);
306 u_int source=(ptr[0]&0xFFF)+((ptr[0]>>4)&0xF000)+((ptr[2]<<16)&0xFFF0000)+((ptr[2]<<12)&0xF0000000);
307 //u_int copy=(ptr[1]&0xFFF)+((ptr[1]>>4)&0xF000)+((ptr[3]<<16)&0xFFF0000)+((ptr[3]<<12)&0xF0000000);
308 u_int len=(ptr[4]&0xFFF)+((ptr[4]>>4)&0xF000);
311 if((*ptr&0xFF000000)!=0xeb000000) ptr++;
312 assert((*ptr&0xFF000000)==0xeb000000); // bl instruction
314 u_int verifier=(int)ptr+((signed int)(*ptr<<8)>>6)+8; // get target of bl
315 if(verifier==(u_int)verify_code_vm||verifier==(u_int)verify_code_ds) {
316 if(memory_map[source>>12]>=0x80000000) source = 0;
317 else source = source+(memory_map[source>>12]<<2);
324 /* Register allocation */
326 // Note: registers are allocated clean (unmodified state)
327 // if you intend to modify the register, you must call dirty_reg().
328 void alloc_reg(struct regstat *cur,int i,signed char reg)
331 int preferred_reg = (reg&7);
332 if(reg==CCREG) preferred_reg=HOST_CCREG;
333 if(reg==PTEMP||reg==FTEMP) preferred_reg=12;
335 // Don't allocate unused registers
336 if((cur->u>>reg)&1) return;
338 // see if it's already allocated
339 for(hr=0;hr<HOST_REGS;hr++)
341 if(cur->regmap[hr]==reg) return;
344 // Keep the same mapping if the register was already allocated in a loop
345 preferred_reg = loop_reg(i,reg,preferred_reg);
347 // Try to allocate the preferred register
348 if(cur->regmap[preferred_reg]==-1) {
349 cur->regmap[preferred_reg]=reg;
350 cur->dirty&=~(1<<preferred_reg);
351 cur->isconst&=~(1<<preferred_reg);
354 r=cur->regmap[preferred_reg];
355 if(r<64&&((cur->u>>r)&1)) {
356 cur->regmap[preferred_reg]=reg;
357 cur->dirty&=~(1<<preferred_reg);
358 cur->isconst&=~(1<<preferred_reg);
361 if(r>=64&&((cur->uu>>(r&63))&1)) {
362 cur->regmap[preferred_reg]=reg;
363 cur->dirty&=~(1<<preferred_reg);
364 cur->isconst&=~(1<<preferred_reg);
368 // Clear any unneeded registers
369 // We try to keep the mapping consistent, if possible, because it
370 // makes branches easier (especially loops). So we try to allocate
371 // first (see above) before removing old mappings. If this is not
372 // possible then go ahead and clear out the registers that are no
374 for(hr=0;hr<HOST_REGS;hr++)
379 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
383 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
387 // Try to allocate any available register, but prefer
388 // registers that have not been used recently.
390 for(hr=0;hr<HOST_REGS;hr++) {
391 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
392 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
394 cur->dirty&=~(1<<hr);
395 cur->isconst&=~(1<<hr);
401 // Try to allocate any available register
402 for(hr=0;hr<HOST_REGS;hr++) {
403 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
405 cur->dirty&=~(1<<hr);
406 cur->isconst&=~(1<<hr);
411 // Ok, now we have to evict someone
412 // Pick a register we hopefully won't need soon
413 u_char hsn[MAXREG+1];
414 memset(hsn,10,sizeof(hsn));
416 lsn(hsn,i,&preferred_reg);
417 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
418 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
420 // Don't evict the cycle count at entry points, otherwise the entry
421 // stub will have to write it.
422 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
423 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
426 // Alloc preferred register if available
427 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
428 for(hr=0;hr<HOST_REGS;hr++) {
429 // Evict both parts of a 64-bit register
430 if((cur->regmap[hr]&63)==r) {
432 cur->dirty&=~(1<<hr);
433 cur->isconst&=~(1<<hr);
436 cur->regmap[preferred_reg]=reg;
439 for(r=1;r<=MAXREG;r++)
441 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
442 for(hr=0;hr<HOST_REGS;hr++) {
443 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
444 if(cur->regmap[hr]==r+64) {
446 cur->dirty&=~(1<<hr);
447 cur->isconst&=~(1<<hr);
452 for(hr=0;hr<HOST_REGS;hr++) {
453 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
454 if(cur->regmap[hr]==r) {
456 cur->dirty&=~(1<<hr);
457 cur->isconst&=~(1<<hr);
468 for(r=1;r<=MAXREG;r++)
471 for(hr=0;hr<HOST_REGS;hr++) {
472 if(cur->regmap[hr]==r+64) {
474 cur->dirty&=~(1<<hr);
475 cur->isconst&=~(1<<hr);
479 for(hr=0;hr<HOST_REGS;hr++) {
480 if(cur->regmap[hr]==r) {
482 cur->dirty&=~(1<<hr);
483 cur->isconst&=~(1<<hr);
490 printf("This shouldn't happen (alloc_reg)");exit(1);
493 void alloc_reg64(struct regstat *cur,int i,signed char reg)
495 int preferred_reg = 8+(reg&1);
498 // allocate the lower 32 bits
499 alloc_reg(cur,i,reg);
501 // Don't allocate unused registers
502 if((cur->uu>>reg)&1) return;
504 // see if the upper half is already allocated
505 for(hr=0;hr<HOST_REGS;hr++)
507 if(cur->regmap[hr]==reg+64) return;
510 // Keep the same mapping if the register was already allocated in a loop
511 preferred_reg = loop_reg(i,reg,preferred_reg);
513 // Try to allocate the preferred register
514 if(cur->regmap[preferred_reg]==-1) {
515 cur->regmap[preferred_reg]=reg|64;
516 cur->dirty&=~(1<<preferred_reg);
517 cur->isconst&=~(1<<preferred_reg);
520 r=cur->regmap[preferred_reg];
521 if(r<64&&((cur->u>>r)&1)) {
522 cur->regmap[preferred_reg]=reg|64;
523 cur->dirty&=~(1<<preferred_reg);
524 cur->isconst&=~(1<<preferred_reg);
527 if(r>=64&&((cur->uu>>(r&63))&1)) {
528 cur->regmap[preferred_reg]=reg|64;
529 cur->dirty&=~(1<<preferred_reg);
530 cur->isconst&=~(1<<preferred_reg);
534 // Clear any unneeded registers
535 // We try to keep the mapping consistent, if possible, because it
536 // makes branches easier (especially loops). So we try to allocate
537 // first (see above) before removing old mappings. If this is not
538 // possible then go ahead and clear out the registers that are no
540 for(hr=HOST_REGS-1;hr>=0;hr--)
545 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
549 if((cur->uu>>(r&63))&1) {cur->regmap[hr]=-1;break;}
553 // Try to allocate any available register, but prefer
554 // registers that have not been used recently.
556 for(hr=0;hr<HOST_REGS;hr++) {
557 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
558 if(regs[i-1].regmap[hr]!=rs1[i-1]&®s[i-1].regmap[hr]!=rs2[i-1]&®s[i-1].regmap[hr]!=rt1[i-1]&®s[i-1].regmap[hr]!=rt2[i-1]) {
559 cur->regmap[hr]=reg|64;
560 cur->dirty&=~(1<<hr);
561 cur->isconst&=~(1<<hr);
567 // Try to allocate any available register
568 for(hr=0;hr<HOST_REGS;hr++) {
569 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
570 cur->regmap[hr]=reg|64;
571 cur->dirty&=~(1<<hr);
572 cur->isconst&=~(1<<hr);
577 // Ok, now we have to evict someone
578 // Pick a register we hopefully won't need soon
579 u_char hsn[MAXREG+1];
580 memset(hsn,10,sizeof(hsn));
582 lsn(hsn,i,&preferred_reg);
583 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
584 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
586 // Don't evict the cycle count at entry points, otherwise the entry
587 // stub will have to write it.
588 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
589 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
592 // Alloc preferred register if available
593 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
594 for(hr=0;hr<HOST_REGS;hr++) {
595 // Evict both parts of a 64-bit register
596 if((cur->regmap[hr]&63)==r) {
598 cur->dirty&=~(1<<hr);
599 cur->isconst&=~(1<<hr);
602 cur->regmap[preferred_reg]=reg|64;
605 for(r=1;r<=MAXREG;r++)
607 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
608 for(hr=0;hr<HOST_REGS;hr++) {
609 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
610 if(cur->regmap[hr]==r+64) {
611 cur->regmap[hr]=reg|64;
612 cur->dirty&=~(1<<hr);
613 cur->isconst&=~(1<<hr);
618 for(hr=0;hr<HOST_REGS;hr++) {
619 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
620 if(cur->regmap[hr]==r) {
621 cur->regmap[hr]=reg|64;
622 cur->dirty&=~(1<<hr);
623 cur->isconst&=~(1<<hr);
634 for(r=1;r<=MAXREG;r++)
637 for(hr=0;hr<HOST_REGS;hr++) {
638 if(cur->regmap[hr]==r+64) {
639 cur->regmap[hr]=reg|64;
640 cur->dirty&=~(1<<hr);
641 cur->isconst&=~(1<<hr);
645 for(hr=0;hr<HOST_REGS;hr++) {
646 if(cur->regmap[hr]==r) {
647 cur->regmap[hr]=reg|64;
648 cur->dirty&=~(1<<hr);
649 cur->isconst&=~(1<<hr);
656 printf("This shouldn't happen");exit(1);
659 // Allocate a temporary register. This is done without regard to
660 // dirty status or whether the register we request is on the unneeded list
661 // Note: This will only allocate one register, even if called multiple times
662 void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
665 int preferred_reg = -1;
667 // see if it's already allocated
668 for(hr=0;hr<HOST_REGS;hr++)
670 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
673 // Try to allocate any available register
674 for(hr=HOST_REGS-1;hr>=0;hr--) {
675 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
677 cur->dirty&=~(1<<hr);
678 cur->isconst&=~(1<<hr);
683 // Find an unneeded register
684 for(hr=HOST_REGS-1;hr>=0;hr--)
690 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
692 cur->dirty&=~(1<<hr);
693 cur->isconst&=~(1<<hr);
700 if((cur->uu>>(r&63))&1) {
701 if(i==0||((unneeded_reg_upper[i-1]>>(r&63))&1)) {
703 cur->dirty&=~(1<<hr);
704 cur->isconst&=~(1<<hr);
712 // Ok, now we have to evict someone
713 // Pick a register we hopefully won't need soon
714 // TODO: we might want to follow unconditional jumps here
715 // TODO: get rid of dupe code and make this into a function
716 u_char hsn[MAXREG+1];
717 memset(hsn,10,sizeof(hsn));
719 lsn(hsn,i,&preferred_reg);
720 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
722 // Don't evict the cycle count at entry points, otherwise the entry
723 // stub will have to write it.
724 if(bt[i]&&hsn[CCREG]>2) hsn[CCREG]=2;
725 if(i>1&&hsn[CCREG]>2&&(itype[i-2]==RJUMP||itype[i-2]==UJUMP||itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP)) hsn[CCREG]=2;
728 for(r=1;r<=MAXREG;r++)
730 if(hsn[r]==j&&r!=rs1[i-1]&&r!=rs2[i-1]&&r!=rt1[i-1]&&r!=rt2[i-1]) {
731 for(hr=0;hr<HOST_REGS;hr++) {
732 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
733 if(cur->regmap[hr]==r+64) {
735 cur->dirty&=~(1<<hr);
736 cur->isconst&=~(1<<hr);
741 for(hr=0;hr<HOST_REGS;hr++) {
742 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
743 if(cur->regmap[hr]==r) {
745 cur->dirty&=~(1<<hr);
746 cur->isconst&=~(1<<hr);
757 for(r=1;r<=MAXREG;r++)
760 for(hr=0;hr<HOST_REGS;hr++) {
761 if(cur->regmap[hr]==r+64) {
763 cur->dirty&=~(1<<hr);
764 cur->isconst&=~(1<<hr);
768 for(hr=0;hr<HOST_REGS;hr++) {
769 if(cur->regmap[hr]==r) {
771 cur->dirty&=~(1<<hr);
772 cur->isconst&=~(1<<hr);
779 printf("This shouldn't happen");exit(1);
781 // Allocate a specific ARM register.
782 void alloc_arm_reg(struct regstat *cur,int i,signed char reg,char hr)
787 // see if it's already allocated (and dealloc it)
788 for(n=0;n<HOST_REGS;n++)
790 if(n!=EXCLUDE_REG&&cur->regmap[n]==reg) {
791 dirty=(cur->dirty>>n)&1;
797 cur->dirty&=~(1<<hr);
798 cur->dirty|=dirty<<hr;
799 cur->isconst&=~(1<<hr);
802 // Alloc cycle count into dedicated register
803 alloc_cc(struct regstat *cur,int i)
805 alloc_arm_reg(cur,i,CCREG,HOST_CCREG);
813 char regname[16][4] = {
831 void output_byte(u_char byte)
835 void output_modrm(u_char mod,u_char rm,u_char ext)
840 u_char byte=(mod<<6)|(ext<<3)|rm;
843 void output_sib(u_char scale,u_char index,u_char base)
848 u_char byte=(scale<<6)|(index<<3)|base;
851 void output_w32(u_int word)
853 *((u_int *)out)=word;
856 u_int rd_rn_rm(u_int rd, u_int rn, u_int rm)
861 return((rn<<16)|(rd<<12)|rm);
863 u_int rd_rn_imm_shift(u_int rd, u_int rn, u_int imm, u_int shift)
868 assert((shift&1)==0);
869 return((rn<<16)|(rd<<12)|(((32-shift)&30)<<7)|imm);
871 u_int genimm(u_int imm,u_int *encoded)
879 *encoded=((i&30)<<7)|imm;
882 imm=(imm>>2)|(imm<<30);i-=2;
886 void genimm_checked(u_int imm,u_int *encoded)
888 u_int ret=genimm(imm,encoded);
891 u_int genjmp(u_int addr)
893 int offset=addr-(int)out-8;
894 if(offset<-33554432||offset>=33554432) {
896 printf("genjmp: out of range: %08x\n", offset);
901 return ((u_int)offset>>2)&0xffffff;
904 void emit_mov(int rs,int rt)
906 assem_debug("mov %s,%s\n",regname[rt],regname[rs]);
907 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs));
910 void emit_movs(int rs,int rt)
912 assem_debug("movs %s,%s\n",regname[rt],regname[rs]);
913 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs));
916 void emit_add(int rs1,int rs2,int rt)
918 assem_debug("add %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
919 output_w32(0xe0800000|rd_rn_rm(rt,rs1,rs2));
922 void emit_adds(int rs1,int rs2,int rt)
924 assem_debug("adds %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
925 output_w32(0xe0900000|rd_rn_rm(rt,rs1,rs2));
928 void emit_adcs(int rs1,int rs2,int rt)
930 assem_debug("adcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
931 output_w32(0xe0b00000|rd_rn_rm(rt,rs1,rs2));
934 void emit_sbc(int rs1,int rs2,int rt)
936 assem_debug("sbc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
937 output_w32(0xe0c00000|rd_rn_rm(rt,rs1,rs2));
940 void emit_sbcs(int rs1,int rs2,int rt)
942 assem_debug("sbcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
943 output_w32(0xe0d00000|rd_rn_rm(rt,rs1,rs2));
946 void emit_neg(int rs, int rt)
948 assem_debug("rsb %s,%s,#0\n",regname[rt],regname[rs]);
949 output_w32(0xe2600000|rd_rn_rm(rt,rs,0));
952 void emit_negs(int rs, int rt)
954 assem_debug("rsbs %s,%s,#0\n",regname[rt],regname[rs]);
955 output_w32(0xe2700000|rd_rn_rm(rt,rs,0));
958 void emit_sub(int rs1,int rs2,int rt)
960 assem_debug("sub %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
961 output_w32(0xe0400000|rd_rn_rm(rt,rs1,rs2));
964 void emit_subs(int rs1,int rs2,int rt)
966 assem_debug("subs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
967 output_w32(0xe0500000|rd_rn_rm(rt,rs1,rs2));
970 void emit_zeroreg(int rt)
972 assem_debug("mov %s,#0\n",regname[rt]);
973 output_w32(0xe3a00000|rd_rn_rm(rt,0,0));
976 void emit_loadlp(u_int imm,u_int rt)
978 add_literal((int)out,imm);
979 assem_debug("ldr %s,pc+? [=%x]\n",regname[rt],imm);
980 output_w32(0xe5900000|rd_rn_rm(rt,15,0));
982 void emit_movw(u_int imm,u_int rt)
985 assem_debug("movw %s,#%d (0x%x)\n",regname[rt],imm,imm);
986 output_w32(0xe3000000|rd_rn_rm(rt,0,0)|(imm&0xfff)|((imm<<4)&0xf0000));
988 void emit_movt(u_int imm,u_int rt)
990 assem_debug("movt %s,#%d (0x%x)\n",regname[rt],imm&0xffff0000,imm&0xffff0000);
991 output_w32(0xe3400000|rd_rn_rm(rt,0,0)|((imm>>16)&0xfff)|((imm>>12)&0xf0000));
993 void emit_movimm(u_int imm,u_int rt)
996 if(genimm(imm,&armval)) {
997 assem_debug("mov %s,#%d\n",regname[rt],imm);
998 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
999 }else if(genimm(~imm,&armval)) {
1000 assem_debug("mvn %s,#%d\n",regname[rt],imm);
1001 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
1002 }else if(imm<65536) {
1004 assem_debug("mov %s,#%d\n",regname[rt],imm&0xFF00);
1005 output_w32(0xe3a00000|rd_rn_imm_shift(rt,0,imm>>8,8));
1006 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1007 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1013 emit_loadlp(imm,rt);
1015 emit_movw(imm&0x0000FFFF,rt);
1016 emit_movt(imm&0xFFFF0000,rt);
1020 void emit_pcreladdr(u_int rt)
1022 assem_debug("add %s,pc,#?\n",regname[rt]);
1023 output_w32(0xe2800000|rd_rn_rm(rt,15,0));
1026 void emit_loadreg(int r, int hr)
1030 printf("64bit load in 32bit mode!\n");
1038 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1039 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1040 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1041 if(r==CCREG) addr=(int)&cycle_count;
1042 if(r==CSREG) addr=(int)&Status;
1043 if(r==FSREG) addr=(int)&FCR31;
1044 if(r==INVCP) addr=(int)&invc_ptr;
1045 u_int offset = addr-(u_int)&dynarec_local;
1046 assert(offset<4096);
1047 assem_debug("ldr %s,fp+%d\n",regname[hr],offset);
1048 output_w32(0xe5900000|rd_rn_rm(hr,FP,0)|offset);
1051 void emit_storereg(int r, int hr)
1055 printf("64bit store in 32bit mode!\n");
1060 int addr=((int)reg)+((r&63)<<REG_SHIFT)+((r&64)>>4);
1061 if((r&63)==HIREG) addr=(int)&hi+((r&64)>>4);
1062 if((r&63)==LOREG) addr=(int)&lo+((r&64)>>4);
1063 if(r==CCREG) addr=(int)&cycle_count;
1064 if(r==FSREG) addr=(int)&FCR31;
1065 u_int offset = addr-(u_int)&dynarec_local;
1066 assert(offset<4096);
1067 assem_debug("str %s,fp+%d\n",regname[hr],offset);
1068 output_w32(0xe5800000|rd_rn_rm(hr,FP,0)|offset);
1071 void emit_test(int rs, int rt)
1073 assem_debug("tst %s,%s\n",regname[rs],regname[rt]);
1074 output_w32(0xe1100000|rd_rn_rm(0,rs,rt));
1077 void emit_testimm(int rs,int imm)
1080 assem_debug("tst %s,#%d\n",regname[rs],imm);
1081 genimm_checked(imm,&armval);
1082 output_w32(0xe3100000|rd_rn_rm(0,rs,0)|armval);
1085 void emit_testeqimm(int rs,int imm)
1088 assem_debug("tsteq %s,$%d\n",regname[rs],imm);
1089 genimm_checked(imm,&armval);
1090 output_w32(0x03100000|rd_rn_rm(0,rs,0)|armval);
1093 void emit_not(int rs,int rt)
1095 assem_debug("mvn %s,%s\n",regname[rt],regname[rs]);
1096 output_w32(0xe1e00000|rd_rn_rm(rt,0,rs));
1099 void emit_mvnmi(int rs,int rt)
1101 assem_debug("mvnmi %s,%s\n",regname[rt],regname[rs]);
1102 output_w32(0x41e00000|rd_rn_rm(rt,0,rs));
1105 void emit_and(u_int rs1,u_int rs2,u_int rt)
1107 assem_debug("and %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1108 output_w32(0xe0000000|rd_rn_rm(rt,rs1,rs2));
1111 void emit_or(u_int rs1,u_int rs2,u_int rt)
1113 assem_debug("orr %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1114 output_w32(0xe1800000|rd_rn_rm(rt,rs1,rs2));
1116 void emit_or_and_set_flags(int rs1,int rs2,int rt)
1118 assem_debug("orrs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1119 output_w32(0xe1900000|rd_rn_rm(rt,rs1,rs2));
1122 void emit_orrshl_imm(u_int rs,u_int imm,u_int rt)
1127 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs],imm);
1128 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|(imm<<7));
1131 void emit_orrshr_imm(u_int rs,u_int imm,u_int rt)
1136 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs],imm);
1137 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs)|(imm<<7));
1140 void emit_xor(u_int rs1,u_int rs2,u_int rt)
1142 assem_debug("eor %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1143 output_w32(0xe0200000|rd_rn_rm(rt,rs1,rs2));
1146 void emit_addimm(u_int rs,int imm,u_int rt)
1152 if(genimm(imm,&armval)) {
1153 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm);
1154 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
1155 }else if(genimm(-imm,&armval)) {
1156 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-imm);
1157 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
1160 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],(-imm)&0xFF00);
1161 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1162 output_w32(0xe2400000|rd_rn_imm_shift(rt,rs,(-imm)>>8,8));
1163 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1166 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1167 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1168 output_w32(0xe2800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1169 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1172 else if(rs!=rt) emit_mov(rs,rt);
1175 void emit_addimm_and_set_flags(int imm,int rt)
1177 assert(imm>-65536&&imm<65536);
1179 if(genimm(imm,&armval)) {
1180 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm);
1181 output_w32(0xe2900000|rd_rn_rm(rt,rt,0)|armval);
1182 }else if(genimm(-imm,&armval)) {
1183 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],imm);
1184 output_w32(0xe2500000|rd_rn_rm(rt,rt,0)|armval);
1186 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF00);
1187 assem_debug("subs %s,%s,#%d\n",regname[rt],regname[rt],(-imm)&0xFF);
1188 output_w32(0xe2400000|rd_rn_imm_shift(rt,rt,(-imm)>>8,8));
1189 output_w32(0xe2500000|rd_rn_imm_shift(rt,rt,(-imm)&0xff,0));
1191 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF00);
1192 assem_debug("adds %s,%s,#%d\n",regname[rt],regname[rt],imm&0xFF);
1193 output_w32(0xe2800000|rd_rn_imm_shift(rt,rt,imm>>8,8));
1194 output_w32(0xe2900000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1197 void emit_addimm_no_flags(u_int imm,u_int rt)
1199 emit_addimm(rt,imm,rt);
1202 void emit_addnop(u_int r)
1205 assem_debug("add %s,%s,#0 (nop)\n",regname[r],regname[r]);
1206 output_w32(0xe2800000|rd_rn_rm(r,r,0));
1209 void emit_adcimm(u_int rs,int imm,u_int rt)
1212 genimm_checked(imm,&armval);
1213 assem_debug("adc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1214 output_w32(0xe2a00000|rd_rn_rm(rt,rs,0)|armval);
1216 /*void emit_sbcimm(int imm,u_int rt)
1219 genimm_checked(imm,&armval);
1220 assem_debug("sbc %s,%s,#%d\n",regname[rt],regname[rt],imm);
1221 output_w32(0xe2c00000|rd_rn_rm(rt,rt,0)|armval);
1223 void emit_sbbimm(int imm,u_int rt)
1225 assem_debug("sbb $%d,%%%s\n",imm,regname[rt]);
1227 if(imm<128&&imm>=-128) {
1229 output_modrm(3,rt,3);
1235 output_modrm(3,rt,3);
1239 void emit_rscimm(int rs,int imm,u_int rt)
1243 genimm_checked(imm,&armval);
1244 assem_debug("rsc %s,%s,#%d\n",regname[rt],regname[rs],imm);
1245 output_w32(0xe2e00000|rd_rn_rm(rt,rs,0)|armval);
1248 void emit_addimm64_32(int rsh,int rsl,int imm,int rth,int rtl)
1250 // TODO: if(genimm(imm,&armval)) ...
1252 emit_movimm(imm,HOST_TEMPREG);
1253 emit_adds(HOST_TEMPREG,rsl,rtl);
1254 emit_adcimm(rsh,0,rth);
1257 void emit_sbb(int rs1,int rs2)
1259 assem_debug("sbb %%%s,%%%s\n",regname[rs2],regname[rs1]);
1261 output_modrm(3,rs1,rs2);
1264 void emit_andimm(int rs,int imm,int rt)
1269 }else if(genimm(imm,&armval)) {
1270 assem_debug("and %s,%s,#%d\n",regname[rt],regname[rs],imm);
1271 output_w32(0xe2000000|rd_rn_rm(rt,rs,0)|armval);
1272 }else if(genimm(~imm,&armval)) {
1273 assem_debug("bic %s,%s,#%d\n",regname[rt],regname[rs],imm);
1274 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|armval);
1275 }else if(imm==65535) {
1277 assem_debug("bic %s,%s,#FF000000\n",regname[rt],regname[rs]);
1278 output_w32(0xe3c00000|rd_rn_rm(rt,rs,0)|0x4FF);
1279 assem_debug("bic %s,%s,#00FF0000\n",regname[rt],regname[rt]);
1280 output_w32(0xe3c00000|rd_rn_rm(rt,rt,0)|0x8FF);
1282 assem_debug("uxth %s,%s\n",regname[rt],regname[rs]);
1283 output_w32(0xe6ff0070|rd_rn_rm(rt,0,rs));
1286 assert(imm>0&&imm<65535);
1288 assem_debug("mov r14,#%d\n",imm&0xFF00);
1289 output_w32(0xe3a00000|rd_rn_imm_shift(HOST_TEMPREG,0,imm>>8,8));
1290 assem_debug("add r14,r14,#%d\n",imm&0xFF);
1291 output_w32(0xe2800000|rd_rn_imm_shift(HOST_TEMPREG,HOST_TEMPREG,imm&0xff,0));
1293 emit_movw(imm,HOST_TEMPREG);
1295 assem_debug("and %s,%s,r14\n",regname[rt],regname[rs]);
1296 output_w32(0xe0000000|rd_rn_rm(rt,rs,HOST_TEMPREG));
1300 void emit_orimm(int rs,int imm,int rt)
1304 if(rs!=rt) emit_mov(rs,rt);
1305 }else if(genimm(imm,&armval)) {
1306 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1307 output_w32(0xe3800000|rd_rn_rm(rt,rs,0)|armval);
1309 assert(imm>0&&imm<65536);
1310 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1311 assem_debug("orr %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1312 output_w32(0xe3800000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1313 output_w32(0xe3800000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1317 void emit_xorimm(int rs,int imm,int rt)
1321 if(rs!=rt) emit_mov(rs,rt);
1322 }else if(genimm(imm,&armval)) {
1323 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm);
1324 output_w32(0xe2200000|rd_rn_rm(rt,rs,0)|armval);
1326 assert(imm>0&&imm<65536);
1327 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF00);
1328 assem_debug("eor %s,%s,#%d\n",regname[rt],regname[rs],imm&0xFF);
1329 output_w32(0xe2200000|rd_rn_imm_shift(rt,rs,imm>>8,8));
1330 output_w32(0xe2200000|rd_rn_imm_shift(rt,rt,imm&0xff,0));
1334 void emit_shlimm(int rs,u_int imm,int rt)
1339 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1340 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1343 void emit_lsls_imm(int rs,int imm,int rt)
1347 assem_debug("lsls %s,%s,#%d\n",regname[rt],regname[rs],imm);
1348 output_w32(0xe1b00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1351 void emit_shrimm(int rs,u_int imm,int rt)
1355 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1356 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
1359 void emit_sarimm(int rs,u_int imm,int rt)
1363 assem_debug("asr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1364 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x40|(imm<<7));
1367 void emit_rorimm(int rs,u_int imm,int rt)
1371 assem_debug("ror %s,%s,#%d\n",regname[rt],regname[rs],imm);
1372 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x60|(imm<<7));
1375 void emit_shldimm(int rs,int rs2,u_int imm,int rt)
1377 assem_debug("shld %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1381 assem_debug("lsl %s,%s,#%d\n",regname[rt],regname[rs],imm);
1382 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|(imm<<7));
1383 assem_debug("orr %s,%s,%s,lsr #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1384 output_w32(0xe1800020|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1387 void emit_shrdimm(int rs,int rs2,u_int imm,int rt)
1389 assem_debug("shrd %%%s,%%%s,%d\n",regname[rt],regname[rs2],imm);
1393 assem_debug("lsr %s,%s,#%d\n",regname[rt],regname[rs],imm);
1394 output_w32(0xe1a00020|rd_rn_rm(rt,0,rs)|(imm<<7));
1395 assem_debug("orr %s,%s,%s,lsl #%d\n",regname[rt],regname[rt],regname[rs2],32-imm);
1396 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs2)|((32-imm)<<7));
1399 void emit_signextend16(int rs,int rt)
1402 emit_shlimm(rs,16,rt);
1403 emit_sarimm(rt,16,rt);
1405 assem_debug("sxth %s,%s\n",regname[rt],regname[rs]);
1406 output_w32(0xe6bf0070|rd_rn_rm(rt,0,rs));
1410 void emit_signextend8(int rs,int rt)
1413 emit_shlimm(rs,24,rt);
1414 emit_sarimm(rt,24,rt);
1416 assem_debug("sxtb %s,%s\n",regname[rt],regname[rs]);
1417 output_w32(0xe6af0070|rd_rn_rm(rt,0,rs));
1421 void emit_shl(u_int rs,u_int shift,u_int rt)
1427 assem_debug("lsl %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1428 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x10|(shift<<8));
1430 void emit_shr(u_int rs,u_int shift,u_int rt)
1435 assem_debug("lsr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1436 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x30|(shift<<8));
1438 void emit_sar(u_int rs,u_int shift,u_int rt)
1443 assem_debug("asr %s,%s,%s\n",regname[rt],regname[rs],regname[shift]);
1444 output_w32(0xe1a00000|rd_rn_rm(rt,0,rs)|0x50|(shift<<8));
1446 void emit_shlcl(int r)
1448 assem_debug("shl %%%s,%%cl\n",regname[r]);
1451 void emit_shrcl(int r)
1453 assem_debug("shr %%%s,%%cl\n",regname[r]);
1456 void emit_sarcl(int r)
1458 assem_debug("sar %%%s,%%cl\n",regname[r]);
1462 void emit_shldcl(int r1,int r2)
1464 assem_debug("shld %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1467 void emit_shrdcl(int r1,int r2)
1469 assem_debug("shrd %%%s,%%%s,%%cl\n",regname[r1],regname[r2]);
1472 void emit_orrshl(u_int rs,u_int shift,u_int rt)
1477 assem_debug("orr %s,%s,%s,lsl %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1478 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x10|(shift<<8));
1480 void emit_orrshr(u_int rs,u_int shift,u_int rt)
1485 assem_debug("orr %s,%s,%s,lsr %s\n",regname[rt],regname[rt],regname[rs],regname[shift]);
1486 output_w32(0xe1800000|rd_rn_rm(rt,rt,rs)|0x30|(shift<<8));
1489 void emit_cmpimm(int rs,int imm)
1492 if(genimm(imm,&armval)) {
1493 assem_debug("cmp %s,#%d\n",regname[rs],imm);
1494 output_w32(0xe3500000|rd_rn_rm(0,rs,0)|armval);
1495 }else if(genimm(-imm,&armval)) {
1496 assem_debug("cmn %s,#%d\n",regname[rs],imm);
1497 output_w32(0xe3700000|rd_rn_rm(0,rs,0)|armval);
1501 emit_movimm(imm,HOST_TEMPREG);
1503 emit_movw(imm,HOST_TEMPREG);
1505 assem_debug("cmp %s,r14\n",regname[rs]);
1506 output_w32(0xe1500000|rd_rn_rm(0,rs,HOST_TEMPREG));
1510 emit_movimm(-imm,HOST_TEMPREG);
1512 emit_movw(-imm,HOST_TEMPREG);
1514 assem_debug("cmn %s,r14\n",regname[rs]);
1515 output_w32(0xe1700000|rd_rn_rm(0,rs,HOST_TEMPREG));
1519 void emit_cmovne(u_int *addr,int rt)
1521 assem_debug("cmovne %x,%%%s",(int)addr,regname[rt]);
1524 void emit_cmovl(u_int *addr,int rt)
1526 assem_debug("cmovl %x,%%%s",(int)addr,regname[rt]);
1529 void emit_cmovs(u_int *addr,int rt)
1531 assem_debug("cmovs %x,%%%s",(int)addr,regname[rt]);
1534 void emit_cmovne_imm(int imm,int rt)
1536 assem_debug("movne %s,#%d\n",regname[rt],imm);
1538 genimm_checked(imm,&armval);
1539 output_w32(0x13a00000|rd_rn_rm(rt,0,0)|armval);
1541 void emit_cmovl_imm(int imm,int rt)
1543 assem_debug("movlt %s,#%d\n",regname[rt],imm);
1545 genimm_checked(imm,&armval);
1546 output_w32(0xb3a00000|rd_rn_rm(rt,0,0)|armval);
1548 void emit_cmovb_imm(int imm,int rt)
1550 assem_debug("movcc %s,#%d\n",regname[rt],imm);
1552 genimm_checked(imm,&armval);
1553 output_w32(0x33a00000|rd_rn_rm(rt,0,0)|armval);
1555 void emit_cmovs_imm(int imm,int rt)
1557 assem_debug("movmi %s,#%d\n",regname[rt],imm);
1559 genimm_checked(imm,&armval);
1560 output_w32(0x43a00000|rd_rn_rm(rt,0,0)|armval);
1562 void emit_cmove_reg(int rs,int rt)
1564 assem_debug("moveq %s,%s\n",regname[rt],regname[rs]);
1565 output_w32(0x01a00000|rd_rn_rm(rt,0,rs));
1567 void emit_cmovne_reg(int rs,int rt)
1569 assem_debug("movne %s,%s\n",regname[rt],regname[rs]);
1570 output_w32(0x11a00000|rd_rn_rm(rt,0,rs));
1572 void emit_cmovl_reg(int rs,int rt)
1574 assem_debug("movlt %s,%s\n",regname[rt],regname[rs]);
1575 output_w32(0xb1a00000|rd_rn_rm(rt,0,rs));
1577 void emit_cmovs_reg(int rs,int rt)
1579 assem_debug("movmi %s,%s\n",regname[rt],regname[rs]);
1580 output_w32(0x41a00000|rd_rn_rm(rt,0,rs));
1583 void emit_slti32(int rs,int imm,int rt)
1585 if(rs!=rt) emit_zeroreg(rt);
1586 emit_cmpimm(rs,imm);
1587 if(rs==rt) emit_movimm(0,rt);
1588 emit_cmovl_imm(1,rt);
1590 void emit_sltiu32(int rs,int imm,int rt)
1592 if(rs!=rt) emit_zeroreg(rt);
1593 emit_cmpimm(rs,imm);
1594 if(rs==rt) emit_movimm(0,rt);
1595 emit_cmovb_imm(1,rt);
1597 void emit_slti64_32(int rsh,int rsl,int imm,int rt)
1600 emit_slti32(rsl,imm,rt);
1604 emit_cmovne_imm(0,rt);
1605 emit_cmovs_imm(1,rt);
1609 emit_cmpimm(rsh,-1);
1610 emit_cmovne_imm(0,rt);
1611 emit_cmovl_imm(1,rt);
1614 void emit_sltiu64_32(int rsh,int rsl,int imm,int rt)
1617 emit_sltiu32(rsl,imm,rt);
1621 emit_cmovne_imm(0,rt);
1625 emit_cmpimm(rsh,-1);
1626 emit_cmovne_imm(1,rt);
1630 void emit_cmp(int rs,int rt)
1632 assem_debug("cmp %s,%s\n",regname[rs],regname[rt]);
1633 output_w32(0xe1500000|rd_rn_rm(0,rs,rt));
1635 void emit_set_gz32(int rs, int rt)
1637 //assem_debug("set_gz32\n");
1640 emit_cmovl_imm(0,rt);
1642 void emit_set_nz32(int rs, int rt)
1644 //assem_debug("set_nz32\n");
1645 if(rs!=rt) emit_movs(rs,rt);
1646 else emit_test(rs,rs);
1647 emit_cmovne_imm(1,rt);
1649 void emit_set_gz64_32(int rsh, int rsl, int rt)
1651 //assem_debug("set_gz64\n");
1652 emit_set_gz32(rsl,rt);
1654 emit_cmovne_imm(1,rt);
1655 emit_cmovs_imm(0,rt);
1657 void emit_set_nz64_32(int rsh, int rsl, int rt)
1659 //assem_debug("set_nz64\n");
1660 emit_or_and_set_flags(rsh,rsl,rt);
1661 emit_cmovne_imm(1,rt);
1663 void emit_set_if_less32(int rs1, int rs2, int rt)
1665 //assem_debug("set if less (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1666 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1668 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1669 emit_cmovl_imm(1,rt);
1671 void emit_set_if_carry32(int rs1, int rs2, int rt)
1673 //assem_debug("set if carry (%%%s,%%%s),%%%s\n",regname[rs1],regname[rs2],regname[rt]);
1674 if(rs1!=rt&&rs2!=rt) emit_zeroreg(rt);
1676 if(rs1==rt||rs2==rt) emit_movimm(0,rt);
1677 emit_cmovb_imm(1,rt);
1679 void emit_set_if_less64_32(int u1, int l1, int u2, int l2, int rt)
1681 //assem_debug("set if less64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1686 emit_sbcs(u1,u2,HOST_TEMPREG);
1687 emit_cmovl_imm(1,rt);
1689 void emit_set_if_carry64_32(int u1, int l1, int u2, int l2, int rt)
1691 //assem_debug("set if carry64 (%%%s,%%%s,%%%s,%%%s),%%%s\n",regname[u1],regname[l1],regname[u2],regname[l2],regname[rt]);
1696 emit_sbcs(u1,u2,HOST_TEMPREG);
1697 emit_cmovb_imm(1,rt);
1700 void emit_call(int a)
1702 assem_debug("bl %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1703 u_int offset=genjmp(a);
1704 output_w32(0xeb000000|offset);
1706 void emit_jmp(int a)
1708 assem_debug("b %x (%x+%x)\n",a,(int)out,a-(int)out-8);
1709 u_int offset=genjmp(a);
1710 output_w32(0xea000000|offset);
1712 void emit_jne(int a)
1714 assem_debug("bne %x\n",a);
1715 u_int offset=genjmp(a);
1716 output_w32(0x1a000000|offset);
1718 void emit_jeq(int a)
1720 assem_debug("beq %x\n",a);
1721 u_int offset=genjmp(a);
1722 output_w32(0x0a000000|offset);
1726 assem_debug("bmi %x\n",a);
1727 u_int offset=genjmp(a);
1728 output_w32(0x4a000000|offset);
1730 void emit_jns(int a)
1732 assem_debug("bpl %x\n",a);
1733 u_int offset=genjmp(a);
1734 output_w32(0x5a000000|offset);
1738 assem_debug("blt %x\n",a);
1739 u_int offset=genjmp(a);
1740 output_w32(0xba000000|offset);
1742 void emit_jge(int a)
1744 assem_debug("bge %x\n",a);
1745 u_int offset=genjmp(a);
1746 output_w32(0xaa000000|offset);
1748 void emit_jno(int a)
1750 assem_debug("bvc %x\n",a);
1751 u_int offset=genjmp(a);
1752 output_w32(0x7a000000|offset);
1756 assem_debug("bcs %x\n",a);
1757 u_int offset=genjmp(a);
1758 output_w32(0x2a000000|offset);
1760 void emit_jcc(int a)
1762 assem_debug("bcc %x\n",a);
1763 u_int offset=genjmp(a);
1764 output_w32(0x3a000000|offset);
1767 void emit_pushimm(int imm)
1769 assem_debug("push $%x\n",imm);
1774 assem_debug("pusha\n");
1779 assem_debug("popa\n");
1782 void emit_pushreg(u_int r)
1784 assem_debug("push %%%s\n",regname[r]);
1787 void emit_popreg(u_int r)
1789 assem_debug("pop %%%s\n",regname[r]);
1792 void emit_callreg(u_int r)
1795 assem_debug("blx %s\n",regname[r]);
1796 output_w32(0xe12fff30|r);
1798 void emit_jmpreg(u_int r)
1800 assem_debug("mov pc,%s\n",regname[r]);
1801 output_w32(0xe1a00000|rd_rn_rm(15,0,r));
1804 void emit_readword_indexed(int offset, int rs, int rt)
1806 assert(offset>-4096&&offset<4096);
1807 assem_debug("ldr %s,%s+%d\n",regname[rt],regname[rs],offset);
1809 output_w32(0xe5900000|rd_rn_rm(rt,rs,0)|offset);
1811 output_w32(0xe5100000|rd_rn_rm(rt,rs,0)|(-offset));
1814 void emit_readword_dualindexedx4(int rs1, int rs2, int rt)
1816 assem_debug("ldr %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1817 output_w32(0xe7900000|rd_rn_rm(rt,rs1,rs2)|0x100);
1819 void emit_ldrcc_dualindexed(int rs1, int rs2, int rt)
1821 assem_debug("ldrcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1822 output_w32(0x37900000|rd_rn_rm(rt,rs1,rs2));
1824 void emit_ldrccb_dualindexed(int rs1, int rs2, int rt)
1826 assem_debug("ldrccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1827 output_w32(0x37d00000|rd_rn_rm(rt,rs1,rs2));
1829 void emit_ldrccsb_dualindexed(int rs1, int rs2, int rt)
1831 assem_debug("ldrccsb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1832 output_w32(0x319000d0|rd_rn_rm(rt,rs1,rs2));
1834 void emit_ldrcch_dualindexed(int rs1, int rs2, int rt)
1836 assem_debug("ldrcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1837 output_w32(0x319000b0|rd_rn_rm(rt,rs1,rs2));
1839 void emit_ldrccsh_dualindexed(int rs1, int rs2, int rt)
1841 assem_debug("ldrccsh %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
1842 output_w32(0x319000f0|rd_rn_rm(rt,rs1,rs2));
1844 void emit_readword_indexed_tlb(int addr, int rs, int map, int rt)
1846 if(map<0) emit_readword_indexed(addr, rs, rt);
1849 emit_readword_dualindexedx4(rs, map, rt);
1852 void emit_readdword_indexed_tlb(int addr, int rs, int map, int rh, int rl)
1855 if(rh>=0) emit_readword_indexed(addr, rs, rh);
1856 emit_readword_indexed(addr+4, rs, rl);
1859 if(rh>=0) emit_readword_indexed_tlb(addr, rs, map, rh);
1860 emit_addimm(map,1,map);
1861 emit_readword_indexed_tlb(addr, rs, map, rl);
1864 void emit_movsbl_indexed(int offset, int rs, int rt)
1866 assert(offset>-256&&offset<256);
1867 assem_debug("ldrsb %s,%s+%d\n",regname[rt],regname[rs],offset);
1869 output_w32(0xe1d000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1871 output_w32(0xe15000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1874 void emit_movsbl_indexed_tlb(int addr, int rs, int map, int rt)
1876 if(map<0) emit_movsbl_indexed(addr, rs, rt);
1879 emit_shlimm(map,2,map);
1880 assem_debug("ldrsb %s,%s+%s\n",regname[rt],regname[rs],regname[map]);
1881 output_w32(0xe19000d0|rd_rn_rm(rt,rs,map));
1883 assert(addr>-256&&addr<256);
1884 assem_debug("add %s,%s,%s,lsl #2\n",regname[rt],regname[rs],regname[map]);
1885 output_w32(0xe0800000|rd_rn_rm(rt,rs,map)|(2<<7));
1886 emit_movsbl_indexed(addr, rt, rt);
1890 void emit_movswl_indexed(int offset, int rs, int rt)
1892 assert(offset>-256&&offset<256);
1893 assem_debug("ldrsh %s,%s+%d\n",regname[rt],regname[rs],offset);
1895 output_w32(0xe1d000f0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1897 output_w32(0xe15000f0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1900 void emit_movzbl_indexed(int offset, int rs, int rt)
1902 assert(offset>-4096&&offset<4096);
1903 assem_debug("ldrb %s,%s+%d\n",regname[rt],regname[rs],offset);
1905 output_w32(0xe5d00000|rd_rn_rm(rt,rs,0)|offset);
1907 output_w32(0xe5500000|rd_rn_rm(rt,rs,0)|(-offset));
1910 void emit_movzbl_dualindexedx4(int rs1, int rs2, int rt)
1912 assem_debug("ldrb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
1913 output_w32(0xe7d00000|rd_rn_rm(rt,rs1,rs2)|0x100);
1915 void emit_movzbl_indexed_tlb(int addr, int rs, int map, int rt)
1917 if(map<0) emit_movzbl_indexed(addr, rs, rt);
1920 emit_movzbl_dualindexedx4(rs, map, rt);
1922 emit_addimm(rs,addr,rt);
1923 emit_movzbl_dualindexedx4(rt, map, rt);
1927 void emit_movzwl_indexed(int offset, int rs, int rt)
1929 assert(offset>-256&&offset<256);
1930 assem_debug("ldrh %s,%s+%d\n",regname[rt],regname[rs],offset);
1932 output_w32(0xe1d000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1934 output_w32(0xe15000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1937 static void emit_ldrd(int offset, int rs, int rt)
1939 assert(offset>-256&&offset<256);
1940 assem_debug("ldrd %s,%s+%d\n",regname[rt],regname[rs],offset);
1942 output_w32(0xe1c000d0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
1944 output_w32(0xe14000d0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
1947 void emit_readword(int addr, int rt)
1949 u_int offset = addr-(u_int)&dynarec_local;
1950 assert(offset<4096);
1951 assem_debug("ldr %s,fp+%d\n",regname[rt],offset);
1952 output_w32(0xe5900000|rd_rn_rm(rt,FP,0)|offset);
1954 void emit_movsbl(int addr, int rt)
1956 u_int offset = addr-(u_int)&dynarec_local;
1958 assem_debug("ldrsb %s,fp+%d\n",regname[rt],offset);
1959 output_w32(0xe1d000d0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1961 void emit_movswl(int addr, int rt)
1963 u_int offset = addr-(u_int)&dynarec_local;
1965 assem_debug("ldrsh %s,fp+%d\n",regname[rt],offset);
1966 output_w32(0xe1d000f0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1968 void emit_movzbl(int addr, int rt)
1970 u_int offset = addr-(u_int)&dynarec_local;
1971 assert(offset<4096);
1972 assem_debug("ldrb %s,fp+%d\n",regname[rt],offset);
1973 output_w32(0xe5d00000|rd_rn_rm(rt,FP,0)|offset);
1975 void emit_movzwl(int addr, int rt)
1977 u_int offset = addr-(u_int)&dynarec_local;
1979 assem_debug("ldrh %s,fp+%d\n",regname[rt],offset);
1980 output_w32(0xe1d000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
1982 void emit_movzwl_reg(int rs, int rt)
1984 assem_debug("movzwl %%%s,%%%s\n",regname[rs]+1,regname[rt]);
1988 void emit_xchg(int rs, int rt)
1990 assem_debug("xchg %%%s,%%%s\n",regname[rs],regname[rt]);
1993 void emit_writeword_indexed(int rt, int offset, int rs)
1995 assert(offset>-4096&&offset<4096);
1996 assem_debug("str %s,%s+%d\n",regname[rt],regname[rs],offset);
1998 output_w32(0xe5800000|rd_rn_rm(rt,rs,0)|offset);
2000 output_w32(0xe5000000|rd_rn_rm(rt,rs,0)|(-offset));
2003 void emit_writeword_dualindexedx4(int rt, int rs1, int rs2)
2005 assem_debug("str %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2006 output_w32(0xe7800000|rd_rn_rm(rt,rs1,rs2)|0x100);
2008 void emit_writeword_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2010 if(map<0) emit_writeword_indexed(rt, addr, rs);
2013 emit_writeword_dualindexedx4(rt, rs, map);
2016 void emit_writedword_indexed_tlb(int rh, int rl, int addr, int rs, int map, int temp)
2019 if(rh>=0) emit_writeword_indexed(rh, addr, rs);
2020 emit_writeword_indexed(rl, addr+4, rs);
2023 if(temp!=rs) emit_addimm(map,1,temp);
2024 emit_writeword_indexed_tlb(rh, addr, rs, map, temp);
2025 if(temp!=rs) emit_writeword_indexed_tlb(rl, addr, rs, temp, temp);
2027 emit_addimm(rs,4,rs);
2028 emit_writeword_indexed_tlb(rl, addr, rs, map, temp);
2032 void emit_writehword_indexed(int rt, int offset, int rs)
2034 assert(offset>-256&&offset<256);
2035 assem_debug("strh %s,%s+%d\n",regname[rt],regname[rs],offset);
2037 output_w32(0xe1c000b0|rd_rn_rm(rt,rs,0)|((offset<<4)&0xf00)|(offset&0xf));
2039 output_w32(0xe14000b0|rd_rn_rm(rt,rs,0)|(((-offset)<<4)&0xf00)|((-offset)&0xf));
2042 void emit_writebyte_indexed(int rt, int offset, int rs)
2044 assert(offset>-4096&&offset<4096);
2045 assem_debug("strb %s,%s+%d\n",regname[rt],regname[rs],offset);
2047 output_w32(0xe5c00000|rd_rn_rm(rt,rs,0)|offset);
2049 output_w32(0xe5400000|rd_rn_rm(rt,rs,0)|(-offset));
2052 void emit_writebyte_dualindexedx4(int rt, int rs1, int rs2)
2054 assem_debug("strb %s,%s,%s lsl #2\n",regname[rt],regname[rs1],regname[rs2]);
2055 output_w32(0xe7c00000|rd_rn_rm(rt,rs1,rs2)|0x100);
2057 void emit_writebyte_indexed_tlb(int rt, int addr, int rs, int map, int temp)
2059 if(map<0) emit_writebyte_indexed(rt, addr, rs);
2062 emit_writebyte_dualindexedx4(rt, rs, map);
2064 emit_addimm(rs,addr,temp);
2065 emit_writebyte_dualindexedx4(rt, temp, map);
2069 void emit_strcc_dualindexed(int rs1, int rs2, int rt)
2071 assem_debug("strcc %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2072 output_w32(0x37800000|rd_rn_rm(rt,rs1,rs2));
2074 void emit_strccb_dualindexed(int rs1, int rs2, int rt)
2076 assem_debug("strccb %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2077 output_w32(0x37c00000|rd_rn_rm(rt,rs1,rs2));
2079 void emit_strcch_dualindexed(int rs1, int rs2, int rt)
2081 assem_debug("strcch %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2082 output_w32(0x318000b0|rd_rn_rm(rt,rs1,rs2));
2084 void emit_writeword(int rt, int addr)
2086 u_int offset = addr-(u_int)&dynarec_local;
2087 assert(offset<4096);
2088 assem_debug("str %s,fp+%d\n",regname[rt],offset);
2089 output_w32(0xe5800000|rd_rn_rm(rt,FP,0)|offset);
2091 void emit_writehword(int rt, int addr)
2093 u_int offset = addr-(u_int)&dynarec_local;
2095 assem_debug("strh %s,fp+%d\n",regname[rt],offset);
2096 output_w32(0xe1c000b0|rd_rn_rm(rt,FP,0)|((offset<<4)&0xf00)|(offset&0xf));
2098 void emit_writebyte(int rt, int addr)
2100 u_int offset = addr-(u_int)&dynarec_local;
2101 assert(offset<4096);
2102 assem_debug("strb %s,fp+%d\n",regname[rt],offset);
2103 output_w32(0xe5c00000|rd_rn_rm(rt,FP,0)|offset);
2105 void emit_writeword_imm(int imm, int addr)
2107 assem_debug("movl $%x,%x\n",imm,addr);
2110 void emit_writebyte_imm(int imm, int addr)
2112 assem_debug("movb $%x,%x\n",imm,addr);
2116 void emit_mul(int rs)
2118 assem_debug("mul %%%s\n",regname[rs]);
2121 void emit_imul(int rs)
2123 assem_debug("imul %%%s\n",regname[rs]);
2126 void emit_umull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2128 assem_debug("umull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2133 output_w32(0xe0800090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2135 void emit_smull(u_int rs1, u_int rs2, u_int hi, u_int lo)
2137 assem_debug("smull %s, %s, %s, %s\n",regname[lo],regname[hi],regname[rs1],regname[rs2]);
2142 output_w32(0xe0c00090|(hi<<16)|(lo<<12)|(rs2<<8)|rs1);
2145 void emit_div(int rs)
2147 assem_debug("div %%%s\n",regname[rs]);
2150 void emit_idiv(int rs)
2152 assem_debug("idiv %%%s\n",regname[rs]);
2157 assem_debug("cdq\n");
2161 void emit_clz(int rs,int rt)
2163 assem_debug("clz %s,%s\n",regname[rt],regname[rs]);
2164 output_w32(0xe16f0f10|rd_rn_rm(rt,0,rs));
2167 void emit_subcs(int rs1,int rs2,int rt)
2169 assem_debug("subcs %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2170 output_w32(0x20400000|rd_rn_rm(rt,rs1,rs2));
2173 void emit_shrcc_imm(int rs,u_int imm,int rt)
2177 assem_debug("lsrcc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2178 output_w32(0x31a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2181 void emit_shrne_imm(int rs,u_int imm,int rt)
2185 assem_debug("lsrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2186 output_w32(0x11a00000|rd_rn_rm(rt,0,rs)|0x20|(imm<<7));
2189 void emit_negmi(int rs, int rt)
2191 assem_debug("rsbmi %s,%s,#0\n",regname[rt],regname[rs]);
2192 output_w32(0x42600000|rd_rn_rm(rt,rs,0));
2195 void emit_negsmi(int rs, int rt)
2197 assem_debug("rsbsmi %s,%s,#0\n",regname[rt],regname[rs]);
2198 output_w32(0x42700000|rd_rn_rm(rt,rs,0));
2201 void emit_orreq(u_int rs1,u_int rs2,u_int rt)
2203 assem_debug("orreq %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2204 output_w32(0x01800000|rd_rn_rm(rt,rs1,rs2));
2207 void emit_orrne(u_int rs1,u_int rs2,u_int rt)
2209 assem_debug("orrne %s,%s,%s\n",regname[rt],regname[rs1],regname[rs2]);
2210 output_w32(0x11800000|rd_rn_rm(rt,rs1,rs2));
2213 void emit_bic_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2215 assem_debug("bic %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2216 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2219 void emit_biceq_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2221 assem_debug("biceq %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2222 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2225 void emit_bicne_lsl(u_int rs1,u_int rs2,u_int shift,u_int rt)
2227 assem_debug("bicne %s,%s,%s lsl %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2228 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x10|(shift<<8));
2231 void emit_bic_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2233 assem_debug("bic %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2234 output_w32(0xe1C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2237 void emit_biceq_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2239 assem_debug("biceq %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2240 output_w32(0x01C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2243 void emit_bicne_lsr(u_int rs1,u_int rs2,u_int shift,u_int rt)
2245 assem_debug("bicne %s,%s,%s lsr %s\n",regname[rt],regname[rs1],regname[rs2],regname[shift]);
2246 output_w32(0x11C00000|rd_rn_rm(rt,rs1,rs2)|0x30|(shift<<8));
2249 void emit_teq(int rs, int rt)
2251 assem_debug("teq %s,%s\n",regname[rs],regname[rt]);
2252 output_w32(0xe1300000|rd_rn_rm(0,rs,rt));
2255 void emit_rsbimm(int rs, int imm, int rt)
2258 genimm_checked(imm,&armval);
2259 assem_debug("rsb %s,%s,#%d\n",regname[rt],regname[rs],imm);
2260 output_w32(0xe2600000|rd_rn_rm(rt,rs,0)|armval);
2263 // Load 2 immediates optimizing for small code size
2264 void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
2266 emit_movimm(imm1,rt1);
2268 if(genimm(imm2-imm1,&armval)) {
2269 assem_debug("add %s,%s,#%d\n",regname[rt2],regname[rt1],imm2-imm1);
2270 output_w32(0xe2800000|rd_rn_rm(rt2,rt1,0)|armval);
2271 }else if(genimm(imm1-imm2,&armval)) {
2272 assem_debug("sub %s,%s,#%d\n",regname[rt2],regname[rt1],imm1-imm2);
2273 output_w32(0xe2400000|rd_rn_rm(rt2,rt1,0)|armval);
2275 else emit_movimm(imm2,rt2);
2278 // Conditionally select one of two immediates, optimizing for small code size
2279 // This will only be called if HAVE_CMOV_IMM is defined
2280 void emit_cmov2imm_e_ne_compact(int imm1,int imm2,u_int rt)
2283 if(genimm(imm2-imm1,&armval)) {
2284 emit_movimm(imm1,rt);
2285 assem_debug("addne %s,%s,#%d\n",regname[rt],regname[rt],imm2-imm1);
2286 output_w32(0x12800000|rd_rn_rm(rt,rt,0)|armval);
2287 }else if(genimm(imm1-imm2,&armval)) {
2288 emit_movimm(imm1,rt);
2289 assem_debug("subne %s,%s,#%d\n",regname[rt],regname[rt],imm1-imm2);
2290 output_w32(0x12400000|rd_rn_rm(rt,rt,0)|armval);
2294 emit_movimm(imm1,rt);
2295 add_literal((int)out,imm2);
2296 assem_debug("ldrne %s,pc+? [=%x]\n",regname[rt],imm2);
2297 output_w32(0x15900000|rd_rn_rm(rt,15,0));
2299 emit_movw(imm1&0x0000FFFF,rt);
2300 if((imm1&0xFFFF)!=(imm2&0xFFFF)) {
2301 assem_debug("movwne %s,#%d (0x%x)\n",regname[rt],imm2&0xFFFF,imm2&0xFFFF);
2302 output_w32(0x13000000|rd_rn_rm(rt,0,0)|(imm2&0xfff)|((imm2<<4)&0xf0000));
2304 emit_movt(imm1&0xFFFF0000,rt);
2305 if((imm1&0xFFFF0000)!=(imm2&0xFFFF0000)) {
2306 assem_debug("movtne %s,#%d (0x%x)\n",regname[rt],imm2&0xffff0000,imm2&0xffff0000);
2307 output_w32(0x13400000|rd_rn_rm(rt,0,0)|((imm2>>16)&0xfff)|((imm2>>12)&0xf0000));
2313 // special case for checking invalid_code
2314 void emit_cmpmem_indexedsr12_imm(int addr,int r,int imm)
2319 // special case for checking invalid_code
2320 void emit_cmpmem_indexedsr12_reg(int base,int r,int imm)
2322 assert(imm<128&&imm>=0);
2324 assem_debug("ldrb lr,%s,%s lsr #12\n",regname[base],regname[r]);
2325 output_w32(0xe7d00000|rd_rn_rm(HOST_TEMPREG,base,r)|0x620);
2326 emit_cmpimm(HOST_TEMPREG,imm);
2329 // special case for tlb mapping
2330 void emit_addsr12(int rs1,int rs2,int rt)
2332 assem_debug("add %s,%s,%s lsr #12\n",regname[rt],regname[rs1],regname[rs2]);
2333 output_w32(0xe0800620|rd_rn_rm(rt,rs1,rs2));
2336 void emit_callne(int a)
2338 assem_debug("blne %x\n",a);
2339 u_int offset=genjmp(a);
2340 output_w32(0x1b000000|offset);
2343 // Used to preload hash table entries
2344 void emit_prefetch(void *addr)
2346 assem_debug("prefetch %x\n",(int)addr);
2349 output_modrm(0,5,1);
2350 output_w32((int)addr);
2352 void emit_prefetchreg(int r)
2354 assem_debug("pld %s\n",regname[r]);
2355 output_w32(0xf5d0f000|rd_rn_rm(0,r,0));
2358 // Special case for mini_ht
2359 void emit_ldreq_indexed(int rs, u_int offset, int rt)
2361 assert(offset<4096);
2362 assem_debug("ldreq %s,[%s, #%d]\n",regname[rt],regname[rs],offset);
2363 output_w32(0x05900000|rd_rn_rm(rt,rs,0)|offset);
2366 void emit_flds(int r,int sr)
2368 assem_debug("flds s%d,[%s]\n",sr,regname[r]);
2369 output_w32(0xed900a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2372 void emit_vldr(int r,int vr)
2374 assem_debug("vldr d%d,[%s]\n",vr,regname[r]);
2375 output_w32(0xed900b00|(vr<<12)|(r<<16));
2378 void emit_fsts(int sr,int r)
2380 assem_debug("fsts s%d,[%s]\n",sr,regname[r]);
2381 output_w32(0xed800a00|((sr&14)<<11)|((sr&1)<<22)|(r<<16));
2384 void emit_vstr(int vr,int r)
2386 assem_debug("vstr d%d,[%s]\n",vr,regname[r]);
2387 output_w32(0xed800b00|(vr<<12)|(r<<16));
2390 void emit_ftosizs(int s,int d)
2392 assem_debug("ftosizs s%d,s%d\n",d,s);
2393 output_w32(0xeebd0ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2396 void emit_ftosizd(int s,int d)
2398 assem_debug("ftosizd s%d,d%d\n",d,s);
2399 output_w32(0xeebd0bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2402 void emit_fsitos(int s,int d)
2404 assem_debug("fsitos s%d,s%d\n",d,s);
2405 output_w32(0xeeb80ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2408 void emit_fsitod(int s,int d)
2410 assem_debug("fsitod d%d,s%d\n",d,s);
2411 output_w32(0xeeb80bc0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2414 void emit_fcvtds(int s,int d)
2416 assem_debug("fcvtds d%d,s%d\n",d,s);
2417 output_w32(0xeeb70ac0|((d&7)<<12)|((s&14)>>1)|((s&1)<<5));
2420 void emit_fcvtsd(int s,int d)
2422 assem_debug("fcvtsd s%d,d%d\n",d,s);
2423 output_w32(0xeeb70bc0|((d&14)<<11)|((d&1)<<22)|(s&7));
2426 void emit_fsqrts(int s,int d)
2428 assem_debug("fsqrts d%d,s%d\n",d,s);
2429 output_w32(0xeeb10ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2432 void emit_fsqrtd(int s,int d)
2434 assem_debug("fsqrtd s%d,d%d\n",d,s);
2435 output_w32(0xeeb10bc0|((d&7)<<12)|(s&7));
2438 void emit_fabss(int s,int d)
2440 assem_debug("fabss d%d,s%d\n",d,s);
2441 output_w32(0xeeb00ac0|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2444 void emit_fabsd(int s,int d)
2446 assem_debug("fabsd s%d,d%d\n",d,s);
2447 output_w32(0xeeb00bc0|((d&7)<<12)|(s&7));
2450 void emit_fnegs(int s,int d)
2452 assem_debug("fnegs d%d,s%d\n",d,s);
2453 output_w32(0xeeb10a40|((d&14)<<11)|((d&1)<<22)|((s&14)>>1)|((s&1)<<5));
2456 void emit_fnegd(int s,int d)
2458 assem_debug("fnegd s%d,d%d\n",d,s);
2459 output_w32(0xeeb10b40|((d&7)<<12)|(s&7));
2462 void emit_fadds(int s1,int s2,int d)
2464 assem_debug("fadds s%d,s%d,s%d\n",d,s1,s2);
2465 output_w32(0xee300a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2468 void emit_faddd(int s1,int s2,int d)
2470 assem_debug("faddd d%d,d%d,d%d\n",d,s1,s2);
2471 output_w32(0xee300b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2474 void emit_fsubs(int s1,int s2,int d)
2476 assem_debug("fsubs s%d,s%d,s%d\n",d,s1,s2);
2477 output_w32(0xee300a40|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2480 void emit_fsubd(int s1,int s2,int d)
2482 assem_debug("fsubd d%d,d%d,d%d\n",d,s1,s2);
2483 output_w32(0xee300b40|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2486 void emit_fmuls(int s1,int s2,int d)
2488 assem_debug("fmuls s%d,s%d,s%d\n",d,s1,s2);
2489 output_w32(0xee200a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2492 void emit_fmuld(int s1,int s2,int d)
2494 assem_debug("fmuld d%d,d%d,d%d\n",d,s1,s2);
2495 output_w32(0xee200b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2498 void emit_fdivs(int s1,int s2,int d)
2500 assem_debug("fdivs s%d,s%d,s%d\n",d,s1,s2);
2501 output_w32(0xee800a00|((d&14)<<11)|((d&1)<<22)|((s1&14)<<15)|((s1&1)<<7)|((s2&14)>>1)|((s2&1)<<5));
2504 void emit_fdivd(int s1,int s2,int d)
2506 assem_debug("fdivd d%d,d%d,d%d\n",d,s1,s2);
2507 output_w32(0xee800b00|((d&7)<<12)|((s1&7)<<16)|(s2&7));
2510 void emit_fcmps(int x,int y)
2512 assem_debug("fcmps s14, s15\n");
2513 output_w32(0xeeb47a67);
2516 void emit_fcmpd(int x,int y)
2518 assem_debug("fcmpd d6, d7\n");
2519 output_w32(0xeeb46b47);
2524 assem_debug("fmstat\n");
2525 output_w32(0xeef1fa10);
2528 void emit_bicne_imm(int rs,int imm,int rt)
2531 genimm_checked(imm,&armval);
2532 assem_debug("bicne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2533 output_w32(0x13c00000|rd_rn_rm(rt,rs,0)|armval);
2536 void emit_biccs_imm(int rs,int imm,int rt)
2539 genimm_checked(imm,&armval);
2540 assem_debug("biccs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2541 output_w32(0x23c00000|rd_rn_rm(rt,rs,0)|armval);
2544 void emit_bicvc_imm(int rs,int imm,int rt)
2547 genimm_checked(imm,&armval);
2548 assem_debug("bicvc %s,%s,#%d\n",regname[rt],regname[rs],imm);
2549 output_w32(0x73c00000|rd_rn_rm(rt,rs,0)|armval);
2552 void emit_bichi_imm(int rs,int imm,int rt)
2555 genimm_checked(imm,&armval);
2556 assem_debug("bichi %s,%s,#%d\n",regname[rt],regname[rs],imm);
2557 output_w32(0x83c00000|rd_rn_rm(rt,rs,0)|armval);
2560 void emit_orrvs_imm(int rs,int imm,int rt)
2563 genimm_checked(imm,&armval);
2564 assem_debug("orrvs %s,%s,#%d\n",regname[rt],regname[rs],imm);
2565 output_w32(0x63800000|rd_rn_rm(rt,rs,0)|armval);
2568 void emit_orrne_imm(int rs,int imm,int rt)
2571 genimm_checked(imm,&armval);
2572 assem_debug("orrne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2573 output_w32(0x13800000|rd_rn_rm(rt,rs,0)|armval);
2576 void emit_andne_imm(int rs,int imm,int rt)
2579 genimm_checked(imm,&armval);
2580 assem_debug("andne %s,%s,#%d\n",regname[rt],regname[rs],imm);
2581 output_w32(0x12000000|rd_rn_rm(rt,rs,0)|armval);
2584 void emit_jno_unlikely(int a)
2587 assem_debug("addvc pc,pc,#? (%x)\n",/*a-(int)out-8,*/a);
2588 output_w32(0x72800000|rd_rn_rm(15,15,0));
2591 static void save_regs_all(u_int reglist)
2594 if(!reglist) return;
2595 assem_debug("stmia fp,{");
2598 assem_debug("r%d,",i);
2600 output_w32(0xe88b0000|reglist);
2602 static void restore_regs_all(u_int reglist)
2605 if(!reglist) return;
2606 assem_debug("ldmia fp,{");
2609 assem_debug("r%d,",i);
2611 output_w32(0xe89b0000|reglist);
2613 // Save registers before function call
2614 static void save_regs(u_int reglist)
2616 reglist&=0x100f; // only save the caller-save registers, r0-r3, r12
2617 save_regs_all(reglist);
2619 // Restore registers after function call
2620 static void restore_regs(u_int reglist)
2622 reglist&=0x100f; // only restore the caller-save registers, r0-r3, r12
2623 restore_regs_all(reglist);
2626 // Write back consts using r14 so we don't disturb the other registers
2627 void wb_consts(signed char i_regmap[],uint64_t i_is32,u_int i_dirty,int i)
2630 for(hr=0;hr<HOST_REGS;hr++) {
2631 if(hr!=EXCLUDE_REG&&i_regmap[hr]>=0&&((i_dirty>>hr)&1)) {
2632 if(((regs[i].isconst>>hr)&1)&&i_regmap[hr]>0) {
2633 if(i_regmap[hr]<64 || !((i_is32>>(i_regmap[hr]&63))&1) ) {
2634 int value=constmap[i][hr];
2636 emit_zeroreg(HOST_TEMPREG);
2639 emit_movimm(value,HOST_TEMPREG);
2641 emit_storereg(i_regmap[hr],HOST_TEMPREG);
2643 if((i_is32>>i_regmap[hr])&1) {
2644 if(value!=-1&&value!=0) emit_sarimm(HOST_TEMPREG,31,HOST_TEMPREG);
2645 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
2654 /* Stubs/epilogue */
2656 void literal_pool(int n)
2658 if(!literalcount) return;
2660 if((int)out-literals[0][0]<4096-n) return;
2664 for(i=0;i<literalcount;i++)
2666 u_int l_addr=(u_int)out;
2669 if(literals[j][1]==literals[i][1]) {
2670 //printf("dup %08x\n",literals[i][1]);
2671 l_addr=literals[j][0];
2675 ptr=(u_int *)literals[i][0];
2676 u_int offset=l_addr-(u_int)ptr-8;
2677 assert(offset<4096);
2678 assert(!(offset&3));
2680 if(l_addr==(u_int)out) {
2681 literals[i][0]=l_addr; // remember for dupes
2682 output_w32(literals[i][1]);
2688 void literal_pool_jumpover(int n)
2690 if(!literalcount) return;
2692 if((int)out-literals[0][0]<4096-n) return;
2697 set_jump_target(jaddr,(int)out);
2700 emit_extjump2(int addr, int target, int linker)
2702 u_char *ptr=(u_char *)addr;
2703 assert((ptr[3]&0x0e)==0xa);
2704 emit_loadlp(target,0);
2705 emit_loadlp(addr,1);
2706 assert(addr>=BASE_ADDR&&addr<(BASE_ADDR+(1<<TARGET_SIZE_2)));
2707 //assert((target>=0x80000000&&target<0x80800000)||(target>0xA4000000&&target<0xA4001000));
2709 #ifdef DEBUG_CYCLE_COUNT
2710 emit_readword((int)&last_count,ECX);
2711 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2712 emit_readword((int)&next_interupt,ECX);
2713 emit_writeword(HOST_CCREG,(int)&Count);
2714 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
2715 emit_writeword(ECX,(int)&last_count);
2721 emit_extjump(int addr, int target)
2723 emit_extjump2(addr, target, (int)dyna_linker);
2725 emit_extjump_ds(int addr, int target)
2727 emit_extjump2(addr, target, (int)dyna_linker_ds);
2730 // put rt_val into rt, potentially making use of rs with value rs_val
2731 static void emit_movimm_from(u_int rs_val,int rs,u_int rt_val,int rt)
2735 if(genimm(rt_val,&armval)) {
2736 assem_debug("mov %s,#%d\n",regname[rt],rt_val);
2737 output_w32(0xe3a00000|rd_rn_rm(rt,0,0)|armval);
2740 if(genimm(~rt_val,&armval)) {
2741 assem_debug("mvn %s,#%d\n",regname[rt],rt_val);
2742 output_w32(0xe3e00000|rd_rn_rm(rt,0,0)|armval);
2746 if(genimm(diff,&armval)) {
2747 assem_debug("add %s,%s,#%d\n",regname[rt],regname[rs],diff);
2748 output_w32(0xe2800000|rd_rn_rm(rt,rs,0)|armval);
2750 }else if(genimm(-diff,&armval)) {
2751 assem_debug("sub %s,%s,#%d\n",regname[rt],regname[rs],-diff);
2752 output_w32(0xe2400000|rd_rn_rm(rt,rs,0)|armval);
2755 emit_movimm(rt_val,rt);
2758 // return 1 if above function can do it's job cheaply
2759 static int is_similar_value(u_int v1,u_int v2)
2763 if(v1==v2) return 1;
2765 for(xs=diff;xs!=0&&(xs&3)==0;xs>>=2)
2767 if(xs<0x100) return 1;
2768 for(xs=-diff;xs!=0&&(xs&3)==0;xs>>=2)
2770 if(xs<0x100) return 1;
2775 static void pass_args(int a0, int a1)
2779 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2781 else if(a0!=0&&a1==0) {
2783 if (a0>=0) emit_mov(a0,0);
2786 if(a0>=0&&a0!=0) emit_mov(a0,0);
2787 if(a1>=0&&a1!=1) emit_mov(a1,1);
2791 static void mov_loadtype_adj(int type,int rs,int rt)
2794 case LOADB_STUB: emit_signextend8(rs,rt); break;
2795 case LOADBU_STUB: emit_andimm(rs,0xff,rt); break;
2796 case LOADH_STUB: emit_signextend16(rs,rt); break;
2797 case LOADHU_STUB: emit_andimm(rs,0xffff,rt); break;
2798 case LOADW_STUB: if(rs!=rt) emit_mov(rs,rt); break;
2804 #include "pcsxmem.h"
2805 #include "pcsxmem_inline.c"
2810 assem_debug("do_readstub %x\n",start+stubs[n][3]*4);
2812 set_jump_target(stubs[n][1],(int)out);
2813 int type=stubs[n][0];
2816 struct regstat *i_regs=(struct regstat *)stubs[n][5];
2817 u_int reglist=stubs[n][7];
2818 signed char *i_regmap=i_regs->regmap;
2819 int addr=get_reg(i_regmap,AGEN1+(i&1));
2822 if(itype[i]==C1LS||itype[i]==C2LS||itype[i]==LOADLR) {
2823 rth=get_reg(i_regmap,FTEMP|64);
2824 rt=get_reg(i_regmap,FTEMP);
2826 rth=get_reg(i_regmap,rt1[i]|64);
2827 rt=get_reg(i_regmap,rt1[i]);
2831 int r,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0;
2833 for(r=0;r<=12;r++) {
2834 if(((1<<r)&0x13ff)&&((1<<r)®list)==0) {
2845 if((regs_saved||(reglist&2)==0)&&temp!=1&&rs!=1)
2847 emit_readword((int)&mem_rtab,temp);
2848 emit_shrimm(rs,12,temp2);
2849 emit_readword_dualindexedx4(temp,temp2,temp2);
2850 emit_lsls_imm(temp2,1,temp2);
2851 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2853 case LOADB_STUB: emit_ldrccsb_dualindexed(temp2,rs,rt); break;
2854 case LOADBU_STUB: emit_ldrccb_dualindexed(temp2,rs,rt); break;
2855 case LOADH_STUB: emit_ldrccsh_dualindexed(temp2,rs,rt); break;
2856 case LOADHU_STUB: emit_ldrcch_dualindexed(temp2,rs,rt); break;
2857 case LOADW_STUB: emit_ldrcc_dualindexed(temp2,rs,rt); break;
2861 restore_jump=(int)out;
2862 emit_jcc(0); // jump to reg restore
2865 emit_jcc(stubs[n][2]); // return address
2870 if(type==LOADB_STUB||type==LOADBU_STUB)
2871 handler=(int)jump_handler_read8;
2872 if(type==LOADH_STUB||type==LOADHU_STUB)
2873 handler=(int)jump_handler_read16;
2874 if(type==LOADW_STUB)
2875 handler=(int)jump_handler_read32;
2877 pass_args(rs,temp2);
2878 int cc=get_reg(i_regmap,CCREG);
2880 emit_loadreg(CCREG,2);
2881 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
2883 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2884 mov_loadtype_adj(type,0,rt);
2887 set_jump_target(restore_jump,(int)out);
2888 restore_regs(reglist);
2889 emit_jmp(stubs[n][2]); // return address
2892 if(addr<0&&itype[i]!=C1LS&&itype[i]!=C2LS&&itype[i]!=LOADLR) addr=get_reg(i_regmap,-1);
2895 if(type==LOADB_STUB||type==LOADBU_STUB)
2896 ftable=(int)readmemb;
2897 if(type==LOADH_STUB||type==LOADHU_STUB)
2898 ftable=(int)readmemh;
2899 if(type==LOADW_STUB)
2900 ftable=(int)readmem;
2902 if(type==LOADD_STUB)
2903 ftable=(int)readmemd;
2906 emit_writeword(rs,(int)&address);
2910 ds=i_regs!=®s[i];
2911 int real_rs=(itype[i]==LOADLR)?-1:get_reg(i_regmap,rs1[i]);
2912 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
2913 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
2914 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
2915 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
2917 emit_shrimm(rs,16,1);
2918 int cc=get_reg(i_regmap,CCREG);
2920 emit_loadreg(CCREG,2);
2922 emit_movimm(ftable,0);
2923 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
2925 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
2927 //emit_readword((int)&last_count,temp);
2928 //emit_add(cc,temp,cc);
2929 //emit_writeword(cc,(int)&Count);
2931 emit_call((int)&indirect_jump_indexed);
2933 //emit_readword_dualindexedx4(rs,HOST_TEMPREG,15);
2935 // We really shouldn't need to update the count here,
2936 // but not doing so causes random crashes...
2937 emit_readword((int)&Count,HOST_TEMPREG);
2938 emit_readword((int)&next_interupt,2);
2939 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
2940 emit_writeword(2,(int)&last_count);
2941 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
2943 emit_storereg(CCREG,HOST_TEMPREG);
2947 restore_regs(reglist);
2948 //if((cc=get_reg(regmap,CCREG))>=0) {
2949 // emit_loadreg(CCREG,cc);
2951 if(itype[i]==C1LS||itype[i]==C2LS||(rt>=0&&rt1[i]!=0)) {
2953 if(type==LOADB_STUB)
2954 emit_movsbl((int)&readmem_dword,rt);
2955 if(type==LOADBU_STUB)
2956 emit_movzbl((int)&readmem_dword,rt);
2957 if(type==LOADH_STUB)
2958 emit_movswl((int)&readmem_dword,rt);
2959 if(type==LOADHU_STUB)
2960 emit_movzwl((int)&readmem_dword,rt);
2961 if(type==LOADW_STUB)
2962 emit_readword((int)&readmem_dword,rt);
2963 if(type==LOADD_STUB) {
2964 emit_readword((int)&readmem_dword,rt);
2965 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
2968 emit_jmp(stubs[n][2]); // return address
2973 // return memhandler, or get directly accessable address and return 0
2974 u_int get_direct_memhandler(void *table,u_int addr,int type,u_int *addr_host)
2977 l1=((u_int *)table)[addr>>12];
2978 if((l1&(1<<31))==0) {
2985 if(type==LOADB_STUB||type==LOADBU_STUB||type==STOREB_STUB)
2986 l2=((u_int *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2987 else if(type==LOADH_STUB||type==LOADHU_STUB||type==STOREH_STUB)
2988 l2=((u_int *)l1)[0x1000/4 + (addr&0xfff)/2];
2990 l2=((u_int *)l1)[(addr&0xfff)/4];
2991 if((l2&(1<<31))==0) {
2993 *addr_host=v+(addr&0xfff);
3001 inline_readstub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
3003 int rs=get_reg(regmap,target);
3004 int rth=get_reg(regmap,target|64);
3005 int rt=get_reg(regmap,target);
3006 if(rs<0) rs=get_reg(regmap,-1);
3009 u_int handler,host_addr=0,is_dynamic,far_call=0;
3010 int cc=get_reg(regmap,CCREG);
3011 if(pcsx_direct_read(type,addr,CLOCK_ADJUST(adj+1),cc,target?rs:-1,rt))
3013 handler=get_direct_memhandler(mem_rtab,addr,type,&host_addr);
3018 emit_movimm_from(addr,rs,host_addr,rs);
3020 case LOADB_STUB: emit_movsbl_indexed(0,rs,rt); break;
3021 case LOADBU_STUB: emit_movzbl_indexed(0,rs,rt); break;
3022 case LOADH_STUB: emit_movswl_indexed(0,rs,rt); break;
3023 case LOADHU_STUB: emit_movzwl_indexed(0,rs,rt); break;
3024 case LOADW_STUB: emit_readword_indexed(0,rs,rt); break;
3029 is_dynamic=pcsxmem_is_handler_dynamic(addr);
3031 if(type==LOADB_STUB||type==LOADBU_STUB)
3032 handler=(int)jump_handler_read8;
3033 if(type==LOADH_STUB||type==LOADHU_STUB)
3034 handler=(int)jump_handler_read16;
3035 if(type==LOADW_STUB)
3036 handler=(int)jump_handler_read32;
3039 // call a memhandler
3044 emit_movimm(addr,0);
3047 int offset=(int)handler-(int)out-8;
3048 if(offset<-33554432||offset>=33554432) {
3049 // unreachable memhandler, a plugin func perhaps
3050 emit_movimm(handler,12);
3054 emit_loadreg(CCREG,2);
3056 emit_movimm(((u_int *)mem_rtab)[addr>>12]<<1,1);
3057 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
3060 emit_readword((int)&last_count,3);
3061 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
3063 emit_writeword(2,(int)&Count);
3073 case LOADB_STUB: emit_signextend8(0,rt); break;
3074 case LOADBU_STUB: emit_andimm(0,0xff,rt); break;
3075 case LOADH_STUB: emit_signextend16(0,rt); break;
3076 case LOADHU_STUB: emit_andimm(0,0xffff,rt); break;
3077 case LOADW_STUB: if(rt!=0) emit_mov(0,rt); break;
3081 restore_regs(reglist);
3084 if(type==LOADB_STUB||type==LOADBU_STUB)
3085 ftable=(int)readmemb;
3086 if(type==LOADH_STUB||type==LOADHU_STUB)
3087 ftable=(int)readmemh;
3088 if(type==LOADW_STUB)
3089 ftable=(int)readmem;
3091 if(type==LOADD_STUB)
3092 ftable=(int)readmemd;
3096 emit_movimm(addr,rs);
3097 emit_writeword(rs,(int)&address);
3101 if((signed int)addr>=(signed int)0xC0000000) {
3102 // Theoretically we can have a pagefault here, if the TLB has never
3103 // been enabled and the address is outside the range 80000000..BFFFFFFF
3104 // Write out the registers so the pagefault can be handled. This is
3105 // a very rare case and likely represents a bug.
3106 int ds=regmap!=regs[i].regmap;
3107 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3108 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3109 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
3112 //emit_shrimm(rs,16,1);
3113 int cc=get_reg(regmap,CCREG);
3115 emit_loadreg(CCREG,2);
3117 //emit_movimm(ftable,0);
3118 emit_movimm(((u_int *)ftable)[addr>>16],0);
3119 //emit_readword((int)&last_count,12);
3120 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
3122 if((signed int)addr>=(signed int)0xC0000000) {
3123 // Pagefault address
3124 int ds=regmap!=regs[i].regmap;
3125 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3129 //emit_writeword(2,(int)&Count);
3130 //emit_call(((u_int *)ftable)[addr>>16]);
3131 emit_call((int)&indirect_jump);
3133 // We really shouldn't need to update the count here,
3134 // but not doing so causes random crashes...
3135 emit_readword((int)&Count,HOST_TEMPREG);
3136 emit_readword((int)&next_interupt,2);
3137 emit_addimm(HOST_TEMPREG,-CLOCK_ADJUST(adj+1),HOST_TEMPREG);
3138 emit_writeword(2,(int)&last_count);
3139 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3141 emit_storereg(CCREG,HOST_TEMPREG);
3145 restore_regs(reglist);
3147 if(type==LOADB_STUB)
3148 emit_movsbl((int)&readmem_dword,rt);
3149 if(type==LOADBU_STUB)
3150 emit_movzbl((int)&readmem_dword,rt);
3151 if(type==LOADH_STUB)
3152 emit_movswl((int)&readmem_dword,rt);
3153 if(type==LOADHU_STUB)
3154 emit_movzwl((int)&readmem_dword,rt);
3155 if(type==LOADW_STUB)
3156 emit_readword((int)&readmem_dword,rt);
3157 if(type==LOADD_STUB) {
3158 emit_readword((int)&readmem_dword,rt);
3159 if(rth>=0) emit_readword(((int)&readmem_dword)+4,rth);
3167 assem_debug("do_writestub %x\n",start+stubs[n][3]*4);
3169 set_jump_target(stubs[n][1],(int)out);
3170 int type=stubs[n][0];
3173 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3174 u_int reglist=stubs[n][7];
3175 signed char *i_regmap=i_regs->regmap;
3176 int addr=get_reg(i_regmap,AGEN1+(i&1));
3179 if(itype[i]==C1LS||itype[i]==C2LS) {
3180 rth=get_reg(i_regmap,FTEMP|64);
3181 rt=get_reg(i_regmap,r=FTEMP);
3183 rth=get_reg(i_regmap,rs2[i]|64);
3184 rt=get_reg(i_regmap,r=rs2[i]);
3189 int rtmp,temp=-1,temp2=HOST_TEMPREG,regs_saved=0,restore_jump=0,ra;
3190 int reglist2=reglist|(1<<rs)|(1<<rt);
3191 for(rtmp=0;rtmp<=12;rtmp++) {
3192 if(((1<<rtmp)&0x13ff)&&((1<<rtmp)®list2)==0) {
3199 for(rtmp=0;rtmp<=3;rtmp++)
3200 if(rtmp!=rs&&rtmp!=rt)
3203 if((regs_saved||(reglist2&8)==0)&&temp!=3&&rs!=3&&rt!=3)
3205 emit_readword((int)&mem_wtab,temp);
3206 emit_shrimm(rs,12,temp2);
3207 emit_readword_dualindexedx4(temp,temp2,temp2);
3208 emit_lsls_imm(temp2,1,temp2);
3210 case STOREB_STUB: emit_strccb_dualindexed(temp2,rs,rt); break;
3211 case STOREH_STUB: emit_strcch_dualindexed(temp2,rs,rt); break;
3212 case STOREW_STUB: emit_strcc_dualindexed(temp2,rs,rt); break;
3216 restore_jump=(int)out;
3217 emit_jcc(0); // jump to reg restore
3220 emit_jcc(stubs[n][2]); // return address (invcode check)
3226 case STOREB_STUB: handler=(int)jump_handler_write8; break;
3227 case STOREH_STUB: handler=(int)jump_handler_write16; break;
3228 case STOREW_STUB: handler=(int)jump_handler_write32; break;
3234 int cc=get_reg(i_regmap,CCREG);
3236 emit_loadreg(CCREG,2);
3237 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
3238 // returns new cycle_count
3240 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
3242 emit_storereg(CCREG,2);
3244 set_jump_target(restore_jump,(int)out);
3245 restore_regs(reglist);
3249 if(addr<0) addr=get_reg(i_regmap,-1);
3252 if(type==STOREB_STUB)
3253 ftable=(int)writememb;
3254 if(type==STOREH_STUB)
3255 ftable=(int)writememh;
3256 if(type==STOREW_STUB)
3257 ftable=(int)writemem;
3259 if(type==STORED_STUB)
3260 ftable=(int)writememd;
3263 emit_writeword(rs,(int)&address);
3264 //emit_shrimm(rs,16,rs);
3265 //emit_movmem_indexedx4(ftable,rs,rs);
3266 if(type==STOREB_STUB)
3267 emit_writebyte(rt,(int)&byte);
3268 if(type==STOREH_STUB)
3269 emit_writehword(rt,(int)&hword);
3270 if(type==STOREW_STUB)
3271 emit_writeword(rt,(int)&word);
3272 if(type==STORED_STUB) {
3274 emit_writeword(rt,(int)&dword);
3275 emit_writeword(r?rth:rt,(int)&dword+4);
3277 printf("STORED_STUB\n");
3283 ds=i_regs!=®s[i];
3284 int real_rs=get_reg(i_regmap,rs1[i]);
3285 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
3286 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
3287 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
3288 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
3290 emit_shrimm(rs,16,1);
3291 int cc=get_reg(i_regmap,CCREG);
3293 emit_loadreg(CCREG,2);
3295 emit_movimm(ftable,0);
3296 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
3298 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3300 //emit_readword((int)&last_count,temp);
3301 //emit_addimm(cc,2*stubs[n][5]+2,cc);
3302 //emit_add(cc,temp,cc);
3303 //emit_writeword(cc,(int)&Count);
3304 emit_call((int)&indirect_jump_indexed);
3306 emit_readword((int)&Count,HOST_TEMPREG);
3307 emit_readword((int)&next_interupt,2);
3308 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3309 emit_writeword(2,(int)&last_count);
3310 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3312 emit_storereg(CCREG,HOST_TEMPREG);
3315 restore_regs(reglist);
3316 //if((cc=get_reg(regmap,CCREG))>=0) {
3317 // emit_loadreg(CCREG,cc);
3319 emit_jmp(stubs[n][2]); // return address
3323 inline_writestub(int type, int i, u_int addr, signed char regmap[], int target, int adj, u_int reglist)
3325 int rs=get_reg(regmap,-1);
3326 int rth=get_reg(regmap,target|64);
3327 int rt=get_reg(regmap,target);
3331 u_int handler,host_addr=0;
3332 handler=get_direct_memhandler(mem_wtab,addr,type,&host_addr);
3335 emit_movimm_from(addr,rs,host_addr,rs);
3337 case STOREB_STUB: emit_writebyte_indexed(rt,0,rs); break;
3338 case STOREH_STUB: emit_writehword_indexed(rt,0,rs); break;
3339 case STOREW_STUB: emit_writeword_indexed(rt,0,rs); break;
3345 // call a memhandler
3348 int cc=get_reg(regmap,CCREG);
3350 emit_loadreg(CCREG,2);
3351 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
3352 emit_movimm(handler,3);
3353 // returns new cycle_count
3354 emit_call((int)jump_handler_write_h);
3355 emit_addimm(0,-CLOCK_ADJUST(adj+1),cc<0?2:cc);
3357 emit_storereg(CCREG,2);
3358 restore_regs(reglist);
3361 if(type==STOREB_STUB)
3362 ftable=(int)writememb;
3363 if(type==STOREH_STUB)
3364 ftable=(int)writememh;
3365 if(type==STOREW_STUB)
3366 ftable=(int)writemem;
3368 if(type==STORED_STUB)
3369 ftable=(int)writememd;
3372 emit_writeword(rs,(int)&address);
3373 //emit_shrimm(rs,16,rs);
3374 //emit_movmem_indexedx4(ftable,rs,rs);
3375 if(type==STOREB_STUB)
3376 emit_writebyte(rt,(int)&byte);
3377 if(type==STOREH_STUB)
3378 emit_writehword(rt,(int)&hword);
3379 if(type==STOREW_STUB)
3380 emit_writeword(rt,(int)&word);
3381 if(type==STORED_STUB) {
3383 emit_writeword(rt,(int)&dword);
3384 emit_writeword(target?rth:rt,(int)&dword+4);
3386 printf("STORED_STUB\n");
3392 // rearmed note: load_all_consts prevents BIOS boot, some bug?
3393 if((signed int)addr>=(signed int)0xC0000000) {
3394 // Theoretically we can have a pagefault here, if the TLB has never
3395 // been enabled and the address is outside the range 80000000..BFFFFFFF
3396 // Write out the registers so the pagefault can be handled. This is
3397 // a very rare case and likely represents a bug.
3398 int ds=regmap!=regs[i].regmap;
3399 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3400 if(!ds) wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3401 else wb_dirtys(branch_regs[i-1].regmap_entry,branch_regs[i-1].was32,branch_regs[i-1].wasdirty);
3404 //emit_shrimm(rs,16,1);
3405 int cc=get_reg(regmap,CCREG);
3407 emit_loadreg(CCREG,2);
3409 //emit_movimm(ftable,0);
3410 emit_movimm(((u_int *)ftable)[addr>>16],0);
3411 //emit_readword((int)&last_count,12);
3412 emit_addimm(cc<0?2:cc,CLOCK_ADJUST(adj+1),2);
3414 if((signed int)addr>=(signed int)0xC0000000) {
3415 // Pagefault address
3416 int ds=regmap!=regs[i].regmap;
3417 emit_movimm(start+i*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3421 //emit_writeword(2,(int)&Count);
3422 //emit_call(((u_int *)ftable)[addr>>16]);
3423 emit_call((int)&indirect_jump);
3424 emit_readword((int)&Count,HOST_TEMPREG);
3425 emit_readword((int)&next_interupt,2);
3426 emit_addimm(HOST_TEMPREG,-CLOCK_ADJUST(adj+1),HOST_TEMPREG);
3427 emit_writeword(2,(int)&last_count);
3428 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3430 emit_storereg(CCREG,HOST_TEMPREG);
3433 restore_regs(reglist);
3437 do_unalignedwritestub(int n)
3439 assem_debug("do_unalignedwritestub %x\n",start+stubs[n][3]*4);
3441 set_jump_target(stubs[n][1],(int)out);
3444 struct regstat *i_regs=(struct regstat *)stubs[n][4];
3445 int addr=stubs[n][5];
3446 u_int reglist=stubs[n][7];
3447 signed char *i_regmap=i_regs->regmap;
3448 int temp2=get_reg(i_regmap,FTEMP);
3451 rt=get_reg(i_regmap,rs2[i]);
3454 assert(opcode[i]==0x2a||opcode[i]==0x2e); // SWL/SWR only implemented
3456 reglist&=~(1<<temp2);
3459 // don't bother with it and call write handler
3462 int cc=get_reg(i_regmap,CCREG);
3464 emit_loadreg(CCREG,2);
3465 emit_addimm(cc<0?2:cc,CLOCK_ADJUST((int)stubs[n][6]+1),2);
3466 emit_call((int)(opcode[i]==0x2a?jump_handle_swl:jump_handle_swr));
3467 emit_addimm(0,-CLOCK_ADJUST((int)stubs[n][6]+1),cc<0?2:cc);
3469 emit_storereg(CCREG,2);
3470 restore_regs(reglist);
3471 emit_jmp(stubs[n][2]); // return address
3473 emit_andimm(addr,0xfffffffc,temp2);
3474 emit_writeword(temp2,(int)&address);
3478 ds=i_regs!=®s[i];
3479 real_rs=get_reg(i_regmap,rs1[i]);
3480 u_int cmask=ds?-1:(0x100f|~i_regs->wasconst);
3481 if(!ds) load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&0x100f,i);
3482 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty&cmask&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs)));
3483 if(!ds) wb_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty&~(1<<addr)&(real_rs<0?-1:~(1<<real_rs))&~0x100f,i);
3485 emit_shrimm(addr,16,1);
3486 int cc=get_reg(i_regmap,CCREG);
3488 emit_loadreg(CCREG,2);
3490 emit_movimm((u_int)readmem,0);
3491 emit_addimm(cc<0?2:cc,2*stubs[n][6]+2,2);
3493 // pagefault address
3494 emit_movimm(start+stubs[n][3]*4+(((regs[i].was32>>rs1[i])&1)<<1)+ds,3);
3496 emit_call((int)&indirect_jump_indexed);
3497 restore_regs(reglist);
3499 emit_readword((int)&readmem_dword,temp2);
3500 int temp=addr; //hmh
3501 emit_shlimm(addr,3,temp);
3502 emit_andimm(temp,24,temp);
3503 #ifdef BIG_ENDIAN_MIPS
3504 if (opcode[i]==0x2e) // SWR
3506 if (opcode[i]==0x2a) // SWL
3508 emit_xorimm(temp,24,temp);
3509 emit_movimm(-1,HOST_TEMPREG);
3510 if (opcode[i]==0x2a) { // SWL
3511 emit_bic_lsr(temp2,HOST_TEMPREG,temp,temp2);
3512 emit_orrshr(rt,temp,temp2);
3514 emit_bic_lsl(temp2,HOST_TEMPREG,temp,temp2);
3515 emit_orrshl(rt,temp,temp2);
3517 emit_readword((int)&address,addr);
3518 emit_writeword(temp2,(int)&word);
3519 //save_regs(reglist); // don't need to, no state changes
3520 emit_shrimm(addr,16,1);
3521 emit_movimm((u_int)writemem,0);
3522 //emit_call((int)&indirect_jump_indexed);
3524 emit_readword_dualindexedx4(0,1,15);
3525 emit_readword((int)&Count,HOST_TEMPREG);
3526 emit_readword((int)&next_interupt,2);
3527 emit_addimm(HOST_TEMPREG,-2*stubs[n][6]-2,HOST_TEMPREG);
3528 emit_writeword(2,(int)&last_count);
3529 emit_sub(HOST_TEMPREG,2,cc<0?HOST_TEMPREG:cc);
3531 emit_storereg(CCREG,HOST_TEMPREG);
3533 restore_regs(reglist);
3534 emit_jmp(stubs[n][2]); // return address
3538 void printregs(int edi,int esi,int ebp,int esp,int b,int d,int c,int a)
3540 printf("regs: %x %x %x %x %x %x %x (%x)\n",a,b,c,d,ebp,esi,edi,(&edi)[-1]);
3546 u_int reglist=stubs[n][3];
3547 set_jump_target(stubs[n][1],(int)out);
3549 if(stubs[n][4]!=0) emit_mov(stubs[n][4],0);
3550 emit_call((int)&invalidate_addr);
3551 restore_regs(reglist);
3552 emit_jmp(stubs[n][2]); // return address
3555 int do_dirty_stub(int i)
3557 assem_debug("do_dirty_stub %x\n",start+i*4);
3558 u_int addr=(int)start<(int)0xC0000000?(u_int)source:(u_int)start;
3562 // Careful about the code output here, verify_dirty needs to parse it.
3564 emit_loadlp(addr,1);
3565 emit_loadlp((int)copy,2);
3566 emit_loadlp(slen*4,3);
3568 emit_movw(addr&0x0000FFFF,1);
3569 emit_movw(((u_int)copy)&0x0000FFFF,2);
3570 emit_movt(addr&0xFFFF0000,1);
3571 emit_movt(((u_int)copy)&0xFFFF0000,2);
3572 emit_movw(slen*4,3);
3574 emit_movimm(start+i*4,0);
3575 emit_call((int)start<(int)0xC0000000?(int)&verify_code:(int)&verify_code_vm);
3578 if(entry==(int)out) entry=instr_addr[i];
3579 emit_jmp(instr_addr[i]);
3583 void do_dirty_stub_ds()
3585 // Careful about the code output here, verify_dirty needs to parse it.
3587 emit_loadlp((int)start<(int)0xC0000000?(int)source:(int)start,1);
3588 emit_loadlp((int)copy,2);
3589 emit_loadlp(slen*4,3);
3591 emit_movw(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0x0000FFFF,1);
3592 emit_movw(((u_int)copy)&0x0000FFFF,2);
3593 emit_movt(((int)start<(int)0xC0000000?(u_int)source:(u_int)start)&0xFFFF0000,1);
3594 emit_movt(((u_int)copy)&0xFFFF0000,2);
3595 emit_movw(slen*4,3);
3597 emit_movimm(start+1,0);
3598 emit_call((int)&verify_code_ds);
3604 assem_debug("do_cop1stub %x\n",start+stubs[n][3]*4);
3605 set_jump_target(stubs[n][1],(int)out);
3607 // int rs=stubs[n][4];
3608 struct regstat *i_regs=(struct regstat *)stubs[n][5];
3611 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3612 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3614 //else {printf("fp exception in delay slot\n");}
3615 wb_dirtys(i_regs->regmap_entry,i_regs->was32,i_regs->wasdirty);
3616 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3617 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3618 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3619 emit_jmp(ds?(int)fp_exception_ds:(int)fp_exception);
3626 int do_tlb_r(int s,int ar,int map,int x,int a,int shift,int c,u_int addr)
3629 if((signed int)addr>=(signed int)0xC0000000) {
3630 // address_generation already loaded the const
3631 emit_readword_dualindexedx4(FP,map,map);
3634 return -1; // No mapping
3638 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3639 emit_addsr12(map,s,map);
3640 // Schedule this while we wait on the load
3641 //if(x) emit_xorimm(s,x,ar);
3642 if(shift>=0) emit_shlimm(s,3,shift);
3643 if(~a) emit_andimm(s,a,ar);
3644 emit_readword_dualindexedx4(FP,map,map);
3648 int do_tlb_r_branch(int map, int c, u_int addr, int *jaddr)
3650 if(!c||(signed int)addr>=(signed int)0xC0000000) {
3658 int gen_tlb_addr_r(int ar, int map) {
3660 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3661 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3665 int do_tlb_w(int s,int ar,int map,int x,int c,u_int addr)
3668 if(addr<0x80800000||addr>=0xC0000000) {
3669 // address_generation already loaded the const
3670 emit_readword_dualindexedx4(FP,map,map);
3673 return -1; // No mapping
3677 emit_movimm(((int)memory_map-(int)&dynarec_local)>>2,map);
3678 emit_addsr12(map,s,map);
3679 // Schedule this while we wait on the load
3680 //if(x) emit_xorimm(s,x,ar);
3681 emit_readword_dualindexedx4(FP,map,map);
3685 int do_tlb_w_branch(int map, int c, u_int addr, int *jaddr)
3687 if(!c||addr<0x80800000||addr>=0xC0000000) {
3688 emit_testimm(map,0x40000000);
3694 int gen_tlb_addr_w(int ar, int map) {
3696 assem_debug("add %s,%s,%s lsl #2\n",regname[ar],regname[ar],regname[map]);
3697 output_w32(0xe0800100|rd_rn_rm(ar,ar,map));
3701 // Generate the address of the memory_map entry, relative to dynarec_local
3702 generate_map_const(u_int addr,int reg) {
3703 //printf("generate_map_const(%x,%s)\n",addr,regname[reg]);
3704 emit_movimm((addr>>12)+(((u_int)memory_map-(u_int)&dynarec_local)>>2),reg);
3709 static int do_tlb_r() { return 0; }
3710 static int do_tlb_r_branch() { return 0; }
3711 static int gen_tlb_addr_r() { return 0; }
3712 static int do_tlb_w() { return 0; }
3713 static int do_tlb_w_branch() { return 0; }
3714 static int gen_tlb_addr_w() { return 0; }
3716 #endif // DISABLE_TLB
3720 void shift_assemble_arm(int i,struct regstat *i_regs)
3723 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
3725 signed char s,t,shift;
3726 t=get_reg(i_regs->regmap,rt1[i]);
3727 s=get_reg(i_regs->regmap,rs1[i]);
3728 shift=get_reg(i_regs->regmap,rs2[i]);
3737 if(s!=t) emit_mov(s,t);
3741 emit_andimm(shift,31,HOST_TEMPREG);
3742 if(opcode2[i]==4) // SLLV
3744 emit_shl(s,HOST_TEMPREG,t);
3746 if(opcode2[i]==6) // SRLV
3748 emit_shr(s,HOST_TEMPREG,t);
3750 if(opcode2[i]==7) // SRAV
3752 emit_sar(s,HOST_TEMPREG,t);
3756 } else { // DSLLV/DSRLV/DSRAV
3757 signed char sh,sl,th,tl,shift;
3758 th=get_reg(i_regs->regmap,rt1[i]|64);
3759 tl=get_reg(i_regs->regmap,rt1[i]);
3760 sh=get_reg(i_regs->regmap,rs1[i]|64);
3761 sl=get_reg(i_regs->regmap,rs1[i]);
3762 shift=get_reg(i_regs->regmap,rs2[i]);
3767 if(th>=0) emit_zeroreg(th);
3772 if(sl!=tl) emit_mov(sl,tl);
3773 if(th>=0&&sh!=th) emit_mov(sh,th);
3777 // FIXME: What if shift==tl ?
3779 int temp=get_reg(i_regs->regmap,-1);
3781 if(th<0&&opcode2[i]!=0x14) {th=temp;} // DSLLV doesn't need a temporary register
3784 emit_andimm(shift,31,HOST_TEMPREG);
3785 if(opcode2[i]==0x14) // DSLLV
3787 if(th>=0) emit_shl(sh,HOST_TEMPREG,th);
3788 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3789 emit_orrshr(sl,HOST_TEMPREG,th);
3790 emit_andimm(shift,31,HOST_TEMPREG);
3791 emit_testimm(shift,32);
3792 emit_shl(sl,HOST_TEMPREG,tl);
3793 if(th>=0) emit_cmovne_reg(tl,th);
3794 emit_cmovne_imm(0,tl);
3796 if(opcode2[i]==0x16) // DSRLV
3799 emit_shr(sl,HOST_TEMPREG,tl);
3800 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3801 emit_orrshl(sh,HOST_TEMPREG,tl);
3802 emit_andimm(shift,31,HOST_TEMPREG);
3803 emit_testimm(shift,32);
3804 emit_shr(sh,HOST_TEMPREG,th);
3805 emit_cmovne_reg(th,tl);
3806 if(real_th>=0) emit_cmovne_imm(0,th);
3808 if(opcode2[i]==0x17) // DSRAV
3811 emit_shr(sl,HOST_TEMPREG,tl);
3812 emit_rsbimm(HOST_TEMPREG,32,HOST_TEMPREG);
3815 emit_sarimm(th,31,temp);
3817 emit_orrshl(sh,HOST_TEMPREG,tl);
3818 emit_andimm(shift,31,HOST_TEMPREG);
3819 emit_testimm(shift,32);
3820 emit_sar(sh,HOST_TEMPREG,th);
3821 emit_cmovne_reg(th,tl);
3822 if(real_th>=0) emit_cmovne_reg(temp,th);
3831 static void speculate_mov(int rs,int rt)
3834 smrv_strong_next|=1<<rt;
3839 static void speculate_mov_weak(int rs,int rt)
3842 smrv_weak_next|=1<<rt;
3847 static void speculate_register_values(int i)
3850 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
3851 // gp,sp are likely to stay the same throughout the block
3852 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
3853 smrv_weak_next=~smrv_strong_next;
3854 //printf(" llr %08x\n", smrv[4]);
3856 smrv_strong=smrv_strong_next;
3857 smrv_weak=smrv_weak_next;
3860 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3861 else if((smrv_strong>>rs2[i])&1) speculate_mov(rs2[i],rt1[i]);
3862 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3863 else if((smrv_weak>>rs2[i])&1) speculate_mov_weak(rs2[i],rt1[i]);
3865 smrv_strong_next&=~(1<<rt1[i]);
3866 smrv_weak_next&=~(1<<rt1[i]);
3870 smrv_strong_next&=~(1<<rt1[i]);
3871 smrv_weak_next&=~(1<<rt1[i]);
3874 if(rt1[i]&&is_const(®s[i],rt1[i])) {
3875 int value,hr=get_reg(regs[i].regmap,rt1[i]);
3877 if(get_final_value(hr,i,&value))
3879 else smrv[rt1[i]]=constmap[i][hr];
3880 smrv_strong_next|=1<<rt1[i];
3884 if ((smrv_strong>>rs1[i])&1) speculate_mov(rs1[i],rt1[i]);
3885 else if((smrv_weak>>rs1[i])&1) speculate_mov_weak(rs1[i],rt1[i]);
3889 if(start<0x2000&&(rt1[i]==26||(smrv[rt1[i]]>>24)==0xa0)) {
3890 // special case for BIOS
3891 smrv[rt1[i]]=0xa0000000;
3892 smrv_strong_next|=1<<rt1[i];
3899 smrv_strong_next&=~(1<<rt1[i]);
3900 smrv_weak_next&=~(1<<rt1[i]);
3904 if(opcode2[i]==0||opcode2[i]==2) { // MFC/CFC
3905 smrv_strong_next&=~(1<<rt1[i]);
3906 smrv_weak_next&=~(1<<rt1[i]);
3910 if (opcode[i]==0x32) { // LWC2
3911 smrv_strong_next&=~(1<<rt1[i]);
3912 smrv_weak_next&=~(1<<rt1[i]);
3918 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
3919 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
3931 static int get_ptr_mem_type(u_int a)
3933 if(a < 0x00200000) {
3934 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
3935 // return wrong, must use memhandler for BIOS self-test to pass
3936 // 007 does similar stuff from a00 mirror, weird stuff
3940 if(0x1f800000 <= a && a < 0x1f801000)
3942 if(0x80200000 <= a && a < 0x80800000)
3944 if(0xa0000000 <= a && a < 0xa0200000)
3950 static int emit_fastpath_cmp_jump(int i,int addr,int *addr_reg_override)
3956 if(((smrv_strong|smrv_weak)>>mr)&1) {
3957 type=get_ptr_mem_type(smrv[mr]);
3958 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
3961 // use the mirror we are running on
3962 type=get_ptr_mem_type(start);
3963 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
3966 if(type==MTYPE_8020) { // RAM 80200000+ mirror
3967 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
3968 addr=*addr_reg_override=HOST_TEMPREG;
3971 else if(type==MTYPE_0000) { // RAM 0 mirror
3972 emit_orimm(addr,0x80000000,HOST_TEMPREG);
3973 addr=*addr_reg_override=HOST_TEMPREG;
3976 else if(type==MTYPE_A000) { // RAM A mirror
3977 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
3978 addr=*addr_reg_override=HOST_TEMPREG;
3981 else if(type==MTYPE_1F80) { // scratchpad
3982 emit_addimm(addr,-0x1f800000,HOST_TEMPREG);
3983 emit_cmpimm(HOST_TEMPREG,0x1000);
3991 emit_cmpimm(addr,RAM_SIZE);
3993 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3994 // Hint to branch predictor that the branch is unlikely to be taken
3996 emit_jno_unlikely(0);
4005 #define shift_assemble shift_assemble_arm
4007 void loadlr_assemble_arm(int i,struct regstat *i_regs)
4009 int s,th,tl,temp,temp2,addr,map=-1;
4012 int memtarget=0,c=0;
4013 int fastload_reg_override=0;
4015 th=get_reg(i_regs->regmap,rt1[i]|64);
4016 tl=get_reg(i_regs->regmap,rt1[i]);
4017 s=get_reg(i_regs->regmap,rs1[i]);
4018 temp=get_reg(i_regs->regmap,-1);
4019 temp2=get_reg(i_regs->regmap,FTEMP);
4020 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
4023 for(hr=0;hr<HOST_REGS;hr++) {
4024 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4027 if(offset||s<0||c) addr=temp2;
4030 c=(i_regs->wasconst>>s)&1;
4032 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
4033 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
4039 map=get_reg(i_regs->regmap,ROREG);
4040 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
4042 emit_shlimm(addr,3,temp);
4043 if (opcode[i]==0x22||opcode[i]==0x26) {
4044 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
4046 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
4048 jaddr=emit_fastpath_cmp_jump(i,temp2,&fastload_reg_override);
4051 if (opcode[i]==0x22||opcode[i]==0x26) {
4052 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
4054 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
4061 }else if (opcode[i]==0x22||opcode[i]==0x26) {
4062 a=0xFFFFFFFC; // LWL/LWR
4064 a=0xFFFFFFF8; // LDL/LDR
4066 map=get_reg(i_regs->regmap,TLREG);
4069 map=do_tlb_r(addr,temp2,map,0,a,c?-1:temp,c,constmap[i][s]+offset);
4071 if (opcode[i]==0x22||opcode[i]==0x26) {
4072 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
4074 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
4077 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
4079 if (opcode[i]==0x22||opcode[i]==0x26) { // LWL/LWR
4082 if(fastload_reg_override) a=fastload_reg_override;
4083 //emit_readword_indexed((int)rdram-0x80000000,temp2,temp2);
4084 emit_readword_indexed_tlb(0,a,map,temp2);
4085 if(jaddr) add_stub(LOADW_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
4088 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj[i],reglist);
4091 emit_andimm(temp,24,temp);
4092 #ifdef BIG_ENDIAN_MIPS
4093 if (opcode[i]==0x26) // LWR
4095 if (opcode[i]==0x22) // LWL
4097 emit_xorimm(temp,24,temp);
4098 emit_movimm(-1,HOST_TEMPREG);
4099 if (opcode[i]==0x26) {
4100 emit_shr(temp2,temp,temp2);
4101 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
4103 emit_shl(temp2,temp,temp2);
4104 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
4106 emit_or(temp2,tl,tl);
4108 //emit_storereg(rt1[i],tl); // DEBUG
4110 if (opcode[i]==0x1A||opcode[i]==0x1B) { // LDL/LDR
4111 // FIXME: little endian, fastload_reg_override
4112 int temp2h=get_reg(i_regs->regmap,FTEMP|64);
4114 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,temp2,temp2h);
4115 //emit_readword_indexed((int)rdram-0x7FFFFFFC,temp2,temp2);
4116 emit_readdword_indexed_tlb(0,temp2,map,temp2h,temp2);
4117 if(jaddr) add_stub(LOADD_STUB,jaddr,(int)out,i,temp2,(int)i_regs,ccadj[i],reglist);
4120 inline_readstub(LOADD_STUB,i,(constmap[i][s]+offset)&0xFFFFFFF8,i_regs->regmap,FTEMP,ccadj[i],reglist);
4124 emit_testimm(temp,32);
4125 emit_andimm(temp,24,temp);
4126 if (opcode[i]==0x1A) { // LDL
4127 emit_rsbimm(temp,32,HOST_TEMPREG);
4128 emit_shl(temp2h,temp,temp2h);
4129 emit_orrshr(temp2,HOST_TEMPREG,temp2h);
4130 emit_movimm(-1,HOST_TEMPREG);
4131 emit_shl(temp2,temp,temp2);
4132 emit_cmove_reg(temp2h,th);
4133 emit_biceq_lsl(tl,HOST_TEMPREG,temp,tl);
4134 emit_bicne_lsl(th,HOST_TEMPREG,temp,th);
4135 emit_orreq(temp2,tl,tl);
4136 emit_orrne(temp2,th,th);
4138 if (opcode[i]==0x1B) { // LDR
4139 emit_xorimm(temp,24,temp);
4140 emit_rsbimm(temp,32,HOST_TEMPREG);
4141 emit_shr(temp2,temp,temp2);
4142 emit_orrshl(temp2h,HOST_TEMPREG,temp2);
4143 emit_movimm(-1,HOST_TEMPREG);
4144 emit_shr(temp2h,temp,temp2h);
4145 emit_cmovne_reg(temp2,tl);
4146 emit_bicne_lsr(th,HOST_TEMPREG,temp,th);
4147 emit_biceq_lsr(tl,HOST_TEMPREG,temp,tl);
4148 emit_orrne(temp2h,th,th);
4149 emit_orreq(temp2h,tl,tl);
4154 #define loadlr_assemble loadlr_assemble_arm
4156 void cop0_assemble(int i,struct regstat *i_regs)
4158 if(opcode2[i]==0) // MFC0
4160 signed char t=get_reg(i_regs->regmap,rt1[i]);
4161 char copr=(source[i]>>11)&0x1f;
4162 //assert(t>=0); // Why does this happen? OOT is weird
4163 if(t>=0&&rt1[i]!=0) {
4165 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
4166 emit_movimm((source[i]>>11)&0x1f,1);
4167 emit_writeword(0,(int)&PC);
4168 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
4170 emit_readword((int)&last_count,ECX);
4171 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
4172 emit_add(HOST_CCREG,ECX,HOST_CCREG);
4173 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4174 emit_writeword(HOST_CCREG,(int)&Count);
4176 emit_call((int)MFC0);
4177 emit_readword((int)&readmem_dword,t);
4179 emit_readword((int)®_cop0+copr*4,t);
4183 else if(opcode2[i]==4) // MTC0
4185 signed char s=get_reg(i_regs->regmap,rs1[i]);
4186 char copr=(source[i]>>11)&0x1f;
4189 emit_writeword(s,(int)&readmem_dword);
4190 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
4191 emit_addimm(FP,(int)&fake_pc-(int)&dynarec_local,0);
4192 emit_movimm((source[i]>>11)&0x1f,1);
4193 emit_writeword(0,(int)&PC);
4194 emit_writebyte(1,(int)&(fake_pc.f.r.nrd));
4196 wb_register(rs1[i],i_regs->regmap,i_regs->dirty,i_regs->is32);
4198 if(copr==9||copr==11||copr==12||copr==13) {
4199 emit_readword((int)&last_count,HOST_TEMPREG);
4200 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
4201 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
4202 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4203 emit_writeword(HOST_CCREG,(int)&Count);
4205 // What a mess. The status register (12) can enable interrupts,
4206 // so needs a special case to handle a pending interrupt.
4207 // The interrupt must be taken immediately, because a subsequent
4208 // instruction might disable interrupts again.
4209 if(copr==12||copr==13) {
4212 // burn cycles to cause cc_interrupt, which will
4213 // reschedule next_interupt. Relies on CCREG from above.
4214 assem_debug("MTC0 DS %d\n", copr);
4215 emit_writeword(HOST_CCREG,(int)&last_count);
4216 emit_movimm(0,HOST_CCREG);
4217 emit_storereg(CCREG,HOST_CCREG);
4218 emit_loadreg(rs1[i],1);
4219 emit_movimm(copr,0);
4220 emit_call((int)pcsx_mtc0_ds);
4221 emit_loadreg(rs1[i],s);
4225 emit_movimm(start+i*4+4,HOST_TEMPREG);
4226 emit_writeword(HOST_TEMPREG,(int)&pcaddr);
4227 emit_movimm(0,HOST_TEMPREG);
4228 emit_writeword(HOST_TEMPREG,(int)&pending_exception);
4230 //else if(copr==12&&is_delayslot) emit_call((int)MTC0_R12);
4234 emit_loadreg(rs1[i],1);
4237 emit_movimm(copr,0);
4238 emit_call((int)pcsx_mtc0);
4240 emit_call((int)MTC0);
4242 if(copr==9||copr==11||copr==12||copr==13) {
4243 emit_readword((int)&Count,HOST_CCREG);
4244 emit_readword((int)&next_interupt,HOST_TEMPREG);
4245 emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4246 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
4247 emit_writeword(HOST_TEMPREG,(int)&last_count);
4248 emit_storereg(CCREG,HOST_CCREG);
4250 if(copr==12||copr==13) {
4251 assert(!is_delayslot);
4252 emit_readword((int)&pending_exception,14);
4254 emit_jne((int)&do_interrupt);
4256 emit_loadreg(rs1[i],s);
4257 if(get_reg(i_regs->regmap,rs1[i]|64)>=0)
4258 emit_loadreg(rs1[i]|64,get_reg(i_regs->regmap,rs1[i]|64));
4263 assert(opcode2[i]==0x10);
4265 if((source[i]&0x3f)==0x01) // TLBR
4266 emit_call((int)TLBR);
4267 if((source[i]&0x3f)==0x02) // TLBWI
4268 emit_call((int)TLBWI_new);
4269 if((source[i]&0x3f)==0x06) { // TLBWR
4270 // The TLB entry written by TLBWR is dependent on the count,
4271 // so update the cycle count
4272 emit_readword((int)&last_count,ECX);
4273 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
4274 emit_add(HOST_CCREG,ECX,HOST_CCREG);
4275 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4276 emit_writeword(HOST_CCREG,(int)&Count);
4277 emit_call((int)TLBWR_new);
4279 if((source[i]&0x3f)==0x08) // TLBP
4280 emit_call((int)TLBP);
4283 if((source[i]&0x3f)==0x10) // RFE
4285 emit_readword((int)&Status,0);
4286 emit_andimm(0,0x3c,1);
4287 emit_andimm(0,~0xf,0);
4288 emit_orrshr_imm(1,2,0);
4289 emit_writeword(0,(int)&Status);
4292 if((source[i]&0x3f)==0x18) // ERET
4295 if(i_regs->regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
4296 emit_addimm(HOST_CCREG,CLOCK_ADJUST(count),HOST_CCREG); // TODO: Should there be an extra cycle here?
4297 emit_jmp((int)jump_eret);
4303 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
4313 emit_readword((int)®_cop2d[copr],tl);
4314 emit_signextend16(tl,tl);
4315 emit_writeword(tl,(int)®_cop2d[copr]); // hmh
4322 emit_readword((int)®_cop2d[copr],tl);
4323 emit_andimm(tl,0xffff,tl);
4324 emit_writeword(tl,(int)®_cop2d[copr]);
4327 emit_readword((int)®_cop2d[14],tl); // SXY2
4328 emit_writeword(tl,(int)®_cop2d[copr]);
4332 emit_readword((int)®_cop2d[9],temp);
4333 emit_testimm(temp,0x8000); // do we need this?
4334 emit_andimm(temp,0xf80,temp);
4335 emit_andne_imm(temp,0,temp);
4336 emit_shrimm(temp,7,tl);
4337 emit_readword((int)®_cop2d[10],temp);
4338 emit_testimm(temp,0x8000);
4339 emit_andimm(temp,0xf80,temp);
4340 emit_andne_imm(temp,0,temp);
4341 emit_orrshr_imm(temp,2,tl);
4342 emit_readword((int)®_cop2d[11],temp);
4343 emit_testimm(temp,0x8000);
4344 emit_andimm(temp,0xf80,temp);
4345 emit_andne_imm(temp,0,temp);
4346 emit_orrshl_imm(temp,3,tl);
4347 emit_writeword(tl,(int)®_cop2d[copr]);
4350 emit_readword((int)®_cop2d[copr],tl);
4355 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
4359 emit_readword((int)®_cop2d[13],temp); // SXY1
4360 emit_writeword(sl,(int)®_cop2d[copr]);
4361 emit_writeword(temp,(int)®_cop2d[12]); // SXY0
4362 emit_readword((int)®_cop2d[14],temp); // SXY2
4363 emit_writeword(sl,(int)®_cop2d[14]);
4364 emit_writeword(temp,(int)®_cop2d[13]); // SXY1
4367 emit_andimm(sl,0x001f,temp);
4368 emit_shlimm(temp,7,temp);
4369 emit_writeword(temp,(int)®_cop2d[9]);
4370 emit_andimm(sl,0x03e0,temp);
4371 emit_shlimm(temp,2,temp);
4372 emit_writeword(temp,(int)®_cop2d[10]);
4373 emit_andimm(sl,0x7c00,temp);
4374 emit_shrimm(temp,3,temp);
4375 emit_writeword(temp,(int)®_cop2d[11]);
4376 emit_writeword(sl,(int)®_cop2d[28]);
4380 emit_mvnmi(temp,temp);
4381 emit_clz(temp,temp);
4382 emit_writeword(sl,(int)®_cop2d[30]);
4383 emit_writeword(temp,(int)®_cop2d[31]);
4388 emit_writeword(sl,(int)®_cop2d[copr]);
4393 void cop2_assemble(int i,struct regstat *i_regs)
4395 u_int copr=(source[i]>>11)&0x1f;
4396 signed char temp=get_reg(i_regs->regmap,-1);
4397 if (opcode2[i]==0) { // MFC2
4398 signed char tl=get_reg(i_regs->regmap,rt1[i]);
4399 if(tl>=0&&rt1[i]!=0)
4400 cop2_get_dreg(copr,tl,temp);
4402 else if (opcode2[i]==4) { // MTC2
4403 signed char sl=get_reg(i_regs->regmap,rs1[i]);
4404 cop2_put_dreg(copr,sl,temp);
4406 else if (opcode2[i]==2) // CFC2
4408 signed char tl=get_reg(i_regs->regmap,rt1[i]);
4409 if(tl>=0&&rt1[i]!=0)
4410 emit_readword((int)®_cop2c[copr],tl);
4412 else if (opcode2[i]==6) // CTC2
4414 signed char sl=get_reg(i_regs->regmap,rs1[i]);
4423 emit_signextend16(sl,temp);
4426 //value = value & 0x7ffff000;
4427 //if (value & 0x7f87e000) value |= 0x80000000;
4428 emit_shrimm(sl,12,temp);
4429 emit_shlimm(temp,12,temp);
4430 emit_testimm(temp,0x7f000000);
4431 emit_testeqimm(temp,0x00870000);
4432 emit_testeqimm(temp,0x0000e000);
4433 emit_orrne_imm(temp,0x80000000,temp);
4439 emit_writeword(temp,(int)®_cop2c[copr]);
4444 static void c2op_prologue(u_int op,u_int reglist)
4446 save_regs_all(reglist);
4449 emit_call((int)pcnt_gte_start);
4451 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0); // cop2 regs
4454 static void c2op_epilogue(u_int op,u_int reglist)
4458 emit_call((int)pcnt_gte_end);
4460 restore_regs_all(reglist);
4463 static void c2op_call_MACtoIR(int lm,int need_flags)
4466 emit_call((int)(lm?gteMACtoIR_lm1:gteMACtoIR_lm0));
4468 emit_call((int)(lm?gteMACtoIR_lm1_nf:gteMACtoIR_lm0_nf));
4471 static void c2op_call_rgb_func(void *func,int lm,int need_ir,int need_flags)
4473 emit_call((int)func);
4474 // func is C code and trashes r0
4475 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
4476 if(need_flags||need_ir)
4477 c2op_call_MACtoIR(lm,need_flags);
4478 emit_call((int)(need_flags?gteMACtoRGB:gteMACtoRGB_nf));
4481 static void c2op_assemble(int i,struct regstat *i_regs)
4483 signed char temp=get_reg(i_regs->regmap,-1);
4484 u_int c2op=source[i]&0x3f;
4485 u_int hr,reglist_full=0,reglist;
4486 int need_flags,need_ir;
4487 for(hr=0;hr<HOST_REGS;hr++) {
4488 if(i_regs->regmap[hr]>=0) reglist_full|=1<<hr;
4490 reglist=reglist_full&0x100f;
4492 if (gte_handlers[c2op]!=NULL) {
4493 need_flags=!(gte_unneeded[i+1]>>63); // +1 because of how liveness detection works
4494 need_ir=(gte_unneeded[i+1]&0xe00)!=0xe00;
4495 assem_debug("gte unneeded %016llx, need_flags %d, need_ir %d\n",
4496 gte_unneeded[i+1],need_flags,need_ir);
4497 if(new_dynarec_hacks&NDHACK_GTE_NO_FLAGS)
4499 int shift = (source[i] >> 19) & 1;
4500 int lm = (source[i] >> 10) & 1;
4504 int v = (source[i] >> 15) & 3;
4505 int cv = (source[i] >> 13) & 3;
4506 int mx = (source[i] >> 17) & 3;
4507 reglist=reglist_full&0x10ff; // +{r4-r7}
4508 c2op_prologue(c2op,reglist);
4509 /* r4,r5 = VXYZ(v) packed; r6 = &MX11(mx); r7 = &CV1(cv) */
4513 emit_movzwl_indexed(9*4,0,4); // gteIR
4514 emit_movzwl_indexed(10*4,0,6);
4515 emit_movzwl_indexed(11*4,0,5);
4516 emit_orrshl_imm(6,16,4);
4519 emit_addimm(0,32*4+mx*8*4,6);
4521 emit_readword((int)&zeromem_ptr,6);
4523 emit_addimm(0,32*4+(cv*8+5)*4,7);
4525 emit_readword((int)&zeromem_ptr,7);
4527 emit_movimm(source[i],1); // opcode
4528 emit_call((int)gteMVMVA_part_neon);
4531 emit_call((int)gteMACtoIR_flags_neon);
4535 emit_call((int)gteMVMVA_part_cv3sh12_arm);
4537 emit_movimm(shift,1);
4538 emit_call((int)(need_flags?gteMVMVA_part_arm:gteMVMVA_part_nf_arm));
4540 if(need_flags||need_ir)
4541 c2op_call_MACtoIR(lm,need_flags);
4546 c2op_prologue(c2op,reglist);
4547 emit_call((int)(shift?gteOP_part_shift:gteOP_part_noshift));
4548 if(need_flags||need_ir) {
4549 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
4550 c2op_call_MACtoIR(lm,need_flags);
4554 c2op_prologue(c2op,reglist);
4555 c2op_call_rgb_func(shift?gteDPCS_part_shift:gteDPCS_part_noshift,lm,need_ir,need_flags);
4558 c2op_prologue(c2op,reglist);
4559 c2op_call_rgb_func(shift?gteINTPL_part_shift:gteINTPL_part_noshift,lm,need_ir,need_flags);
4562 c2op_prologue(c2op,reglist);
4563 emit_call((int)(shift?gteSQR_part_shift:gteSQR_part_noshift));
4564 if(need_flags||need_ir) {
4565 emit_addimm(FP,(int)&psxRegs.CP2D.r[0]-(int)&dynarec_local,0);
4566 c2op_call_MACtoIR(lm,need_flags);
4570 c2op_prologue(c2op,reglist);
4571 c2op_call_rgb_func(gteDCPL_part,lm,need_ir,need_flags);
4574 c2op_prologue(c2op,reglist);
4575 c2op_call_rgb_func(shift?gteGPF_part_shift:gteGPF_part_noshift,lm,need_ir,need_flags);
4578 c2op_prologue(c2op,reglist);
4579 c2op_call_rgb_func(shift?gteGPL_part_shift:gteGPL_part_noshift,lm,need_ir,need_flags);
4583 c2op_prologue(c2op,reglist);
4585 emit_movimm(source[i],1); // opcode
4586 emit_writeword(1,(int)&psxRegs.code);
4588 emit_call((int)(need_flags?gte_handlers[c2op]:gte_handlers_nf[c2op]));
4591 c2op_epilogue(c2op,reglist);
4595 void cop1_unusable(int i,struct regstat *i_regs)
4597 // XXX: should just just do the exception instead
4601 add_stub(FP_STUB,jaddr,(int)out,i,0,(int)i_regs,is_delayslot,0);
4606 void cop1_assemble(int i,struct regstat *i_regs)
4608 #ifndef DISABLE_COP1
4609 // Check cop1 unusable
4611 signed char rs=get_reg(i_regs->regmap,CSREG);
4613 emit_testimm(rs,0x20000000);
4616 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
4619 if (opcode2[i]==0) { // MFC1
4620 signed char tl=get_reg(i_regs->regmap,rt1[i]);
4622 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],tl);
4623 emit_readword_indexed(0,tl,tl);
4626 else if (opcode2[i]==1) { // DMFC1
4627 signed char tl=get_reg(i_regs->regmap,rt1[i]);
4628 signed char th=get_reg(i_regs->regmap,rt1[i]|64);
4630 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],tl);
4631 if(th>=0) emit_readword_indexed(4,tl,th);
4632 emit_readword_indexed(0,tl,tl);
4635 else if (opcode2[i]==4) { // MTC1
4636 signed char sl=get_reg(i_regs->regmap,rs1[i]);
4637 signed char temp=get_reg(i_regs->regmap,-1);
4638 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4639 emit_writeword_indexed(sl,0,temp);
4641 else if (opcode2[i]==5) { // DMTC1
4642 signed char sl=get_reg(i_regs->regmap,rs1[i]);
4643 signed char sh=rs1[i]>0?get_reg(i_regs->regmap,rs1[i]|64):sl;
4644 signed char temp=get_reg(i_regs->regmap,-1);
4645 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4646 emit_writeword_indexed(sh,4,temp);
4647 emit_writeword_indexed(sl,0,temp);
4649 else if (opcode2[i]==2) // CFC1
4651 signed char tl=get_reg(i_regs->regmap,rt1[i]);
4653 u_int copr=(source[i]>>11)&0x1f;
4654 if(copr==0) emit_readword((int)&FCR0,tl);
4655 if(copr==31) emit_readword((int)&FCR31,tl);
4658 else if (opcode2[i]==6) // CTC1
4660 signed char sl=get_reg(i_regs->regmap,rs1[i]);
4661 u_int copr=(source[i]>>11)&0x1f;
4665 emit_writeword(sl,(int)&FCR31);
4666 // Set the rounding mode
4668 //char temp=get_reg(i_regs->regmap,-1);
4669 //emit_andimm(sl,3,temp);
4670 //emit_fldcw_indexed((int)&rounding_modes,temp);
4674 cop1_unusable(i, i_regs);
4678 void fconv_assemble_arm(int i,struct regstat *i_regs)
4680 #ifndef DISABLE_COP1
4681 signed char temp=get_reg(i_regs->regmap,-1);
4683 // Check cop1 unusable
4685 signed char rs=get_reg(i_regs->regmap,CSREG);
4687 emit_testimm(rs,0x20000000);
4690 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
4694 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4695 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) { // trunc_w_s
4696 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4698 emit_ftosizs(15,15); // float->int, truncate
4699 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
4700 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4704 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) { // trunc_w_d
4705 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4707 emit_ftosizd(7,13); // double->int, truncate
4708 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4713 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) { // cvt_s_w
4714 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4716 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f))
4717 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4722 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) { // cvt_d_w
4723 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4725 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4731 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) { // cvt_d_s
4732 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4734 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
4739 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) { // cvt_s_d
4740 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4742 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
4752 for(hr=0;hr<HOST_REGS;hr++) {
4753 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4757 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x20) {
4758 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4759 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4760 emit_call((int)cvt_s_w);
4762 if(opcode2[i]==0x14&&(source[i]&0x3f)==0x21) {
4763 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4764 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4765 emit_call((int)cvt_d_w);
4767 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x20) {
4768 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4769 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4770 emit_call((int)cvt_s_l);
4772 if(opcode2[i]==0x15&&(source[i]&0x3f)==0x21) {
4773 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4774 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4775 emit_call((int)cvt_d_l);
4778 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x21) {
4779 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4780 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4781 emit_call((int)cvt_d_s);
4783 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x24) {
4784 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4785 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4786 emit_call((int)cvt_w_s);
4788 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x25) {
4789 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4790 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4791 emit_call((int)cvt_l_s);
4794 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x20) {
4795 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4796 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4797 emit_call((int)cvt_s_d);
4799 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x24) {
4800 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4801 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4802 emit_call((int)cvt_w_d);
4804 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x25) {
4805 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4806 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4807 emit_call((int)cvt_l_d);
4810 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x08) {
4811 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4812 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4813 emit_call((int)round_l_s);
4815 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x09) {
4816 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4817 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4818 emit_call((int)trunc_l_s);
4820 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0a) {
4821 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4822 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4823 emit_call((int)ceil_l_s);
4825 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0b) {
4826 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4827 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4828 emit_call((int)floor_l_s);
4830 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0c) {
4831 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4832 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4833 emit_call((int)round_w_s);
4835 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0d) {
4836 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4837 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4838 emit_call((int)trunc_w_s);
4840 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0e) {
4841 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4842 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4843 emit_call((int)ceil_w_s);
4845 if(opcode2[i]==0x10&&(source[i]&0x3f)==0x0f) {
4846 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4847 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4848 emit_call((int)floor_w_s);
4851 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x08) {
4852 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4853 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4854 emit_call((int)round_l_d);
4856 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x09) {
4857 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4858 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4859 emit_call((int)trunc_l_d);
4861 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0a) {
4862 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4863 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4864 emit_call((int)ceil_l_d);
4866 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0b) {
4867 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4868 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
4869 emit_call((int)floor_l_d);
4871 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0c) {
4872 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4873 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4874 emit_call((int)round_w_d);
4876 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0d) {
4877 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4878 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4879 emit_call((int)trunc_w_d);
4881 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0e) {
4882 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4883 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4884 emit_call((int)ceil_w_d);
4886 if(opcode2[i]==0x11&&(source[i]&0x3f)==0x0f) {
4887 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
4888 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
4889 emit_call((int)floor_w_d);
4892 restore_regs(reglist);
4894 cop1_unusable(i, i_regs);
4897 #define fconv_assemble fconv_assemble_arm
4899 void fcomp_assemble(int i,struct regstat *i_regs)
4901 #ifndef DISABLE_COP1
4902 signed char fs=get_reg(i_regs->regmap,FSREG);
4903 signed char temp=get_reg(i_regs->regmap,-1);
4905 // Check cop1 unusable
4907 signed char cs=get_reg(i_regs->regmap,CSREG);
4909 emit_testimm(cs,0x20000000);
4912 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
4916 if((source[i]&0x3f)==0x30) {
4917 emit_andimm(fs,~0x800000,fs);
4921 if((source[i]&0x3e)==0x38) {
4922 // sf/ngle - these should throw exceptions for NaNs
4923 emit_andimm(fs,~0x800000,fs);
4927 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
4928 if(opcode2[i]==0x10) {
4929 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
4930 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
4931 emit_orimm(fs,0x800000,fs);
4933 emit_flds(HOST_TEMPREG,15);
4936 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_s
4937 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_s
4938 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_s
4939 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_s
4940 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_s
4941 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_s
4942 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_s
4943 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_s
4944 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_s
4945 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_s
4946 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_s
4947 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_s
4948 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_s
4951 if(opcode2[i]==0x11) {
4952 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
4953 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
4954 emit_orimm(fs,0x800000,fs);
4956 emit_vldr(HOST_TEMPREG,7);
4959 if((source[i]&0x3f)==0x31) emit_bicvc_imm(fs,0x800000,fs); // c_un_d
4960 if((source[i]&0x3f)==0x32) emit_bicne_imm(fs,0x800000,fs); // c_eq_d
4961 if((source[i]&0x3f)==0x33) {emit_bicne_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ueq_d
4962 if((source[i]&0x3f)==0x34) emit_biccs_imm(fs,0x800000,fs); // c_olt_d
4963 if((source[i]&0x3f)==0x35) {emit_biccs_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ult_d
4964 if((source[i]&0x3f)==0x36) emit_bichi_imm(fs,0x800000,fs); // c_ole_d
4965 if((source[i]&0x3f)==0x37) {emit_bichi_imm(fs,0x800000,fs);emit_orrvs_imm(fs,0x800000,fs);} // c_ule_d
4966 if((source[i]&0x3f)==0x3a) emit_bicne_imm(fs,0x800000,fs); // c_seq_d
4967 if((source[i]&0x3f)==0x3b) emit_bicne_imm(fs,0x800000,fs); // c_ngl_d
4968 if((source[i]&0x3f)==0x3c) emit_biccs_imm(fs,0x800000,fs); // c_lt_d
4969 if((source[i]&0x3f)==0x3d) emit_biccs_imm(fs,0x800000,fs); // c_nge_d
4970 if((source[i]&0x3f)==0x3e) emit_bichi_imm(fs,0x800000,fs); // c_le_d
4971 if((source[i]&0x3f)==0x3f) emit_bichi_imm(fs,0x800000,fs); // c_ngt_d
4979 for(hr=0;hr<HOST_REGS;hr++) {
4980 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
4984 if(opcode2[i]==0x10) {
4985 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
4986 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
4987 if((source[i]&0x3f)==0x30) emit_call((int)c_f_s);
4988 if((source[i]&0x3f)==0x31) emit_call((int)c_un_s);
4989 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_s);
4990 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_s);
4991 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_s);
4992 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_s);
4993 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_s);
4994 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_s);
4995 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_s);
4996 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_s);
4997 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_s);
4998 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_s);
4999 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_s);
5000 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_s);
5001 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_s);
5002 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_s);
5004 if(opcode2[i]==0x11) {
5005 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
5006 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
5007 if((source[i]&0x3f)==0x30) emit_call((int)c_f_d);
5008 if((source[i]&0x3f)==0x31) emit_call((int)c_un_d);
5009 if((source[i]&0x3f)==0x32) emit_call((int)c_eq_d);
5010 if((source[i]&0x3f)==0x33) emit_call((int)c_ueq_d);
5011 if((source[i]&0x3f)==0x34) emit_call((int)c_olt_d);
5012 if((source[i]&0x3f)==0x35) emit_call((int)c_ult_d);
5013 if((source[i]&0x3f)==0x36) emit_call((int)c_ole_d);
5014 if((source[i]&0x3f)==0x37) emit_call((int)c_ule_d);
5015 if((source[i]&0x3f)==0x38) emit_call((int)c_sf_d);
5016 if((source[i]&0x3f)==0x39) emit_call((int)c_ngle_d);
5017 if((source[i]&0x3f)==0x3a) emit_call((int)c_seq_d);
5018 if((source[i]&0x3f)==0x3b) emit_call((int)c_ngl_d);
5019 if((source[i]&0x3f)==0x3c) emit_call((int)c_lt_d);
5020 if((source[i]&0x3f)==0x3d) emit_call((int)c_nge_d);
5021 if((source[i]&0x3f)==0x3e) emit_call((int)c_le_d);
5022 if((source[i]&0x3f)==0x3f) emit_call((int)c_ngt_d);
5024 restore_regs(reglist);
5025 emit_loadreg(FSREG,fs);
5027 cop1_unusable(i, i_regs);
5031 void float_assemble(int i,struct regstat *i_regs)
5033 #ifndef DISABLE_COP1
5034 signed char temp=get_reg(i_regs->regmap,-1);
5036 // Check cop1 unusable
5038 signed char cs=get_reg(i_regs->regmap,CSREG);
5040 emit_testimm(cs,0x20000000);
5043 add_stub(FP_STUB,jaddr,(int)out,i,cs,(int)i_regs,is_delayslot,0);
5047 #if(defined(__VFP_FP__) && !defined(__SOFTFP__))
5048 if((source[i]&0x3f)==6) // mov
5050 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5051 if(opcode2[i]==0x10) {
5052 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
5053 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],HOST_TEMPREG);
5054 emit_readword_indexed(0,temp,temp);
5055 emit_writeword_indexed(temp,0,HOST_TEMPREG);
5057 if(opcode2[i]==0x11) {
5058 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
5059 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],HOST_TEMPREG);
5061 emit_vstr(7,HOST_TEMPREG);
5067 if((source[i]&0x3f)>3)
5069 if(opcode2[i]==0x10) {
5070 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
5072 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5073 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
5075 if((source[i]&0x3f)==4) // sqrt
5077 if((source[i]&0x3f)==5) // abs
5079 if((source[i]&0x3f)==7) // neg
5083 if(opcode2[i]==0x11) {
5084 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
5086 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5087 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
5089 if((source[i]&0x3f)==4) // sqrt
5091 if((source[i]&0x3f)==5) // abs
5093 if((source[i]&0x3f)==7) // neg
5099 if((source[i]&0x3f)<4)
5101 if(opcode2[i]==0x10) {
5102 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],temp);
5104 if(opcode2[i]==0x11) {
5105 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],temp);
5107 if(((source[i]>>11)&0x1f)!=((source[i]>>16)&0x1f)) {
5108 if(opcode2[i]==0x10) {
5109 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],HOST_TEMPREG);
5111 emit_flds(HOST_TEMPREG,13);
5112 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5113 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
5114 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
5117 if((source[i]&0x3f)==0) emit_fadds(15,13,15);
5118 if((source[i]&0x3f)==1) emit_fsubs(15,13,15);
5119 if((source[i]&0x3f)==2) emit_fmuls(15,13,15);
5120 if((source[i]&0x3f)==3) emit_fdivs(15,13,15);
5121 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
5122 emit_fsts(15,HOST_TEMPREG);
5127 else if(opcode2[i]==0x11) {
5128 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],HOST_TEMPREG);
5130 emit_vldr(HOST_TEMPREG,6);
5131 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5132 if(((source[i]>>16)&0x1f)!=((source[i]>>6)&0x1f)) {
5133 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
5136 if((source[i]&0x3f)==0) emit_faddd(7,6,7);
5137 if((source[i]&0x3f)==1) emit_fsubd(7,6,7);
5138 if((source[i]&0x3f)==2) emit_fmuld(7,6,7);
5139 if((source[i]&0x3f)==3) emit_fdivd(7,6,7);
5140 if(((source[i]>>16)&0x1f)==((source[i]>>6)&0x1f)) {
5141 emit_vstr(7,HOST_TEMPREG);
5148 if(opcode2[i]==0x10) {
5150 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5151 emit_readword((int)®_cop1_simple[(source[i]>>6)&0x1f],temp);
5153 if((source[i]&0x3f)==0) emit_fadds(15,15,15);
5154 if((source[i]&0x3f)==1) emit_fsubs(15,15,15);
5155 if((source[i]&0x3f)==2) emit_fmuls(15,15,15);
5156 if((source[i]&0x3f)==3) emit_fdivs(15,15,15);
5159 else if(opcode2[i]==0x11) {
5161 if(((source[i]>>11)&0x1f)!=((source[i]>>6)&0x1f)) {
5162 emit_readword((int)®_cop1_double[(source[i]>>6)&0x1f],temp);
5164 if((source[i]&0x3f)==0) emit_faddd(7,7,7);
5165 if((source[i]&0x3f)==1) emit_fsubd(7,7,7);
5166 if((source[i]&0x3f)==2) emit_fmuld(7,7,7);
5167 if((source[i]&0x3f)==3) emit_fdivd(7,7,7);
5176 for(hr=0;hr<HOST_REGS;hr++) {
5177 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
5179 if(opcode2[i]==0x10) { // Single precision
5181 emit_readword((int)®_cop1_simple[(source[i]>>11)&0x1f],ARG1_REG);
5182 if((source[i]&0x3f)<4) {
5183 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],ARG2_REG);
5184 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG3_REG);
5186 emit_readword((int)®_cop1_simple[(source[i]>> 6)&0x1f],ARG2_REG);
5188 switch(source[i]&0x3f)
5190 case 0x00: emit_call((int)add_s);break;
5191 case 0x01: emit_call((int)sub_s);break;
5192 case 0x02: emit_call((int)mul_s);break;
5193 case 0x03: emit_call((int)div_s);break;
5194 case 0x04: emit_call((int)sqrt_s);break;
5195 case 0x05: emit_call((int)abs_s);break;
5196 case 0x06: emit_call((int)mov_s);break;
5197 case 0x07: emit_call((int)neg_s);break;
5199 restore_regs(reglist);
5201 if(opcode2[i]==0x11) { // Double precision
5203 emit_readword((int)®_cop1_double[(source[i]>>11)&0x1f],ARG1_REG);
5204 if((source[i]&0x3f)<4) {
5205 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],ARG2_REG);
5206 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG3_REG);
5208 emit_readword((int)®_cop1_double[(source[i]>> 6)&0x1f],ARG2_REG);
5210 switch(source[i]&0x3f)
5212 case 0x00: emit_call((int)add_d);break;
5213 case 0x01: emit_call((int)sub_d);break;
5214 case 0x02: emit_call((int)mul_d);break;
5215 case 0x03: emit_call((int)div_d);break;
5216 case 0x04: emit_call((int)sqrt_d);break;
5217 case 0x05: emit_call((int)abs_d);break;
5218 case 0x06: emit_call((int)mov_d);break;
5219 case 0x07: emit_call((int)neg_d);break;
5221 restore_regs(reglist);
5224 cop1_unusable(i, i_regs);
5228 void multdiv_assemble_arm(int i,struct regstat *i_regs)
5235 // case 0x1D: DMULTU
5240 if((opcode2[i]&4)==0) // 32-bit
5242 if(opcode2[i]==0x18) // MULT
5244 signed char m1=get_reg(i_regs->regmap,rs1[i]);
5245 signed char m2=get_reg(i_regs->regmap,rs2[i]);
5246 signed char hi=get_reg(i_regs->regmap,HIREG);
5247 signed char lo=get_reg(i_regs->regmap,LOREG);
5252 emit_smull(m1,m2,hi,lo);
5254 if(opcode2[i]==0x19) // MULTU
5256 signed char m1=get_reg(i_regs->regmap,rs1[i]);
5257 signed char m2=get_reg(i_regs->regmap,rs2[i]);
5258 signed char hi=get_reg(i_regs->regmap,HIREG);
5259 signed char lo=get_reg(i_regs->regmap,LOREG);
5264 emit_umull(m1,m2,hi,lo);
5266 if(opcode2[i]==0x1A) // DIV
5268 signed char d1=get_reg(i_regs->regmap,rs1[i]);
5269 signed char d2=get_reg(i_regs->regmap,rs2[i]);
5272 signed char quotient=get_reg(i_regs->regmap,LOREG);
5273 signed char remainder=get_reg(i_regs->regmap,HIREG);
5274 assert(quotient>=0);
5275 assert(remainder>=0);
5276 emit_movs(d1,remainder);
5277 emit_movimm(0xffffffff,quotient);
5278 emit_negmi(quotient,quotient); // .. quotient and ..
5279 emit_negmi(remainder,remainder); // .. remainder for div0 case (will be negated back after jump)
5280 emit_movs(d2,HOST_TEMPREG);
5281 emit_jeq((int)out+52); // Division by zero
5282 emit_negmi(HOST_TEMPREG,HOST_TEMPREG);
5283 emit_clz(HOST_TEMPREG,quotient);
5284 emit_shl(HOST_TEMPREG,quotient,HOST_TEMPREG);
5285 emit_orimm(quotient,1<<31,quotient);
5286 emit_shr(quotient,quotient,quotient);
5287 emit_cmp(remainder,HOST_TEMPREG);
5288 emit_subcs(remainder,HOST_TEMPREG,remainder);
5289 emit_adcs(quotient,quotient,quotient);
5290 emit_shrimm(HOST_TEMPREG,1,HOST_TEMPREG);
5291 emit_jcc((int)out-16); // -4
5293 emit_negmi(quotient,quotient);
5295 emit_negmi(remainder,remainder);
5297 if(opcode2[i]==0x1B) // DIVU
5299 signed char d1=get_reg(i_regs->regmap,rs1[i]); // dividend
5300 signed char d2=get_reg(i_regs->regmap,rs2[i]); // divisor
5303 signed char quotient=get_reg(i_regs->regmap,LOREG);
5304 signed char remainder=get_reg(i_regs->regmap,HIREG);
5305 assert(quotient>=0);
5306 assert(remainder>=0);
5307 emit_mov(d1,remainder);
5308 emit_movimm(0xffffffff,quotient); // div0 case
5310 emit_jeq((int)out+40); // Division by zero
5311 emit_clz(d2,HOST_TEMPREG);
5312 emit_movimm(1<<31,quotient);
5313 emit_shl(d2,HOST_TEMPREG,d2);
5314 emit_shr(quotient,HOST_TEMPREG,quotient);
5315 emit_cmp(remainder,d2);
5316 emit_subcs(remainder,d2,remainder);
5317 emit_adcs(quotient,quotient,quotient);
5318 emit_shrcc_imm(d2,1,d2);
5319 emit_jcc((int)out-16); // -4
5325 if(opcode2[i]==0x1C) // DMULT
5327 assert(opcode2[i]!=0x1C);
5328 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
5329 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
5330 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
5331 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
5340 emit_call((int)&mult64);
5345 signed char hih=get_reg(i_regs->regmap,HIREG|64);
5346 signed char hil=get_reg(i_regs->regmap,HIREG);
5347 if(hih>=0) emit_loadreg(HIREG|64,hih);
5348 if(hil>=0) emit_loadreg(HIREG,hil);
5349 signed char loh=get_reg(i_regs->regmap,LOREG|64);
5350 signed char lol=get_reg(i_regs->regmap,LOREG);
5351 if(loh>=0) emit_loadreg(LOREG|64,loh);
5352 if(lol>=0) emit_loadreg(LOREG,lol);
5354 if(opcode2[i]==0x1D) // DMULTU
5356 signed char m1h=get_reg(i_regs->regmap,rs1[i]|64);
5357 signed char m1l=get_reg(i_regs->regmap,rs1[i]);
5358 signed char m2h=get_reg(i_regs->regmap,rs2[i]|64);
5359 signed char m2l=get_reg(i_regs->regmap,rs2[i]);
5365 if(m1l!=0) emit_mov(m1l,0);
5366 if(m1h==0) emit_readword((int)&dynarec_local,1);
5367 else if(m1h>1) emit_mov(m1h,1);
5368 if(m2l<2) emit_readword((int)&dynarec_local+m2l*4,2);
5369 else if(m2l>2) emit_mov(m2l,2);
5370 if(m2h<3) emit_readword((int)&dynarec_local+m2h*4,3);
5371 else if(m2h>3) emit_mov(m2h,3);
5372 emit_call((int)&multu64);
5373 restore_regs(0x100f);
5374 signed char hih=get_reg(i_regs->regmap,HIREG|64);
5375 signed char hil=get_reg(i_regs->regmap,HIREG);
5376 signed char loh=get_reg(i_regs->regmap,LOREG|64);
5377 signed char lol=get_reg(i_regs->regmap,LOREG);
5378 /*signed char temp=get_reg(i_regs->regmap,-1);
5379 signed char rh=get_reg(i_regs->regmap,HIREG|64);
5380 signed char rl=get_reg(i_regs->regmap,HIREG);
5386 //emit_mov(m1l,EAX);
5388 emit_umull(rl,rh,m1l,m2l);
5389 emit_storereg(LOREG,rl);
5391 //emit_mov(m1h,EAX);
5393 emit_umull(rl,rh,m1h,m2l);
5394 emit_adds(rl,temp,temp);
5395 emit_adcimm(rh,0,rh);
5396 emit_storereg(HIREG,rh);
5397 //emit_mov(m2h,EAX);
5399 emit_umull(rl,rh,m1l,m2h);
5400 emit_adds(rl,temp,temp);
5401 emit_adcimm(rh,0,rh);
5402 emit_storereg(LOREG|64,temp);
5404 //emit_mov(m2h,EAX);
5406 emit_umull(rl,rh,m1h,m2h);
5407 emit_adds(rl,temp,rl);
5408 emit_loadreg(HIREG,temp);
5409 emit_adcimm(rh,0,rh);
5410 emit_adds(rl,temp,rl);
5411 emit_adcimm(rh,0,rh);
5418 emit_call((int)&multu64);
5423 signed char hih=get_reg(i_regs->regmap,HIREG|64);
5424 signed char hil=get_reg(i_regs->regmap,HIREG);
5425 if(hih>=0) emit_loadreg(HIREG|64,hih); // DEBUG
5426 if(hil>=0) emit_loadreg(HIREG,hil); // DEBUG
5428 // Shouldn't be necessary
5429 //char loh=get_reg(i_regs->regmap,LOREG|64);
5430 //char lol=get_reg(i_regs->regmap,LOREG);
5431 //if(loh>=0) emit_loadreg(LOREG|64,loh);
5432 //if(lol>=0) emit_loadreg(LOREG,lol);
5434 if(opcode2[i]==0x1E) // DDIV
5436 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
5437 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
5438 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
5439 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
5445 if(d1l!=0) emit_mov(d1l,0);
5446 if(d1h==0) emit_readword((int)&dynarec_local,1);
5447 else if(d1h>1) emit_mov(d1h,1);
5448 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
5449 else if(d2l>2) emit_mov(d2l,2);
5450 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
5451 else if(d2h>3) emit_mov(d2h,3);
5452 emit_call((int)&div64);
5453 restore_regs(0x100f);
5454 signed char hih=get_reg(i_regs->regmap,HIREG|64);
5455 signed char hil=get_reg(i_regs->regmap,HIREG);
5456 signed char loh=get_reg(i_regs->regmap,LOREG|64);
5457 signed char lol=get_reg(i_regs->regmap,LOREG);
5458 if(hih>=0) emit_loadreg(HIREG|64,hih);
5459 if(hil>=0) emit_loadreg(HIREG,hil);
5460 if(loh>=0) emit_loadreg(LOREG|64,loh);
5461 if(lol>=0) emit_loadreg(LOREG,lol);
5463 if(opcode2[i]==0x1F) // DDIVU
5465 //u_int hr,reglist=0;
5466 //for(hr=0;hr<HOST_REGS;hr++) {
5467 // if(i_regs->regmap[hr]>=0 && (i_regs->regmap[hr]&62)!=HIREG) reglist|=1<<hr;
5469 signed char d1h=get_reg(i_regs->regmap,rs1[i]|64);
5470 signed char d1l=get_reg(i_regs->regmap,rs1[i]);
5471 signed char d2h=get_reg(i_regs->regmap,rs2[i]|64);
5472 signed char d2l=get_reg(i_regs->regmap,rs2[i]);
5478 if(d1l!=0) emit_mov(d1l,0);
5479 if(d1h==0) emit_readword((int)&dynarec_local,1);
5480 else if(d1h>1) emit_mov(d1h,1);
5481 if(d2l<2) emit_readword((int)&dynarec_local+d2l*4,2);
5482 else if(d2l>2) emit_mov(d2l,2);
5483 if(d2h<3) emit_readword((int)&dynarec_local+d2h*4,3);
5484 else if(d2h>3) emit_mov(d2h,3);
5485 emit_call((int)&divu64);
5486 restore_regs(0x100f);
5487 signed char hih=get_reg(i_regs->regmap,HIREG|64);
5488 signed char hil=get_reg(i_regs->regmap,HIREG);
5489 signed char loh=get_reg(i_regs->regmap,LOREG|64);
5490 signed char lol=get_reg(i_regs->regmap,LOREG);
5491 if(hih>=0) emit_loadreg(HIREG|64,hih);
5492 if(hil>=0) emit_loadreg(HIREG,hil);
5493 if(loh>=0) emit_loadreg(LOREG|64,loh);
5494 if(lol>=0) emit_loadreg(LOREG,lol);
5503 // Multiply by zero is zero.
5504 // MIPS does not have a divide by zero exception.
5505 // The result is undefined, we return zero.
5506 signed char hr=get_reg(i_regs->regmap,HIREG);
5507 signed char lr=get_reg(i_regs->regmap,LOREG);
5508 if(hr>=0) emit_zeroreg(hr);
5509 if(lr>=0) emit_zeroreg(lr);
5512 #define multdiv_assemble multdiv_assemble_arm
5514 void do_preload_rhash(int r) {
5515 // Don't need this for ARM. On x86, this puts the value 0xf8 into the
5516 // register. On ARM the hash can be done with a single instruction (below)
5519 void do_preload_rhtbl(int ht) {
5520 emit_addimm(FP,(int)&mini_ht-(int)&dynarec_local,ht);
5523 void do_rhash(int rs,int rh) {
5524 emit_andimm(rs,0xf8,rh);
5527 void do_miniht_load(int ht,int rh) {
5528 assem_debug("ldr %s,[%s,%s]!\n",regname[rh],regname[ht],regname[rh]);
5529 output_w32(0xe7b00000|rd_rn_rm(rh,ht,rh));
5532 void do_miniht_jump(int rs,int rh,int ht) {
5534 emit_ldreq_indexed(ht,4,15);
5535 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5537 emit_jmp(jump_vaddr_reg[7]);
5539 emit_jmp(jump_vaddr_reg[rs]);
5543 void do_miniht_insert(u_int return_address,int rt,int temp) {
5545 emit_movimm(return_address,rt); // PC into link register
5546 add_to_linker((int)out,return_address,1);
5547 emit_pcreladdr(temp);
5548 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
5549 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
5551 emit_movw(return_address&0x0000FFFF,rt);
5552 add_to_linker((int)out,return_address,1);
5553 emit_pcreladdr(temp);
5554 emit_writeword(temp,(int)&mini_ht[(return_address&0xFF)>>3][1]);
5555 emit_movt(return_address&0xFFFF0000,rt);
5556 emit_writeword(rt,(int)&mini_ht[(return_address&0xFF)>>3][0]);
5560 // Sign-extend to 64 bits and write out upper half of a register
5561 // This is useful where we have a 32-bit value in a register, and want to
5562 // keep it in a 32-bit register, but can't guarantee that it won't be read
5563 // as a 64-bit value later.
5564 void wb_sx(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32_pre,uint64_t is32,uint64_t u,uint64_t uu)
5567 if(is32_pre==is32) return;
5569 for(hr=0;hr<HOST_REGS;hr++) {
5570 if(hr!=EXCLUDE_REG) {
5571 //if(pre[hr]==entry[hr]) {
5572 if((reg=pre[hr])>=0) {
5574 if( ((is32_pre&~is32&~uu)>>reg)&1 ) {
5575 emit_sarimm(hr,31,HOST_TEMPREG);
5576 emit_storereg(reg|64,HOST_TEMPREG);
5586 void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t is32_pre,uint64_t u,uint64_t uu)
5588 //if(dirty_pre==dirty) return;
5590 for(hr=0;hr<HOST_REGS;hr++) {
5591 if(hr!=EXCLUDE_REG) {
5593 if(((~u)>>(reg&63))&1) {
5595 if(((dirty_pre&~dirty)>>hr)&1) {
5597 emit_storereg(reg,hr);
5598 if( ((is32_pre&~uu)>>reg)&1 ) {
5599 emit_sarimm(hr,31,HOST_TEMPREG);
5600 emit_storereg(reg|64,HOST_TEMPREG);
5604 emit_storereg(reg,hr);
5614 /* using strd could possibly help but you'd have to allocate registers in pairs
5615 void wb_invalidate_arm(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,uint64_t u,uint64_t uu)
5619 for(hr=HOST_REGS-1;hr>=0;hr--) {
5620 if(hr!=EXCLUDE_REG) {
5621 if(pre[hr]!=entry[hr]) {
5624 if(get_reg(entry,pre[hr])<0) {
5626 if(!((u>>pre[hr])&1)) {
5627 if(hr<10&&(~hr&1)&&(pre[hr+1]<0||wrote==hr+1)) {
5628 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
5629 emit_sarimm(hr,31,hr+1);
5630 emit_strdreg(pre[hr],hr);
5633 emit_storereg(pre[hr],hr);
5635 emit_storereg(pre[hr],hr);
5636 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
5637 emit_sarimm(hr,31,hr);
5638 emit_storereg(pre[hr]|64,hr);
5643 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
5644 emit_storereg(pre[hr],hr);
5654 for(hr=0;hr<HOST_REGS;hr++) {
5655 if(hr!=EXCLUDE_REG) {
5656 if(pre[hr]!=entry[hr]) {
5659 if((nr=get_reg(entry,pre[hr]))>=0) {
5667 #define wb_invalidate wb_invalidate_arm
5670 // Clearing the cache is rather slow on ARM Linux, so mark the areas
5671 // that need to be cleared, and then only clear these areas once.
5672 void do_clear_cache()
5675 for (i=0;i<(1<<(TARGET_SIZE_2-17));i++)
5677 u_int bitmap=needs_clear_cache[i];
5683 start=BASE_ADDR+i*131072+j*4096;
5691 __clear_cache((void *)start,(void *)end);
5697 needs_clear_cache[i]=0;
5702 // CPU-architecture-specific initialization
5704 #ifndef DISABLE_COP1
5705 rounding_modes[0]=0x0<<22; // round
5706 rounding_modes[1]=0x3<<22; // trunc
5707 rounding_modes[2]=0x1<<22; // ceil
5708 rounding_modes[3]=0x2<<22; // floor
5712 // vim:shiftwidth=2:expandtab