1 #include "new_dynarec.h"
4 #ifndef __ARM_ARCH_7A__
8 extern char invalid_code[0x100000];
17 /* same as psxRegs.GPR.n.* */
20 /* same as psxRegs.CP0.n.* */
21 extern int reg_cop0[];
22 #define Status psxRegs.CP0.n.Status
23 #define Cause psxRegs.CP0.n.Cause
24 #define EPC psxRegs.CP0.n.EPC
25 #define BadVAddr psxRegs.CP0.n.BadVAddr
26 #define Context psxRegs.CP0.n.Context
27 #define EntryHi psxRegs.CP0.n.EntryHi
28 #define Count psxRegs.cycle // psxRegs.CP0.n.Count
31 extern int reg_cop2d[], reg_cop2c[];
32 extern void *gte_handlers[64];
33 extern void *gte_handlers_nf[64];
34 extern const char *gte_regnames[64];
35 extern const char gte_cycletab[64];
38 extern int FCR0, FCR31;
41 extern void (*readmem[0x10000])();
42 extern void (*readmemb[0x10000])();
43 extern void (*readmemh[0x10000])();
44 extern void (*writemem[0x10000])();
45 extern void (*writememb[0x10000])();
46 extern void (*writememh[0x10000])();
48 extern unsigned int address;
49 extern unsigned int readmem_word; /* same as readmem_dword */
50 extern unsigned int word; /* write */
51 extern unsigned short hword;
52 extern unsigned char byte;
54 extern void *psxH_ptr;
56 // same as invalid_code, just a region for ram write checks (inclusive)
57 extern u32 inv_code_start, inv_code_end;
60 extern unsigned int next_interupt;
61 extern int pending_exception;
64 void pcsx_mtc0(u32 reg);
65 void pcsx_mtc0_ds(u32 reg);
68 extern void (*psxHLEt[])();