1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * linkage_arm.s for PCSX *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "arm_features.h"
23 #include "new_dynarec_config.h"
24 #include "linkage_offsets.h"
28 #define dynarec_local ESYM(dynarec_local)
29 #define ndrc_add_jump_out ESYM(ndrc_add_jump_out)
30 #define ndrc_get_addr_ht ESYM(ndrc_get_addr_ht)
31 #define ndrc_get_addr_ht_param ESYM(ndrc_get_addr_ht_param)
32 #define ndrc_write_invalidate_one ESYM(ndrc_write_invalidate_one)
33 #define gen_interupt ESYM(gen_interupt)
34 #define gteCheckStallRaw ESYM(gteCheckStallRaw)
35 #define psxException ESYM(psxException)
36 #define execI ESYM(execI)
42 .type dynarec_local, %object
43 .size dynarec_local, LO_dynarec_local_size
45 .space LO_dynarec_local_size
47 #define DRC_VAR_(name, vname, size_) \
48 vname = dynarec_local + LO_##name; \
50 .type vname, %object; \
53 #define DRC_VAR(name, size_) \
54 DRC_VAR_(name, ESYM(name), size_)
56 DRC_VAR(next_interupt, 4)
57 DRC_VAR(cycle_count, 4)
58 DRC_VAR(last_count, 4)
59 DRC_VAR(pending_exception, 4)
61 DRC_VAR(branch_target, 4)
64 DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
70 DRC_VAR(reg_cop0, 128)
71 DRC_VAR(reg_cop2d, 128)
72 DRC_VAR(reg_cop2c, 128)
76 @DRC_VAR(interrupt, 4)
77 @DRC_VAR(intCycle, 256)
80 DRC_VAR(inv_code_start, 4)
81 DRC_VAR(inv_code_end, 4)
85 DRC_VAR(zeromem_ptr, 4)
87 DRC_VAR(scratch_buf_ptr, 4)
88 DRC_VAR(ram_offset, 4)
103 .macro load_varadr reg var
104 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
105 movw \reg, #:lower16:(\var-(1678f+8))
106 movt \reg, #:upper16:(\var-(1678f+8))
109 #elif defined(HAVE_ARMV7) && !defined(__PIC__)
110 movw \reg, #:lower16:\var
111 movt \reg, #:upper16:\var
117 .macro load_varadr_ext reg var
118 #if defined(HAVE_ARMV7) && defined(TEXRELS_FORBIDDEN)
119 movw \reg, #:lower16:(ptr_\var-(1678f+8))
120 movt \reg, #:upper16:(ptr_\var-(1678f+8))
124 load_varadr \reg \var
128 .macro mov_16 reg imm
132 mov \reg, #(\imm & 0x00ff)
133 orr \reg, #(\imm & 0xff00)
137 .macro mov_24 reg imm
139 movw \reg, #(\imm & 0xffff)
140 movt \reg, #(\imm >> 16)
142 mov \reg, #(\imm & 0x0000ff)
143 orr \reg, #(\imm & 0x00ff00)
144 orr \reg, #(\imm & 0xff0000)
148 FUNCTION(dyna_linker):
149 /* r0 = virtual target address */
150 /* r1 = pointer to an instruction to patch */
151 #ifndef NO_WRITE_EXEC
157 /* must not compile - that might expire the caller block */
159 bl ndrc_get_addr_ht_param
163 add r6, r5, r6, asr #6 /* old target */
165 moveq pc, r0 /* Stale i-cache */
171 and r1, r7, #0xff000000
174 add r1, r1, r2, lsr #8
180 /* XXX: should be able to do better than this... */
184 .size dyna_linker, .-dyna_linker
187 FUNCTION(jump_vaddr_r1):
190 .size jump_vaddr_r1, .-jump_vaddr_r1
191 FUNCTION(jump_vaddr_r2):
194 .size jump_vaddr_r2, .-jump_vaddr_r2
195 FUNCTION(jump_vaddr_r3):
198 .size jump_vaddr_r3, .-jump_vaddr_r3
199 FUNCTION(jump_vaddr_r4):
202 .size jump_vaddr_r4, .-jump_vaddr_r4
203 FUNCTION(jump_vaddr_r5):
206 .size jump_vaddr_r5, .-jump_vaddr_r5
207 FUNCTION(jump_vaddr_r6):
210 .size jump_vaddr_r6, .-jump_vaddr_r6
211 FUNCTION(jump_vaddr_r8):
214 .size jump_vaddr_r8, .-jump_vaddr_r8
215 FUNCTION(jump_vaddr_r9):
218 .size jump_vaddr_r9, .-jump_vaddr_r9
219 FUNCTION(jump_vaddr_r10):
222 .size jump_vaddr_r10, .-jump_vaddr_r10
223 FUNCTION(jump_vaddr_r12):
226 .size jump_vaddr_r12, .-jump_vaddr_r12
227 FUNCTION(jump_vaddr_r7):
229 .size jump_vaddr_r7, .-jump_vaddr_r7
230 FUNCTION(jump_vaddr_r0):
233 .size jump_vaddr_r0, .-jump_vaddr_r0
236 FUNCTION(cc_interrupt):
237 ldr r0, [fp, #LO_last_count]
240 str r1, [fp, #LO_pending_exception]
241 str r10, [fp, #LO_cycle] /* PCSX cycles */
244 add r0, fp, #LO_reg_cop0 /* CP0 */
247 ldr r10, [fp, #LO_cycle]
248 ldr r0, [fp, #LO_next_interupt]
249 ldr r1, [fp, #LO_pending_exception]
250 ldr r2, [fp, #LO_stop]
251 str r0, [fp, #LO_last_count]
254 ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
257 ldr r0, [fp, #LO_pcaddr]
260 .size cc_interrupt, .-cc_interrupt
263 FUNCTION(jump_addrerror_ds): /* R3000E_AdEL / R3000E_AdES in r0 */
264 str r1, [fp, #(LO_psxRegs + (34+8)*4)] /* BadVaddr */
267 FUNCTION(jump_addrerror):
268 str r1, [fp, #(LO_psxRegs + (34+8)*4)] /* BadVaddr */
271 FUNCTION(jump_overflow_ds):
272 mov r0, #(12<<2) /* R3000E_Ov */
275 FUNCTION(jump_overflow):
279 FUNCTION(jump_break_ds):
280 mov r0, #(9<<2) /* R3000E_Bp */
283 FUNCTION(jump_break):
287 FUNCTION(jump_syscall_ds):
288 mov r0, #(8<<2) /* R3000E_Syscall */
291 FUNCTION(jump_syscall):
296 ldr r3, [fp, #LO_last_count]
297 str r2, [fp, #LO_pcaddr]
299 str r10, [fp, #LO_cycle] /* PCSX cycles */
300 add r2, fp, #LO_reg_cop0 /* CP0 */
303 /* note: psxException might do recursive recompiler call from it's HLE code,
304 * so be ready for this */
305 FUNCTION(jump_to_new_pc):
306 ldr r2, [fp, #LO_stop]
307 ldr r1, [fp, #LO_next_interupt]
308 ldr r10, [fp, #LO_cycle]
309 ldr r0, [fp, #LO_pcaddr]
311 str r1, [fp, #LO_last_count]
316 .size jump_to_new_pc, .-jump_to_new_pc
319 FUNCTION(new_dyna_leave):
320 ldr r0, [fp, #LO_last_count]
322 str r10, [fp, #LO_cycle]
323 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
324 .size new_dyna_leave, .-new_dyna_leave
327 FUNCTION(invalidate_addr_r0):
328 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
329 b invalidate_addr_call
330 .size invalidate_addr_r0, .-invalidate_addr_r0
332 FUNCTION(invalidate_addr_r1):
333 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
335 b invalidate_addr_call
336 .size invalidate_addr_r1, .-invalidate_addr_r1
338 FUNCTION(invalidate_addr_r2):
339 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
341 b invalidate_addr_call
342 .size invalidate_addr_r2, .-invalidate_addr_r2
344 FUNCTION(invalidate_addr_r3):
345 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
347 b invalidate_addr_call
348 .size invalidate_addr_r3, .-invalidate_addr_r3
350 FUNCTION(invalidate_addr_r4):
351 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
353 b invalidate_addr_call
354 .size invalidate_addr_r4, .-invalidate_addr_r4
356 FUNCTION(invalidate_addr_r5):
357 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
359 b invalidate_addr_call
360 .size invalidate_addr_r5, .-invalidate_addr_r5
362 FUNCTION(invalidate_addr_r6):
363 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
365 b invalidate_addr_call
366 .size invalidate_addr_r6, .-invalidate_addr_r6
368 FUNCTION(invalidate_addr_r7):
369 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
371 b invalidate_addr_call
372 .size invalidate_addr_r7, .-invalidate_addr_r7
374 FUNCTION(invalidate_addr_r8):
375 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
377 b invalidate_addr_call
378 .size invalidate_addr_r8, .-invalidate_addr_r8
380 FUNCTION(invalidate_addr_r9):
381 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
383 b invalidate_addr_call
384 .size invalidate_addr_r9, .-invalidate_addr_r9
386 FUNCTION(invalidate_addr_r10):
387 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
389 b invalidate_addr_call
390 .size invalidate_addr_r10, .-invalidate_addr_r10
392 FUNCTION(invalidate_addr_r12):
393 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
395 .size invalidate_addr_r12, .-invalidate_addr_r12
397 invalidate_addr_call:
398 ldr r12, [fp, #LO_inv_code_start]
399 ldr lr, [fp, #LO_inv_code_end]
402 blcc ndrc_write_invalidate_one
403 ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
404 .size invalidate_addr_call, .-invalidate_addr_call
407 FUNCTION(new_dyna_start):
408 /* ip is stored to conform EABI alignment */
409 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
410 mov fp, r0 /* dynarec_local */
411 ldr r0, [fp, #LO_pcaddr]
413 ldr r1, [fp, #LO_next_interupt]
414 ldr r10, [fp, #LO_cycle]
415 str r1, [fp, #LO_last_count]
418 .size new_dyna_start, .-new_dyna_start
420 /* --------------------------------------- */
422 .macro memhandler_post
423 /* r2 = cycles_out, r3 = tmp */
424 ldr r3, [fp, #LO_next_interupt]
425 ldr r2, [fp, #LO_cycle] @ memhandlers can modify cc, like dma
426 str r3, [fp, #LO_last_count]
432 .macro pcsx_read_mem_part readop tab_shift
433 /* r0 = address, r1 = handler_tab, r2 = cycles */
435 lsr r3, #(20+\tab_shift)
436 ldr r12, [fp, #LO_last_count]
437 ldr r1, [r1, r3, lsl #2]
444 \readop r0, [r1, r3, lsl #\tab_shift]
448 str r12, [fp, #LO_cycle]
451 FUNCTION(jump_handler_read8):
452 add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
453 pcsx_read_mem_part ldrbcc, 0
454 bx r1 @ addr, unused, cycles
456 FUNCTION(jump_handler_read16):
457 add r1, #0x1000/4*4 @ shift to r16 part
458 pcsx_read_mem_part ldrhcc, 1
459 bx r1 @ addr, unused, cycles
461 FUNCTION(jump_handler_read32):
462 pcsx_read_mem_part ldrcc, 2
463 bx r1 @ addr, unused, cycles
465 str lr, [fp, #LO_saved_lr]
467 ldr lr, [fp, #LO_saved_lr]
472 .macro pcsx_write_mem wrtop tab_shift
473 /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
475 lsr r12, #(20+\tab_shift)
476 ldr r3, [r3, r12, lsl #2]
477 str r0, [fp, #LO_address] @ some handlers still need it..
483 \wrtop r1, [r3, r12, lsl #\tab_shift]
486 ldr r12, [fp, #LO_last_count]
489 str r2, [fp, #LO_cycle]
491 str lr, [fp, #LO_saved_lr]
493 ldr lr, [fp, #LO_saved_lr]
499 FUNCTION(jump_handler_write8):
500 add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
501 pcsx_write_mem strbcc, 0
503 FUNCTION(jump_handler_write16):
504 add r3, #0x1000/4*4 @ shift to r16 part
505 pcsx_write_mem strhcc, 1
507 FUNCTION(jump_handler_write32):
508 pcsx_write_mem strcc, 2
510 FUNCTION(jump_handler_write_h):
511 /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
512 ldr r12, [fp, #LO_last_count]
513 str r0, [fp, #LO_address] @ some handlers still need it..
516 str r2, [fp, #LO_cycle]
518 str lr, [fp, #LO_saved_lr]
520 ldr lr, [fp, #LO_saved_lr]
525 FUNCTION(jump_handle_swl):
526 /* r0 = address, r1 = data, r2 = cycles */
527 ldr r3, [fp, #LO_mem_wtab]
529 ldr r3, [r3, r12, lsl #2]
531 bcs jump_handle_swx_interp
550 lsreq r12, r1, #24 @ 0
555 FUNCTION(jump_handle_swr):
556 /* r0 = address, r1 = data, r2 = cycles */
557 ldr r3, [fp, #LO_mem_wtab]
559 ldr r3, [r3, r12, lsl #2]
561 bcs jump_handle_swx_interp
576 jump_handle_swx_interp: /* almost never happens */
577 ldr r3, [fp, #LO_last_count]
578 add r0, fp, #LO_psxRegs
580 str r2, [fp, #LO_cycle] /* PCSX cycles */
584 .macro rcntx_read_mode0 num
585 /* r0 = address, r2 = cycles */
586 ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
588 sub r0, r0, r3, lsl #16
593 FUNCTION(rcnt0_read_count_m0):
596 FUNCTION(rcnt1_read_count_m0):
599 FUNCTION(rcnt2_read_count_m0):
602 FUNCTION(rcnt0_read_count_m1):
603 /* r0 = address, r2 = cycles */
604 ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
607 mul r0, r1, r2 @ /= 5
611 FUNCTION(rcnt1_read_count_m1):
612 /* r0 = address, r2 = cycles */
613 ldr r3, [fp, #LO_rcnts+6*4+7*4*1]
616 umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
619 FUNCTION(rcnt2_read_count_m1):
620 /* r0 = address, r2 = cycles */
621 ldr r3, [fp, #LO_rcnts+6*4+7*4*2]
622 mov r0, r2, lsl #16-3
623 sub r0, r0, r3, lsl #16-3
627 FUNCTION(call_gteStall):
628 /* r0 = op_cycles, r1 = cycles */
629 ldr r2, [fp, #LO_last_count]
630 str lr, [fp, #LO_saved_lr]
632 str r1, [fp, #LO_cycle]
633 add r1, fp, #LO_psxRegs
635 ldr lr, [fp, #LO_saved_lr]
645 orr r1, r1, r1, lsl #8
647 orr r1, r1, r1, lsl #16 @ searched char in every byte
648 ldrb r0, [r0, #12] @ last byte
656 orr r3, r3, #0xff000000 @ EXCLUDE_REG
657 uadd8 r0, r12, r1 @ add and set GE bits when not 0 (match)
659 sel r0, r12, r1 @ 0 if no match, else ff in some byte
665 clz r0, r0 @ 0, 8, 16, 24 or 32
668 sub r0, r12, r0, lsr #3 @ 3, 2, 1, 0 or -1
669 sub r2, r12, r2, lsr #3
670 sub r3, r12, r3, lsr #3
677 #endif /* HAVE_ARMV6 */
679 @ vim:filetype=armasm