1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * linkage_arm.s for PCSX *
3 * Copyright (C) 2009-2011 Ari64 *
4 * Copyright (C) 2010-2013 GraÅžvydas "notaz" Ignotas *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
20 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include "arm_features.h"
23 #include "linkage_offsets.h"
27 #define dynarec_local ESYM(dynarec_local)
28 #define add_link ESYM(add_link)
29 #define new_recompile_block ESYM(new_recompile_block)
30 #define get_addr ESYM(get_addr)
31 #define get_addr_ht ESYM(get_addr_ht)
32 #define clean_blocks ESYM(clean_blocks)
33 #define gen_interupt ESYM(gen_interupt)
34 #define psxException ESYM(psxException)
35 #define execI ESYM(execI)
36 #define invalidate_addr ESYM(invalidate_addr)
42 .type dynarec_local, %object
43 .size dynarec_local, LO_dynarec_local_size
45 .space LO_dynarec_local_size
47 #define DRC_VAR_(name, vname, size_) \
48 vname = dynarec_local + LO_##name; \
50 .type vname, %object; \
53 #define DRC_VAR(name, size_) \
54 DRC_VAR_(name, ESYM(name), size_)
56 DRC_VAR(next_interupt, 4)
57 DRC_VAR(cycle_count, 4)
58 DRC_VAR(last_count, 4)
59 DRC_VAR(pending_exception, 4)
63 DRC_VAR(psxRegs, LO_psxRegs_end - LO_psxRegs)
69 DRC_VAR(reg_cop0, 128)
70 DRC_VAR(reg_cop2d, 128)
71 DRC_VAR(reg_cop2c, 128)
75 @DRC_VAR(interrupt, 4)
76 @DRC_VAR(intCycle, 256)
82 DRC_VAR(zeromem_ptr, 4)
83 DRC_VAR(inv_code_start, 4)
84 DRC_VAR(inv_code_end, 4)
85 DRC_VAR(branch_target, 4)
86 DRC_VAR(scratch_buf_ptr, 4)
87 @DRC_VAR(align0, 12) /* unused/alignment */
89 DRC_VAR(restore_candidate, 512)
101 .word ESYM(jump_dirty)
103 .word ESYM(hash_table)
118 .macro load_varadr reg var
119 #if defined(HAVE_ARMV7) && !defined(__PIC__)
120 movw \reg, #:lower16:\var
121 movt \reg, #:upper16:\var
122 #elif defined(HAVE_ARMV7) && defined(__MACH__)
123 movw \reg, #:lower16:(\var-(1678f+8))
124 movt \reg, #:upper16:(\var-(1678f+8))
132 .macro load_varadr_ext reg var
133 #if defined(HAVE_ARMV7) && defined(__MACH__) && defined(__PIC__)
134 movw \reg, #:lower16:(ptr_\var-(1678f+8))
135 movt \reg, #:upper16:(ptr_\var-(1678f+8))
139 load_varadr \reg \var
143 .macro mov_16 reg imm
147 mov \reg, #(\imm & 0x00ff)
148 orr \reg, #(\imm & 0xff00)
152 .macro mov_24 reg imm
154 movw \reg, #(\imm & 0xffff)
155 movt \reg, #(\imm >> 16)
157 mov \reg, #(\imm & 0x0000ff)
158 orr \reg, #(\imm & 0x00ff00)
159 orr \reg, #(\imm & 0xff0000)
163 .macro dyna_linker_main
164 /* r0 = virtual target address */
165 /* r1 = instruction to patch */
166 load_varadr_ext r3, jump_in
179 ldr r5, [r3, r2, lsl #2]
181 add r6, r1, r12, asr #6
187 ldr r3, [r5] /* ll_entry .vaddr */
188 ldrd r4, r5, [r4, #8] /* ll_entry .next, .addr */
192 moveq pc, r4 /* Stale i-cache */
194 b 1b /* jump_in may have dupes, continue search */
197 beq 3f /* r0 not in jump_in */
203 and r1, r7, #0xff000000
206 add r1, r1, r2, lsr #8
210 /* hash_table lookup */
212 load_varadr_ext r3, jump_dirty
213 eor r4, r0, r0, lsl #16
215 load_varadr_ext r6, hash_table
219 ldr r5, [r3, r2, lsl #2]
226 /* jump_dirty lookup */
236 /* hash_table insert */
248 FUNCTION(dyna_linker):
249 /* r0 = virtual target address */
250 /* r1 = instruction to patch */
255 bl new_recompile_block
263 .size dyna_linker, .-dyna_linker
265 FUNCTION(exec_pagefault):
266 /* r0 = instruction pointer */
267 /* r1 = fault address */
269 ldr r3, [fp, #LO_reg_cop0+48] /* Status */
271 ldr r4, [fp, #LO_reg_cop0+16] /* Context */
272 bic r6, r6, #0x0F800000
273 str r0, [fp, #LO_reg_cop0+56] /* EPC */
275 str r1, [fp, #LO_reg_cop0+32] /* BadVAddr */
277 str r3, [fp, #LO_reg_cop0+48] /* Status */
278 and r5, r6, r1, lsr #9
279 str r2, [fp, #LO_reg_cop0+52] /* Cause */
280 and r1, r1, r6, lsl #9
281 str r1, [fp, #LO_reg_cop0+40] /* EntryHi */
283 str r4, [fp, #LO_reg_cop0+16] /* Context */
287 .size exec_pagefault, .-exec_pagefault
289 /* Special dynamic linker for the case where a page fault
290 may occur in a branch delay slot */
291 FUNCTION(dyna_linker_ds):
292 /* r0 = virtual target address */
293 /* r1 = instruction to patch */
300 bl new_recompile_block
307 mov r2, #0x80000008 /* High bit set indicates pagefault in delay slot */
310 .size dyna_linker_ds, .-dyna_linker_ds
314 FUNCTION(jump_vaddr_r0):
315 eor r2, r0, r0, lsl #16
317 .size jump_vaddr_r0, .-jump_vaddr_r0
318 FUNCTION(jump_vaddr_r1):
319 eor r2, r1, r1, lsl #16
322 .size jump_vaddr_r1, .-jump_vaddr_r1
323 FUNCTION(jump_vaddr_r2):
325 eor r2, r2, r2, lsl #16
327 .size jump_vaddr_r2, .-jump_vaddr_r2
328 FUNCTION(jump_vaddr_r3):
329 eor r2, r3, r3, lsl #16
332 .size jump_vaddr_r3, .-jump_vaddr_r3
333 FUNCTION(jump_vaddr_r4):
334 eor r2, r4, r4, lsl #16
337 .size jump_vaddr_r4, .-jump_vaddr_r4
338 FUNCTION(jump_vaddr_r5):
339 eor r2, r5, r5, lsl #16
342 .size jump_vaddr_r5, .-jump_vaddr_r5
343 FUNCTION(jump_vaddr_r6):
344 eor r2, r6, r6, lsl #16
347 .size jump_vaddr_r6, .-jump_vaddr_r6
348 FUNCTION(jump_vaddr_r8):
349 eor r2, r8, r8, lsl #16
352 .size jump_vaddr_r8, .-jump_vaddr_r8
353 FUNCTION(jump_vaddr_r9):
354 eor r2, r9, r9, lsl #16
357 .size jump_vaddr_r9, .-jump_vaddr_r9
358 FUNCTION(jump_vaddr_r10):
359 eor r2, r10, r10, lsl #16
362 .size jump_vaddr_r10, .-jump_vaddr_r10
363 FUNCTION(jump_vaddr_r12):
364 eor r2, r12, r12, lsl #16
367 .size jump_vaddr_r12, .-jump_vaddr_r12
368 FUNCTION(jump_vaddr_r7):
369 eor r2, r7, r7, lsl #16
371 .size jump_vaddr_r7, .-jump_vaddr_r7
372 FUNCTION(jump_vaddr):
373 load_varadr_ext r1, hash_table
375 and r2, r3, r2, lsr #12
382 str r10, [fp, #LO_cycle_count]
384 ldr r10, [fp, #LO_cycle_count]
386 .size jump_vaddr, .-jump_vaddr
390 FUNCTION(verify_code_ds):
391 str r8, [fp, #LO_branch_target]
392 FUNCTION(verify_code_vm):
393 FUNCTION(verify_code):
421 ldr r8, [fp, #LO_branch_target]
426 .size verify_code, .-verify_code
427 .size verify_code_vm, .-verify_code_vm
430 FUNCTION(cc_interrupt):
431 ldr r0, [fp, #LO_last_count]
435 str r1, [fp, #LO_pending_exception]
436 and r2, r2, r10, lsr #17
437 add r3, fp, #LO_restore_candidate
438 str r10, [fp, #LO_cycle] /* PCSX cycles */
439 @@ str r10, [fp, #LO_reg_cop0+36] /* Count */
447 ldr r10, [fp, #LO_cycle]
448 ldr r0, [fp, #LO_next_interupt]
449 ldr r1, [fp, #LO_pending_exception]
450 ldr r2, [fp, #LO_stop]
451 str r0, [fp, #LO_last_count]
454 ldmfdne sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
458 ldr r0, [fp, #LO_pcaddr]
462 /* Move 'dirty' blocks to the 'clean' list */
473 .size cc_interrupt, .-cc_interrupt
476 FUNCTION(do_interrupt):
477 ldr r0, [fp, #LO_pcaddr]
481 .size do_interrupt, .-do_interrupt
484 FUNCTION(fp_exception):
487 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
489 str r0, [fp, #LO_reg_cop0+56] /* EPC */
492 str r1, [fp, #LO_reg_cop0+48] /* Status */
493 str r2, [fp, #LO_reg_cop0+52] /* Cause */
497 .size fp_exception, .-fp_exception
499 FUNCTION(fp_exception_ds):
500 mov r2, #0x90000000 /* Set high bit if delay slot */
502 .size fp_exception_ds, .-fp_exception_ds
505 FUNCTION(jump_syscall):
506 ldr r1, [fp, #LO_reg_cop0+48] /* Status */
508 str r0, [fp, #LO_reg_cop0+56] /* EPC */
511 str r1, [fp, #LO_reg_cop0+48] /* Status */
512 str r2, [fp, #LO_reg_cop0+52] /* Cause */
516 .size jump_syscall, .-jump_syscall
520 FUNCTION(jump_syscall_hle):
521 str r0, [fp, #LO_pcaddr] /* PC must be set to EPC for psxException */
522 ldr r2, [fp, #LO_last_count]
523 mov r1, #0 /* in delay slot */
525 mov r0, #0x20 /* cause */
526 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
529 /* note: psxException might do recursive recompiler call from it's HLE code,
530 * so be ready for this */
532 ldr r1, [fp, #LO_next_interupt]
533 ldr r10, [fp, #LO_cycle]
534 ldr r0, [fp, #LO_pcaddr]
536 str r1, [fp, #LO_last_count]
539 .size jump_syscall_hle, .-jump_syscall_hle
542 FUNCTION(jump_hlecall):
543 ldr r2, [fp, #LO_last_count]
544 str r0, [fp, #LO_pcaddr]
547 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
549 .size jump_hlecall, .-jump_hlecall
552 FUNCTION(jump_intcall):
553 ldr r2, [fp, #LO_last_count]
554 str r0, [fp, #LO_pcaddr]
557 str r2, [fp, #LO_cycle] /* PCSX cycle counter */
559 .size jump_hlecall, .-jump_hlecall
562 FUNCTION(new_dyna_leave):
563 ldr r0, [fp, #LO_last_count]
566 str r10, [fp, #LO_cycle]
567 ldmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, pc}
568 .size new_dyna_leave, .-new_dyna_leave
571 FUNCTION(invalidate_addr_r0):
572 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
573 b invalidate_addr_call
574 .size invalidate_addr_r0, .-invalidate_addr_r0
576 FUNCTION(invalidate_addr_r1):
577 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
579 b invalidate_addr_call
580 .size invalidate_addr_r1, .-invalidate_addr_r1
582 FUNCTION(invalidate_addr_r2):
583 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
585 b invalidate_addr_call
586 .size invalidate_addr_r2, .-invalidate_addr_r2
588 FUNCTION(invalidate_addr_r3):
589 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
591 b invalidate_addr_call
592 .size invalidate_addr_r3, .-invalidate_addr_r3
594 FUNCTION(invalidate_addr_r4):
595 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
597 b invalidate_addr_call
598 .size invalidate_addr_r4, .-invalidate_addr_r4
600 FUNCTION(invalidate_addr_r5):
601 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
603 b invalidate_addr_call
604 .size invalidate_addr_r5, .-invalidate_addr_r5
606 FUNCTION(invalidate_addr_r6):
607 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
609 b invalidate_addr_call
610 .size invalidate_addr_r6, .-invalidate_addr_r6
612 FUNCTION(invalidate_addr_r7):
613 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
615 b invalidate_addr_call
616 .size invalidate_addr_r7, .-invalidate_addr_r7
618 FUNCTION(invalidate_addr_r8):
619 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
621 b invalidate_addr_call
622 .size invalidate_addr_r8, .-invalidate_addr_r8
624 FUNCTION(invalidate_addr_r9):
625 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
627 b invalidate_addr_call
628 .size invalidate_addr_r9, .-invalidate_addr_r9
630 FUNCTION(invalidate_addr_r10):
631 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
633 b invalidate_addr_call
634 .size invalidate_addr_r10, .-invalidate_addr_r10
636 FUNCTION(invalidate_addr_r12):
637 stmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, lr}
639 .size invalidate_addr_r12, .-invalidate_addr_r12
641 invalidate_addr_call:
642 ldr r12, [fp, #LO_inv_code_start]
643 ldr lr, [fp, #LO_inv_code_end]
647 ldmia fp, {r0, r1, r2, r3, EXTRA_UNSAVED_REGS r12, pc}
648 .size invalidate_addr_call, .-invalidate_addr_call
651 FUNCTION(new_dyna_start):
652 /* ip is stored to conform EABI alignment */
653 stmfd sp!, {r4, r5, r6, r7, r8, r9, sl, fp, ip, lr}
654 load_varadr fp, dynarec_local
655 ldr r0, [fp, #LO_pcaddr]
657 ldr r1, [fp, #LO_next_interupt]
658 ldr r10, [fp, #LO_cycle]
659 str r1, [fp, #LO_last_count]
662 .size new_dyna_start, .-new_dyna_start
664 /* --------------------------------------- */
668 .macro pcsx_read_mem readop tab_shift
669 /* r0 = address, r1 = handler_tab, r2 = cycles */
671 lsr r3, #(20+\tab_shift)
672 ldr r12, [fp, #LO_last_count]
673 ldr r1, [r1, r3, lsl #2]
680 \readop r0, [r1, r3, lsl #\tab_shift]
683 str r2, [fp, #LO_cycle]
687 FUNCTION(jump_handler_read8):
688 add r1, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
689 pcsx_read_mem ldrbcc, 0
691 FUNCTION(jump_handler_read16):
692 add r1, #0x1000/4*4 @ shift to r16 part
693 pcsx_read_mem ldrhcc, 1
695 FUNCTION(jump_handler_read32):
696 pcsx_read_mem ldrcc, 2
699 .macro pcsx_write_mem wrtop tab_shift
700 /* r0 = address, r1 = data, r2 = cycles, r3 = handler_tab */
702 lsr r12, #(20+\tab_shift)
703 ldr r3, [r3, r12, lsl #2]
704 str r0, [fp, #LO_address] @ some handlers still need it..
706 mov r0, r2 @ cycle return in case of direct store
711 \wrtop r1, [r3, r12, lsl #\tab_shift]
714 ldr r12, [fp, #LO_last_count]
718 str r2, [fp, #LO_cycle]
721 ldr r0, [fp, #LO_next_interupt]
723 str r0, [fp, #LO_last_count]
728 FUNCTION(jump_handler_write8):
729 add r3, #0x1000/4*4 + 0x1000/2*4 @ shift to r8 part
730 pcsx_write_mem strbcc, 0
732 FUNCTION(jump_handler_write16):
733 add r3, #0x1000/4*4 @ shift to r16 part
734 pcsx_write_mem strhcc, 1
736 FUNCTION(jump_handler_write32):
737 pcsx_write_mem strcc, 2
739 FUNCTION(jump_handler_write_h):
740 /* r0 = address, r1 = data, r2 = cycles, r3 = handler */
741 ldr r12, [fp, #LO_last_count]
742 str r0, [fp, #LO_address] @ some handlers still need it..
746 str r2, [fp, #LO_cycle]
749 ldr r0, [fp, #LO_next_interupt]
751 str r0, [fp, #LO_last_count]
755 FUNCTION(jump_handle_swl):
756 /* r0 = address, r1 = data, r2 = cycles */
757 ldr r3, [fp, #LO_mem_wtab]
759 ldr r3, [r3, r12, lsl #2]
780 lsreq r12, r1, #24 @ 0
790 FUNCTION(jump_handle_swr):
791 /* r0 = address, r1 = data, r2 = cycles */
792 ldr r3, [fp, #LO_mem_wtab]
794 ldr r3, [r3, r12, lsl #2]
816 .macro rcntx_read_mode0 num
817 /* r0 = address, r2 = cycles */
818 ldr r3, [fp, #LO_rcnts+6*4+7*4*\num] @ cycleStart
820 sub r0, r0, r3, lsl #16
825 FUNCTION(rcnt0_read_count_m0):
828 FUNCTION(rcnt1_read_count_m0):
831 FUNCTION(rcnt2_read_count_m0):
834 FUNCTION(rcnt0_read_count_m1):
835 /* r0 = address, r2 = cycles */
836 ldr r3, [fp, #LO_rcnts+6*4+7*4*0] @ cycleStart
839 mul r0, r1, r2 @ /= 5
843 FUNCTION(rcnt1_read_count_m1):
844 /* r0 = address, r2 = cycles */
845 ldr r3, [fp, #LO_rcnts+6*4+7*4*1]
848 umull r3, r0, r1, r2 @ ~ /= hsync_cycles, max ~0x1e6cdd
851 FUNCTION(rcnt2_read_count_m1):
852 /* r0 = address, r2 = cycles */
853 ldr r3, [fp, #LO_rcnts+6*4+7*4*2]
854 mov r0, r2, lsl #16-3
855 sub r0, r0, r3, lsl #16-3
859 @ vim:filetype=armasm