1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
27 #include <libkern/OSCacheControl.h>
30 #include <3ds_utils.h>
37 #include "new_dynarec_config.h"
38 #include "../psxhle.h"
39 #include "../psxinterpreter.h"
41 #include "emu_if.h" // emulator interface
42 #include "arm_features.h"
45 #define noinline __attribute__((noinline))
47 #define noinline __attribute__((noinline,noclone))
50 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
53 #define min(a, b) ((b) < (a) ? (b) : (a))
56 #define max(a, b) ((b) > (a) ? (b) : (a))
64 #define assem_debug printf
66 #define assem_debug(...)
68 //#define inv_debug printf
69 #define inv_debug(...)
72 #include "assem_x86.h"
75 #include "assem_x64.h"
78 #include "assem_arm.h"
81 #include "assem_arm64.h"
84 #define RAM_SIZE 0x200000
86 #define MAX_OUTPUT_BLOCK_SIZE 262144
87 #define EXPIRITY_OFFSET (MAX_OUTPUT_BLOCK_SIZE * 2)
88 #define PAGE_COUNT 1024
90 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
91 #define INVALIDATE_USE_COND_CALL
95 // apparently Vita has a 16MB limit, so either we cut tc in half,
96 // or use this hack (it's a hack because tc size was designed to be power-of-2)
97 #define TC_REDUCE_BYTES 4096
99 #define TC_REDUCE_BYTES 0
104 struct tramp_insns ops[2048 / sizeof(struct tramp_insns)];
105 const void *f[2048 / sizeof(void *)];
110 u_char translation_cache[(1 << TARGET_SIZE_2) - TC_REDUCE_BYTES];
111 struct ndrc_tramp tramp;
114 #ifdef BASE_ADDR_DYNAMIC
115 static struct ndrc_mem *ndrc;
117 static struct ndrc_mem ndrc_ __attribute__((aligned(4096)));
118 static struct ndrc_mem *ndrc = &ndrc_;
120 #ifdef TC_WRITE_OFFSET
122 # include <sys/types.h>
123 # include <sys/stat.h>
127 static long ndrc_write_ofs;
128 #define NDRC_WRITE_OFFSET(x) (void *)((char *)(x) + ndrc_write_ofs)
130 #define NDRC_WRITE_OFFSET(x) (x)
151 // regmap_pre[i] - regs before [i] insn starts; dirty things here that
152 // don't match .regmap will be written back
153 // [i].regmap_entry - regs that must be set up if someone jumps here
154 // [i].regmap - regs [i] insn will read/(over)write
155 // branch_regs[i].* - same as above but for branches, takes delay slot into account
158 signed char regmap_entry[HOST_REGS];
159 signed char regmap[HOST_REGS];
163 u_int wasconst; // before; for example 'lw r2, (r2)' wasconst is true
164 u_int isconst; // ... but isconst is false when r2 is known
165 u_int loadedconst; // host regs that have constants loaded
166 u_int waswritten; // MIPS regs that were used as store base before
196 struct block_info *next;
199 u_int start; // vaddr of the block start
200 u_int len; // of the whole block source
205 u_char inv_near_misses;
223 static struct decoded_insn
243 static struct ht_entry hash_table[65536];
244 static struct block_info *blocks[PAGE_COUNT];
245 static struct jump_info *jumps[PAGE_COUNT];
247 static u_int *source;
248 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
249 static uint64_t gte_rt[MAXBLOCK];
250 static uint64_t gte_unneeded[MAXBLOCK];
251 static u_int smrv[32]; // speculated MIPS register values
252 static u_int smrv_strong; // mask or regs that are likely to have correct values
253 static u_int smrv_weak; // same, but somewhat less likely
254 static u_int smrv_strong_next; // same, but after current insn executes
255 static u_int smrv_weak_next;
256 static int imm[MAXBLOCK];
257 static u_int ba[MAXBLOCK];
258 static uint64_t unneeded_reg[MAXBLOCK];
259 static uint64_t branch_unneeded_reg[MAXBLOCK];
260 // see 'struct regstat' for a description
261 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
262 // contains 'real' consts at [i] insn, but may differ from what's actually
263 // loaded in host reg as 'final' value is always loaded, see get_final_value()
264 static uint32_t current_constmap[HOST_REGS];
265 static uint32_t constmap[MAXBLOCK][HOST_REGS];
266 static struct regstat regs[MAXBLOCK];
267 static struct regstat branch_regs[MAXBLOCK];
268 static signed char minimum_free_regs[MAXBLOCK];
269 static int ccadj[MAXBLOCK];
271 static void *instr_addr[MAXBLOCK];
272 static struct link_entry link_addr[MAXBLOCK];
273 static int linkcount;
274 static struct code_stub stubs[MAXBLOCK*3];
275 static int stubcount;
276 static u_int literals[1024][2];
277 static int literalcount;
278 static int is_delayslot;
279 static char shadow[1048576] __attribute__((aligned(16)));
281 static u_int expirep;
282 static u_int stop_after_jal;
283 static u_int f1_hack;
285 static int stat_bc_direct;
286 static int stat_bc_pre;
287 static int stat_bc_restore;
288 static int stat_ht_lookups;
289 static int stat_jump_in_lookups;
290 static int stat_restore_tries;
291 static int stat_restore_compares;
292 static int stat_inv_addr_calls;
293 static int stat_inv_hits;
294 static int stat_blocks;
295 static int stat_links;
296 #define stat_inc(s) s++
297 #define stat_dec(s) s--
298 #define stat_clear(s) s = 0
302 #define stat_clear(s)
305 int new_dynarec_hacks;
306 int new_dynarec_hacks_pergame;
307 int new_dynarec_hacks_old;
308 int new_dynarec_did_compile;
310 #define HACK_ENABLED(x) ((new_dynarec_hacks | new_dynarec_hacks_pergame) & (x))
312 extern int cycle_count; // ... until end of the timeslice, counts -N -> 0
313 extern int last_count; // last absolute target, often = next_interupt
315 extern int pending_exception;
316 extern int branch_target;
317 extern uintptr_t ram_offset;
318 extern uintptr_t mini_ht[32][2];
320 /* registers that may be allocated */
322 #define LOREG 32 // lo
323 #define HIREG 33 // hi
324 //#define FSREG 34 // FPU status (FCSR)
325 #define CSREG 35 // Coprocessor status
326 #define CCREG 36 // Cycle count
327 #define INVCP 37 // Pointer to invalid_code
328 //#define MMREG 38 // Pointer to memory_map
329 #define ROREG 39 // ram offset (if rdram!=0x80000000)
331 #define FTEMP 40 // FPU temporary register
332 #define PTEMP 41 // Prefetch temporary register
333 //#define TLREG 42 // TLB mapping offset
334 #define RHASH 43 // Return address hash
335 #define RHTBL 44 // Return address hash table address
336 #define RTEMP 45 // JR/JALR address register
338 #define AGEN1 46 // Address generation temporary register
339 //#define AGEN2 47 // Address generation temporary register
340 //#define MGEN1 48 // Maptable address generation temporary register
341 //#define MGEN2 49 // Maptable address generation temporary register
342 #define BTREG 50 // Branch target temporary register
344 /* instruction types */
345 #define NOP 0 // No operation
346 #define LOAD 1 // Load
347 #define STORE 2 // Store
348 #define LOADLR 3 // Unaligned load
349 #define STORELR 4 // Unaligned store
350 #define MOV 5 // Move
351 #define ALU 6 // Arithmetic/logic
352 #define MULTDIV 7 // Multiply/divide
353 #define SHIFT 8 // Shift by register
354 #define SHIFTIMM 9// Shift by immediate
355 #define IMM16 10 // 16-bit immediate
356 #define RJUMP 11 // Unconditional jump to register
357 #define UJUMP 12 // Unconditional jump
358 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
359 #define SJUMP 14 // Conditional branch (regimm format)
360 #define COP0 15 // Coprocessor 0
361 #define COP1 16 // Coprocessor 1
362 #define C1LS 17 // Coprocessor 1 load/store
363 //#define FJUMP 18 // Conditional branch (floating point)
364 //#define FLOAT 19 // Floating point unit
365 //#define FCONV 20 // Convert integer to float
366 //#define FCOMP 21 // Floating point compare (sets FSREG)
367 #define SYSCALL 22// SYSCALL,BREAK
368 #define OTHER 23 // Other
369 //#define SPAN 24 // Branch/delay slot spans 2 pages
370 #define NI 25 // Not implemented
371 #define HLECALL 26// PCSX fake opcodes for HLE
372 #define COP2 27 // Coprocessor 2 move
373 #define C2LS 28 // Coprocessor 2 load/store
374 #define C2OP 29 // Coprocessor 2 operation
375 #define INTCALL 30// Call interpreter to handle rare corner cases
382 #define DJT_1 (void *)1l // no function, just a label in assem_debug log
383 #define DJT_2 (void *)2l
389 void fp_exception_ds();
390 void jump_syscall (u_int u0, u_int u1, u_int pc);
391 void jump_syscall_ds(u_int u0, u_int u1, u_int pc);
392 void jump_break (u_int u0, u_int u1, u_int pc);
393 void jump_break_ds(u_int u0, u_int u1, u_int pc);
394 void jump_to_new_pc();
395 void call_gteStall();
396 void new_dyna_leave();
398 void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile);
399 void *ndrc_get_addr_ht(u_int vaddr);
400 void ndrc_invalidate_addr(u_int addr);
401 void ndrc_add_jump_out(u_int vaddr, void *src);
403 static int new_recompile_block(u_int addr);
404 static void invalidate_block(struct block_info *block);
406 // Needed by assembler
407 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty);
408 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty);
409 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr);
410 static void load_all_regs(const signed char i_regmap[]);
411 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[]);
412 static void load_regs_entry(int t);
413 static void load_all_consts(const signed char regmap[], u_int dirty, int i);
414 static u_int get_host_reglist(const signed char *regmap);
416 static int get_final_value(int hr, int i, int *value);
417 static void add_stub(enum stub_type type, void *addr, void *retaddr,
418 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
419 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
420 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist);
421 static void add_to_linker(void *addr, u_int target, int ext);
422 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
423 int addr, int *offset_reg, int *addr_reg_override);
424 static void *get_direct_memhandler(void *table, u_int addr,
425 enum stub_type type, uintptr_t *addr_host);
426 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist);
427 static void pass_args(int a0, int a1);
428 static void emit_far_jump(const void *f);
429 static void emit_far_call(const void *f);
432 #include <psp2/kernel/sysmem.h>
434 // note: this interacts with RetroArch's Vita bootstrap code: bootstrap/vita/sbrk.c
435 extern int getVMBlock();
436 int _newlib_vm_size_user = sizeof(*ndrc);
439 static void mprotect_w_x(void *start, void *end, int is_x)
443 // *Open* enables write on all memory that was
444 // allocated by sceKernelAllocMemBlockForVM()?
446 sceKernelCloseVMDomain();
448 sceKernelOpenVMDomain();
449 #elif defined(HAVE_LIBNX)
451 // check to avoid the full flush in jitTransitionToExecutable()
452 if (g_jit.type != JitType_CodeMemory) {
454 rc = jitTransitionToExecutable(&g_jit);
456 rc = jitTransitionToWritable(&g_jit);
458 ;//SysPrintf("jitTransition %d %08x\n", is_x, rc);
460 #elif defined(TC_WRITE_OFFSET)
461 // separated rx and rw areas are always available
463 u_long mstart = (u_long)start & ~4095ul;
464 u_long mend = (u_long)end;
465 if (mprotect((void *)mstart, mend - mstart,
466 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
467 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
472 static void start_tcache_write(void *start, void *end)
474 mprotect_w_x(start, end, 0);
477 static void end_tcache_write(void *start, void *end)
479 #if defined(__arm__) || defined(__aarch64__)
480 size_t len = (char *)end - (char *)start;
481 #if defined(__BLACKBERRY_QNX__)
482 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
483 #elif defined(__MACH__)
484 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
486 sceKernelSyncVMDomain(sceBlock, start, len);
488 ctr_flush_invalidate_cache();
489 #elif defined(HAVE_LIBNX)
490 if (g_jit.type == JitType_CodeMemory) {
491 armDCacheClean(start, len);
492 armICacheInvalidate((char *)start - ndrc_write_ofs, len);
494 #elif defined(__aarch64__)
495 // as of 2021, __clear_cache() is still broken on arm64
496 // so here is a custom one :(
497 clear_cache_arm64(start, end);
499 __clear_cache(start, end);
504 mprotect_w_x(start, end, 1);
507 static void *start_block(void)
509 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
510 if (end > ndrc->translation_cache + sizeof(ndrc->translation_cache))
511 end = ndrc->translation_cache + sizeof(ndrc->translation_cache);
512 start_tcache_write(NDRC_WRITE_OFFSET(out), NDRC_WRITE_OFFSET(end));
516 static void end_block(void *start)
518 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(out));
521 #ifdef NDRC_CACHE_FLUSH_ALL
523 static int needs_clear_cache;
525 static void mark_clear_cache(void *target)
527 if (!needs_clear_cache) {
528 start_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
529 needs_clear_cache = 1;
533 static void do_clear_cache(void)
535 if (needs_clear_cache) {
536 end_tcache_write(NDRC_WRITE_OFFSET(ndrc), NDRC_WRITE_OFFSET(ndrc + 1));
537 needs_clear_cache = 0;
543 // also takes care of w^x mappings when patching code
544 static u_int needs_clear_cache[1<<(TARGET_SIZE_2-17)];
546 static void mark_clear_cache(void *target)
548 uintptr_t offset = (u_char *)target - ndrc->translation_cache;
549 u_int mask = 1u << ((offset >> 12) & 31);
550 if (!(needs_clear_cache[offset >> 17] & mask)) {
551 char *start = (char *)NDRC_WRITE_OFFSET((uintptr_t)target & ~4095l);
552 start_tcache_write(start, start + 4095);
553 needs_clear_cache[offset >> 17] |= mask;
557 // Clearing the cache is rather slow on ARM Linux, so mark the areas
558 // that need to be cleared, and then only clear these areas once.
559 static void do_clear_cache(void)
562 for (i = 0; i < (1<<(TARGET_SIZE_2-17)); i++)
564 u_int bitmap = needs_clear_cache[i];
567 for (j = 0; j < 32; j++)
570 if (!(bitmap & (1u << j)))
573 start = ndrc->translation_cache + i*131072 + j*4096;
575 for (j++; j < 32; j++) {
576 if (!(bitmap & (1u << j)))
580 end_tcache_write(NDRC_WRITE_OFFSET(start), NDRC_WRITE_OFFSET(end));
582 needs_clear_cache[i] = 0;
586 #endif // NDRC_CACHE_FLUSH_ALL
588 #define NO_CYCLE_PENALTY_THR 12
590 int cycle_multiplier = CYCLE_MULT_DEFAULT; // 100 for 1.0
591 int cycle_multiplier_override;
592 int cycle_multiplier_old;
593 static int cycle_multiplier_active;
595 static int CLOCK_ADJUST(int x)
597 int m = cycle_multiplier_active;
598 int s = (x >> 31) | 1;
599 return (x * m + s * 50) / 100;
602 static int ds_writes_rjump_rs(int i)
604 return dops[i].rs1 != 0 && (dops[i].rs1 == dops[i+1].rt1 || dops[i].rs1 == dops[i+1].rt2);
607 // psx addr mirror masking (for invalidation)
608 static u_int pmmask(u_int vaddr)
610 vaddr &= ~0xe0000000;
611 if (vaddr < 0x01000000)
612 vaddr &= ~0x00e00000; // RAM mirrors
616 static u_int get_page(u_int vaddr)
618 u_int page = pmmask(vaddr) >> 12;
619 if (page >= PAGE_COUNT / 2)
620 page = PAGE_COUNT / 2 + (page & (PAGE_COUNT / 2 - 1));
624 // get a page for looking for a block that has vaddr
625 // (needed because the block may start in previous page)
626 static u_int get_page_prev(u_int vaddr)
628 assert(MAXBLOCK <= (1 << 12));
629 u_int page = get_page(vaddr);
635 static struct ht_entry *hash_table_get(u_int vaddr)
637 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
640 static void hash_table_add(u_int vaddr, void *tcaddr)
642 struct ht_entry *ht_bin = hash_table_get(vaddr);
644 ht_bin->vaddr[1] = ht_bin->vaddr[0];
645 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
646 ht_bin->vaddr[0] = vaddr;
647 ht_bin->tcaddr[0] = tcaddr;
650 static void hash_table_remove(int vaddr)
652 //printf("remove hash: %x\n",vaddr);
653 struct ht_entry *ht_bin = hash_table_get(vaddr);
654 if (ht_bin->vaddr[1] == vaddr) {
655 ht_bin->vaddr[1] = -1;
656 ht_bin->tcaddr[1] = NULL;
658 if (ht_bin->vaddr[0] == vaddr) {
659 ht_bin->vaddr[0] = ht_bin->vaddr[1];
660 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
661 ht_bin->vaddr[1] = -1;
662 ht_bin->tcaddr[1] = NULL;
666 static void mark_invalid_code(u_int vaddr, u_int len, char invalid)
668 u_int vaddr_m = vaddr & 0x1fffffff;
670 for (i = vaddr_m & ~0xfff; i < vaddr_m + len; i += 0x1000) {
671 // ram mirrors, but should not hurt bios
672 for (j = 0; j < 0x800000; j += 0x200000) {
673 invalid_code[(i|j) >> 12] =
674 invalid_code[(i|j|0x80000000u) >> 12] =
675 invalid_code[(i|j|0xa0000000u) >> 12] = invalid;
678 if (!invalid && vaddr + len > inv_code_start && vaddr <= inv_code_end)
679 inv_code_start = inv_code_end = ~0;
682 static int doesnt_expire_soon(u_char *tcaddr)
684 u_int diff = (u_int)(tcaddr - out) & ((1u << TARGET_SIZE_2) - 1u);
685 return diff > EXPIRITY_OFFSET + MAX_OUTPUT_BLOCK_SIZE;
688 static void *try_restore_block(u_int vaddr, u_int start_page, u_int end_page)
690 void *found_clean = NULL;
693 stat_inc(stat_restore_tries);
694 for (page = start_page; page <= end_page; page++) {
695 struct block_info *block;
696 for (block = blocks[page]; block != NULL; block = block->next) {
697 if (vaddr < block->start)
699 if (!block->is_dirty || vaddr >= block->start + block->len)
701 for (i = 0; i < block->jump_in_cnt; i++)
702 if (block->jump_in[i].vaddr == vaddr)
704 if (i == block->jump_in_cnt)
706 assert(block->source && block->copy);
707 stat_inc(stat_restore_compares);
708 if (memcmp(block->source, block->copy, block->len))
711 block->is_dirty = block->inv_near_misses = 0;
712 found_clean = block->jump_in[i].addr;
713 hash_table_add(vaddr, found_clean);
714 mark_invalid_code(block->start, block->len, 0);
715 stat_inc(stat_bc_restore);
716 inv_debug("INV: restored %08x %p (%d)\n", vaddr, found_clean, block->jump_in_cnt);
723 // Get address from virtual address
724 // This is called from the recompiled JR/JALR instructions
725 static void noinline *get_addr(u_int vaddr, int can_compile)
727 u_int start_page = get_page_prev(vaddr);
728 u_int i, page, end_page = get_page(vaddr);
729 void *found_clean = NULL;
731 stat_inc(stat_jump_in_lookups);
732 for (page = start_page; page <= end_page; page++) {
733 const struct block_info *block;
734 for (block = blocks[page]; block != NULL; block = block->next) {
735 if (vaddr < block->start)
737 if (block->is_dirty || vaddr >= block->start + block->len)
739 for (i = 0; i < block->jump_in_cnt; i++)
740 if (block->jump_in[i].vaddr == vaddr)
742 if (i == block->jump_in_cnt)
744 found_clean = block->jump_in[i].addr;
745 hash_table_add(vaddr, found_clean);
749 found_clean = try_restore_block(vaddr, start_page, end_page);
756 int r = new_recompile_block(vaddr);
758 return ndrc_get_addr_ht(vaddr);
760 // generate an address error
762 Cause=(vaddr<<31)|(4<<2);
763 EPC=(vaddr&1)?vaddr-5:vaddr;
765 return ndrc_get_addr_ht(0x80000080);
768 // Look up address in hash table first
769 void *ndrc_get_addr_ht_param(u_int vaddr, int can_compile)
771 const struct ht_entry *ht_bin = hash_table_get(vaddr);
772 stat_inc(stat_ht_lookups);
773 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
774 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
775 return get_addr(vaddr, can_compile);
778 void *ndrc_get_addr_ht(u_int vaddr)
780 return ndrc_get_addr_ht_param(vaddr, 1);
783 static void clear_all_regs(signed char regmap[])
785 memset(regmap, -1, sizeof(regmap[0]) * HOST_REGS);
788 // get_reg: get allocated host reg from mips reg
789 // returns -1 if no such mips reg was allocated
790 #if defined(__arm__) && defined(HAVE_ARMV6) && HOST_REGS == 13 && EXCLUDE_REG == 11
792 extern signed char get_reg(const signed char regmap[], signed char r);
796 static signed char get_reg(const signed char regmap[], signed char r)
799 for (hr = 0; hr < HOST_REGS; hr++) {
800 if (hr == EXCLUDE_REG)
810 // get reg as mask bit (1 << hr)
811 static u_int get_regm(const signed char regmap[], signed char r)
813 return (1u << (get_reg(regmap, r) & 31)) & ~(1u << 31);
816 static signed char get_reg_temp(const signed char regmap[])
819 for (hr = 0; hr < HOST_REGS; hr++) {
820 if (hr == EXCLUDE_REG)
822 if (regmap[hr] == (signed char)-1)
828 // Find a register that is available for two consecutive cycles
829 static signed char get_reg2(signed char regmap1[], const signed char regmap2[], int r)
832 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
836 // reverse reg map: mips -> host
837 #define RRMAP_SIZE 64
838 static void make_rregs(const signed char regmap[], signed char rrmap[RRMAP_SIZE],
839 u_int *regs_can_change)
841 u_int r, hr, hr_can_change = 0;
842 memset(rrmap, -1, RRMAP_SIZE);
843 for (hr = 0; hr < HOST_REGS; )
846 rrmap[r & (RRMAP_SIZE - 1)] = hr;
847 // only add mips $1-$31+$lo, others shifted out
848 hr_can_change |= (uint64_t)1 << (hr + ((r - 1) & 32));
850 if (hr == EXCLUDE_REG)
853 hr_can_change |= 1u << (rrmap[33] & 31);
854 hr_can_change |= 1u << (rrmap[CCREG] & 31);
855 hr_can_change &= ~(1u << 31);
856 *regs_can_change = hr_can_change;
859 // same as get_reg, but takes rrmap
860 static signed char get_rreg(signed char rrmap[RRMAP_SIZE], signed char r)
862 assert(0 <= r && r < RRMAP_SIZE);
866 static int count_free_regs(const signed char regmap[])
870 for(hr=0;hr<HOST_REGS;hr++)
872 if(hr!=EXCLUDE_REG) {
873 if(regmap[hr]<0) count++;
879 static void dirty_reg(struct regstat *cur, signed char reg)
883 hr = get_reg(cur->regmap, reg);
888 static void set_const(struct regstat *cur, signed char reg, uint32_t value)
892 hr = get_reg(cur->regmap, reg);
894 cur->isconst |= 1<<hr;
895 current_constmap[hr] = value;
899 static void clear_const(struct regstat *cur, signed char reg)
903 hr = get_reg(cur->regmap, reg);
905 cur->isconst &= ~(1<<hr);
908 static int is_const(const struct regstat *cur, signed char reg)
911 if (reg < 0) return 0;
913 hr = get_reg(cur->regmap, reg);
915 return (cur->isconst>>hr)&1;
919 static uint32_t get_const(const struct regstat *cur, signed char reg)
923 hr = get_reg(cur->regmap, reg);
925 return current_constmap[hr];
927 SysPrintf("Unknown constant in r%d\n", reg);
931 // Least soon needed registers
932 // Look at the next ten instructions and see which registers
933 // will be used. Try not to reallocate these.
934 static void lsn(u_char hsn[], int i, int *preferred_reg)
944 if (dops[i+j].is_ujump)
946 // Don't go past an unconditonal jump
953 if(dops[i+j].rs1) hsn[dops[i+j].rs1]=j;
954 if(dops[i+j].rs2) hsn[dops[i+j].rs2]=j;
955 if(dops[i+j].rt1) hsn[dops[i+j].rt1]=j;
956 if(dops[i+j].rt2) hsn[dops[i+j].rt2]=j;
957 if(dops[i+j].itype==STORE || dops[i+j].itype==STORELR) {
958 // Stores can allocate zero
959 hsn[dops[i+j].rs1]=j;
960 hsn[dops[i+j].rs2]=j;
962 if (ram_offset && (dops[i+j].is_load || dops[i+j].is_store))
964 // On some architectures stores need invc_ptr
965 #if defined(HOST_IMM8)
966 if (dops[i+j].is_store)
969 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
977 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
979 // Follow first branch
980 int t=(ba[i+b]-start)>>2;
981 j=7-b;if(t+j>=slen) j=slen-t-1;
984 if(dops[t+j].rs1) if(hsn[dops[t+j].rs1]>j+b+2) hsn[dops[t+j].rs1]=j+b+2;
985 if(dops[t+j].rs2) if(hsn[dops[t+j].rs2]>j+b+2) hsn[dops[t+j].rs2]=j+b+2;
986 //if(dops[t+j].rt1) if(hsn[dops[t+j].rt1]>j+b+2) hsn[dops[t+j].rt1]=j+b+2;
987 //if(dops[t+j].rt2) if(hsn[dops[t+j].rt2]>j+b+2) hsn[dops[t+j].rt2]=j+b+2;
990 // TODO: preferred register based on backward branch
992 // Delay slot should preferably not overwrite branch conditions or cycle count
993 if (i > 0 && dops[i-1].is_jump) {
994 if(dops[i-1].rs1) if(hsn[dops[i-1].rs1]>1) hsn[dops[i-1].rs1]=1;
995 if(dops[i-1].rs2) if(hsn[dops[i-1].rs2]>1) hsn[dops[i-1].rs2]=1;
1001 // Coprocessor load/store needs FTEMP, even if not declared
1002 if(dops[i].itype==C2LS) {
1005 // Load L/R also uses FTEMP as a temporary register
1006 if(dops[i].itype==LOADLR) {
1009 // Also SWL/SWR/SDL/SDR
1010 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) {
1013 // Don't remove the miniht registers
1014 if(dops[i].itype==UJUMP||dops[i].itype==RJUMP)
1021 // We only want to allocate registers if we're going to use them again soon
1022 static int needed_again(int r, int i)
1028 if (i > 0 && dops[i-1].is_ujump)
1030 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
1031 return 0; // Don't need any registers if exiting the block
1039 if (dops[i+j].is_ujump)
1041 // Don't go past an unconditonal jump
1045 if(dops[i+j].itype==SYSCALL||dops[i+j].itype==HLECALL||dops[i+j].itype==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
1052 if(dops[i+j].rs1==r) rn=j;
1053 if(dops[i+j].rs2==r) rn=j;
1054 if((unneeded_reg[i+j]>>r)&1) rn=10;
1055 if(i+j>=0&&(dops[i+j].itype==UJUMP||dops[i+j].itype==CJUMP||dops[i+j].itype==SJUMP))
1065 // Try to match register allocations at the end of a loop with those
1067 static int loop_reg(int i, int r, int hr)
1076 if (dops[i+j].is_ujump)
1078 // Don't go past an unconditonal jump
1085 if(dops[i-1].itype==UJUMP||dops[i-1].itype==CJUMP||dops[i-1].itype==SJUMP)
1091 if((unneeded_reg[i+k]>>r)&1) return hr;
1092 if(i+k>=0&&(dops[i+k].itype==UJUMP||dops[i+k].itype==CJUMP||dops[i+k].itype==SJUMP))
1094 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
1096 int t=(ba[i+k]-start)>>2;
1097 int reg=get_reg(regs[t].regmap_entry,r);
1098 if(reg>=0) return reg;
1099 //reg=get_reg(regs[t+1].regmap_entry,r);
1100 //if(reg>=0) return reg;
1108 // Allocate every register, preserving source/target regs
1109 static void alloc_all(struct regstat *cur,int i)
1113 for(hr=0;hr<HOST_REGS;hr++) {
1114 if(hr!=EXCLUDE_REG) {
1115 if((cur->regmap[hr]!=dops[i].rs1)&&(cur->regmap[hr]!=dops[i].rs2)&&
1116 (cur->regmap[hr]!=dops[i].rt1)&&(cur->regmap[hr]!=dops[i].rt2))
1119 cur->dirty&=~(1<<hr);
1122 if(cur->regmap[hr]==0)
1125 cur->dirty&=~(1<<hr);
1132 static int host_tempreg_in_use;
1134 static void host_tempreg_acquire(void)
1136 assert(!host_tempreg_in_use);
1137 host_tempreg_in_use = 1;
1140 static void host_tempreg_release(void)
1142 host_tempreg_in_use = 0;
1145 static void host_tempreg_acquire(void) {}
1146 static void host_tempreg_release(void) {}
1150 extern void gen_interupt();
1151 extern void do_insn_cmp();
1152 #define FUNCNAME(f) { f, " " #f }
1153 static const struct {
1156 } function_names[] = {
1157 FUNCNAME(cc_interrupt),
1158 FUNCNAME(gen_interupt),
1159 FUNCNAME(ndrc_get_addr_ht),
1160 FUNCNAME(jump_handler_read8),
1161 FUNCNAME(jump_handler_read16),
1162 FUNCNAME(jump_handler_read32),
1163 FUNCNAME(jump_handler_write8),
1164 FUNCNAME(jump_handler_write16),
1165 FUNCNAME(jump_handler_write32),
1166 FUNCNAME(ndrc_invalidate_addr),
1167 FUNCNAME(jump_to_new_pc),
1168 FUNCNAME(jump_break),
1169 FUNCNAME(jump_break_ds),
1170 FUNCNAME(jump_syscall),
1171 FUNCNAME(jump_syscall_ds),
1172 FUNCNAME(call_gteStall),
1173 FUNCNAME(new_dyna_leave),
1174 FUNCNAME(pcsx_mtc0),
1175 FUNCNAME(pcsx_mtc0_ds),
1177 FUNCNAME(do_insn_cmp),
1181 static const char *func_name(const void *a)
1184 for (i = 0; i < sizeof(function_names)/sizeof(function_names[0]); i++)
1185 if (function_names[i].addr == a)
1186 return function_names[i].name;
1190 #define func_name(x) ""
1194 #include "assem_x86.c"
1197 #include "assem_x64.c"
1200 #include "assem_arm.c"
1203 #include "assem_arm64.c"
1206 static void *get_trampoline(const void *f)
1208 struct ndrc_tramp *tramp = NDRC_WRITE_OFFSET(&ndrc->tramp);
1211 for (i = 0; i < ARRAY_SIZE(tramp->f); i++) {
1212 if (tramp->f[i] == f || tramp->f[i] == NULL)
1215 if (i == ARRAY_SIZE(tramp->f)) {
1216 SysPrintf("trampoline table is full, last func %p\n", f);
1219 if (tramp->f[i] == NULL) {
1220 start_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1222 end_tcache_write(&tramp->f[i], &tramp->f[i + 1]);
1224 // invalidate the RX mirror (unsure if necessary, but just in case...)
1225 armDCacheFlush(&ndrc->tramp.f[i], sizeof(ndrc->tramp.f[i]));
1228 return &ndrc->tramp.ops[i];
1231 static void emit_far_jump(const void *f)
1233 if (can_jump_or_call(f)) {
1238 f = get_trampoline(f);
1242 static void emit_far_call(const void *f)
1244 if (can_jump_or_call(f)) {
1249 f = get_trampoline(f);
1253 // Check if an address is already compiled
1254 // but don't return addresses which are about to expire from the cache
1255 static void *check_addr(u_int vaddr)
1257 struct ht_entry *ht_bin = hash_table_get(vaddr);
1259 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
1260 if (ht_bin->vaddr[i] == vaddr)
1261 if (doesnt_expire_soon(ht_bin->tcaddr[i]))
1262 return ht_bin->tcaddr[i];
1265 // refactor to get_addr_nocompile?
1266 u_int start_page = get_page_prev(vaddr);
1267 u_int page, end_page = get_page(vaddr);
1269 stat_inc(stat_jump_in_lookups);
1270 for (page = start_page; page <= end_page; page++) {
1271 const struct block_info *block;
1272 for (block = blocks[page]; block != NULL; block = block->next) {
1273 if (vaddr < block->start)
1275 if (block->is_dirty || vaddr >= block->start + block->len)
1277 if (!doesnt_expire_soon(ndrc->translation_cache + block->tc_offs))
1279 for (i = 0; i < block->jump_in_cnt; i++)
1280 if (block->jump_in[i].vaddr == vaddr)
1282 if (i == block->jump_in_cnt)
1285 // Update existing entry with current address
1286 void *addr = block->jump_in[i].addr;
1287 if (ht_bin->vaddr[0] == vaddr) {
1288 ht_bin->tcaddr[0] = addr;
1291 if (ht_bin->vaddr[1] == vaddr) {
1292 ht_bin->tcaddr[1] = addr;
1295 // Insert into hash table with low priority.
1296 // Don't evict existing entries, as they are probably
1297 // addresses that are being accessed frequently.
1298 if (ht_bin->vaddr[0] == -1) {
1299 ht_bin->vaddr[0] = vaddr;
1300 ht_bin->tcaddr[0] = addr;
1302 else if (ht_bin->vaddr[1] == -1) {
1303 ht_bin->vaddr[1] = vaddr;
1304 ht_bin->tcaddr[1] = addr;
1312 static void blocks_clear(struct block_info **head)
1314 struct block_info *cur, *next;
1316 if ((cur = *head)) {
1326 static int blocks_remove_matching_addrs(struct block_info **head,
1327 u_int base_offs, int shift)
1329 struct block_info *next;
1332 if ((((*head)->tc_offs ^ base_offs) >> shift) == 0) {
1333 inv_debug("EXP: rm block %08x (tc_offs %zx)\n", (*head)->start, (*head)->tc_offs);
1334 invalidate_block(*head);
1335 next = (*head)->next;
1338 stat_dec(stat_blocks);
1343 head = &((*head)->next);
1349 // This is called when we write to a compiled block (see do_invstub)
1350 static void unlink_jumps_vaddr_range(u_int start, u_int end)
1352 u_int page, start_page = get_page(start), end_page = get_page(end - 1);
1355 for (page = start_page; page <= end_page; page++) {
1356 struct jump_info *ji = jumps[page];
1359 for (i = 0; i < ji->count; ) {
1360 if (ji->e[i].target_vaddr < start || ji->e[i].target_vaddr >= end) {
1365 inv_debug("INV: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr,
1366 (u_char *)ji->e[i].stub - ndrc->translation_cache);
1367 void *host_addr = find_extjump_insn(ji->e[i].stub);
1368 mark_clear_cache(host_addr);
1369 set_jump_target(host_addr, ji->e[i].stub); // point back to dyna_linker stub
1371 stat_dec(stat_links);
1373 if (i < ji->count) {
1374 ji->e[i] = ji->e[ji->count];
1382 static void unlink_jumps_tc_range(struct jump_info *ji, u_int base_offs, int shift)
1387 for (i = 0; i < ji->count; ) {
1388 u_int tc_offs = (u_char *)ji->e[i].stub - ndrc->translation_cache;
1389 if (((tc_offs ^ base_offs) >> shift) != 0) {
1394 inv_debug("EXP: rm link to %08x (tc_offs %zx)\n", ji->e[i].target_vaddr, tc_offs);
1395 stat_dec(stat_links);
1397 if (i < ji->count) {
1398 ji->e[i] = ji->e[ji->count];
1405 static void invalidate_block(struct block_info *block)
1409 block->is_dirty = 1;
1410 unlink_jumps_vaddr_range(block->start, block->start + block->len);
1411 for (i = 0; i < block->jump_in_cnt; i++)
1412 hash_table_remove(block->jump_in[i].vaddr);
1415 static int invalidate_range(u_int start, u_int end,
1416 u32 *inv_start_ret, u32 *inv_end_ret)
1418 struct block_info *last_block = NULL;
1419 u_int start_page = get_page_prev(start);
1420 u_int end_page = get_page(end - 1);
1421 u_int start_m = pmmask(start);
1422 u_int end_m = pmmask(end - 1);
1423 u_int inv_start, inv_end;
1424 u_int blk_start_m, blk_end_m;
1428 // additional area without code (to supplement invalid_code[]), [start, end)
1429 // avoids excessive ndrc_invalidate_addr() calls
1430 inv_start = start_m & ~0xfff;
1431 inv_end = end_m | 0xfff;
1433 for (page = start_page; page <= end_page; page++) {
1434 struct block_info *block;
1435 for (block = blocks[page]; block != NULL; block = block->next) {
1436 if (block->is_dirty)
1439 blk_end_m = pmmask(block->start + block->len);
1440 if (blk_end_m <= start_m) {
1441 inv_start = max(inv_start, blk_end_m);
1444 blk_start_m = pmmask(block->start);
1445 if (end_m <= blk_start_m) {
1446 inv_end = min(inv_end, blk_start_m - 1);
1449 if (!block->source) // "hack" block - leave it alone
1453 invalidate_block(block);
1454 stat_inc(stat_inv_hits);
1458 if (!hit && last_block && last_block->source) {
1459 // could be some leftover unused block, uselessly trapping writes
1460 last_block->inv_near_misses++;
1461 if (last_block->inv_near_misses > 128) {
1462 invalidate_block(last_block);
1463 stat_inc(stat_inv_hits);
1470 memset(mini_ht, -1, sizeof(mini_ht));
1474 if (inv_start <= (start_m & ~0xfff) && inv_end >= (start_m | 0xfff))
1475 // the whole page is empty now
1476 mark_invalid_code(start, 1, 1);
1478 if (inv_start_ret) *inv_start_ret = inv_start | (start & 0xe0000000);
1479 if (inv_end_ret) *inv_end_ret = inv_end | (end & 0xe0000000);
1483 void new_dynarec_invalidate_range(unsigned int start, unsigned int end)
1485 invalidate_range(start, end, NULL, NULL);
1488 void ndrc_invalidate_addr(u_int addr)
1490 // this check is done by the caller
1491 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1492 int ret = invalidate_range(addr, addr + 4, &inv_code_start, &inv_code_end);
1494 inv_debug("INV ADDR: %08x hit %d blocks\n", addr, ret);
1496 inv_debug("INV ADDR: %08x miss, inv %08x-%08x\n", addr, inv_code_start, inv_code_end);
1497 stat_inc(stat_inv_addr_calls);
1500 // This is called when loading a save state.
1501 // Anything could have changed, so invalidate everything.
1502 void new_dynarec_invalidate_all_pages(void)
1504 struct block_info *block;
1506 for (page = 0; page < ARRAY_SIZE(blocks); page++) {
1507 for (block = blocks[page]; block != NULL; block = block->next) {
1508 if (block->is_dirty)
1510 if (!block->source) // hack block?
1512 invalidate_block(block);
1517 memset(mini_ht, -1, sizeof(mini_ht));
1522 static void do_invstub(int n)
1525 u_int reglist = stubs[n].a;
1526 set_jump_target(stubs[n].addr, out);
1528 if (stubs[n].b != 0)
1529 emit_mov(stubs[n].b, 0);
1530 emit_readword(&inv_code_start, 1);
1531 emit_readword(&inv_code_end, 2);
1536 emit_far_call(ndrc_invalidate_addr);
1537 set_jump_target(jaddr, out);
1538 restore_regs(reglist);
1539 emit_jmp(stubs[n].retaddr); // return address
1542 // Add an entry to jump_out after making a link
1543 // src should point to code by emit_extjump()
1544 void ndrc_add_jump_out(u_int vaddr, void *src)
1546 inv_debug("ndrc_add_jump_out: %p -> %x\n", src, vaddr);
1547 u_int page = get_page(vaddr);
1548 struct jump_info *ji;
1550 stat_inc(stat_links);
1551 check_extjump2(src);
1554 ji = malloc(sizeof(*ji) + sizeof(ji->e[0]) * 16);
1558 else if (ji->count >= ji->alloc) {
1560 ji = realloc(ji, sizeof(*ji) + sizeof(ji->e[0]) * ji->alloc);
1563 ji->e[ji->count].target_vaddr = vaddr;
1564 ji->e[ji->count].stub = src;
1568 /* Register allocation */
1570 // Note: registers are allocated clean (unmodified state)
1571 // if you intend to modify the register, you must call dirty_reg().
1572 static void alloc_reg(struct regstat *cur,int i,signed char reg)
1575 int preferred_reg = PREFERRED_REG_FIRST
1576 + reg % (PREFERRED_REG_LAST - PREFERRED_REG_FIRST + 1);
1577 if (reg == CCREG) preferred_reg = HOST_CCREG;
1578 if (reg == PTEMP || reg == FTEMP) preferred_reg = 12;
1579 assert(PREFERRED_REG_FIRST != EXCLUDE_REG && EXCLUDE_REG != HOST_REGS);
1582 // Don't allocate unused registers
1583 if((cur->u>>reg)&1) return;
1585 // see if it's already allocated
1586 if (get_reg(cur->regmap, reg) >= 0)
1589 // Keep the same mapping if the register was already allocated in a loop
1590 preferred_reg = loop_reg(i,reg,preferred_reg);
1592 // Try to allocate the preferred register
1593 if(cur->regmap[preferred_reg]==-1) {
1594 cur->regmap[preferred_reg]=reg;
1595 cur->dirty&=~(1<<preferred_reg);
1596 cur->isconst&=~(1<<preferred_reg);
1599 r=cur->regmap[preferred_reg];
1602 cur->regmap[preferred_reg]=reg;
1603 cur->dirty&=~(1<<preferred_reg);
1604 cur->isconst&=~(1<<preferred_reg);
1608 // Clear any unneeded registers
1609 // We try to keep the mapping consistent, if possible, because it
1610 // makes branches easier (especially loops). So we try to allocate
1611 // first (see above) before removing old mappings. If this is not
1612 // possible then go ahead and clear out the registers that are no
1614 for(hr=0;hr<HOST_REGS;hr++)
1619 if((cur->u>>r)&1) {cur->regmap[hr]=-1;break;}
1623 // Try to allocate any available register, but prefer
1624 // registers that have not been used recently.
1626 for (hr = PREFERRED_REG_FIRST; ; ) {
1627 if (cur->regmap[hr] < 0) {
1628 int oldreg = regs[i-1].regmap[hr];
1629 if (oldreg < 0 || (oldreg != dops[i-1].rs1 && oldreg != dops[i-1].rs2
1630 && oldreg != dops[i-1].rt1 && oldreg != dops[i-1].rt2))
1632 cur->regmap[hr]=reg;
1633 cur->dirty&=~(1<<hr);
1634 cur->isconst&=~(1<<hr);
1639 if (hr == EXCLUDE_REG)
1641 if (hr == HOST_REGS)
1643 if (hr == PREFERRED_REG_FIRST)
1648 // Try to allocate any available register
1649 for (hr = PREFERRED_REG_FIRST; ; ) {
1650 if (cur->regmap[hr] < 0) {
1651 cur->regmap[hr]=reg;
1652 cur->dirty&=~(1<<hr);
1653 cur->isconst&=~(1<<hr);
1657 if (hr == EXCLUDE_REG)
1659 if (hr == HOST_REGS)
1661 if (hr == PREFERRED_REG_FIRST)
1665 // Ok, now we have to evict someone
1666 // Pick a register we hopefully won't need soon
1667 u_char hsn[MAXREG+1];
1668 memset(hsn,10,sizeof(hsn));
1670 lsn(hsn,i,&preferred_reg);
1671 //printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",cur->regmap[0],cur->regmap[1],cur->regmap[2],cur->regmap[3],cur->regmap[5],cur->regmap[6],cur->regmap[7]);
1672 //printf("hsn(%x): %d %d %d %d %d %d %d\n",start+i*4,hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1674 // Don't evict the cycle count at entry points, otherwise the entry
1675 // stub will have to write it.
1676 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1677 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1680 // Alloc preferred register if available
1681 if(hsn[r=cur->regmap[preferred_reg]&63]==j) {
1682 for(hr=0;hr<HOST_REGS;hr++) {
1683 // Evict both parts of a 64-bit register
1684 if(cur->regmap[hr]==r) {
1686 cur->dirty&=~(1<<hr);
1687 cur->isconst&=~(1<<hr);
1690 cur->regmap[preferred_reg]=reg;
1693 for(r=1;r<=MAXREG;r++)
1695 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1696 for(hr=0;hr<HOST_REGS;hr++) {
1697 if(hr!=HOST_CCREG||j<hsn[CCREG]) {
1698 if(cur->regmap[hr]==r) {
1699 cur->regmap[hr]=reg;
1700 cur->dirty&=~(1<<hr);
1701 cur->isconst&=~(1<<hr);
1712 for(r=1;r<=MAXREG;r++)
1715 for(hr=0;hr<HOST_REGS;hr++) {
1716 if(cur->regmap[hr]==r) {
1717 cur->regmap[hr]=reg;
1718 cur->dirty&=~(1<<hr);
1719 cur->isconst&=~(1<<hr);
1726 SysPrintf("This shouldn't happen (alloc_reg)");abort();
1729 // Allocate a temporary register. This is done without regard to
1730 // dirty status or whether the register we request is on the unneeded list
1731 // Note: This will only allocate one register, even if called multiple times
1732 static void alloc_reg_temp(struct regstat *cur,int i,signed char reg)
1735 int preferred_reg = -1;
1737 // see if it's already allocated
1738 for(hr=0;hr<HOST_REGS;hr++)
1740 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==reg) return;
1743 // Try to allocate any available register
1744 for(hr=HOST_REGS-1;hr>=0;hr--) {
1745 if(hr!=EXCLUDE_REG&&cur->regmap[hr]==-1) {
1746 cur->regmap[hr]=reg;
1747 cur->dirty&=~(1<<hr);
1748 cur->isconst&=~(1<<hr);
1753 // Find an unneeded register
1754 for(hr=HOST_REGS-1;hr>=0;hr--)
1760 if(i==0||((unneeded_reg[i-1]>>r)&1)) {
1761 cur->regmap[hr]=reg;
1762 cur->dirty&=~(1<<hr);
1763 cur->isconst&=~(1<<hr);
1770 // Ok, now we have to evict someone
1771 // Pick a register we hopefully won't need soon
1772 // TODO: we might want to follow unconditional jumps here
1773 // TODO: get rid of dupe code and make this into a function
1774 u_char hsn[MAXREG+1];
1775 memset(hsn,10,sizeof(hsn));
1777 lsn(hsn,i,&preferred_reg);
1778 //printf("hsn: %d %d %d %d %d %d %d\n",hsn[cur->regmap[0]&63],hsn[cur->regmap[1]&63],hsn[cur->regmap[2]&63],hsn[cur->regmap[3]&63],hsn[cur->regmap[5]&63],hsn[cur->regmap[6]&63],hsn[cur->regmap[7]&63]);
1780 // Don't evict the cycle count at entry points, otherwise the entry
1781 // stub will have to write it.
1782 if(dops[i].bt&&hsn[CCREG]>2) hsn[CCREG]=2;
1783 if (i>1 && hsn[CCREG] > 2 && dops[i-2].is_jump) hsn[CCREG]=2;
1786 for(r=1;r<=MAXREG;r++)
1788 if(hsn[r]==j&&r!=dops[i-1].rs1&&r!=dops[i-1].rs2&&r!=dops[i-1].rt1&&r!=dops[i-1].rt2) {
1789 for(hr=0;hr<HOST_REGS;hr++) {
1790 if(hr!=HOST_CCREG||hsn[CCREG]>2) {
1791 if(cur->regmap[hr]==r) {
1792 cur->regmap[hr]=reg;
1793 cur->dirty&=~(1<<hr);
1794 cur->isconst&=~(1<<hr);
1805 for(r=1;r<=MAXREG;r++)
1808 for(hr=0;hr<HOST_REGS;hr++) {
1809 if(cur->regmap[hr]==r) {
1810 cur->regmap[hr]=reg;
1811 cur->dirty&=~(1<<hr);
1812 cur->isconst&=~(1<<hr);
1819 SysPrintf("This shouldn't happen");abort();
1822 static void mov_alloc(struct regstat *current,int i)
1824 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) {
1825 alloc_cc(current,i); // for stalls
1826 dirty_reg(current,CCREG);
1829 // Note: Don't need to actually alloc the source registers
1830 //alloc_reg(current,i,dops[i].rs1);
1831 alloc_reg(current,i,dops[i].rt1);
1833 clear_const(current,dops[i].rs1);
1834 clear_const(current,dops[i].rt1);
1835 dirty_reg(current,dops[i].rt1);
1838 static void shiftimm_alloc(struct regstat *current,int i)
1840 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
1843 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1844 else dops[i].use_lt1=!!dops[i].rs1;
1845 alloc_reg(current,i,dops[i].rt1);
1846 dirty_reg(current,dops[i].rt1);
1847 if(is_const(current,dops[i].rs1)) {
1848 int v=get_const(current,dops[i].rs1);
1849 if(dops[i].opcode2==0x00) set_const(current,dops[i].rt1,v<<imm[i]);
1850 if(dops[i].opcode2==0x02) set_const(current,dops[i].rt1,(u_int)v>>imm[i]);
1851 if(dops[i].opcode2==0x03) set_const(current,dops[i].rt1,v>>imm[i]);
1853 else clear_const(current,dops[i].rt1);
1858 clear_const(current,dops[i].rs1);
1859 clear_const(current,dops[i].rt1);
1862 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
1866 if(dops[i].opcode2==0x3c) // DSLL32
1870 if(dops[i].opcode2==0x3e) // DSRL32
1874 if(dops[i].opcode2==0x3f) // DSRA32
1880 static void shift_alloc(struct regstat *current,int i)
1883 if(dops[i].opcode2<=0x07) // SLLV/SRLV/SRAV
1885 if(dops[i].rs1) alloc_reg(current,i,dops[i].rs1);
1886 if(dops[i].rs2) alloc_reg(current,i,dops[i].rs2);
1887 alloc_reg(current,i,dops[i].rt1);
1888 if(dops[i].rt1==dops[i].rs2) {
1889 alloc_reg_temp(current,i,-1);
1890 minimum_free_regs[i]=1;
1892 } else { // DSLLV/DSRLV/DSRAV
1895 clear_const(current,dops[i].rs1);
1896 clear_const(current,dops[i].rs2);
1897 clear_const(current,dops[i].rt1);
1898 dirty_reg(current,dops[i].rt1);
1902 static void alu_alloc(struct regstat *current,int i)
1904 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
1906 if(dops[i].rs1&&dops[i].rs2) {
1907 alloc_reg(current,i,dops[i].rs1);
1908 alloc_reg(current,i,dops[i].rs2);
1911 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1912 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1914 alloc_reg(current,i,dops[i].rt1);
1917 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
1919 alloc_reg(current,i,dops[i].rs1);
1920 alloc_reg(current,i,dops[i].rs2);
1921 alloc_reg(current,i,dops[i].rt1);
1924 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
1926 if(dops[i].rs1&&dops[i].rs2) {
1927 alloc_reg(current,i,dops[i].rs1);
1928 alloc_reg(current,i,dops[i].rs2);
1932 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1933 if(dops[i].rs2&&needed_again(dops[i].rs2,i)) alloc_reg(current,i,dops[i].rs2);
1935 alloc_reg(current,i,dops[i].rt1);
1938 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1941 clear_const(current,dops[i].rs1);
1942 clear_const(current,dops[i].rs2);
1943 clear_const(current,dops[i].rt1);
1944 dirty_reg(current,dops[i].rt1);
1947 static void imm16_alloc(struct regstat *current,int i)
1949 if(dops[i].rs1&&needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
1950 else dops[i].use_lt1=!!dops[i].rs1;
1951 if(dops[i].rt1) alloc_reg(current,i,dops[i].rt1);
1952 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
1955 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
1956 clear_const(current,dops[i].rs1);
1957 clear_const(current,dops[i].rt1);
1959 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
1960 if(is_const(current,dops[i].rs1)) {
1961 int v=get_const(current,dops[i].rs1);
1962 if(dops[i].opcode==0x0c) set_const(current,dops[i].rt1,v&imm[i]);
1963 if(dops[i].opcode==0x0d) set_const(current,dops[i].rt1,v|imm[i]);
1964 if(dops[i].opcode==0x0e) set_const(current,dops[i].rt1,v^imm[i]);
1966 else clear_const(current,dops[i].rt1);
1968 else if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
1969 if(is_const(current,dops[i].rs1)) {
1970 int v=get_const(current,dops[i].rs1);
1971 set_const(current,dops[i].rt1,v+imm[i]);
1973 else clear_const(current,dops[i].rt1);
1976 set_const(current,dops[i].rt1,imm[i]<<16); // LUI
1978 dirty_reg(current,dops[i].rt1);
1981 static void load_alloc(struct regstat *current,int i)
1983 clear_const(current,dops[i].rt1);
1984 //if(dops[i].rs1!=dops[i].rt1&&needed_again(dops[i].rs1,i)) clear_const(current,dops[i].rs1); // Does this help or hurt?
1985 if(!dops[i].rs1) current->u&=~1LL; // Allow allocating r0 if it's the source register
1986 if (needed_again(dops[i].rs1, i))
1987 alloc_reg(current, i, dops[i].rs1);
1989 alloc_reg(current, i, ROREG);
1990 if(dops[i].rt1&&!((current->u>>dops[i].rt1)&1)) {
1991 alloc_reg(current,i,dops[i].rt1);
1992 assert(get_reg(current->regmap,dops[i].rt1)>=0);
1993 if(dops[i].opcode==0x27||dops[i].opcode==0x37) // LWU/LD
1997 else if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
2001 dirty_reg(current,dops[i].rt1);
2002 // LWL/LWR need a temporary register for the old value
2003 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2005 alloc_reg(current,i,FTEMP);
2006 alloc_reg_temp(current,i,-1);
2007 minimum_free_regs[i]=1;
2012 // Load to r0 or unneeded register (dummy load)
2013 // but we still need a register to calculate the address
2014 if(dops[i].opcode==0x22||dops[i].opcode==0x26)
2016 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
2018 alloc_reg_temp(current,i,-1);
2019 minimum_free_regs[i]=1;
2020 if(dops[i].opcode==0x1A||dops[i].opcode==0x1B) // LDL/LDR
2027 static void store_alloc(struct regstat *current,int i)
2029 clear_const(current,dops[i].rs2);
2030 if(!(dops[i].rs2)) current->u&=~1LL; // Allow allocating r0 if necessary
2031 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2032 alloc_reg(current,i,dops[i].rs2);
2033 if(dops[i].opcode==0x2c||dops[i].opcode==0x2d||dops[i].opcode==0x3f) { // 64-bit SDL/SDR/SD
2037 alloc_reg(current, i, ROREG);
2038 #if defined(HOST_IMM8)
2039 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2040 alloc_reg(current, i, INVCP);
2042 if(dops[i].opcode==0x2a||dops[i].opcode==0x2e||dops[i].opcode==0x2c||dops[i].opcode==0x2d) { // SWL/SWL/SDL/SDR
2043 alloc_reg(current,i,FTEMP);
2045 // We need a temporary register for address generation
2046 alloc_reg_temp(current,i,-1);
2047 minimum_free_regs[i]=1;
2050 static void c1ls_alloc(struct regstat *current,int i)
2052 clear_const(current,dops[i].rt1);
2053 alloc_reg(current,i,CSREG); // Status
2056 static void c2ls_alloc(struct regstat *current,int i)
2058 clear_const(current,dops[i].rt1);
2059 if(needed_again(dops[i].rs1,i)) alloc_reg(current,i,dops[i].rs1);
2060 alloc_reg(current,i,FTEMP);
2062 alloc_reg(current, i, ROREG);
2063 #if defined(HOST_IMM8)
2064 // On CPUs without 32-bit immediates we need a pointer to invalid_code
2065 if (dops[i].opcode == 0x3a) // SWC2
2066 alloc_reg(current,i,INVCP);
2068 // We need a temporary register for address generation
2069 alloc_reg_temp(current,i,-1);
2070 minimum_free_regs[i]=1;
2073 #ifndef multdiv_alloc
2074 static void multdiv_alloc(struct regstat *current,int i)
2081 // case 0x1D: DMULTU
2084 clear_const(current,dops[i].rs1);
2085 clear_const(current,dops[i].rs2);
2086 alloc_cc(current,i); // for stalls
2087 if(dops[i].rs1&&dops[i].rs2)
2089 if((dops[i].opcode2&4)==0) // 32-bit
2091 current->u&=~(1LL<<HIREG);
2092 current->u&=~(1LL<<LOREG);
2093 alloc_reg(current,i,HIREG);
2094 alloc_reg(current,i,LOREG);
2095 alloc_reg(current,i,dops[i].rs1);
2096 alloc_reg(current,i,dops[i].rs2);
2097 dirty_reg(current,HIREG);
2098 dirty_reg(current,LOREG);
2107 // Multiply by zero is zero.
2108 // MIPS does not have a divide by zero exception.
2109 // The result is undefined, we return zero.
2110 alloc_reg(current,i,HIREG);
2111 alloc_reg(current,i,LOREG);
2112 dirty_reg(current,HIREG);
2113 dirty_reg(current,LOREG);
2118 static void cop0_alloc(struct regstat *current,int i)
2120 if(dops[i].opcode2==0) // MFC0
2123 clear_const(current,dops[i].rt1);
2124 alloc_all(current,i);
2125 alloc_reg(current,i,dops[i].rt1);
2126 dirty_reg(current,dops[i].rt1);
2129 else if(dops[i].opcode2==4) // MTC0
2132 clear_const(current,dops[i].rs1);
2133 alloc_reg(current,i,dops[i].rs1);
2134 alloc_all(current,i);
2137 alloc_all(current,i); // FIXME: Keep r0
2139 alloc_reg(current,i,0);
2145 assert(dops[i].opcode2==0x10);
2146 alloc_all(current,i);
2148 minimum_free_regs[i]=HOST_REGS;
2151 static void cop2_alloc(struct regstat *current,int i)
2153 if (dops[i].opcode2 < 3) // MFC2/CFC2
2155 alloc_cc(current,i); // for stalls
2156 dirty_reg(current,CCREG);
2158 clear_const(current,dops[i].rt1);
2159 alloc_reg(current,i,dops[i].rt1);
2160 dirty_reg(current,dops[i].rt1);
2163 else if (dops[i].opcode2 > 3) // MTC2/CTC2
2166 clear_const(current,dops[i].rs1);
2167 alloc_reg(current,i,dops[i].rs1);
2171 alloc_reg(current,i,0);
2174 alloc_reg_temp(current,i,-1);
2175 minimum_free_regs[i]=1;
2178 static void c2op_alloc(struct regstat *current,int i)
2180 alloc_cc(current,i); // for stalls
2181 dirty_reg(current,CCREG);
2182 alloc_reg_temp(current,i,-1);
2185 static void syscall_alloc(struct regstat *current,int i)
2187 alloc_cc(current,i);
2188 dirty_reg(current,CCREG);
2189 alloc_all(current,i);
2190 minimum_free_regs[i]=HOST_REGS;
2194 static void delayslot_alloc(struct regstat *current,int i)
2196 switch(dops[i].itype) {
2204 imm16_alloc(current,i);
2208 load_alloc(current,i);
2212 store_alloc(current,i);
2215 alu_alloc(current,i);
2218 shift_alloc(current,i);
2221 multdiv_alloc(current,i);
2224 shiftimm_alloc(current,i);
2227 mov_alloc(current,i);
2230 cop0_alloc(current,i);
2235 cop2_alloc(current,i);
2238 c1ls_alloc(current,i);
2241 c2ls_alloc(current,i);
2244 c2op_alloc(current,i);
2249 static void add_stub(enum stub_type type, void *addr, void *retaddr,
2250 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
2252 assert(stubcount < ARRAY_SIZE(stubs));
2253 stubs[stubcount].type = type;
2254 stubs[stubcount].addr = addr;
2255 stubs[stubcount].retaddr = retaddr;
2256 stubs[stubcount].a = a;
2257 stubs[stubcount].b = b;
2258 stubs[stubcount].c = c;
2259 stubs[stubcount].d = d;
2260 stubs[stubcount].e = e;
2264 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
2265 int i, int addr_reg, const struct regstat *i_regs, int ccadj, u_int reglist)
2267 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
2270 // Write out a single register
2271 static void wb_register(signed char r, const signed char regmap[], uint64_t dirty)
2274 for(hr=0;hr<HOST_REGS;hr++) {
2275 if(hr!=EXCLUDE_REG) {
2278 assert(regmap[hr]<64);
2279 emit_storereg(r,hr);
2286 static void wb_valid(signed char pre[],signed char entry[],u_int dirty_pre,u_int dirty,uint64_t u)
2288 //if(dirty_pre==dirty) return;
2290 for (hr = 0; hr < HOST_REGS; hr++) {
2292 if (r < 1 || r > 33 || ((u >> r) & 1))
2294 if (((dirty_pre & ~dirty) >> hr) & 1)
2295 emit_storereg(r, hr);
2300 static void pass_args(int a0, int a1)
2304 emit_mov(a0,2); emit_mov(a1,1); emit_mov(2,0);
2306 else if(a0!=0&&a1==0) {
2308 if (a0>=0) emit_mov(a0,0);
2311 if(a0>=0&&a0!=0) emit_mov(a0,0);
2312 if(a1>=0&&a1!=1) emit_mov(a1,1);
2316 static void alu_assemble(int i, const struct regstat *i_regs)
2318 if(dops[i].opcode2>=0x20&&dops[i].opcode2<=0x23) { // ADD/ADDU/SUB/SUBU
2320 signed char s1,s2,t;
2321 t=get_reg(i_regs->regmap,dops[i].rt1);
2323 s1=get_reg(i_regs->regmap,dops[i].rs1);
2324 s2=get_reg(i_regs->regmap,dops[i].rs2);
2325 if(dops[i].rs1&&dops[i].rs2) {
2328 if(dops[i].opcode2&2) emit_sub(s1,s2,t);
2329 else emit_add(s1,s2,t);
2331 else if(dops[i].rs1) {
2332 if(s1>=0) emit_mov(s1,t);
2333 else emit_loadreg(dops[i].rs1,t);
2335 else if(dops[i].rs2) {
2337 if(dops[i].opcode2&2) emit_neg(s2,t);
2338 else emit_mov(s2,t);
2341 emit_loadreg(dops[i].rs2,t);
2342 if(dops[i].opcode2&2) emit_neg(t,t);
2345 else emit_zeroreg(t);
2349 if(dops[i].opcode2>=0x2c&&dops[i].opcode2<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2352 if(dops[i].opcode2==0x2a||dops[i].opcode2==0x2b) { // SLT/SLTU
2354 signed char s1l,s2l,t;
2356 t=get_reg(i_regs->regmap,dops[i].rt1);
2359 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2360 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2361 if(dops[i].rs2==0) // rx<r0
2363 if(dops[i].opcode2==0x2a&&dops[i].rs1!=0) { // SLT
2365 emit_shrimm(s1l,31,t);
2367 else // SLTU (unsigned can not be less than zero, 0<0)
2370 else if(dops[i].rs1==0) // r0<rx
2373 if(dops[i].opcode2==0x2a) // SLT
2374 emit_set_gz32(s2l,t);
2375 else // SLTU (set if not zero)
2376 emit_set_nz32(s2l,t);
2379 assert(s1l>=0);assert(s2l>=0);
2380 if(dops[i].opcode2==0x2a) // SLT
2381 emit_set_if_less32(s1l,s2l,t);
2383 emit_set_if_carry32(s1l,s2l,t);
2389 if(dops[i].opcode2>=0x24&&dops[i].opcode2<=0x27) { // AND/OR/XOR/NOR
2391 signed char s1l,s2l,tl;
2392 tl=get_reg(i_regs->regmap,dops[i].rt1);
2395 s1l=get_reg(i_regs->regmap,dops[i].rs1);
2396 s2l=get_reg(i_regs->regmap,dops[i].rs2);
2397 if(dops[i].rs1&&dops[i].rs2) {
2400 if(dops[i].opcode2==0x24) { // AND
2401 emit_and(s1l,s2l,tl);
2403 if(dops[i].opcode2==0x25) { // OR
2404 emit_or(s1l,s2l,tl);
2406 if(dops[i].opcode2==0x26) { // XOR
2407 emit_xor(s1l,s2l,tl);
2409 if(dops[i].opcode2==0x27) { // NOR
2410 emit_or(s1l,s2l,tl);
2416 if(dops[i].opcode2==0x24) { // AND
2419 if(dops[i].opcode2==0x25||dops[i].opcode2==0x26) { // OR/XOR
2421 if(s1l>=0) emit_mov(s1l,tl);
2422 else emit_loadreg(dops[i].rs1,tl); // CHECK: regmap_entry?
2426 if(s2l>=0) emit_mov(s2l,tl);
2427 else emit_loadreg(dops[i].rs2,tl); // CHECK: regmap_entry?
2429 else emit_zeroreg(tl);
2431 if(dops[i].opcode2==0x27) { // NOR
2433 if(s1l>=0) emit_not(s1l,tl);
2435 emit_loadreg(dops[i].rs1,tl);
2441 if(s2l>=0) emit_not(s2l,tl);
2443 emit_loadreg(dops[i].rs2,tl);
2447 else emit_movimm(-1,tl);
2456 static void imm16_assemble(int i, const struct regstat *i_regs)
2458 if (dops[i].opcode==0x0f) { // LUI
2461 t=get_reg(i_regs->regmap,dops[i].rt1);
2464 if(!((i_regs->isconst>>t)&1))
2465 emit_movimm(imm[i]<<16,t);
2469 if(dops[i].opcode==0x08||dops[i].opcode==0x09) { // ADDI/ADDIU
2472 t=get_reg(i_regs->regmap,dops[i].rt1);
2473 s=get_reg(i_regs->regmap,dops[i].rs1);
2478 if(!((i_regs->isconst>>t)&1)) {
2480 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2481 emit_addimm(t,imm[i],t);
2483 if(!((i_regs->wasconst>>s)&1))
2484 emit_addimm(s,imm[i],t);
2486 emit_movimm(constmap[i][s]+imm[i],t);
2492 if(!((i_regs->isconst>>t)&1))
2493 emit_movimm(imm[i],t);
2498 if(dops[i].opcode==0x18||dops[i].opcode==0x19) { // DADDI/DADDIU
2501 tl=get_reg(i_regs->regmap,dops[i].rt1);
2502 sl=get_reg(i_regs->regmap,dops[i].rs1);
2506 emit_addimm(sl,imm[i],tl);
2508 emit_movimm(imm[i],tl);
2513 else if(dops[i].opcode==0x0a||dops[i].opcode==0x0b) { // SLTI/SLTIU
2515 //assert(dops[i].rs1!=0); // r0 might be valid, but it's probably a bug
2517 t=get_reg(i_regs->regmap,dops[i].rt1);
2518 sl=get_reg(i_regs->regmap,dops[i].rs1);
2522 if(dops[i].opcode==0x0a) { // SLTI
2524 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2525 emit_slti32(t,imm[i],t);
2527 emit_slti32(sl,imm[i],t);
2532 if(i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2533 emit_sltiu32(t,imm[i],t);
2535 emit_sltiu32(sl,imm[i],t);
2539 // SLTI(U) with r0 is just stupid,
2540 // nonetheless examples can be found
2541 if(dops[i].opcode==0x0a) // SLTI
2542 if(0<imm[i]) emit_movimm(1,t);
2543 else emit_zeroreg(t);
2546 if(imm[i]) emit_movimm(1,t);
2547 else emit_zeroreg(t);
2553 else if(dops[i].opcode>=0x0c&&dops[i].opcode<=0x0e) { // ANDI/ORI/XORI
2556 tl=get_reg(i_regs->regmap,dops[i].rt1);
2557 sl=get_reg(i_regs->regmap,dops[i].rs1);
2558 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2559 if(dops[i].opcode==0x0c) //ANDI
2563 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2564 emit_andimm(tl,imm[i],tl);
2566 if(!((i_regs->wasconst>>sl)&1))
2567 emit_andimm(sl,imm[i],tl);
2569 emit_movimm(constmap[i][sl]&imm[i],tl);
2579 if(i_regs->regmap_entry[tl]!=dops[i].rs1) emit_loadreg(dops[i].rs1,tl);
2581 if(dops[i].opcode==0x0d) { // ORI
2583 emit_orimm(tl,imm[i],tl);
2585 if(!((i_regs->wasconst>>sl)&1))
2586 emit_orimm(sl,imm[i],tl);
2588 emit_movimm(constmap[i][sl]|imm[i],tl);
2591 if(dops[i].opcode==0x0e) { // XORI
2593 emit_xorimm(tl,imm[i],tl);
2595 if(!((i_regs->wasconst>>sl)&1))
2596 emit_xorimm(sl,imm[i],tl);
2598 emit_movimm(constmap[i][sl]^imm[i],tl);
2603 emit_movimm(imm[i],tl);
2611 static void shiftimm_assemble(int i, const struct regstat *i_regs)
2613 if(dops[i].opcode2<=0x3) // SLL/SRL/SRA
2617 t=get_reg(i_regs->regmap,dops[i].rt1);
2618 s=get_reg(i_regs->regmap,dops[i].rs1);
2620 if(t>=0&&!((i_regs->isconst>>t)&1)){
2627 if(s<0&&i_regs->regmap_entry[t]!=dops[i].rs1) emit_loadreg(dops[i].rs1,t);
2629 if(dops[i].opcode2==0) // SLL
2631 emit_shlimm(s<0?t:s,imm[i],t);
2633 if(dops[i].opcode2==2) // SRL
2635 emit_shrimm(s<0?t:s,imm[i],t);
2637 if(dops[i].opcode2==3) // SRA
2639 emit_sarimm(s<0?t:s,imm[i],t);
2643 if(s>=0 && s!=t) emit_mov(s,t);
2647 //emit_storereg(dops[i].rt1,t); //DEBUG
2650 if(dops[i].opcode2>=0x38&&dops[i].opcode2<=0x3b) // DSLL/DSRL/DSRA
2654 if(dops[i].opcode2==0x3c) // DSLL32
2658 if(dops[i].opcode2==0x3e) // DSRL32
2662 if(dops[i].opcode2==0x3f) // DSRA32
2668 #ifndef shift_assemble
2669 static void shift_assemble(int i, const struct regstat *i_regs)
2671 signed char s,t,shift;
2672 if (dops[i].rt1 == 0)
2674 assert(dops[i].opcode2<=0x07); // SLLV/SRLV/SRAV
2675 t = get_reg(i_regs->regmap, dops[i].rt1);
2676 s = get_reg(i_regs->regmap, dops[i].rs1);
2677 shift = get_reg(i_regs->regmap, dops[i].rs2);
2683 else if(dops[i].rs2==0) {
2685 if(s!=t) emit_mov(s,t);
2688 host_tempreg_acquire();
2689 emit_andimm(shift,31,HOST_TEMPREG);
2690 switch(dops[i].opcode2) {
2692 emit_shl(s,HOST_TEMPREG,t);
2695 emit_shr(s,HOST_TEMPREG,t);
2698 emit_sar(s,HOST_TEMPREG,t);
2703 host_tempreg_release();
2717 static int get_ptr_mem_type(u_int a)
2719 if(a < 0x00200000) {
2720 if(a<0x1000&&((start>>20)==0xbfc||(start>>24)==0xa0))
2721 // return wrong, must use memhandler for BIOS self-test to pass
2722 // 007 does similar stuff from a00 mirror, weird stuff
2726 if(0x1f800000 <= a && a < 0x1f801000)
2728 if(0x80200000 <= a && a < 0x80800000)
2730 if(0xa0000000 <= a && a < 0xa0200000)
2735 static int get_ro_reg(const struct regstat *i_regs, int host_tempreg_free)
2737 int r = get_reg(i_regs->regmap, ROREG);
2738 if (r < 0 && host_tempreg_free) {
2739 host_tempreg_acquire();
2740 emit_loadreg(ROREG, r = HOST_TEMPREG);
2747 static void *emit_fastpath_cmp_jump(int i, const struct regstat *i_regs,
2748 int addr, int *offset_reg, int *addr_reg_override)
2752 int mr = dops[i].rs1;
2754 if(((smrv_strong|smrv_weak)>>mr)&1) {
2755 type=get_ptr_mem_type(smrv[mr]);
2756 //printf("set %08x @%08x r%d %d\n", smrv[mr], start+i*4, mr, type);
2759 // use the mirror we are running on
2760 type=get_ptr_mem_type(start);
2761 //printf("set nospec @%08x r%d %d\n", start+i*4, mr, type);
2764 if(type==MTYPE_8020) { // RAM 80200000+ mirror
2765 host_tempreg_acquire();
2766 emit_andimm(addr,~0x00e00000,HOST_TEMPREG);
2767 addr=*addr_reg_override=HOST_TEMPREG;
2770 else if(type==MTYPE_0000) { // RAM 0 mirror
2771 host_tempreg_acquire();
2772 emit_orimm(addr,0x80000000,HOST_TEMPREG);
2773 addr=*addr_reg_override=HOST_TEMPREG;
2776 else if(type==MTYPE_A000) { // RAM A mirror
2777 host_tempreg_acquire();
2778 emit_andimm(addr,~0x20000000,HOST_TEMPREG);
2779 addr=*addr_reg_override=HOST_TEMPREG;
2782 else if(type==MTYPE_1F80) { // scratchpad
2783 if (psxH == (void *)0x1f800000) {
2784 host_tempreg_acquire();
2785 emit_xorimm(addr,0x1f800000,HOST_TEMPREG);
2786 emit_cmpimm(HOST_TEMPREG,0x1000);
2787 host_tempreg_release();
2792 // do the usual RAM check, jump will go to the right handler
2797 if (type == 0) // need ram check
2799 emit_cmpimm(addr,RAM_SIZE);
2801 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2802 // Hint to branch predictor that the branch is unlikely to be taken
2803 if (dops[i].rs1 >= 28)
2804 emit_jno_unlikely(0);
2808 if (ram_offset != 0)
2809 *offset_reg = get_ro_reg(i_regs, 0);
2815 // return memhandler, or get directly accessable address and return 0
2816 static void *get_direct_memhandler(void *table, u_int addr,
2817 enum stub_type type, uintptr_t *addr_host)
2819 uintptr_t msb = 1ull << (sizeof(uintptr_t)*8 - 1);
2820 uintptr_t l1, l2 = 0;
2821 l1 = ((uintptr_t *)table)[addr>>12];
2823 uintptr_t v = l1 << 1;
2824 *addr_host = v + addr;
2829 if (type == LOADB_STUB || type == LOADBU_STUB || type == STOREB_STUB)
2830 l2 = ((uintptr_t *)l1)[0x1000/4 + 0x1000/2 + (addr&0xfff)];
2831 else if (type == LOADH_STUB || type == LOADHU_STUB || type == STOREH_STUB)
2832 l2 = ((uintptr_t *)l1)[0x1000/4 + (addr&0xfff)/2];
2834 l2 = ((uintptr_t *)l1)[(addr&0xfff)/4];
2836 uintptr_t v = l2 << 1;
2837 *addr_host = v + (addr&0xfff);
2840 return (void *)(l2 << 1);
2844 static u_int get_host_reglist(const signed char *regmap)
2846 u_int reglist = 0, hr;
2847 for (hr = 0; hr < HOST_REGS; hr++) {
2848 if (hr != EXCLUDE_REG && regmap[hr] >= 0)
2854 static u_int reglist_exclude(u_int reglist, int r1, int r2)
2857 reglist &= ~(1u << r1);
2859 reglist &= ~(1u << r2);
2863 // find a temp caller-saved register not in reglist (so assumed to be free)
2864 static int reglist_find_free(u_int reglist)
2866 u_int free_regs = ~reglist & CALLER_SAVE_REGS;
2869 return __builtin_ctz(free_regs);
2872 static void do_load_word(int a, int rt, int offset_reg)
2874 if (offset_reg >= 0)
2875 emit_ldr_dualindexed(offset_reg, a, rt);
2877 emit_readword_indexed(0, a, rt);
2880 static void do_store_word(int a, int ofs, int rt, int offset_reg, int preseve_a)
2882 if (offset_reg < 0) {
2883 emit_writeword_indexed(rt, ofs, a);
2887 emit_addimm(a, ofs, a);
2888 emit_str_dualindexed(offset_reg, a, rt);
2889 if (ofs != 0 && preseve_a)
2890 emit_addimm(a, -ofs, a);
2893 static void do_store_hword(int a, int ofs, int rt, int offset_reg, int preseve_a)
2895 if (offset_reg < 0) {
2896 emit_writehword_indexed(rt, ofs, a);
2900 emit_addimm(a, ofs, a);
2901 emit_strh_dualindexed(offset_reg, a, rt);
2902 if (ofs != 0 && preseve_a)
2903 emit_addimm(a, -ofs, a);
2906 static void do_store_byte(int a, int rt, int offset_reg)
2908 if (offset_reg >= 0)
2909 emit_strb_dualindexed(offset_reg, a, rt);
2911 emit_writebyte_indexed(rt, 0, a);
2914 static void load_assemble(int i, const struct regstat *i_regs, int ccadj_)
2919 int memtarget=0,c=0;
2920 int offset_reg = -1;
2921 int fastio_reg_override = -1;
2922 u_int reglist=get_host_reglist(i_regs->regmap);
2923 tl=get_reg(i_regs->regmap,dops[i].rt1);
2924 s=get_reg(i_regs->regmap,dops[i].rs1);
2926 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2928 c=(i_regs->wasconst>>s)&1;
2930 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2933 //printf("load_assemble: c=%d\n",c);
2934 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2935 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2936 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2938 // could be FIFO, must perform the read
2940 assem_debug("(forced read)\n");
2941 tl=get_reg_temp(i_regs->regmap);
2944 if(offset||s<0||c) addr=tl;
2946 //if(tl<0) tl=get_reg_temp(i_regs->regmap);
2948 //printf("load_assemble: c=%d\n",c);
2949 //if(c) printf("load_assemble: const=%lx\n",(long)constmap[i][s]+offset);
2950 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2954 // Strmnnrmn's speed hack
2955 if(dops[i].rs1!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2958 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
2959 &offset_reg, &fastio_reg_override);
2962 else if (ram_offset && memtarget) {
2963 offset_reg = get_ro_reg(i_regs, 0);
2965 int dummy=(dops[i].rt1==0)||(tl!=get_reg(i_regs->regmap,dops[i].rt1)); // ignore loads to r0 and unneeded reg
2966 switch (dops[i].opcode) {
2972 if (fastio_reg_override >= 0)
2973 a = fastio_reg_override;
2975 if (offset_reg >= 0)
2976 emit_ldrsb_dualindexed(offset_reg, a, tl);
2978 emit_movsbl_indexed(0, a, tl);
2981 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
2984 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
2991 if (fastio_reg_override >= 0)
2992 a = fastio_reg_override;
2993 if (offset_reg >= 0)
2994 emit_ldrsh_dualindexed(offset_reg, a, tl);
2996 emit_movswl_indexed(0, a, tl);
2999 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3002 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3008 if (fastio_reg_override >= 0)
3009 a = fastio_reg_override;
3010 do_load_word(a, tl, offset_reg);
3013 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3016 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3023 if (fastio_reg_override >= 0)
3024 a = fastio_reg_override;
3026 if (offset_reg >= 0)
3027 emit_ldrb_dualindexed(offset_reg, a, tl);
3029 emit_movzbl_indexed(0, a, tl);
3032 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3035 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3042 if (fastio_reg_override >= 0)
3043 a = fastio_reg_override;
3044 if (offset_reg >= 0)
3045 emit_ldrh_dualindexed(offset_reg, a, tl);
3047 emit_movzwl_indexed(0, a, tl);
3050 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3053 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,dops[i].rt1,ccadj_,reglist);
3061 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3062 host_tempreg_release();
3065 #ifndef loadlr_assemble
3066 static void loadlr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3068 int s,tl,temp,temp2,addr;
3071 int memtarget=0,c=0;
3072 int offset_reg = -1;
3073 int fastio_reg_override = -1;
3074 u_int reglist=get_host_reglist(i_regs->regmap);
3075 tl=get_reg(i_regs->regmap,dops[i].rt1);
3076 s=get_reg(i_regs->regmap,dops[i].rs1);
3077 temp=get_reg_temp(i_regs->regmap);
3078 temp2=get_reg(i_regs->regmap,FTEMP);
3079 addr=get_reg(i_regs->regmap,AGEN1+(i&1));
3083 if(offset||s<0||c) addr=temp2;
3086 c=(i_regs->wasconst>>s)&1;
3088 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3092 emit_shlimm(addr,3,temp);
3093 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3094 emit_andimm(addr,0xFFFFFFFC,temp2); // LWL/LWR
3096 emit_andimm(addr,0xFFFFFFF8,temp2); // LDL/LDR
3098 jaddr = emit_fastpath_cmp_jump(i, i_regs, temp2,
3099 &offset_reg, &fastio_reg_override);
3102 if (ram_offset && memtarget) {
3103 offset_reg = get_ro_reg(i_regs, 0);
3105 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
3106 emit_movimm(((constmap[i][s]+offset)<<3)&24,temp); // LWL/LWR
3108 emit_movimm(((constmap[i][s]+offset)<<3)&56,temp); // LDL/LDR
3111 if (dops[i].opcode==0x22||dops[i].opcode==0x26) { // LWL/LWR
3114 if (fastio_reg_override >= 0)
3115 a = fastio_reg_override;
3116 do_load_word(a, temp2, offset_reg);
3117 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3118 host_tempreg_release();
3119 if(jaddr) add_stub_r(LOADW_STUB,jaddr,out,i,temp2,i_regs,ccadj_,reglist);
3122 inline_readstub(LOADW_STUB,i,(constmap[i][s]+offset)&0xFFFFFFFC,i_regs->regmap,FTEMP,ccadj_,reglist);
3125 emit_andimm(temp,24,temp);
3126 if (dops[i].opcode==0x22) // LWL
3127 emit_xorimm(temp,24,temp);
3128 host_tempreg_acquire();
3129 emit_movimm(-1,HOST_TEMPREG);
3130 if (dops[i].opcode==0x26) {
3131 emit_shr(temp2,temp,temp2);
3132 emit_bic_lsr(tl,HOST_TEMPREG,temp,tl);
3134 emit_shl(temp2,temp,temp2);
3135 emit_bic_lsl(tl,HOST_TEMPREG,temp,tl);
3137 host_tempreg_release();
3138 emit_or(temp2,tl,tl);
3140 //emit_storereg(dops[i].rt1,tl); // DEBUG
3142 if (dops[i].opcode==0x1A||dops[i].opcode==0x1B) { // LDL/LDR
3148 static void store_assemble(int i, const struct regstat *i_regs, int ccadj_)
3154 enum stub_type type=0;
3155 int memtarget=0,c=0;
3156 int agr=AGEN1+(i&1);
3157 int offset_reg = -1;
3158 int fastio_reg_override = -1;
3159 u_int reglist=get_host_reglist(i_regs->regmap);
3160 tl=get_reg(i_regs->regmap,dops[i].rs2);
3161 s=get_reg(i_regs->regmap,dops[i].rs1);
3162 temp=get_reg(i_regs->regmap,agr);
3163 if(temp<0) temp=get_reg_temp(i_regs->regmap);
3166 c=(i_regs->wasconst>>s)&1;
3168 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3173 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3174 if(offset||s<0||c) addr=temp;
3177 jaddr = emit_fastpath_cmp_jump(i, i_regs, addr,
3178 &offset_reg, &fastio_reg_override);
3180 else if (ram_offset && memtarget) {
3181 offset_reg = get_ro_reg(i_regs, 0);
3184 switch (dops[i].opcode) {
3189 if (fastio_reg_override >= 0)
3190 a = fastio_reg_override;
3191 do_store_byte(a, tl, offset_reg);
3199 if (fastio_reg_override >= 0)
3200 a = fastio_reg_override;
3201 do_store_hword(a, 0, tl, offset_reg, 1);
3208 if (fastio_reg_override >= 0)
3209 a = fastio_reg_override;
3210 do_store_word(a, 0, tl, offset_reg, 1);
3218 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3219 host_tempreg_release();
3221 // PCSX store handlers don't check invcode again
3223 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3226 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3228 #ifdef DESTRUCTIVE_SHIFT
3229 // The x86 shift operation is 'destructive'; it overwrites the
3230 // source register, so we need to make a copy first and use that.
3233 #if defined(HOST_IMM8)
3234 int ir=get_reg(i_regs->regmap,INVCP);
3236 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3238 emit_cmpmem_indexedsr12_imm(invalid_code,addr,1);
3240 #ifdef INVALIDATE_USE_COND_CALL
3241 emit_callne(invalidate_addr_reg[addr]);
3245 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3249 u_int addr_val=constmap[i][s]+offset;
3251 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj_,reglist);
3252 } else if(c&&!memtarget) {
3253 inline_writestub(type,i,addr_val,i_regs->regmap,dops[i].rs2,ccadj_,reglist);
3255 // basic current block modification detection..
3256 // not looking back as that should be in mips cache already
3257 // (see Spyro2 title->attract mode)
3258 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3259 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3260 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3261 if(i_regs->regmap==regs[i].regmap) {
3262 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3263 wb_dirtys(regs[i].regmap_entry,regs[i].wasdirty);
3264 emit_movimm(start+i*4+4,0);
3265 emit_writeword(0,&pcaddr);
3266 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3267 emit_far_call(ndrc_get_addr_ht);
3273 static void storelr_assemble(int i, const struct regstat *i_regs, int ccadj_)
3279 void *case1, *case23, *case3;
3280 void *done0, *done1, *done2;
3281 int memtarget=0,c=0;
3282 int agr=AGEN1+(i&1);
3283 int offset_reg = -1;
3284 u_int reglist=get_host_reglist(i_regs->regmap);
3285 tl=get_reg(i_regs->regmap,dops[i].rs2);
3286 s=get_reg(i_regs->regmap,dops[i].rs1);
3287 temp=get_reg(i_regs->regmap,agr);
3288 if(temp<0) temp=get_reg_temp(i_regs->regmap);
3291 c=(i_regs->isconst>>s)&1;
3293 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3299 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3300 if(!offset&&s!=temp) emit_mov(s,temp);
3306 if(!memtarget||!dops[i].rs1) {
3312 offset_reg = get_ro_reg(i_regs, 0);
3314 if (dops[i].opcode==0x2C||dops[i].opcode==0x2D) { // SDL/SDR
3318 emit_testimm(temp,2);
3321 emit_testimm(temp,1);
3325 if (dops[i].opcode == 0x2A) { // SWL
3326 // Write msb into least significant byte
3327 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3328 do_store_byte(temp, tl, offset_reg);
3329 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3331 else if (dops[i].opcode == 0x2E) { // SWR
3332 // Write entire word
3333 do_store_word(temp, 0, tl, offset_reg, 1);
3338 set_jump_target(case1, out);
3339 if (dops[i].opcode == 0x2A) { // SWL
3340 // Write two msb into two least significant bytes
3341 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3342 do_store_hword(temp, -1, tl, offset_reg, 0);
3343 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3345 else if (dops[i].opcode == 0x2E) { // SWR
3346 // Write 3 lsb into three most significant bytes
3347 do_store_byte(temp, tl, offset_reg);
3348 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3349 do_store_hword(temp, 1, tl, offset_reg, 0);
3350 if (dops[i].rs2) emit_rorimm(tl, 24, tl);
3355 set_jump_target(case23, out);
3356 emit_testimm(temp,1);
3360 if (dops[i].opcode==0x2A) { // SWL
3361 // Write 3 msb into three least significant bytes
3362 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3363 do_store_hword(temp, -2, tl, offset_reg, 1);
3364 if (dops[i].rs2) emit_rorimm(tl, 16, tl);
3365 do_store_byte(temp, tl, offset_reg);
3366 if (dops[i].rs2) emit_rorimm(tl, 8, tl);
3368 else if (dops[i].opcode == 0x2E) { // SWR
3369 // Write two lsb into two most significant bytes
3370 do_store_hword(temp, 0, tl, offset_reg, 1);
3375 set_jump_target(case3, out);
3376 if (dops[i].opcode == 0x2A) { // SWL
3377 do_store_word(temp, -3, tl, offset_reg, 0);
3379 else if (dops[i].opcode == 0x2E) { // SWR
3380 do_store_byte(temp, tl, offset_reg);
3382 set_jump_target(done0, out);
3383 set_jump_target(done1, out);
3384 set_jump_target(done2, out);
3385 if (offset_reg == HOST_TEMPREG)
3386 host_tempreg_release();
3388 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj_,reglist);
3389 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3390 #if defined(HOST_IMM8)
3391 int ir=get_reg(i_regs->regmap,INVCP);
3393 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3395 emit_cmpmem_indexedsr12_imm(invalid_code,temp,1);
3397 #ifdef INVALIDATE_USE_COND_CALL
3398 emit_callne(invalidate_addr_reg[temp]);
3402 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3407 static void cop0_assemble(int i, const struct regstat *i_regs, int ccadj_)
3409 if(dops[i].opcode2==0) // MFC0
3411 signed char t=get_reg(i_regs->regmap,dops[i].rt1);
3412 u_int copr=(source[i]>>11)&0x1f;
3413 //assert(t>=0); // Why does this happen? OOT is weird
3414 if(t>=0&&dops[i].rt1!=0) {
3415 emit_readword(®_cop0[copr],t);
3418 else if(dops[i].opcode2==4) // MTC0
3420 signed char s=get_reg(i_regs->regmap,dops[i].rs1);
3421 char copr=(source[i]>>11)&0x1f;
3423 wb_register(dops[i].rs1,i_regs->regmap,i_regs->dirty);
3424 if(copr==9||copr==11||copr==12||copr==13) {
3425 emit_readword(&last_count,HOST_TEMPREG);
3426 emit_loadreg(CCREG,HOST_CCREG); // TODO: do proper reg alloc
3427 emit_add(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3428 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
3429 emit_writeword(HOST_CCREG,&Count);
3431 // What a mess. The status register (12) can enable interrupts,
3432 // so needs a special case to handle a pending interrupt.
3433 // The interrupt must be taken immediately, because a subsequent
3434 // instruction might disable interrupts again.
3435 if(copr==12||copr==13) {
3437 // burn cycles to cause cc_interrupt, which will
3438 // reschedule next_interupt. Relies on CCREG from above.
3439 assem_debug("MTC0 DS %d\n", copr);
3440 emit_writeword(HOST_CCREG,&last_count);
3441 emit_movimm(0,HOST_CCREG);
3442 emit_storereg(CCREG,HOST_CCREG);
3443 emit_loadreg(dops[i].rs1,1);
3444 emit_movimm(copr,0);
3445 emit_far_call(pcsx_mtc0_ds);
3446 emit_loadreg(dops[i].rs1,s);
3449 emit_movimm(start+i*4+4,HOST_TEMPREG);
3450 emit_writeword(HOST_TEMPREG,&pcaddr);
3451 emit_movimm(0,HOST_TEMPREG);
3452 emit_writeword(HOST_TEMPREG,&pending_exception);
3455 emit_loadreg(dops[i].rs1,1);
3458 emit_movimm(copr,0);
3459 emit_far_call(pcsx_mtc0);
3460 if(copr==9||copr==11||copr==12||copr==13) {
3461 emit_readword(&Count,HOST_CCREG);
3462 emit_readword(&next_interupt,HOST_TEMPREG);
3463 emit_addimm(HOST_CCREG,-ccadj_,HOST_CCREG);
3464 emit_sub(HOST_CCREG,HOST_TEMPREG,HOST_CCREG);
3465 emit_writeword(HOST_TEMPREG,&last_count);
3466 emit_storereg(CCREG,HOST_CCREG);
3468 if(copr==12||copr==13) {
3469 assert(!is_delayslot);
3470 emit_readword(&pending_exception,14);
3474 emit_readword(&pcaddr, 0);
3475 emit_addimm(HOST_CCREG,2,HOST_CCREG);
3476 emit_far_call(ndrc_get_addr_ht);
3478 set_jump_target(jaddr, out);
3480 emit_loadreg(dops[i].rs1,s);
3484 assert(dops[i].opcode2==0x10);
3485 //if((source[i]&0x3f)==0x10) // RFE
3487 emit_readword(&Status,0);
3488 emit_andimm(0,0x3c,1);
3489 emit_andimm(0,~0xf,0);
3490 emit_orrshr_imm(1,2,0);
3491 emit_writeword(0,&Status);
3496 static void cop1_unusable(int i, const struct regstat *i_regs)
3498 // XXX: should just just do the exception instead
3503 add_stub_r(FP_STUB,jaddr,out,i,0,i_regs,is_delayslot,0);
3507 static void cop1_assemble(int i, const struct regstat *i_regs)
3509 cop1_unusable(i, i_regs);
3512 static void c1ls_assemble(int i, const struct regstat *i_regs)
3514 cop1_unusable(i, i_regs);
3518 static void do_cop1stub(int n)
3521 assem_debug("do_cop1stub %x\n",start+stubs[n].a*4);
3522 set_jump_target(stubs[n].addr, out);
3524 // int rs=stubs[n].b;
3525 struct regstat *i_regs=(struct regstat *)stubs[n].c;
3528 load_all_consts(regs[i].regmap_entry,regs[i].wasdirty,i);
3529 //if(i_regs!=®s[i]) printf("oops: regs[i]=%x i_regs=%x",(int)®s[i],(int)i_regs);
3531 //else {printf("fp exception in delay slot\n");}
3532 wb_dirtys(i_regs->regmap_entry,i_regs->wasdirty);
3533 if(regs[i].regmap_entry[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
3534 emit_movimm(start+(i-ds)*4,EAX); // Get PC
3535 emit_addimm(HOST_CCREG,ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3536 emit_far_jump(ds?fp_exception_ds:fp_exception);
3539 static int cop2_is_stalling_op(int i, int *cycles)
3541 if (dops[i].opcode == 0x3a) { // SWC2
3545 if (dops[i].itype == COP2 && (dops[i].opcode2 == 0 || dops[i].opcode2 == 2)) { // MFC2/CFC2
3549 if (dops[i].itype == C2OP) {
3550 *cycles = gte_cycletab[source[i] & 0x3f];
3553 // ... what about MTC2/CTC2/LWC2?
3558 static void log_gte_stall(int stall, u_int cycle)
3560 if ((u_int)stall <= 44)
3561 printf("x stall %2d %u\n", stall, cycle + last_count);
3564 static void emit_log_gte_stall(int i, int stall, u_int reglist)
3568 emit_movimm(stall, 0);
3570 emit_mov(HOST_TEMPREG, 0);
3571 emit_addimm(HOST_CCREG, ccadj[i], 1);
3572 emit_far_call(log_gte_stall);
3573 restore_regs(reglist);
3577 static void cop2_do_stall_check(u_int op, int i, const struct regstat *i_regs, u_int reglist)
3579 int j = i, other_gte_op_cycles = -1, stall = -MAXBLOCK, cycles_passed;
3580 int rtmp = reglist_find_free(reglist);
3582 if (HACK_ENABLED(NDHACK_NO_STALLS))
3584 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3585 // happens occasionally... cc evicted? Don't bother then
3586 //printf("no cc %08x\n", start + i*4);
3590 for (j = i - 1; j >= 0; j--) {
3591 //if (dops[j].is_ds) break;
3592 if (cop2_is_stalling_op(j, &other_gte_op_cycles) || dops[j].bt)
3594 if (j > 0 && ccadj[j - 1] > ccadj[j])
3599 cycles_passed = ccadj[i] - ccadj[j];
3600 if (other_gte_op_cycles >= 0)
3601 stall = other_gte_op_cycles - cycles_passed;
3602 else if (cycles_passed >= 44)
3603 stall = 0; // can't stall
3604 if (stall == -MAXBLOCK && rtmp >= 0) {
3605 // unknown stall, do the expensive runtime check
3606 assem_debug("; cop2_do_stall_check\n");
3609 emit_movimm(gte_cycletab[op], 0);
3610 emit_addimm(HOST_CCREG, ccadj[i], 1);
3611 emit_far_call(call_gteStall);
3612 restore_regs(reglist);
3614 host_tempreg_acquire();
3615 emit_readword(&psxRegs.gteBusyCycle, rtmp);
3616 emit_addimm(rtmp, -ccadj[i], rtmp);
3617 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3618 emit_cmpimm(HOST_TEMPREG, 44);
3619 emit_cmovb_reg(rtmp, HOST_CCREG);
3620 //emit_log_gte_stall(i, 0, reglist);
3621 host_tempreg_release();
3624 else if (stall > 0) {
3625 //emit_log_gte_stall(i, stall, reglist);
3626 emit_addimm(HOST_CCREG, stall, HOST_CCREG);
3629 // save gteBusyCycle, if needed
3630 if (gte_cycletab[op] == 0)
3632 other_gte_op_cycles = -1;
3633 for (j = i + 1; j < slen; j++) {
3634 if (cop2_is_stalling_op(j, &other_gte_op_cycles))
3636 if (dops[j].is_jump) {
3638 if (j + 1 < slen && cop2_is_stalling_op(j + 1, &other_gte_op_cycles))
3643 if (other_gte_op_cycles >= 0)
3644 // will handle stall when assembling that op
3646 cycles_passed = ccadj[min(j, slen -1)] - ccadj[i];
3647 if (cycles_passed >= 44)
3649 assem_debug("; save gteBusyCycle\n");
3650 host_tempreg_acquire();
3652 emit_readword(&last_count, HOST_TEMPREG);
3653 emit_add(HOST_TEMPREG, HOST_CCREG, HOST_TEMPREG);
3654 emit_addimm(HOST_TEMPREG, ccadj[i], HOST_TEMPREG);
3655 emit_addimm(HOST_TEMPREG, gte_cycletab[op]), HOST_TEMPREG);
3656 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3658 emit_addimm(HOST_CCREG, ccadj[i] + gte_cycletab[op], HOST_TEMPREG);
3659 emit_writeword(HOST_TEMPREG, &psxRegs.gteBusyCycle);
3661 host_tempreg_release();
3664 static int is_mflohi(int i)
3666 return (dops[i].itype == MOV && (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG));
3669 static int check_multdiv(int i, int *cycles)
3671 if (dops[i].itype != MULTDIV)
3673 if (dops[i].opcode2 == 0x18 || dops[i].opcode2 == 0x19) // MULT(U)
3674 *cycles = 11; // approx from 7 11 14
3680 static void multdiv_prepare_stall(int i, const struct regstat *i_regs, int ccadj_)
3682 int j, found = 0, c = 0;
3683 if (HACK_ENABLED(NDHACK_NO_STALLS))
3685 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG) {
3686 // happens occasionally... cc evicted? Don't bother then
3689 for (j = i + 1; j < slen; j++) {
3692 if ((found = is_mflohi(j)))
3694 if (dops[j].is_jump) {
3696 if (j + 1 < slen && (found = is_mflohi(j + 1)))
3702 // handle all in multdiv_do_stall()
3704 check_multdiv(i, &c);
3706 assem_debug("; muldiv prepare stall %d\n", c);
3707 host_tempreg_acquire();
3708 emit_addimm(HOST_CCREG, ccadj_ + c, HOST_TEMPREG);
3709 emit_writeword(HOST_TEMPREG, &psxRegs.muldivBusyCycle);
3710 host_tempreg_release();
3713 static void multdiv_do_stall(int i, const struct regstat *i_regs)
3715 int j, known_cycles = 0;
3716 u_int reglist = get_host_reglist(i_regs->regmap);
3717 int rtmp = get_reg_temp(i_regs->regmap);
3719 rtmp = reglist_find_free(reglist);
3720 if (HACK_ENABLED(NDHACK_NO_STALLS))
3722 if (get_reg(i_regs->regmap, CCREG) != HOST_CCREG || rtmp < 0) {
3723 // happens occasionally... cc evicted? Don't bother then
3724 //printf("no cc/rtmp %08x\n", start + i*4);
3728 for (j = i - 1; j >= 0; j--) {
3729 if (dops[j].is_ds) break;
3730 if (check_multdiv(j, &known_cycles))
3733 // already handled by this op
3735 if (dops[j].bt || (j > 0 && ccadj[j - 1] > ccadj[j]))
3740 if (known_cycles > 0) {
3741 known_cycles -= ccadj[i] - ccadj[j];
3742 assem_debug("; muldiv stall resolved %d\n", known_cycles);
3743 if (known_cycles > 0)
3744 emit_addimm(HOST_CCREG, known_cycles, HOST_CCREG);
3747 assem_debug("; muldiv stall unresolved\n");
3748 host_tempreg_acquire();
3749 emit_readword(&psxRegs.muldivBusyCycle, rtmp);
3750 emit_addimm(rtmp, -ccadj[i], rtmp);
3751 emit_sub(rtmp, HOST_CCREG, HOST_TEMPREG);
3752 emit_cmpimm(HOST_TEMPREG, 37);
3753 emit_cmovb_reg(rtmp, HOST_CCREG);
3754 //emit_log_gte_stall(i, 0, reglist);
3755 host_tempreg_release();
3758 static void cop2_get_dreg(u_int copr,signed char tl,signed char temp)
3768 emit_readword(®_cop2d[copr],tl);
3769 emit_signextend16(tl,tl);
3770 emit_writeword(tl,®_cop2d[copr]); // hmh
3777 emit_readword(®_cop2d[copr],tl);
3778 emit_andimm(tl,0xffff,tl);
3779 emit_writeword(tl,®_cop2d[copr]);
3782 emit_readword(®_cop2d[14],tl); // SXY2
3783 emit_writeword(tl,®_cop2d[copr]);
3787 c2op_mfc2_29_assemble(tl,temp);
3790 emit_readword(®_cop2d[copr],tl);
3795 static void cop2_put_dreg(u_int copr,signed char sl,signed char temp)
3799 emit_readword(®_cop2d[13],temp); // SXY1
3800 emit_writeword(sl,®_cop2d[copr]);
3801 emit_writeword(temp,®_cop2d[12]); // SXY0
3802 emit_readword(®_cop2d[14],temp); // SXY2
3803 emit_writeword(sl,®_cop2d[14]);
3804 emit_writeword(temp,®_cop2d[13]); // SXY1
3807 emit_andimm(sl,0x001f,temp);
3808 emit_shlimm(temp,7,temp);
3809 emit_writeword(temp,®_cop2d[9]);
3810 emit_andimm(sl,0x03e0,temp);
3811 emit_shlimm(temp,2,temp);
3812 emit_writeword(temp,®_cop2d[10]);
3813 emit_andimm(sl,0x7c00,temp);
3814 emit_shrimm(temp,3,temp);
3815 emit_writeword(temp,®_cop2d[11]);
3816 emit_writeword(sl,®_cop2d[28]);
3819 emit_xorsar_imm(sl,sl,31,temp);
3820 #if defined(HAVE_ARMV5) || defined(__aarch64__)
3821 emit_clz(temp,temp);
3823 emit_movs(temp,HOST_TEMPREG);
3824 emit_movimm(0,temp);
3825 emit_jeq((int)out+4*4);
3826 emit_addpl_imm(temp,1,temp);
3827 emit_lslpls_imm(HOST_TEMPREG,1,HOST_TEMPREG);
3828 emit_jns((int)out-2*4);
3830 emit_writeword(sl,®_cop2d[30]);
3831 emit_writeword(temp,®_cop2d[31]);
3836 emit_writeword(sl,®_cop2d[copr]);
3841 static void c2ls_assemble(int i, const struct regstat *i_regs, int ccadj_)
3846 int memtarget=0,c=0;
3848 enum stub_type type;
3849 int agr=AGEN1+(i&1);
3850 int offset_reg = -1;
3851 int fastio_reg_override = -1;
3852 u_int reglist=get_host_reglist(i_regs->regmap);
3853 u_int copr=(source[i]>>16)&0x1f;
3854 s=get_reg(i_regs->regmap,dops[i].rs1);
3855 tl=get_reg(i_regs->regmap,FTEMP);
3857 assert(dops[i].rs1>0);
3860 if(i_regs->regmap[HOST_CCREG]==CCREG)
3861 reglist&=~(1<<HOST_CCREG);
3864 if (dops[i].opcode==0x3a) { // SWC2
3865 ar=get_reg(i_regs->regmap,agr);
3866 if(ar<0) ar=get_reg_temp(i_regs->regmap);
3871 if(s>=0) c=(i_regs->wasconst>>s)&1;
3872 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3873 if (!offset&&!c&&s>=0) ar=s;
3876 cop2_do_stall_check(0, i, i_regs, reglist);
3878 if (dops[i].opcode==0x3a) { // SWC2
3879 cop2_get_dreg(copr,tl,-1);
3887 emit_jmp(0); // inline_readstub/inline_writestub?
3891 jaddr2 = emit_fastpath_cmp_jump(i, i_regs, ar,
3892 &offset_reg, &fastio_reg_override);
3894 else if (ram_offset && memtarget) {
3895 offset_reg = get_ro_reg(i_regs, 0);
3897 switch (dops[i].opcode) {
3898 case 0x32: { // LWC2
3900 if (fastio_reg_override >= 0)
3901 a = fastio_reg_override;
3902 do_load_word(a, tl, offset_reg);
3905 case 0x3a: { // SWC2
3906 #ifdef DESTRUCTIVE_SHIFT
3907 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3910 if (fastio_reg_override >= 0)
3911 a = fastio_reg_override;
3912 do_store_word(a, 0, tl, offset_reg, 1);
3919 if (fastio_reg_override == HOST_TEMPREG || offset_reg == HOST_TEMPREG)
3920 host_tempreg_release();
3922 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj_,reglist);
3923 if(dops[i].opcode==0x3a) // SWC2
3924 if(!(i_regs->waswritten&(1<<dops[i].rs1)) && !HACK_ENABLED(NDHACK_NO_SMC_CHECK)) {
3925 #if defined(HOST_IMM8)
3926 int ir=get_reg(i_regs->regmap,INVCP);
3928 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3930 emit_cmpmem_indexedsr12_imm(invalid_code,ar,1);
3932 #ifdef INVALIDATE_USE_COND_CALL
3933 emit_callne(invalidate_addr_reg[ar]);
3937 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3940 if (dops[i].opcode==0x32) { // LWC2
3941 host_tempreg_acquire();
3942 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3943 host_tempreg_release();
3947 static void cop2_assemble(int i, const struct regstat *i_regs)
3949 u_int copr = (source[i]>>11) & 0x1f;
3950 signed char temp = get_reg_temp(i_regs->regmap);
3952 if (!HACK_ENABLED(NDHACK_NO_STALLS)) {
3953 u_int reglist = reglist_exclude(get_host_reglist(i_regs->regmap), temp, -1);
3954 if (dops[i].opcode2 == 0 || dops[i].opcode2 == 2) { // MFC2/CFC2
3955 signed char tl = get_reg(i_regs->regmap, dops[i].rt1);
3956 reglist = reglist_exclude(reglist, tl, -1);
3958 cop2_do_stall_check(0, i, i_regs, reglist);
3960 if (dops[i].opcode2==0) { // MFC2
3961 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3962 if(tl>=0&&dops[i].rt1!=0)
3963 cop2_get_dreg(copr,tl,temp);
3965 else if (dops[i].opcode2==4) { // MTC2
3966 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3967 cop2_put_dreg(copr,sl,temp);
3969 else if (dops[i].opcode2==2) // CFC2
3971 signed char tl=get_reg(i_regs->regmap,dops[i].rt1);
3972 if(tl>=0&&dops[i].rt1!=0)
3973 emit_readword(®_cop2c[copr],tl);
3975 else if (dops[i].opcode2==6) // CTC2
3977 signed char sl=get_reg(i_regs->regmap,dops[i].rs1);
3986 emit_signextend16(sl,temp);
3989 c2op_ctc2_31_assemble(sl,temp);
3995 emit_writeword(temp,®_cop2c[copr]);
4000 static void do_unalignedwritestub(int n)
4002 assem_debug("do_unalignedwritestub %x\n",start+stubs[n].a*4);
4004 set_jump_target(stubs[n].addr, out);
4007 struct regstat *i_regs=(struct regstat *)stubs[n].c;
4008 int addr=stubs[n].b;
4009 u_int reglist=stubs[n].e;
4010 signed char *i_regmap=i_regs->regmap;
4011 int temp2=get_reg(i_regmap,FTEMP);
4013 rt=get_reg(i_regmap,dops[i].rs2);
4016 assert(dops[i].opcode==0x2a||dops[i].opcode==0x2e); // SWL/SWR only implemented
4018 reglist&=~(1<<temp2);
4020 // don't bother with it and call write handler
4023 int cc=get_reg(i_regmap,CCREG);
4025 emit_loadreg(CCREG,2);
4026 emit_addimm(cc<0?2:cc,(int)stubs[n].d+1,2);
4027 emit_far_call((dops[i].opcode==0x2a?jump_handle_swl:jump_handle_swr));
4028 emit_addimm(0,-((int)stubs[n].d+1),cc<0?2:cc);
4030 emit_storereg(CCREG,2);
4031 restore_regs(reglist);
4032 emit_jmp(stubs[n].retaddr); // return address
4035 #ifndef multdiv_assemble
4036 void multdiv_assemble(int i,struct regstat *i_regs)
4038 printf("Need multdiv_assemble for this architecture.\n");
4043 static void mov_assemble(int i, const struct regstat *i_regs)
4045 //if(dops[i].opcode2==0x10||dops[i].opcode2==0x12) { // MFHI/MFLO
4046 //if(dops[i].opcode2==0x11||dops[i].opcode2==0x13) { // MTHI/MTLO
4049 tl=get_reg(i_regs->regmap,dops[i].rt1);
4052 sl=get_reg(i_regs->regmap,dops[i].rs1);
4053 if(sl>=0) emit_mov(sl,tl);
4054 else emit_loadreg(dops[i].rs1,tl);
4057 if (dops[i].rs1 == HIREG || dops[i].rs1 == LOREG) // MFHI/MFLO
4058 multdiv_do_stall(i, i_regs);
4061 // call interpreter, exception handler, things that change pc/regs/cycles ...
4062 static void call_c_cpu_handler(int i, const struct regstat *i_regs, int ccadj_, u_int pc, void *func)
4064 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4065 assert(ccreg==HOST_CCREG);
4066 assert(!is_delayslot);
4069 emit_movimm(pc,3); // Get PC
4070 emit_readword(&last_count,2);
4071 emit_writeword(3,&psxRegs.pc);
4072 emit_addimm(HOST_CCREG,ccadj_,HOST_CCREG);
4073 emit_add(2,HOST_CCREG,2);
4074 emit_writeword(2,&psxRegs.cycle);
4075 emit_far_call(func);
4076 emit_far_jump(jump_to_new_pc);
4079 static void syscall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4081 // 'break' tends to be littered around to catch things like
4082 // division by 0 and is almost never executed, so don't emit much code here
4083 void *func = (dops[i].opcode2 == 0x0C)
4084 ? (is_delayslot ? jump_syscall_ds : jump_syscall)
4085 : (is_delayslot ? jump_break_ds : jump_break);
4086 assert(get_reg(i_regs->regmap, CCREG) == HOST_CCREG);
4087 emit_movimm(start + i*4, 2); // pc
4088 emit_addimm(HOST_CCREG, ccadj_ + CLOCK_ADJUST(1), HOST_CCREG);
4089 emit_far_jump(func);
4092 static void hlecall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4094 void *hlefunc = psxNULL;
4095 uint32_t hleCode = source[i] & 0x03ffffff;
4096 if (hleCode < ARRAY_SIZE(psxHLEt))
4097 hlefunc = psxHLEt[hleCode];
4099 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4+4, hlefunc);
4102 static void intcall_assemble(int i, const struct regstat *i_regs, int ccadj_)
4104 call_c_cpu_handler(i, i_regs, ccadj_, start + i*4, execI);
4107 static void speculate_mov(int rs,int rt)
4110 smrv_strong_next|=1<<rt;
4115 static void speculate_mov_weak(int rs,int rt)
4118 smrv_weak_next|=1<<rt;
4123 static void speculate_register_values(int i)
4126 memcpy(smrv,psxRegs.GPR.r,sizeof(smrv));
4127 // gp,sp are likely to stay the same throughout the block
4128 smrv_strong_next=(1<<28)|(1<<29)|(1<<30);
4129 smrv_weak_next=~smrv_strong_next;
4130 //printf(" llr %08x\n", smrv[4]);
4132 smrv_strong=smrv_strong_next;
4133 smrv_weak=smrv_weak_next;
4134 switch(dops[i].itype) {
4136 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4137 else if((smrv_strong>>dops[i].rs2)&1) speculate_mov(dops[i].rs2,dops[i].rt1);
4138 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4139 else if((smrv_weak>>dops[i].rs2)&1) speculate_mov_weak(dops[i].rs2,dops[i].rt1);
4141 smrv_strong_next&=~(1<<dops[i].rt1);
4142 smrv_weak_next&=~(1<<dops[i].rt1);
4146 smrv_strong_next&=~(1<<dops[i].rt1);
4147 smrv_weak_next&=~(1<<dops[i].rt1);
4150 if(dops[i].rt1&&is_const(®s[i],dops[i].rt1)) {
4151 int value,hr=get_reg(regs[i].regmap,dops[i].rt1);
4153 if(get_final_value(hr,i,&value))
4154 smrv[dops[i].rt1]=value;
4155 else smrv[dops[i].rt1]=constmap[i][hr];
4156 smrv_strong_next|=1<<dops[i].rt1;
4160 if ((smrv_strong>>dops[i].rs1)&1) speculate_mov(dops[i].rs1,dops[i].rt1);
4161 else if((smrv_weak>>dops[i].rs1)&1) speculate_mov_weak(dops[i].rs1,dops[i].rt1);
4165 if(start<0x2000&&(dops[i].rt1==26||(smrv[dops[i].rt1]>>24)==0xa0)) {
4166 // special case for BIOS
4167 smrv[dops[i].rt1]=0xa0000000;
4168 smrv_strong_next|=1<<dops[i].rt1;
4175 smrv_strong_next&=~(1<<dops[i].rt1);
4176 smrv_weak_next&=~(1<<dops[i].rt1);
4180 if(dops[i].opcode2==0||dops[i].opcode2==2) { // MFC/CFC
4181 smrv_strong_next&=~(1<<dops[i].rt1);
4182 smrv_weak_next&=~(1<<dops[i].rt1);
4186 if (dops[i].opcode==0x32) { // LWC2
4187 smrv_strong_next&=~(1<<dops[i].rt1);
4188 smrv_weak_next&=~(1<<dops[i].rt1);
4194 printf("x %08x %08x %d %d c %08x %08x\n",smrv[r],start+i*4,
4195 ((smrv_strong>>r)&1),(smrv_weak>>r)&1,regs[i].isconst,regs[i].wasconst);
4199 static void ujump_assemble(int i, const struct regstat *i_regs);
4200 static void rjump_assemble(int i, const struct regstat *i_regs);
4201 static void cjump_assemble(int i, const struct regstat *i_regs);
4202 static void sjump_assemble(int i, const struct regstat *i_regs);
4204 static int assemble(int i, const struct regstat *i_regs, int ccadj_)
4207 switch (dops[i].itype) {
4209 alu_assemble(i, i_regs);
4212 imm16_assemble(i, i_regs);
4215 shift_assemble(i, i_regs);
4218 shiftimm_assemble(i, i_regs);
4221 load_assemble(i, i_regs, ccadj_);
4224 loadlr_assemble(i, i_regs, ccadj_);
4227 store_assemble(i, i_regs, ccadj_);
4230 storelr_assemble(i, i_regs, ccadj_);
4233 cop0_assemble(i, i_regs, ccadj_);
4236 cop1_assemble(i, i_regs);
4239 c1ls_assemble(i, i_regs);
4242 cop2_assemble(i, i_regs);
4245 c2ls_assemble(i, i_regs, ccadj_);
4248 c2op_assemble(i, i_regs);
4251 multdiv_assemble(i, i_regs);
4252 multdiv_prepare_stall(i, i_regs, ccadj_);
4255 mov_assemble(i, i_regs);
4258 syscall_assemble(i, i_regs, ccadj_);
4261 hlecall_assemble(i, i_regs, ccadj_);
4264 intcall_assemble(i, i_regs, ccadj_);
4267 ujump_assemble(i, i_regs);
4271 rjump_assemble(i, i_regs);
4275 cjump_assemble(i, i_regs);
4279 sjump_assemble(i, i_regs);
4285 // not handled, just skip
4293 static void ds_assemble(int i, const struct regstat *i_regs)
4295 speculate_register_values(i);
4297 switch (dops[i].itype) {
4305 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4308 assemble(i, i_regs, ccadj[i]);
4313 // Is the branch target a valid internal jump?
4314 static int internal_branch(int addr)
4316 if(addr&1) return 0; // Indirect (register) jump
4317 if(addr>=start && addr<start+slen*4-4)
4324 static void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t u)
4327 for(hr=0;hr<HOST_REGS;hr++) {
4328 if(hr!=EXCLUDE_REG) {
4329 if(pre[hr]!=entry[hr]) {
4332 if(get_reg(entry,pre[hr])<0) {
4334 if(!((u>>pre[hr])&1))
4335 emit_storereg(pre[hr],hr);
4342 // Move from one register to another (no writeback)
4343 for(hr=0;hr<HOST_REGS;hr++) {
4344 if(hr!=EXCLUDE_REG) {
4345 if(pre[hr]!=entry[hr]) {
4346 if(pre[hr]>=0&&pre[hr]<TEMPREG) {
4348 if((nr=get_reg(entry,pre[hr]))>=0) {
4357 // Load the specified registers
4358 // This only loads the registers given as arguments because
4359 // we don't want to load things that will be overwritten
4360 static inline void load_reg(signed char entry[], signed char regmap[], int rs)
4362 int hr = get_reg(regmap, rs);
4363 if (hr >= 0 && entry[hr] != regmap[hr])
4364 emit_loadreg(regmap[hr], hr);
4367 static void load_regs(signed char entry[], signed char regmap[], int rs1, int rs2)
4369 load_reg(entry, regmap, rs1);
4371 load_reg(entry, regmap, rs2);
4374 // Load registers prior to the start of a loop
4375 // so that they are not loaded within the loop
4376 static void loop_preload(signed char pre[],signed char entry[])
4379 for (hr = 0; hr < HOST_REGS; hr++) {
4381 if (r >= 0 && pre[hr] != r && get_reg(pre, r) < 0) {
4382 assem_debug("loop preload:\n");
4384 emit_loadreg(r, hr);
4389 // Generate address for load/store instruction
4390 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4391 static void address_generation(int i, const struct regstat *i_regs, signed char entry[])
4393 if (dops[i].is_load || dops[i].is_store) {
4395 int agr=AGEN1+(i&1);
4396 if(dops[i].itype==LOAD) {
4397 ra=get_reg(i_regs->regmap,dops[i].rt1);
4398 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4401 if(dops[i].itype==LOADLR) {
4402 ra=get_reg(i_regs->regmap,FTEMP);
4404 if(dops[i].itype==STORE||dops[i].itype==STORELR) {
4405 ra=get_reg(i_regs->regmap,agr);
4406 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4408 if(dops[i].itype==C2LS) {
4409 if ((dops[i].opcode&0x3b)==0x31||(dops[i].opcode&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4410 ra=get_reg(i_regs->regmap,FTEMP);
4411 else { // SWC1/SDC1/SWC2/SDC2
4412 ra=get_reg(i_regs->regmap,agr);
4413 if(ra<0) ra=get_reg_temp(i_regs->regmap);
4416 int rs=get_reg(i_regs->regmap,dops[i].rs1);
4419 int c=(i_regs->wasconst>>rs)&1;
4420 if(dops[i].rs1==0) {
4421 // Using r0 as a base address
4422 if(!entry||entry[ra]!=agr) {
4423 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4424 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4425 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4426 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4428 emit_movimm(offset,ra);
4430 } // else did it in the previous cycle
4433 if(!entry||entry[ra]!=dops[i].rs1)
4434 emit_loadreg(dops[i].rs1,ra);
4435 //if(!entry||entry[ra]!=dops[i].rs1)
4436 // printf("poor load scheduling!\n");
4439 if(dops[i].rs1!=dops[i].rt1||dops[i].itype!=LOAD) {
4440 if(!entry||entry[ra]!=agr) {
4441 if (dops[i].opcode==0x22||dops[i].opcode==0x26) {
4442 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4443 }else if (dops[i].opcode==0x1a||dops[i].opcode==0x1b) {
4444 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4446 emit_movimm(constmap[i][rs]+offset,ra);
4447 regs[i].loadedconst|=1<<ra;
4449 } // else did it in the previous cycle
4450 } // else load_consts already did it
4452 if(offset&&!c&&dops[i].rs1) {
4454 emit_addimm(rs,offset,ra);
4456 emit_addimm(ra,offset,ra);
4461 // Preload constants for next instruction
4462 if (dops[i+1].is_load || dops[i+1].is_store) {
4465 agr=AGEN1+((i+1)&1);
4466 ra=get_reg(i_regs->regmap,agr);
4468 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
4469 int offset=imm[i+1];
4470 int c=(regs[i+1].wasconst>>rs)&1;
4471 if(c&&(dops[i+1].rs1!=dops[i+1].rt1||dops[i+1].itype!=LOAD)) {
4472 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4473 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4474 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4475 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4477 emit_movimm(constmap[i+1][rs]+offset,ra);
4478 regs[i+1].loadedconst|=1<<ra;
4481 else if(dops[i+1].rs1==0) {
4482 // Using r0 as a base address
4483 if (dops[i+1].opcode==0x22||dops[i+1].opcode==0x26) {
4484 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4485 }else if (dops[i+1].opcode==0x1a||dops[i+1].opcode==0x1b) {
4486 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4488 emit_movimm(offset,ra);
4495 static int get_final_value(int hr, int i, int *value)
4497 int reg=regs[i].regmap[hr];
4499 if(regs[i+1].regmap[hr]!=reg) break;
4500 if(!((regs[i+1].isconst>>hr)&1)) break;
4501 if(dops[i+1].bt) break;
4505 if (dops[i].is_jump) {
4506 *value=constmap[i][hr];
4510 if (dops[i+1].is_jump) {
4511 // Load in delay slot, out-of-order execution
4512 if(dops[i+2].itype==LOAD&&dops[i+2].rs1==reg&&dops[i+2].rt1==reg&&((regs[i+1].wasconst>>hr)&1))
4514 // Precompute load address
4515 *value=constmap[i][hr]+imm[i+2];
4519 if(dops[i+1].itype==LOAD&&dops[i+1].rs1==reg&&dops[i+1].rt1==reg)
4521 // Precompute load address
4522 *value=constmap[i][hr]+imm[i+1];
4523 //printf("c=%x imm=%lx\n",(long)constmap[i][hr],imm[i+1]);
4528 *value=constmap[i][hr];
4529 //printf("c=%lx\n",(long)constmap[i][hr]);
4530 if(i==slen-1) return 1;
4532 return !((unneeded_reg[i+1]>>reg)&1);
4535 // Load registers with known constants
4536 static void load_consts(signed char pre[],signed char regmap[],int i)
4539 // propagate loaded constant flags
4540 if(i==0||dops[i].bt)
4541 regs[i].loadedconst=0;
4543 for(hr=0;hr<HOST_REGS;hr++) {
4544 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4545 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4547 regs[i].loadedconst|=1<<hr;
4552 for(hr=0;hr<HOST_REGS;hr++) {
4553 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4554 //if(entry[hr]!=regmap[hr]) {
4555 if(!((regs[i].loadedconst>>hr)&1)) {
4556 assert(regmap[hr]<64);
4557 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4558 int value,similar=0;
4559 if(get_final_value(hr,i,&value)) {
4560 // see if some other register has similar value
4561 for(hr2=0;hr2<HOST_REGS;hr2++) {
4562 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4563 if(is_similar_value(value,constmap[i][hr2])) {
4571 if(get_final_value(hr2,i,&value2)) // is this needed?
4572 emit_movimm_from(value2,hr2,value,hr);
4574 emit_movimm(value,hr);
4580 emit_movimm(value,hr);
4583 regs[i].loadedconst|=1<<hr;
4590 static void load_all_consts(const signed char regmap[], u_int dirty, int i)
4594 for(hr=0;hr<HOST_REGS;hr++) {
4595 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4596 assert(regmap[hr] < 64);
4597 if(((regs[i].isconst>>hr)&1)&®map[hr]>0) {
4598 int value=constmap[i][hr];
4603 emit_movimm(value,hr);
4610 // Write out all dirty registers (except cycle count)
4611 static void wb_dirtys(const signed char i_regmap[], uint64_t i_dirty)
4614 for(hr=0;hr<HOST_REGS;hr++) {
4615 if(hr!=EXCLUDE_REG) {
4616 if(i_regmap[hr]>0) {
4617 if(i_regmap[hr]!=CCREG) {
4618 if((i_dirty>>hr)&1) {
4619 assert(i_regmap[hr]<64);
4620 emit_storereg(i_regmap[hr],hr);
4628 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4629 // This writes the registers not written by store_regs_bt
4630 static void wb_needed_dirtys(const signed char i_regmap[], uint64_t i_dirty, int addr)
4633 int t=(addr-start)>>2;
4634 for(hr=0;hr<HOST_REGS;hr++) {
4635 if(hr!=EXCLUDE_REG) {
4636 if(i_regmap[hr]>0) {
4637 if(i_regmap[hr]!=CCREG) {
4638 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1)) {
4639 if((i_dirty>>hr)&1) {
4640 assert(i_regmap[hr]<64);
4641 emit_storereg(i_regmap[hr],hr);
4650 // Load all registers (except cycle count)
4651 static void load_all_regs(const signed char i_regmap[])
4654 for(hr=0;hr<HOST_REGS;hr++) {
4655 if(hr!=EXCLUDE_REG) {
4656 if(i_regmap[hr]==0) {
4660 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4662 emit_loadreg(i_regmap[hr],hr);
4668 // Load all current registers also needed by next instruction
4669 static void load_needed_regs(const signed char i_regmap[], const signed char next_regmap[])
4672 for(hr=0;hr<HOST_REGS;hr++) {
4673 if(hr!=EXCLUDE_REG) {
4674 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4675 if(i_regmap[hr]==0) {
4679 if(i_regmap[hr]>0 && i_regmap[hr]<TEMPREG && i_regmap[hr]!=CCREG)
4681 emit_loadreg(i_regmap[hr],hr);
4688 // Load all regs, storing cycle count if necessary
4689 static void load_regs_entry(int t)
4692 if(dops[t].is_ds) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4693 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t],HOST_CCREG);
4694 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4695 emit_storereg(CCREG,HOST_CCREG);
4698 for(hr=0;hr<HOST_REGS;hr++) {
4699 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4700 if(regs[t].regmap_entry[hr]==0) {
4703 else if(regs[t].regmap_entry[hr]!=CCREG)
4705 emit_loadreg(regs[t].regmap_entry[hr],hr);
4711 // Store dirty registers prior to branch
4712 static void store_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4714 if(internal_branch(addr))
4716 int t=(addr-start)>>2;
4718 for(hr=0;hr<HOST_REGS;hr++) {
4719 if(hr!=EXCLUDE_REG) {
4720 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4721 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1)) {
4722 if((i_dirty>>hr)&1) {
4723 assert(i_regmap[hr]<64);
4724 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4725 emit_storereg(i_regmap[hr],hr);
4734 // Branch out of this block, write out all dirty regs
4735 wb_dirtys(i_regmap,i_dirty);
4739 // Load all needed registers for branch target
4740 static void load_regs_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4742 //if(addr>=start && addr<(start+slen*4))
4743 if(internal_branch(addr))
4745 int t=(addr-start)>>2;
4747 // Store the cycle count before loading something else
4748 if(i_regmap[HOST_CCREG]!=CCREG) {
4749 assert(i_regmap[HOST_CCREG]==-1);
4751 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4752 emit_storereg(CCREG,HOST_CCREG);
4755 for(hr=0;hr<HOST_REGS;hr++) {
4756 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4757 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4758 if(regs[t].regmap_entry[hr]==0) {
4761 else if(regs[t].regmap_entry[hr]!=CCREG)
4763 emit_loadreg(regs[t].regmap_entry[hr],hr);
4771 static int match_bt(signed char i_regmap[],uint64_t i_dirty,int addr)
4773 if(addr>=start && addr<start+slen*4-4)
4775 int t=(addr-start)>>2;
4777 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4778 for(hr=0;hr<HOST_REGS;hr++)
4782 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4784 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4791 if(i_regmap[hr]<TEMPREG)
4793 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4796 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4802 else // Same register but is it 32-bit or dirty?
4805 if(!((regs[t].dirty>>hr)&1))
4809 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4811 //printf("%x: dirty no match\n",addr);
4819 // Delay slots are not valid branch targets
4820 //if(t>0&&(dops[t-1].is_jump) return 0;
4821 // Delay slots require additional processing, so do not match
4822 if(dops[t].is_ds) return 0;
4827 for(hr=0;hr<HOST_REGS;hr++)
4833 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4848 static void drc_dbg_emit_do_cmp(int i, int ccadj_)
4850 extern void do_insn_cmp();
4852 u_int hr, reglist = get_host_reglist(regs[i].regmap);
4854 assem_debug("//do_insn_cmp %08x\n", start+i*4);
4856 // write out changed consts to match the interpreter
4857 if (i > 0 && !dops[i].bt) {
4858 for (hr = 0; hr < HOST_REGS; hr++) {
4859 int reg = regs[i].regmap_entry[hr]; // regs[i-1].regmap[hr];
4860 if (hr == EXCLUDE_REG || reg < 0)
4862 if (!((regs[i-1].isconst >> hr) & 1))
4864 if (i > 1 && reg == regs[i-2].regmap[hr] && constmap[i-1][hr] == constmap[i-2][hr])
4866 emit_movimm(constmap[i-1][hr],0);
4867 emit_storereg(reg, 0);
4870 emit_movimm(start+i*4,0);
4871 emit_writeword(0,&pcaddr);
4872 int cc = get_reg(regs[i].regmap_entry, CCREG);
4874 emit_loadreg(CCREG, cc = 0);
4875 emit_addimm(cc, ccadj_, 0);
4876 emit_writeword(0, &psxRegs.cycle);
4877 emit_far_call(do_insn_cmp);
4878 //emit_readword(&cycle,0);
4879 //emit_addimm(0,2,0);
4880 //emit_writeword(0,&cycle);
4882 restore_regs(reglist);
4883 assem_debug("\\\\do_insn_cmp\n");
4886 #define drc_dbg_emit_do_cmp(x,y)
4889 // Used when a branch jumps into the delay slot of another branch
4890 static void ds_assemble_entry(int i)
4892 int t = (ba[i] - start) >> 2;
4893 int ccadj_ = -CLOCK_ADJUST(1);
4895 instr_addr[t] = out;
4896 assem_debug("Assemble delay slot at %x\n",ba[i]);
4897 assem_debug("<->\n");
4898 drc_dbg_emit_do_cmp(t, ccadj_);
4899 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4900 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty);
4901 load_regs(regs[t].regmap_entry,regs[t].regmap,dops[t].rs1,dops[t].rs2);
4902 address_generation(t,®s[t],regs[t].regmap_entry);
4903 if (ram_offset && (dops[t].is_load || dops[t].is_store))
4904 load_reg(regs[t].regmap_entry,regs[t].regmap,ROREG);
4905 if (dops[t].is_store)
4906 load_reg(regs[t].regmap_entry,regs[t].regmap,INVCP);
4908 switch (dops[t].itype) {
4916 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4919 assemble(t, ®s[t], ccadj_);
4921 store_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4922 load_regs_bt(regs[t].regmap,regs[t].dirty,ba[i]+4);
4923 if(internal_branch(ba[i]+4))
4924 assem_debug("branch: internal\n");
4926 assem_debug("branch: external\n");
4927 assert(internal_branch(ba[i]+4));
4928 add_to_linker(out,ba[i]+4,internal_branch(ba[i]+4));
4932 // Load 2 immediates optimizing for small code size
4933 static void emit_mov2imm_compact(int imm1,u_int rt1,int imm2,u_int rt2)
4935 emit_movimm(imm1,rt1);
4936 emit_movimm_from(imm1,rt1,imm2,rt2);
4939 static void do_cc(int i, const signed char i_regmap[], int *adj,
4940 int addr, int taken, int invert)
4942 int count, count_plus2;
4946 if(dops[i].itype==RJUMP)
4950 //if(ba[i]>=start && ba[i]<(start+slen*4))
4951 if(internal_branch(ba[i]))
4954 if(dops[t].is_ds) *adj=-CLOCK_ADJUST(1); // Branch into delay slot adds an extra cycle
4962 count_plus2 = count + CLOCK_ADJUST(2);
4963 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4965 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4967 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4968 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4972 else if(*adj==0||invert) {
4973 int cycles = count_plus2;
4978 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4979 cycles=*adj+count+2-*adj;
4982 emit_addimm_and_set_flags(cycles, HOST_CCREG);
4988 emit_cmpimm(HOST_CCREG, -count_plus2);
4992 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:count_plus2,i,addr,taken,0);
4995 static void do_ccstub(int n)
4998 assem_debug("do_ccstub %x\n",start+(u_int)stubs[n].b*4);
4999 set_jump_target(stubs[n].addr, out);
5001 if(stubs[n].d==NULLDS) {
5002 // Delay slot instruction is nullified ("likely" branch)
5003 wb_dirtys(regs[i].regmap,regs[i].dirty);
5005 else if(stubs[n].d!=TAKEN) {
5006 wb_dirtys(branch_regs[i].regmap,branch_regs[i].dirty);
5009 if(internal_branch(ba[i]))
5010 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5014 // Save PC as return address
5015 emit_movimm(stubs[n].c,EAX);
5016 emit_writeword(EAX,&pcaddr);
5020 // Return address depends on which way the branch goes
5021 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
5023 int s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5024 int s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5030 else if(dops[i].rs2==0)
5035 #ifdef DESTRUCTIVE_WRITEBACK
5037 if((branch_regs[i].dirty>>s1l)&&1)
5038 emit_loadreg(dops[i].rs1,s1l);
5041 if((branch_regs[i].dirty>>s1l)&1)
5042 emit_loadreg(dops[i].rs2,s1l);
5045 if((branch_regs[i].dirty>>s2l)&1)
5046 emit_loadreg(dops[i].rs2,s2l);
5049 int addr=-1,alt=-1,ntaddr=-1;
5052 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5053 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5054 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5062 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5063 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5064 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5070 if((dops[i].opcode&0x2E)==6) // BLEZ/BGTZ needs another register
5074 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5075 branch_regs[i].regmap[hr]!=dops[i].rs1 &&
5076 branch_regs[i].regmap[hr]!=dops[i].rs2 )
5082 assert(hr<HOST_REGS);
5084 if((dops[i].opcode&0x2f)==4) // BEQ
5086 #ifdef HAVE_CMOV_IMM
5087 if(s2l>=0) emit_cmp(s1l,s2l);
5088 else emit_test(s1l,s1l);
5089 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5091 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5092 if(s2l>=0) emit_cmp(s1l,s2l);
5093 else emit_test(s1l,s1l);
5094 emit_cmovne_reg(alt,addr);
5097 if((dops[i].opcode&0x2f)==5) // BNE
5099 #ifdef HAVE_CMOV_IMM
5100 if(s2l>=0) emit_cmp(s1l,s2l);
5101 else emit_test(s1l,s1l);
5102 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5104 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5105 if(s2l>=0) emit_cmp(s1l,s2l);
5106 else emit_test(s1l,s1l);
5107 emit_cmovne_reg(alt,addr);
5110 if((dops[i].opcode&0x2f)==6) // BLEZ
5112 //emit_movimm(ba[i],alt);
5113 //emit_movimm(start+i*4+8,addr);
5114 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5116 emit_cmovl_reg(alt,addr);
5118 if((dops[i].opcode&0x2f)==7) // BGTZ
5120 //emit_movimm(ba[i],addr);
5121 //emit_movimm(start+i*4+8,ntaddr);
5122 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5124 emit_cmovl_reg(ntaddr,addr);
5126 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==0) // BLTZ
5128 //emit_movimm(ba[i],alt);
5129 //emit_movimm(start+i*4+8,addr);
5130 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5132 emit_cmovs_reg(alt,addr);
5134 if((dops[i].opcode==1)&&(dops[i].opcode2&0x2D)==1) // BGEZ
5136 //emit_movimm(ba[i],addr);
5137 //emit_movimm(start+i*4+8,alt);
5138 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5140 emit_cmovs_reg(alt,addr);
5142 if(dops[i].opcode==0x11 && dops[i].opcode2==0x08 ) {
5143 if(source[i]&0x10000) // BC1T
5145 //emit_movimm(ba[i],alt);
5146 //emit_movimm(start+i*4+8,addr);
5147 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5148 emit_testimm(s1l,0x800000);
5149 emit_cmovne_reg(alt,addr);
5153 //emit_movimm(ba[i],addr);
5154 //emit_movimm(start+i*4+8,alt);
5155 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5156 emit_testimm(s1l,0x800000);
5157 emit_cmovne_reg(alt,addr);
5160 emit_writeword(addr,&pcaddr);
5163 if(dops[i].itype==RJUMP)
5165 int r=get_reg(branch_regs[i].regmap,dops[i].rs1);
5166 if (ds_writes_rjump_rs(i)) {
5167 r=get_reg(branch_regs[i].regmap,RTEMP);
5169 emit_writeword(r,&pcaddr);
5171 else {SysPrintf("Unknown branch type in do_ccstub\n");abort();}
5173 // Update cycle count
5174 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5175 if(stubs[n].a) emit_addimm(HOST_CCREG,(int)stubs[n].a,HOST_CCREG);
5176 emit_far_call(cc_interrupt);
5177 if(stubs[n].a) emit_addimm(HOST_CCREG,-(int)stubs[n].a,HOST_CCREG);
5178 if(stubs[n].d==TAKEN) {
5179 if(internal_branch(ba[i]))
5180 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5181 else if(dops[i].itype==RJUMP) {
5182 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5183 emit_readword(&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5185 emit_loadreg(dops[i].rs1,get_reg(branch_regs[i].regmap,dops[i].rs1));
5187 }else if(stubs[n].d==NOTTAKEN) {
5188 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5189 else load_all_regs(branch_regs[i].regmap);
5190 }else if(stubs[n].d==NULLDS) {
5191 // Delay slot instruction is nullified ("likely" branch)
5192 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5193 else load_all_regs(regs[i].regmap);
5195 load_all_regs(branch_regs[i].regmap);
5197 if (stubs[n].retaddr)
5198 emit_jmp(stubs[n].retaddr);
5200 do_jump_vaddr(stubs[n].e);
5203 static void add_to_linker(void *addr, u_int target, int is_internal)
5205 assert(linkcount < ARRAY_SIZE(link_addr));
5206 link_addr[linkcount].addr = addr;
5207 link_addr[linkcount].target = target;
5208 link_addr[linkcount].internal = is_internal;
5212 static void ujump_assemble_write_ra(int i)
5215 unsigned int return_address;
5216 rt=get_reg(branch_regs[i].regmap,31);
5217 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5219 return_address=start+i*4+8;
5222 if(internal_branch(return_address)&&dops[i+1].rt1!=31) {
5223 int temp=-1; // note: must be ds-safe
5227 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5228 else emit_movimm(return_address,rt);
5236 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5239 emit_movimm(return_address,rt); // PC into link register
5241 emit_prefetch(hash_table_get(return_address));
5247 static void ujump_assemble(int i, const struct regstat *i_regs)
5250 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5251 address_generation(i+1,i_regs,regs[i].regmap_entry);
5253 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5254 if(dops[i].rt1==31&&temp>=0)
5256 signed char *i_regmap=i_regs->regmap;
5257 int return_address=start+i*4+8;
5258 if(get_reg(branch_regs[i].regmap,31)>0)
5259 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5262 if(dops[i].rt1==31&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5263 ujump_assemble_write_ra(i); // writeback ra for DS
5266 ds_assemble(i+1,i_regs);
5267 uint64_t bc_unneeded=branch_regs[i].u;
5268 bc_unneeded|=1|(1LL<<dops[i].rt1);
5269 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5270 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5271 if(!ra_done&&dops[i].rt1==31)
5272 ujump_assemble_write_ra(i);
5274 cc=get_reg(branch_regs[i].regmap,CCREG);
5275 assert(cc==HOST_CCREG);
5276 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5278 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5280 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5281 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5282 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5283 if(internal_branch(ba[i]))
5284 assem_debug("branch: internal\n");
5286 assem_debug("branch: external\n");
5287 if (internal_branch(ba[i]) && dops[(ba[i]-start)>>2].is_ds) {
5288 ds_assemble_entry(i);
5291 add_to_linker(out,ba[i],internal_branch(ba[i]));
5296 static void rjump_assemble_write_ra(int i)
5298 int rt,return_address;
5299 assert(dops[i+1].rt1!=dops[i].rt1);
5300 assert(dops[i+1].rt2!=dops[i].rt1);
5301 rt=get_reg(branch_regs[i].regmap,dops[i].rt1);
5302 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5304 return_address=start+i*4+8;
5308 if(i_regmap[temp]!=PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5311 emit_movimm(return_address,rt); // PC into link register
5313 emit_prefetch(hash_table_get(return_address));
5317 static void rjump_assemble(int i, const struct regstat *i_regs)
5322 rs=get_reg(branch_regs[i].regmap,dops[i].rs1);
5324 if (ds_writes_rjump_rs(i)) {
5325 // Delay slot abuse, make a copy of the branch address register
5326 temp=get_reg(branch_regs[i].regmap,RTEMP);
5328 assert(regs[i].regmap[temp]==RTEMP);
5332 address_generation(i+1,i_regs,regs[i].regmap_entry);
5336 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5337 signed char *i_regmap=i_regs->regmap;
5338 int return_address=start+i*4+8;
5339 if(i_regmap[temp]==PTEMP) emit_movimm((uintptr_t)hash_table_get(return_address),temp);
5344 if(dops[i].rs1==31) {
5345 int rh=get_reg(regs[i].regmap,RHASH);
5346 if(rh>=0) do_preload_rhash(rh);
5349 if(dops[i].rt1!=0&&(dops[i].rt1==dops[i+1].rs1||dops[i].rt1==dops[i+1].rs2)) {
5350 rjump_assemble_write_ra(i);
5353 ds_assemble(i+1,i_regs);
5354 uint64_t bc_unneeded=branch_regs[i].u;
5355 bc_unneeded|=1|(1LL<<dops[i].rt1);
5356 bc_unneeded&=~(1LL<<dops[i].rs1);
5357 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5358 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,CCREG);
5359 if(!ra_done&&dops[i].rt1!=0)
5360 rjump_assemble_write_ra(i);
5361 cc=get_reg(branch_regs[i].regmap,CCREG);
5362 assert(cc==HOST_CCREG);
5365 int rh=get_reg(branch_regs[i].regmap,RHASH);
5366 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5367 if(dops[i].rs1==31) {
5368 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5369 do_preload_rhtbl(ht);
5373 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5374 #ifdef DESTRUCTIVE_WRITEBACK
5375 if((branch_regs[i].dirty>>rs)&1) {
5376 if(dops[i].rs1!=dops[i+1].rt1&&dops[i].rs1!=dops[i+1].rt2) {
5377 emit_loadreg(dops[i].rs1,rs);
5382 if(dops[i].rt1==31&&temp>=0) emit_prefetchreg(temp);
5385 if(dops[i].rs1==31) {
5386 do_miniht_load(ht,rh);
5389 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5390 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5392 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5393 add_stub(CC_STUB,out,NULL,0,i,-1,TAKEN,rs);
5394 if(dops[i+1].itype==COP0 && dops[i+1].opcode2==0x10)
5395 // special case for RFE
5399 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,-1);
5401 if(dops[i].rs1==31) {
5402 do_miniht_jump(rs,rh,ht);
5409 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5410 if(dops[i].rt1!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5414 static void cjump_assemble(int i, const struct regstat *i_regs)
5416 const signed char *i_regmap = i_regs->regmap;
5419 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5420 assem_debug("match=%d\n",match);
5422 int unconditional=0,nop=0;
5424 int internal=internal_branch(ba[i]);
5425 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5426 if(!match) invert=1;
5427 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5428 if(i>(ba[i]-start)>>2) invert=1;
5431 invert=1; // because of near cond. branches
5435 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5436 s2l=get_reg(branch_regs[i].regmap,dops[i].rs2);
5439 s1l=get_reg(i_regmap,dops[i].rs1);
5440 s2l=get_reg(i_regmap,dops[i].rs2);
5442 if(dops[i].rs1==0&&dops[i].rs2==0)
5444 if(dops[i].opcode&1) nop=1;
5445 else unconditional=1;
5446 //assert(dops[i].opcode!=5);
5447 //assert(dops[i].opcode!=7);
5448 //assert(dops[i].opcode!=0x15);
5449 //assert(dops[i].opcode!=0x17);
5451 else if(dops[i].rs1==0)
5456 else if(dops[i].rs2==0)
5462 // Out of order execution (delay slot first)
5464 address_generation(i+1,i_regs,regs[i].regmap_entry);
5465 ds_assemble(i+1,i_regs);
5467 uint64_t bc_unneeded=branch_regs[i].u;
5468 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5470 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5471 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs2);
5472 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5473 cc=get_reg(branch_regs[i].regmap,CCREG);
5474 assert(cc==HOST_CCREG);
5476 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5477 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5478 //assem_debug("cycle count (adj)\n");
5480 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5481 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5482 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5483 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5485 assem_debug("branch: internal\n");
5487 assem_debug("branch: external\n");
5488 if (internal && dops[(ba[i]-start)>>2].is_ds) {
5489 ds_assemble_entry(i);
5492 add_to_linker(out,ba[i],internal);
5495 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5496 if(((u_int)out)&7) emit_addnop(0);
5501 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5504 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5507 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5508 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5509 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5511 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5513 if(dops[i].opcode==4) // BEQ
5515 if(s2l>=0) emit_cmp(s1l,s2l);
5516 else emit_test(s1l,s1l);
5521 add_to_linker(out,ba[i],internal);
5525 if(dops[i].opcode==5) // BNE
5527 if(s2l>=0) emit_cmp(s1l,s2l);
5528 else emit_test(s1l,s1l);
5533 add_to_linker(out,ba[i],internal);
5537 if(dops[i].opcode==6) // BLEZ
5544 add_to_linker(out,ba[i],internal);
5548 if(dops[i].opcode==7) // BGTZ
5555 add_to_linker(out,ba[i],internal);
5560 if(taken) set_jump_target(taken, out);
5561 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5562 if (match && (!internal || !dops[(ba[i]-start)>>2].is_ds)) {
5564 emit_addimm(cc,-adj,cc);
5565 add_to_linker(out,ba[i],internal);
5568 add_to_linker(out,ba[i],internal*2);
5574 if(adj) emit_addimm(cc,-adj,cc);
5575 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5576 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5578 assem_debug("branch: internal\n");
5580 assem_debug("branch: external\n");
5581 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5582 ds_assemble_entry(i);
5585 add_to_linker(out,ba[i],internal);
5589 set_jump_target(nottaken, out);
5592 if(nottaken1) set_jump_target(nottaken1, out);
5594 if(!invert) emit_addimm(cc,adj,cc);
5596 } // (!unconditional)
5600 // In-order execution (branch first)
5601 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5602 if(!unconditional&&!nop) {
5603 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5605 if((dops[i].opcode&0x2f)==4) // BEQ
5607 if(s2l>=0) emit_cmp(s1l,s2l);
5608 else emit_test(s1l,s1l);
5612 if((dops[i].opcode&0x2f)==5) // BNE
5614 if(s2l>=0) emit_cmp(s1l,s2l);
5615 else emit_test(s1l,s1l);
5619 if((dops[i].opcode&0x2f)==6) // BLEZ
5625 if((dops[i].opcode&0x2f)==7) // BGTZ
5631 } // if(!unconditional)
5633 uint64_t ds_unneeded=branch_regs[i].u;
5634 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5638 if(taken) set_jump_target(taken, out);
5639 assem_debug("1:\n");
5640 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5642 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5643 address_generation(i+1,&branch_regs[i],0);
5645 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5646 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5647 ds_assemble(i+1,&branch_regs[i]);
5648 cc=get_reg(branch_regs[i].regmap,CCREG);
5650 emit_loadreg(CCREG,cc=HOST_CCREG);
5651 // CHECK: Is the following instruction (fall thru) allocated ok?
5653 assert(cc==HOST_CCREG);
5654 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5655 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5656 assem_debug("cycle count (adj)\n");
5657 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5658 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5660 assem_debug("branch: internal\n");
5662 assem_debug("branch: external\n");
5663 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5664 ds_assemble_entry(i);
5667 add_to_linker(out,ba[i],internal);
5672 if(!unconditional) {
5673 if(nottaken1) set_jump_target(nottaken1, out);
5674 set_jump_target(nottaken, out);
5675 assem_debug("2:\n");
5676 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5678 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5679 address_generation(i+1,&branch_regs[i],0);
5681 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5682 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5683 ds_assemble(i+1,&branch_regs[i]);
5684 cc=get_reg(branch_regs[i].regmap,CCREG);
5686 // Cycle count isn't in a register, temporarily load it then write it out
5687 emit_loadreg(CCREG,HOST_CCREG);
5688 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5691 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5692 emit_storereg(CCREG,HOST_CCREG);
5695 cc=get_reg(i_regmap,CCREG);
5696 assert(cc==HOST_CCREG);
5697 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5700 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5706 static void sjump_assemble(int i, const struct regstat *i_regs)
5708 const signed char *i_regmap = i_regs->regmap;
5711 match=match_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5712 assem_debug("smatch=%d ooo=%d\n", match, dops[i].ooo);
5714 int unconditional=0,nevertaken=0;
5716 int internal=internal_branch(ba[i]);
5717 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5718 if(!match) invert=1;
5719 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5720 if(i>(ba[i]-start)>>2) invert=1;
5723 invert=1; // because of near cond. branches
5726 //if(dops[i].opcode2>=0x10) return; // FIXME (BxxZAL)
5727 //assert(dops[i].opcode2<0x10||dops[i].rs1==0); // FIXME (BxxZAL)
5730 s1l=get_reg(branch_regs[i].regmap,dops[i].rs1);
5733 s1l=get_reg(i_regmap,dops[i].rs1);
5737 if(dops[i].opcode2&1) unconditional=1;
5739 // These are never taken (r0 is never less than zero)
5740 //assert(dops[i].opcode2!=0);
5741 //assert(dops[i].opcode2!=2);
5742 //assert(dops[i].opcode2!=0x10);
5743 //assert(dops[i].opcode2!=0x12);
5747 // Out of order execution (delay slot first)
5749 address_generation(i+1,i_regs,regs[i].regmap_entry);
5750 ds_assemble(i+1,i_regs);
5752 uint64_t bc_unneeded=branch_regs[i].u;
5753 bc_unneeded&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
5755 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,bc_unneeded);
5756 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i].rs1,dops[i].rs1);
5757 load_reg(regs[i].regmap,branch_regs[i].regmap,CCREG);
5758 if(dops[i].rt1==31) {
5759 int rt,return_address;
5760 rt=get_reg(branch_regs[i].regmap,31);
5761 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5763 // Save the PC even if the branch is not taken
5764 return_address=start+i*4+8;
5765 emit_movimm(return_address,rt); // PC into link register
5767 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5771 cc=get_reg(branch_regs[i].regmap,CCREG);
5772 assert(cc==HOST_CCREG);
5774 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5775 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5776 assem_debug("cycle count (adj)\n");
5778 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5779 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5780 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5781 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5783 assem_debug("branch: internal\n");
5785 assem_debug("branch: external\n");
5786 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5787 ds_assemble_entry(i);
5790 add_to_linker(out,ba[i],internal);
5793 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5794 if(((u_int)out)&7) emit_addnop(0);
5798 else if(nevertaken) {
5799 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5802 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5805 void *nottaken = NULL;
5806 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5807 if(adj&&!invert) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5810 if((dops[i].opcode2&0xf)==0) // BLTZ/BLTZAL
5817 add_to_linker(out,ba[i],internal);
5821 if((dops[i].opcode2&0xf)==1) // BGEZ/BLTZAL
5828 add_to_linker(out,ba[i],internal);
5835 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5836 if (match && (!internal || !dops[(ba[i] - start) >> 2].is_ds)) {
5838 emit_addimm(cc,-adj,cc);
5839 add_to_linker(out,ba[i],internal);
5842 add_to_linker(out,ba[i],internal*2);
5848 if(adj) emit_addimm(cc,-adj,cc);
5849 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5850 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5852 assem_debug("branch: internal\n");
5854 assem_debug("branch: external\n");
5855 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5856 ds_assemble_entry(i);
5859 add_to_linker(out,ba[i],internal);
5863 set_jump_target(nottaken, out);
5867 if(!invert) emit_addimm(cc,adj,cc);
5869 } // (!unconditional)
5873 // In-order execution (branch first)
5875 void *nottaken = NULL;
5876 if(dops[i].rt1==31) {
5877 int rt,return_address;
5878 rt=get_reg(branch_regs[i].regmap,31);
5880 // Save the PC even if the branch is not taken
5881 return_address=start+i*4+8;
5882 emit_movimm(return_address,rt); // PC into link register
5884 emit_prefetch(hash_table_get(return_address));
5888 if(!unconditional) {
5889 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5891 if((dops[i].opcode2&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5897 if((dops[i].opcode2&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5903 } // if(!unconditional)
5905 uint64_t ds_unneeded=branch_regs[i].u;
5906 ds_unneeded&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
5910 //assem_debug("1:\n");
5911 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5913 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5914 address_generation(i+1,&branch_regs[i],0);
5916 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5917 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5918 ds_assemble(i+1,&branch_regs[i]);
5919 cc=get_reg(branch_regs[i].regmap,CCREG);
5921 emit_loadreg(CCREG,cc=HOST_CCREG);
5922 // CHECK: Is the following instruction (fall thru) allocated ok?
5924 assert(cc==HOST_CCREG);
5925 store_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5926 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5927 assem_debug("cycle count (adj)\n");
5928 if(adj) emit_addimm(cc, ccadj[i] + CLOCK_ADJUST(2) - adj, cc);
5929 load_regs_bt(branch_regs[i].regmap,branch_regs[i].dirty,ba[i]);
5931 assem_debug("branch: internal\n");
5933 assem_debug("branch: external\n");
5934 if (internal && dops[(ba[i] - start) >> 2].is_ds) {
5935 ds_assemble_entry(i);
5938 add_to_linker(out,ba[i],internal);
5943 if(!unconditional) {
5944 set_jump_target(nottaken, out);
5945 assem_debug("1:\n");
5946 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,ds_unneeded);
5947 load_regs(regs[i].regmap,branch_regs[i].regmap,dops[i+1].rs1,dops[i+1].rs2);
5948 address_generation(i+1,&branch_regs[i],0);
5950 load_reg(regs[i].regmap,branch_regs[i].regmap,ROREG);
5951 load_regs(regs[i].regmap,branch_regs[i].regmap,CCREG,INVCP);
5952 ds_assemble(i+1,&branch_regs[i]);
5953 cc=get_reg(branch_regs[i].regmap,CCREG);
5955 // Cycle count isn't in a register, temporarily load it then write it out
5956 emit_loadreg(CCREG,HOST_CCREG);
5957 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), HOST_CCREG);
5960 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5961 emit_storereg(CCREG,HOST_CCREG);
5964 cc=get_reg(i_regmap,CCREG);
5965 assert(cc==HOST_CCREG);
5966 emit_addimm_and_set_flags(ccadj[i] + CLOCK_ADJUST(2), cc);
5969 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5975 static void check_regmap(signed char *regmap)
5979 for (i = 0; i < HOST_REGS; i++) {
5982 for (j = i + 1; j < HOST_REGS; j++)
5983 assert(regmap[i] != regmap[j]);
5989 #include <inttypes.h>
5990 static char insn[MAXBLOCK][10];
5992 #define set_mnemonic(i_, n_) \
5993 strcpy(insn[i_], n_)
5995 void print_regmap(const char *name, const signed char *regmap)
5999 fputs(name, stdout);
6000 for (i = 0; i < HOST_REGS; i++) {
6003 l = snprintf(buf, sizeof(buf), "$%d", regmap[i]);
6007 printf(" r%d=%s", i, buf);
6009 fputs("\n", stdout);
6013 void disassemble_inst(int i)
6015 if (dops[i].bt) printf("*"); else printf(" ");
6016 switch(dops[i].itype) {
6018 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6020 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2,i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6022 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],dops[i].rs1,start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6024 if (dops[i].opcode==0x9&&dops[i].rt1!=31)
6025 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1);
6027 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6030 if(dops[i].opcode==0xf) //LUI
6031 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],dops[i].rt1,imm[i]&0xffff);
6033 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6037 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6041 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],dops[i].rs2,dops[i].rs1,imm[i]);
6045 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,dops[i].rs2);
6048 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],dops[i].rs1,dops[i].rs2);
6051 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],dops[i].rt1,dops[i].rs1,imm[i]);
6054 if((dops[i].opcode2&0x1d)==0x10)
6055 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rt1);
6056 else if((dops[i].opcode2&0x1d)==0x11)
6057 printf (" %x: %s r%d\n",start+i*4,insn[i],dops[i].rs1);
6059 printf (" %x: %s\n",start+i*4,insn[i]);
6062 if(dops[i].opcode2==0)
6063 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC0
6064 else if(dops[i].opcode2==4)
6065 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC0
6066 else printf (" %x: %s\n",start+i*4,insn[i]);
6069 if(dops[i].opcode2<3)
6070 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC1
6071 else if(dops[i].opcode2>3)
6072 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC1
6073 else printf (" %x: %s\n",start+i*4,insn[i]);
6076 if(dops[i].opcode2<3)
6077 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rt1,(source[i]>>11)&0x1f); // MFC2
6078 else if(dops[i].opcode2>3)
6079 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],dops[i].rs1,(source[i]>>11)&0x1f); // MTC2
6080 else printf (" %x: %s\n",start+i*4,insn[i]);
6083 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6086 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,dops[i].rs1,imm[i]);
6089 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6092 //printf (" %s %8x\n",insn[i],source[i]);
6093 printf (" %x: %s\n",start+i*4,insn[i]);
6096 printf("D: %"PRIu64" WD: %"PRIu64" U: %"PRIu64"\n",
6097 regs[i].dirty, regs[i].wasdirty, unneeded_reg[i]);
6098 print_regmap("pre: ", regmap_pre[i]);
6099 print_regmap("entry: ", regs[i].regmap_entry);
6100 print_regmap("map: ", regs[i].regmap);
6101 if (dops[i].is_jump) {
6102 print_regmap("bentry:", branch_regs[i].regmap_entry);
6103 print_regmap("bmap: ", branch_regs[i].regmap);
6107 #define set_mnemonic(i_, n_)
6108 static void disassemble_inst(int i) {}
6111 #define DRC_TEST_VAL 0x74657374
6113 static noinline void new_dynarec_test(void)
6115 int (*testfunc)(void);
6120 // check structure linkage
6121 if ((u_char *)rcnts - (u_char *)&psxRegs != sizeof(psxRegs))
6123 SysPrintf("linkage_arm* miscompilation/breakage detected.\n");
6126 SysPrintf("(%p) testing if we can run recompiled code @%p...\n",
6127 new_dynarec_test, out);
6128 ((volatile u_int *)NDRC_WRITE_OFFSET(out))[0]++; // make the cache dirty
6130 for (i = 0; i < ARRAY_SIZE(ret); i++) {
6131 out = ndrc->translation_cache;
6132 beginning = start_block();
6133 emit_movimm(DRC_TEST_VAL + i, 0); // test
6136 end_block(beginning);
6137 testfunc = beginning;
6138 ret[i] = testfunc();
6141 if (ret[0] == DRC_TEST_VAL && ret[1] == DRC_TEST_VAL + 1)
6142 SysPrintf("test passed.\n");
6144 SysPrintf("test failed, will likely crash soon (r=%08x %08x)\n", ret[0], ret[1]);
6145 out = ndrc->translation_cache;
6148 // clear the state completely, instead of just marking
6149 // things invalid like invalidate_all_pages() does
6150 void new_dynarec_clear_full(void)
6153 out = ndrc->translation_cache;
6154 memset(invalid_code,1,sizeof(invalid_code));
6155 memset(hash_table,0xff,sizeof(hash_table));
6156 memset(mini_ht,-1,sizeof(mini_ht));
6157 memset(shadow,0,sizeof(shadow));
6159 expirep = EXPIRITY_OFFSET;
6160 pending_exception=0;
6163 inv_code_start=inv_code_end=~0;
6166 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6167 blocks_clear(&blocks[n]);
6168 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6172 stat_clear(stat_blocks);
6173 stat_clear(stat_links);
6175 cycle_multiplier_old = cycle_multiplier;
6176 new_dynarec_hacks_old = new_dynarec_hacks;
6179 void new_dynarec_init(void)
6181 SysPrintf("Init new dynarec, ndrc size %x\n", (int)sizeof(*ndrc));
6186 #ifdef BASE_ADDR_DYNAMIC
6188 sceBlock = getVMBlock(); //sceKernelAllocMemBlockForVM("code", sizeof(*ndrc));
6190 SysPrintf("sceKernelAllocMemBlockForVM failed: %x\n", sceBlock);
6191 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&ndrc);
6193 SysPrintf("sceKernelGetMemBlockBase failed: %x\n", ret);
6194 sceKernelOpenVMDomain();
6195 sceClibPrintf("translation_cache = 0x%08lx\n ", (long)ndrc->translation_cache);
6196 #elif defined(_MSC_VER)
6197 ndrc = VirtualAlloc(NULL, sizeof(*ndrc), MEM_COMMIT | MEM_RESERVE,
6198 PAGE_EXECUTE_READWRITE);
6199 #elif defined(HAVE_LIBNX)
6200 Result rc = jitCreate(&g_jit, sizeof(*ndrc));
6202 SysPrintf("jitCreate failed: %08x\n", rc);
6203 SysPrintf("jitCreate: RX: %p RW: %p type: %d\n", g_jit.rx_addr, g_jit.rw_addr, g_jit.type);
6204 jitTransitionToWritable(&g_jit);
6205 ndrc = g_jit.rx_addr;
6206 ndrc_write_ofs = (char *)g_jit.rw_addr - (char *)ndrc;
6207 memset(NDRC_WRITE_OFFSET(&ndrc->tramp), 0, sizeof(ndrc->tramp));
6209 uintptr_t desired_addr = 0;
6210 int prot = PROT_READ | PROT_WRITE | PROT_EXEC;
6211 int flags = MAP_PRIVATE | MAP_ANONYMOUS;
6215 desired_addr = ((uintptr_t)&_end + 0xffffff) & ~0xffffffl;
6217 #ifdef TC_WRITE_OFFSET
6218 // mostly for testing
6219 fd = open("/dev/shm/pcsxr", O_CREAT | O_RDWR, 0600);
6220 ftruncate(fd, sizeof(*ndrc));
6221 void *mw = mmap(NULL, sizeof(*ndrc), PROT_READ | PROT_WRITE,
6222 (flags = MAP_SHARED), fd, 0);
6223 assert(mw != MAP_FAILED);
6224 prot = PROT_READ | PROT_EXEC;
6226 ndrc = mmap((void *)desired_addr, sizeof(*ndrc), prot, flags, fd, 0);
6227 if (ndrc == MAP_FAILED) {
6228 SysPrintf("mmap() failed: %s\n", strerror(errno));
6231 #ifdef TC_WRITE_OFFSET
6232 ndrc_write_ofs = (char *)mw - (char *)ndrc;
6236 #ifndef NO_WRITE_EXEC
6237 // not all systems allow execute in data segment by default
6238 // size must be 4K aligned for 3DS?
6239 if (mprotect(ndrc, sizeof(*ndrc),
6240 PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6241 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6244 out = ndrc->translation_cache;
6245 cycle_multiplier=200;
6246 new_dynarec_clear_full();
6248 // Copy this into local area so we don't have to put it in every literal pool
6249 invc_ptr=invalid_code;
6253 ram_offset=(uintptr_t)rdram-0x80000000;
6255 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
6256 SysPrintf("Mapped (RAM/scrp/ROM/LUTs/TC):\n");
6257 SysPrintf("%p/%p/%p/%p/%p\n", psxM, psxH, psxR, mem_rtab, out);
6260 void new_dynarec_cleanup(void)
6263 #ifdef BASE_ADDR_DYNAMIC
6265 // sceBlock is managed by retroarch's bootstrap code
6266 //sceKernelFreeMemBlock(sceBlock);
6268 #elif defined(HAVE_LIBNX)
6272 if (munmap(ndrc, sizeof(*ndrc)) < 0)
6273 SysPrintf("munmap() failed\n");
6277 for (n = 0; n < ARRAY_SIZE(blocks); n++)
6278 blocks_clear(&blocks[n]);
6279 for (n = 0; n < ARRAY_SIZE(jumps); n++) {
6283 stat_clear(stat_blocks);
6284 stat_clear(stat_links);
6285 new_dynarec_print_stats();
6288 static u_int *get_source_start(u_int addr, u_int *limit)
6290 if (addr < 0x00200000 ||
6291 (0xa0000000 <= addr && addr < 0xa0200000))
6293 // used for BIOS calls mostly?
6294 *limit = (addr&0xa0000000)|0x00200000;
6295 return (u_int *)(rdram + (addr&0x1fffff));
6297 else if (!Config.HLE && (
6298 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
6299 (0xbfc00000 <= addr && addr < 0xbfc80000)))
6301 // BIOS. The multiplier should be much higher as it's uncached 8bit mem,
6302 // but timings in PCSX are too tied to the interpreter's BIAS
6303 if (!HACK_ENABLED(NDHACK_OVERRIDE_CYCLE_M))
6304 cycle_multiplier_active = 200;
6306 *limit = (addr & 0xfff00000) | 0x80000;
6307 return (u_int *)((u_char *)psxR + (addr&0x7ffff));
6309 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
6310 *limit = (addr & 0x80600000) + 0x00200000;
6311 return (u_int *)(rdram + (addr&0x1fffff));
6316 static u_int scan_for_ret(u_int addr)
6321 mem = get_source_start(addr, &limit);
6325 if (limit > addr + 0x1000)
6326 limit = addr + 0x1000;
6327 for (; addr < limit; addr += 4, mem++) {
6328 if (*mem == 0x03e00008) // jr $ra
6334 struct savestate_block {
6339 static int addr_cmp(const void *p1_, const void *p2_)
6341 const struct savestate_block *p1 = p1_, *p2 = p2_;
6342 return p1->addr - p2->addr;
6345 int new_dynarec_save_blocks(void *save, int size)
6347 struct savestate_block *sblocks = save;
6348 int maxcount = size / sizeof(sblocks[0]);
6349 struct savestate_block tmp_blocks[1024];
6350 struct block_info *block;
6351 int p, s, d, o, bcnt;
6355 for (p = 0; p < ARRAY_SIZE(blocks); p++) {
6357 for (block = blocks[p]; block != NULL; block = block->next) {
6358 if (block->is_dirty)
6360 tmp_blocks[bcnt].addr = block->start;
6361 tmp_blocks[bcnt].regflags = block->reg_sv_flags;
6366 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
6368 addr = tmp_blocks[0].addr;
6369 for (s = d = 0; s < bcnt; s++) {
6370 if (tmp_blocks[s].addr < addr)
6372 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
6373 tmp_blocks[d++] = tmp_blocks[s];
6374 addr = scan_for_ret(tmp_blocks[s].addr);
6377 if (o + d > maxcount)
6379 memcpy(&sblocks[o], tmp_blocks, d * sizeof(sblocks[0]));
6383 return o * sizeof(sblocks[0]);
6386 void new_dynarec_load_blocks(const void *save, int size)
6388 const struct savestate_block *sblocks = save;
6389 int count = size / sizeof(sblocks[0]);
6390 struct block_info *block;
6391 u_int regs_save[32];
6396 // restore clean blocks, if any
6397 for (page = 0, b = i = 0; page < ARRAY_SIZE(blocks); page++) {
6398 for (block = blocks[page]; block != NULL; block = block->next, b++) {
6399 if (!block->is_dirty)
6401 assert(block->source && block->copy);
6402 if (memcmp(block->source, block->copy, block->len))
6405 // see try_restore_block
6406 block->is_dirty = 0;
6407 mark_invalid_code(block->start, block->len, 0);
6411 inv_debug("load_blocks: %d/%d clean blocks\n", i, b);
6413 // change GPRs for speculation to at least partially work..
6414 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
6415 for (i = 1; i < 32; i++)
6416 psxRegs.GPR.r[i] = 0x80000000;
6418 for (b = 0; b < count; b++) {
6419 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6421 psxRegs.GPR.r[i] = 0x1f800000;
6424 ndrc_get_addr_ht(sblocks[b].addr);
6426 for (f = sblocks[b].regflags, i = 0; f; f >>= 1, i++) {
6428 psxRegs.GPR.r[i] = 0x80000000;
6432 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
6435 void new_dynarec_print_stats(void)
6438 printf("cc %3d,%3d,%3d lu%6d,%3d,%3d c%3d inv%3d,%3d tc_offs %zu b %u,%u\n",
6439 stat_bc_pre, stat_bc_direct, stat_bc_restore,
6440 stat_ht_lookups, stat_jump_in_lookups, stat_restore_tries,
6441 stat_restore_compares, stat_inv_addr_calls, stat_inv_hits,
6442 out - ndrc->translation_cache, stat_blocks, stat_links);
6443 stat_bc_direct = stat_bc_pre = stat_bc_restore =
6444 stat_ht_lookups = stat_jump_in_lookups = stat_restore_tries =
6445 stat_restore_compares = stat_inv_addr_calls = stat_inv_hits = 0;
6449 static int apply_hacks(void)
6452 if (HACK_ENABLED(NDHACK_NO_COMPAT_HACKS))
6454 /* special hack(s) */
6455 for (i = 0; i < slen - 4; i++)
6457 // lui a4, 0xf200; jal <rcnt_read>; addu a0, 2; slti v0, 28224
6458 if (source[i] == 0x3c04f200 && dops[i+1].itype == UJUMP
6459 && source[i+2] == 0x34840002 && dops[i+3].opcode == 0x0a
6460 && imm[i+3] == 0x6e40 && dops[i+3].rs1 == 2)
6462 SysPrintf("PE2 hack @%08x\n", start + (i+3)*4);
6463 dops[i + 3].itype = NOP;
6467 if (i > 10 && source[i-1] == 0 && source[i-2] == 0x03e00008
6468 && source[i-4] == 0x8fbf0018 && source[i-6] == 0x00c0f809
6469 && dops[i-7].itype == STORE)
6472 if (dops[i].itype == IMM16)
6474 // swl r2, 15(r6); swr r2, 12(r6); sw r6, *; jalr r6
6475 if (dops[i].itype == STORELR && dops[i].rs1 == 6
6476 && dops[i-1].itype == STORELR && dops[i-1].rs1 == 6)
6478 SysPrintf("F1 hack from %08x, old dst %08x\n", start, hack_addr);
6486 static noinline void pass1_disassemble(u_int pagelimit)
6488 int i, j, done = 0, ni_count = 0;
6489 unsigned int type,op,op2;
6491 for (i = 0; !done; i++)
6493 memset(&dops[i], 0, sizeof(dops[i]));
6495 minimum_free_regs[i]=0;
6496 dops[i].opcode=op=source[i]>>26;
6499 case 0x00: set_mnemonic(i, "special"); type=NI;
6503 case 0x00: set_mnemonic(i, "SLL"); type=SHIFTIMM; break;
6504 case 0x02: set_mnemonic(i, "SRL"); type=SHIFTIMM; break;
6505 case 0x03: set_mnemonic(i, "SRA"); type=SHIFTIMM; break;
6506 case 0x04: set_mnemonic(i, "SLLV"); type=SHIFT; break;
6507 case 0x06: set_mnemonic(i, "SRLV"); type=SHIFT; break;
6508 case 0x07: set_mnemonic(i, "SRAV"); type=SHIFT; break;
6509 case 0x08: set_mnemonic(i, "JR"); type=RJUMP; break;
6510 case 0x09: set_mnemonic(i, "JALR"); type=RJUMP; break;
6511 case 0x0C: set_mnemonic(i, "SYSCALL"); type=SYSCALL; break;
6512 case 0x0D: set_mnemonic(i, "BREAK"); type=SYSCALL; break;
6513 case 0x0F: set_mnemonic(i, "SYNC"); type=OTHER; break;
6514 case 0x10: set_mnemonic(i, "MFHI"); type=MOV; break;
6515 case 0x11: set_mnemonic(i, "MTHI"); type=MOV; break;
6516 case 0x12: set_mnemonic(i, "MFLO"); type=MOV; break;
6517 case 0x13: set_mnemonic(i, "MTLO"); type=MOV; break;
6518 case 0x18: set_mnemonic(i, "MULT"); type=MULTDIV; break;
6519 case 0x19: set_mnemonic(i, "MULTU"); type=MULTDIV; break;
6520 case 0x1A: set_mnemonic(i, "DIV"); type=MULTDIV; break;
6521 case 0x1B: set_mnemonic(i, "DIVU"); type=MULTDIV; break;
6522 case 0x20: set_mnemonic(i, "ADD"); type=ALU; break;
6523 case 0x21: set_mnemonic(i, "ADDU"); type=ALU; break;
6524 case 0x22: set_mnemonic(i, "SUB"); type=ALU; break;
6525 case 0x23: set_mnemonic(i, "SUBU"); type=ALU; break;
6526 case 0x24: set_mnemonic(i, "AND"); type=ALU; break;
6527 case 0x25: set_mnemonic(i, "OR"); type=ALU; break;
6528 case 0x26: set_mnemonic(i, "XOR"); type=ALU; break;
6529 case 0x27: set_mnemonic(i, "NOR"); type=ALU; break;
6530 case 0x2A: set_mnemonic(i, "SLT"); type=ALU; break;
6531 case 0x2B: set_mnemonic(i, "SLTU"); type=ALU; break;
6532 case 0x30: set_mnemonic(i, "TGE"); type=NI; break;
6533 case 0x31: set_mnemonic(i, "TGEU"); type=NI; break;
6534 case 0x32: set_mnemonic(i, "TLT"); type=NI; break;
6535 case 0x33: set_mnemonic(i, "TLTU"); type=NI; break;
6536 case 0x34: set_mnemonic(i, "TEQ"); type=NI; break;
6537 case 0x36: set_mnemonic(i, "TNE"); type=NI; break;
6539 case 0x14: set_mnemonic(i, "DSLLV"); type=SHIFT; break;
6540 case 0x16: set_mnemonic(i, "DSRLV"); type=SHIFT; break;
6541 case 0x17: set_mnemonic(i, "DSRAV"); type=SHIFT; break;
6542 case 0x1C: set_mnemonic(i, "DMULT"); type=MULTDIV; break;
6543 case 0x1D: set_mnemonic(i, "DMULTU"); type=MULTDIV; break;
6544 case 0x1E: set_mnemonic(i, "DDIV"); type=MULTDIV; break;
6545 case 0x1F: set_mnemonic(i, "DDIVU"); type=MULTDIV; break;
6546 case 0x2C: set_mnemonic(i, "DADD"); type=ALU; break;
6547 case 0x2D: set_mnemonic(i, "DADDU"); type=ALU; break;
6548 case 0x2E: set_mnemonic(i, "DSUB"); type=ALU; break;
6549 case 0x2F: set_mnemonic(i, "DSUBU"); type=ALU; break;
6550 case 0x38: set_mnemonic(i, "DSLL"); type=SHIFTIMM; break;
6551 case 0x3A: set_mnemonic(i, "DSRL"); type=SHIFTIMM; break;
6552 case 0x3B: set_mnemonic(i, "DSRA"); type=SHIFTIMM; break;
6553 case 0x3C: set_mnemonic(i, "DSLL32"); type=SHIFTIMM; break;
6554 case 0x3E: set_mnemonic(i, "DSRL32"); type=SHIFTIMM; break;
6555 case 0x3F: set_mnemonic(i, "DSRA32"); type=SHIFTIMM; break;
6559 case 0x01: set_mnemonic(i, "regimm"); type=NI;
6560 op2=(source[i]>>16)&0x1f;
6563 case 0x00: set_mnemonic(i, "BLTZ"); type=SJUMP; break;
6564 case 0x01: set_mnemonic(i, "BGEZ"); type=SJUMP; break;
6565 //case 0x02: set_mnemonic(i, "BLTZL"); type=SJUMP; break;
6566 //case 0x03: set_mnemonic(i, "BGEZL"); type=SJUMP; break;
6567 //case 0x08: set_mnemonic(i, "TGEI"); type=NI; break;
6568 //case 0x09: set_mnemonic(i, "TGEIU"); type=NI; break;
6569 //case 0x0A: set_mnemonic(i, "TLTI"); type=NI; break;
6570 //case 0x0B: set_mnemonic(i, "TLTIU"); type=NI; break;
6571 //case 0x0C: set_mnemonic(i, "TEQI"); type=NI; break;
6572 //case 0x0E: set_mnemonic(i, "TNEI"); type=NI; break;
6573 case 0x10: set_mnemonic(i, "BLTZAL"); type=SJUMP; break;
6574 case 0x11: set_mnemonic(i, "BGEZAL"); type=SJUMP; break;
6575 //case 0x12: set_mnemonic(i, "BLTZALL"); type=SJUMP; break;
6576 //case 0x13: set_mnemonic(i, "BGEZALL"); type=SJUMP; break;
6579 case 0x02: set_mnemonic(i, "J"); type=UJUMP; break;
6580 case 0x03: set_mnemonic(i, "JAL"); type=UJUMP; break;
6581 case 0x04: set_mnemonic(i, "BEQ"); type=CJUMP; break;
6582 case 0x05: set_mnemonic(i, "BNE"); type=CJUMP; break;
6583 case 0x06: set_mnemonic(i, "BLEZ"); type=CJUMP; break;
6584 case 0x07: set_mnemonic(i, "BGTZ"); type=CJUMP; break;
6585 case 0x08: set_mnemonic(i, "ADDI"); type=IMM16; break;
6586 case 0x09: set_mnemonic(i, "ADDIU"); type=IMM16; break;
6587 case 0x0A: set_mnemonic(i, "SLTI"); type=IMM16; break;
6588 case 0x0B: set_mnemonic(i, "SLTIU"); type=IMM16; break;
6589 case 0x0C: set_mnemonic(i, "ANDI"); type=IMM16; break;
6590 case 0x0D: set_mnemonic(i, "ORI"); type=IMM16; break;
6591 case 0x0E: set_mnemonic(i, "XORI"); type=IMM16; break;
6592 case 0x0F: set_mnemonic(i, "LUI"); type=IMM16; break;
6593 case 0x10: set_mnemonic(i, "cop0"); type=NI;
6594 op2=(source[i]>>21)&0x1f;
6597 case 0x00: set_mnemonic(i, "MFC0"); type=COP0; break;
6598 case 0x02: set_mnemonic(i, "CFC0"); type=COP0; break;
6599 case 0x04: set_mnemonic(i, "MTC0"); type=COP0; break;
6600 case 0x06: set_mnemonic(i, "CTC0"); type=COP0; break;
6601 case 0x10: set_mnemonic(i, "RFE"); type=COP0; break;
6604 case 0x11: set_mnemonic(i, "cop1"); type=COP1;
6605 op2=(source[i]>>21)&0x1f;
6608 case 0x14: set_mnemonic(i, "BEQL"); type=CJUMP; break;
6609 case 0x15: set_mnemonic(i, "BNEL"); type=CJUMP; break;
6610 case 0x16: set_mnemonic(i, "BLEZL"); type=CJUMP; break;
6611 case 0x17: set_mnemonic(i, "BGTZL"); type=CJUMP; break;
6612 case 0x18: set_mnemonic(i, "DADDI"); type=IMM16; break;
6613 case 0x19: set_mnemonic(i, "DADDIU"); type=IMM16; break;
6614 case 0x1A: set_mnemonic(i, "LDL"); type=LOADLR; break;
6615 case 0x1B: set_mnemonic(i, "LDR"); type=LOADLR; break;
6617 case 0x20: set_mnemonic(i, "LB"); type=LOAD; break;
6618 case 0x21: set_mnemonic(i, "LH"); type=LOAD; break;
6619 case 0x22: set_mnemonic(i, "LWL"); type=LOADLR; break;
6620 case 0x23: set_mnemonic(i, "LW"); type=LOAD; break;
6621 case 0x24: set_mnemonic(i, "LBU"); type=LOAD; break;
6622 case 0x25: set_mnemonic(i, "LHU"); type=LOAD; break;
6623 case 0x26: set_mnemonic(i, "LWR"); type=LOADLR; break;
6625 case 0x27: set_mnemonic(i, "LWU"); type=LOAD; break;
6627 case 0x28: set_mnemonic(i, "SB"); type=STORE; break;
6628 case 0x29: set_mnemonic(i, "SH"); type=STORE; break;
6629 case 0x2A: set_mnemonic(i, "SWL"); type=STORELR; break;
6630 case 0x2B: set_mnemonic(i, "SW"); type=STORE; break;
6632 case 0x2C: set_mnemonic(i, "SDL"); type=STORELR; break;
6633 case 0x2D: set_mnemonic(i, "SDR"); type=STORELR; break;
6635 case 0x2E: set_mnemonic(i, "SWR"); type=STORELR; break;
6636 case 0x2F: set_mnemonic(i, "CACHE"); type=NOP; break;
6637 case 0x30: set_mnemonic(i, "LL"); type=NI; break;
6638 case 0x31: set_mnemonic(i, "LWC1"); type=C1LS; break;
6640 case 0x34: set_mnemonic(i, "LLD"); type=NI; break;
6641 case 0x35: set_mnemonic(i, "LDC1"); type=C1LS; break;
6642 case 0x37: set_mnemonic(i, "LD"); type=LOAD; break;
6644 case 0x38: set_mnemonic(i, "SC"); type=NI; break;
6645 case 0x39: set_mnemonic(i, "SWC1"); type=C1LS; break;
6647 case 0x3C: set_mnemonic(i, "SCD"); type=NI; break;
6648 case 0x3D: set_mnemonic(i, "SDC1"); type=C1LS; break;
6649 case 0x3F: set_mnemonic(i, "SD"); type=STORE; break;
6651 case 0x12: set_mnemonic(i, "COP2"); type=NI;
6652 op2=(source[i]>>21)&0x1f;
6654 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
6655 if (gte_handlers[source[i]&0x3f]!=NULL) {
6657 if (gte_regnames[source[i]&0x3f]!=NULL)
6658 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
6660 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
6667 case 0x00: set_mnemonic(i, "MFC2"); type=COP2; break;
6668 case 0x02: set_mnemonic(i, "CFC2"); type=COP2; break;
6669 case 0x04: set_mnemonic(i, "MTC2"); type=COP2; break;
6670 case 0x06: set_mnemonic(i, "CTC2"); type=COP2; break;
6673 case 0x32: set_mnemonic(i, "LWC2"); type=C2LS; break;
6674 case 0x3A: set_mnemonic(i, "SWC2"); type=C2LS; break;
6675 case 0x3B: set_mnemonic(i, "HLECALL"); type=HLECALL; break;
6676 default: set_mnemonic(i, "???"); type=NI;
6677 SysPrintf("NI %08x @%08x (%08x)\n", source[i], start + i*4, start);
6681 dops[i].opcode2=op2;
6682 /* Get registers/immediates */
6684 gte_rs[i]=gte_rt[i]=0;
6687 dops[i].rs1=(source[i]>>21)&0x1f;
6689 dops[i].rt1=(source[i]>>16)&0x1f;
6691 imm[i]=(short)source[i];
6695 dops[i].rs1=(source[i]>>21)&0x1f;
6696 dops[i].rs2=(source[i]>>16)&0x1f;
6699 imm[i]=(short)source[i];
6702 // LWL/LWR only load part of the register,
6703 // therefore the target register must be treated as a source too
6704 dops[i].rs1=(source[i]>>21)&0x1f;
6705 dops[i].rs2=(source[i]>>16)&0x1f;
6706 dops[i].rt1=(source[i]>>16)&0x1f;
6708 imm[i]=(short)source[i];
6711 if (op==0x0f) dops[i].rs1=0; // LUI instruction has no source register
6712 else dops[i].rs1=(source[i]>>21)&0x1f;
6714 dops[i].rt1=(source[i]>>16)&0x1f;
6716 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
6717 imm[i]=(unsigned short)source[i];
6719 imm[i]=(short)source[i];
6727 // The JAL instruction writes to r31.
6734 dops[i].rs1=(source[i]>>21)&0x1f;
6738 // The JALR instruction writes to rd.
6740 dops[i].rt1=(source[i]>>11)&0x1f;
6745 dops[i].rs1=(source[i]>>21)&0x1f;
6746 dops[i].rs2=(source[i]>>16)&0x1f;
6749 if(op&2) { // BGTZ/BLEZ
6754 dops[i].rs1=(source[i]>>21)&0x1f;
6758 if(op2&0x10) { // BxxAL
6760 // NOTE: If the branch is not taken, r31 is still overwritten
6764 dops[i].rs1=(source[i]>>21)&0x1f; // source
6765 dops[i].rs2=(source[i]>>16)&0x1f; // subtract amount
6766 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6770 dops[i].rs1=(source[i]>>21)&0x1f; // source
6771 dops[i].rs2=(source[i]>>16)&0x1f; // divisor
6780 if(op2==0x10) dops[i].rs1=HIREG; // MFHI
6781 if(op2==0x11) dops[i].rt1=HIREG; // MTHI
6782 if(op2==0x12) dops[i].rs1=LOREG; // MFLO
6783 if(op2==0x13) dops[i].rt1=LOREG; // MTLO
6784 if((op2&0x1d)==0x10) dops[i].rt1=(source[i]>>11)&0x1f; // MFxx
6785 if((op2&0x1d)==0x11) dops[i].rs1=(source[i]>>21)&0x1f; // MTxx
6788 dops[i].rs1=(source[i]>>16)&0x1f; // target of shift
6789 dops[i].rs2=(source[i]>>21)&0x1f; // shift amount
6790 dops[i].rt1=(source[i]>>11)&0x1f; // destination
6794 dops[i].rs1=(source[i]>>16)&0x1f;
6796 dops[i].rt1=(source[i]>>11)&0x1f;
6798 imm[i]=(source[i]>>6)&0x1f;
6799 // DSxx32 instructions
6800 if(op2>=0x3c) imm[i]|=0x20;
6807 if(op2==0||op2==2) dops[i].rt1=(source[i]>>16)&0x1F; // MFC0/CFC0
6808 if(op2==4||op2==6) dops[i].rs1=(source[i]>>16)&0x1F; // MTC0/CTC0
6809 if(op2==4&&((source[i]>>11)&0x1f)==12) dops[i].rt2=CSREG; // Status
6810 if(op2==16) if((source[i]&0x3f)==0x18) dops[i].rs2=CCREG; // ERET
6817 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
6818 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
6826 if(op2<3) dops[i].rt1=(source[i]>>16)&0x1F; // MFC2/CFC2
6827 if(op2>3) dops[i].rs1=(source[i]>>16)&0x1F; // MTC2/CTC2
6829 int gr=(source[i]>>11)&0x1F;
6832 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
6833 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
6834 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
6835 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
6839 dops[i].rs1=(source[i]>>21)&0x1F;
6843 imm[i]=(short)source[i];
6846 dops[i].rs1=(source[i]>>21)&0x1F;
6850 imm[i]=(short)source[i];
6851 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
6852 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
6859 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
6860 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
6861 gte_rt[i]|=1ll<<63; // every op changes flags
6862 if((source[i]&0x3f)==GTE_MVMVA) {
6863 int v = (source[i] >> 15) & 3;
6864 gte_rs[i]&=~0xe3fll;
6865 if(v==3) gte_rs[i]|=0xe00ll;
6866 else gte_rs[i]|=3ll<<(v*2);
6883 /* Calculate branch target addresses */
6885 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
6886 else if(type==CJUMP&&dops[i].rs1==dops[i].rs2&&(op&1))
6887 ba[i]=start+i*4+8; // Ignore never taken branch
6888 else if(type==SJUMP&&dops[i].rs1==0&&!(op2&1))
6889 ba[i]=start+i*4+8; // Ignore never taken branch
6890 else if(type==CJUMP||type==SJUMP)
6891 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
6894 /* simplify always (not)taken branches */
6895 if (type == CJUMP && dops[i].rs1 == dops[i].rs2) {
6896 dops[i].rs1 = dops[i].rs2 = 0;
6898 dops[i].itype = type = UJUMP;
6899 dops[i].rs2 = CCREG;
6902 else if (type == SJUMP && dops[i].rs1 == 0 && (op2 & 1))
6903 dops[i].itype = type = UJUMP;
6905 dops[i].is_jump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP || dops[i].itype == CJUMP || dops[i].itype == SJUMP);
6906 dops[i].is_ujump = (dops[i].itype == RJUMP || dops[i].itype == UJUMP); // || (source[i] >> 16) == 0x1000 // beq r0,r0
6907 dops[i].is_load = (dops[i].itype == LOAD || dops[i].itype == LOADLR || op == 0x32); // LWC2
6908 dops[i].is_store = (dops[i].itype == STORE || dops[i].itype == STORELR || op == 0x3a); // SWC2
6910 /* messy cases to just pass over to the interpreter */
6911 if (i > 0 && dops[i-1].is_jump) {
6913 // branch in delay slot?
6914 if (dops[i].is_jump) {
6915 // don't handle first branch and call interpreter if it's hit
6916 SysPrintf("branch in delay slot @%08x (%08x)\n", start + i*4, start);
6919 // basic load delay detection
6920 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&dops[i].rt1!=0) {
6921 int t=(ba[i-1]-start)/4;
6922 if(0 <= t && t < i &&(dops[i].rt1==dops[t].rs1||dops[i].rt1==dops[t].rs2)&&dops[t].itype!=CJUMP&&dops[t].itype!=SJUMP) {
6923 // jump target wants DS result - potential load delay effect
6924 SysPrintf("load delay @%08x (%08x)\n", start + i*4, start);
6926 dops[t+1].bt=1; // expected return from interpreter
6928 else if(i>=2&&dops[i-2].rt1==2&&dops[i].rt1==2&&dops[i].rs1!=2&&dops[i].rs2!=2&&dops[i-1].rs1!=2&&dops[i-1].rs2!=2&&
6929 !(i>=3&&dops[i-3].is_jump)) {
6930 // v0 overwrite like this is a sign of trouble, bail out
6931 SysPrintf("v0 overwrite @%08x (%08x)\n", start + i*4, start);
6936 memset(&dops[i-1], 0, sizeof(dops[i-1]));
6937 dops[i-1].itype = INTCALL;
6938 dops[i-1].rs1 = CCREG;
6941 i--; // don't compile the DS
6945 /* Is this the end of the block? */
6946 if (i > 0 && dops[i-1].is_ujump) {
6947 if (dops[i-1].rt1 == 0) { // not jal
6948 int found_bbranch = 0, t = (ba[i-1] - start) / 4;
6949 if ((u_int)(t - i) < 64 && start + (t+64)*4 < pagelimit) {
6950 // scan for a branch back to i+1
6951 for (j = t; j < t + 64; j++) {
6952 int tmpop = source[j] >> 26;
6953 if (tmpop == 1 || ((tmpop & ~3) == 4)) {
6954 int t2 = j + 1 + (int)(signed short)source[j];
6956 //printf("blk expand %08x<-%08x\n", start + (i+1)*4, start + j*4);
6967 if(stop_after_jal) done=1;
6969 if((source[i+1]&0xfc00003f)==0x0d) done=1;
6971 // Don't recompile stuff that's already compiled
6972 if(check_addr(start+i*4+4)) done=1;
6973 // Don't get too close to the limit
6974 if(i>MAXBLOCK/2) done=1;
6976 if (dops[i].itype == SYSCALL || dops[i].itype == HLECALL || dops[i].itype == INTCALL)
6977 done = stop_after_jal ? 1 : 2;
6979 // Does the block continue due to a branch?
6982 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
6983 if(ba[j]==start+i*4+4) done=j=0;
6984 if(ba[j]==start+i*4+8) done=j=0;
6987 //assert(i<MAXBLOCK-1);
6988 if(start+i*4==pagelimit-4) done=1;
6989 assert(start+i*4<pagelimit);
6990 if (i==MAXBLOCK-1) done=1;
6991 // Stop if we're compiling junk
6992 if(dops[i].itype == NI && (++ni_count > 8 || dops[i].opcode == 0x11)) {
6993 done=stop_after_jal=1;
6994 SysPrintf("Disabled speculative precompilation\n");
6997 while (i > 0 && dops[i-1].is_jump)
7000 assert(!dops[i-1].is_jump);
7004 // Basic liveness analysis for MIPS registers
7005 static noinline void pass2_unneeded_regs(int istart,int iend,int r)
7008 uint64_t u,gte_u,b,gte_b;
7009 uint64_t temp_u,temp_gte_u=0;
7010 uint64_t gte_u_unknown=0;
7011 if (HACK_ENABLED(NDHACK_GTE_UNNEEDED))
7015 gte_u=gte_u_unknown;
7017 //u=unneeded_reg[iend+1];
7019 gte_u=gte_unneeded[iend+1];
7022 for (i=iend;i>=istart;i--)
7024 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
7027 // If subroutine call, flag return address as a possible branch target
7028 if(dops[i].rt1==31 && i<slen-2) dops[i+2].bt=1;
7030 if(ba[i]<start || ba[i]>=(start+slen*4))
7032 // Branch out of this block, flush all regs
7034 gte_u=gte_u_unknown;
7035 branch_unneeded_reg[i]=u;
7036 // Merge in delay slot
7037 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7038 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7041 gte_u&=~gte_rs[i+1];
7045 // Internal branch, flag target
7046 dops[(ba[i]-start)>>2].bt=1;
7047 if(ba[i]<=start+i*4) {
7049 if(dops[i].is_ujump)
7051 // Unconditional branch
7055 // Conditional branch (not taken case)
7056 temp_u=unneeded_reg[i+2];
7057 temp_gte_u&=gte_unneeded[i+2];
7059 // Merge in delay slot
7060 temp_u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7061 temp_u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7063 temp_gte_u|=gte_rt[i+1];
7064 temp_gte_u&=~gte_rs[i+1];
7065 temp_u|=(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2);
7066 temp_u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7068 temp_gte_u|=gte_rt[i];
7069 temp_gte_u&=~gte_rs[i];
7070 unneeded_reg[i]=temp_u;
7071 gte_unneeded[i]=temp_gte_u;
7072 // Only go three levels deep. This recursion can take an
7073 // excessive amount of time if there are a lot of nested loops.
7075 pass2_unneeded_regs((ba[i]-start)>>2,i-1,r+1);
7077 unneeded_reg[(ba[i]-start)>>2]=1;
7078 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
7081 if (dops[i].is_ujump)
7083 // Unconditional branch
7084 u=unneeded_reg[(ba[i]-start)>>2];
7085 gte_u=gte_unneeded[(ba[i]-start)>>2];
7086 branch_unneeded_reg[i]=u;
7087 // Merge in delay slot
7088 u|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7089 u&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7092 gte_u&=~gte_rs[i+1];
7094 // Conditional branch
7095 b=unneeded_reg[(ba[i]-start)>>2];
7096 gte_b=gte_unneeded[(ba[i]-start)>>2];
7097 branch_unneeded_reg[i]=b;
7098 // Branch delay slot
7099 b|=(1LL<<dops[i+1].rt1)|(1LL<<dops[i+1].rt2);
7100 b&=~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7103 gte_b&=~gte_rs[i+1];
7107 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7109 branch_unneeded_reg[i]=1;
7115 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
7117 // SYSCALL instruction (software interrupt)
7120 else if(dops[i].itype==COP0 && dops[i].opcode2==0x10)
7126 // Written registers are unneeded
7127 u|=1LL<<dops[i].rt1;
7128 u|=1LL<<dops[i].rt2;
7130 // Accessed registers are needed
7131 u&=~(1LL<<dops[i].rs1);
7132 u&=~(1LL<<dops[i].rs2);
7134 if(gte_rs[i]&&dops[i].rt1&&(unneeded_reg[i+1]&(1ll<<dops[i].rt1)))
7135 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7136 // Source-target dependencies
7137 // R0 is always unneeded
7141 gte_unneeded[i]=gte_u;
7143 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7146 for(r=1;r<=CCREG;r++) {
7147 if((unneeded_reg[i]>>r)&1) {
7148 if(r==HIREG) printf(" HI");
7149 else if(r==LOREG) printf(" LO");
7150 else printf(" r%d",r);
7158 static noinline void pass3_register_alloc(u_int addr)
7160 struct regstat current; // Current register allocations/status
7161 clear_all_regs(current.regmap_entry);
7162 clear_all_regs(current.regmap);
7163 current.wasdirty = current.dirty = 0;
7164 current.u = unneeded_reg[0];
7165 alloc_reg(¤t, 0, CCREG);
7166 dirty_reg(¤t, CCREG);
7167 current.wasconst = 0;
7168 current.isconst = 0;
7169 current.loadedconst = 0;
7170 current.waswritten = 0;
7177 // First instruction is delay slot
7182 current.regmap[HOST_BTREG]=BTREG;
7189 for(hr=0;hr<HOST_REGS;hr++)
7191 // Is this really necessary?
7192 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7195 current.waswritten=0;
7198 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7199 regs[i].wasconst=current.isconst;
7200 regs[i].wasdirty=current.dirty;
7204 regs[i].loadedconst=0;
7205 if (!dops[i].is_jump) {
7207 current.u=unneeded_reg[i+1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7214 current.u=branch_unneeded_reg[i]&~((1LL<<dops[i+1].rs1)|(1LL<<dops[i+1].rs2));
7215 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7218 SysPrintf("oops, branch at end of block with no delay slot @%08x\n", start + i*4);
7224 ds=0; // Skip delay slot, already allocated as part of branch
7225 // ...but we need to alloc it in case something jumps here
7227 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7229 current.u=branch_unneeded_reg[i-1];
7231 current.u&=~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7233 struct regstat temp;
7234 memcpy(&temp,¤t,sizeof(current));
7235 temp.wasdirty=temp.dirty;
7236 // TODO: Take into account unconditional branches, as below
7237 delayslot_alloc(&temp,i);
7238 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7239 regs[i].wasdirty=temp.wasdirty;
7240 regs[i].dirty=temp.dirty;
7244 // Create entry (branch target) regmap
7245 for(hr=0;hr<HOST_REGS;hr++)
7247 int r=temp.regmap[hr];
7249 if(r!=regmap_pre[i][hr]) {
7250 regs[i].regmap_entry[hr]=-1;
7255 if((current.u>>r)&1) {
7256 regs[i].regmap_entry[hr]=-1;
7257 regs[i].regmap[hr]=-1;
7258 //Don't clear regs in the delay slot as the branch might need them
7259 //current.regmap[hr]=-1;
7261 regs[i].regmap_entry[hr]=r;
7264 // First instruction expects CCREG to be allocated
7265 if(i==0&&hr==HOST_CCREG)
7266 regs[i].regmap_entry[hr]=CCREG;
7268 regs[i].regmap_entry[hr]=-1;
7272 else { // Not delay slot
7273 switch(dops[i].itype) {
7275 //current.isconst=0; // DEBUG
7276 //current.wasconst=0; // DEBUG
7277 //regs[i].wasconst=0; // DEBUG
7278 clear_const(¤t,dops[i].rt1);
7279 alloc_cc(¤t,i);
7280 dirty_reg(¤t,CCREG);
7281 if (dops[i].rt1==31) {
7282 alloc_reg(¤t,i,31);
7283 dirty_reg(¤t,31);
7284 //assert(dops[i+1].rs1!=31&&dops[i+1].rs2!=31);
7285 //assert(dops[i+1].rt1!=dops[i].rt1);
7287 alloc_reg(¤t,i,PTEMP);
7291 delayslot_alloc(¤t,i+1);
7292 //current.isconst=0; // DEBUG
7294 //printf("i=%d, isconst=%x\n",i,current.isconst);
7297 //current.isconst=0;
7298 //current.wasconst=0;
7299 //regs[i].wasconst=0;
7300 clear_const(¤t,dops[i].rs1);
7301 clear_const(¤t,dops[i].rt1);
7302 alloc_cc(¤t,i);
7303 dirty_reg(¤t,CCREG);
7304 if (!ds_writes_rjump_rs(i)) {
7305 alloc_reg(¤t,i,dops[i].rs1);
7306 if (dops[i].rt1!=0) {
7307 alloc_reg(¤t,i,dops[i].rt1);
7308 dirty_reg(¤t,dops[i].rt1);
7309 assert(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt1);
7310 assert(dops[i+1].rt1!=dops[i].rt1);
7312 alloc_reg(¤t,i,PTEMP);
7316 if(dops[i].rs1==31) { // JALR
7317 alloc_reg(¤t,i,RHASH);
7318 alloc_reg(¤t,i,RHTBL);
7321 delayslot_alloc(¤t,i+1);
7323 // The delay slot overwrites our source register,
7324 // allocate a temporary register to hold the old value.
7328 delayslot_alloc(¤t,i+1);
7330 alloc_reg(¤t,i,RTEMP);
7332 //current.isconst=0; // DEBUG
7337 //current.isconst=0;
7338 //current.wasconst=0;
7339 //regs[i].wasconst=0;
7340 clear_const(¤t,dops[i].rs1);
7341 clear_const(¤t,dops[i].rs2);
7342 if((dops[i].opcode&0x3E)==4) // BEQ/BNE
7344 alloc_cc(¤t,i);
7345 dirty_reg(¤t,CCREG);
7346 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7347 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7348 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2))||
7349 (dops[i].rs2&&(dops[i].rs2==dops[i+1].rt1||dops[i].rs2==dops[i+1].rt2))) {
7350 // The delay slot overwrites one of our conditions.
7351 // Allocate the branch condition registers instead.
7355 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7356 if(dops[i].rs2) alloc_reg(¤t,i,dops[i].rs2);
7361 delayslot_alloc(¤t,i+1);
7365 if((dops[i].opcode&0x3E)==6) // BLEZ/BGTZ
7367 alloc_cc(¤t,i);
7368 dirty_reg(¤t,CCREG);
7369 alloc_reg(¤t,i,dops[i].rs1);
7370 if(dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) {
7371 // The delay slot overwrites one of our conditions.
7372 // Allocate the branch condition registers instead.
7376 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7381 delayslot_alloc(¤t,i+1);
7385 // Don't alloc the delay slot yet because we might not execute it
7386 if((dops[i].opcode&0x3E)==0x14) // BEQL/BNEL
7391 alloc_cc(¤t,i);
7392 dirty_reg(¤t,CCREG);
7393 alloc_reg(¤t,i,dops[i].rs1);
7394 alloc_reg(¤t,i,dops[i].rs2);
7397 if((dops[i].opcode&0x3E)==0x16) // BLEZL/BGTZL
7402 alloc_cc(¤t,i);
7403 dirty_reg(¤t,CCREG);
7404 alloc_reg(¤t,i,dops[i].rs1);
7407 //current.isconst=0;
7410 //current.isconst=0;
7411 //current.wasconst=0;
7412 //regs[i].wasconst=0;
7413 clear_const(¤t,dops[i].rs1);
7414 clear_const(¤t,dops[i].rt1);
7415 //if((dops[i].opcode2&0x1E)==0x0) // BLTZ/BGEZ
7416 if((dops[i].opcode2&0x0E)==0x0) // BLTZ/BGEZ
7418 alloc_cc(¤t,i);
7419 dirty_reg(¤t,CCREG);
7420 alloc_reg(¤t,i,dops[i].rs1);
7421 if (dops[i].rt1==31) { // BLTZAL/BGEZAL
7422 alloc_reg(¤t,i,31);
7423 dirty_reg(¤t,31);
7424 //#ifdef REG_PREFETCH
7425 //alloc_reg(¤t,i,PTEMP);
7428 if((dops[i].rs1&&(dops[i].rs1==dops[i+1].rt1||dops[i].rs1==dops[i+1].rt2)) // The delay slot overwrites the branch condition.
7429 ||(dops[i].rt1==31&&(dops[i+1].rs1==31||dops[i+1].rs2==31||dops[i+1].rt1==31||dops[i+1].rt2==31))) { // DS touches $ra
7430 // Allocate the branch condition registers instead.
7434 if(dops[i].rs1) alloc_reg(¤t,i,dops[i].rs1);
7439 delayslot_alloc(¤t,i+1);
7443 // Don't alloc the delay slot yet because we might not execute it
7444 if((dops[i].opcode2&0x1E)==0x2) // BLTZL/BGEZL
7449 alloc_cc(¤t,i);
7450 dirty_reg(¤t,CCREG);
7451 alloc_reg(¤t,i,dops[i].rs1);
7454 //current.isconst=0;
7457 imm16_alloc(¤t,i);
7461 load_alloc(¤t,i);
7465 store_alloc(¤t,i);
7468 alu_alloc(¤t,i);
7471 shift_alloc(¤t,i);
7474 multdiv_alloc(¤t,i);
7477 shiftimm_alloc(¤t,i);
7480 mov_alloc(¤t,i);
7483 cop0_alloc(¤t,i);
7488 cop2_alloc(¤t,i);
7491 c1ls_alloc(¤t,i);
7494 c2ls_alloc(¤t,i);
7497 c2op_alloc(¤t,i);
7502 syscall_alloc(¤t,i);
7506 // Create entry (branch target) regmap
7507 for(hr=0;hr<HOST_REGS;hr++)
7510 r=current.regmap[hr];
7512 if(r!=regmap_pre[i][hr]) {
7513 // TODO: delay slot (?)
7514 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
7515 if(or<0||r>=TEMPREG){
7516 regs[i].regmap_entry[hr]=-1;
7520 // Just move it to a different register
7521 regs[i].regmap_entry[hr]=r;
7522 // If it was dirty before, it's still dirty
7523 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r);
7530 regs[i].regmap_entry[hr]=0;
7535 if((current.u>>r)&1) {
7536 regs[i].regmap_entry[hr]=-1;
7537 //regs[i].regmap[hr]=-1;
7538 current.regmap[hr]=-1;
7540 regs[i].regmap_entry[hr]=r;
7544 // Branches expect CCREG to be allocated at the target
7545 if(regmap_pre[i][hr]==CCREG)
7546 regs[i].regmap_entry[hr]=CCREG;
7548 regs[i].regmap_entry[hr]=-1;
7551 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
7554 if(i>0&&(dops[i-1].itype==STORE||dops[i-1].itype==STORELR||(dops[i-1].itype==C2LS&&dops[i-1].opcode==0x3a))&&(u_int)imm[i-1]<0x800)
7555 current.waswritten|=1<<dops[i-1].rs1;
7556 current.waswritten&=~(1<<dops[i].rt1);
7557 current.waswritten&=~(1<<dops[i].rt2);
7558 if((dops[i].itype==STORE||dops[i].itype==STORELR||(dops[i].itype==C2LS&&dops[i].opcode==0x3a))&&(u_int)imm[i]>=0x800)
7559 current.waswritten&=~(1<<dops[i].rs1);
7561 /* Branch post-alloc */
7564 current.wasdirty=current.dirty;
7565 switch(dops[i-1].itype) {
7567 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7568 branch_regs[i-1].isconst=0;
7569 branch_regs[i-1].wasconst=0;
7570 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7571 alloc_cc(&branch_regs[i-1],i-1);
7572 dirty_reg(&branch_regs[i-1],CCREG);
7573 if(dops[i-1].rt1==31) { // JAL
7574 alloc_reg(&branch_regs[i-1],i-1,31);
7575 dirty_reg(&branch_regs[i-1],31);
7577 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7578 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7581 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7582 branch_regs[i-1].isconst=0;
7583 branch_regs[i-1].wasconst=0;
7584 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7585 alloc_cc(&branch_regs[i-1],i-1);
7586 dirty_reg(&branch_regs[i-1],CCREG);
7587 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rs1);
7588 if(dops[i-1].rt1!=0) { // JALR
7589 alloc_reg(&branch_regs[i-1],i-1,dops[i-1].rt1);
7590 dirty_reg(&branch_regs[i-1],dops[i-1].rt1);
7593 if(dops[i-1].rs1==31) { // JALR
7594 alloc_reg(&branch_regs[i-1],i-1,RHASH);
7595 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
7598 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7599 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7602 if((dops[i-1].opcode&0x3E)==4) // BEQ/BNE
7604 alloc_cc(¤t,i-1);
7605 dirty_reg(¤t,CCREG);
7606 if((dops[i-1].rs1&&(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2))||
7607 (dops[i-1].rs2&&(dops[i-1].rs2==dops[i].rt1||dops[i-1].rs2==dops[i].rt2))) {
7608 // The delay slot overwrote one of our conditions
7609 // Delay slot goes after the test (in order)
7610 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7612 delayslot_alloc(¤t,i);
7617 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i-1].rs1)|(1LL<<dops[i-1].rs2));
7618 // Alloc the branch condition registers
7619 if(dops[i-1].rs1) alloc_reg(¤t,i-1,dops[i-1].rs1);
7620 if(dops[i-1].rs2) alloc_reg(¤t,i-1,dops[i-1].rs2);
7622 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7623 branch_regs[i-1].isconst=0;
7624 branch_regs[i-1].wasconst=0;
7625 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7626 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7629 if((dops[i-1].opcode&0x3E)==6) // BLEZ/BGTZ
7631 alloc_cc(¤t,i-1);
7632 dirty_reg(¤t,CCREG);
7633 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7634 // The delay slot overwrote the branch condition
7635 // Delay slot goes after the test (in order)
7636 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7638 delayslot_alloc(¤t,i);
7643 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7644 // Alloc the branch condition register
7645 alloc_reg(¤t,i-1,dops[i-1].rs1);
7647 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7648 branch_regs[i-1].isconst=0;
7649 branch_regs[i-1].wasconst=0;
7650 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7651 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7654 // Alloc the delay slot in case the branch is taken
7655 if((dops[i-1].opcode&0x3E)==0x14) // BEQL/BNEL
7657 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7658 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
7659 alloc_cc(&branch_regs[i-1],i);
7660 dirty_reg(&branch_regs[i-1],CCREG);
7661 delayslot_alloc(&branch_regs[i-1],i);
7662 branch_regs[i-1].isconst=0;
7663 alloc_reg(¤t,i,CCREG); // Not taken path
7664 dirty_reg(¤t,CCREG);
7665 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7668 if((dops[i-1].opcode&0x3E)==0x16) // BLEZL/BGTZL
7670 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7671 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
7672 alloc_cc(&branch_regs[i-1],i);
7673 dirty_reg(&branch_regs[i-1],CCREG);
7674 delayslot_alloc(&branch_regs[i-1],i);
7675 branch_regs[i-1].isconst=0;
7676 alloc_reg(¤t,i,CCREG); // Not taken path
7677 dirty_reg(¤t,CCREG);
7678 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7682 //if((dops[i-1].opcode2&0x1E)==0) // BLTZ/BGEZ
7683 if((dops[i-1].opcode2&0x0E)==0) // BLTZ/BGEZ
7685 alloc_cc(¤t,i-1);
7686 dirty_reg(¤t,CCREG);
7687 if(dops[i-1].rs1==dops[i].rt1||dops[i-1].rs1==dops[i].rt2) {
7688 // The delay slot overwrote the branch condition
7689 // Delay slot goes after the test (in order)
7690 current.u=branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2));
7692 delayslot_alloc(¤t,i);
7697 current.u=branch_unneeded_reg[i-1]&~(1LL<<dops[i-1].rs1);
7698 // Alloc the branch condition register
7699 alloc_reg(¤t,i-1,dops[i-1].rs1);
7701 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7702 branch_regs[i-1].isconst=0;
7703 branch_regs[i-1].wasconst=0;
7704 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
7705 memcpy(constmap[i],constmap[i-1],sizeof(constmap[i]));
7708 // Alloc the delay slot in case the branch is taken
7709 if((dops[i-1].opcode2&0x1E)==2) // BLTZL/BGEZL
7711 memcpy(&branch_regs[i-1],¤t,sizeof(current));
7712 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<dops[i].rs1)|(1LL<<dops[i].rs2)|(1LL<<dops[i].rt1)|(1LL<<dops[i].rt2)))|1;
7713 alloc_cc(&branch_regs[i-1],i);
7714 dirty_reg(&branch_regs[i-1],CCREG);
7715 delayslot_alloc(&branch_regs[i-1],i);
7716 branch_regs[i-1].isconst=0;
7717 alloc_reg(¤t,i,CCREG); // Not taken path
7718 dirty_reg(¤t,CCREG);
7719 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
7721 // FIXME: BLTZAL/BGEZAL
7722 if(dops[i-1].opcode2&0x10) { // BxxZAL
7723 alloc_reg(&branch_regs[i-1],i-1,31);
7724 dirty_reg(&branch_regs[i-1],31);
7729 if (dops[i-1].is_ujump)
7731 if(dops[i-1].rt1==31) // JAL/JALR
7733 // Subroutine call will return here, don't alloc any registers
7735 clear_all_regs(current.regmap);
7736 alloc_reg(¤t,i,CCREG);
7737 dirty_reg(¤t,CCREG);
7741 // Internal branch will jump here, match registers to caller
7743 clear_all_regs(current.regmap);
7744 alloc_reg(¤t,i,CCREG);
7745 dirty_reg(¤t,CCREG);
7748 if(ba[j]==start+i*4+4) {
7749 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
7750 current.dirty=branch_regs[j].dirty;
7755 if(ba[j]==start+i*4+4) {
7756 for(hr=0;hr<HOST_REGS;hr++) {
7757 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
7758 current.regmap[hr]=-1;
7760 current.dirty&=branch_regs[j].dirty;
7769 // Count cycles in between branches
7770 ccadj[i] = CLOCK_ADJUST(cc);
7771 if (i > 0 && (dops[i-1].is_jump || dops[i].itype == SYSCALL || dops[i].itype == HLECALL))
7775 #if !defined(DRC_DBG)
7776 else if(dops[i].itype==C2OP&>e_cycletab[source[i]&0x3f]>2)
7778 // this should really be removed since the real stalls have been implemented,
7779 // but doing so causes sizeable perf regression against the older version
7780 u_int gtec = gte_cycletab[source[i] & 0x3f];
7781 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? gtec/2 : 2;
7783 else if(i>1&&dops[i].itype==STORE&&dops[i-1].itype==STORE&&dops[i-2].itype==STORE&&!dops[i].bt)
7787 else if(dops[i].itype==C2LS)
7789 // same as with C2OP
7790 cc += HACK_ENABLED(NDHACK_NO_STALLS) ? 4 : 2;
7798 if(!dops[i].is_ds) {
7799 regs[i].dirty=current.dirty;
7800 regs[i].isconst=current.isconst;
7801 memcpy(constmap[i],current_constmap,sizeof(constmap[i]));
7803 for(hr=0;hr<HOST_REGS;hr++) {
7804 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
7805 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
7806 regs[i].wasconst&=~(1<<hr);
7810 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
7811 regs[i].waswritten=current.waswritten;
7815 static noinline void pass4_cull_unused_regs(void)
7817 u_int last_needed_regs[4] = {0,0,0,0};
7821 for (i=slen-1;i>=0;i--)
7824 __builtin_prefetch(regs[i-2].regmap);
7827 if(ba[i]<start || ba[i]>=(start+slen*4))
7829 // Branch out of this block, don't need anything
7835 // Need whatever matches the target
7837 int t=(ba[i]-start)>>2;
7838 for(hr=0;hr<HOST_REGS;hr++)
7840 if(regs[i].regmap_entry[hr]>=0) {
7841 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
7845 // Conditional branch may need registers for following instructions
7846 if (!dops[i].is_ujump)
7849 nr |= last_needed_regs[(i+2) & 3];
7850 for(hr=0;hr<HOST_REGS;hr++)
7852 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
7853 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
7857 // Don't need stuff which is overwritten
7858 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7859 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7860 // Merge in delay slot
7861 if (dops[i+1].rt1) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt1);
7862 if (dops[i+1].rt2) nr &= ~get_regm(regs[i].regmap, dops[i+1].rt2);
7863 nr |= get_regm(regmap_pre[i], dops[i+1].rs1);
7864 nr |= get_regm(regmap_pre[i], dops[i+1].rs2);
7865 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs1);
7866 nr |= get_regm(regs[i].regmap_entry, dops[i+1].rs2);
7867 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store)) {
7868 nr |= get_regm(regmap_pre[i], ROREG);
7869 nr |= get_regm(regs[i].regmap_entry, ROREG);
7871 if (dops[i+1].is_store) {
7872 nr |= get_regm(regmap_pre[i], INVCP);
7873 nr |= get_regm(regs[i].regmap_entry, INVCP);
7876 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
7878 // SYSCALL instruction (software interrupt)
7881 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
7883 // ERET instruction (return from interrupt)
7889 for(hr=0;hr<HOST_REGS;hr++) {
7890 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
7891 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
7892 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
7893 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
7897 // Overwritten registers are not needed
7898 if (dops[i].rt1) nr &= ~get_regm(regs[i].regmap, dops[i].rt1);
7899 if (dops[i].rt2) nr &= ~get_regm(regs[i].regmap, dops[i].rt2);
7900 nr &= ~get_regm(regs[i].regmap, FTEMP);
7901 // Source registers are needed
7902 nr |= get_regm(regmap_pre[i], dops[i].rs1);
7903 nr |= get_regm(regmap_pre[i], dops[i].rs2);
7904 nr |= get_regm(regs[i].regmap_entry, dops[i].rs1);
7905 nr |= get_regm(regs[i].regmap_entry, dops[i].rs2);
7906 if (ram_offset && (dops[i].is_load || dops[i].is_store)) {
7907 nr |= get_regm(regmap_pre[i], ROREG);
7908 nr |= get_regm(regs[i].regmap_entry, ROREG);
7910 if (dops[i].is_store) {
7911 nr |= get_regm(regmap_pre[i], INVCP);
7912 nr |= get_regm(regs[i].regmap_entry, INVCP);
7915 if (i > 0 && !dops[i].bt && regs[i].wasdirty)
7916 for(hr=0;hr<HOST_REGS;hr++)
7918 // Don't store a register immediately after writing it,
7919 // may prevent dual-issue.
7920 // But do so if this is a branch target, otherwise we
7921 // might have to load the register before the branch.
7922 if((regs[i].wasdirty>>hr)&1) {
7923 if((regmap_pre[i][hr]>0&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1))) {
7924 if(dops[i-1].rt1==regmap_pre[i][hr]) nr|=1<<hr;
7925 if(dops[i-1].rt2==regmap_pre[i][hr]) nr|=1<<hr;
7927 if((regs[i].regmap_entry[hr]>0&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1))) {
7928 if(dops[i-1].rt1==regs[i].regmap_entry[hr]) nr|=1<<hr;
7929 if(dops[i-1].rt2==regs[i].regmap_entry[hr]) nr|=1<<hr;
7933 // Cycle count is needed at branches. Assume it is needed at the target too.
7934 if(i==0||dops[i].bt||dops[i].itype==CJUMP) {
7935 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7936 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
7939 last_needed_regs[i & 3] = nr;
7941 // Deallocate unneeded registers
7942 for(hr=0;hr<HOST_REGS;hr++)
7945 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
7948 int map1 = 0, map2 = 0, temp = 0; // or -1 ??
7949 if (dops[i+1].is_load || dops[i+1].is_store)
7951 if (dops[i+1].is_store)
7953 if(dops[i+1].itype==LOADLR || dops[i+1].itype==STORELR || dops[i+1].itype==C2LS)
7955 if(regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
7956 regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
7957 regs[i].regmap[hr]!=dops[i+1].rt1 && regs[i].regmap[hr]!=dops[i+1].rt2 &&
7958 regs[i].regmap[hr]!=dops[i+1].rs1 && regs[i].regmap[hr]!=dops[i+1].rs2 &&
7959 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=PTEMP &&
7960 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
7961 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
7962 regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2)
7964 regs[i].regmap[hr]=-1;
7965 regs[i].isconst&=~(1<<hr);
7966 regs[i].dirty&=~(1<<hr);
7967 regs[i+1].wasdirty&=~(1<<hr);
7968 if(branch_regs[i].regmap[hr]!=dops[i].rs1 && branch_regs[i].regmap[hr]!=dops[i].rs2 &&
7969 branch_regs[i].regmap[hr]!=dops[i].rt1 && branch_regs[i].regmap[hr]!=dops[i].rt2 &&
7970 branch_regs[i].regmap[hr]!=dops[i+1].rt1 && branch_regs[i].regmap[hr]!=dops[i+1].rt2 &&
7971 branch_regs[i].regmap[hr]!=dops[i+1].rs1 && branch_regs[i].regmap[hr]!=dops[i+1].rs2 &&
7972 branch_regs[i].regmap[hr]!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
7973 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
7974 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
7975 branch_regs[i].regmap[hr]!=map1 && branch_regs[i].regmap[hr]!=map2)
7977 branch_regs[i].regmap[hr]=-1;
7978 branch_regs[i].regmap_entry[hr]=-1;
7979 if (!dops[i].is_ujump)
7982 regmap_pre[i+2][hr]=-1;
7983 regs[i+2].wasconst&=~(1<<hr);
7994 int map1 = -1, map2 = -1, temp=-1;
7995 if (dops[i].is_load || dops[i].is_store)
7997 if (dops[i].is_store)
7999 if (dops[i].itype==LOADLR || dops[i].itype==STORELR || dops[i].itype==C2LS)
8001 if(regs[i].regmap[hr]!=dops[i].rt1 && regs[i].regmap[hr]!=dops[i].rt2 &&
8002 regs[i].regmap[hr]!=dops[i].rs1 && regs[i].regmap[hr]!=dops[i].rs2 &&
8003 regs[i].regmap[hr]!=temp && regs[i].regmap[hr]!=map1 && regs[i].regmap[hr]!=map2 &&
8004 //(dops[i].itype!=SPAN||regs[i].regmap[hr]!=CCREG)
8005 regs[i].regmap[hr] != CCREG)
8007 if(i<slen-1&&!dops[i].is_ds) {
8008 assert(regs[i].regmap[hr]<64);
8009 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]>0)
8010 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8012 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
8013 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
8015 regmap_pre[i+1][hr]=-1;
8016 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
8017 regs[i+1].wasconst&=~(1<<hr);
8019 regs[i].regmap[hr]=-1;
8020 regs[i].isconst&=~(1<<hr);
8021 regs[i].dirty&=~(1<<hr);
8022 regs[i+1].wasdirty&=~(1<<hr);
8031 // If a register is allocated during a loop, try to allocate it for the
8032 // entire loop, if possible. This avoids loading/storing registers
8033 // inside of the loop.
8034 static noinline void pass5a_preallocate1(void)
8037 signed char f_regmap[HOST_REGS];
8038 clear_all_regs(f_regmap);
8039 for(i=0;i<slen-1;i++)
8041 if(dops[i].itype==UJUMP||dops[i].itype==CJUMP||dops[i].itype==SJUMP)
8043 if(ba[i]>=start && ba[i]<(start+i*4))
8044 if(dops[i+1].itype==NOP||dops[i+1].itype==MOV||dops[i+1].itype==ALU
8045 ||dops[i+1].itype==SHIFTIMM||dops[i+1].itype==IMM16||dops[i+1].itype==LOAD
8046 ||dops[i+1].itype==STORE||dops[i+1].itype==STORELR||dops[i+1].itype==C1LS
8047 ||dops[i+1].itype==SHIFT||dops[i+1].itype==COP1
8048 ||dops[i+1].itype==COP2||dops[i+1].itype==C2LS||dops[i+1].itype==C2OP)
8050 int t=(ba[i]-start)>>2;
8051 if(t > 0 && !dops[t-1].is_jump) // loop_preload can't handle jumps into delay slots
8052 if(t<2||(dops[t-2].itype!=UJUMP&&dops[t-2].itype!=RJUMP)||dops[t-2].rt1!=31) // call/ret assumes no registers allocated
8053 for(hr=0;hr<HOST_REGS;hr++)
8055 if(regs[i].regmap[hr]>=0) {
8056 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8057 // dealloc old register
8059 for(n=0;n<HOST_REGS;n++)
8061 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8063 // and alloc new one
8064 f_regmap[hr]=regs[i].regmap[hr];
8067 if(branch_regs[i].regmap[hr]>=0) {
8068 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
8069 // dealloc old register
8071 for(n=0;n<HOST_REGS;n++)
8073 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
8075 // and alloc new one
8076 f_regmap[hr]=branch_regs[i].regmap[hr];
8080 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
8081 f_regmap[hr]=branch_regs[i].regmap[hr];
8083 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
8084 f_regmap[hr]=branch_regs[i].regmap[hr];
8086 // Avoid dirty->clean transition
8087 #ifdef DESTRUCTIVE_WRITEBACK
8088 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
8090 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
8091 // case above, however it's always a good idea. We can't hoist the
8092 // load if the register was already allocated, so there's no point
8093 // wasting time analyzing most of these cases. It only "succeeds"
8094 // when the mapping was different and the load can be replaced with
8095 // a mov, which is of negligible benefit. So such cases are
8097 if(f_regmap[hr]>0) {
8098 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
8102 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8103 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
8105 if(regs[j].regmap[hr]==f_regmap[hr]&&f_regmap[hr]<TEMPREG) {
8106 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
8108 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
8109 if(get_reg(regs[i].regmap,f_regmap[hr])>=0) break;
8110 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
8112 while(k>1&®s[k-1].regmap[hr]==-1) {
8113 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8114 //printf("no free regs for store %x\n",start+(k-1)*4);
8117 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
8118 //printf("no-match due to different register\n");
8121 if (dops[k-2].is_jump) {
8122 //printf("no-match due to branch\n");
8125 // call/ret fast path assumes no registers allocated
8126 if(k>2&&(dops[k-3].itype==UJUMP||dops[k-3].itype==RJUMP)&&dops[k-3].rt1==31) {
8131 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
8132 //printf("Extend r%d, %x ->\n",hr,start+k*4);
8134 regs[k].regmap_entry[hr]=f_regmap[hr];
8135 regs[k].regmap[hr]=f_regmap[hr];
8136 regmap_pre[k+1][hr]=f_regmap[hr];
8137 regs[k].wasdirty&=~(1<<hr);
8138 regs[k].dirty&=~(1<<hr);
8139 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
8140 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
8141 regs[k].wasconst&=~(1<<hr);
8142 regs[k].isconst&=~(1<<hr);
8147 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
8150 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
8151 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
8152 //printf("OK fill %x (r%d)\n",start+i*4,hr);
8153 regs[i].regmap_entry[hr]=f_regmap[hr];
8154 regs[i].regmap[hr]=f_regmap[hr];
8155 regs[i].wasdirty&=~(1<<hr);
8156 regs[i].dirty&=~(1<<hr);
8157 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
8158 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
8159 regs[i].wasconst&=~(1<<hr);
8160 regs[i].isconst&=~(1<<hr);
8161 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
8162 branch_regs[i].wasdirty&=~(1<<hr);
8163 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
8164 branch_regs[i].regmap[hr]=f_regmap[hr];
8165 branch_regs[i].dirty&=~(1<<hr);
8166 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
8167 branch_regs[i].wasconst&=~(1<<hr);
8168 branch_regs[i].isconst&=~(1<<hr);
8169 if (!dops[i].is_ujump) {
8170 regmap_pre[i+2][hr]=f_regmap[hr];
8171 regs[i+2].wasdirty&=~(1<<hr);
8172 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
8177 // Alloc register clean at beginning of loop,
8178 // but may dirty it in pass 6
8179 regs[k].regmap_entry[hr]=f_regmap[hr];
8180 regs[k].regmap[hr]=f_regmap[hr];
8181 regs[k].dirty&=~(1<<hr);
8182 regs[k].wasconst&=~(1<<hr);
8183 regs[k].isconst&=~(1<<hr);
8184 if (dops[k].is_jump) {
8185 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
8186 branch_regs[k].regmap[hr]=f_regmap[hr];
8187 branch_regs[k].dirty&=~(1<<hr);
8188 branch_regs[k].wasconst&=~(1<<hr);
8189 branch_regs[k].isconst&=~(1<<hr);
8190 if (!dops[k].is_ujump) {
8191 regmap_pre[k+2][hr]=f_regmap[hr];
8192 regs[k+2].wasdirty&=~(1<<hr);
8197 regmap_pre[k+1][hr]=f_regmap[hr];
8198 regs[k+1].wasdirty&=~(1<<hr);
8201 if(regs[j].regmap[hr]==f_regmap[hr])
8202 regs[j].regmap_entry[hr]=f_regmap[hr];
8206 if(regs[j].regmap[hr]>=0)
8208 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
8209 //printf("no-match due to different register\n");
8212 if (dops[j].is_ujump)
8214 // Stop on unconditional branch
8217 if(dops[j].itype==CJUMP||dops[j].itype==SJUMP)
8220 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
8223 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
8226 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
8227 //printf("no-match due to different register (branch)\n");
8231 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8232 //printf("No free regs for store %x\n",start+j*4);
8235 assert(f_regmap[hr]<64);
8242 // Non branch or undetermined branch target
8243 for(hr=0;hr<HOST_REGS;hr++)
8245 if(hr!=EXCLUDE_REG) {
8246 if(regs[i].regmap[hr]>=0) {
8247 if(f_regmap[hr]!=regs[i].regmap[hr]) {
8248 // dealloc old register
8250 for(n=0;n<HOST_REGS;n++)
8252 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
8254 // and alloc new one
8255 f_regmap[hr]=regs[i].regmap[hr];
8260 // Try to restore cycle count at branch targets
8262 for(j=i;j<slen-1;j++) {
8263 if(regs[j].regmap[HOST_CCREG]!=-1) break;
8264 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
8265 //printf("no free regs for store %x\n",start+j*4);
8269 if(regs[j].regmap[HOST_CCREG]==CCREG) {
8271 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
8273 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8274 regs[k].regmap[HOST_CCREG]=CCREG;
8275 regmap_pre[k+1][HOST_CCREG]=CCREG;
8276 regs[k+1].wasdirty|=1<<HOST_CCREG;
8277 regs[k].dirty|=1<<HOST_CCREG;
8278 regs[k].wasconst&=~(1<<HOST_CCREG);
8279 regs[k].isconst&=~(1<<HOST_CCREG);
8282 regs[j].regmap_entry[HOST_CCREG]=CCREG;
8284 // Work backwards from the branch target
8285 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
8287 //printf("Extend backwards\n");
8290 while(regs[k-1].regmap[HOST_CCREG]==-1) {
8291 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
8292 //printf("no free regs for store %x\n",start+(k-1)*4);
8297 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
8298 //printf("Extend CC, %x ->\n",start+k*4);
8300 regs[k].regmap_entry[HOST_CCREG]=CCREG;
8301 regs[k].regmap[HOST_CCREG]=CCREG;
8302 regmap_pre[k+1][HOST_CCREG]=CCREG;
8303 regs[k+1].wasdirty|=1<<HOST_CCREG;
8304 regs[k].dirty|=1<<HOST_CCREG;
8305 regs[k].wasconst&=~(1<<HOST_CCREG);
8306 regs[k].isconst&=~(1<<HOST_CCREG);
8311 //printf("Fail Extend CC, %x ->\n",start+k*4);
8315 if(dops[i].itype!=STORE&&dops[i].itype!=STORELR&&dops[i].itype!=C1LS&&dops[i].itype!=SHIFT&&
8316 dops[i].itype!=NOP&&dops[i].itype!=MOV&&dops[i].itype!=ALU&&dops[i].itype!=SHIFTIMM&&
8317 dops[i].itype!=IMM16&&dops[i].itype!=LOAD&&dops[i].itype!=COP1)
8319 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
8325 // This allocates registers (if possible) one instruction prior
8326 // to use, which can avoid a load-use penalty on certain CPUs.
8327 static noinline void pass5b_preallocate2(void)
8330 for(i=0;i<slen-1;i++)
8332 if (!i || !dops[i-1].is_jump)
8336 if(dops[i].itype==ALU||dops[i].itype==MOV||dops[i].itype==LOAD||dops[i].itype==SHIFTIMM||dops[i].itype==IMM16
8337 ||((dops[i].itype==COP1||dops[i].itype==COP2)&&dops[i].opcode2<3))
8340 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs1))>=0)
8342 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8344 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8345 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8346 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8347 regs[i].isconst&=~(1<<hr);
8348 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8349 constmap[i][hr]=constmap[i+1][hr];
8350 regs[i+1].wasdirty&=~(1<<hr);
8351 regs[i].dirty&=~(1<<hr);
8356 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rs2))>=0)
8358 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8360 regs[i].regmap[hr]=regs[i+1].regmap[hr];
8361 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
8362 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
8363 regs[i].isconst&=~(1<<hr);
8364 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8365 constmap[i][hr]=constmap[i+1][hr];
8366 regs[i+1].wasdirty&=~(1<<hr);
8367 regs[i].dirty&=~(1<<hr);
8371 // Preload target address for load instruction (non-constant)
8372 if(dops[i+1].itype==LOAD&&dops[i+1].rs1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8373 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8375 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8377 regs[i].regmap[hr]=dops[i+1].rs1;
8378 regmap_pre[i+1][hr]=dops[i+1].rs1;
8379 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8380 regs[i].isconst&=~(1<<hr);
8381 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8382 constmap[i][hr]=constmap[i+1][hr];
8383 regs[i+1].wasdirty&=~(1<<hr);
8384 regs[i].dirty&=~(1<<hr);
8388 // Load source into target register
8389 if(dops[i+1].use_lt1&&get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8390 if((hr=get_reg(regs[i+1].regmap,dops[i+1].rt1))>=0)
8392 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8394 regs[i].regmap[hr]=dops[i+1].rs1;
8395 regmap_pre[i+1][hr]=dops[i+1].rs1;
8396 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8397 regs[i].isconst&=~(1<<hr);
8398 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8399 constmap[i][hr]=constmap[i+1][hr];
8400 regs[i+1].wasdirty&=~(1<<hr);
8401 regs[i].dirty&=~(1<<hr);
8405 // Address for store instruction (non-constant)
8406 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR
8407 ||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
8408 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8409 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
8410 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8412 regs[i+1].regmap[hr]=AGEN1+((i+1)&1);
8413 regs[i+1].isconst&=~(1<<hr);
8416 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8418 regs[i].regmap[hr]=dops[i+1].rs1;
8419 regmap_pre[i+1][hr]=dops[i+1].rs1;
8420 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8421 regs[i].isconst&=~(1<<hr);
8422 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8423 constmap[i][hr]=constmap[i+1][hr];
8424 regs[i+1].wasdirty&=~(1<<hr);
8425 regs[i].dirty&=~(1<<hr);
8429 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
8430 if(get_reg(regs[i+1].regmap,dops[i+1].rs1)<0) {
8432 hr=get_reg(regs[i+1].regmap,FTEMP);
8434 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
8436 regs[i].regmap[hr]=dops[i+1].rs1;
8437 regmap_pre[i+1][hr]=dops[i+1].rs1;
8438 regs[i+1].regmap_entry[hr]=dops[i+1].rs1;
8439 regs[i].isconst&=~(1<<hr);
8440 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
8441 constmap[i][hr]=constmap[i+1][hr];
8442 regs[i+1].wasdirty&=~(1<<hr);
8443 regs[i].dirty&=~(1<<hr);
8445 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
8447 // move it to another register
8448 regs[i+1].regmap[hr]=-1;
8449 regmap_pre[i+2][hr]=-1;
8450 regs[i+1].regmap[nr]=FTEMP;
8451 regmap_pre[i+2][nr]=FTEMP;
8452 regs[i].regmap[nr]=dops[i+1].rs1;
8453 regmap_pre[i+1][nr]=dops[i+1].rs1;
8454 regs[i+1].regmap_entry[nr]=dops[i+1].rs1;
8455 regs[i].isconst&=~(1<<nr);
8456 regs[i+1].isconst&=~(1<<nr);
8457 regs[i].dirty&=~(1<<nr);
8458 regs[i+1].wasdirty&=~(1<<nr);
8459 regs[i+1].dirty&=~(1<<nr);
8460 regs[i+2].wasdirty&=~(1<<nr);
8464 if(dops[i+1].itype==LOAD||dops[i+1].itype==LOADLR||dops[i+1].itype==STORE||dops[i+1].itype==STORELR/*||dops[i+1].itype==C1LS||||dops[i+1].itype==C2LS*/) {
8466 if(dops[i+1].itype==LOAD)
8467 hr=get_reg(regs[i+1].regmap,dops[i+1].rt1);
8468 if(dops[i+1].itype==LOADLR||(dops[i+1].opcode&0x3b)==0x31||(dops[i+1].opcode&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
8469 hr=get_reg(regs[i+1].regmap,FTEMP);
8470 if(dops[i+1].itype==STORE||dops[i+1].itype==STORELR||(dops[i+1].opcode&0x3b)==0x39||(dops[i+1].opcode&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
8471 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
8472 if(hr<0) hr=get_reg_temp(regs[i+1].regmap);
8474 if(hr>=0&®s[i].regmap[hr]<0) {
8475 int rs=get_reg(regs[i+1].regmap,dops[i+1].rs1);
8476 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
8477 regs[i].regmap[hr]=AGEN1+((i+1)&1);
8478 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
8479 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
8480 regs[i].isconst&=~(1<<hr);
8481 regs[i+1].wasdirty&=~(1<<hr);
8482 regs[i].dirty&=~(1<<hr);
8492 // Write back dirty registers as soon as we will no longer modify them,
8493 // so that we don't end up with lots of writes at the branches.
8494 static noinline void pass6_clean_registers(int istart, int iend, int wr)
8496 static u_int wont_dirty[MAXBLOCK];
8497 static u_int will_dirty[MAXBLOCK];
8500 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
8501 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
8503 will_dirty_i=will_dirty_next=0;
8504 wont_dirty_i=wont_dirty_next=0;
8506 will_dirty_i=will_dirty_next=will_dirty[iend+1];
8507 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
8509 for (i=iend;i>=istart;i--)
8511 signed char rregmap_i[RRMAP_SIZE];
8512 u_int hr_candirty = 0;
8513 assert(HOST_REGS < 32);
8514 make_rregs(regs[i].regmap, rregmap_i, &hr_candirty);
8515 __builtin_prefetch(regs[i-1].regmap);
8518 signed char branch_rregmap_i[RRMAP_SIZE];
8519 u_int branch_hr_candirty = 0;
8520 make_rregs(branch_regs[i].regmap, branch_rregmap_i, &branch_hr_candirty);
8521 if(ba[i]<start || ba[i]>=(start+slen*4))
8523 // Branch out of this block, flush all regs
8525 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8526 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8527 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8528 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8529 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8530 will_dirty_i &= branch_hr_candirty;
8531 if (dops[i].is_ujump)
8533 // Unconditional branch
8535 // Merge in delay slot (will dirty)
8536 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8537 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8538 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8539 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8540 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8541 will_dirty_i &= hr_candirty;
8545 // Conditional branch
8546 wont_dirty_i = wont_dirty_next;
8547 // Merge in delay slot (will dirty)
8548 // (the original code had no explanation why these 2 are commented out)
8549 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8550 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8551 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8552 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8553 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8554 will_dirty_i &= hr_candirty;
8556 // Merge in delay slot (wont dirty)
8557 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8558 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8559 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8560 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8561 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8562 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8563 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8564 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8565 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8566 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8567 wont_dirty_i &= ~(1u << 31);
8569 #ifndef DESTRUCTIVE_WRITEBACK
8570 branch_regs[i].dirty&=wont_dirty_i;
8572 branch_regs[i].dirty|=will_dirty_i;
8578 if(ba[i]<=start+i*4) {
8580 if (dops[i].is_ujump)
8582 // Unconditional branch
8585 // Merge in delay slot (will dirty)
8586 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8587 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8588 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8589 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8590 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8591 temp_will_dirty &= branch_hr_candirty;
8592 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8593 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8594 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8595 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8596 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8597 temp_will_dirty &= hr_candirty;
8599 // Conditional branch (not taken case)
8600 temp_will_dirty=will_dirty_next;
8601 temp_wont_dirty=wont_dirty_next;
8602 // Merge in delay slot (will dirty)
8603 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8604 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8605 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8606 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8607 temp_will_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8608 temp_will_dirty &= branch_hr_candirty;
8609 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8610 //temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8611 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8612 temp_will_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8613 temp_will_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8614 temp_will_dirty &= hr_candirty;
8616 // Merge in delay slot (wont dirty)
8617 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8618 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8619 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8620 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8621 temp_wont_dirty |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8622 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8623 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8624 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8625 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8626 temp_wont_dirty |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8627 temp_wont_dirty &= ~(1u << 31);
8628 // Deal with changed mappings
8630 for(r=0;r<HOST_REGS;r++) {
8631 if(r!=EXCLUDE_REG) {
8632 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
8633 temp_will_dirty&=~(1<<r);
8634 temp_wont_dirty&=~(1<<r);
8635 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8636 temp_will_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8637 temp_wont_dirty|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8639 temp_will_dirty|=1<<r;
8640 temp_wont_dirty|=1<<r;
8647 will_dirty[i]=temp_will_dirty;
8648 wont_dirty[i]=temp_wont_dirty;
8649 pass6_clean_registers((ba[i]-start)>>2,i-1,0);
8651 // Limit recursion. It can take an excessive amount
8652 // of time if there are a lot of nested loops.
8653 will_dirty[(ba[i]-start)>>2]=0;
8654 wont_dirty[(ba[i]-start)>>2]=-1;
8659 if (dops[i].is_ujump)
8661 // Unconditional branch
8664 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
8665 for(r=0;r<HOST_REGS;r++) {
8666 if(r!=EXCLUDE_REG) {
8667 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
8668 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
8669 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
8671 if(branch_regs[i].regmap[r]>=0) {
8672 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8673 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>branch_regs[i].regmap[r])&1)<<r;
8678 // Merge in delay slot
8679 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8680 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8681 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8682 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8683 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8684 will_dirty_i &= branch_hr_candirty;
8685 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8686 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8687 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8688 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8689 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8690 will_dirty_i &= hr_candirty;
8692 // Conditional branch
8693 will_dirty_i=will_dirty_next;
8694 wont_dirty_i=wont_dirty_next;
8695 //if(ba[i]>start+i*4) // Disable recursion (for debugging)
8696 for(r=0;r<HOST_REGS;r++) {
8697 if(r!=EXCLUDE_REG) {
8698 signed char target_reg=branch_regs[i].regmap[r];
8699 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
8700 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
8701 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
8703 else if(target_reg>=0) {
8704 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
8705 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>target_reg)&1)<<r;
8709 // Merge in delay slot
8710 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8711 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8712 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8713 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8714 will_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8715 will_dirty_i &= branch_hr_candirty;
8716 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8717 //will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8718 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8719 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8720 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8721 will_dirty_i &= hr_candirty;
8723 // Merge in delay slot (won't dirty)
8724 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8725 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8726 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt1) & 31);
8727 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i+1].rt2) & 31);
8728 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8729 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt1) & 31);
8730 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i].rt2) & 31);
8731 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt1) & 31);
8732 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, dops[i+1].rt2) & 31);
8733 wont_dirty_i |= 1u << (get_rreg(branch_rregmap_i, CCREG) & 31);
8734 wont_dirty_i &= ~(1u << 31);
8736 #ifndef DESTRUCTIVE_WRITEBACK
8737 branch_regs[i].dirty&=wont_dirty_i;
8739 branch_regs[i].dirty|=will_dirty_i;
8744 else if(dops[i].itype==SYSCALL||dops[i].itype==HLECALL||dops[i].itype==INTCALL)
8746 // SYSCALL instruction (software interrupt)
8750 else if(dops[i].itype==COP0 && (source[i]&0x3f)==0x18)
8752 // ERET instruction (return from interrupt)
8756 will_dirty_next=will_dirty_i;
8757 wont_dirty_next=wont_dirty_i;
8758 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8759 will_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8760 will_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8761 will_dirty_i &= hr_candirty;
8762 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt1) & 31);
8763 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i].rt2) & 31);
8764 wont_dirty_i |= 1u << (get_rreg(rregmap_i, CCREG) & 31);
8765 wont_dirty_i &= ~(1u << 31);
8766 if (i > istart && !dops[i].is_jump) {
8767 // Don't store a register immediately after writing it,
8768 // may prevent dual-issue.
8769 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt1) & 31);
8770 wont_dirty_i |= 1u << (get_rreg(rregmap_i, dops[i-1].rt2) & 31);
8773 will_dirty[i]=will_dirty_i;
8774 wont_dirty[i]=wont_dirty_i;
8775 // Mark registers that won't be dirtied as not dirty
8777 regs[i].dirty|=will_dirty_i;
8778 #ifndef DESTRUCTIVE_WRITEBACK
8779 regs[i].dirty&=wont_dirty_i;
8782 if (i < iend-1 && !dops[i].is_ujump) {
8783 for(r=0;r<HOST_REGS;r++) {
8784 if(r!=EXCLUDE_REG) {
8785 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
8786 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
8787 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8795 for(r=0;r<HOST_REGS;r++) {
8796 if(r!=EXCLUDE_REG) {
8797 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
8798 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
8799 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
8806 // Deal with changed mappings
8807 temp_will_dirty=will_dirty_i;
8808 temp_wont_dirty=wont_dirty_i;
8809 for(r=0;r<HOST_REGS;r++) {
8810 if(r!=EXCLUDE_REG) {
8812 if(regs[i].regmap[r]==regmap_pre[i][r]) {
8814 #ifndef DESTRUCTIVE_WRITEBACK
8815 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8817 regs[i].wasdirty|=will_dirty_i&(1<<r);
8820 else if(regmap_pre[i][r]>=0&&(nr=get_rreg(rregmap_i,regmap_pre[i][r]))>=0) {
8821 // Register moved to a different register
8822 will_dirty_i&=~(1<<r);
8823 wont_dirty_i&=~(1<<r);
8824 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
8825 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
8827 #ifndef DESTRUCTIVE_WRITEBACK
8828 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
8830 regs[i].wasdirty|=will_dirty_i&(1<<r);
8834 will_dirty_i&=~(1<<r);
8835 wont_dirty_i&=~(1<<r);
8836 if(regmap_pre[i][r]>0 && regmap_pre[i][r]<34) {
8837 will_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8838 wont_dirty_i|=((unneeded_reg[i]>>regmap_pre[i][r])&1)<<r;
8841 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
8849 static noinline void pass10_expire_blocks(void)
8851 u_int step = MAX_OUTPUT_BLOCK_SIZE / PAGE_COUNT / 2;
8852 // not sizeof(ndrc->translation_cache) due to vita hack
8853 u_int step_mask = ((1u << TARGET_SIZE_2) - 1u) & ~(step - 1u);
8854 u_int end = (out - ndrc->translation_cache + EXPIRITY_OFFSET) & step_mask;
8855 u_int base_shift = __builtin_ctz(MAX_OUTPUT_BLOCK_SIZE);
8858 for (; expirep != end; expirep = ((expirep + step) & step_mask))
8860 u_int base_offs = expirep & ~(MAX_OUTPUT_BLOCK_SIZE - 1);
8861 u_int block_i = expirep / step & (PAGE_COUNT - 1);
8862 u_int phase = (expirep >> (base_shift - 1)) & 1u;
8863 if (!(expirep & (MAX_OUTPUT_BLOCK_SIZE / 2 - 1))) {
8864 inv_debug("EXP: base_offs %x/%x phase %u\n", base_offs,
8865 out - ndrc->translation_cache, phase);
8869 hit = blocks_remove_matching_addrs(&blocks[block_i], base_offs, base_shift);
8873 memset(mini_ht, -1, sizeof(mini_ht));
8878 unlink_jumps_tc_range(jumps[block_i], base_offs, base_shift);
8882 static struct block_info *new_block_info(u_int start, u_int len,
8883 const void *source, const void *copy, u_char *beginning, u_short jump_in_count)
8885 struct block_info **b_pptr;
8886 struct block_info *block;
8887 u_int page = get_page(start);
8889 block = malloc(sizeof(*block) + jump_in_count * sizeof(block->jump_in[0]));
8891 assert(jump_in_count > 0);
8892 block->source = source;
8894 block->start = start;
8896 block->reg_sv_flags = 0;
8897 block->tc_offs = beginning - ndrc->translation_cache;
8898 //block->tc_len = out - beginning;
8899 block->is_dirty = 0;
8900 block->inv_near_misses = 0;
8901 block->jump_in_cnt = jump_in_count;
8903 // insert sorted by start mirror-unmasked vaddr
8904 for (b_pptr = &blocks[page]; ; b_pptr = &((*b_pptr)->next)) {
8905 if (*b_pptr == NULL || (*b_pptr)->start >= start) {
8906 block->next = *b_pptr;
8911 stat_inc(stat_blocks);
8915 static int new_recompile_block(u_int addr)
8917 u_int pagelimit = 0;
8918 u_int state_rflags = 0;
8921 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
8923 // this is just for speculation
8924 for (i = 1; i < 32; i++) {
8925 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8926 state_rflags |= 1 << i;
8929 assert(!(addr & 3));
8931 new_dynarec_did_compile=1;
8932 if (Config.HLE && start == 0x80001000) // hlecall
8934 // XXX: is this enough? Maybe check hleSoftCall?
8935 void *beginning = start_block();
8937 emit_movimm(start,0);
8938 emit_writeword(0,&pcaddr);
8939 emit_far_jump(new_dyna_leave);
8941 end_block(beginning);
8942 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8943 block->jump_in[0].vaddr = start;
8944 block->jump_in[0].addr = beginning;
8947 else if (f1_hack && hack_addr == 0) {
8948 void *beginning = start_block();
8949 emit_movimm(start, 0);
8950 emit_writeword(0, &hack_addr);
8951 emit_readword(&psxRegs.GPR.n.sp, 0);
8952 emit_readptr(&mem_rtab, 1);
8953 emit_shrimm(0, 12, 2);
8954 emit_readptr_dualindexedx_ptrlen(1, 2, 1);
8955 emit_addimm(0, 0x18, 0);
8956 emit_adds_ptr(1, 1, 1);
8957 emit_ldr_dualindexed(1, 0, 0);
8958 emit_writeword(0, &psxRegs.GPR.r[26]); // lw k0, 0x18(sp)
8959 emit_far_call(ndrc_get_addr_ht);
8960 emit_jmpreg(0); // jr k0
8962 end_block(beginning);
8964 struct block_info *block = new_block_info(start, 4, NULL, NULL, beginning, 1);
8965 block->jump_in[0].vaddr = start;
8966 block->jump_in[0].addr = beginning;
8967 SysPrintf("F1 hack to %08x\n", start);
8971 cycle_multiplier_active = cycle_multiplier_override && cycle_multiplier == CYCLE_MULT_DEFAULT
8972 ? cycle_multiplier_override : cycle_multiplier;
8974 source = get_source_start(start, &pagelimit);
8975 if (source == NULL) {
8976 if (addr != hack_addr) {
8977 SysPrintf("Compile at bogus memory address: %08x\n", addr);
8984 /* Pass 1: disassemble */
8985 /* Pass 2: register dependencies, branch targets */
8986 /* Pass 3: register allocation */
8987 /* Pass 4: branch dependencies */
8988 /* Pass 5: pre-alloc */
8989 /* Pass 6: optimize clean/dirty state */
8990 /* Pass 7: flag 32-bit registers */
8991 /* Pass 8: assembly */
8992 /* Pass 9: linker */
8993 /* Pass 10: garbage collection / free memory */
8995 /* Pass 1 disassembly */
8997 pass1_disassemble(pagelimit);
8999 int clear_hack_addr = apply_hacks();
9001 /* Pass 2 - Register dependencies and branch targets */
9003 pass2_unneeded_regs(0,slen-1,0);
9005 /* Pass 3 - Register allocation */
9007 pass3_register_alloc(addr);
9009 /* Pass 4 - Cull unused host registers */
9011 pass4_cull_unused_regs();
9013 /* Pass 5 - Pre-allocate registers */
9015 pass5a_preallocate1();
9016 pass5b_preallocate2();
9018 /* Pass 6 - Optimize clean/dirty state */
9019 pass6_clean_registers(0, slen-1, 1);
9021 /* Pass 7 - Identify 32-bit registers */
9022 for (i=slen-1;i>=0;i--)
9024 if(dops[i].itype==CJUMP||dops[i].itype==SJUMP)
9026 // Conditional branch
9027 if((source[i]>>16)!=0x1000&&i<slen-2) {
9028 // Mark this address as a branch target since it may be called
9029 // upon return from interrupt
9035 /* Pass 8 - Assembly */
9036 linkcount=0;stubcount=0;
9039 void *beginning=start_block();
9040 void *instr_addr0_override = NULL;
9043 if (start == 0x80030000) {
9044 // nasty hack for the fastbios thing
9045 // override block entry to this code
9046 instr_addr0_override = out;
9047 emit_movimm(start,0);
9048 // abuse io address var as a flag that we
9049 // have already returned here once
9050 emit_readword(&address,1);
9051 emit_writeword(0,&pcaddr);
9052 emit_writeword(0,&address);
9055 emit_jeq(out + 4*2);
9056 emit_far_jump(new_dyna_leave);
9058 emit_jne(new_dyna_leave);
9063 __builtin_prefetch(regs[i+1].regmap);
9064 check_regmap(regmap_pre[i]);
9065 check_regmap(regs[i].regmap_entry);
9066 check_regmap(regs[i].regmap);
9067 //if(ds) printf("ds: ");
9068 disassemble_inst(i);
9070 ds=0; // Skip delay slot
9071 if(dops[i].bt) assem_debug("OOPS - branch into delay slot\n");
9072 instr_addr[i] = NULL;
9074 speculate_register_values(i);
9075 #ifndef DESTRUCTIVE_WRITEBACK
9076 if (i < 2 || !dops[i-2].is_ujump)
9078 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,unneeded_reg[i]);
9080 if((dops[i].itype==CJUMP||dops[i].itype==SJUMP)) {
9081 dirty_pre=branch_regs[i].dirty;
9083 dirty_pre=regs[i].dirty;
9087 if (i < 2 || !dops[i-2].is_ujump)
9089 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,unneeded_reg[i]);
9090 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9092 // branch target entry point
9093 instr_addr[i] = out;
9094 assem_debug("<->\n");
9095 drc_dbg_emit_do_cmp(i, ccadj[i]);
9096 if (clear_hack_addr) {
9098 emit_writeword(0, &hack_addr);
9099 clear_hack_addr = 0;
9103 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
9104 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty);
9105 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i].rs1,dops[i].rs2);
9106 address_generation(i,®s[i],regs[i].regmap_entry);
9107 load_consts(regmap_pre[i],regs[i].regmap,i);
9110 // Load the delay slot registers if necessary
9111 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2&&(dops[i+1].rs1!=dops[i].rt1||dops[i].rt1==0))
9112 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9113 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2&&(dops[i+1].rs2!=dops[i].rt1||dops[i].rt1==0))
9114 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9115 if (ram_offset && (dops[i+1].is_load || dops[i+1].is_store))
9116 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9117 if (dops[i+1].is_store)
9118 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9122 // Preload registers for following instruction
9123 if(dops[i+1].rs1!=dops[i].rs1&&dops[i+1].rs1!=dops[i].rs2)
9124 if(dops[i+1].rs1!=dops[i].rt1&&dops[i+1].rs1!=dops[i].rt2)
9125 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs1,dops[i+1].rs1);
9126 if(dops[i+1].rs2!=dops[i+1].rs1&&dops[i+1].rs2!=dops[i].rs1&&dops[i+1].rs2!=dops[i].rs2)
9127 if(dops[i+1].rs2!=dops[i].rt1&&dops[i+1].rs2!=dops[i].rt2)
9128 load_regs(regs[i].regmap_entry,regs[i].regmap,dops[i+1].rs2,dops[i+1].rs2);
9130 // TODO: if(is_ooo(i)) address_generation(i+1);
9131 if (!dops[i].is_jump || dops[i].itype == CJUMP)
9132 load_reg(regs[i].regmap_entry,regs[i].regmap,CCREG);
9133 if (ram_offset && (dops[i].is_load || dops[i].is_store))
9134 load_reg(regs[i].regmap_entry,regs[i].regmap,ROREG);
9135 if (dops[i].is_store)
9136 load_reg(regs[i].regmap_entry,regs[i].regmap,INVCP);
9138 ds = assemble(i, ®s[i], ccadj[i]);
9140 if (dops[i].is_ujump)
9143 literal_pool_jumpover(256);
9148 if (slen > 0 && dops[slen-1].itype == INTCALL) {
9149 // no ending needed for this block since INTCALL never returns
9151 // If the block did not end with an unconditional branch,
9152 // add a jump to the next instruction.
9154 if (!dops[i-2].is_ujump) {
9155 assert(!dops[i-1].is_jump);
9157 if(dops[i-2].itype!=CJUMP&&dops[i-2].itype!=SJUMP) {
9158 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9159 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9160 emit_loadreg(CCREG,HOST_CCREG);
9161 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9165 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].dirty,start+i*4);
9166 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
9168 add_to_linker(out,start+i*4,0);
9175 assert(!dops[i-1].is_jump);
9176 store_regs_bt(regs[i-1].regmap,regs[i-1].dirty,start+i*4);
9177 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
9178 emit_loadreg(CCREG,HOST_CCREG);
9179 emit_addimm(HOST_CCREG, ccadj[i-1] + CLOCK_ADJUST(1), HOST_CCREG);
9180 add_to_linker(out,start+i*4,0);
9184 // TODO: delay slot stubs?
9186 for(i=0;i<stubcount;i++)
9188 switch(stubs[i].type)
9196 do_readstub(i);break;
9201 do_writestub(i);break;
9205 do_invstub(i);break;
9207 do_cop1stub(i);break;
9209 do_unalignedwritestub(i);break;
9213 if (instr_addr0_override)
9214 instr_addr[0] = instr_addr0_override;
9217 /* check for improper expiration */
9218 for (i = 0; i < ARRAY_SIZE(jumps); i++) {
9222 for (j = 0; j < jumps[i]->count; j++)
9223 assert(jumps[i]->e[j].stub < beginning || (u_char *)jumps[i]->e[j].stub > out);
9227 /* Pass 9 - Linker */
9228 for(i=0;i<linkcount;i++)
9230 assem_debug("%p -> %8x\n",link_addr[i].addr,link_addr[i].target);
9232 if (!link_addr[i].internal)
9235 void *addr = check_addr(link_addr[i].target);
9236 emit_extjump(link_addr[i].addr, link_addr[i].target);
9238 set_jump_target(link_addr[i].addr, addr);
9239 ndrc_add_jump_out(link_addr[i].target,stub);
9242 set_jump_target(link_addr[i].addr, stub);
9247 int target=(link_addr[i].target-start)>>2;
9248 assert(target>=0&&target<slen);
9249 assert(instr_addr[target]);
9250 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9251 //set_jump_target_fillslot(link_addr[i].addr,instr_addr[target],link_addr[i].ext>>1);
9253 set_jump_target(link_addr[i].addr, instr_addr[target]);
9258 u_int source_len = slen*4;
9259 if (dops[slen-1].itype == INTCALL && source_len > 4)
9260 // no need to treat the last instruction as compiled
9261 // as interpreter fully handles it
9264 if ((u_char *)copy + source_len > (u_char *)shadow + sizeof(shadow))
9267 // External Branch Targets (jump_in)
9268 int jump_in_count = 1;
9269 assert(instr_addr[0]);
9270 for (i = 1; i < slen; i++)
9272 if (dops[i].bt && instr_addr[i])
9276 struct block_info *block =
9277 new_block_info(start, slen * 4, source, copy, beginning, jump_in_count);
9278 block->reg_sv_flags = state_rflags;
9281 for (i = 0; i < slen; i++)
9283 if ((i == 0 || dops[i].bt) && instr_addr[i])
9285 assem_debug("%p (%d) <- %8x\n", instr_addr[i], i, start + i*4);
9286 u_int vaddr = start + i*4;
9292 entry = instr_addr[i];
9294 emit_jmp(instr_addr[i]);
9296 block->jump_in[jump_in_i].vaddr = vaddr;
9297 block->jump_in[jump_in_i].addr = entry;
9301 assert(jump_in_i == jump_in_count);
9302 hash_table_add(block->jump_in[0].vaddr, block->jump_in[0].addr);
9303 // Write out the literal pool if necessary
9305 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
9307 if(((u_int)out)&7) emit_addnop(13);
9309 assert(out - (u_char *)beginning < MAX_OUTPUT_BLOCK_SIZE);
9310 //printf("shadow buffer: %p-%p\n",copy,(u_char *)copy+slen*4);
9311 memcpy(copy, source, source_len);
9314 end_block(beginning);
9316 // If we're within 256K of the end of the buffer,
9317 // start over from the beginning. (Is 256K enough?)
9318 if (out > ndrc->translation_cache + sizeof(ndrc->translation_cache) - MAX_OUTPUT_BLOCK_SIZE)
9319 out = ndrc->translation_cache;
9321 // Trap writes to any of the pages we compiled
9322 mark_invalid_code(start, slen*4, 0);
9324 /* Pass 10 - Free memory by expiring oldest blocks */
9326 pass10_expire_blocks();
9331 stat_inc(stat_bc_direct);
9335 // vim:shiftwidth=2:expandtab