libpcsxcore/new_dynarec/new_dynarec.c

   1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
   2  *   Mupen64plus - new_dynarec.c                                           *
   3  *   Copyright (C) 2009-2011 Ari64                                         *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.          *
  19  * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
  20
  21 #include <stdlib.h>
  22 #include <stdint.h> //include for uint64_t
  23 #include <assert.h>
  24 #include <errno.h>
  25 #include <sys/mman.h>
  26
  27 #include "emu_if.h" //emulator interface
  28
  29 //#define DISASM
  30 //#define assem_debug printf
  31 //#define inv_debug printf
  32 #define assem_debug(...)
  33 #define inv_debug(...)
  34
  35 #ifdef __i386__
  36 #include "assem_x86.h"
  37 #endif
  38 #ifdef __x86_64__
  39 #include "assem_x64.h"
  40 #endif
  41 #ifdef __arm__
  42 #include "assem_arm.h"
  43 #endif
  44
  45 #ifdef __BLACKBERRY_QNX__
  46 #undef __clear_cache
  47 #define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
  48 #elif defined(__MACH__)
  49 #include <libkern/OSCacheControl.h>
  50 #define __clear_cache mach_clear_cache
  51 static void __clear_cache(void *start, void *end) {
  52   size_t len = (char *)end - (char *)start;
  53   sys_dcache_flush(start, len);
  54   sys_icache_invalidate(start, len);
  55 }
  56 #elif defined(_3DS)
  57 #include "3ds_utils.h"
  58 #define __clear_cache(start,end) ctr_flush_invalidate_cache()
  59 #endif
  60
  61 #define MAXBLOCK 4096
  62 #define MAX_OUTPUT_BLOCK_SIZE 262144
  63
  64 struct regstat
  65 {
  66   signed char regmap_entry[HOST_REGS];
  67   signed char regmap[HOST_REGS];
  68   uint64_t was32;
  69   uint64_t is32;
  70   uint64_t wasdirty;
  71   uint64_t dirty;
  72   uint64_t u;
  73   uint64_t uu;
  74   u_int wasconst;
  75   u_int isconst;
  76   u_int loadedconst;             // host regs that have constants loaded
  77   u_int waswritten;              // MIPS regs that were used as store base before
  78 };
  79
  80 // note: asm depends on this layout
  81 struct ll_entry
  82 {
  83   u_int vaddr;
  84   u_int reg_sv_flags;
  85   void *addr;
  86   struct ll_entry *next;
  87 };
  88
  89   u_int start;
  90   u_int *source;
  91   char insn[MAXBLOCK][10];
  92   u_char itype[MAXBLOCK];
  93   u_char opcode[MAXBLOCK];
  94   u_char opcode2[MAXBLOCK];
  95   u_char bt[MAXBLOCK];
  96   u_char rs1[MAXBLOCK];
  97   u_char rs2[MAXBLOCK];
  98   u_char rt1[MAXBLOCK];
  99   u_char rt2[MAXBLOCK];
 100   u_char us1[MAXBLOCK];
 101   u_char us2[MAXBLOCK];
 102   u_char dep1[MAXBLOCK];
 103   u_char dep2[MAXBLOCK];
 104   u_char lt1[MAXBLOCK];
 105   static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
 106   static uint64_t gte_rt[MAXBLOCK];
 107   static uint64_t gte_unneeded[MAXBLOCK];
 108   static u_int smrv[32]; // speculated MIPS register values
 109   static u_int smrv_strong; // mask or regs that are likely to have correct values
 110   static u_int smrv_weak; // same, but somewhat less likely
 111   static u_int smrv_strong_next; // same, but after current insn executes
 112   static u_int smrv_weak_next;
 113   int imm[MAXBLOCK];
 114   u_int ba[MAXBLOCK];
 115   char likely[MAXBLOCK];
 116   char is_ds[MAXBLOCK];
 117   char ooo[MAXBLOCK];
 118   uint64_t unneeded_reg[MAXBLOCK];
 119   uint64_t unneeded_reg_upper[MAXBLOCK];
 120   uint64_t branch_unneeded_reg[MAXBLOCK];
 121   uint64_t branch_unneeded_reg_upper[MAXBLOCK];
 122   uint64_t p32[MAXBLOCK];
 123   uint64_t pr32[MAXBLOCK];
 124   signed char regmap_pre[MAXBLOCK][HOST_REGS];
 125   static uint64_t current_constmap[HOST_REGS];
 126   static uint64_t constmap[MAXBLOCK][HOST_REGS];
 127   static struct regstat regs[MAXBLOCK];
 128   static struct regstat branch_regs[MAXBLOCK];
 129   signed char minimum_free_regs[MAXBLOCK];
 130   u_int needed_reg[MAXBLOCK];
 131   uint64_t requires_32bit[MAXBLOCK];
 132   u_int wont_dirty[MAXBLOCK];
 133   u_int will_dirty[MAXBLOCK];
 134   int ccadj[MAXBLOCK];
 135   int slen;
 136   u_int instr_addr[MAXBLOCK];
 137   u_int link_addr[MAXBLOCK][3];
 138   int linkcount;
 139   u_int stubs[MAXBLOCK*3][8];
 140   int stubcount;
 141   u_int literals[1024][2];
 142   int literalcount;
 143   int is_delayslot;
 144   int cop1_usable;
 145   u_char *out;
 146   struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
 147   struct ll_entry *jump_out[4096];
 148   struct ll_entry *jump_dirty[4096];
 149   u_int hash_table[65536][4]  __attribute__((aligned(16)));
 150   char shadow[1048576]  __attribute__((aligned(16)));
 151   void *copy;
 152   int expirep;
 153 #ifndef PCSX
 154   u_int using_tlb;
 155 #else
 156   static const u_int using_tlb=0;
 157 #endif
 158   int new_dynarec_did_compile;
 159   int new_dynarec_hacks;
 160   u_int stop_after_jal;
 161 #ifndef RAM_FIXED
 162   static u_int ram_offset;
 163 #else
 164   static const u_int ram_offset=0;
 165 #endif
 166   extern u_char restore_candidate[512];
 167   extern int cycle_count;
 168
 169   /* registers that may be allocated */
 170   /* 1-31 gpr */
 171 #define HIREG 32 // hi
 172 #define LOREG 33 // lo
 173 #define FSREG 34 // FPU status (FCSR)
 174 #define CSREG 35 // Coprocessor status
 175 #define CCREG 36 // Cycle count
 176 #define INVCP 37 // Pointer to invalid_code
 177 #define MMREG 38 // Pointer to memory_map
 178 #define ROREG 39 // ram offset (if rdram!=0x80000000)
 179 #define TEMPREG 40
 180 #define FTEMP 40 // FPU temporary register
 181 #define PTEMP 41 // Prefetch temporary register
 182 #define TLREG 42 // TLB mapping offset
 183 #define RHASH 43 // Return address hash
 184 #define RHTBL 44 // Return address hash table address
 185 #define RTEMP 45 // JR/JALR address register
 186 #define MAXREG 45
 187 #define AGEN1 46 // Address generation temporary register
 188 #define AGEN2 47 // Address generation temporary register
 189 #define MGEN1 48 // Maptable address generation temporary register
 190 #define MGEN2 49 // Maptable address generation temporary register
 191 #define BTREG 50 // Branch target temporary register
 192
 193   /* instruction types */
 194 #define NOP 0     // No operation
 195 #define LOAD 1    // Load
 196 #define STORE 2   // Store
 197 #define LOADLR 3  // Unaligned load
 198 #define STORELR 4 // Unaligned store
 199 #define MOV 5     // Move
 200 #define ALU 6     // Arithmetic/logic
 201 #define MULTDIV 7 // Multiply/divide
 202 #define SHIFT 8   // Shift by register
 203 #define SHIFTIMM 9// Shift by immediate
 204 #define IMM16 10  // 16-bit immediate
 205 #define RJUMP 11  // Unconditional jump to register
 206 #define UJUMP 12  // Unconditional jump
 207 #define CJUMP 13  // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
 208 #define SJUMP 14  // Conditional branch (regimm format)
 209 #define COP0 15   // Coprocessor 0
 210 #define COP1 16   // Coprocessor 1
 211 #define C1LS 17   // Coprocessor 1 load/store
 212 #define FJUMP 18  // Conditional branch (floating point)
 213 #define FLOAT 19  // Floating point unit
 214 #define FCONV 20  // Convert integer to float
 215 #define FCOMP 21  // Floating point compare (sets FSREG)
 216 #define SYSCALL 22// SYSCALL
 217 #define OTHER 23  // Other
 218 #define SPAN 24   // Branch/delay slot spans 2 pages
 219 #define NI 25     // Not implemented
 220 #define HLECALL 26// PCSX fake opcodes for HLE
 221 #define COP2 27   // Coprocessor 2 move
 222 #define C2LS 28   // Coprocessor 2 load/store
 223 #define C2OP 29   // Coprocessor 2 operation
 224 #define INTCALL 30// Call interpreter to handle rare corner cases
 225
 226   /* stubs */
 227 #define CC_STUB 1
 228 #define FP_STUB 2
 229 #define LOADB_STUB 3
 230 #define LOADH_STUB 4
 231 #define LOADW_STUB 5
 232 #define LOADD_STUB 6
 233 #define LOADBU_STUB 7
 234 #define LOADHU_STUB 8
 235 #define STOREB_STUB 9
 236 #define STOREH_STUB 10
 237 #define STOREW_STUB 11
 238 #define STORED_STUB 12
 239 #define STORELR_STUB 13
 240 #define INVCODE_STUB 14
 241
 242   /* branch codes */
 243 #define TAKEN 1
 244 #define NOTTAKEN 2
 245 #define NULLDS 3
 246
 247 // asm linkage
 248 int new_recompile_block(int addr);
 249 void *get_addr_ht(u_int vaddr);
 250 void invalidate_block(u_int block);
 251 void invalidate_addr(u_int addr);
 252 void remove_hash(int vaddr);
 253 void jump_vaddr();
 254 void dyna_linker();
 255 void dyna_linker_ds();
 256 void verify_code();
 257 void verify_code_vm();
 258 void verify_code_ds();
 259 void cc_interrupt();
 260 void fp_exception();
 261 void fp_exception_ds();
 262 void jump_syscall();
 263 void jump_syscall_hle();
 264 void jump_eret();
 265 void jump_hlecall();
 266 void jump_intcall();
 267 void new_dyna_leave();
 268
 269 // TLB
 270 void TLBWI_new();
 271 void TLBWR_new();
 272 void read_nomem_new();
 273 void read_nomemb_new();
 274 void read_nomemh_new();
 275 void read_nomemd_new();
 276 void write_nomem_new();
 277 void write_nomemb_new();
 278 void write_nomemh_new();
 279 void write_nomemd_new();
 280 void write_rdram_new();
 281 void write_rdramb_new();
 282 void write_rdramh_new();
 283 void write_rdramd_new();
 284 extern u_int memory_map[1048576];
 285
 286 // Needed by assembler
 287 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
 288 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
 289 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
 290 void load_all_regs(signed char i_regmap[]);
 291 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
 292 void load_regs_entry(int t);
 293 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
 294
 295 int tracedebug=0;
 296
 297 //#define DEBUG_CYCLE_COUNT 1
 298
 299 #define NO_CYCLE_PENALTY_THR 12
 300
 301 int cycle_multiplier; // 100 for 1.0
 302
 303 static int CLOCK_ADJUST(int x)
 304 {
 305   int s=(x>>31)|1;
 306   return (x * cycle_multiplier + s * 50) / 100;
 307 }
 308
 309 static void tlb_hacks()
 310 {
 311 #ifndef DISABLE_TLB
 312   // Goldeneye hack
 313   if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
 314   {
 315     u_int addr;
 316     int n;
 317     switch (ROM_HEADER->Country_code&0xFF)
 318     {
 319       case 0x45: // U
 320         addr=0x34b30;
 321         break;
 322       case 0x4A: // J
 323         addr=0x34b70;
 324         break;
 325       case 0x50: // E
 326         addr=0x329f0;
 327         break;
 328       default:
 329         // Unknown country code
 330         addr=0;
 331         break;
 332     }
 333     u_int rom_addr=(u_int)rom;
 334     #ifdef ROM_COPY
 335     // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
 336     // in the lower 4G of memory to use this hack.  Copy it if necessary.
 337     if((void *)rom>(void *)0xffffffff) {
 338       munmap(ROM_COPY, 67108864);
 339       if(mmap(ROM_COPY, 12582912,
 340               PROT_READ | PROT_WRITE,
 341               MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
 342               -1, 0) <= 0) {printf("mmap() failed\n");}
 343       memcpy(ROM_COPY,rom,12582912);
 344       rom_addr=(u_int)ROM_COPY;
 345     }
 346     #endif
 347     if(addr) {
 348       for(n=0x7F000;n<0x80000;n++) {
 349         memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
 350       }
 351     }
 352   }
 353 #endif
 354 }
 355
 356 static u_int get_page(u_int vaddr)
 357 {
 358 #ifndef PCSX
 359   u_int page=(vaddr^0x80000000)>>12;
 360 #else
 361   u_int page=vaddr&~0xe0000000;
 362   if (page < 0x1000000)
 363     page &= ~0x0e00000; // RAM mirrors
 364   page>>=12;
 365 #endif
 366 #ifndef DISABLE_TLB
 367   if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
 368 #endif
 369   if(page>2048) page=2048+(page&2047);
 370   return page;
 371 }
 372
 373 #ifndef PCSX
 374 static u_int get_vpage(u_int vaddr)
 375 {
 376   u_int vpage=(vaddr^0x80000000)>>12;
 377 #ifndef DISABLE_TLB
 378   if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
 379 #endif
 380   if(vpage>2048) vpage=2048+(vpage&2047);
 381   return vpage;
 382 }
 383 #else
 384 // no virtual mem in PCSX
 385 static u_int get_vpage(u_int vaddr)
 386 {
 387   return get_page(vaddr);
 388 }
 389 #endif
 390
 391 // Get address from virtual address
 392 // This is called from the recompiled JR/JALR instructions
 393 void *get_addr(u_int vaddr)
 394 {
 395   u_int page=get_page(vaddr);
 396   u_int vpage=get_vpage(vaddr);
 397   struct ll_entry *head;
 398   //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
 399   head=jump_in[page];
 400   while(head!=NULL) {
 401     if(head->vaddr==vaddr) {
 402   //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 403       int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 404       ht_bin[3]=ht_bin[1];
 405       ht_bin[2]=ht_bin[0];
 406       ht_bin[1]=(int)head->addr;
 407       ht_bin[0]=vaddr;
 408       return head->addr;
 409     }
 410     head=head->next;
 411   }
 412   head=jump_dirty[vpage];
 413   while(head!=NULL) {
 414     if(head->vaddr==vaddr) {
 415       //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
 416       // Don't restore blocks which are about to expire from the cache
 417       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 418       if(verify_dirty(head->addr)) {
 419         //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
 420         invalid_code[vaddr>>12]=0;
 421         inv_code_start=inv_code_end=~0;
 422 #ifndef DISABLE_TLB
 423         memory_map[vaddr>>12]|=0x40000000;
 424 #endif
 425         if(vpage<2048) {
 426 #ifndef DISABLE_TLB
 427           if(tlb_LUT_r[vaddr>>12]) {
 428             invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
 429             memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
 430           }
 431 #endif
 432           restore_candidate[vpage>>3]|=1<<(vpage&7);
 433         }
 434         else restore_candidate[page>>3]|=1<<(page&7);
 435         int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 436         if(ht_bin[0]==vaddr) {
 437           ht_bin[1]=(int)head->addr; // Replace existing entry
 438         }
 439         else
 440         {
 441           ht_bin[3]=ht_bin[1];
 442           ht_bin[2]=ht_bin[0];
 443           ht_bin[1]=(int)head->addr;
 444           ht_bin[0]=vaddr;
 445         }
 446         return head->addr;
 447       }
 448     }
 449     head=head->next;
 450   }
 451   //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
 452   int r=new_recompile_block(vaddr);
 453   if(r==0) return get_addr(vaddr);
 454   // Execute in unmapped page, generate pagefault execption
 455   Status|=2;
 456   Cause=(vaddr<<31)|0x8;
 457   EPC=(vaddr&1)?vaddr-5:vaddr;
 458   BadVAddr=(vaddr&~1);
 459   Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
 460   EntryHi=BadVAddr&0xFFFFE000;
 461   return get_addr_ht(0x80000000);
 462 }
 463 // Look up address in hash table first
 464 void *get_addr_ht(u_int vaddr)
 465 {
 466   //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
 467   int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 468   if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
 469   if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
 470   return get_addr(vaddr);
 471 }
 472
 473 void clear_all_regs(signed char regmap[])
 474 {
 475   int hr;
 476   for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
 477 }
 478
 479 signed char get_reg(signed char regmap[],int r)
 480 {
 481   int hr;
 482   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap[hr]==r) return hr;
 483   return -1;
 484 }
 485
 486 // Find a register that is available for two consecutive cycles
 487 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
 488 {
 489   int hr;
 490   for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&&regmap1[hr]==r&&regmap2[hr]==r) return hr;
 491   return -1;
 492 }
 493
 494 int count_free_regs(signed char regmap[])
 495 {
 496   int count=0;
 497   int hr;
 498   for(hr=0;hr<HOST_REGS;hr++)
 499   {
 500     if(hr!=EXCLUDE_REG) {
 501       if(regmap[hr]<0) count++;
 502     }
 503   }
 504   return count;
 505 }
 506
 507 void dirty_reg(struct regstat *cur,signed char reg)
 508 {
 509   int hr;
 510   if(!reg) return;
 511   for (hr=0;hr<HOST_REGS;hr++) {
 512     if((cur->regmap[hr]&63)==reg) {
 513       cur->dirty|=1<<hr;
 514     }
 515   }
 516 }
 517
 518 // If we dirty the lower half of a 64 bit register which is now being
 519 // sign-extended, we need to dump the upper half.
 520 // Note: Do this only after completion of the instruction, because
 521 // some instructions may need to read the full 64-bit value even if
 522 // overwriting it (eg SLTI, DSRA32).
 523 static void flush_dirty_uppers(struct regstat *cur)
 524 {
 525   int hr,reg;
 526   for (hr=0;hr<HOST_REGS;hr++) {
 527     if((cur->dirty>>hr)&1) {
 528       reg=cur->regmap[hr];
 529       if(reg>=64)
 530         if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
 531     }
 532   }
 533 }
 534
 535 void set_const(struct regstat *cur,signed char reg,uint64_t value)
 536 {
 537   int hr;
 538   if(!reg) return;
 539   for (hr=0;hr<HOST_REGS;hr++) {
 540     if(cur->regmap[hr]==reg) {
 541       cur->isconst|=1<<hr;
 542       current_constmap[hr]=value;
 543     }
 544     else if((cur->regmap[hr]^64)==reg) {
 545       cur->isconst|=1<<hr;
 546       current_constmap[hr]=value>>32;
 547     }
 548   }
 549 }
 550
 551 void clear_const(struct regstat *cur,signed char reg)
 552 {
 553   int hr;
 554   if(!reg) return;
 555   for (hr=0;hr<HOST_REGS;hr++) {
 556     if((cur->regmap[hr]&63)==reg) {
 557       cur->isconst&=~(1<<hr);
 558     }
 559   }
 560 }
 561
 562 int is_const(struct regstat *cur,signed char reg)
 563 {
 564   int hr;
 565   if(reg<0) return 0;
 566   if(!reg) return 1;
 567   for (hr=0;hr<HOST_REGS;hr++) {
 568     if((cur->regmap[hr]&63)==reg) {
 569       return (cur->isconst>>hr)&1;
 570     }
 571   }
 572   return 0;
 573 }
 574 uint64_t get_const(struct regstat *cur,signed char reg)
 575 {
 576   int hr;
 577   if(!reg) return 0;
 578   for (hr=0;hr<HOST_REGS;hr++) {
 579     if(cur->regmap[hr]==reg) {
 580       return current_constmap[hr];
 581     }
 582   }
 583   SysPrintf("Unknown constant in r%d\n",reg);
 584   exit(1);
 585 }
 586
 587 // Least soon needed registers
 588 // Look at the next ten instructions and see which registers
 589 // will be used.  Try not to reallocate these.
 590 void lsn(u_char hsn[], int i, int *preferred_reg)
 591 {
 592   int j;
 593   int b=-1;
 594   for(j=0;j<9;j++)
 595   {
 596     if(i+j>=slen) {
 597       j=slen-i-1;
 598       break;
 599     }
 600     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 601     {
 602       // Don't go past an unconditonal jump
 603       j++;
 604       break;
 605     }
 606   }
 607   for(;j>=0;j--)
 608   {
 609     if(rs1[i+j]) hsn[rs1[i+j]]=j;
 610     if(rs2[i+j]) hsn[rs2[i+j]]=j;
 611     if(rt1[i+j]) hsn[rt1[i+j]]=j;
 612     if(rt2[i+j]) hsn[rt2[i+j]]=j;
 613     if(itype[i+j]==STORE || itype[i+j]==STORELR) {
 614       // Stores can allocate zero
 615       hsn[rs1[i+j]]=j;
 616       hsn[rs2[i+j]]=j;
 617     }
 618     // On some architectures stores need invc_ptr
 619     #if defined(HOST_IMM8)
 620     if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
 621       hsn[INVCP]=j;
 622     }
 623     #endif
 624     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 625     {
 626       hsn[CCREG]=j;
 627       b=j;
 628     }
 629   }
 630   if(b>=0)
 631   {
 632     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 633     {
 634       // Follow first branch
 635       int t=(ba[i+b]-start)>>2;
 636       j=7-b;if(t+j>=slen) j=slen-t-1;
 637       for(;j>=0;j--)
 638       {
 639         if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
 640         if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
 641         //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
 642         //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
 643       }
 644     }
 645     // TODO: preferred register based on backward branch
 646   }
 647   // Delay slot should preferably not overwrite branch conditions or cycle count
 648   if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
 649     if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
 650     if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
 651     hsn[CCREG]=1;
 652     // ...or hash tables
 653     hsn[RHASH]=1;
 654     hsn[RHTBL]=1;
 655   }
 656   // Coprocessor load/store needs FTEMP, even if not declared
 657   if(itype[i]==C1LS||itype[i]==C2LS) {
 658     hsn[FTEMP]=0;
 659   }
 660   // Load L/R also uses FTEMP as a temporary register
 661   if(itype[i]==LOADLR) {
 662     hsn[FTEMP]=0;
 663   }
 664   // Also SWL/SWR/SDL/SDR
 665   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
 666     hsn[FTEMP]=0;
 667   }
 668   // Don't remove the TLB registers either
 669   if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
 670     hsn[TLREG]=0;
 671   }
 672   // Don't remove the miniht registers
 673   if(itype[i]==UJUMP||itype[i]==RJUMP)
 674   {
 675     hsn[RHASH]=0;
 676     hsn[RHTBL]=0;
 677   }
 678 }
 679
 680 // We only want to allocate registers if we're going to use them again soon
 681 int needed_again(int r, int i)
 682 {
 683   int j;
 684   int b=-1;
 685   int rn=10;
 686
 687   if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
 688   {
 689     if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
 690       return 0; // Don't need any registers if exiting the block
 691   }
 692   for(j=0;j<9;j++)
 693   {
 694     if(i+j>=slen) {
 695       j=slen-i-1;
 696       break;
 697     }
 698     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 699     {
 700       // Don't go past an unconditonal jump
 701       j++;
 702       break;
 703     }
 704     if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
 705     {
 706       break;
 707     }
 708   }
 709   for(;j>=1;j--)
 710   {
 711     if(rs1[i+j]==r) rn=j;
 712     if(rs2[i+j]==r) rn=j;
 713     if((unneeded_reg[i+j]>>r)&1) rn=10;
 714     if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
 715     {
 716       b=j;
 717     }
 718   }
 719   /*
 720   if(b>=0)
 721   {
 722     if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
 723     {
 724       // Follow first branch
 725       int o=rn;
 726       int t=(ba[i+b]-start)>>2;
 727       j=7-b;if(t+j>=slen) j=slen-t-1;
 728       for(;j>=0;j--)
 729       {
 730         if(!((unneeded_reg[t+j]>>r)&1)) {
 731           if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 732           if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
 733         }
 734         else rn=o;
 735       }
 736     }
 737   }*/
 738   if(rn<10) return 1;
 739   return 0;
 740 }
 741
 742 // Try to match register allocations at the end of a loop with those
 743 // at the beginning
 744 int loop_reg(int i, int r, int hr)
 745 {
 746   int j,k;
 747   for(j=0;j<9;j++)
 748   {
 749     if(i+j>=slen) {
 750       j=slen-i-1;
 751       break;
 752     }
 753     if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
 754     {
 755       // Don't go past an unconditonal jump
 756       j++;
 757       break;
 758     }
 759   }
 760   k=0;
 761   if(i>0){
 762     if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
 763       k--;
 764   }
 765   for(;k<j;k++)
 766   {
 767     if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
 768     if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
 769     if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
 770     {
 771       if(ba[i+k]>=start && ba[i+k]<(start+i*4))
 772       {
 773         int t=(ba[i+k]-start)>>2;
 774         int reg=get_reg(regs[t].regmap_entry,r);
 775         if(reg>=0) return reg;
 776         //reg=get_reg(regs[t+1].regmap_entry,r);
 777         //if(reg>=0) return reg;
 778       }
 779     }
 780   }
 781   return hr;
 782 }
 783
 784
 785 // Allocate every register, preserving source/target regs
 786 void alloc_all(struct regstat *cur,int i)
 787 {
 788   int hr;
 789
 790   for(hr=0;hr<HOST_REGS;hr++) {
 791     if(hr!=EXCLUDE_REG) {
 792       if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
 793          ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
 794       {
 795         cur->regmap[hr]=-1;
 796         cur->dirty&=~(1<<hr);
 797       }
 798       // Don't need zeros
 799       if((cur->regmap[hr]&63)==0)
 800       {
 801         cur->regmap[hr]=-1;
 802         cur->dirty&=~(1<<hr);
 803       }
 804     }
 805   }
 806 }
 807
 808 #ifndef FORCE32
 809 void div64(int64_t dividend,int64_t divisor)
 810 {
 811   lo=dividend/divisor;
 812   hi=dividend%divisor;
 813   //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
 814   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 815 }
 816 void divu64(uint64_t dividend,uint64_t divisor)
 817 {
 818   lo=dividend/divisor;
 819   hi=dividend%divisor;
 820   //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 821   //                                     ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 822 }
 823
 824 void mult64(uint64_t m1,uint64_t m2)
 825 {
 826    unsigned long long int op1, op2, op3, op4;
 827    unsigned long long int result1, result2, result3, result4;
 828    unsigned long long int temp1, temp2, temp3, temp4;
 829    int sign = 0;
 830
 831    if (m1 < 0)
 832      {
 833     op2 = -m1;
 834     sign = 1 - sign;
 835      }
 836    else op2 = m1;
 837    if (m2 < 0)
 838      {
 839     op4 = -m2;
 840     sign = 1 - sign;
 841      }
 842    else op4 = m2;
 843
 844    op1 = op2 & 0xFFFFFFFF;
 845    op2 = (op2 >> 32) & 0xFFFFFFFF;
 846    op3 = op4 & 0xFFFFFFFF;
 847    op4 = (op4 >> 32) & 0xFFFFFFFF;
 848
 849    temp1 = op1 * op3;
 850    temp2 = (temp1 >> 32) + op1 * op4;
 851    temp3 = op2 * op3;
 852    temp4 = (temp3 >> 32) + op2 * op4;
 853
 854    result1 = temp1 & 0xFFFFFFFF;
 855    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 856    result3 = (result2 >> 32) + temp4;
 857    result4 = (result3 >> 32);
 858
 859    lo = result1 | (result2 << 32);
 860    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 861    if (sign)
 862      {
 863     hi = ~hi;
 864     if (!lo) hi++;
 865     else lo = ~lo + 1;
 866      }
 867 }
 868
 869 void multu64(uint64_t m1,uint64_t m2)
 870 {
 871    unsigned long long int op1, op2, op3, op4;
 872    unsigned long long int result1, result2, result3, result4;
 873    unsigned long long int temp1, temp2, temp3, temp4;
 874
 875    op1 = m1 & 0xFFFFFFFF;
 876    op2 = (m1 >> 32) & 0xFFFFFFFF;
 877    op3 = m2 & 0xFFFFFFFF;
 878    op4 = (m2 >> 32) & 0xFFFFFFFF;
 879
 880    temp1 = op1 * op3;
 881    temp2 = (temp1 >> 32) + op1 * op4;
 882    temp3 = op2 * op3;
 883    temp4 = (temp3 >> 32) + op2 * op4;
 884
 885    result1 = temp1 & 0xFFFFFFFF;
 886    result2 = temp2 + (temp3 & 0xFFFFFFFF);
 887    result3 = (result2 >> 32) + temp4;
 888    result4 = (result3 >> 32);
 889
 890    lo = result1 | (result2 << 32);
 891    hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
 892
 893   //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
 894   //                                      ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
 895 }
 896
 897 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
 898 {
 899   if(bits) {
 900     original<<=64-bits;
 901     original>>=64-bits;
 902     loaded<<=bits;
 903     original|=loaded;
 904   }
 905   else original=loaded;
 906   return original;
 907 }
 908 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
 909 {
 910   if(bits^56) {
 911     original>>=64-(bits^56);
 912     original<<=64-(bits^56);
 913     loaded>>=bits^56;
 914     original|=loaded;
 915   }
 916   else original=loaded;
 917   return original;
 918 }
 919 #endif
 920
 921 #ifdef __i386__
 922 #include "assem_x86.c"
 923 #endif
 924 #ifdef __x86_64__
 925 #include "assem_x64.c"
 926 #endif
 927 #ifdef __arm__
 928 #include "assem_arm.c"
 929 #endif
 930
 931 // Add virtual address mapping to linked list
 932 void ll_add(struct ll_entry **head,int vaddr,void *addr)
 933 {
 934   struct ll_entry *new_entry;
 935   new_entry=malloc(sizeof(struct ll_entry));
 936   assert(new_entry!=NULL);
 937   new_entry->vaddr=vaddr;
 938   new_entry->reg_sv_flags=0;
 939   new_entry->addr=addr;
 940   new_entry->next=*head;
 941   *head=new_entry;
 942 }
 943
 944 void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
 945 {
 946   ll_add(head,vaddr,addr);
 947   (*head)->reg_sv_flags=reg_sv_flags;
 948 }
 949
 950 // Check if an address is already compiled
 951 // but don't return addresses which are about to expire from the cache
 952 void *check_addr(u_int vaddr)
 953 {
 954   u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
 955   if(ht_bin[0]==vaddr) {
 956     if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 957       if(isclean(ht_bin[1])) return (void *)ht_bin[1];
 958   }
 959   if(ht_bin[2]==vaddr) {
 960     if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
 961       if(isclean(ht_bin[3])) return (void *)ht_bin[3];
 962   }
 963   u_int page=get_page(vaddr);
 964   struct ll_entry *head;
 965   head=jump_in[page];
 966   while(head!=NULL) {
 967     if(head->vaddr==vaddr) {
 968       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
 969         // Update existing entry with current address
 970         if(ht_bin[0]==vaddr) {
 971           ht_bin[1]=(int)head->addr;
 972           return head->addr;
 973         }
 974         if(ht_bin[2]==vaddr) {
 975           ht_bin[3]=(int)head->addr;
 976           return head->addr;
 977         }
 978         // Insert into hash table with low priority.
 979         // Don't evict existing entries, as they are probably
 980         // addresses that are being accessed frequently.
 981         if(ht_bin[0]==-1) {
 982           ht_bin[1]=(int)head->addr;
 983           ht_bin[0]=vaddr;
 984         }else if(ht_bin[2]==-1) {
 985           ht_bin[3]=(int)head->addr;
 986           ht_bin[2]=vaddr;
 987         }
 988         return head->addr;
 989       }
 990     }
 991     head=head->next;
 992   }
 993   return 0;
 994 }
 995
 996 void remove_hash(int vaddr)
 997 {
 998   //printf("remove hash: %x\n",vaddr);
 999   int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1000   if(ht_bin[2]==vaddr) {
1001     ht_bin[2]=ht_bin[3]=-1;
1002   }
1003   if(ht_bin[0]==vaddr) {
1004     ht_bin[0]=ht_bin[2];
1005     ht_bin[1]=ht_bin[3];
1006     ht_bin[2]=ht_bin[3]=-1;
1007   }
1008 }
1009
1010 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1011 {
1012   struct ll_entry *next;
1013   while(*head) {
1014     if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1015        ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1016     {
1017       inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1018       remove_hash((*head)->vaddr);
1019       next=(*head)->next;
1020       free(*head);
1021       *head=next;
1022     }
1023     else
1024     {
1025       head=&((*head)->next);
1026     }
1027   }
1028 }
1029
1030 // Remove all entries from linked list
1031 void ll_clear(struct ll_entry **head)
1032 {
1033   struct ll_entry *cur;
1034   struct ll_entry *next;
1035   if(cur=*head) {
1036     *head=0;
1037     while(cur) {
1038       next=cur->next;
1039       free(cur);
1040       cur=next;
1041     }
1042   }
1043 }
1044
1045 // Dereference the pointers and remove if it matches
1046 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1047 {
1048   while(head) {
1049     int ptr=get_pointer(head->addr);
1050     inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1051     if(((ptr>>shift)==(addr>>shift)) ||
1052        (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1053     {
1054       inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1055       u_int host_addr=(u_int)kill_pointer(head->addr);
1056       #ifdef __arm__
1057         needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1058       #endif
1059     }
1060     head=head->next;
1061   }
1062 }
1063
1064 // This is called when we write to a compiled block (see do_invstub)
1065 void invalidate_page(u_int page)
1066 {
1067   struct ll_entry *head;
1068   struct ll_entry *next;
1069   head=jump_in[page];
1070   jump_in[page]=0;
1071   while(head!=NULL) {
1072     inv_debug("INVALIDATE: %x\n",head->vaddr);
1073     remove_hash(head->vaddr);
1074     next=head->next;
1075     free(head);
1076     head=next;
1077   }
1078   head=jump_out[page];
1079   jump_out[page]=0;
1080   while(head!=NULL) {
1081     inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1082     u_int host_addr=(u_int)kill_pointer(head->addr);
1083     #ifdef __arm__
1084       needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1085     #endif
1086     next=head->next;
1087     free(head);
1088     head=next;
1089   }
1090 }
1091
1092 static void invalidate_block_range(u_int block, u_int first, u_int last)
1093 {
1094   u_int page=get_page(block<<12);
1095   //printf("first=%d last=%d\n",first,last);
1096   invalidate_page(page);
1097   assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1098   assert(last<page+5);
1099   // Invalidate the adjacent pages if a block crosses a 4K boundary
1100   while(first<page) {
1101     invalidate_page(first);
1102     first++;
1103   }
1104   for(first=page+1;first<last;first++) {
1105     invalidate_page(first);
1106   }
1107   #ifdef __arm__
1108     do_clear_cache();
1109   #endif
1110
1111   // Don't trap writes
1112   invalid_code[block]=1;
1113 #ifndef DISABLE_TLB
1114   // If there is a valid TLB entry for this page, remove write protect
1115   if(tlb_LUT_w[block]) {
1116     assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1117     // CHECK: Is this right?
1118     memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1119     u_int real_block=tlb_LUT_w[block]>>12;
1120     invalid_code[real_block]=1;
1121     if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1122   }
1123   else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1124 #endif
1125
1126   #ifdef USE_MINI_HT
1127   memset(mini_ht,-1,sizeof(mini_ht));
1128   #endif
1129 }
1130
1131 void invalidate_block(u_int block)
1132 {
1133   u_int page=get_page(block<<12);
1134   u_int vpage=get_vpage(block<<12);
1135   inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1136   //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1137   u_int first,last;
1138   first=last=page;
1139   struct ll_entry *head;
1140   head=jump_dirty[vpage];
1141   //printf("page=%d vpage=%d\n",page,vpage);
1142   while(head!=NULL) {
1143     u_int start,end;
1144     if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1145       get_bounds((int)head->addr,&start,&end);
1146       //printf("start: %x end: %x\n",start,end);
1147       if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
1148         if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1149           if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1150           if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1151         }
1152       }
1153 #ifndef DISABLE_TLB
1154       if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1155         if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1156           if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1157           if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1158         }
1159       }
1160 #endif
1161     }
1162     head=head->next;
1163   }
1164   invalidate_block_range(block,first,last);
1165 }
1166
1167 void invalidate_addr(u_int addr)
1168 {
1169 #ifdef PCSX
1170   //static int rhits;
1171   // this check is done by the caller
1172   //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1173   u_int page=get_vpage(addr);
1174   if(page<2048) { // RAM
1175     struct ll_entry *head;
1176     u_int addr_min=~0, addr_max=0;
1177     u_int mask=RAM_SIZE-1;
1178     u_int addr_main=0x80000000|(addr&mask);
1179     int pg1;
1180     inv_code_start=addr_main&~0xfff;
1181     inv_code_end=addr_main|0xfff;
1182     pg1=page;
1183     if (pg1>0) {
1184       // must check previous page too because of spans..
1185       pg1--;
1186       inv_code_start-=0x1000;
1187     }
1188     for(;pg1<=page;pg1++) {
1189       for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1190         u_int start,end;
1191         get_bounds((int)head->addr,&start,&end);
1192         if(ram_offset) {
1193           start-=ram_offset;
1194           end-=ram_offset;
1195         }
1196         if(start<=addr_main&&addr_main<end) {
1197           if(start<addr_min) addr_min=start;
1198           if(end>addr_max) addr_max=end;
1199         }
1200         else if(addr_main<start) {
1201           if(start<inv_code_end)
1202             inv_code_end=start-1;
1203         }
1204         else {
1205           if(end>inv_code_start)
1206             inv_code_start=end;
1207         }
1208       }
1209     }
1210     if (addr_min!=~0) {
1211       inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1212       inv_code_start=inv_code_end=~0;
1213       invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1214       return;
1215     }
1216     else {
1217       inv_code_start=(addr&~mask)|(inv_code_start&mask);
1218       inv_code_end=(addr&~mask)|(inv_code_end&mask);
1219       inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1220       return;
1221     }
1222   }
1223 #endif
1224   invalidate_block(addr>>12);
1225 }
1226
1227 // This is called when loading a save state.
1228 // Anything could have changed, so invalidate everything.
1229 void invalidate_all_pages()
1230 {
1231   u_int page,n;
1232   for(page=0;page<4096;page++)
1233     invalidate_page(page);
1234   for(page=0;page<1048576;page++)
1235     if(!invalid_code[page]) {
1236       restore_candidate[(page&2047)>>3]|=1<<(page&7);
1237       restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1238     }
1239   #ifdef __arm__
1240   __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1241   #endif
1242   #ifdef USE_MINI_HT
1243   memset(mini_ht,-1,sizeof(mini_ht));
1244   #endif
1245   #ifndef DISABLE_TLB
1246   // TLB
1247   for(page=0;page<0x100000;page++) {
1248     if(tlb_LUT_r[page]) {
1249       memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1250       if(!tlb_LUT_w[page]||!invalid_code[page])
1251         memory_map[page]|=0x40000000; // Write protect
1252     }
1253     else memory_map[page]=-1;
1254     if(page==0x80000) page=0xC0000;
1255   }
1256   tlb_hacks();
1257   #endif
1258 }
1259
1260 // Add an entry to jump_out after making a link
1261 void add_link(u_int vaddr,void *src)
1262 {
1263   u_int page=get_page(vaddr);
1264   inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1265   int *ptr=(int *)(src+4);
1266   assert((*ptr&0x0fff0000)==0x059f0000);
1267   ll_add(jump_out+page,vaddr,src);
1268   //int ptr=get_pointer(src);
1269   //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1270 }
1271
1272 // If a code block was found to be unmodified (bit was set in
1273 // restore_candidate) and it remains unmodified (bit is clear
1274 // in invalid_code) then move the entries for that 4K page from
1275 // the dirty list to the clean list.
1276 void clean_blocks(u_int page)
1277 {
1278   struct ll_entry *head;
1279   inv_debug("INV: clean_blocks page=%d\n",page);
1280   head=jump_dirty[page];
1281   while(head!=NULL) {
1282     if(!invalid_code[head->vaddr>>12]) {
1283       // Don't restore blocks which are about to expire from the cache
1284       if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1285         u_int start,end;
1286         if(verify_dirty((int)head->addr)) {
1287           //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1288           u_int i;
1289           u_int inv=0;
1290           get_bounds((int)head->addr,&start,&end);
1291           if(start-(u_int)rdram<RAM_SIZE) {
1292             for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1293               inv|=invalid_code[i];
1294             }
1295           }
1296 #ifndef DISABLE_TLB
1297           if((signed int)head->vaddr>=(signed int)0xC0000000) {
1298             u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1299             //printf("addr=%x start=%x end=%x\n",addr,start,end);
1300             if(addr<start||addr>=end) inv=1;
1301           }
1302 #endif
1303           else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1304             inv=1;
1305           }
1306           if(!inv) {
1307             void * clean_addr=(void *)get_clean_addr((int)head->addr);
1308             if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1309               u_int ppage=page;
1310 #ifndef DISABLE_TLB
1311               if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1312 #endif
1313               inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1314               //printf("page=%x, addr=%x\n",page,head->vaddr);
1315               //assert(head->vaddr>>12==(page|0x80000));
1316               ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1317               int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1318               if(ht_bin[0]==head->vaddr) {
1319                 ht_bin[1]=(int)clean_addr; // Replace existing entry
1320               }
1321               if(ht_bin[2]==head->vaddr) {
1322                 ht_bin[3]=(int)clean_addr; // Replace existing entry
1323               }
1324             }
1325           }
1326         }
1327       }
1328     }
1329     head=head->next;
1330   }
1331 }
1332
1333
1334 void mov_alloc(struct regstat *current,int i)
1335 {
1336   // Note: Don't need to actually alloc the source registers
1337   if((~current->is32>>rs1[i])&1) {
1338     //alloc_reg64(current,i,rs1[i]);
1339     alloc_reg64(current,i,rt1[i]);
1340     current->is32&=~(1LL<<rt1[i]);
1341   } else {
1342     //alloc_reg(current,i,rs1[i]);
1343     alloc_reg(current,i,rt1[i]);
1344     current->is32|=(1LL<<rt1[i]);
1345   }
1346   clear_const(current,rs1[i]);
1347   clear_const(current,rt1[i]);
1348   dirty_reg(current,rt1[i]);
1349 }
1350
1351 void shiftimm_alloc(struct regstat *current,int i)
1352 {
1353   if(opcode2[i]<=0x3) // SLL/SRL/SRA
1354   {
1355     if(rt1[i]) {
1356       if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1357       else lt1[i]=rs1[i];
1358       alloc_reg(current,i,rt1[i]);
1359       current->is32|=1LL<<rt1[i];
1360       dirty_reg(current,rt1[i]);
1361       if(is_const(current,rs1[i])) {
1362         int v=get_const(current,rs1[i]);
1363         if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1364         if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1365         if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1366       }
1367       else clear_const(current,rt1[i]);
1368     }
1369   }
1370   else
1371   {
1372     clear_const(current,rs1[i]);
1373     clear_const(current,rt1[i]);
1374   }
1375
1376   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1377   {
1378     if(rt1[i]) {
1379       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1380       alloc_reg64(current,i,rt1[i]);
1381       current->is32&=~(1LL<<rt1[i]);
1382       dirty_reg(current,rt1[i]);
1383     }
1384   }
1385   if(opcode2[i]==0x3c) // DSLL32
1386   {
1387     if(rt1[i]) {
1388       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1389       alloc_reg64(current,i,rt1[i]);
1390       current->is32&=~(1LL<<rt1[i]);
1391       dirty_reg(current,rt1[i]);
1392     }
1393   }
1394   if(opcode2[i]==0x3e) // DSRL32
1395   {
1396     if(rt1[i]) {
1397       alloc_reg64(current,i,rs1[i]);
1398       if(imm[i]==32) {
1399         alloc_reg64(current,i,rt1[i]);
1400         current->is32&=~(1LL<<rt1[i]);
1401       } else {
1402         alloc_reg(current,i,rt1[i]);
1403         current->is32|=1LL<<rt1[i];
1404       }
1405       dirty_reg(current,rt1[i]);
1406     }
1407   }
1408   if(opcode2[i]==0x3f) // DSRA32
1409   {
1410     if(rt1[i]) {
1411       alloc_reg64(current,i,rs1[i]);
1412       alloc_reg(current,i,rt1[i]);
1413       current->is32|=1LL<<rt1[i];
1414       dirty_reg(current,rt1[i]);
1415     }
1416   }
1417 }
1418
1419 void shift_alloc(struct regstat *current,int i)
1420 {
1421   if(rt1[i]) {
1422     if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1423     {
1424       if(rs1[i]) alloc_reg(current,i,rs1[i]);
1425       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1426       alloc_reg(current,i,rt1[i]);
1427       if(rt1[i]==rs2[i]) {
1428         alloc_reg_temp(current,i,-1);
1429         minimum_free_regs[i]=1;
1430       }
1431       current->is32|=1LL<<rt1[i];
1432     } else { // DSLLV/DSRLV/DSRAV
1433       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1434       if(rs2[i]) alloc_reg(current,i,rs2[i]);
1435       alloc_reg64(current,i,rt1[i]);
1436       current->is32&=~(1LL<<rt1[i]);
1437       if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1438       {
1439         alloc_reg_temp(current,i,-1);
1440         minimum_free_regs[i]=1;
1441       }
1442     }
1443     clear_const(current,rs1[i]);
1444     clear_const(current,rs2[i]);
1445     clear_const(current,rt1[i]);
1446     dirty_reg(current,rt1[i]);
1447   }
1448 }
1449
1450 void alu_alloc(struct regstat *current,int i)
1451 {
1452   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1453     if(rt1[i]) {
1454       if(rs1[i]&&rs2[i]) {
1455         alloc_reg(current,i,rs1[i]);
1456         alloc_reg(current,i,rs2[i]);
1457       }
1458       else {
1459         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1460         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1461       }
1462       alloc_reg(current,i,rt1[i]);
1463     }
1464     current->is32|=1LL<<rt1[i];
1465   }
1466   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1467     if(rt1[i]) {
1468       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1469       {
1470         alloc_reg64(current,i,rs1[i]);
1471         alloc_reg64(current,i,rs2[i]);
1472         alloc_reg(current,i,rt1[i]);
1473       } else {
1474         alloc_reg(current,i,rs1[i]);
1475         alloc_reg(current,i,rs2[i]);
1476         alloc_reg(current,i,rt1[i]);
1477       }
1478     }
1479     current->is32|=1LL<<rt1[i];
1480   }
1481   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1482     if(rt1[i]) {
1483       if(rs1[i]&&rs2[i]) {
1484         alloc_reg(current,i,rs1[i]);
1485         alloc_reg(current,i,rs2[i]);
1486       }
1487       else
1488       {
1489         if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1490         if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1491       }
1492       alloc_reg(current,i,rt1[i]);
1493       if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1494       {
1495         if(!((current->uu>>rt1[i])&1)) {
1496           alloc_reg64(current,i,rt1[i]);
1497         }
1498         if(get_reg(current->regmap,rt1[i]|64)>=0) {
1499           if(rs1[i]&&rs2[i]) {
1500             alloc_reg64(current,i,rs1[i]);
1501             alloc_reg64(current,i,rs2[i]);
1502           }
1503           else
1504           {
1505             // Is is really worth it to keep 64-bit values in registers?
1506             #ifdef NATIVE_64BIT
1507             if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1508             if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1509             #endif
1510           }
1511         }
1512         current->is32&=~(1LL<<rt1[i]);
1513       } else {
1514         current->is32|=1LL<<rt1[i];
1515       }
1516     }
1517   }
1518   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1519     if(rt1[i]) {
1520       if(rs1[i]&&rs2[i]) {
1521         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1522           alloc_reg64(current,i,rs1[i]);
1523           alloc_reg64(current,i,rs2[i]);
1524           alloc_reg64(current,i,rt1[i]);
1525         } else {
1526           alloc_reg(current,i,rs1[i]);
1527           alloc_reg(current,i,rs2[i]);
1528           alloc_reg(current,i,rt1[i]);
1529         }
1530       }
1531       else {
1532         alloc_reg(current,i,rt1[i]);
1533         if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1534           // DADD used as move, or zeroing
1535           // If we have a 64-bit source, then make the target 64 bits too
1536           if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1537             if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1538             alloc_reg64(current,i,rt1[i]);
1539           } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1540             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1541             alloc_reg64(current,i,rt1[i]);
1542           }
1543           if(opcode2[i]>=0x2e&&rs2[i]) {
1544             // DSUB used as negation - 64-bit result
1545             // If we have a 32-bit register, extend it to 64 bits
1546             if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1547             alloc_reg64(current,i,rt1[i]);
1548           }
1549         }
1550       }
1551       if(rs1[i]&&rs2[i]) {
1552         current->is32&=~(1LL<<rt1[i]);
1553       } else if(rs1[i]) {
1554         current->is32&=~(1LL<<rt1[i]);
1555         if((current->is32>>rs1[i])&1)
1556           current->is32|=1LL<<rt1[i];
1557       } else if(rs2[i]) {
1558         current->is32&=~(1LL<<rt1[i]);
1559         if((current->is32>>rs2[i])&1)
1560           current->is32|=1LL<<rt1[i];
1561       } else {
1562         current->is32|=1LL<<rt1[i];
1563       }
1564     }
1565   }
1566   clear_const(current,rs1[i]);
1567   clear_const(current,rs2[i]);
1568   clear_const(current,rt1[i]);
1569   dirty_reg(current,rt1[i]);
1570 }
1571
1572 void imm16_alloc(struct regstat *current,int i)
1573 {
1574   if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1575   else lt1[i]=rs1[i];
1576   if(rt1[i]) alloc_reg(current,i,rt1[i]);
1577   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1578     current->is32&=~(1LL<<rt1[i]);
1579     if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1580       // TODO: Could preserve the 32-bit flag if the immediate is zero
1581       alloc_reg64(current,i,rt1[i]);
1582       alloc_reg64(current,i,rs1[i]);
1583     }
1584     clear_const(current,rs1[i]);
1585     clear_const(current,rt1[i]);
1586   }
1587   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1588     if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1589     current->is32|=1LL<<rt1[i];
1590     clear_const(current,rs1[i]);
1591     clear_const(current,rt1[i]);
1592   }
1593   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1594     if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1595       if(rs1[i]!=rt1[i]) {
1596         if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1597         alloc_reg64(current,i,rt1[i]);
1598         current->is32&=~(1LL<<rt1[i]);
1599       }
1600     }
1601     else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1602     if(is_const(current,rs1[i])) {
1603       int v=get_const(current,rs1[i]);
1604       if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1605       if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1606       if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1607     }
1608     else clear_const(current,rt1[i]);
1609   }
1610   else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1611     if(is_const(current,rs1[i])) {
1612       int v=get_const(current,rs1[i]);
1613       set_const(current,rt1[i],v+imm[i]);
1614     }
1615     else clear_const(current,rt1[i]);
1616     current->is32|=1LL<<rt1[i];
1617   }
1618   else {
1619     set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1620     current->is32|=1LL<<rt1[i];
1621   }
1622   dirty_reg(current,rt1[i]);
1623 }
1624
1625 void load_alloc(struct regstat *current,int i)
1626 {
1627   clear_const(current,rt1[i]);
1628   //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1629   if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1630   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1631   if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1632     alloc_reg(current,i,rt1[i]);
1633     assert(get_reg(current->regmap,rt1[i])>=0);
1634     if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1635     {
1636       current->is32&=~(1LL<<rt1[i]);
1637       alloc_reg64(current,i,rt1[i]);
1638     }
1639     else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1640     {
1641       current->is32&=~(1LL<<rt1[i]);
1642       alloc_reg64(current,i,rt1[i]);
1643       alloc_all(current,i);
1644       alloc_reg64(current,i,FTEMP);
1645       minimum_free_regs[i]=HOST_REGS;
1646     }
1647     else current->is32|=1LL<<rt1[i];
1648     dirty_reg(current,rt1[i]);
1649     // If using TLB, need a register for pointer to the mapping table
1650     if(using_tlb) alloc_reg(current,i,TLREG);
1651     // LWL/LWR need a temporary register for the old value
1652     if(opcode[i]==0x22||opcode[i]==0x26)
1653     {
1654       alloc_reg(current,i,FTEMP);
1655       alloc_reg_temp(current,i,-1);
1656       minimum_free_regs[i]=1;
1657     }
1658   }
1659   else
1660   {
1661     // Load to r0 or unneeded register (dummy load)
1662     // but we still need a register to calculate the address
1663     if(opcode[i]==0x22||opcode[i]==0x26)
1664     {
1665       alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1666     }
1667     // If using TLB, need a register for pointer to the mapping table
1668     if(using_tlb) alloc_reg(current,i,TLREG);
1669     alloc_reg_temp(current,i,-1);
1670     minimum_free_regs[i]=1;
1671     if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1672     {
1673       alloc_all(current,i);
1674       alloc_reg64(current,i,FTEMP);
1675       minimum_free_regs[i]=HOST_REGS;
1676     }
1677   }
1678 }
1679
1680 void store_alloc(struct regstat *current,int i)
1681 {
1682   clear_const(current,rs2[i]);
1683   if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1684   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1685   alloc_reg(current,i,rs2[i]);
1686   if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1687     alloc_reg64(current,i,rs2[i]);
1688     if(rs2[i]) alloc_reg(current,i,FTEMP);
1689   }
1690   // If using TLB, need a register for pointer to the mapping table
1691   if(using_tlb) alloc_reg(current,i,TLREG);
1692   #if defined(HOST_IMM8)
1693   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1694   else alloc_reg(current,i,INVCP);
1695   #endif
1696   if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1697     alloc_reg(current,i,FTEMP);
1698   }
1699   // We need a temporary register for address generation
1700   alloc_reg_temp(current,i,-1);
1701   minimum_free_regs[i]=1;
1702 }
1703
1704 void c1ls_alloc(struct regstat *current,int i)
1705 {
1706   //clear_const(current,rs1[i]); // FIXME
1707   clear_const(current,rt1[i]);
1708   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1709   alloc_reg(current,i,CSREG); // Status
1710   alloc_reg(current,i,FTEMP);
1711   if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1712     alloc_reg64(current,i,FTEMP);
1713   }
1714   // If using TLB, need a register for pointer to the mapping table
1715   if(using_tlb) alloc_reg(current,i,TLREG);
1716   #if defined(HOST_IMM8)
1717   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1718   else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1719     alloc_reg(current,i,INVCP);
1720   #endif
1721   // We need a temporary register for address generation
1722   alloc_reg_temp(current,i,-1);
1723 }
1724
1725 void c2ls_alloc(struct regstat *current,int i)
1726 {
1727   clear_const(current,rt1[i]);
1728   if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1729   alloc_reg(current,i,FTEMP);
1730   // If using TLB, need a register for pointer to the mapping table
1731   if(using_tlb) alloc_reg(current,i,TLREG);
1732   #if defined(HOST_IMM8)
1733   // On CPUs without 32-bit immediates we need a pointer to invalid_code
1734   else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1735     alloc_reg(current,i,INVCP);
1736   #endif
1737   // We need a temporary register for address generation
1738   alloc_reg_temp(current,i,-1);
1739   minimum_free_regs[i]=1;
1740 }
1741
1742 #ifndef multdiv_alloc
1743 void multdiv_alloc(struct regstat *current,int i)
1744 {
1745   //  case 0x18: MULT
1746   //  case 0x19: MULTU
1747   //  case 0x1A: DIV
1748   //  case 0x1B: DIVU
1749   //  case 0x1C: DMULT
1750   //  case 0x1D: DMULTU
1751   //  case 0x1E: DDIV
1752   //  case 0x1F: DDIVU
1753   clear_const(current,rs1[i]);
1754   clear_const(current,rs2[i]);
1755   if(rs1[i]&&rs2[i])
1756   {
1757     if((opcode2[i]&4)==0) // 32-bit
1758     {
1759       current->u&=~(1LL<<HIREG);
1760       current->u&=~(1LL<<LOREG);
1761       alloc_reg(current,i,HIREG);
1762       alloc_reg(current,i,LOREG);
1763       alloc_reg(current,i,rs1[i]);
1764       alloc_reg(current,i,rs2[i]);
1765       current->is32|=1LL<<HIREG;
1766       current->is32|=1LL<<LOREG;
1767       dirty_reg(current,HIREG);
1768       dirty_reg(current,LOREG);
1769     }
1770     else // 64-bit
1771     {
1772       current->u&=~(1LL<<HIREG);
1773       current->u&=~(1LL<<LOREG);
1774       current->uu&=~(1LL<<HIREG);
1775       current->uu&=~(1LL<<LOREG);
1776       alloc_reg64(current,i,HIREG);
1777       //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1778       alloc_reg64(current,i,rs1[i]);
1779       alloc_reg64(current,i,rs2[i]);
1780       alloc_all(current,i);
1781       current->is32&=~(1LL<<HIREG);
1782       current->is32&=~(1LL<<LOREG);
1783       dirty_reg(current,HIREG);
1784       dirty_reg(current,LOREG);
1785       minimum_free_regs[i]=HOST_REGS;
1786     }
1787   }
1788   else
1789   {
1790     // Multiply by zero is zero.
1791     // MIPS does not have a divide by zero exception.
1792     // The result is undefined, we return zero.
1793     alloc_reg(current,i,HIREG);
1794     alloc_reg(current,i,LOREG);
1795     current->is32|=1LL<<HIREG;
1796     current->is32|=1LL<<LOREG;
1797     dirty_reg(current,HIREG);
1798     dirty_reg(current,LOREG);
1799   }
1800 }
1801 #endif
1802
1803 void cop0_alloc(struct regstat *current,int i)
1804 {
1805   if(opcode2[i]==0) // MFC0
1806   {
1807     if(rt1[i]) {
1808       clear_const(current,rt1[i]);
1809       alloc_all(current,i);
1810       alloc_reg(current,i,rt1[i]);
1811       current->is32|=1LL<<rt1[i];
1812       dirty_reg(current,rt1[i]);
1813     }
1814   }
1815   else if(opcode2[i]==4) // MTC0
1816   {
1817     if(rs1[i]){
1818       clear_const(current,rs1[i]);
1819       alloc_reg(current,i,rs1[i]);
1820       alloc_all(current,i);
1821     }
1822     else {
1823       alloc_all(current,i); // FIXME: Keep r0
1824       current->u&=~1LL;
1825       alloc_reg(current,i,0);
1826     }
1827   }
1828   else
1829   {
1830     // TLBR/TLBWI/TLBWR/TLBP/ERET
1831     assert(opcode2[i]==0x10);
1832     alloc_all(current,i);
1833   }
1834   minimum_free_regs[i]=HOST_REGS;
1835 }
1836
1837 void cop1_alloc(struct regstat *current,int i)
1838 {
1839   alloc_reg(current,i,CSREG); // Load status
1840   if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1841   {
1842     if(rt1[i]){
1843       clear_const(current,rt1[i]);
1844       if(opcode2[i]==1) {
1845         alloc_reg64(current,i,rt1[i]); // DMFC1
1846         current->is32&=~(1LL<<rt1[i]);
1847       }else{
1848         alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1849         current->is32|=1LL<<rt1[i];
1850       }
1851       dirty_reg(current,rt1[i]);
1852     }
1853     alloc_reg_temp(current,i,-1);
1854   }
1855   else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1856   {
1857     if(rs1[i]){
1858       clear_const(current,rs1[i]);
1859       if(opcode2[i]==5)
1860         alloc_reg64(current,i,rs1[i]); // DMTC1
1861       else
1862         alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1863       alloc_reg_temp(current,i,-1);
1864     }
1865     else {
1866       current->u&=~1LL;
1867       alloc_reg(current,i,0);
1868       alloc_reg_temp(current,i,-1);
1869     }
1870   }
1871   minimum_free_regs[i]=1;
1872 }
1873 void fconv_alloc(struct regstat *current,int i)
1874 {
1875   alloc_reg(current,i,CSREG); // Load status
1876   alloc_reg_temp(current,i,-1);
1877   minimum_free_regs[i]=1;
1878 }
1879 void float_alloc(struct regstat *current,int i)
1880 {
1881   alloc_reg(current,i,CSREG); // Load status
1882   alloc_reg_temp(current,i,-1);
1883   minimum_free_regs[i]=1;
1884 }
1885 void c2op_alloc(struct regstat *current,int i)
1886 {
1887   alloc_reg_temp(current,i,-1);
1888 }
1889 void fcomp_alloc(struct regstat *current,int i)
1890 {
1891   alloc_reg(current,i,CSREG); // Load status
1892   alloc_reg(current,i,FSREG); // Load flags
1893   dirty_reg(current,FSREG); // Flag will be modified
1894   alloc_reg_temp(current,i,-1);
1895   minimum_free_regs[i]=1;
1896 }
1897
1898 void syscall_alloc(struct regstat *current,int i)
1899 {
1900   alloc_cc(current,i);
1901   dirty_reg(current,CCREG);
1902   alloc_all(current,i);
1903   minimum_free_regs[i]=HOST_REGS;
1904   current->isconst=0;
1905 }
1906
1907 void delayslot_alloc(struct regstat *current,int i)
1908 {
1909   switch(itype[i]) {
1910     case UJUMP:
1911     case CJUMP:
1912     case SJUMP:
1913     case RJUMP:
1914     case FJUMP:
1915     case SYSCALL:
1916     case HLECALL:
1917     case SPAN:
1918       assem_debug("jump in the delay slot.  this shouldn't happen.\n");//exit(1);
1919       SysPrintf("Disabled speculative precompilation\n");
1920       stop_after_jal=1;
1921       break;
1922     case IMM16:
1923       imm16_alloc(current,i);
1924       break;
1925     case LOAD:
1926     case LOADLR:
1927       load_alloc(current,i);
1928       break;
1929     case STORE:
1930     case STORELR:
1931       store_alloc(current,i);
1932       break;
1933     case ALU:
1934       alu_alloc(current,i);
1935       break;
1936     case SHIFT:
1937       shift_alloc(current,i);
1938       break;
1939     case MULTDIV:
1940       multdiv_alloc(current,i);
1941       break;
1942     case SHIFTIMM:
1943       shiftimm_alloc(current,i);
1944       break;
1945     case MOV:
1946       mov_alloc(current,i);
1947       break;
1948     case COP0:
1949       cop0_alloc(current,i);
1950       break;
1951     case COP1:
1952     case COP2:
1953       cop1_alloc(current,i);
1954       break;
1955     case C1LS:
1956       c1ls_alloc(current,i);
1957       break;
1958     case C2LS:
1959       c2ls_alloc(current,i);
1960       break;
1961     case FCONV:
1962       fconv_alloc(current,i);
1963       break;
1964     case FLOAT:
1965       float_alloc(current,i);
1966       break;
1967     case FCOMP:
1968       fcomp_alloc(current,i);
1969       break;
1970     case C2OP:
1971       c2op_alloc(current,i);
1972       break;
1973   }
1974 }
1975
1976 // Special case where a branch and delay slot span two pages in virtual memory
1977 static void pagespan_alloc(struct regstat *current,int i)
1978 {
1979   current->isconst=0;
1980   current->wasconst=0;
1981   regs[i].wasconst=0;
1982   minimum_free_regs[i]=HOST_REGS;
1983   alloc_all(current,i);
1984   alloc_cc(current,i);
1985   dirty_reg(current,CCREG);
1986   if(opcode[i]==3) // JAL
1987   {
1988     alloc_reg(current,i,31);
1989     dirty_reg(current,31);
1990   }
1991   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1992   {
1993     alloc_reg(current,i,rs1[i]);
1994     if (rt1[i]!=0) {
1995       alloc_reg(current,i,rt1[i]);
1996       dirty_reg(current,rt1[i]);
1997     }
1998   }
1999   if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2000   {
2001     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2002     if(rs2[i]) alloc_reg(current,i,rs2[i]);
2003     if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2004     {
2005       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2006       if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2007     }
2008   }
2009   else
2010   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2011   {
2012     if(rs1[i]) alloc_reg(current,i,rs1[i]);
2013     if(!((current->is32>>rs1[i])&1))
2014     {
2015       if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2016     }
2017   }
2018   else
2019   if(opcode[i]==0x11) // BC1
2020   {
2021     alloc_reg(current,i,FSREG);
2022     alloc_reg(current,i,CSREG);
2023   }
2024   //else ...
2025 }
2026
2027 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2028 {
2029   stubs[stubcount][0]=type;
2030   stubs[stubcount][1]=addr;
2031   stubs[stubcount][2]=retaddr;
2032   stubs[stubcount][3]=a;
2033   stubs[stubcount][4]=b;
2034   stubs[stubcount][5]=c;
2035   stubs[stubcount][6]=d;
2036   stubs[stubcount][7]=e;
2037   stubcount++;
2038 }
2039
2040 // Write out a single register
2041 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2042 {
2043   int hr;
2044   for(hr=0;hr<HOST_REGS;hr++) {
2045     if(hr!=EXCLUDE_REG) {
2046       if((regmap[hr]&63)==r) {
2047         if((dirty>>hr)&1) {
2048           if(regmap[hr]<64) {
2049             emit_storereg(r,hr);
2050 #ifndef FORCE32
2051             if((is32>>regmap[hr])&1) {
2052               emit_sarimm(hr,31,hr);
2053               emit_storereg(r|64,hr);
2054             }
2055 #endif
2056           }else{
2057             emit_storereg(r|64,hr);
2058           }
2059         }
2060       }
2061     }
2062   }
2063 }
2064
2065 int mchecksum()
2066 {
2067   //if(!tracedebug) return 0;
2068   int i;
2069   int sum=0;
2070   for(i=0;i<2097152;i++) {
2071     unsigned int temp=sum;
2072     sum<<=1;
2073     sum|=(~temp)>>31;
2074     sum^=((u_int *)rdram)[i];
2075   }
2076   return sum;
2077 }
2078 int rchecksum()
2079 {
2080   int i;
2081   int sum=0;
2082   for(i=0;i<64;i++)
2083     sum^=((u_int *)reg)[i];
2084   return sum;
2085 }
2086 void rlist()
2087 {
2088   int i;
2089   printf("TRACE: ");
2090   for(i=0;i<32;i++)
2091     printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2092   printf("\n");
2093 #ifndef DISABLE_COP1
2094   printf("TRACE: ");
2095   for(i=0;i<32;i++)
2096     printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2097   printf("\n");
2098 #endif
2099 }
2100
2101 void enabletrace()
2102 {
2103   tracedebug=1;
2104 }
2105
2106 void memdebug(int i)
2107 {
2108   //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2109   //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2110   //rlist();
2111   //if(tracedebug) {
2112   //if(Count>=-2084597794) {
2113   if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2114   //if(0) {
2115     printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2116     //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2117     //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2118     rlist();
2119     #ifdef __i386__
2120     printf("TRACE: %x\n",(&i)[-1]);
2121     #endif
2122     #ifdef __arm__
2123     int j;
2124     printf("TRACE: %x \n",(&j)[10]);
2125     printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2126     #endif
2127     //fflush(stdout);
2128   }
2129   //printf("TRACE: %x\n",(&i)[-1]);
2130 }
2131
2132 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2133 {
2134   printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2135 }
2136
2137 void alu_assemble(int i,struct regstat *i_regs)
2138 {
2139   if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2140     if(rt1[i]) {
2141       signed char s1,s2,t;
2142       t=get_reg(i_regs->regmap,rt1[i]);
2143       if(t>=0) {
2144         s1=get_reg(i_regs->regmap,rs1[i]);
2145         s2=get_reg(i_regs->regmap,rs2[i]);
2146         if(rs1[i]&&rs2[i]) {
2147           assert(s1>=0);
2148           assert(s2>=0);
2149           if(opcode2[i]&2) emit_sub(s1,s2,t);
2150           else emit_add(s1,s2,t);
2151         }
2152         else if(rs1[i]) {
2153           if(s1>=0) emit_mov(s1,t);
2154           else emit_loadreg(rs1[i],t);
2155         }
2156         else if(rs2[i]) {
2157           if(s2>=0) {
2158             if(opcode2[i]&2) emit_neg(s2,t);
2159             else emit_mov(s2,t);
2160           }
2161           else {
2162             emit_loadreg(rs2[i],t);
2163             if(opcode2[i]&2) emit_neg(t,t);
2164           }
2165         }
2166         else emit_zeroreg(t);
2167       }
2168     }
2169   }
2170   if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2171     if(rt1[i]) {
2172       signed char s1l,s2l,s1h,s2h,tl,th;
2173       tl=get_reg(i_regs->regmap,rt1[i]);
2174       th=get_reg(i_regs->regmap,rt1[i]|64);
2175       if(tl>=0) {
2176         s1l=get_reg(i_regs->regmap,rs1[i]);
2177         s2l=get_reg(i_regs->regmap,rs2[i]);
2178         s1h=get_reg(i_regs->regmap,rs1[i]|64);
2179         s2h=get_reg(i_regs->regmap,rs2[i]|64);
2180         if(rs1[i]&&rs2[i]) {
2181           assert(s1l>=0);
2182           assert(s2l>=0);
2183           if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2184           else emit_adds(s1l,s2l,tl);
2185           if(th>=0) {
2186             #ifdef INVERTED_CARRY
2187             if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2188             #else
2189             if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2190             #endif
2191             else emit_add(s1h,s2h,th);
2192           }
2193         }
2194         else if(rs1[i]) {
2195           if(s1l>=0) emit_mov(s1l,tl);
2196           else emit_loadreg(rs1[i],tl);
2197           if(th>=0) {
2198             if(s1h>=0) emit_mov(s1h,th);
2199             else emit_loadreg(rs1[i]|64,th);
2200           }
2201         }
2202         else if(rs2[i]) {
2203           if(s2l>=0) {
2204             if(opcode2[i]&2) emit_negs(s2l,tl);
2205             else emit_mov(s2l,tl);
2206           }
2207           else {
2208             emit_loadreg(rs2[i],tl);
2209             if(opcode2[i]&2) emit_negs(tl,tl);
2210           }
2211           if(th>=0) {
2212             #ifdef INVERTED_CARRY
2213             if(s2h>=0) emit_mov(s2h,th);
2214             else emit_loadreg(rs2[i]|64,th);
2215             if(opcode2[i]&2) {
2216               emit_adcimm(-1,th); // x86 has inverted carry flag
2217               emit_not(th,th);
2218             }
2219             #else
2220             if(opcode2[i]&2) {
2221               if(s2h>=0) emit_rscimm(s2h,0,th);
2222               else {
2223                 emit_loadreg(rs2[i]|64,th);
2224                 emit_rscimm(th,0,th);
2225               }
2226             }else{
2227               if(s2h>=0) emit_mov(s2h,th);
2228               else emit_loadreg(rs2[i]|64,th);
2229             }
2230             #endif
2231           }
2232         }
2233         else {
2234           emit_zeroreg(tl);
2235           if(th>=0) emit_zeroreg(th);
2236         }
2237       }
2238     }
2239   }
2240   if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2241     if(rt1[i]) {
2242       signed char s1l,s1h,s2l,s2h,t;
2243       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2244       {
2245         t=get_reg(i_regs->regmap,rt1[i]);
2246         //assert(t>=0);
2247         if(t>=0) {
2248           s1l=get_reg(i_regs->regmap,rs1[i]);
2249           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2250           s2l=get_reg(i_regs->regmap,rs2[i]);
2251           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2252           if(rs2[i]==0) // rx<r0
2253           {
2254             assert(s1h>=0);
2255             if(opcode2[i]==0x2a) // SLT
2256               emit_shrimm(s1h,31,t);
2257             else // SLTU (unsigned can not be less than zero)
2258               emit_zeroreg(t);
2259           }
2260           else if(rs1[i]==0) // r0<rx
2261           {
2262             assert(s2h>=0);
2263             if(opcode2[i]==0x2a) // SLT
2264               emit_set_gz64_32(s2h,s2l,t);
2265             else // SLTU (set if not zero)
2266               emit_set_nz64_32(s2h,s2l,t);
2267           }
2268           else {
2269             assert(s1l>=0);assert(s1h>=0);
2270             assert(s2l>=0);assert(s2h>=0);
2271             if(opcode2[i]==0x2a) // SLT
2272               emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2273             else // SLTU
2274               emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2275           }
2276         }
2277       } else {
2278         t=get_reg(i_regs->regmap,rt1[i]);
2279         //assert(t>=0);
2280         if(t>=0) {
2281           s1l=get_reg(i_regs->regmap,rs1[i]);
2282           s2l=get_reg(i_regs->regmap,rs2[i]);
2283           if(rs2[i]==0) // rx<r0
2284           {
2285             assert(s1l>=0);
2286             if(opcode2[i]==0x2a) // SLT
2287               emit_shrimm(s1l,31,t);
2288             else // SLTU (unsigned can not be less than zero)
2289               emit_zeroreg(t);
2290           }
2291           else if(rs1[i]==0) // r0<rx
2292           {
2293             assert(s2l>=0);
2294             if(opcode2[i]==0x2a) // SLT
2295               emit_set_gz32(s2l,t);
2296             else // SLTU (set if not zero)
2297               emit_set_nz32(s2l,t);
2298           }
2299           else{
2300             assert(s1l>=0);assert(s2l>=0);
2301             if(opcode2[i]==0x2a) // SLT
2302               emit_set_if_less32(s1l,s2l,t);
2303             else // SLTU
2304               emit_set_if_carry32(s1l,s2l,t);
2305           }
2306         }
2307       }
2308     }
2309   }
2310   if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2311     if(rt1[i]) {
2312       signed char s1l,s1h,s2l,s2h,th,tl;
2313       tl=get_reg(i_regs->regmap,rt1[i]);
2314       th=get_reg(i_regs->regmap,rt1[i]|64);
2315       if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2316       {
2317         assert(tl>=0);
2318         if(tl>=0) {
2319           s1l=get_reg(i_regs->regmap,rs1[i]);
2320           s1h=get_reg(i_regs->regmap,rs1[i]|64);
2321           s2l=get_reg(i_regs->regmap,rs2[i]);
2322           s2h=get_reg(i_regs->regmap,rs2[i]|64);
2323           if(rs1[i]&&rs2[i]) {
2324             assert(s1l>=0);assert(s1h>=0);
2325             assert(s2l>=0);assert(s2h>=0);
2326             if(opcode2[i]==0x24) { // AND
2327               emit_and(s1l,s2l,tl);
2328               emit_and(s1h,s2h,th);
2329             } else
2330             if(opcode2[i]==0x25) { // OR
2331               emit_or(s1l,s2l,tl);
2332               emit_or(s1h,s2h,th);
2333             } else
2334             if(opcode2[i]==0x26) { // XOR
2335               emit_xor(s1l,s2l,tl);
2336               emit_xor(s1h,s2h,th);
2337             } else
2338             if(opcode2[i]==0x27) { // NOR
2339               emit_or(s1l,s2l,tl);
2340               emit_or(s1h,s2h,th);
2341               emit_not(tl,tl);
2342               emit_not(th,th);
2343             }
2344           }
2345           else
2346           {
2347             if(opcode2[i]==0x24) { // AND
2348               emit_zeroreg(tl);
2349               emit_zeroreg(th);
2350             } else
2351             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2352               if(rs1[i]){
2353                 if(s1l>=0) emit_mov(s1l,tl);
2354                 else emit_loadreg(rs1[i],tl);
2355                 if(s1h>=0) emit_mov(s1h,th);
2356                 else emit_loadreg(rs1[i]|64,th);
2357               }
2358               else
2359               if(rs2[i]){
2360                 if(s2l>=0) emit_mov(s2l,tl);
2361                 else emit_loadreg(rs2[i],tl);
2362                 if(s2h>=0) emit_mov(s2h,th);
2363                 else emit_loadreg(rs2[i]|64,th);
2364               }
2365               else{
2366                 emit_zeroreg(tl);
2367                 emit_zeroreg(th);
2368               }
2369             } else
2370             if(opcode2[i]==0x27) { // NOR
2371               if(rs1[i]){
2372                 if(s1l>=0) emit_not(s1l,tl);
2373                 else{
2374                   emit_loadreg(rs1[i],tl);
2375                   emit_not(tl,tl);
2376                 }
2377                 if(s1h>=0) emit_not(s1h,th);
2378                 else{
2379                   emit_loadreg(rs1[i]|64,th);
2380                   emit_not(th,th);
2381                 }
2382               }
2383               else
2384               if(rs2[i]){
2385                 if(s2l>=0) emit_not(s2l,tl);
2386                 else{
2387                   emit_loadreg(rs2[i],tl);
2388                   emit_not(tl,tl);
2389                 }
2390                 if(s2h>=0) emit_not(s2h,th);
2391                 else{
2392                   emit_loadreg(rs2[i]|64,th);
2393                   emit_not(th,th);
2394                 }
2395               }
2396               else {
2397                 emit_movimm(-1,tl);
2398                 emit_movimm(-1,th);
2399               }
2400             }
2401           }
2402         }
2403       }
2404       else
2405       {
2406         // 32 bit
2407         if(tl>=0) {
2408           s1l=get_reg(i_regs->regmap,rs1[i]);
2409           s2l=get_reg(i_regs->regmap,rs2[i]);
2410           if(rs1[i]&&rs2[i]) {
2411             assert(s1l>=0);
2412             assert(s2l>=0);
2413             if(opcode2[i]==0x24) { // AND
2414               emit_and(s1l,s2l,tl);
2415             } else
2416             if(opcode2[i]==0x25) { // OR
2417               emit_or(s1l,s2l,tl);
2418             } else
2419             if(opcode2[i]==0x26) { // XOR
2420               emit_xor(s1l,s2l,tl);
2421             } else
2422             if(opcode2[i]==0x27) { // NOR
2423               emit_or(s1l,s2l,tl);
2424               emit_not(tl,tl);
2425             }
2426           }
2427           else
2428           {
2429             if(opcode2[i]==0x24) { // AND
2430               emit_zeroreg(tl);
2431             } else
2432             if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2433               if(rs1[i]){
2434                 if(s1l>=0) emit_mov(s1l,tl);
2435                 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2436               }
2437               else
2438               if(rs2[i]){
2439                 if(s2l>=0) emit_mov(s2l,tl);
2440                 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2441               }
2442               else emit_zeroreg(tl);
2443             } else
2444             if(opcode2[i]==0x27) { // NOR
2445               if(rs1[i]){
2446                 if(s1l>=0) emit_not(s1l,tl);
2447                 else {
2448                   emit_loadreg(rs1[i],tl);
2449                   emit_not(tl,tl);
2450                 }
2451               }
2452               else
2453               if(rs2[i]){
2454                 if(s2l>=0) emit_not(s2l,tl);
2455                 else {
2456                   emit_loadreg(rs2[i],tl);
2457                   emit_not(tl,tl);
2458                 }
2459               }
2460               else emit_movimm(-1,tl);
2461             }
2462           }
2463         }
2464       }
2465     }
2466   }
2467 }
2468
2469 void imm16_assemble(int i,struct regstat *i_regs)
2470 {
2471   if (opcode[i]==0x0f) { // LUI
2472     if(rt1[i]) {
2473       signed char t;
2474       t=get_reg(i_regs->regmap,rt1[i]);
2475       //assert(t>=0);
2476       if(t>=0) {
2477         if(!((i_regs->isconst>>t)&1))
2478           emit_movimm(imm[i]<<16,t);
2479       }
2480     }
2481   }
2482   if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2483     if(rt1[i]) {
2484       signed char s,t;
2485       t=get_reg(i_regs->regmap,rt1[i]);
2486       s=get_reg(i_regs->regmap,rs1[i]);
2487       if(rs1[i]) {
2488         //assert(t>=0);
2489         //assert(s>=0);
2490         if(t>=0) {
2491           if(!((i_regs->isconst>>t)&1)) {
2492             if(s<0) {
2493               if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2494               emit_addimm(t,imm[i],t);
2495             }else{
2496               if(!((i_regs->wasconst>>s)&1))
2497                 emit_addimm(s,imm[i],t);
2498               else
2499                 emit_movimm(constmap[i][s]+imm[i],t);
2500             }
2501           }
2502         }
2503       } else {
2504         if(t>=0) {
2505           if(!((i_regs->isconst>>t)&1))
2506             emit_movimm(imm[i],t);
2507         }
2508       }
2509     }
2510   }
2511   if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2512     if(rt1[i]) {
2513       signed char sh,sl,th,tl;
2514       th=get_reg(i_regs->regmap,rt1[i]|64);
2515       tl=get_reg(i_regs->regmap,rt1[i]);
2516       sh=get_reg(i_regs->regmap,rs1[i]|64);
2517       sl=get_reg(i_regs->regmap,rs1[i]);
2518       if(tl>=0) {
2519         if(rs1[i]) {
2520           assert(sh>=0);
2521           assert(sl>=0);
2522           if(th>=0) {
2523             emit_addimm64_32(sh,sl,imm[i],th,tl);
2524           }
2525           else {
2526             emit_addimm(sl,imm[i],tl);
2527           }
2528         } else {
2529           emit_movimm(imm[i],tl);
2530           if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2531         }
2532       }
2533     }
2534   }
2535   else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2536     if(rt1[i]) {
2537       //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2538       signed char sh,sl,t;
2539       t=get_reg(i_regs->regmap,rt1[i]);
2540       sh=get_reg(i_regs->regmap,rs1[i]|64);
2541       sl=get_reg(i_regs->regmap,rs1[i]);
2542       //assert(t>=0);
2543       if(t>=0) {
2544         if(rs1[i]>0) {
2545           if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2546           if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2547             if(opcode[i]==0x0a) { // SLTI
2548               if(sl<0) {
2549                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2550                 emit_slti32(t,imm[i],t);
2551               }else{
2552                 emit_slti32(sl,imm[i],t);
2553               }
2554             }
2555             else { // SLTIU
2556               if(sl<0) {
2557                 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2558                 emit_sltiu32(t,imm[i],t);
2559               }else{
2560                 emit_sltiu32(sl,imm[i],t);
2561               }
2562             }
2563           }else{ // 64-bit
2564             assert(sl>=0);
2565             if(opcode[i]==0x0a) // SLTI
2566               emit_slti64_32(sh,sl,imm[i],t);
2567             else // SLTIU
2568               emit_sltiu64_32(sh,sl,imm[i],t);
2569           }
2570         }else{
2571           // SLTI(U) with r0 is just stupid,
2572           // nonetheless examples can be found
2573           if(opcode[i]==0x0a) // SLTI
2574             if(0<imm[i]) emit_movimm(1,t);
2575             else emit_zeroreg(t);
2576           else // SLTIU
2577           {
2578             if(imm[i]) emit_movimm(1,t);
2579             else emit_zeroreg(t);
2580           }
2581         }
2582       }
2583     }
2584   }
2585   else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2586     if(rt1[i]) {
2587       signed char sh,sl,th,tl;
2588       th=get_reg(i_regs->regmap,rt1[i]|64);
2589       tl=get_reg(i_regs->regmap,rt1[i]);
2590       sh=get_reg(i_regs->regmap,rs1[i]|64);
2591       sl=get_reg(i_regs->regmap,rs1[i]);
2592       if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2593         if(opcode[i]==0x0c) //ANDI
2594         {
2595           if(rs1[i]) {
2596             if(sl<0) {
2597               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2598               emit_andimm(tl,imm[i],tl);
2599             }else{
2600               if(!((i_regs->wasconst>>sl)&1))
2601                 emit_andimm(sl,imm[i],tl);
2602               else
2603                 emit_movimm(constmap[i][sl]&imm[i],tl);
2604             }
2605           }
2606           else
2607             emit_zeroreg(tl);
2608           if(th>=0) emit_zeroreg(th);
2609         }
2610         else
2611         {
2612           if(rs1[i]) {
2613             if(sl<0) {
2614               if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2615             }
2616             if(th>=0) {
2617               if(sh<0) {
2618                 emit_loadreg(rs1[i]|64,th);
2619               }else{
2620                 emit_mov(sh,th);
2621               }
2622             }
2623             if(opcode[i]==0x0d) //ORI
2624             if(sl<0) {
2625               emit_orimm(tl,imm[i],tl);
2626             }else{
2627               if(!((i_regs->wasconst>>sl)&1))
2628                 emit_orimm(sl,imm[i],tl);
2629               else
2630                 emit_movimm(constmap[i][sl]|imm[i],tl);
2631             }
2632             if(opcode[i]==0x0e) //XORI
2633             if(sl<0) {
2634               emit_xorimm(tl,imm[i],tl);
2635             }else{
2636               if(!((i_regs->wasconst>>sl)&1))
2637                 emit_xorimm(sl,imm[i],tl);
2638               else
2639                 emit_movimm(constmap[i][sl]^imm[i],tl);
2640             }
2641           }
2642           else {
2643             emit_movimm(imm[i],tl);
2644             if(th>=0) emit_zeroreg(th);
2645           }
2646         }
2647       }
2648     }
2649   }
2650 }
2651
2652 void shiftimm_assemble(int i,struct regstat *i_regs)
2653 {
2654   if(opcode2[i]<=0x3) // SLL/SRL/SRA
2655   {
2656     if(rt1[i]) {
2657       signed char s,t;
2658       t=get_reg(i_regs->regmap,rt1[i]);
2659       s=get_reg(i_regs->regmap,rs1[i]);
2660       //assert(t>=0);
2661       if(t>=0&&!((i_regs->isconst>>t)&1)){
2662         if(rs1[i]==0)
2663         {
2664           emit_zeroreg(t);
2665         }
2666         else
2667         {
2668           if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2669           if(imm[i]) {
2670             if(opcode2[i]==0) // SLL
2671             {
2672               emit_shlimm(s<0?t:s,imm[i],t);
2673             }
2674             if(opcode2[i]==2) // SRL
2675             {
2676               emit_shrimm(s<0?t:s,imm[i],t);
2677             }
2678             if(opcode2[i]==3) // SRA
2679             {
2680               emit_sarimm(s<0?t:s,imm[i],t);
2681             }
2682           }else{
2683             // Shift by zero
2684             if(s>=0 && s!=t) emit_mov(s,t);
2685           }
2686         }
2687       }
2688       //emit_storereg(rt1[i],t); //DEBUG
2689     }
2690   }
2691   if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2692   {
2693     if(rt1[i]) {
2694       signed char sh,sl,th,tl;
2695       th=get_reg(i_regs->regmap,rt1[i]|64);
2696       tl=get_reg(i_regs->regmap,rt1[i]);
2697       sh=get_reg(i_regs->regmap,rs1[i]|64);
2698       sl=get_reg(i_regs->regmap,rs1[i]);
2699       if(tl>=0) {
2700         if(rs1[i]==0)
2701         {
2702           emit_zeroreg(tl);
2703           if(th>=0) emit_zeroreg(th);
2704         }
2705         else
2706         {
2707           assert(sl>=0);
2708           assert(sh>=0);
2709           if(imm[i]) {
2710             if(opcode2[i]==0x38) // DSLL
2711             {
2712               if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2713               emit_shlimm(sl,imm[i],tl);
2714             }
2715             if(opcode2[i]==0x3a) // DSRL
2716             {
2717               emit_shrdimm(sl,sh,imm[i],tl);
2718               if(th>=0) emit_shrimm(sh,imm[i],th);
2719             }
2720             if(opcode2[i]==0x3b) // DSRA
2721             {
2722               emit_shrdimm(sl,sh,imm[i],tl);
2723               if(th>=0) emit_sarimm(sh,imm[i],th);
2724             }
2725           }else{
2726             // Shift by zero
2727             if(sl!=tl) emit_mov(sl,tl);
2728             if(th>=0&&sh!=th) emit_mov(sh,th);
2729           }
2730         }
2731       }
2732     }
2733   }
2734   if(opcode2[i]==0x3c) // DSLL32
2735   {
2736     if(rt1[i]) {
2737       signed char sl,tl,th;
2738       tl=get_reg(i_regs->regmap,rt1[i]);
2739       th=get_reg(i_regs->regmap,rt1[i]|64);
2740       sl=get_reg(i_regs->regmap,rs1[i]);
2741       if(th>=0||tl>=0){
2742         assert(tl>=0);
2743         assert(th>=0);
2744         assert(sl>=0);
2745         emit_mov(sl,th);
2746         emit_zeroreg(tl);
2747         if(imm[i]>32)
2748         {
2749           emit_shlimm(th,imm[i]&31,th);
2750         }
2751       }
2752     }
2753   }
2754   if(opcode2[i]==0x3e) // DSRL32
2755   {
2756     if(rt1[i]) {
2757       signed char sh,tl,th;
2758       tl=get_reg(i_regs->regmap,rt1[i]);
2759       th=get_reg(i_regs->regmap,rt1[i]|64);
2760       sh=get_reg(i_regs->regmap,rs1[i]|64);
2761       if(tl>=0){
2762         assert(sh>=0);
2763         emit_mov(sh,tl);
2764         if(th>=0) emit_zeroreg(th);
2765         if(imm[i]>32)
2766         {
2767           emit_shrimm(tl,imm[i]&31,tl);
2768         }
2769       }
2770     }
2771   }
2772   if(opcode2[i]==0x3f) // DSRA32
2773   {
2774     if(rt1[i]) {
2775       signed char sh,tl;
2776       tl=get_reg(i_regs->regmap,rt1[i]);
2777       sh=get_reg(i_regs->regmap,rs1[i]|64);
2778       if(tl>=0){
2779         assert(sh>=0);
2780         emit_mov(sh,tl);
2781         if(imm[i]>32)
2782         {
2783           emit_sarimm(tl,imm[i]&31,tl);
2784         }
2785       }
2786     }
2787   }
2788 }
2789
2790 #ifndef shift_assemble
2791 void shift_assemble(int i,struct regstat *i_regs)
2792 {
2793   printf("Need shift_assemble for this architecture.\n");
2794   exit(1);
2795 }
2796 #endif
2797
2798 void load_assemble(int i,struct regstat *i_regs)
2799 {
2800   int s,th,tl,addr,map=-1;
2801   int offset;
2802   int jaddr=0;
2803   int memtarget=0,c=0;
2804   int fastload_reg_override=0;
2805   u_int hr,reglist=0;
2806   th=get_reg(i_regs->regmap,rt1[i]|64);
2807   tl=get_reg(i_regs->regmap,rt1[i]);
2808   s=get_reg(i_regs->regmap,rs1[i]);
2809   offset=imm[i];
2810   for(hr=0;hr<HOST_REGS;hr++) {
2811     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2812   }
2813   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2814   if(s>=0) {
2815     c=(i_regs->wasconst>>s)&1;
2816     if (c) {
2817       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2818       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2819     }
2820   }
2821   //printf("load_assemble: c=%d\n",c);
2822   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2823   // FIXME: Even if the load is a NOP, we should check for pagefaults...
2824 #ifdef PCSX
2825   if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2826     ||rt1[i]==0) {
2827       // could be FIFO, must perform the read
2828       // ||dummy read
2829       assem_debug("(forced read)\n");
2830       tl=get_reg(i_regs->regmap,-1);
2831       assert(tl>=0);
2832   }
2833 #endif
2834   if(offset||s<0||c) addr=tl;
2835   else addr=s;
2836   //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2837  if(tl>=0) {
2838   //printf("load_assemble: c=%d\n",c);
2839   //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2840   assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2841   reglist&=~(1<<tl);
2842   if(th>=0) reglist&=~(1<<th);
2843   if(!using_tlb) {
2844     if(!c) {
2845       #ifdef RAM_OFFSET
2846       map=get_reg(i_regs->regmap,ROREG);
2847       if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2848       #endif
2849 //#define R29_HACK 1
2850       #ifdef R29_HACK
2851       // Strmnnrmn's speed hack
2852       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2853       #endif
2854       {
2855         jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2856       }
2857     }
2858     else if(ram_offset&&memtarget) {
2859       emit_addimm(addr,ram_offset,HOST_TEMPREG);
2860       fastload_reg_override=HOST_TEMPREG;
2861     }
2862   }else{ // using tlb
2863     int x=0;
2864     if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2865     if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2866     map=get_reg(i_regs->regmap,TLREG);
2867     assert(map>=0);
2868     reglist&=~(1<<map);
2869     map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2870     do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2871   }
2872   int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2873   if (opcode[i]==0x20) { // LB
2874     if(!c||memtarget) {
2875       if(!dummy) {
2876         #ifdef HOST_IMM_ADDR32
2877         if(c)
2878           emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2879         else
2880         #endif
2881         {
2882           //emit_xorimm(addr,3,tl);
2883           //gen_tlb_addr_r(tl,map);
2884           //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2885           int x=0,a=tl;
2886 #ifdef BIG_ENDIAN_MIPS
2887           if(!c) emit_xorimm(addr,3,tl);
2888           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2889 #else
2890           if(!c) a=addr;
2891 #endif
2892           if(fastload_reg_override) a=fastload_reg_override;
2893
2894           emit_movsbl_indexed_tlb(x,a,map,tl);
2895         }
2896       }
2897       if(jaddr)
2898         add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2899     }
2900     else
2901       inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2902   }
2903   if (opcode[i]==0x21) { // LH
2904     if(!c||memtarget) {
2905       if(!dummy) {
2906         #ifdef HOST_IMM_ADDR32
2907         if(c)
2908           emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2909         else
2910         #endif
2911         {
2912           int x=0,a=tl;
2913 #ifdef BIG_ENDIAN_MIPS
2914           if(!c) emit_xorimm(addr,2,tl);
2915           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2916 #else
2917           if(!c) a=addr;
2918 #endif
2919           if(fastload_reg_override) a=fastload_reg_override;
2920           //#ifdef
2921           //emit_movswl_indexed_tlb(x,tl,map,tl);
2922           //else
2923           if(map>=0) {
2924             gen_tlb_addr_r(a,map);
2925             emit_movswl_indexed(x,a,tl);
2926           }else{
2927             #if 1 //def RAM_OFFSET
2928             emit_movswl_indexed(x,a,tl);
2929             #else
2930             emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2931             #endif
2932           }
2933         }
2934       }
2935       if(jaddr)
2936         add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2937     }
2938     else
2939       inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2940   }
2941   if (opcode[i]==0x23) { // LW
2942     if(!c||memtarget) {
2943       if(!dummy) {
2944         int a=addr;
2945         if(fastload_reg_override) a=fastload_reg_override;
2946         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2947         #ifdef HOST_IMM_ADDR32
2948         if(c)
2949           emit_readword_tlb(constmap[i][s]+offset,map,tl);
2950         else
2951         #endif
2952         emit_readword_indexed_tlb(0,a,map,tl);
2953       }
2954       if(jaddr)
2955         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2956     }
2957     else
2958       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2959   }
2960   if (opcode[i]==0x24) { // LBU
2961     if(!c||memtarget) {
2962       if(!dummy) {
2963         #ifdef HOST_IMM_ADDR32
2964         if(c)
2965           emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2966         else
2967         #endif
2968         {
2969           //emit_xorimm(addr,3,tl);
2970           //gen_tlb_addr_r(tl,map);
2971           //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2972           int x=0,a=tl;
2973 #ifdef BIG_ENDIAN_MIPS
2974           if(!c) emit_xorimm(addr,3,tl);
2975           else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2976 #else
2977           if(!c) a=addr;
2978 #endif
2979           if(fastload_reg_override) a=fastload_reg_override;
2980
2981           emit_movzbl_indexed_tlb(x,a,map,tl);
2982         }
2983       }
2984       if(jaddr)
2985         add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2986     }
2987     else
2988       inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2989   }
2990   if (opcode[i]==0x25) { // LHU
2991     if(!c||memtarget) {
2992       if(!dummy) {
2993         #ifdef HOST_IMM_ADDR32
2994         if(c)
2995           emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2996         else
2997         #endif
2998         {
2999           int x=0,a=tl;
3000 #ifdef BIG_ENDIAN_MIPS
3001           if(!c) emit_xorimm(addr,2,tl);
3002           else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3003 #else
3004           if(!c) a=addr;
3005 #endif
3006           if(fastload_reg_override) a=fastload_reg_override;
3007           //#ifdef
3008           //emit_movzwl_indexed_tlb(x,tl,map,tl);
3009           //#else
3010           if(map>=0) {
3011             gen_tlb_addr_r(a,map);
3012             emit_movzwl_indexed(x,a,tl);
3013           }else{
3014             #if 1 //def RAM_OFFSET
3015             emit_movzwl_indexed(x,a,tl);
3016             #else
3017             emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3018             #endif
3019           }
3020         }
3021       }
3022       if(jaddr)
3023         add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3024     }
3025     else
3026       inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3027   }
3028   if (opcode[i]==0x27) { // LWU
3029     assert(th>=0);
3030     if(!c||memtarget) {
3031       if(!dummy) {
3032         int a=addr;
3033         if(fastload_reg_override) a=fastload_reg_override;
3034         //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3035         #ifdef HOST_IMM_ADDR32
3036         if(c)
3037           emit_readword_tlb(constmap[i][s]+offset,map,tl);
3038         else
3039         #endif
3040         emit_readword_indexed_tlb(0,a,map,tl);
3041       }
3042       if(jaddr)
3043         add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3044     }
3045     else {
3046       inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3047     }
3048     emit_zeroreg(th);
3049   }
3050   if (opcode[i]==0x37) { // LD
3051     if(!c||memtarget) {
3052       if(!dummy) {
3053         int a=addr;
3054         if(fastload_reg_override) a=fastload_reg_override;
3055         //gen_tlb_addr_r(tl,map);
3056         //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3057         //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3058         #ifdef HOST_IMM_ADDR32
3059         if(c)
3060           emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3061         else
3062         #endif
3063         emit_readdword_indexed_tlb(0,a,map,th,tl);
3064       }
3065       if(jaddr)
3066         add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3067     }
3068     else
3069       inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3070   }
3071  }
3072   //emit_storereg(rt1[i],tl); // DEBUG
3073   //if(opcode[i]==0x23)
3074   //if(opcode[i]==0x24)
3075   //if(opcode[i]==0x23||opcode[i]==0x24)
3076   /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3077   {
3078     //emit_pusha();
3079     save_regs(0x100f);
3080         emit_readword((int)&last_count,ECX);
3081         #ifdef __i386__
3082         if(get_reg(i_regs->regmap,CCREG)<0)
3083           emit_loadreg(CCREG,HOST_CCREG);
3084         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3085         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3086         emit_writeword(HOST_CCREG,(int)&Count);
3087         #endif
3088         #ifdef __arm__
3089         if(get_reg(i_regs->regmap,CCREG)<0)
3090           emit_loadreg(CCREG,0);
3091         else
3092           emit_mov(HOST_CCREG,0);
3093         emit_add(0,ECX,0);
3094         emit_addimm(0,2*ccadj[i],0);
3095         emit_writeword(0,(int)&Count);
3096         #endif
3097     emit_call((int)memdebug);
3098     //emit_popa();
3099     restore_regs(0x100f);
3100   }/**/
3101 }
3102
3103 #ifndef loadlr_assemble
3104 void loadlr_assemble(int i,struct regstat *i_regs)
3105 {
3106   printf("Need loadlr_assemble for this architecture.\n");
3107   exit(1);
3108 }
3109 #endif
3110
3111 void store_assemble(int i,struct regstat *i_regs)
3112 {
3113   int s,th,tl,map=-1;
3114   int addr,temp;
3115   int offset;
3116   int jaddr=0,jaddr2,type;
3117   int memtarget=0,c=0;
3118   int agr=AGEN1+(i&1);
3119   int faststore_reg_override=0;
3120   u_int hr,reglist=0;
3121   th=get_reg(i_regs->regmap,rs2[i]|64);
3122   tl=get_reg(i_regs->regmap,rs2[i]);
3123   s=get_reg(i_regs->regmap,rs1[i]);
3124   temp=get_reg(i_regs->regmap,agr);
3125   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3126   offset=imm[i];
3127   if(s>=0) {
3128     c=(i_regs->wasconst>>s)&1;
3129     if(c) {
3130       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3131       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3132     }
3133   }
3134   assert(tl>=0);
3135   assert(temp>=0);
3136   for(hr=0;hr<HOST_REGS;hr++) {
3137     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3138   }
3139   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3140   if(offset||s<0||c) addr=temp;
3141   else addr=s;
3142   if(!using_tlb) {
3143     if(!c) {
3144       #ifndef PCSX
3145       #ifdef R29_HACK
3146       // Strmnnrmn's speed hack
3147       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3148       #endif
3149       emit_cmpimm(addr,RAM_SIZE);
3150       #ifdef DESTRUCTIVE_SHIFT
3151       if(s==addr) emit_mov(s,temp);
3152       #endif
3153       #ifdef R29_HACK
3154       memtarget=1;
3155       if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3156       #endif
3157       {
3158         jaddr=(int)out;
3159         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3160         // Hint to branch predictor that the branch is unlikely to be taken
3161         if(rs1[i]>=28)
3162           emit_jno_unlikely(0);
3163         else
3164         #endif
3165         emit_jno(0);
3166       }
3167       #else
3168         jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3169       #endif
3170     }
3171     else if(ram_offset&&memtarget) {
3172       emit_addimm(addr,ram_offset,HOST_TEMPREG);
3173       faststore_reg_override=HOST_TEMPREG;
3174     }
3175   }else{ // using tlb
3176     int x=0;
3177     if (opcode[i]==0x28) x=3; // SB
3178     if (opcode[i]==0x29) x=2; // SH
3179     map=get_reg(i_regs->regmap,TLREG);
3180     assert(map>=0);
3181     reglist&=~(1<<map);
3182     map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3183     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3184   }
3185
3186   if (opcode[i]==0x28) { // SB
3187     if(!c||memtarget) {
3188       int x=0,a=temp;
3189 #ifdef BIG_ENDIAN_MIPS
3190       if(!c) emit_xorimm(addr,3,temp);
3191       else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3192 #else
3193       if(!c) a=addr;
3194 #endif
3195       if(faststore_reg_override) a=faststore_reg_override;
3196       //gen_tlb_addr_w(temp,map);
3197       //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3198       emit_writebyte_indexed_tlb(tl,x,a,map,a);
3199     }
3200     type=STOREB_STUB;
3201   }
3202   if (opcode[i]==0x29) { // SH
3203     if(!c||memtarget) {
3204       int x=0,a=temp;
3205 #ifdef BIG_ENDIAN_MIPS
3206       if(!c) emit_xorimm(addr,2,temp);
3207       else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3208 #else
3209       if(!c) a=addr;
3210 #endif
3211       if(faststore_reg_override) a=faststore_reg_override;
3212       //#ifdef
3213       //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3214       //#else
3215       if(map>=0) {
3216         gen_tlb_addr_w(a,map);
3217         emit_writehword_indexed(tl,x,a);
3218       }else
3219         //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3220         emit_writehword_indexed(tl,x,a);
3221     }
3222     type=STOREH_STUB;
3223   }
3224   if (opcode[i]==0x2B) { // SW
3225     if(!c||memtarget) {
3226       int a=addr;
3227       if(faststore_reg_override) a=faststore_reg_override;
3228       //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3229       emit_writeword_indexed_tlb(tl,0,a,map,temp);
3230     }
3231     type=STOREW_STUB;
3232   }
3233   if (opcode[i]==0x3F) { // SD
3234     if(!c||memtarget) {
3235       int a=addr;
3236       if(faststore_reg_override) a=faststore_reg_override;
3237       if(rs2[i]) {
3238         assert(th>=0);
3239         //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3240         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3241         emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3242       }else{
3243         // Store zero
3244         //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3245         //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3246         emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3247       }
3248     }
3249     type=STORED_STUB;
3250   }
3251 #ifdef PCSX
3252   if(jaddr) {
3253     // PCSX store handlers don't check invcode again
3254     reglist|=1<<addr;
3255     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3256     jaddr=0;
3257   }
3258 #endif
3259   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3260     if(!c||memtarget) {
3261       #ifdef DESTRUCTIVE_SHIFT
3262       // The x86 shift operation is 'destructive'; it overwrites the
3263       // source register, so we need to make a copy first and use that.
3264       addr=temp;
3265       #endif
3266       #if defined(HOST_IMM8)
3267       int ir=get_reg(i_regs->regmap,INVCP);
3268       assert(ir>=0);
3269       emit_cmpmem_indexedsr12_reg(ir,addr,1);
3270       #else
3271       emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3272       #endif
3273       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3274       emit_callne(invalidate_addr_reg[addr]);
3275       #else
3276       jaddr2=(int)out;
3277       emit_jne(0);
3278       add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3279       #endif
3280     }
3281   }
3282   u_int addr_val=constmap[i][s]+offset;
3283   if(jaddr) {
3284     add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3285   } else if(c&&!memtarget) {
3286     inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3287   }
3288   // basic current block modification detection..
3289   // not looking back as that should be in mips cache already
3290   if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3291     SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3292     assert(i_regs->regmap==regs[i].regmap); // not delay slot
3293     if(i_regs->regmap==regs[i].regmap) {
3294       load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3295       wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3296       emit_movimm(start+i*4+4,0);
3297       emit_writeword(0,(int)&pcaddr);
3298       emit_jmp((int)do_interrupt);
3299     }
3300   }
3301   //if(opcode[i]==0x2B || opcode[i]==0x3F)
3302   //if(opcode[i]==0x2B || opcode[i]==0x28)
3303   //if(opcode[i]==0x2B || opcode[i]==0x29)
3304   //if(opcode[i]==0x2B)
3305   /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3306   {
3307     #ifdef __i386__
3308     emit_pusha();
3309     #endif
3310     #ifdef __arm__
3311     save_regs(0x100f);
3312     #endif
3313         emit_readword((int)&last_count,ECX);
3314         #ifdef __i386__
3315         if(get_reg(i_regs->regmap,CCREG)<0)
3316           emit_loadreg(CCREG,HOST_CCREG);
3317         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3318         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3319         emit_writeword(HOST_CCREG,(int)&Count);
3320         #endif
3321         #ifdef __arm__
3322         if(get_reg(i_regs->regmap,CCREG)<0)
3323           emit_loadreg(CCREG,0);
3324         else
3325           emit_mov(HOST_CCREG,0);
3326         emit_add(0,ECX,0);
3327         emit_addimm(0,2*ccadj[i],0);
3328         emit_writeword(0,(int)&Count);
3329         #endif
3330     emit_call((int)memdebug);
3331     #ifdef __i386__
3332     emit_popa();
3333     #endif
3334     #ifdef __arm__
3335     restore_regs(0x100f);
3336     #endif
3337   }/**/
3338 }
3339
3340 void storelr_assemble(int i,struct regstat *i_regs)
3341 {
3342   int s,th,tl;
3343   int temp;
3344   int temp2;
3345   int offset;
3346   int jaddr=0,jaddr2;
3347   int case1,case2,case3;
3348   int done0,done1,done2;
3349   int memtarget=0,c=0;
3350   int agr=AGEN1+(i&1);
3351   u_int hr,reglist=0;
3352   th=get_reg(i_regs->regmap,rs2[i]|64);
3353   tl=get_reg(i_regs->regmap,rs2[i]);
3354   s=get_reg(i_regs->regmap,rs1[i]);
3355   temp=get_reg(i_regs->regmap,agr);
3356   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3357   offset=imm[i];
3358   if(s>=0) {
3359     c=(i_regs->isconst>>s)&1;
3360     if(c) {
3361       memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3362       if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3363     }
3364   }
3365   assert(tl>=0);
3366   for(hr=0;hr<HOST_REGS;hr++) {
3367     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3368   }
3369   assert(temp>=0);
3370   if(!using_tlb) {
3371     if(!c) {
3372       emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3373       if(!offset&&s!=temp) emit_mov(s,temp);
3374       jaddr=(int)out;
3375       emit_jno(0);
3376     }
3377     else
3378     {
3379       if(!memtarget||!rs1[i]) {
3380         jaddr=(int)out;
3381         emit_jmp(0);
3382       }
3383     }
3384     #ifdef RAM_OFFSET
3385     int map=get_reg(i_regs->regmap,ROREG);
3386     if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3387     gen_tlb_addr_w(temp,map);
3388     #else
3389     if((u_int)rdram!=0x80000000)
3390       emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3391     #endif
3392   }else{ // using tlb
3393     int map=get_reg(i_regs->regmap,TLREG);
3394     assert(map>=0);
3395     reglist&=~(1<<map);
3396     map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3397     if(!c&&!offset&&s>=0) emit_mov(s,temp);
3398     do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3399     if(!jaddr&&!memtarget) {
3400       jaddr=(int)out;
3401       emit_jmp(0);
3402     }
3403     gen_tlb_addr_w(temp,map);
3404   }
3405
3406   if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3407     temp2=get_reg(i_regs->regmap,FTEMP);
3408     if(!rs2[i]) temp2=th=tl;
3409   }
3410
3411 #ifndef BIG_ENDIAN_MIPS
3412     emit_xorimm(temp,3,temp);
3413 #endif
3414   emit_testimm(temp,2);
3415   case2=(int)out;
3416   emit_jne(0);
3417   emit_testimm(temp,1);
3418   case1=(int)out;
3419   emit_jne(0);
3420   // 0
3421   if (opcode[i]==0x2A) { // SWL
3422     emit_writeword_indexed(tl,0,temp);
3423   }
3424   if (opcode[i]==0x2E) { // SWR
3425     emit_writebyte_indexed(tl,3,temp);
3426   }
3427   if (opcode[i]==0x2C) { // SDL
3428     emit_writeword_indexed(th,0,temp);
3429     if(rs2[i]) emit_mov(tl,temp2);
3430   }
3431   if (opcode[i]==0x2D) { // SDR
3432     emit_writebyte_indexed(tl,3,temp);
3433     if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3434   }
3435   done0=(int)out;
3436   emit_jmp(0);
3437   // 1
3438   set_jump_target(case1,(int)out);
3439   if (opcode[i]==0x2A) { // SWL
3440     // Write 3 msb into three least significant bytes
3441     if(rs2[i]) emit_rorimm(tl,8,tl);
3442     emit_writehword_indexed(tl,-1,temp);
3443     if(rs2[i]) emit_rorimm(tl,16,tl);
3444     emit_writebyte_indexed(tl,1,temp);
3445     if(rs2[i]) emit_rorimm(tl,8,tl);
3446   }
3447   if (opcode[i]==0x2E) { // SWR
3448     // Write two lsb into two most significant bytes
3449     emit_writehword_indexed(tl,1,temp);
3450   }
3451   if (opcode[i]==0x2C) { // SDL
3452     if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3453     // Write 3 msb into three least significant bytes
3454     if(rs2[i]) emit_rorimm(th,8,th);
3455     emit_writehword_indexed(th,-1,temp);
3456     if(rs2[i]) emit_rorimm(th,16,th);
3457     emit_writebyte_indexed(th,1,temp);
3458     if(rs2[i]) emit_rorimm(th,8,th);
3459   }
3460   if (opcode[i]==0x2D) { // SDR
3461     if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3462     // Write two lsb into two most significant bytes
3463     emit_writehword_indexed(tl,1,temp);
3464   }
3465   done1=(int)out;
3466   emit_jmp(0);
3467   // 2
3468   set_jump_target(case2,(int)out);
3469   emit_testimm(temp,1);
3470   case3=(int)out;
3471   emit_jne(0);
3472   if (opcode[i]==0x2A) { // SWL
3473     // Write two msb into two least significant bytes
3474     if(rs2[i]) emit_rorimm(tl,16,tl);
3475     emit_writehword_indexed(tl,-2,temp);
3476     if(rs2[i]) emit_rorimm(tl,16,tl);
3477   }
3478   if (opcode[i]==0x2E) { // SWR
3479     // Write 3 lsb into three most significant bytes
3480     emit_writebyte_indexed(tl,-1,temp);
3481     if(rs2[i]) emit_rorimm(tl,8,tl);
3482     emit_writehword_indexed(tl,0,temp);
3483     if(rs2[i]) emit_rorimm(tl,24,tl);
3484   }
3485   if (opcode[i]==0x2C) { // SDL
3486     if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3487     // Write two msb into two least significant bytes
3488     if(rs2[i]) emit_rorimm(th,16,th);
3489     emit_writehword_indexed(th,-2,temp);
3490     if(rs2[i]) emit_rorimm(th,16,th);
3491   }
3492   if (opcode[i]==0x2D) { // SDR
3493     if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3494     // Write 3 lsb into three most significant bytes
3495     emit_writebyte_indexed(tl,-1,temp);
3496     if(rs2[i]) emit_rorimm(tl,8,tl);
3497     emit_writehword_indexed(tl,0,temp);
3498     if(rs2[i]) emit_rorimm(tl,24,tl);
3499   }
3500   done2=(int)out;
3501   emit_jmp(0);
3502   // 3
3503   set_jump_target(case3,(int)out);
3504   if (opcode[i]==0x2A) { // SWL
3505     // Write msb into least significant byte
3506     if(rs2[i]) emit_rorimm(tl,24,tl);
3507     emit_writebyte_indexed(tl,-3,temp);
3508     if(rs2[i]) emit_rorimm(tl,8,tl);
3509   }
3510   if (opcode[i]==0x2E) { // SWR
3511     // Write entire word
3512     emit_writeword_indexed(tl,-3,temp);
3513   }
3514   if (opcode[i]==0x2C) { // SDL
3515     if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3516     // Write msb into least significant byte
3517     if(rs2[i]) emit_rorimm(th,24,th);
3518     emit_writebyte_indexed(th,-3,temp);
3519     if(rs2[i]) emit_rorimm(th,8,th);
3520   }
3521   if (opcode[i]==0x2D) { // SDR
3522     if(rs2[i]) emit_mov(th,temp2);
3523     // Write entire word
3524     emit_writeword_indexed(tl,-3,temp);
3525   }
3526   set_jump_target(done0,(int)out);
3527   set_jump_target(done1,(int)out);
3528   set_jump_target(done2,(int)out);
3529   if (opcode[i]==0x2C) { // SDL
3530     emit_testimm(temp,4);
3531     done0=(int)out;
3532     emit_jne(0);
3533     emit_andimm(temp,~3,temp);
3534     emit_writeword_indexed(temp2,4,temp);
3535     set_jump_target(done0,(int)out);
3536   }
3537   if (opcode[i]==0x2D) { // SDR
3538     emit_testimm(temp,4);
3539     done0=(int)out;
3540     emit_jeq(0);
3541     emit_andimm(temp,~3,temp);
3542     emit_writeword_indexed(temp2,-4,temp);
3543     set_jump_target(done0,(int)out);
3544   }
3545   if(!c||!memtarget)
3546     add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3547   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3548     #ifdef RAM_OFFSET
3549     int map=get_reg(i_regs->regmap,ROREG);
3550     if(map<0) map=HOST_TEMPREG;
3551     gen_orig_addr_w(temp,map);
3552     #else
3553     emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3554     #endif
3555     #if defined(HOST_IMM8)
3556     int ir=get_reg(i_regs->regmap,INVCP);
3557     assert(ir>=0);
3558     emit_cmpmem_indexedsr12_reg(ir,temp,1);
3559     #else
3560     emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3561     #endif
3562     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3563     emit_callne(invalidate_addr_reg[temp]);
3564     #else
3565     jaddr2=(int)out;
3566     emit_jne(0);
3567     add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3568     #endif
3569   }
3570   /*
3571     emit_pusha();
3572     //save_regs(0x100f);
3573         emit_readword((int)&last_count,ECX);
3574         if(get_reg(i_regs->regmap,CCREG)<0)
3575           emit_loadreg(CCREG,HOST_CCREG);
3576         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3577         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3578         emit_writeword(HOST_CCREG,(int)&Count);
3579     emit_call((int)memdebug);
3580     emit_popa();
3581     //restore_regs(0x100f);
3582   /**/
3583 }
3584
3585 void c1ls_assemble(int i,struct regstat *i_regs)
3586 {
3587 #ifndef DISABLE_COP1
3588   int s,th,tl;
3589   int temp,ar;
3590   int map=-1;
3591   int offset;
3592   int c=0;
3593   int jaddr,jaddr2=0,jaddr3,type;
3594   int agr=AGEN1+(i&1);
3595   u_int hr,reglist=0;
3596   th=get_reg(i_regs->regmap,FTEMP|64);
3597   tl=get_reg(i_regs->regmap,FTEMP);
3598   s=get_reg(i_regs->regmap,rs1[i]);
3599   temp=get_reg(i_regs->regmap,agr);
3600   if(temp<0) temp=get_reg(i_regs->regmap,-1);
3601   offset=imm[i];
3602   assert(tl>=0);
3603   assert(rs1[i]>0);
3604   assert(temp>=0);
3605   for(hr=0;hr<HOST_REGS;hr++) {
3606     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3607   }
3608   if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3609   if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3610   {
3611     // Loads use a temporary register which we need to save
3612     reglist|=1<<temp;
3613   }
3614   if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3615     ar=temp;
3616   else // LWC1/LDC1
3617     ar=tl;
3618   //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3619   //else c=(i_regs->wasconst>>s)&1;
3620   if(s>=0) c=(i_regs->wasconst>>s)&1;
3621   // Check cop1 unusable
3622   if(!cop1_usable) {
3623     signed char rs=get_reg(i_regs->regmap,CSREG);
3624     assert(rs>=0);
3625     emit_testimm(rs,0x20000000);
3626     jaddr=(int)out;
3627     emit_jeq(0);
3628     add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3629     cop1_usable=1;
3630   }
3631   if (opcode[i]==0x39) { // SWC1 (get float address)
3632     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],tl);
3633   }
3634   if (opcode[i]==0x3D) { // SDC1 (get double address)
3635     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],tl);
3636   }
3637   // Generate address + offset
3638   if(!using_tlb) {
3639     if(!c)
3640       emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3641   }
3642   else
3643   {
3644     map=get_reg(i_regs->regmap,TLREG);
3645     assert(map>=0);
3646     reglist&=~(1<<map);
3647     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3648       map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3649     }
3650     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3651       map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3652     }
3653   }
3654   if (opcode[i]==0x39) { // SWC1 (read float)
3655     emit_readword_indexed(0,tl,tl);
3656   }
3657   if (opcode[i]==0x3D) { // SDC1 (read double)
3658     emit_readword_indexed(4,tl,th);
3659     emit_readword_indexed(0,tl,tl);
3660   }
3661   if (opcode[i]==0x31) { // LWC1 (get target address)
3662     emit_readword((int)&reg_cop1_simple[(source[i]>>16)&0x1f],temp);
3663   }
3664   if (opcode[i]==0x35) { // LDC1 (get target address)
3665     emit_readword((int)&reg_cop1_double[(source[i]>>16)&0x1f],temp);
3666   }
3667   if(!using_tlb) {
3668     if(!c) {
3669       jaddr2=(int)out;
3670       emit_jno(0);
3671     }
3672     else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3673       jaddr2=(int)out;
3674       emit_jmp(0); // inline_readstub/inline_writestub?  Very rare case
3675     }
3676     #ifdef DESTRUCTIVE_SHIFT
3677     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3678       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3679     }
3680     #endif
3681   }else{
3682     if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3683       do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3684     }
3685     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3686       do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3687     }
3688   }
3689   if (opcode[i]==0x31) { // LWC1
3690     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3691     //gen_tlb_addr_r(ar,map);
3692     //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3693     #ifdef HOST_IMM_ADDR32
3694     if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3695     else
3696     #endif
3697     emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3698     type=LOADW_STUB;
3699   }
3700   if (opcode[i]==0x35) { // LDC1
3701     assert(th>=0);
3702     //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3703     //gen_tlb_addr_r(ar,map);
3704     //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3705     //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3706     #ifdef HOST_IMM_ADDR32
3707     if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3708     else
3709     #endif
3710     emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3711     type=LOADD_STUB;
3712   }
3713   if (opcode[i]==0x39) { // SWC1
3714     //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3715     emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3716     type=STOREW_STUB;
3717   }
3718   if (opcode[i]==0x3D) { // SDC1
3719     assert(th>=0);
3720     //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3721     //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3722     emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3723     type=STORED_STUB;
3724   }
3725   if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3726     if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3727       #ifndef DESTRUCTIVE_SHIFT
3728       temp=offset||c||s<0?ar:s;
3729       #endif
3730       #if defined(HOST_IMM8)
3731       int ir=get_reg(i_regs->regmap,INVCP);
3732       assert(ir>=0);
3733       emit_cmpmem_indexedsr12_reg(ir,temp,1);
3734       #else
3735       emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3736       #endif
3737       #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3738       emit_callne(invalidate_addr_reg[temp]);
3739       #else
3740       jaddr3=(int)out;
3741       emit_jne(0);
3742       add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3743       #endif
3744     }
3745   }
3746   if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3747   if (opcode[i]==0x31) { // LWC1 (write float)
3748     emit_writeword_indexed(tl,0,temp);
3749   }
3750   if (opcode[i]==0x35) { // LDC1 (write double)
3751     emit_writeword_indexed(th,4,temp);
3752     emit_writeword_indexed(tl,0,temp);
3753   }
3754   //if(opcode[i]==0x39)
3755   /*if(opcode[i]==0x39||opcode[i]==0x31)
3756   {
3757     emit_pusha();
3758         emit_readword((int)&last_count,ECX);
3759         if(get_reg(i_regs->regmap,CCREG)<0)
3760           emit_loadreg(CCREG,HOST_CCREG);
3761         emit_add(HOST_CCREG,ECX,HOST_CCREG);
3762         emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3763         emit_writeword(HOST_CCREG,(int)&Count);
3764     emit_call((int)memdebug);
3765     emit_popa();
3766   }/**/
3767 #else
3768   cop1_unusable(i, i_regs);
3769 #endif
3770 }
3771
3772 void c2ls_assemble(int i,struct regstat *i_regs)
3773 {
3774   int s,tl;
3775   int ar;
3776   int offset;
3777   int memtarget=0,c=0;
3778   int jaddr2=0,jaddr3,type;
3779   int agr=AGEN1+(i&1);
3780   int fastio_reg_override=0;
3781   u_int hr,reglist=0;
3782   u_int copr=(source[i]>>16)&0x1f;
3783   s=get_reg(i_regs->regmap,rs1[i]);
3784   tl=get_reg(i_regs->regmap,FTEMP);
3785   offset=imm[i];
3786   assert(rs1[i]>0);
3787   assert(tl>=0);
3788   assert(!using_tlb);
3789
3790   for(hr=0;hr<HOST_REGS;hr++) {
3791     if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3792   }
3793   if(i_regs->regmap[HOST_CCREG]==CCREG)
3794     reglist&=~(1<<HOST_CCREG);
3795
3796   // get the address
3797   if (opcode[i]==0x3a) { // SWC2
3798     ar=get_reg(i_regs->regmap,agr);
3799     if(ar<0) ar=get_reg(i_regs->regmap,-1);
3800     reglist|=1<<ar;
3801   } else { // LWC2
3802     ar=tl;
3803   }
3804   if(s>=0) c=(i_regs->wasconst>>s)&1;
3805   memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3806   if (!offset&&!c&&s>=0) ar=s;
3807   assert(ar>=0);
3808
3809   if (opcode[i]==0x3a) { // SWC2
3810     cop2_get_dreg(copr,tl,HOST_TEMPREG);
3811     type=STOREW_STUB;
3812   }
3813   else
3814     type=LOADW_STUB;
3815
3816   if(c&&!memtarget) {
3817     jaddr2=(int)out;
3818     emit_jmp(0); // inline_readstub/inline_writestub?
3819   }
3820   else {
3821     if(!c) {
3822       jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3823     }
3824     else if(ram_offset&&memtarget) {
3825       emit_addimm(ar,ram_offset,HOST_TEMPREG);
3826       fastio_reg_override=HOST_TEMPREG;
3827     }
3828     if (opcode[i]==0x32) { // LWC2
3829       #ifdef HOST_IMM_ADDR32
3830       if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3831       else
3832       #endif
3833       int a=ar;
3834       if(fastio_reg_override) a=fastio_reg_override;
3835       emit_readword_indexed(0,a,tl);
3836     }
3837     if (opcode[i]==0x3a) { // SWC2
3838       #ifdef DESTRUCTIVE_SHIFT
3839       if(!offset&&!c&&s>=0) emit_mov(s,ar);
3840       #endif
3841       int a=ar;
3842       if(fastio_reg_override) a=fastio_reg_override;
3843       emit_writeword_indexed(tl,0,a);
3844     }
3845   }
3846   if(jaddr2)
3847     add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3848   if(opcode[i]==0x3a) // SWC2
3849   if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3850 #if defined(HOST_IMM8)
3851     int ir=get_reg(i_regs->regmap,INVCP);
3852     assert(ir>=0);
3853     emit_cmpmem_indexedsr12_reg(ir,ar,1);
3854 #else
3855     emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3856 #endif
3857     #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3858     emit_callne(invalidate_addr_reg[ar]);
3859     #else
3860     jaddr3=(int)out;
3861     emit_jne(0);
3862     add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3863     #endif
3864   }
3865   if (opcode[i]==0x32) { // LWC2
3866     cop2_put_dreg(copr,tl,HOST_TEMPREG);
3867   }
3868 }
3869
3870 #ifndef multdiv_assemble
3871 void multdiv_assemble(int i,struct regstat *i_regs)
3872 {
3873   printf("Need multdiv_assemble for this architecture.\n");
3874   exit(1);
3875 }
3876 #endif
3877
3878 void mov_assemble(int i,struct regstat *i_regs)
3879 {
3880   //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3881   //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3882   if(rt1[i]) {
3883     signed char sh,sl,th,tl;
3884     th=get_reg(i_regs->regmap,rt1[i]|64);
3885     tl=get_reg(i_regs->regmap,rt1[i]);
3886     //assert(tl>=0);
3887     if(tl>=0) {
3888       sh=get_reg(i_regs->regmap,rs1[i]|64);
3889       sl=get_reg(i_regs->regmap,rs1[i]);
3890       if(sl>=0) emit_mov(sl,tl);
3891       else emit_loadreg(rs1[i],tl);
3892       if(th>=0) {
3893         if(sh>=0) emit_mov(sh,th);
3894         else emit_loadreg(rs1[i]|64,th);
3895       }
3896     }
3897   }
3898 }
3899
3900 #ifndef fconv_assemble
3901 void fconv_assemble(int i,struct regstat *i_regs)
3902 {
3903   printf("Need fconv_assemble for this architecture.\n");
3904   exit(1);
3905 }
3906 #endif
3907
3908 #if 0
3909 void float_assemble(int i,struct regstat *i_regs)
3910 {
3911   printf("Need float_assemble for this architecture.\n");
3912   exit(1);
3913 }
3914 #endif
3915
3916 void syscall_assemble(int i,struct regstat *i_regs)
3917 {
3918   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3919   assert(ccreg==HOST_CCREG);
3920   assert(!is_delayslot);
3921   emit_movimm(start+i*4,EAX); // Get PC
3922   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right?  There should probably be an extra cycle...
3923   emit_jmp((int)jump_syscall_hle); // XXX
3924 }
3925
3926 void hlecall_assemble(int i,struct regstat *i_regs)
3927 {
3928   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3929   assert(ccreg==HOST_CCREG);
3930   assert(!is_delayslot);
3931   emit_movimm(start+i*4+4,0); // Get PC
3932   emit_movimm((int)psxHLEt[source[i]&7],1);
3933   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3934   emit_jmp((int)jump_hlecall);
3935 }
3936
3937 void intcall_assemble(int i,struct regstat *i_regs)
3938 {
3939   signed char ccreg=get_reg(i_regs->regmap,CCREG);
3940   assert(ccreg==HOST_CCREG);
3941   assert(!is_delayslot);
3942   emit_movimm(start+i*4,0); // Get PC
3943   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3944   emit_jmp((int)jump_intcall);
3945 }
3946
3947 void ds_assemble(int i,struct regstat *i_regs)
3948 {
3949   speculate_register_values(i);
3950   is_delayslot=1;
3951   switch(itype[i]) {
3952     case ALU:
3953       alu_assemble(i,i_regs);break;
3954     case IMM16:
3955       imm16_assemble(i,i_regs);break;
3956     case SHIFT:
3957       shift_assemble(i,i_regs);break;
3958     case SHIFTIMM:
3959       shiftimm_assemble(i,i_regs);break;
3960     case LOAD:
3961       load_assemble(i,i_regs);break;
3962     case LOADLR:
3963       loadlr_assemble(i,i_regs);break;
3964     case STORE:
3965       store_assemble(i,i_regs);break;
3966     case STORELR:
3967       storelr_assemble(i,i_regs);break;
3968     case COP0:
3969       cop0_assemble(i,i_regs);break;
3970     case COP1:
3971       cop1_assemble(i,i_regs);break;
3972     case C1LS:
3973       c1ls_assemble(i,i_regs);break;
3974     case COP2:
3975       cop2_assemble(i,i_regs);break;
3976     case C2LS:
3977       c2ls_assemble(i,i_regs);break;
3978     case C2OP:
3979       c2op_assemble(i,i_regs);break;
3980     case FCONV:
3981       fconv_assemble(i,i_regs);break;
3982     case FLOAT:
3983       float_assemble(i,i_regs);break;
3984     case FCOMP:
3985       fcomp_assemble(i,i_regs);break;
3986     case MULTDIV:
3987       multdiv_assemble(i,i_regs);break;
3988     case MOV:
3989       mov_assemble(i,i_regs);break;
3990     case SYSCALL:
3991     case HLECALL:
3992     case INTCALL:
3993     case SPAN:
3994     case UJUMP:
3995     case RJUMP:
3996     case CJUMP:
3997     case SJUMP:
3998     case FJUMP:
3999       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
4000   }
4001   is_delayslot=0;
4002 }
4003
4004 // Is the branch target a valid internal jump?
4005 int internal_branch(uint64_t i_is32,int addr)
4006 {
4007   if(addr&1) return 0; // Indirect (register) jump
4008   if(addr>=start && addr<start+slen*4-4)
4009   {
4010     int t=(addr-start)>>2;
4011     // Delay slots are not valid branch targets
4012     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4013     // 64 -> 32 bit transition requires a recompile
4014     /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4015     {
4016       if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4017       else printf("optimizable: yes\n");
4018     }*/
4019     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4020 #ifndef FORCE32
4021     if(requires_32bit[t]&~i_is32) return 0;
4022     else
4023 #endif
4024       return 1;
4025   }
4026   return 0;
4027 }
4028
4029 #ifndef wb_invalidate
4030 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4031   uint64_t u,uint64_t uu)
4032 {
4033   int hr;
4034   for(hr=0;hr<HOST_REGS;hr++) {
4035     if(hr!=EXCLUDE_REG) {
4036       if(pre[hr]!=entry[hr]) {
4037         if(pre[hr]>=0) {
4038           if((dirty>>hr)&1) {
4039             if(get_reg(entry,pre[hr])<0) {
4040               if(pre[hr]<64) {
4041                 if(!((u>>pre[hr])&1)) {
4042                   emit_storereg(pre[hr],hr);
4043                   if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4044                     emit_sarimm(hr,31,hr);
4045                     emit_storereg(pre[hr]|64,hr);
4046                   }
4047                 }
4048               }else{
4049                 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4050                   emit_storereg(pre[hr],hr);
4051                 }
4052               }
4053             }
4054           }
4055         }
4056       }
4057     }
4058   }
4059   // Move from one register to another (no writeback)
4060   for(hr=0;hr<HOST_REGS;hr++) {
4061     if(hr!=EXCLUDE_REG) {
4062       if(pre[hr]!=entry[hr]) {
4063         if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4064           int nr;
4065           if((nr=get_reg(entry,pre[hr]))>=0) {
4066             emit_mov(hr,nr);
4067           }
4068         }
4069       }
4070     }
4071   }
4072 }
4073 #endif
4074
4075 // Load the specified registers
4076 // This only loads the registers given as arguments because
4077 // we don't want to load things that will be overwritten
4078 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4079 {
4080   int hr;
4081   // Load 32-bit regs
4082   for(hr=0;hr<HOST_REGS;hr++) {
4083     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4084       if(entry[hr]!=regmap[hr]) {
4085         if(regmap[hr]==rs1||regmap[hr]==rs2)
4086         {
4087           if(regmap[hr]==0) {
4088             emit_zeroreg(hr);
4089           }
4090           else
4091           {
4092             emit_loadreg(regmap[hr],hr);
4093           }
4094         }
4095       }
4096     }
4097   }
4098   //Load 64-bit regs
4099   for(hr=0;hr<HOST_REGS;hr++) {
4100     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4101       if(entry[hr]!=regmap[hr]) {
4102         if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4103         {
4104           assert(regmap[hr]!=64);
4105           if((is32>>(regmap[hr]&63))&1) {
4106             int lr=get_reg(regmap,regmap[hr]-64);
4107             if(lr>=0)
4108               emit_sarimm(lr,31,hr);
4109             else
4110               emit_loadreg(regmap[hr],hr);
4111           }
4112           else
4113           {
4114             emit_loadreg(regmap[hr],hr);
4115           }
4116         }
4117       }
4118     }
4119   }
4120 }
4121
4122 // Load registers prior to the start of a loop
4123 // so that they are not loaded within the loop
4124 static void loop_preload(signed char pre[],signed char entry[])
4125 {
4126   int hr;
4127   for(hr=0;hr<HOST_REGS;hr++) {
4128     if(hr!=EXCLUDE_REG) {
4129       if(pre[hr]!=entry[hr]) {
4130         if(entry[hr]>=0) {
4131           if(get_reg(pre,entry[hr])<0) {
4132             assem_debug("loop preload:\n");
4133             //printf("loop preload: %d\n",hr);
4134             if(entry[hr]==0) {
4135               emit_zeroreg(hr);
4136             }
4137             else if(entry[hr]<TEMPREG)
4138             {
4139               emit_loadreg(entry[hr],hr);
4140             }
4141             else if(entry[hr]-64<TEMPREG)
4142             {
4143               emit_loadreg(entry[hr],hr);
4144             }
4145           }
4146         }
4147       }
4148     }
4149   }
4150 }
4151
4152 // Generate address for load/store instruction
4153 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4154 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4155 {
4156   if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4157     int ra=-1;
4158     int agr=AGEN1+(i&1);
4159     int mgr=MGEN1+(i&1);
4160     if(itype[i]==LOAD) {
4161       ra=get_reg(i_regs->regmap,rt1[i]);
4162       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4163       assert(ra>=0);
4164     }
4165     if(itype[i]==LOADLR) {
4166       ra=get_reg(i_regs->regmap,FTEMP);
4167     }
4168     if(itype[i]==STORE||itype[i]==STORELR) {
4169       ra=get_reg(i_regs->regmap,agr);
4170       if(ra<0) ra=get_reg(i_regs->regmap,-1);
4171     }
4172     if(itype[i]==C1LS||itype[i]==C2LS) {
4173       if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4174         ra=get_reg(i_regs->regmap,FTEMP);
4175       else { // SWC1/SDC1/SWC2/SDC2
4176         ra=get_reg(i_regs->regmap,agr);
4177         if(ra<0) ra=get_reg(i_regs->regmap,-1);
4178       }
4179     }
4180     int rs=get_reg(i_regs->regmap,rs1[i]);
4181     int rm=get_reg(i_regs->regmap,TLREG);
4182     if(ra>=0) {
4183       int offset=imm[i];
4184       int c=(i_regs->wasconst>>rs)&1;
4185       if(rs1[i]==0) {
4186         // Using r0 as a base address
4187         /*if(rm>=0) {
4188           if(!entry||entry[rm]!=mgr) {
4189             generate_map_const(offset,rm);
4190           } // else did it in the previous cycle
4191         }*/
4192         if(!entry||entry[ra]!=agr) {
4193           if (opcode[i]==0x22||opcode[i]==0x26) {
4194             emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4195           }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4196             emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4197           }else{
4198             emit_movimm(offset,ra);
4199           }
4200         } // else did it in the previous cycle
4201       }
4202       else if(rs<0) {
4203         if(!entry||entry[ra]!=rs1[i])
4204           emit_loadreg(rs1[i],ra);
4205         //if(!entry||entry[ra]!=rs1[i])
4206         //  printf("poor load scheduling!\n");
4207       }
4208       else if(c) {
4209 #ifndef DISABLE_TLB
4210         if(rm>=0) {
4211           if(!entry||entry[rm]!=mgr) {
4212             if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4213               // Stores to memory go thru the mapper to detect self-modifying
4214               // code, loads don't.
4215               if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4216                  (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4217                 generate_map_const(constmap[i][rs]+offset,rm);
4218             }else{
4219               if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4220                 generate_map_const(constmap[i][rs]+offset,rm);
4221             }
4222           }
4223         }
4224 #endif
4225         if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4226           if(!entry||entry[ra]!=agr) {
4227             if (opcode[i]==0x22||opcode[i]==0x26) {
4228               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4229             }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4230               emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4231             }else{
4232               #ifdef HOST_IMM_ADDR32
4233               if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4234                  (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4235               #endif
4236               emit_movimm(constmap[i][rs]+offset,ra);
4237               regs[i].loadedconst|=1<<ra;
4238             }
4239           } // else did it in the previous cycle
4240         } // else load_consts already did it
4241       }
4242       if(offset&&!c&&rs1[i]) {
4243         if(rs>=0) {
4244           emit_addimm(rs,offset,ra);
4245         }else{
4246           emit_addimm(ra,offset,ra);
4247         }
4248       }
4249     }
4250   }
4251   // Preload constants for next instruction
4252   if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4253     int agr,ra;
4254     #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4255     // Mapper entry
4256     agr=MGEN1+((i+1)&1);
4257     ra=get_reg(i_regs->regmap,agr);
4258     if(ra>=0) {
4259       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4260       int offset=imm[i+1];
4261       int c=(regs[i+1].wasconst>>rs)&1;
4262       if(c) {
4263         if(itype[i+1]==STORE||itype[i+1]==STORELR
4264            ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4265           // Stores to memory go thru the mapper to detect self-modifying
4266           // code, loads don't.
4267           if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4268              (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4269             generate_map_const(constmap[i+1][rs]+offset,ra);
4270         }else{
4271           if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4272             generate_map_const(constmap[i+1][rs]+offset,ra);
4273         }
4274       }
4275       /*else if(rs1[i]==0) {
4276         generate_map_const(offset,ra);
4277       }*/
4278     }
4279     #endif
4280     // Actual address
4281     agr=AGEN1+((i+1)&1);
4282     ra=get_reg(i_regs->regmap,agr);
4283     if(ra>=0) {
4284       int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4285       int offset=imm[i+1];
4286       int c=(regs[i+1].wasconst>>rs)&1;
4287       if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4288         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4289           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4290         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4291           emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4292         }else{
4293           #ifdef HOST_IMM_ADDR32
4294           if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4295              (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4296           #endif
4297           emit_movimm(constmap[i+1][rs]+offset,ra);
4298           regs[i+1].loadedconst|=1<<ra;
4299         }
4300       }
4301       else if(rs1[i+1]==0) {
4302         // Using r0 as a base address
4303         if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4304           emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4305         }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4306           emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4307         }else{
4308           emit_movimm(offset,ra);
4309         }
4310       }
4311     }
4312   }
4313 }
4314
4315 int get_final_value(int hr, int i, int *value)
4316 {
4317   int reg=regs[i].regmap[hr];
4318   while(i<slen-1) {
4319     if(regs[i+1].regmap[hr]!=reg) break;
4320     if(!((regs[i+1].isconst>>hr)&1)) break;
4321     if(bt[i+1]) break;
4322     i++;
4323   }
4324   if(i<slen-1) {
4325     if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4326       *value=constmap[i][hr];
4327       return 1;
4328     }
4329     if(!bt[i+1]) {
4330       if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4331         // Load in delay slot, out-of-order execution
4332         if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4333         {
4334           #ifdef HOST_IMM_ADDR32
4335           if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4336           #endif
4337           // Precompute load address
4338           *value=constmap[i][hr]+imm[i+2];
4339           return 1;
4340         }
4341       }
4342       if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4343       {
4344         #ifdef HOST_IMM_ADDR32
4345         if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4346         #endif
4347         // Precompute load address
4348         *value=constmap[i][hr]+imm[i+1];
4349         //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4350         return 1;
4351       }
4352     }
4353   }
4354   *value=constmap[i][hr];
4355   //printf("c=%x\n",(int)constmap[i][hr]);
4356   if(i==slen-1) return 1;
4357   if(reg<64) {
4358     return !((unneeded_reg[i+1]>>reg)&1);
4359   }else{
4360     return !((unneeded_reg_upper[i+1]>>reg)&1);
4361   }
4362 }
4363
4364 // Load registers with known constants
4365 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4366 {
4367   int hr,hr2;
4368   // propagate loaded constant flags
4369   if(i==0||bt[i])
4370     regs[i].loadedconst=0;
4371   else {
4372     for(hr=0;hr<HOST_REGS;hr++) {
4373       if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4374          &&regmap[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4375       {
4376         regs[i].loadedconst|=1<<hr;
4377       }
4378     }
4379   }
4380   // Load 32-bit regs
4381   for(hr=0;hr<HOST_REGS;hr++) {
4382     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4383       //if(entry[hr]!=regmap[hr]) {
4384       if(!((regs[i].loadedconst>>hr)&1)) {
4385         if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4386           int value,similar=0;
4387           if(get_final_value(hr,i,&value)) {
4388             // see if some other register has similar value
4389             for(hr2=0;hr2<HOST_REGS;hr2++) {
4390               if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4391                 if(is_similar_value(value,constmap[i][hr2])) {
4392                   similar=1;
4393                   break;
4394                 }
4395               }
4396             }
4397             if(similar) {
4398               int value2;
4399               if(get_final_value(hr2,i,&value2)) // is this needed?
4400                 emit_movimm_from(value2,hr2,value,hr);
4401               else
4402                 emit_movimm(value,hr);
4403             }
4404             else if(value==0) {
4405               emit_zeroreg(hr);
4406             }
4407             else {
4408               emit_movimm(value,hr);
4409             }
4410           }
4411           regs[i].loadedconst|=1<<hr;
4412         }
4413       }
4414     }
4415   }
4416   // Load 64-bit regs
4417   for(hr=0;hr<HOST_REGS;hr++) {
4418     if(hr!=EXCLUDE_REG&&regmap[hr]>=0) {
4419       //if(entry[hr]!=regmap[hr]) {
4420       if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4421         if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4422           if((is32>>(regmap[hr]&63))&1) {
4423             int lr=get_reg(regmap,regmap[hr]-64);
4424             assert(lr>=0);
4425             emit_sarimm(lr,31,hr);
4426           }
4427           else
4428           {
4429             int value;
4430             if(get_final_value(hr,i,&value)) {
4431               if(value==0) {
4432                 emit_zeroreg(hr);
4433               }
4434               else {
4435                 emit_movimm(value,hr);
4436               }
4437             }
4438           }
4439         }
4440       }
4441     }
4442   }
4443 }
4444 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4445 {
4446   int hr;
4447   // Load 32-bit regs
4448   for(hr=0;hr<HOST_REGS;hr++) {
4449     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4450       if(((regs[i].isconst>>hr)&1)&&regmap[hr]<64&&regmap[hr]>0) {
4451         int value=constmap[i][hr];
4452         if(value==0) {
4453           emit_zeroreg(hr);
4454         }
4455         else {
4456           emit_movimm(value,hr);
4457         }
4458       }
4459     }
4460   }
4461   // Load 64-bit regs
4462   for(hr=0;hr<HOST_REGS;hr++) {
4463     if(hr!=EXCLUDE_REG&&regmap[hr]>=0&&((dirty>>hr)&1)) {
4464       if(((regs[i].isconst>>hr)&1)&&regmap[hr]>64) {
4465         if((is32>>(regmap[hr]&63))&1) {
4466           int lr=get_reg(regmap,regmap[hr]-64);
4467           assert(lr>=0);
4468           emit_sarimm(lr,31,hr);
4469         }
4470         else
4471         {
4472           int value=constmap[i][hr];
4473           if(value==0) {
4474             emit_zeroreg(hr);
4475           }
4476           else {
4477             emit_movimm(value,hr);
4478           }
4479         }
4480       }
4481     }
4482   }
4483 }
4484
4485 // Write out all dirty registers (except cycle count)
4486 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4487 {
4488   int hr;
4489   for(hr=0;hr<HOST_REGS;hr++) {
4490     if(hr!=EXCLUDE_REG) {
4491       if(i_regmap[hr]>0) {
4492         if(i_regmap[hr]!=CCREG) {
4493           if((i_dirty>>hr)&1) {
4494             if(i_regmap[hr]<64) {
4495               emit_storereg(i_regmap[hr],hr);
4496 #ifndef FORCE32
4497               if( ((i_is32>>i_regmap[hr])&1) ) {
4498                 #ifdef DESTRUCTIVE_WRITEBACK
4499                 emit_sarimm(hr,31,hr);
4500                 emit_storereg(i_regmap[hr]|64,hr);
4501                 #else
4502                 emit_sarimm(hr,31,HOST_TEMPREG);
4503                 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4504                 #endif
4505               }
4506 #endif
4507             }else{
4508               if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4509                 emit_storereg(i_regmap[hr],hr);
4510               }
4511             }
4512           }
4513         }
4514       }
4515     }
4516   }
4517 }
4518 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4519 // This writes the registers not written by store_regs_bt
4520 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4521 {
4522   int hr;
4523   int t=(addr-start)>>2;
4524   for(hr=0;hr<HOST_REGS;hr++) {
4525     if(hr!=EXCLUDE_REG) {
4526       if(i_regmap[hr]>0) {
4527         if(i_regmap[hr]!=CCREG) {
4528           if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4529             if((i_dirty>>hr)&1) {
4530               if(i_regmap[hr]<64) {
4531                 emit_storereg(i_regmap[hr],hr);
4532 #ifndef FORCE32
4533                 if( ((i_is32>>i_regmap[hr])&1) ) {
4534                   #ifdef DESTRUCTIVE_WRITEBACK
4535                   emit_sarimm(hr,31,hr);
4536                   emit_storereg(i_regmap[hr]|64,hr);
4537                   #else
4538                   emit_sarimm(hr,31,HOST_TEMPREG);
4539                   emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4540                   #endif
4541                 }
4542 #endif
4543               }else{
4544                 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4545                   emit_storereg(i_regmap[hr],hr);
4546                 }
4547               }
4548             }
4549           }
4550         }
4551       }
4552     }
4553   }
4554 }
4555
4556 // Load all registers (except cycle count)
4557 void load_all_regs(signed char i_regmap[])
4558 {
4559   int hr;
4560   for(hr=0;hr<HOST_REGS;hr++) {
4561     if(hr!=EXCLUDE_REG) {
4562       if(i_regmap[hr]==0) {
4563         emit_zeroreg(hr);
4564       }
4565       else
4566       if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4567       {
4568         emit_loadreg(i_regmap[hr],hr);
4569       }
4570     }
4571   }
4572 }
4573
4574 // Load all current registers also needed by next instruction
4575 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4576 {
4577   int hr;
4578   for(hr=0;hr<HOST_REGS;hr++) {
4579     if(hr!=EXCLUDE_REG) {
4580       if(get_reg(next_regmap,i_regmap[hr])>=0) {
4581         if(i_regmap[hr]==0) {
4582           emit_zeroreg(hr);
4583         }
4584         else
4585         if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4586         {
4587           emit_loadreg(i_regmap[hr],hr);
4588         }
4589       }
4590     }
4591   }
4592 }
4593
4594 // Load all regs, storing cycle count if necessary
4595 void load_regs_entry(int t)
4596 {
4597   int hr;
4598   if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4599   else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4600   if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4601     emit_storereg(CCREG,HOST_CCREG);
4602   }
4603   // Load 32-bit regs
4604   for(hr=0;hr<HOST_REGS;hr++) {
4605     if(regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4606       if(regs[t].regmap_entry[hr]==0) {
4607         emit_zeroreg(hr);
4608       }
4609       else if(regs[t].regmap_entry[hr]!=CCREG)
4610       {
4611         emit_loadreg(regs[t].regmap_entry[hr],hr);
4612       }
4613     }
4614   }
4615   // Load 64-bit regs
4616   for(hr=0;hr<HOST_REGS;hr++) {
4617     if(regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4618       assert(regs[t].regmap_entry[hr]!=64);
4619       if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4620         int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4621         if(lr<0) {
4622           emit_loadreg(regs[t].regmap_entry[hr],hr);
4623         }
4624         else
4625         {
4626           emit_sarimm(lr,31,hr);
4627         }
4628       }
4629       else
4630       {
4631         emit_loadreg(regs[t].regmap_entry[hr],hr);
4632       }
4633     }
4634   }
4635 }
4636
4637 // Store dirty registers prior to branch
4638 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4639 {
4640   if(internal_branch(i_is32,addr))
4641   {
4642     int t=(addr-start)>>2;
4643     int hr;
4644     for(hr=0;hr<HOST_REGS;hr++) {
4645       if(hr!=EXCLUDE_REG) {
4646         if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4647           if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4648             if((i_dirty>>hr)&1) {
4649               if(i_regmap[hr]<64) {
4650                 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4651                   emit_storereg(i_regmap[hr],hr);
4652                   if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4653                     #ifdef DESTRUCTIVE_WRITEBACK
4654                     emit_sarimm(hr,31,hr);
4655                     emit_storereg(i_regmap[hr]|64,hr);
4656                     #else
4657                     emit_sarimm(hr,31,HOST_TEMPREG);
4658                     emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4659                     #endif
4660                   }
4661                 }
4662               }else{
4663                 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4664                   emit_storereg(i_regmap[hr],hr);
4665                 }
4666               }
4667             }
4668           }
4669         }
4670       }
4671     }
4672   }
4673   else
4674   {
4675     // Branch out of this block, write out all dirty regs
4676     wb_dirtys(i_regmap,i_is32,i_dirty);
4677   }
4678 }
4679
4680 // Load all needed registers for branch target
4681 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4682 {
4683   //if(addr>=start && addr<(start+slen*4))
4684   if(internal_branch(i_is32,addr))
4685   {
4686     int t=(addr-start)>>2;
4687     int hr;
4688     // Store the cycle count before loading something else
4689     if(i_regmap[HOST_CCREG]!=CCREG) {
4690       assert(i_regmap[HOST_CCREG]==-1);
4691     }
4692     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4693       emit_storereg(CCREG,HOST_CCREG);
4694     }
4695     // Load 32-bit regs
4696     for(hr=0;hr<HOST_REGS;hr++) {
4697       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=0&&regs[t].regmap_entry[hr]<TEMPREG) {
4698         #ifdef DESTRUCTIVE_WRITEBACK
4699         if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4700         #else
4701         if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4702         #endif
4703           if(regs[t].regmap_entry[hr]==0) {
4704             emit_zeroreg(hr);
4705           }
4706           else if(regs[t].regmap_entry[hr]!=CCREG)
4707           {
4708             emit_loadreg(regs[t].regmap_entry[hr],hr);
4709           }
4710         }
4711       }
4712     }
4713     //Load 64-bit regs
4714     for(hr=0;hr<HOST_REGS;hr++) {
4715       if(hr!=EXCLUDE_REG&&regs[t].regmap_entry[hr]>=64&&regs[t].regmap_entry[hr]<TEMPREG+64) {
4716         if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4717           assert(regs[t].regmap_entry[hr]!=64);
4718           if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4719             int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4720             if(lr<0) {
4721               emit_loadreg(regs[t].regmap_entry[hr],hr);
4722             }
4723             else
4724             {
4725               emit_sarimm(lr,31,hr);
4726             }
4727           }
4728           else
4729           {
4730             emit_loadreg(regs[t].regmap_entry[hr],hr);
4731           }
4732         }
4733         else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4734           int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4735           assert(lr>=0);
4736           emit_sarimm(lr,31,hr);
4737         }
4738       }
4739     }
4740   }
4741 }
4742
4743 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4744 {
4745   if(addr>=start && addr<start+slen*4-4)
4746   {
4747     int t=(addr-start)>>2;
4748     int hr;
4749     if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4750     for(hr=0;hr<HOST_REGS;hr++)
4751     {
4752       if(hr!=EXCLUDE_REG)
4753       {
4754         if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4755         {
4756           if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4757           {
4758             return 0;
4759           }
4760           else
4761           if((i_dirty>>hr)&1)
4762           {
4763             if(i_regmap[hr]<TEMPREG)
4764             {
4765               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4766                 return 0;
4767             }
4768             else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4769             {
4770               if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4771                 return 0;
4772             }
4773           }
4774         }
4775         else // Same register but is it 32-bit or dirty?
4776         if(i_regmap[hr]>=0)
4777         {
4778           if(!((regs[t].dirty>>hr)&1))
4779           {
4780             if((i_dirty>>hr)&1)
4781             {
4782               if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4783               {
4784                 //printf("%x: dirty no match\n",addr);
4785                 return 0;
4786               }
4787             }
4788           }
4789           if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4790           {
4791             //printf("%x: is32 no match\n",addr);
4792             return 0;
4793           }
4794         }
4795       }
4796     }
4797     //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4798 #ifndef FORCE32
4799     if(requires_32bit[t]&~i_is32) return 0;
4800 #endif
4801     // Delay slots are not valid branch targets
4802     //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4803     // Delay slots require additional processing, so do not match
4804     if(is_ds[t]) return 0;
4805   }
4806   else
4807   {
4808     int hr;
4809     for(hr=0;hr<HOST_REGS;hr++)
4810     {
4811       if(hr!=EXCLUDE_REG)
4812       {
4813         if(i_regmap[hr]>=0)
4814         {
4815           if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4816           {
4817             if((i_dirty>>hr)&1)
4818             {
4819               return 0;
4820             }
4821           }
4822         }
4823       }
4824     }
4825   }
4826   return 1;
4827 }
4828
4829 // Used when a branch jumps into the delay slot of another branch
4830 void ds_assemble_entry(int i)
4831 {
4832   int t=(ba[i]-start)>>2;
4833   if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4834   assem_debug("Assemble delay slot at %x\n",ba[i]);
4835   assem_debug("<->\n");
4836   if(regs[t].regmap_entry[HOST_CCREG]==CCREG&&regs[t].regmap[HOST_CCREG]!=CCREG)
4837     wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4838   load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4839   address_generation(t,&regs[t],regs[t].regmap_entry);
4840   if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4841     load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4842   cop1_usable=0;
4843   is_delayslot=0;
4844   switch(itype[t]) {
4845     case ALU:
4846       alu_assemble(t,&regs[t]);break;
4847     case IMM16:
4848       imm16_assemble(t,&regs[t]);break;
4849     case SHIFT:
4850       shift_assemble(t,&regs[t]);break;
4851     case SHIFTIMM:
4852       shiftimm_assemble(t,&regs[t]);break;
4853     case LOAD:
4854       load_assemble(t,&regs[t]);break;
4855     case LOADLR:
4856       loadlr_assemble(t,&regs[t]);break;
4857     case STORE:
4858       store_assemble(t,&regs[t]);break;
4859     case STORELR:
4860       storelr_assemble(t,&regs[t]);break;
4861     case COP0:
4862       cop0_assemble(t,&regs[t]);break;
4863     case COP1:
4864       cop1_assemble(t,&regs[t]);break;
4865     case C1LS:
4866       c1ls_assemble(t,&regs[t]);break;
4867     case COP2:
4868       cop2_assemble(t,&regs[t]);break;
4869     case C2LS:
4870       c2ls_assemble(t,&regs[t]);break;
4871     case C2OP:
4872       c2op_assemble(t,&regs[t]);break;
4873     case FCONV:
4874       fconv_assemble(t,&regs[t]);break;
4875     case FLOAT:
4876       float_assemble(t,&regs[t]);break;
4877     case FCOMP:
4878       fcomp_assemble(t,&regs[t]);break;
4879     case MULTDIV:
4880       multdiv_assemble(t,&regs[t]);break;
4881     case MOV:
4882       mov_assemble(t,&regs[t]);break;
4883     case SYSCALL:
4884     case HLECALL:
4885     case INTCALL:
4886     case SPAN:
4887     case UJUMP:
4888     case RJUMP:
4889     case CJUMP:
4890     case SJUMP:
4891     case FJUMP:
4892       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
4893   }
4894   store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4895   load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4896   if(internal_branch(regs[t].is32,ba[i]+4))
4897     assem_debug("branch: internal\n");
4898   else
4899     assem_debug("branch: external\n");
4900   assert(internal_branch(regs[t].is32,ba[i]+4));
4901   add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4902   emit_jmp(0);
4903 }
4904
4905 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4906 {
4907   int count;
4908   int jaddr;
4909   int idle=0;
4910   int t=0;
4911   if(itype[i]==RJUMP)
4912   {
4913     *adj=0;
4914   }
4915   //if(ba[i]>=start && ba[i]<(start+slen*4))
4916   if(internal_branch(branch_regs[i].is32,ba[i]))
4917   {
4918     t=(ba[i]-start)>>2;
4919     if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4920     else *adj=ccadj[t];
4921   }
4922   else
4923   {
4924     *adj=0;
4925   }
4926   count=ccadj[i];
4927   if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4928     // Idle loop
4929     if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4930     idle=(int)out;
4931     //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4932     emit_andimm(HOST_CCREG,3,HOST_CCREG);
4933     jaddr=(int)out;
4934     emit_jmp(0);
4935   }
4936   else if(*adj==0||invert) {
4937     int cycles=CLOCK_ADJUST(count+2);
4938     // faster loop HACK
4939     if (t&&*adj) {
4940       int rel=t-i;
4941       if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4942         cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
4943     }
4944     emit_addimm_and_set_flags(cycles,HOST_CCREG);
4945     jaddr=(int)out;
4946     emit_jns(0);
4947   }
4948   else
4949   {
4950     emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4951     jaddr=(int)out;
4952     emit_jns(0);
4953   }
4954   add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4955 }
4956
4957 void do_ccstub(int n)
4958 {
4959   literal_pool(256);
4960   assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4961   set_jump_target(stubs[n][1],(int)out);
4962   int i=stubs[n][4];
4963   if(stubs[n][6]==NULLDS) {
4964     // Delay slot instruction is nullified ("likely" branch)
4965     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4966   }
4967   else if(stubs[n][6]!=TAKEN) {
4968     wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4969   }
4970   else {
4971     if(internal_branch(branch_regs[i].is32,ba[i]))
4972       wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4973   }
4974   if(stubs[n][5]!=-1)
4975   {
4976     // Save PC as return address
4977     emit_movimm(stubs[n][5],EAX);
4978     emit_writeword(EAX,(int)&pcaddr);
4979   }
4980   else
4981   {
4982     // Return address depends on which way the branch goes
4983     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4984     {
4985       int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4986       int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4987       int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4988       int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4989       if(rs1[i]==0)
4990       {
4991         s1l=s2l;s1h=s2h;
4992         s2l=s2h=-1;
4993       }
4994       else if(rs2[i]==0)
4995       {
4996         s2l=s2h=-1;
4997       }
4998       if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4999         s1h=s2h=-1;
5000       }
5001       assert(s1l>=0);
5002       #ifdef DESTRUCTIVE_WRITEBACK
5003       if(rs1[i]) {
5004         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5005           emit_loadreg(rs1[i],s1l);
5006       }
5007       else {
5008         if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5009           emit_loadreg(rs2[i],s1l);
5010       }
5011       if(s2l>=0)
5012         if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5013           emit_loadreg(rs2[i],s2l);
5014       #endif
5015       int hr=0;
5016       int addr=-1,alt=-1,ntaddr=-1;
5017       while(hr<HOST_REGS)
5018       {
5019         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5020            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5021            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5022         {
5023           addr=hr++;break;
5024         }
5025         hr++;
5026       }
5027       while(hr<HOST_REGS)
5028       {
5029         if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5030            (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5031            (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5032         {
5033           alt=hr++;break;
5034         }
5035         hr++;
5036       }
5037       if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5038       {
5039         while(hr<HOST_REGS)
5040         {
5041           if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5042              (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5043              (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5044           {
5045             ntaddr=hr;break;
5046           }
5047           hr++;
5048         }
5049         assert(hr<HOST_REGS);
5050       }
5051       if((opcode[i]&0x2f)==4) // BEQ
5052       {
5053         #ifdef HAVE_CMOV_IMM
5054         if(s1h<0) {
5055           if(s2l>=0) emit_cmp(s1l,s2l);
5056           else emit_test(s1l,s1l);
5057           emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5058         }
5059         else
5060         #endif
5061         {
5062           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5063           if(s1h>=0) {
5064             if(s2h>=0) emit_cmp(s1h,s2h);
5065             else emit_test(s1h,s1h);
5066             emit_cmovne_reg(alt,addr);
5067           }
5068           if(s2l>=0) emit_cmp(s1l,s2l);
5069           else emit_test(s1l,s1l);
5070           emit_cmovne_reg(alt,addr);
5071         }
5072       }
5073       if((opcode[i]&0x2f)==5) // BNE
5074       {
5075         #ifdef HAVE_CMOV_IMM
5076         if(s1h<0) {
5077           if(s2l>=0) emit_cmp(s1l,s2l);
5078           else emit_test(s1l,s1l);
5079           emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5080         }
5081         else
5082         #endif
5083         {
5084           emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5085           if(s1h>=0) {
5086             if(s2h>=0) emit_cmp(s1h,s2h);
5087             else emit_test(s1h,s1h);
5088             emit_cmovne_reg(alt,addr);
5089           }
5090           if(s2l>=0) emit_cmp(s1l,s2l);
5091           else emit_test(s1l,s1l);
5092           emit_cmovne_reg(alt,addr);
5093         }
5094       }
5095       if((opcode[i]&0x2f)==6) // BLEZ
5096       {
5097         //emit_movimm(ba[i],alt);
5098         //emit_movimm(start+i*4+8,addr);
5099         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5100         emit_cmpimm(s1l,1);
5101         if(s1h>=0) emit_mov(addr,ntaddr);
5102         emit_cmovl_reg(alt,addr);
5103         if(s1h>=0) {
5104           emit_test(s1h,s1h);
5105           emit_cmovne_reg(ntaddr,addr);
5106           emit_cmovs_reg(alt,addr);
5107         }
5108       }
5109       if((opcode[i]&0x2f)==7) // BGTZ
5110       {
5111         //emit_movimm(ba[i],addr);
5112         //emit_movimm(start+i*4+8,ntaddr);
5113         emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5114         emit_cmpimm(s1l,1);
5115         if(s1h>=0) emit_mov(addr,alt);
5116         emit_cmovl_reg(ntaddr,addr);
5117         if(s1h>=0) {
5118           emit_test(s1h,s1h);
5119           emit_cmovne_reg(alt,addr);
5120           emit_cmovs_reg(ntaddr,addr);
5121         }
5122       }
5123       if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5124       {
5125         //emit_movimm(ba[i],alt);
5126         //emit_movimm(start+i*4+8,addr);
5127         emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5128         if(s1h>=0) emit_test(s1h,s1h);
5129         else emit_test(s1l,s1l);
5130         emit_cmovs_reg(alt,addr);
5131       }
5132       if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5133       {
5134         //emit_movimm(ba[i],addr);
5135         //emit_movimm(start+i*4+8,alt);
5136         emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5137         if(s1h>=0) emit_test(s1h,s1h);
5138         else emit_test(s1l,s1l);
5139         emit_cmovs_reg(alt,addr);
5140       }
5141       if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5142         if(source[i]&0x10000) // BC1T
5143         {
5144           //emit_movimm(ba[i],alt);
5145           //emit_movimm(start+i*4+8,addr);
5146           emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5147           emit_testimm(s1l,0x800000);
5148           emit_cmovne_reg(alt,addr);
5149         }
5150         else // BC1F
5151         {
5152           //emit_movimm(ba[i],addr);
5153           //emit_movimm(start+i*4+8,alt);
5154           emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5155           emit_testimm(s1l,0x800000);
5156           emit_cmovne_reg(alt,addr);
5157         }
5158       }
5159       emit_writeword(addr,(int)&pcaddr);
5160     }
5161     else
5162     if(itype[i]==RJUMP)
5163     {
5164       int r=get_reg(branch_regs[i].regmap,rs1[i]);
5165       if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5166         r=get_reg(branch_regs[i].regmap,RTEMP);
5167       }
5168       emit_writeword(r,(int)&pcaddr);
5169     }
5170     else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
5171   }
5172   // Update cycle count
5173   assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5174   if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5175   emit_call((int)cc_interrupt);
5176   if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5177   if(stubs[n][6]==TAKEN) {
5178     if(internal_branch(branch_regs[i].is32,ba[i]))
5179       load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5180     else if(itype[i]==RJUMP) {
5181       if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5182         emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5183       else
5184         emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5185     }
5186   }else if(stubs[n][6]==NOTTAKEN) {
5187     if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5188     else load_all_regs(branch_regs[i].regmap);
5189   }else if(stubs[n][6]==NULLDS) {
5190     // Delay slot instruction is nullified ("likely" branch)
5191     if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5192     else load_all_regs(regs[i].regmap);
5193   }else{
5194     load_all_regs(branch_regs[i].regmap);
5195   }
5196   emit_jmp(stubs[n][2]); // return address
5197
5198   /* This works but uses a lot of memory...
5199   emit_readword((int)&last_count,ECX);
5200   emit_add(HOST_CCREG,ECX,EAX);
5201   emit_writeword(EAX,(int)&Count);
5202   emit_call((int)gen_interupt);
5203   emit_readword((int)&Count,HOST_CCREG);
5204   emit_readword((int)&next_interupt,EAX);
5205   emit_readword((int)&pending_exception,EBX);
5206   emit_writeword(EAX,(int)&last_count);
5207   emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5208   emit_test(EBX,EBX);
5209   int jne_instr=(int)out;
5210   emit_jne(0);
5211   if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5212   load_all_regs(branch_regs[i].regmap);
5213   emit_jmp(stubs[n][2]); // return address
5214   set_jump_target(jne_instr,(int)out);
5215   emit_readword((int)&pcaddr,EAX);
5216   // Call get_addr_ht instead of doing the hash table here.
5217   // This code is executed infrequently and takes up a lot of space
5218   // so smaller is better.
5219   emit_storereg(CCREG,HOST_CCREG);
5220   emit_pushreg(EAX);
5221   emit_call((int)get_addr_ht);
5222   emit_loadreg(CCREG,HOST_CCREG);
5223   emit_addimm(ESP,4,ESP);
5224   emit_jmpreg(EAX);*/
5225 }
5226
5227 add_to_linker(int addr,int target,int ext)
5228 {
5229   link_addr[linkcount][0]=addr;
5230   link_addr[linkcount][1]=target;
5231   link_addr[linkcount][2]=ext;
5232   linkcount++;
5233 }
5234
5235 static void ujump_assemble_write_ra(int i)
5236 {
5237   int rt;
5238   unsigned int return_address;
5239   rt=get_reg(branch_regs[i].regmap,31);
5240   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5241   //assert(rt>=0);
5242   return_address=start+i*4+8;
5243   if(rt>=0) {
5244     #ifdef USE_MINI_HT
5245     if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5246       int temp=-1; // note: must be ds-safe
5247       #ifdef HOST_TEMPREG
5248       temp=HOST_TEMPREG;
5249       #endif
5250       if(temp>=0) do_miniht_insert(return_address,rt,temp);
5251       else emit_movimm(return_address,rt);
5252     }
5253     else
5254     #endif
5255     {
5256       #ifdef REG_PREFETCH
5257       if(temp>=0)
5258       {
5259         if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5260       }
5261       #endif
5262       emit_movimm(return_address,rt); // PC into link register
5263       #ifdef IMM_PREFETCH
5264       emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5265       #endif
5266     }
5267   }
5268 }
5269
5270 void ujump_assemble(int i,struct regstat *i_regs)
5271 {
5272   signed char *i_regmap=i_regs->regmap;
5273   int ra_done=0;
5274   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5275   address_generation(i+1,i_regs,regs[i].regmap_entry);
5276   #ifdef REG_PREFETCH
5277   int temp=get_reg(branch_regs[i].regmap,PTEMP);
5278   if(rt1[i]==31&&temp>=0)
5279   {
5280     int return_address=start+i*4+8;
5281     if(get_reg(branch_regs[i].regmap,31)>0)
5282     if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5283   }
5284   #endif
5285   if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5286     ujump_assemble_write_ra(i); // writeback ra for DS
5287     ra_done=1;
5288   }
5289   ds_assemble(i+1,i_regs);
5290   uint64_t bc_unneeded=branch_regs[i].u;
5291   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5292   bc_unneeded|=1|(1LL<<rt1[i]);
5293   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5294   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5295                 bc_unneeded,bc_unneeded_upper);
5296   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5297   if(!ra_done&&rt1[i]==31)
5298     ujump_assemble_write_ra(i);
5299   int cc,adj;
5300   cc=get_reg(branch_regs[i].regmap,CCREG);
5301   assert(cc==HOST_CCREG);
5302   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5303   #ifdef REG_PREFETCH
5304   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5305   #endif
5306   do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5307   if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5308   load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5309   if(internal_branch(branch_regs[i].is32,ba[i]))
5310     assem_debug("branch: internal\n");
5311   else
5312     assem_debug("branch: external\n");
5313   if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5314     ds_assemble_entry(i);
5315   }
5316   else {
5317     add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5318     emit_jmp(0);
5319   }
5320 }
5321
5322 static void rjump_assemble_write_ra(int i)
5323 {
5324   int rt,return_address;
5325   assert(rt1[i+1]!=rt1[i]);
5326   assert(rt2[i+1]!=rt1[i]);
5327   rt=get_reg(branch_regs[i].regmap,rt1[i]);
5328   assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5329   assert(rt>=0);
5330   return_address=start+i*4+8;
5331   #ifdef REG_PREFETCH
5332   if(temp>=0)
5333   {
5334     if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5335   }
5336   #endif
5337   emit_movimm(return_address,rt); // PC into link register
5338   #ifdef IMM_PREFETCH
5339   emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5340   #endif
5341 }
5342
5343 void rjump_assemble(int i,struct regstat *i_regs)
5344 {
5345   signed char *i_regmap=i_regs->regmap;
5346   int temp;
5347   int rs,cc,adj;
5348   int ra_done=0;
5349   rs=get_reg(branch_regs[i].regmap,rs1[i]);
5350   assert(rs>=0);
5351   if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5352     // Delay slot abuse, make a copy of the branch address register
5353     temp=get_reg(branch_regs[i].regmap,RTEMP);
5354     assert(temp>=0);
5355     assert(regs[i].regmap[temp]==RTEMP);
5356     emit_mov(rs,temp);
5357     rs=temp;
5358   }
5359   address_generation(i+1,i_regs,regs[i].regmap_entry);
5360   #ifdef REG_PREFETCH
5361   if(rt1[i]==31)
5362   {
5363     if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5364       int return_address=start+i*4+8;
5365       if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5366     }
5367   }
5368   #endif
5369   #ifdef USE_MINI_HT
5370   if(rs1[i]==31) {
5371     int rh=get_reg(regs[i].regmap,RHASH);
5372     if(rh>=0) do_preload_rhash(rh);
5373   }
5374   #endif
5375   if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5376     rjump_assemble_write_ra(i);
5377     ra_done=1;
5378   }
5379   ds_assemble(i+1,i_regs);
5380   uint64_t bc_unneeded=branch_regs[i].u;
5381   uint64_t bc_unneeded_upper=branch_regs[i].uu;
5382   bc_unneeded|=1|(1LL<<rt1[i]);
5383   bc_unneeded_upper|=1|(1LL<<rt1[i]);
5384   bc_unneeded&=~(1LL<<rs1[i]);
5385   wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5386                 bc_unneeded,bc_unneeded_upper);
5387   load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5388   if(!ra_done&&rt1[i]!=0)
5389     rjump_assemble_write_ra(i);
5390   cc=get_reg(branch_regs[i].regmap,CCREG);
5391   assert(cc==HOST_CCREG);
5392   #ifdef USE_MINI_HT
5393   int rh=get_reg(branch_regs[i].regmap,RHASH);
5394   int ht=get_reg(branch_regs[i].regmap,RHTBL);
5395   if(rs1[i]==31) {
5396     if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5397     do_preload_rhtbl(ht);
5398     do_rhash(rs,rh);
5399   }
5400   #endif
5401   store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5402   #ifdef DESTRUCTIVE_WRITEBACK
5403   if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5404     if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5405       emit_loadreg(rs1[i],rs);
5406     }
5407   }
5408   #endif
5409   #ifdef REG_PREFETCH
5410   if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5411   #endif
5412   #ifdef USE_MINI_HT
5413   if(rs1[i]==31) {
5414     do_miniht_load(ht,rh);
5415   }
5416   #endif
5417   //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5418   //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5419   //assert(adj==0);
5420   emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5421   add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5422 #ifdef PCSX
5423   if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5424     // special case for RFE
5425     emit_jmp(0);
5426   else
5427 #endif
5428   emit_jns(0);
5429   //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5430   #ifdef USE_MINI_HT
5431   if(rs1[i]==31) {
5432     do_miniht_jump(rs,rh,ht);
5433   }
5434   else
5435   #endif
5436   {
5437     //if(rs!=EAX) emit_mov(rs,EAX);
5438     //emit_jmp((int)jump_vaddr_eax);
5439     emit_jmp(jump_vaddr_reg[rs]);
5440   }
5441   /* Check hash table
5442   temp=!rs;
5443   emit_mov(rs,temp);
5444   emit_shrimm(rs,16,rs);
5445   emit_xor(temp,rs,rs);
5446   emit_movzwl_reg(rs,rs);
5447   emit_shlimm(rs,4,rs);
5448   emit_cmpmem_indexed((int)hash_table,rs,temp);
5449   emit_jne((int)out+14);
5450   emit_readword_indexed((int)hash_table+4,rs,rs);
5451   emit_jmpreg(rs);
5452   emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5453   emit_addimm_no_flags(8,rs);
5454   emit_jeq((int)out-17);
5455   // No hit on hash table, call compiler
5456   emit_pushreg(temp);
5457 //DEBUG >
5458 #ifdef DEBUG_CYCLE_COUNT
5459   emit_readword((int)&last_count,ECX);
5460   emit_add(HOST_CCREG,ECX,HOST_CCREG);
5461   emit_readword((int)&next_interupt,ECX);
5462   emit_writeword(HOST_CCREG,(int)&Count);
5463   emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5464   emit_writeword(ECX,(int)&last_count);
5465 #endif
5466 //DEBUG <
5467   emit_storereg(CCREG,HOST_CCREG);
5468   emit_call((int)get_addr);
5469   emit_loadreg(CCREG,HOST_CCREG);
5470   emit_addimm(ESP,4,ESP);
5471   emit_jmpreg(EAX);*/
5472   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5473   if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5474   #endif
5475 }
5476
5477 void cjump_assemble(int i,struct regstat *i_regs)
5478 {
5479   signed char *i_regmap=i_regs->regmap;
5480   int cc;
5481   int match;
5482   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5483   assem_debug("match=%d\n",match);
5484   int s1h,s1l,s2h,s2l;
5485   int prev_cop1_usable=cop1_usable;
5486   int unconditional=0,nop=0;
5487   int only32=0;
5488   int invert=0;
5489   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5490   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5491   if(!match) invert=1;
5492   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5493   if(i>(ba[i]-start)>>2) invert=1;
5494   #endif
5495
5496   if(ooo[i]) {
5497     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5498     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5499     s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5500     s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5501   }
5502   else {
5503     s1l=get_reg(i_regmap,rs1[i]);
5504     s1h=get_reg(i_regmap,rs1[i]|64);
5505     s2l=get_reg(i_regmap,rs2[i]);
5506     s2h=get_reg(i_regmap,rs2[i]|64);
5507   }
5508   if(rs1[i]==0&&rs2[i]==0)
5509   {
5510     if(opcode[i]&1) nop=1;
5511     else unconditional=1;
5512     //assert(opcode[i]!=5);
5513     //assert(opcode[i]!=7);
5514     //assert(opcode[i]!=0x15);
5515     //assert(opcode[i]!=0x17);
5516   }
5517   else if(rs1[i]==0)
5518   {
5519     s1l=s2l;s1h=s2h;
5520     s2l=s2h=-1;
5521     only32=(regs[i].was32>>rs2[i])&1;
5522   }
5523   else if(rs2[i]==0)
5524   {
5525     s2l=s2h=-1;
5526     only32=(regs[i].was32>>rs1[i])&1;
5527   }
5528   else {
5529     only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5530   }
5531
5532   if(ooo[i]) {
5533     // Out of order execution (delay slot first)
5534     //printf("OOOE\n");
5535     address_generation(i+1,i_regs,regs[i].regmap_entry);
5536     ds_assemble(i+1,i_regs);
5537     int adj;
5538     uint64_t bc_unneeded=branch_regs[i].u;
5539     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5540     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5541     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5542     bc_unneeded|=1;
5543     bc_unneeded_upper|=1;
5544     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5545                   bc_unneeded,bc_unneeded_upper);
5546     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5547     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5548     cc=get_reg(branch_regs[i].regmap,CCREG);
5549     assert(cc==HOST_CCREG);
5550     if(unconditional)
5551       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5552     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5553     //assem_debug("cycle count (adj)\n");
5554     if(unconditional) {
5555       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5556       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5557         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5558         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5559         if(internal)
5560           assem_debug("branch: internal\n");
5561         else
5562           assem_debug("branch: external\n");
5563         if(internal&&is_ds[(ba[i]-start)>>2]) {
5564           ds_assemble_entry(i);
5565         }
5566         else {
5567           add_to_linker((int)out,ba[i],internal);
5568           emit_jmp(0);
5569         }
5570         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5571         if(((u_int)out)&7) emit_addnop(0);
5572         #endif
5573       }
5574     }
5575     else if(nop) {
5576       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5577       int jaddr=(int)out;
5578       emit_jns(0);
5579       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5580     }
5581     else {
5582       int taken=0,nottaken=0,nottaken1=0;
5583       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5584       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5585       if(!only32)
5586       {
5587         assert(s1h>=0);
5588         if(opcode[i]==4) // BEQ
5589         {
5590           if(s2h>=0) emit_cmp(s1h,s2h);
5591           else emit_test(s1h,s1h);
5592           nottaken1=(int)out;
5593           emit_jne(1);
5594         }
5595         if(opcode[i]==5) // BNE
5596         {
5597           if(s2h>=0) emit_cmp(s1h,s2h);
5598           else emit_test(s1h,s1h);
5599           if(invert) taken=(int)out;
5600           else add_to_linker((int)out,ba[i],internal);
5601           emit_jne(0);
5602         }
5603         if(opcode[i]==6) // BLEZ
5604         {
5605           emit_test(s1h,s1h);
5606           if(invert) taken=(int)out;
5607           else add_to_linker((int)out,ba[i],internal);
5608           emit_js(0);
5609           nottaken1=(int)out;
5610           emit_jne(1);
5611         }
5612         if(opcode[i]==7) // BGTZ
5613         {
5614           emit_test(s1h,s1h);
5615           nottaken1=(int)out;
5616           emit_js(1);
5617           if(invert) taken=(int)out;
5618           else add_to_linker((int)out,ba[i],internal);
5619           emit_jne(0);
5620         }
5621       } // if(!only32)
5622
5623       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5624       assert(s1l>=0);
5625       if(opcode[i]==4) // BEQ
5626       {
5627         if(s2l>=0) emit_cmp(s1l,s2l);
5628         else emit_test(s1l,s1l);
5629         if(invert){
5630           nottaken=(int)out;
5631           emit_jne(1);
5632         }else{
5633           add_to_linker((int)out,ba[i],internal);
5634           emit_jeq(0);
5635         }
5636       }
5637       if(opcode[i]==5) // BNE
5638       {
5639         if(s2l>=0) emit_cmp(s1l,s2l);
5640         else emit_test(s1l,s1l);
5641         if(invert){
5642           nottaken=(int)out;
5643           emit_jeq(1);
5644         }else{
5645           add_to_linker((int)out,ba[i],internal);
5646           emit_jne(0);
5647         }
5648       }
5649       if(opcode[i]==6) // BLEZ
5650       {
5651         emit_cmpimm(s1l,1);
5652         if(invert){
5653           nottaken=(int)out;
5654           emit_jge(1);
5655         }else{
5656           add_to_linker((int)out,ba[i],internal);
5657           emit_jl(0);
5658         }
5659       }
5660       if(opcode[i]==7) // BGTZ
5661       {
5662         emit_cmpimm(s1l,1);
5663         if(invert){
5664           nottaken=(int)out;
5665           emit_jl(1);
5666         }else{
5667           add_to_linker((int)out,ba[i],internal);
5668           emit_jge(0);
5669         }
5670       }
5671       if(invert) {
5672         if(taken) set_jump_target(taken,(int)out);
5673         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5674         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5675           if(adj) {
5676             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5677             add_to_linker((int)out,ba[i],internal);
5678           }else{
5679             emit_addnop(13);
5680             add_to_linker((int)out,ba[i],internal*2);
5681           }
5682           emit_jmp(0);
5683         }else
5684         #endif
5685         {
5686           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5687           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5688           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5689           if(internal)
5690             assem_debug("branch: internal\n");
5691           else
5692             assem_debug("branch: external\n");
5693           if(internal&&is_ds[(ba[i]-start)>>2]) {
5694             ds_assemble_entry(i);
5695           }
5696           else {
5697             add_to_linker((int)out,ba[i],internal);
5698             emit_jmp(0);
5699           }
5700         }
5701         set_jump_target(nottaken,(int)out);
5702       }
5703
5704       if(nottaken1) set_jump_target(nottaken1,(int)out);
5705       if(adj) {
5706         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5707       }
5708     } // (!unconditional)
5709   } // if(ooo)
5710   else
5711   {
5712     // In-order execution (branch first)
5713     //if(likely[i]) printf("IOL\n");
5714     //else
5715     //printf("IOE\n");
5716     int taken=0,nottaken=0,nottaken1=0;
5717     if(!unconditional&&!nop) {
5718       if(!only32)
5719       {
5720         assert(s1h>=0);
5721         if((opcode[i]&0x2f)==4) // BEQ
5722         {
5723           if(s2h>=0) emit_cmp(s1h,s2h);
5724           else emit_test(s1h,s1h);
5725           nottaken1=(int)out;
5726           emit_jne(2);
5727         }
5728         if((opcode[i]&0x2f)==5) // BNE
5729         {
5730           if(s2h>=0) emit_cmp(s1h,s2h);
5731           else emit_test(s1h,s1h);
5732           taken=(int)out;
5733           emit_jne(1);
5734         }
5735         if((opcode[i]&0x2f)==6) // BLEZ
5736         {
5737           emit_test(s1h,s1h);
5738           taken=(int)out;
5739           emit_js(1);
5740           nottaken1=(int)out;
5741           emit_jne(2);
5742         }
5743         if((opcode[i]&0x2f)==7) // BGTZ
5744         {
5745           emit_test(s1h,s1h);
5746           nottaken1=(int)out;
5747           emit_js(2);
5748           taken=(int)out;
5749           emit_jne(1);
5750         }
5751       } // if(!only32)
5752
5753       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5754       assert(s1l>=0);
5755       if((opcode[i]&0x2f)==4) // BEQ
5756       {
5757         if(s2l>=0) emit_cmp(s1l,s2l);
5758         else emit_test(s1l,s1l);
5759         nottaken=(int)out;
5760         emit_jne(2);
5761       }
5762       if((opcode[i]&0x2f)==5) // BNE
5763       {
5764         if(s2l>=0) emit_cmp(s1l,s2l);
5765         else emit_test(s1l,s1l);
5766         nottaken=(int)out;
5767         emit_jeq(2);
5768       }
5769       if((opcode[i]&0x2f)==6) // BLEZ
5770       {
5771         emit_cmpimm(s1l,1);
5772         nottaken=(int)out;
5773         emit_jge(2);
5774       }
5775       if((opcode[i]&0x2f)==7) // BGTZ
5776       {
5777         emit_cmpimm(s1l,1);
5778         nottaken=(int)out;
5779         emit_jl(2);
5780       }
5781     } // if(!unconditional)
5782     int adj;
5783     uint64_t ds_unneeded=branch_regs[i].u;
5784     uint64_t ds_unneeded_upper=branch_regs[i].uu;
5785     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5786     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5787     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5788     ds_unneeded|=1;
5789     ds_unneeded_upper|=1;
5790     // branch taken
5791     if(!nop) {
5792       if(taken) set_jump_target(taken,(int)out);
5793       assem_debug("1:\n");
5794       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5795                     ds_unneeded,ds_unneeded_upper);
5796       // load regs
5797       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5798       address_generation(i+1,&branch_regs[i],0);
5799       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5800       ds_assemble(i+1,&branch_regs[i]);
5801       cc=get_reg(branch_regs[i].regmap,CCREG);
5802       if(cc==-1) {
5803         emit_loadreg(CCREG,cc=HOST_CCREG);
5804         // CHECK: Is the following instruction (fall thru) allocated ok?
5805       }
5806       assert(cc==HOST_CCREG);
5807       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5808       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5809       assem_debug("cycle count (adj)\n");
5810       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5811       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5812       if(internal)
5813         assem_debug("branch: internal\n");
5814       else
5815         assem_debug("branch: external\n");
5816       if(internal&&is_ds[(ba[i]-start)>>2]) {
5817         ds_assemble_entry(i);
5818       }
5819       else {
5820         add_to_linker((int)out,ba[i],internal);
5821         emit_jmp(0);
5822       }
5823     }
5824     // branch not taken
5825     cop1_usable=prev_cop1_usable;
5826     if(!unconditional) {
5827       if(nottaken1) set_jump_target(nottaken1,(int)out);
5828       set_jump_target(nottaken,(int)out);
5829       assem_debug("2:\n");
5830       if(!likely[i]) {
5831         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5832                       ds_unneeded,ds_unneeded_upper);
5833         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5834         address_generation(i+1,&branch_regs[i],0);
5835         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5836         ds_assemble(i+1,&branch_regs[i]);
5837       }
5838       cc=get_reg(branch_regs[i].regmap,CCREG);
5839       if(cc==-1&&!likely[i]) {
5840         // Cycle count isn't in a register, temporarily load it then write it out
5841         emit_loadreg(CCREG,HOST_CCREG);
5842         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5843         int jaddr=(int)out;
5844         emit_jns(0);
5845         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5846         emit_storereg(CCREG,HOST_CCREG);
5847       }
5848       else{
5849         cc=get_reg(i_regmap,CCREG);
5850         assert(cc==HOST_CCREG);
5851         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5852         int jaddr=(int)out;
5853         emit_jns(0);
5854         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5855       }
5856     }
5857   }
5858 }
5859
5860 void sjump_assemble(int i,struct regstat *i_regs)
5861 {
5862   signed char *i_regmap=i_regs->regmap;
5863   int cc;
5864   int match;
5865   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5866   assem_debug("smatch=%d\n",match);
5867   int s1h,s1l;
5868   int prev_cop1_usable=cop1_usable;
5869   int unconditional=0,nevertaken=0;
5870   int only32=0;
5871   int invert=0;
5872   int internal=internal_branch(branch_regs[i].is32,ba[i]);
5873   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5874   if(!match) invert=1;
5875   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5876   if(i>(ba[i]-start)>>2) invert=1;
5877   #endif
5878
5879   //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5880   //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5881
5882   if(ooo[i]) {
5883     s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5884     s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5885   }
5886   else {
5887     s1l=get_reg(i_regmap,rs1[i]);
5888     s1h=get_reg(i_regmap,rs1[i]|64);
5889   }
5890   if(rs1[i]==0)
5891   {
5892     if(opcode2[i]&1) unconditional=1;
5893     else nevertaken=1;
5894     // These are never taken (r0 is never less than zero)
5895     //assert(opcode2[i]!=0);
5896     //assert(opcode2[i]!=2);
5897     //assert(opcode2[i]!=0x10);
5898     //assert(opcode2[i]!=0x12);
5899   }
5900   else {
5901     only32=(regs[i].was32>>rs1[i])&1;
5902   }
5903
5904   if(ooo[i]) {
5905     // Out of order execution (delay slot first)
5906     //printf("OOOE\n");
5907     address_generation(i+1,i_regs,regs[i].regmap_entry);
5908     ds_assemble(i+1,i_regs);
5909     int adj;
5910     uint64_t bc_unneeded=branch_regs[i].u;
5911     uint64_t bc_unneeded_upper=branch_regs[i].uu;
5912     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5913     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5914     bc_unneeded|=1;
5915     bc_unneeded_upper|=1;
5916     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5917                   bc_unneeded,bc_unneeded_upper);
5918     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5919     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5920     if(rt1[i]==31) {
5921       int rt,return_address;
5922       rt=get_reg(branch_regs[i].regmap,31);
5923       assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5924       if(rt>=0) {
5925         // Save the PC even if the branch is not taken
5926         return_address=start+i*4+8;
5927         emit_movimm(return_address,rt); // PC into link register
5928         #ifdef IMM_PREFETCH
5929         if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5930         #endif
5931       }
5932     }
5933     cc=get_reg(branch_regs[i].regmap,CCREG);
5934     assert(cc==HOST_CCREG);
5935     if(unconditional)
5936       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5937     //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5938     assem_debug("cycle count (adj)\n");
5939     if(unconditional) {
5940       do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5941       if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5942         if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5943         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5944         if(internal)
5945           assem_debug("branch: internal\n");
5946         else
5947           assem_debug("branch: external\n");
5948         if(internal&&is_ds[(ba[i]-start)>>2]) {
5949           ds_assemble_entry(i);
5950         }
5951         else {
5952           add_to_linker((int)out,ba[i],internal);
5953           emit_jmp(0);
5954         }
5955         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5956         if(((u_int)out)&7) emit_addnop(0);
5957         #endif
5958       }
5959     }
5960     else if(nevertaken) {
5961       emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5962       int jaddr=(int)out;
5963       emit_jns(0);
5964       add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5965     }
5966     else {
5967       int nottaken=0;
5968       do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5969       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5970       if(!only32)
5971       {
5972         assert(s1h>=0);
5973         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5974         {
5975           emit_test(s1h,s1h);
5976           if(invert){
5977             nottaken=(int)out;
5978             emit_jns(1);
5979           }else{
5980             add_to_linker((int)out,ba[i],internal);
5981             emit_js(0);
5982           }
5983         }
5984         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5985         {
5986           emit_test(s1h,s1h);
5987           if(invert){
5988             nottaken=(int)out;
5989             emit_js(1);
5990           }else{
5991             add_to_linker((int)out,ba[i],internal);
5992             emit_jns(0);
5993           }
5994         }
5995       } // if(!only32)
5996       else
5997       {
5998         assert(s1l>=0);
5999         if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6000         {
6001           emit_test(s1l,s1l);
6002           if(invert){
6003             nottaken=(int)out;
6004             emit_jns(1);
6005           }else{
6006             add_to_linker((int)out,ba[i],internal);
6007             emit_js(0);
6008           }
6009         }
6010         if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6011         {
6012           emit_test(s1l,s1l);
6013           if(invert){
6014             nottaken=(int)out;
6015             emit_js(1);
6016           }else{
6017             add_to_linker((int)out,ba[i],internal);
6018             emit_jns(0);
6019           }
6020         }
6021       } // if(!only32)
6022
6023       if(invert) {
6024         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6025         if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6026           if(adj) {
6027             emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6028             add_to_linker((int)out,ba[i],internal);
6029           }else{
6030             emit_addnop(13);
6031             add_to_linker((int)out,ba[i],internal*2);
6032           }
6033           emit_jmp(0);
6034         }else
6035         #endif
6036         {
6037           if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6038           store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6039           load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6040           if(internal)
6041             assem_debug("branch: internal\n");
6042           else
6043             assem_debug("branch: external\n");
6044           if(internal&&is_ds[(ba[i]-start)>>2]) {
6045             ds_assemble_entry(i);
6046           }
6047           else {
6048             add_to_linker((int)out,ba[i],internal);
6049             emit_jmp(0);
6050           }
6051         }
6052         set_jump_target(nottaken,(int)out);
6053       }
6054
6055       if(adj) {
6056         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6057       }
6058     } // (!unconditional)
6059   } // if(ooo)
6060   else
6061   {
6062     // In-order execution (branch first)
6063     //printf("IOE\n");
6064     int nottaken=0;
6065     if(rt1[i]==31) {
6066       int rt,return_address;
6067       rt=get_reg(branch_regs[i].regmap,31);
6068       if(rt>=0) {
6069         // Save the PC even if the branch is not taken
6070         return_address=start+i*4+8;
6071         emit_movimm(return_address,rt); // PC into link register
6072         #ifdef IMM_PREFETCH
6073         emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6074         #endif
6075       }
6076     }
6077     if(!unconditional) {
6078       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6079       if(!only32)
6080       {
6081         assert(s1h>=0);
6082         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6083         {
6084           emit_test(s1h,s1h);
6085           nottaken=(int)out;
6086           emit_jns(1);
6087         }
6088         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6089         {
6090           emit_test(s1h,s1h);
6091           nottaken=(int)out;
6092           emit_js(1);
6093         }
6094       } // if(!only32)
6095       else
6096       {
6097         assert(s1l>=0);
6098         if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6099         {
6100           emit_test(s1l,s1l);
6101           nottaken=(int)out;
6102           emit_jns(1);
6103         }
6104         if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6105         {
6106           emit_test(s1l,s1l);
6107           nottaken=(int)out;
6108           emit_js(1);
6109         }
6110       }
6111     } // if(!unconditional)
6112     int adj;
6113     uint64_t ds_unneeded=branch_regs[i].u;
6114     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6115     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6116     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6117     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6118     ds_unneeded|=1;
6119     ds_unneeded_upper|=1;
6120     // branch taken
6121     if(!nevertaken) {
6122       //assem_debug("1:\n");
6123       wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6124                     ds_unneeded,ds_unneeded_upper);
6125       // load regs
6126       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6127       address_generation(i+1,&branch_regs[i],0);
6128       load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6129       ds_assemble(i+1,&branch_regs[i]);
6130       cc=get_reg(branch_regs[i].regmap,CCREG);
6131       if(cc==-1) {
6132         emit_loadreg(CCREG,cc=HOST_CCREG);
6133         // CHECK: Is the following instruction (fall thru) allocated ok?
6134       }
6135       assert(cc==HOST_CCREG);
6136       store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6137       do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6138       assem_debug("cycle count (adj)\n");
6139       if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6140       load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6141       if(internal)
6142         assem_debug("branch: internal\n");
6143       else
6144         assem_debug("branch: external\n");
6145       if(internal&&is_ds[(ba[i]-start)>>2]) {
6146         ds_assemble_entry(i);
6147       }
6148       else {
6149         add_to_linker((int)out,ba[i],internal);
6150         emit_jmp(0);
6151       }
6152     }
6153     // branch not taken
6154     cop1_usable=prev_cop1_usable;
6155     if(!unconditional) {
6156       set_jump_target(nottaken,(int)out);
6157       assem_debug("1:\n");
6158       if(!likely[i]) {
6159         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6160                       ds_unneeded,ds_unneeded_upper);
6161         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6162         address_generation(i+1,&branch_regs[i],0);
6163         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6164         ds_assemble(i+1,&branch_regs[i]);
6165       }
6166       cc=get_reg(branch_regs[i].regmap,CCREG);
6167       if(cc==-1&&!likely[i]) {
6168         // Cycle count isn't in a register, temporarily load it then write it out
6169         emit_loadreg(CCREG,HOST_CCREG);
6170         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6171         int jaddr=(int)out;
6172         emit_jns(0);
6173         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6174         emit_storereg(CCREG,HOST_CCREG);
6175       }
6176       else{
6177         cc=get_reg(i_regmap,CCREG);
6178         assert(cc==HOST_CCREG);
6179         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6180         int jaddr=(int)out;
6181         emit_jns(0);
6182         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6183       }
6184     }
6185   }
6186 }
6187
6188 void fjump_assemble(int i,struct regstat *i_regs)
6189 {
6190   signed char *i_regmap=i_regs->regmap;
6191   int cc;
6192   int match;
6193   match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6194   assem_debug("fmatch=%d\n",match);
6195   int fs,cs;
6196   int eaddr;
6197   int invert=0;
6198   int internal=internal_branch(branch_regs[i].is32,ba[i]);
6199   if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6200   if(!match) invert=1;
6201   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6202   if(i>(ba[i]-start)>>2) invert=1;
6203   #endif
6204
6205   if(ooo[i]) {
6206     fs=get_reg(branch_regs[i].regmap,FSREG);
6207     address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6208   }
6209   else {
6210     fs=get_reg(i_regmap,FSREG);
6211   }
6212
6213   // Check cop1 unusable
6214   if(!cop1_usable) {
6215     cs=get_reg(i_regmap,CSREG);
6216     assert(cs>=0);
6217     emit_testimm(cs,0x20000000);
6218     eaddr=(int)out;
6219     emit_jeq(0);
6220     add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6221     cop1_usable=1;
6222   }
6223
6224   if(ooo[i]) {
6225     // Out of order execution (delay slot first)
6226     //printf("OOOE\n");
6227     ds_assemble(i+1,i_regs);
6228     int adj;
6229     uint64_t bc_unneeded=branch_regs[i].u;
6230     uint64_t bc_unneeded_upper=branch_regs[i].uu;
6231     bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6232     bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6233     bc_unneeded|=1;
6234     bc_unneeded_upper|=1;
6235     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6236                   bc_unneeded,bc_unneeded_upper);
6237     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6238     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6239     cc=get_reg(branch_regs[i].regmap,CCREG);
6240     assert(cc==HOST_CCREG);
6241     do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6242     assem_debug("cycle count (adj)\n");
6243     if(1) {
6244       int nottaken=0;
6245       if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6246       if(1) {
6247         assert(fs>=0);
6248         emit_testimm(fs,0x800000);
6249         if(source[i]&0x10000) // BC1T
6250         {
6251           if(invert){
6252             nottaken=(int)out;
6253             emit_jeq(1);
6254           }else{
6255             add_to_linker((int)out,ba[i],internal);
6256             emit_jne(0);
6257           }
6258         }
6259         else // BC1F
6260           if(invert){
6261             nottaken=(int)out;
6262             emit_jne(1);
6263           }else{
6264             add_to_linker((int)out,ba[i],internal);
6265             emit_jeq(0);
6266           }
6267         {
6268         }
6269       } // if(!only32)
6270
6271       if(invert) {
6272         if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6273         #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6274         else if(match) emit_addnop(13);
6275         #endif
6276         store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6277         load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6278         if(internal)
6279           assem_debug("branch: internal\n");
6280         else
6281           assem_debug("branch: external\n");
6282         if(internal&&is_ds[(ba[i]-start)>>2]) {
6283           ds_assemble_entry(i);
6284         }
6285         else {
6286           add_to_linker((int)out,ba[i],internal);
6287           emit_jmp(0);
6288         }
6289         set_jump_target(nottaken,(int)out);
6290       }
6291
6292       if(adj) {
6293         if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6294       }
6295     } // (!unconditional)
6296   } // if(ooo)
6297   else
6298   {
6299     // In-order execution (branch first)
6300     //printf("IOE\n");
6301     int nottaken=0;
6302     if(1) {
6303       //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6304       if(1) {
6305         assert(fs>=0);
6306         emit_testimm(fs,0x800000);
6307         if(source[i]&0x10000) // BC1T
6308         {
6309           nottaken=(int)out;
6310           emit_jeq(1);
6311         }
6312         else // BC1F
6313         {
6314           nottaken=(int)out;
6315           emit_jne(1);
6316         }
6317       }
6318     } // if(!unconditional)
6319     int adj;
6320     uint64_t ds_unneeded=branch_regs[i].u;
6321     uint64_t ds_unneeded_upper=branch_regs[i].uu;
6322     ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6323     ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6324     if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6325     ds_unneeded|=1;
6326     ds_unneeded_upper|=1;
6327     // branch taken
6328     //assem_debug("1:\n");
6329     wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6330                   ds_unneeded,ds_unneeded_upper);
6331     // load regs
6332     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6333     address_generation(i+1,&branch_regs[i],0);
6334     load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6335     ds_assemble(i+1,&branch_regs[i]);
6336     cc=get_reg(branch_regs[i].regmap,CCREG);
6337     if(cc==-1) {
6338       emit_loadreg(CCREG,cc=HOST_CCREG);
6339       // CHECK: Is the following instruction (fall thru) allocated ok?
6340     }
6341     assert(cc==HOST_CCREG);
6342     store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6343     do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6344     assem_debug("cycle count (adj)\n");
6345     if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6346     load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6347     if(internal)
6348       assem_debug("branch: internal\n");
6349     else
6350       assem_debug("branch: external\n");
6351     if(internal&&is_ds[(ba[i]-start)>>2]) {
6352       ds_assemble_entry(i);
6353     }
6354     else {
6355       add_to_linker((int)out,ba[i],internal);
6356       emit_jmp(0);
6357     }
6358
6359     // branch not taken
6360     if(1) { // <- FIXME (don't need this)
6361       set_jump_target(nottaken,(int)out);
6362       assem_debug("1:\n");
6363       if(!likely[i]) {
6364         wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6365                       ds_unneeded,ds_unneeded_upper);
6366         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6367         address_generation(i+1,&branch_regs[i],0);
6368         load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6369         ds_assemble(i+1,&branch_regs[i]);
6370       }
6371       cc=get_reg(branch_regs[i].regmap,CCREG);
6372       if(cc==-1&&!likely[i]) {
6373         // Cycle count isn't in a register, temporarily load it then write it out
6374         emit_loadreg(CCREG,HOST_CCREG);
6375         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6376         int jaddr=(int)out;
6377         emit_jns(0);
6378         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6379         emit_storereg(CCREG,HOST_CCREG);
6380       }
6381       else{
6382         cc=get_reg(i_regmap,CCREG);
6383         assert(cc==HOST_CCREG);
6384         emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6385         int jaddr=(int)out;
6386         emit_jns(0);
6387         add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6388       }
6389     }
6390   }
6391 }
6392
6393 static void pagespan_assemble(int i,struct regstat *i_regs)
6394 {
6395   int s1l=get_reg(i_regs->regmap,rs1[i]);
6396   int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6397   int s2l=get_reg(i_regs->regmap,rs2[i]);
6398   int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6399   void *nt_branch=NULL;
6400   int taken=0;
6401   int nottaken=0;
6402   int unconditional=0;
6403   if(rs1[i]==0)
6404   {
6405     s1l=s2l;s1h=s2h;
6406     s2l=s2h=-1;
6407   }
6408   else if(rs2[i]==0)
6409   {
6410     s2l=s2h=-1;
6411   }
6412   if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6413     s1h=s2h=-1;
6414   }
6415   int hr=0;
6416   int addr,alt,ntaddr;
6417   if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6418   else {
6419     while(hr<HOST_REGS)
6420     {
6421       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6422          (i_regs->regmap[hr]&63)!=rs1[i] &&
6423          (i_regs->regmap[hr]&63)!=rs2[i] )
6424       {
6425         addr=hr++;break;
6426       }
6427       hr++;
6428     }
6429   }
6430   while(hr<HOST_REGS)
6431   {
6432     if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6433        (i_regs->regmap[hr]&63)!=rs1[i] &&
6434        (i_regs->regmap[hr]&63)!=rs2[i] )
6435     {
6436       alt=hr++;break;
6437     }
6438     hr++;
6439   }
6440   if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6441   {
6442     while(hr<HOST_REGS)
6443     {
6444       if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6445          (i_regs->regmap[hr]&63)!=rs1[i] &&
6446          (i_regs->regmap[hr]&63)!=rs2[i] )
6447       {
6448         ntaddr=hr;break;
6449       }
6450       hr++;
6451     }
6452   }
6453   assert(hr<HOST_REGS);
6454   if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6455     load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6456   }
6457   emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6458   if(opcode[i]==2) // J
6459   {
6460     unconditional=1;
6461   }
6462   if(opcode[i]==3) // JAL
6463   {
6464     // TODO: mini_ht
6465     int rt=get_reg(i_regs->regmap,31);
6466     emit_movimm(start+i*4+8,rt);
6467     unconditional=1;
6468   }
6469   if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6470   {
6471     emit_mov(s1l,addr);
6472     if(opcode2[i]==9) // JALR
6473     {
6474       int rt=get_reg(i_regs->regmap,rt1[i]);
6475       emit_movimm(start+i*4+8,rt);
6476     }
6477   }
6478   if((opcode[i]&0x3f)==4) // BEQ
6479   {
6480     if(rs1[i]==rs2[i])
6481     {
6482       unconditional=1;
6483     }
6484     else
6485     #ifdef HAVE_CMOV_IMM
6486     if(s1h<0) {
6487       if(s2l>=0) emit_cmp(s1l,s2l);
6488       else emit_test(s1l,s1l);
6489       emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6490     }
6491     else
6492     #endif
6493     {
6494       assert(s1l>=0);
6495       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6496       if(s1h>=0) {
6497         if(s2h>=0) emit_cmp(s1h,s2h);
6498         else emit_test(s1h,s1h);
6499         emit_cmovne_reg(alt,addr);
6500       }
6501       if(s2l>=0) emit_cmp(s1l,s2l);
6502       else emit_test(s1l,s1l);
6503       emit_cmovne_reg(alt,addr);
6504     }
6505   }
6506   if((opcode[i]&0x3f)==5) // BNE
6507   {
6508     #ifdef HAVE_CMOV_IMM
6509     if(s1h<0) {
6510       if(s2l>=0) emit_cmp(s1l,s2l);
6511       else emit_test(s1l,s1l);
6512       emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6513     }
6514     else
6515     #endif
6516     {
6517       assert(s1l>=0);
6518       emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6519       if(s1h>=0) {
6520         if(s2h>=0) emit_cmp(s1h,s2h);
6521         else emit_test(s1h,s1h);
6522         emit_cmovne_reg(alt,addr);
6523       }
6524       if(s2l>=0) emit_cmp(s1l,s2l);
6525       else emit_test(s1l,s1l);
6526       emit_cmovne_reg(alt,addr);
6527     }
6528   }
6529   if((opcode[i]&0x3f)==0x14) // BEQL
6530   {
6531     if(s1h>=0) {
6532       if(s2h>=0) emit_cmp(s1h,s2h);
6533       else emit_test(s1h,s1h);
6534       nottaken=(int)out;
6535       emit_jne(0);
6536     }
6537     if(s2l>=0) emit_cmp(s1l,s2l);
6538     else emit_test(s1l,s1l);
6539     if(nottaken) set_jump_target(nottaken,(int)out);
6540     nottaken=(int)out;
6541     emit_jne(0);
6542   }
6543   if((opcode[i]&0x3f)==0x15) // BNEL
6544   {
6545     if(s1h>=0) {
6546       if(s2h>=0) emit_cmp(s1h,s2h);
6547       else emit_test(s1h,s1h);
6548       taken=(int)out;
6549       emit_jne(0);
6550     }
6551     if(s2l>=0) emit_cmp(s1l,s2l);
6552     else emit_test(s1l,s1l);
6553     nottaken=(int)out;
6554     emit_jeq(0);
6555     if(taken) set_jump_target(taken,(int)out);
6556   }
6557   if((opcode[i]&0x3f)==6) // BLEZ
6558   {
6559     emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6560     emit_cmpimm(s1l,1);
6561     if(s1h>=0) emit_mov(addr,ntaddr);
6562     emit_cmovl_reg(alt,addr);
6563     if(s1h>=0) {
6564       emit_test(s1h,s1h);
6565       emit_cmovne_reg(ntaddr,addr);
6566       emit_cmovs_reg(alt,addr);
6567     }
6568   }
6569   if((opcode[i]&0x3f)==7) // BGTZ
6570   {
6571     emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6572     emit_cmpimm(s1l,1);
6573     if(s1h>=0) emit_mov(addr,alt);
6574     emit_cmovl_reg(ntaddr,addr);
6575     if(s1h>=0) {
6576       emit_test(s1h,s1h);
6577       emit_cmovne_reg(alt,addr);
6578       emit_cmovs_reg(ntaddr,addr);
6579     }
6580   }
6581   if((opcode[i]&0x3f)==0x16) // BLEZL
6582   {
6583     assert((opcode[i]&0x3f)!=0x16);
6584   }
6585   if((opcode[i]&0x3f)==0x17) // BGTZL
6586   {
6587     assert((opcode[i]&0x3f)!=0x17);
6588   }
6589   assert(opcode[i]!=1); // BLTZ/BGEZ
6590
6591   //FIXME: Check CSREG
6592   if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6593     if((source[i]&0x30000)==0) // BC1F
6594     {
6595       emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6596       emit_testimm(s1l,0x800000);
6597       emit_cmovne_reg(alt,addr);
6598     }
6599     if((source[i]&0x30000)==0x10000) // BC1T
6600     {
6601       emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6602       emit_testimm(s1l,0x800000);
6603       emit_cmovne_reg(alt,addr);
6604     }
6605     if((source[i]&0x30000)==0x20000) // BC1FL
6606     {
6607       emit_testimm(s1l,0x800000);
6608       nottaken=(int)out;
6609       emit_jne(0);
6610     }
6611     if((source[i]&0x30000)==0x30000) // BC1TL
6612     {
6613       emit_testimm(s1l,0x800000);
6614       nottaken=(int)out;
6615       emit_jeq(0);
6616     }
6617   }
6618
6619   assert(i_regs->regmap[HOST_CCREG]==CCREG);
6620   wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6621   if(likely[i]||unconditional)
6622   {
6623     emit_movimm(ba[i],HOST_BTREG);
6624   }
6625   else if(addr!=HOST_BTREG)
6626   {
6627     emit_mov(addr,HOST_BTREG);
6628   }
6629   void *branch_addr=out;
6630   emit_jmp(0);
6631   int target_addr=start+i*4+5;
6632   void *stub=out;
6633   void *compiled_target_addr=check_addr(target_addr);
6634   emit_extjump_ds((int)branch_addr,target_addr);
6635   if(compiled_target_addr) {
6636     set_jump_target((int)branch_addr,(int)compiled_target_addr);
6637     add_link(target_addr,stub);
6638   }
6639   else set_jump_target((int)branch_addr,(int)stub);
6640   if(likely[i]) {
6641     // Not-taken path
6642     set_jump_target((int)nottaken,(int)out);
6643     wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6644     void *branch_addr=out;
6645     emit_jmp(0);
6646     int target_addr=start+i*4+8;
6647     void *stub=out;
6648     void *compiled_target_addr=check_addr(target_addr);
6649     emit_extjump_ds((int)branch_addr,target_addr);
6650     if(compiled_target_addr) {
6651       set_jump_target((int)branch_addr,(int)compiled_target_addr);
6652       add_link(target_addr,stub);
6653     }
6654     else set_jump_target((int)branch_addr,(int)stub);
6655   }
6656 }
6657
6658 // Assemble the delay slot for the above
6659 static void pagespan_ds()
6660 {
6661   assem_debug("initial delay slot:\n");
6662   u_int vaddr=start+1;
6663   u_int page=get_page(vaddr);
6664   u_int vpage=get_vpage(vaddr);
6665   ll_add(jump_dirty+vpage,vaddr,(void *)out);
6666   do_dirty_stub_ds();
6667   ll_add(jump_in+page,vaddr,(void *)out);
6668   assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6669   if(regs[0].regmap[HOST_CCREG]!=CCREG)
6670     wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6671   if(regs[0].regmap[HOST_BTREG]!=BTREG)
6672     emit_writeword(HOST_BTREG,(int)&branch_target);
6673   load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6674   address_generation(0,&regs[0],regs[0].regmap_entry);
6675   if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6676     load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6677   cop1_usable=0;
6678   is_delayslot=0;
6679   switch(itype[0]) {
6680     case ALU:
6681       alu_assemble(0,&regs[0]);break;
6682     case IMM16:
6683       imm16_assemble(0,&regs[0]);break;
6684     case SHIFT:
6685       shift_assemble(0,&regs[0]);break;
6686     case SHIFTIMM:
6687       shiftimm_assemble(0,&regs[0]);break;
6688     case LOAD:
6689       load_assemble(0,&regs[0]);break;
6690     case LOADLR:
6691       loadlr_assemble(0,&regs[0]);break;
6692     case STORE:
6693       store_assemble(0,&regs[0]);break;
6694     case STORELR:
6695       storelr_assemble(0,&regs[0]);break;
6696     case COP0:
6697       cop0_assemble(0,&regs[0]);break;
6698     case COP1:
6699       cop1_assemble(0,&regs[0]);break;
6700     case C1LS:
6701       c1ls_assemble(0,&regs[0]);break;
6702     case COP2:
6703       cop2_assemble(0,&regs[0]);break;
6704     case C2LS:
6705       c2ls_assemble(0,&regs[0]);break;
6706     case C2OP:
6707       c2op_assemble(0,&regs[0]);break;
6708     case FCONV:
6709       fconv_assemble(0,&regs[0]);break;
6710     case FLOAT:
6711       float_assemble(0,&regs[0]);break;
6712     case FCOMP:
6713       fcomp_assemble(0,&regs[0]);break;
6714     case MULTDIV:
6715       multdiv_assemble(0,&regs[0]);break;
6716     case MOV:
6717       mov_assemble(0,&regs[0]);break;
6718     case SYSCALL:
6719     case HLECALL:
6720     case INTCALL:
6721     case SPAN:
6722     case UJUMP:
6723     case RJUMP:
6724     case CJUMP:
6725     case SJUMP:
6726     case FJUMP:
6727       SysPrintf("Jump in the delay slot.  This is probably a bug.\n");
6728   }
6729   int btaddr=get_reg(regs[0].regmap,BTREG);
6730   if(btaddr<0) {
6731     btaddr=get_reg(regs[0].regmap,-1);
6732     emit_readword((int)&branch_target,btaddr);
6733   }
6734   assert(btaddr!=HOST_CCREG);
6735   if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6736 #ifdef HOST_IMM8
6737   emit_movimm(start+4,HOST_TEMPREG);
6738   emit_cmp(btaddr,HOST_TEMPREG);
6739 #else
6740   emit_cmpimm(btaddr,start+4);
6741 #endif
6742   int branch=(int)out;
6743   emit_jeq(0);
6744   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6745   emit_jmp(jump_vaddr_reg[btaddr]);
6746   set_jump_target(branch,(int)out);
6747   store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6748   load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6749 }
6750
6751 // Basic liveness analysis for MIPS registers
6752 void unneeded_registers(int istart,int iend,int r)
6753 {
6754   int i;
6755   uint64_t u,uu,gte_u,b,bu,gte_bu;
6756   uint64_t temp_u,temp_uu,temp_gte_u=0;
6757   uint64_t tdep;
6758   uint64_t gte_u_unknown=0;
6759   if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6760     gte_u_unknown=~0ll;
6761   if(iend==slen-1) {
6762     u=1;uu=1;
6763     gte_u=gte_u_unknown;
6764   }else{
6765     u=unneeded_reg[iend+1];
6766     uu=unneeded_reg_upper[iend+1];
6767     u=1;uu=1;
6768     gte_u=gte_unneeded[iend+1];
6769   }
6770
6771   for (i=iend;i>=istart;i--)
6772   {
6773     //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6774     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6775     {
6776       // If subroutine call, flag return address as a possible branch target
6777       if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6778
6779       if(ba[i]<start || ba[i]>=(start+slen*4))
6780       {
6781         // Branch out of this block, flush all regs
6782         u=1;
6783         uu=1;
6784         gte_u=gte_u_unknown;
6785         /* Hexagon hack
6786         if(itype[i]==UJUMP&&rt1[i]==31)
6787         {
6788           uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6789         }
6790         if(itype[i]==RJUMP&&rs1[i]==31)
6791         {
6792           uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6793         }
6794         if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6795           if(itype[i]==UJUMP&&rt1[i]==31)
6796           {
6797             //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6798             uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6799           }
6800           if(itype[i]==RJUMP&&rs1[i]==31)
6801           {
6802             //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6803             uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6804           }
6805         }*/
6806         branch_unneeded_reg[i]=u;
6807         branch_unneeded_reg_upper[i]=uu;
6808         // Merge in delay slot
6809         tdep=(~uu>>rt1[i+1])&1;
6810         u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6811         uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6812         u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6813         uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6814         uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6815         u|=1;uu|=1;
6816         gte_u|=gte_rt[i+1];
6817         gte_u&=~gte_rs[i+1];
6818         // If branch is "likely" (and conditional)
6819         // then we skip the delay slot on the fall-thru path
6820         if(likely[i]) {
6821           if(i<slen-1) {
6822             u&=unneeded_reg[i+2];
6823             uu&=unneeded_reg_upper[i+2];
6824             gte_u&=gte_unneeded[i+2];
6825           }
6826           else
6827           {
6828             u=1;
6829             uu=1;
6830             gte_u=gte_u_unknown;
6831           }
6832         }
6833       }
6834       else
6835       {
6836         // Internal branch, flag target
6837         bt[(ba[i]-start)>>2]=1;
6838         if(ba[i]<=start+i*4) {
6839           // Backward branch
6840           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6841           {
6842             // Unconditional branch
6843             temp_u=1;temp_uu=1;
6844             temp_gte_u=0;
6845           } else {
6846             // Conditional branch (not taken case)
6847             temp_u=unneeded_reg[i+2];
6848             temp_uu=unneeded_reg_upper[i+2];
6849             temp_gte_u&=gte_unneeded[i+2];
6850           }
6851           // Merge in delay slot
6852           tdep=(~temp_uu>>rt1[i+1])&1;
6853           temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6854           temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6855           temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6856           temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6857           temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6858           temp_u|=1;temp_uu|=1;
6859           temp_gte_u|=gte_rt[i+1];
6860           temp_gte_u&=~gte_rs[i+1];
6861           // If branch is "likely" (and conditional)
6862           // then we skip the delay slot on the fall-thru path
6863           if(likely[i]) {
6864             if(i<slen-1) {
6865               temp_u&=unneeded_reg[i+2];
6866               temp_uu&=unneeded_reg_upper[i+2];
6867               temp_gte_u&=gte_unneeded[i+2];
6868             }
6869             else
6870             {
6871               temp_u=1;
6872               temp_uu=1;
6873               temp_gte_u=gte_u_unknown;
6874             }
6875           }
6876           tdep=(~temp_uu>>rt1[i])&1;
6877           temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6878           temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6879           temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6880           temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6881           temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6882           temp_u|=1;temp_uu|=1;
6883           temp_gte_u|=gte_rt[i];
6884           temp_gte_u&=~gte_rs[i];
6885           unneeded_reg[i]=temp_u;
6886           unneeded_reg_upper[i]=temp_uu;
6887           gte_unneeded[i]=temp_gte_u;
6888           // Only go three levels deep.  This recursion can take an
6889           // excessive amount of time if there are a lot of nested loops.
6890           if(r<2) {
6891             unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6892           }else{
6893             unneeded_reg[(ba[i]-start)>>2]=1;
6894             unneeded_reg_upper[(ba[i]-start)>>2]=1;
6895             gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6896           }
6897         } /*else*/ if(1) {
6898           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6899           {
6900             // Unconditional branch
6901             u=unneeded_reg[(ba[i]-start)>>2];
6902             uu=unneeded_reg_upper[(ba[i]-start)>>2];
6903             gte_u=gte_unneeded[(ba[i]-start)>>2];
6904             branch_unneeded_reg[i]=u;
6905             branch_unneeded_reg_upper[i]=uu;
6906         //u=1;
6907         //uu=1;
6908         //branch_unneeded_reg[i]=u;
6909         //branch_unneeded_reg_upper[i]=uu;
6910             // Merge in delay slot
6911             tdep=(~uu>>rt1[i+1])&1;
6912             u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6913             uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6914             u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6915             uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6916             uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6917             u|=1;uu|=1;
6918             gte_u|=gte_rt[i+1];
6919             gte_u&=~gte_rs[i+1];
6920           } else {
6921             // Conditional branch
6922             b=unneeded_reg[(ba[i]-start)>>2];
6923             bu=unneeded_reg_upper[(ba[i]-start)>>2];
6924             gte_bu=gte_unneeded[(ba[i]-start)>>2];
6925             branch_unneeded_reg[i]=b;
6926             branch_unneeded_reg_upper[i]=bu;
6927         //b=1;
6928         //bu=1;
6929         //branch_unneeded_reg[i]=b;
6930         //branch_unneeded_reg_upper[i]=bu;
6931             // Branch delay slot
6932             tdep=(~uu>>rt1[i+1])&1;
6933             b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6934             bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6935             b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6936             bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6937             bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6938             b|=1;bu|=1;
6939             gte_bu|=gte_rt[i+1];
6940             gte_bu&=~gte_rs[i+1];
6941             // If branch is "likely" then we skip the
6942             // delay slot on the fall-thru path
6943             if(likely[i]) {
6944               u=b;
6945               uu=bu;
6946               gte_u=gte_bu;
6947               if(i<slen-1) {
6948                 u&=unneeded_reg[i+2];
6949                 uu&=unneeded_reg_upper[i+2];
6950                 gte_u&=gte_unneeded[i+2];
6951         //u=1;
6952         //uu=1;
6953               }
6954             } else {
6955               u&=b;
6956               uu&=bu;
6957               gte_u&=gte_bu;
6958         //u=1;
6959         //uu=1;
6960             }
6961             if(i<slen-1) {
6962               branch_unneeded_reg[i]&=unneeded_reg[i+2];
6963               branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6964         //branch_unneeded_reg[i]=1;
6965         //branch_unneeded_reg_upper[i]=1;
6966             } else {
6967               branch_unneeded_reg[i]=1;
6968               branch_unneeded_reg_upper[i]=1;
6969             }
6970           }
6971         }
6972       }
6973     }
6974     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6975     {
6976       // SYSCALL instruction (software interrupt)
6977       u=1;
6978       uu=1;
6979     }
6980     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6981     {
6982       // ERET instruction (return from interrupt)
6983       u=1;
6984       uu=1;
6985     }
6986     //u=uu=1; // DEBUG
6987     tdep=(~uu>>rt1[i])&1;
6988     // Written registers are unneeded
6989     u|=1LL<<rt1[i];
6990     u|=1LL<<rt2[i];
6991     uu|=1LL<<rt1[i];
6992     uu|=1LL<<rt2[i];
6993     gte_u|=gte_rt[i];
6994     // Accessed registers are needed
6995     u&=~(1LL<<rs1[i]);
6996     u&=~(1LL<<rs2[i]);
6997     uu&=~(1LL<<us1[i]);
6998     uu&=~(1LL<<us2[i]);
6999     gte_u&=~gte_rs[i];
7000     if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
7001       gte_u|=gte_rs[i]&gte_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7002     // Source-target dependencies
7003     uu&=~(tdep<<dep1[i]);
7004     uu&=~(tdep<<dep2[i]);
7005     // R0 is always unneeded
7006     u|=1;uu|=1;
7007     // Save it
7008     unneeded_reg[i]=u;
7009     unneeded_reg_upper[i]=uu;
7010     gte_unneeded[i]=gte_u;
7011     /*
7012     printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7013     printf("U:");
7014     int r;
7015     for(r=1;r<=CCREG;r++) {
7016       if((unneeded_reg[i]>>r)&1) {
7017         if(r==HIREG) printf(" HI");
7018         else if(r==LOREG) printf(" LO");
7019         else printf(" r%d",r);
7020       }
7021     }
7022     printf(" UU:");
7023     for(r=1;r<=CCREG;r++) {
7024       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7025         if(r==HIREG) printf(" HI");
7026         else if(r==LOREG) printf(" LO");
7027         else printf(" r%d",r);
7028       }
7029     }
7030     printf("\n");*/
7031   }
7032 #ifdef FORCE32
7033   for (i=iend;i>=istart;i--)
7034   {
7035     unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7036   }
7037 #endif
7038 }
7039
7040 // Identify registers which are likely to contain 32-bit values
7041 // This is used to predict whether any branches will jump to a
7042 // location with 64-bit values in registers.
7043 static void provisional_32bit()
7044 {
7045   int i,j;
7046   uint64_t is32=1;
7047   uint64_t lastbranch=1;
7048
7049   for(i=0;i<slen;i++)
7050   {
7051     if(i>0) {
7052       if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7053         if(i>1) is32=lastbranch;
7054         else is32=1;
7055       }
7056     }
7057     if(i>1)
7058     {
7059       if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7060         if(likely[i-2]) {
7061           if(i>2) is32=lastbranch;
7062           else is32=1;
7063         }
7064       }
7065       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7066       {
7067         if(rs1[i-2]==0||rs2[i-2]==0)
7068         {
7069           if(rs1[i-2]) {
7070             is32|=1LL<<rs1[i-2];
7071           }
7072           if(rs2[i-2]) {
7073             is32|=1LL<<rs2[i-2];
7074           }
7075         }
7076       }
7077     }
7078     // If something jumps here with 64-bit values
7079     // then promote those registers to 64 bits
7080     if(bt[i])
7081     {
7082       uint64_t temp_is32=is32;
7083       for(j=i-1;j>=0;j--)
7084       {
7085         if(ba[j]==start+i*4)
7086           //temp_is32&=branch_regs[j].is32;
7087           temp_is32&=p32[j];
7088       }
7089       for(j=i;j<slen;j++)
7090       {
7091         if(ba[j]==start+i*4)
7092           temp_is32=1;
7093       }
7094       is32=temp_is32;
7095     }
7096     int type=itype[i];
7097     int op=opcode[i];
7098     int op2=opcode2[i];
7099     int rt=rt1[i];
7100     int s1=rs1[i];
7101     int s2=rs2[i];
7102     if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7103       // Branches don't write registers, consider the delay slot instead.
7104       type=itype[i+1];
7105       op=opcode[i+1];
7106       op2=opcode2[i+1];
7107       rt=rt1[i+1];
7108       s1=rs1[i+1];
7109       s2=rs2[i+1];
7110       lastbranch=is32;
7111     }
7112     switch(type) {
7113       case LOAD:
7114         if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7115            opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7116           is32&=~(1LL<<rt);
7117         else
7118           is32|=1LL<<rt;
7119         break;
7120       case STORE:
7121       case STORELR:
7122         break;
7123       case LOADLR:
7124         if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7125         if(op==0x22) is32|=1LL<<rt; // LWL
7126         break;
7127       case IMM16:
7128         if (op==0x08||op==0x09|| // ADDI/ADDIU
7129             op==0x0a||op==0x0b|| // SLTI/SLTIU
7130             op==0x0c|| // ANDI
7131             op==0x0f)  // LUI
7132         {
7133           is32|=1LL<<rt;
7134         }
7135         if(op==0x18||op==0x19) { // DADDI/DADDIU
7136           is32&=~(1LL<<rt);
7137           //if(imm[i]==0)
7138           //  is32|=((is32>>s1)&1LL)<<rt;
7139         }
7140         if(op==0x0d||op==0x0e) { // ORI/XORI
7141           uint64_t sr=((is32>>s1)&1LL);
7142           is32&=~(1LL<<rt);
7143           is32|=sr<<rt;
7144         }
7145         break;
7146       case UJUMP:
7147         break;
7148       case RJUMP:
7149         break;
7150       case CJUMP:
7151         break;
7152       case SJUMP:
7153         break;
7154       case FJUMP:
7155         break;
7156       case ALU:
7157         if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7158           is32|=1LL<<rt;
7159         }
7160         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7161           is32|=1LL<<rt;
7162         }
7163         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7164           uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7165           is32&=~(1LL<<rt);
7166           is32|=sr<<rt;
7167         }
7168         else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7169           if(s1==0&&s2==0) {
7170             is32|=1LL<<rt;
7171           }
7172           else if(s2==0) {
7173             uint64_t sr=((is32>>s1)&1LL);
7174             is32&=~(1LL<<rt);
7175             is32|=sr<<rt;
7176           }
7177           else if(s1==0) {
7178             uint64_t sr=((is32>>s2)&1LL);
7179             is32&=~(1LL<<rt);
7180             is32|=sr<<rt;
7181           }
7182           else {
7183             is32&=~(1LL<<rt);
7184           }
7185         }
7186         else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7187           if(s1==0&&s2==0) {
7188             is32|=1LL<<rt;
7189           }
7190           else if(s2==0) {
7191             uint64_t sr=((is32>>s1)&1LL);
7192             is32&=~(1LL<<rt);
7193             is32|=sr<<rt;
7194           }
7195           else {
7196             is32&=~(1LL<<rt);
7197           }
7198         }
7199         break;
7200       case MULTDIV:
7201         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7202           is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7203         }
7204         else {
7205           is32|=(1LL<<HIREG)|(1LL<<LOREG);
7206         }
7207         break;
7208       case MOV:
7209         {
7210           uint64_t sr=((is32>>s1)&1LL);
7211           is32&=~(1LL<<rt);
7212           is32|=sr<<rt;
7213         }
7214         break;
7215       case SHIFT:
7216         if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7217         else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7218         break;
7219       case SHIFTIMM:
7220         is32|=1LL<<rt;
7221         // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7222         if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7223         break;
7224       case COP0:
7225         if(op2==0) is32|=1LL<<rt; // MFC0
7226         break;
7227       case COP1:
7228       case COP2:
7229         if(op2==0) is32|=1LL<<rt; // MFC1
7230         if(op2==1) is32&=~(1LL<<rt); // DMFC1
7231         if(op2==2) is32|=1LL<<rt; // CFC1
7232         break;
7233       case C1LS:
7234       case C2LS:
7235         break;
7236       case FLOAT:
7237       case FCONV:
7238         break;
7239       case FCOMP:
7240         break;
7241       case C2OP:
7242       case SYSCALL:
7243       case HLECALL:
7244         break;
7245       default:
7246         break;
7247     }
7248     is32|=1;
7249     p32[i]=is32;
7250
7251     if(i>0)
7252     {
7253       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7254       {
7255         if(rt1[i-1]==31) // JAL/JALR
7256         {
7257           // Subroutine call will return here, don't alloc any registers
7258           is32=1;
7259         }
7260         else if(i+1<slen)
7261         {
7262           // Internal branch will jump here, match registers to caller
7263           is32=0x3FFFFFFFFLL;
7264         }
7265       }
7266     }
7267   }
7268 }
7269
7270 // Identify registers which may be assumed to contain 32-bit values
7271 // and where optimizations will rely on this.
7272 // This is used to determine whether backward branches can safely
7273 // jump to a location with 64-bit values in registers.
7274 static void provisional_r32()
7275 {
7276   u_int r32=0;
7277   int i;
7278
7279   for (i=slen-1;i>=0;i--)
7280   {
7281     int hr;
7282     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7283     {
7284       if(ba[i]<start || ba[i]>=(start+slen*4))
7285       {
7286         // Branch out of this block, don't need anything
7287         r32=0;
7288       }
7289       else
7290       {
7291         // Internal branch
7292         // Need whatever matches the target
7293         // (and doesn't get overwritten by the delay slot instruction)
7294         r32=0;
7295         int t=(ba[i]-start)>>2;
7296         if(ba[i]>start+i*4) {
7297           // Forward branch
7298           //if(!(requires_32bit[t]&~regs[i].was32))
7299           //  r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7300           if(!(pr32[t]&~regs[i].was32))
7301             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7302         }else{
7303           // Backward branch
7304           if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7305             r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7306         }
7307       }
7308       // Conditional branch may need registers for following instructions
7309       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7310       {
7311         if(i<slen-2) {
7312           //r32|=requires_32bit[i+2];
7313           r32|=pr32[i+2];
7314           r32&=regs[i].was32;
7315           // Mark this address as a branch target since it may be called
7316           // upon return from interrupt
7317           //bt[i+2]=1;
7318         }
7319       }
7320       // Merge in delay slot
7321       if(!likely[i]) {
7322         // These are overwritten unless the branch is "likely"
7323         // and the delay slot is nullified if not taken
7324         r32&=~(1LL<<rt1[i+1]);
7325         r32&=~(1LL<<rt2[i+1]);
7326       }
7327       // Assume these are needed (delay slot)
7328       if(us1[i+1]>0)
7329       {
7330         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7331       }
7332       if(us2[i+1]>0)
7333       {
7334         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7335       }
7336       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7337       {
7338         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7339       }
7340       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7341       {
7342         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7343       }
7344     }
7345     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7346     {
7347       // SYSCALL instruction (software interrupt)
7348       r32=0;
7349     }
7350     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7351     {
7352       // ERET instruction (return from interrupt)
7353       r32=0;
7354     }
7355     // Check 32 bits
7356     r32&=~(1LL<<rt1[i]);
7357     r32&=~(1LL<<rt2[i]);
7358     if(us1[i]>0)
7359     {
7360       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7361     }
7362     if(us2[i]>0)
7363     {
7364       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7365     }
7366     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7367     {
7368       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7369     }
7370     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7371     {
7372       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7373     }
7374     //requires_32bit[i]=r32;
7375     pr32[i]=r32;
7376
7377     // Dirty registers which are 32-bit, require 32-bit input
7378     // as they will be written as 32-bit values
7379     for(hr=0;hr<HOST_REGS;hr++)
7380     {
7381       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
7382         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7383           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7384           pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7385           //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7386         }
7387       }
7388     }
7389   }
7390 }
7391
7392 // Write back dirty registers as soon as we will no longer modify them,
7393 // so that we don't end up with lots of writes at the branches.
7394 void clean_registers(int istart,int iend,int wr)
7395 {
7396   int i;
7397   int r;
7398   u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7399   u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7400   if(iend==slen-1) {
7401     will_dirty_i=will_dirty_next=0;
7402     wont_dirty_i=wont_dirty_next=0;
7403   }else{
7404     will_dirty_i=will_dirty_next=will_dirty[iend+1];
7405     wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7406   }
7407   for (i=iend;i>=istart;i--)
7408   {
7409     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7410     {
7411       if(ba[i]<start || ba[i]>=(start+slen*4))
7412       {
7413         // Branch out of this block, flush all regs
7414         if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7415         {
7416           // Unconditional branch
7417           will_dirty_i=0;
7418           wont_dirty_i=0;
7419           // Merge in delay slot (will dirty)
7420           for(r=0;r<HOST_REGS;r++) {
7421             if(r!=EXCLUDE_REG) {
7422               if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7423               if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7424               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7425               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7426               if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7427               if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7428               if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7429               if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7430               if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7431               if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7432               if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7433               if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7434               if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7435               if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7436             }
7437           }
7438         }
7439         else
7440         {
7441           // Conditional branch
7442           will_dirty_i=0;
7443           wont_dirty_i=wont_dirty_next;
7444           // Merge in delay slot (will dirty)
7445           for(r=0;r<HOST_REGS;r++) {
7446             if(r!=EXCLUDE_REG) {
7447               if(!likely[i]) {
7448                 // Might not dirty if likely branch is not taken
7449                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7450                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7451                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7452                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7453                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7454                 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7455                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7456                 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7457                 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7458                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7459                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7460                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7461                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7462                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7463               }
7464             }
7465           }
7466         }
7467         // Merge in delay slot (wont dirty)
7468         for(r=0;r<HOST_REGS;r++) {
7469           if(r!=EXCLUDE_REG) {
7470             if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7471             if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7472             if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7473             if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7474             if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7475             if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7476             if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7477             if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7478             if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7479             if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7480           }
7481         }
7482         if(wr) {
7483           #ifndef DESTRUCTIVE_WRITEBACK
7484           branch_regs[i].dirty&=wont_dirty_i;
7485           #endif
7486           branch_regs[i].dirty|=will_dirty_i;
7487         }
7488       }
7489       else
7490       {
7491         // Internal branch
7492         if(ba[i]<=start+i*4) {
7493           // Backward branch
7494           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7495           {
7496             // Unconditional branch
7497             temp_will_dirty=0;
7498             temp_wont_dirty=0;
7499             // Merge in delay slot (will dirty)
7500             for(r=0;r<HOST_REGS;r++) {
7501               if(r!=EXCLUDE_REG) {
7502                 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7503                 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7504                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7505                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7506                 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7507                 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7508                 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7509                 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7510                 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7511                 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7512                 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7513                 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7514                 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7515                 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7516               }
7517             }
7518           } else {
7519             // Conditional branch (not taken case)
7520             temp_will_dirty=will_dirty_next;
7521             temp_wont_dirty=wont_dirty_next;
7522             // Merge in delay slot (will dirty)
7523             for(r=0;r<HOST_REGS;r++) {
7524               if(r!=EXCLUDE_REG) {
7525                 if(!likely[i]) {
7526                   // Will not dirty if likely branch is not taken
7527                   if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7528                   if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7529                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7530                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7531                   if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7532                   if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7533                   if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7534                   //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7535                   //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7536                   if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7537                   if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7538                   if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7539                   if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7540                   if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7541                 }
7542               }
7543             }
7544           }
7545           // Merge in delay slot (wont dirty)
7546           for(r=0;r<HOST_REGS;r++) {
7547             if(r!=EXCLUDE_REG) {
7548               if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7549               if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7550               if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7551               if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7552               if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7553               if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7554               if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7555               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7556               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7557               if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7558             }
7559           }
7560           // Deal with changed mappings
7561           if(i<iend) {
7562             for(r=0;r<HOST_REGS;r++) {
7563               if(r!=EXCLUDE_REG) {
7564                 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7565                   temp_will_dirty&=~(1<<r);
7566                   temp_wont_dirty&=~(1<<r);
7567                   if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7568                     temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7569                     temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7570                   } else {
7571                     temp_will_dirty|=1<<r;
7572                     temp_wont_dirty|=1<<r;
7573                   }
7574                 }
7575               }
7576             }
7577           }
7578           if(wr) {
7579             will_dirty[i]=temp_will_dirty;
7580             wont_dirty[i]=temp_wont_dirty;
7581             clean_registers((ba[i]-start)>>2,i-1,0);
7582           }else{
7583             // Limit recursion.  It can take an excessive amount
7584             // of time if there are a lot of nested loops.
7585             will_dirty[(ba[i]-start)>>2]=0;
7586             wont_dirty[(ba[i]-start)>>2]=-1;
7587           }
7588         }
7589         /*else*/ if(1)
7590         {
7591           if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7592           {
7593             // Unconditional branch
7594             will_dirty_i=0;
7595             wont_dirty_i=0;
7596           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7597             for(r=0;r<HOST_REGS;r++) {
7598               if(r!=EXCLUDE_REG) {
7599                 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7600                   will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7601                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7602                 }
7603                 if(branch_regs[i].regmap[r]>=0) {
7604                   will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7605                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7606                 }
7607               }
7608             }
7609           //}
7610             // Merge in delay slot
7611             for(r=0;r<HOST_REGS;r++) {
7612               if(r!=EXCLUDE_REG) {
7613                 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7614                 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7615                 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7616                 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7617                 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7618                 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7619                 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7620                 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7621                 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7622                 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7623                 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7624                 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7625                 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7626                 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7627               }
7628             }
7629           } else {
7630             // Conditional branch
7631             will_dirty_i=will_dirty_next;
7632             wont_dirty_i=wont_dirty_next;
7633           //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7634             for(r=0;r<HOST_REGS;r++) {
7635               if(r!=EXCLUDE_REG) {
7636                 signed char target_reg=branch_regs[i].regmap[r];
7637                 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7638                   will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7639                   wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7640                 }
7641                 else if(target_reg>=0) {
7642                   will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7643                   wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7644                 }
7645                 // Treat delay slot as part of branch too
7646                 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7647                   will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7648                   wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7649                 }
7650                 else
7651                 {
7652                   will_dirty[i+1]&=~(1<<r);
7653                 }*/
7654               }
7655             }
7656           //}
7657             // Merge in delay slot
7658             for(r=0;r<HOST_REGS;r++) {
7659               if(r!=EXCLUDE_REG) {
7660                 if(!likely[i]) {
7661                   // Might not dirty if likely branch is not taken
7662                   if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7663                   if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7664                   if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7665                   if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7666                   if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7667                   if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7668                   if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7669                   //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7670                   //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7671                   if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7672                   if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7673                   if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7674                   if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7675                   if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7676                 }
7677               }
7678             }
7679           }
7680           // Merge in delay slot (won't dirty)
7681           for(r=0;r<HOST_REGS;r++) {
7682             if(r!=EXCLUDE_REG) {
7683               if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7684               if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7685               if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7686               if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7687               if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7688               if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7689               if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7690               if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7691               if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7692               if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7693             }
7694           }
7695           if(wr) {
7696             #ifndef DESTRUCTIVE_WRITEBACK
7697             branch_regs[i].dirty&=wont_dirty_i;
7698             #endif
7699             branch_regs[i].dirty|=will_dirty_i;
7700           }
7701         }
7702       }
7703     }
7704     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7705     {
7706       // SYSCALL instruction (software interrupt)
7707       will_dirty_i=0;
7708       wont_dirty_i=0;
7709     }
7710     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7711     {
7712       // ERET instruction (return from interrupt)
7713       will_dirty_i=0;
7714       wont_dirty_i=0;
7715     }
7716     will_dirty_next=will_dirty_i;
7717     wont_dirty_next=wont_dirty_i;
7718     for(r=0;r<HOST_REGS;r++) {
7719       if(r!=EXCLUDE_REG) {
7720         if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7721         if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7722         if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7723         if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7724         if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7725         if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7726         if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7727         if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7728         if(i>istart) {
7729           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7730           {
7731             // Don't store a register immediately after writing it,
7732             // may prevent dual-issue.
7733             if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7734             if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7735           }
7736         }
7737       }
7738     }
7739     // Save it
7740     will_dirty[i]=will_dirty_i;
7741     wont_dirty[i]=wont_dirty_i;
7742     // Mark registers that won't be dirtied as not dirty
7743     if(wr) {
7744       /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7745       for(r=0;r<HOST_REGS;r++) {
7746         if((will_dirty_i>>r)&1) {
7747           printf(" r%d",r);
7748         }
7749       }
7750       printf("\n");*/
7751
7752       //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7753         regs[i].dirty|=will_dirty_i;
7754         #ifndef DESTRUCTIVE_WRITEBACK
7755         regs[i].dirty&=wont_dirty_i;
7756         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7757         {
7758           if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7759             for(r=0;r<HOST_REGS;r++) {
7760               if(r!=EXCLUDE_REG) {
7761                 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7762                   regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7763                 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7764               }
7765             }
7766           }
7767         }
7768         else
7769         {
7770           if(i<iend) {
7771             for(r=0;r<HOST_REGS;r++) {
7772               if(r!=EXCLUDE_REG) {
7773                 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7774                   regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7775                 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7776               }
7777             }
7778           }
7779         }
7780         #endif
7781       //}
7782     }
7783     // Deal with changed mappings
7784     temp_will_dirty=will_dirty_i;
7785     temp_wont_dirty=wont_dirty_i;
7786     for(r=0;r<HOST_REGS;r++) {
7787       if(r!=EXCLUDE_REG) {
7788         int nr;
7789         if(regs[i].regmap[r]==regmap_pre[i][r]) {
7790           if(wr) {
7791             #ifndef DESTRUCTIVE_WRITEBACK
7792             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7793             #endif
7794             regs[i].wasdirty|=will_dirty_i&(1<<r);
7795           }
7796         }
7797         else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7798           // Register moved to a different register
7799           will_dirty_i&=~(1<<r);
7800           wont_dirty_i&=~(1<<r);
7801           will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7802           wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7803           if(wr) {
7804             #ifndef DESTRUCTIVE_WRITEBACK
7805             regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7806             #endif
7807             regs[i].wasdirty|=will_dirty_i&(1<<r);
7808           }
7809         }
7810         else {
7811           will_dirty_i&=~(1<<r);
7812           wont_dirty_i&=~(1<<r);
7813           if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7814             will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7815             wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7816           } else {
7817             wont_dirty_i|=1<<r;
7818             /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7819           }
7820         }
7821       }
7822     }
7823   }
7824 }
7825
7826 #ifdef DISASM
7827   /* disassembly */
7828 void disassemble_inst(int i)
7829 {
7830     if (bt[i]) printf("*"); else printf(" ");
7831     switch(itype[i]) {
7832       case UJUMP:
7833         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7834       case CJUMP:
7835         printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7836       case SJUMP:
7837         printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7838       case FJUMP:
7839         printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7840       case RJUMP:
7841         if (opcode[i]==0x9&&rt1[i]!=31)
7842           printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7843         else
7844           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7845         break;
7846       case SPAN:
7847         printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7848       case IMM16:
7849         if(opcode[i]==0xf) //LUI
7850           printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7851         else
7852           printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7853         break;
7854       case LOAD:
7855       case LOADLR:
7856         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7857         break;
7858       case STORE:
7859       case STORELR:
7860         printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7861         break;
7862       case ALU:
7863       case SHIFT:
7864         printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7865         break;
7866       case MULTDIV:
7867         printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7868         break;
7869       case SHIFTIMM:
7870         printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7871         break;
7872       case MOV:
7873         if((opcode2[i]&0x1d)==0x10)
7874           printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7875         else if((opcode2[i]&0x1d)==0x11)
7876           printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7877         else
7878           printf (" %x: %s\n",start+i*4,insn[i]);
7879         break;
7880       case COP0:
7881         if(opcode2[i]==0)
7882           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7883         else if(opcode2[i]==4)
7884           printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7885         else printf (" %x: %s\n",start+i*4,insn[i]);
7886         break;
7887       case COP1:
7888         if(opcode2[i]<3)
7889           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7890         else if(opcode2[i]>3)
7891           printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7892         else printf (" %x: %s\n",start+i*4,insn[i]);
7893         break;
7894       case COP2:
7895         if(opcode2[i]<3)
7896           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7897         else if(opcode2[i]>3)
7898           printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7899         else printf (" %x: %s\n",start+i*4,insn[i]);
7900         break;
7901       case C1LS:
7902         printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7903         break;
7904       case C2LS:
7905         printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7906         break;
7907       case INTCALL:
7908         printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7909         break;
7910       default:
7911         //printf (" %s %8x\n",insn[i],source[i]);
7912         printf (" %x: %s\n",start+i*4,insn[i]);
7913     }
7914 }
7915 #else
7916 static void disassemble_inst(int i) {}
7917 #endif // DISASM
7918
7919 #define DRC_TEST_VAL 0x74657374
7920
7921 static int new_dynarec_test(void)
7922 {
7923   int (*testfunc)(void) = (void *)out;
7924   int ret;
7925   emit_movimm(DRC_TEST_VAL,0); // test
7926   emit_jmpreg(14);
7927   literal_pool(0);
7928 #ifdef __arm__
7929   __clear_cache((void *)testfunc, out);
7930 #endif
7931   SysPrintf("testing if we can run recompiled code..\n");
7932   ret = testfunc();
7933   if (ret == DRC_TEST_VAL)
7934     SysPrintf("test passed.\n");
7935   else
7936     SysPrintf("test failed: %08x\n", ret);
7937   out=(u_char *)BASE_ADDR;
7938   return ret == DRC_TEST_VAL;
7939 }
7940
7941 // clear the state completely, instead of just marking
7942 // things invalid like invalidate_all_pages() does
7943 void new_dynarec_clear_full()
7944 {
7945   int n;
7946   out=(u_char *)BASE_ADDR;
7947   memset(invalid_code,1,sizeof(invalid_code));
7948   memset(hash_table,0xff,sizeof(hash_table));
7949   memset(mini_ht,-1,sizeof(mini_ht));
7950   memset(restore_candidate,0,sizeof(restore_candidate));
7951   memset(shadow,0,sizeof(shadow));
7952   copy=shadow;
7953   expirep=16384; // Expiry pointer, +2 blocks
7954   pending_exception=0;
7955   literalcount=0;
7956   stop_after_jal=0;
7957   inv_code_start=inv_code_end=~0;
7958   // TLB
7959 #ifndef DISABLE_TLB
7960   using_tlb=0;
7961   for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7962     memory_map[n]=-1;
7963   for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7964     memory_map[n]=((u_int)rdram-0x80000000)>>2;
7965   for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7966     memory_map[n]=-1;
7967 #endif
7968   for(n=0;n<4096;n++) ll_clear(jump_in+n);
7969   for(n=0;n<4096;n++) ll_clear(jump_out+n);
7970   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7971 }
7972
7973 void new_dynarec_init()
7974 {
7975   SysPrintf("Init new dynarec\n");
7976   out=(u_char *)BASE_ADDR;
7977 #if BASE_ADDR_FIXED
7978   if (mmap (out, 1<<TARGET_SIZE_2,
7979             PROT_READ | PROT_WRITE | PROT_EXEC,
7980             MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7981             -1, 0) <= 0) {
7982     SysPrintf("mmap() failed: %s\n", strerror(errno));
7983   }
7984 #else
7985   // not all systems allow execute in data segment by default
7986   if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
7987     SysPrintf("mprotect() failed: %s\n", strerror(errno));
7988 #endif
7989 #ifdef MUPEN64
7990   rdword=&readmem_dword;
7991   fake_pc.f.r.rs=&readmem_dword;
7992   fake_pc.f.r.rt=&readmem_dword;
7993   fake_pc.f.r.rd=&readmem_dword;
7994 #endif
7995   int n;
7996   cycle_multiplier=200;
7997   new_dynarec_clear_full();
7998 #ifdef HOST_IMM8
7999   // Copy this into local area so we don't have to put it in every literal pool
8000   invc_ptr=invalid_code;
8001 #endif
8002 #ifdef MUPEN64
8003   for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8004     writemem[n] = write_nomem_new;
8005     writememb[n] = write_nomemb_new;
8006     writememh[n] = write_nomemh_new;
8007 #ifndef FORCE32
8008     writememd[n] = write_nomemd_new;
8009 #endif
8010     readmem[n] = read_nomem_new;
8011     readmemb[n] = read_nomemb_new;
8012     readmemh[n] = read_nomemh_new;
8013 #ifndef FORCE32
8014     readmemd[n] = read_nomemd_new;
8015 #endif
8016   }
8017   for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8018     writemem[n] = write_rdram_new;
8019     writememb[n] = write_rdramb_new;
8020     writememh[n] = write_rdramh_new;
8021 #ifndef FORCE32
8022     writememd[n] = write_rdramd_new;
8023 #endif
8024   }
8025   for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8026     writemem[n] = write_nomem_new;
8027     writememb[n] = write_nomemb_new;
8028     writememh[n] = write_nomemh_new;
8029 #ifndef FORCE32
8030     writememd[n] = write_nomemd_new;
8031 #endif
8032     readmem[n] = read_nomem_new;
8033     readmemb[n] = read_nomemb_new;
8034     readmemh[n] = read_nomemh_new;
8035 #ifndef FORCE32
8036     readmemd[n] = read_nomemd_new;
8037 #endif
8038   }
8039 #endif
8040   tlb_hacks();
8041   arch_init();
8042   new_dynarec_test();
8043 #ifndef RAM_FIXED
8044   ram_offset=(u_int)rdram-0x80000000;
8045 #endif
8046   if (ram_offset!=0)
8047     SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
8048 }
8049
8050 void new_dynarec_cleanup()
8051 {
8052   int n;
8053   #if BASE_ADDR_FIXED
8054   if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {SysPrintf("munmap() failed\n");}
8055   #endif
8056   for(n=0;n<4096;n++) ll_clear(jump_in+n);
8057   for(n=0;n<4096;n++) ll_clear(jump_out+n);
8058   for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8059   #ifdef ROM_COPY
8060   if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
8061   #endif
8062 }
8063
8064 static u_int *get_source_start(u_int addr, u_int *limit)
8065 {
8066   if (addr < 0x00200000 ||
8067     (0xa0000000 <= addr && addr < 0xa0200000)) {
8068     // used for BIOS calls mostly?
8069     *limit = (addr&0xa0000000)|0x00200000;
8070     return (u_int *)((u_int)rdram + (addr&0x1fffff));
8071   }
8072   else if (!Config.HLE && (
8073     /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8074     (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8075     // BIOS
8076     *limit = (addr & 0xfff00000) | 0x80000;
8077     return (u_int *)((u_int)psxR + (addr&0x7ffff));
8078   }
8079   else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
8080     *limit = (addr & 0x80600000) + 0x00200000;
8081     return (u_int *)((u_int)rdram + (addr&0x1fffff));
8082   }
8083 }
8084
8085 static u_int scan_for_ret(u_int addr)
8086 {
8087   u_int limit = 0;
8088   u_int *mem;
8089
8090   mem = get_source_start(addr, &limit);
8091   if (mem == NULL)
8092     return addr;
8093
8094   if (limit > addr + 0x1000)
8095     limit = addr + 0x1000;
8096   for (; addr < limit; addr += 4, mem++) {
8097     if (*mem == 0x03e00008) // jr $ra
8098       return addr + 8;
8099   }
8100 }
8101
8102 struct savestate_block {
8103   uint32_t addr;
8104   uint32_t regflags;
8105 };
8106
8107 static int addr_cmp(const void *p1_, const void *p2_)
8108 {
8109   const struct savestate_block *p1 = p1_, *p2 = p2_;
8110   return p1->addr - p2->addr;
8111 }
8112
8113 int new_dynarec_save_blocks(void *save, int size)
8114 {
8115   struct savestate_block *blocks = save;
8116   int maxcount = size / sizeof(blocks[0]);
8117   struct savestate_block tmp_blocks[1024];
8118   struct ll_entry *head;
8119   int p, s, d, o, bcnt;
8120   u_int addr;
8121
8122   o = 0;
8123   for (p = 0; p < sizeof(jump_in) / sizeof(jump_in[0]); p++) {
8124     bcnt = 0;
8125     for (head = jump_in[p]; head != NULL; head = head->next) {
8126       tmp_blocks[bcnt].addr = head->vaddr;
8127       tmp_blocks[bcnt].regflags = head->reg_sv_flags;
8128       bcnt++;
8129     }
8130     if (bcnt < 1)
8131       continue;
8132     qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
8133
8134     addr = tmp_blocks[0].addr;
8135     for (s = d = 0; s < bcnt; s++) {
8136       if (tmp_blocks[s].addr < addr)
8137         continue;
8138       if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
8139         tmp_blocks[d++] = tmp_blocks[s];
8140       addr = scan_for_ret(tmp_blocks[s].addr);
8141     }
8142
8143     if (o + d > maxcount)
8144       d = maxcount - o;
8145     memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
8146     o += d;
8147   }
8148
8149   return o * sizeof(blocks[0]);
8150 }
8151
8152 void new_dynarec_load_blocks(const void *save, int size)
8153 {
8154   const struct savestate_block *blocks = save;
8155   int count = size / sizeof(blocks[0]);
8156   u_int regs_save[32];
8157   uint32_t f;
8158   int i, b;
8159
8160   get_addr(psxRegs.pc);
8161
8162   // change GPRs for speculation to at least partially work..
8163   memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
8164   for (i = 1; i < 32; i++)
8165     psxRegs.GPR.r[i] = 0x80000000;
8166
8167   for (b = 0; b < count; b++) {
8168     for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
8169       if (f & 1)
8170         psxRegs.GPR.r[i] = 0x1f800000;
8171     }
8172
8173     get_addr(blocks[b].addr);
8174
8175     for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
8176       if (f & 1)
8177         psxRegs.GPR.r[i] = 0x80000000;
8178     }
8179   }
8180
8181   memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
8182 }
8183
8184 int new_recompile_block(int addr)
8185 {
8186   u_int pagelimit = 0;
8187   u_int state_rflags = 0;
8188   int i;
8189
8190   assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8191   //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8192   //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8193   //if(debug)
8194   //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8195   //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8196   /*if(Count>=312978186) {
8197     rlist();
8198   }*/
8199   //rlist();
8200
8201   // this is just for speculation
8202   for (i = 1; i < 32; i++) {
8203     if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
8204       state_rflags |= 1 << i;
8205   }
8206
8207   start = (u_int)addr&~3;
8208   //assert(((u_int)addr&1)==0);
8209   new_dynarec_did_compile=1;
8210   if (Config.HLE && start == 0x80001000) // hlecall
8211   {
8212     // XXX: is this enough? Maybe check hleSoftCall?
8213     u_int beginning=(u_int)out;
8214     u_int page=get_page(start);
8215     invalid_code[start>>12]=0;
8216     emit_movimm(start,0);
8217     emit_writeword(0,(int)&pcaddr);
8218     emit_jmp((int)new_dyna_leave);
8219     literal_pool(0);
8220 #ifdef __arm__
8221     __clear_cache((void *)beginning,out);
8222 #endif
8223     ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
8224     return 0;
8225   }
8226
8227   source = get_source_start(start, &pagelimit);
8228   if (source == NULL) {
8229     SysPrintf("Compile at bogus memory address: %08x\n", addr);
8230     exit(1);
8231   }
8232
8233   /* Pass 1: disassemble */
8234   /* Pass 2: register dependencies, branch targets */
8235   /* Pass 3: register allocation */
8236   /* Pass 4: branch dependencies */
8237   /* Pass 5: pre-alloc */
8238   /* Pass 6: optimize clean/dirty state */
8239   /* Pass 7: flag 32-bit registers */
8240   /* Pass 8: assembly */
8241   /* Pass 9: linker */
8242   /* Pass 10: garbage collection / free memory */
8243
8244   int j;
8245   int done=0;
8246   unsigned int type,op,op2;
8247
8248   //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8249
8250   /* Pass 1 disassembly */
8251
8252   for(i=0;!done;i++) {
8253     bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8254     minimum_free_regs[i]=0;
8255     opcode[i]=op=source[i]>>26;
8256     switch(op)
8257     {
8258       case 0x00: strcpy(insn[i],"special"); type=NI;
8259         op2=source[i]&0x3f;
8260         switch(op2)
8261         {
8262           case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8263           case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8264           case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8265           case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8266           case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8267           case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8268           case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8269           case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8270           case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8271           case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8272           case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8273           case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8274           case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8275           case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8276           case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8277           case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8278           case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8279           case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8280           case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8281           case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8282           case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8283           case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8284           case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8285           case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8286           case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8287           case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8288           case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8289           case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8290           case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8291           case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8292           case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8293           case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8294           case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8295           case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8296           case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8297 #ifndef FORCE32
8298           case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8299           case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8300           case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8301           case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8302           case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8303           case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8304           case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8305           case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8306           case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8307           case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8308           case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8309           case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8310           case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8311           case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8312           case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8313           case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8314           case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8315 #endif
8316         }
8317         break;
8318       case 0x01: strcpy(insn[i],"regimm"); type=NI;
8319         op2=(source[i]>>16)&0x1f;
8320         switch(op2)
8321         {
8322           case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8323           case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8324           case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8325           case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8326           case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8327           case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8328           case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8329           case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8330           case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8331           case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8332           case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8333           case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8334           case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8335           case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8336         }
8337         break;
8338       case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8339       case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8340       case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8341       case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8342       case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8343       case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8344       case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8345       case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8346       case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8347       case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8348       case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8349       case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8350       case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8351       case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8352       case 0x10: strcpy(insn[i],"cop0"); type=NI;
8353         op2=(source[i]>>21)&0x1f;
8354         switch(op2)
8355         {
8356           case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8357           case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8358           case 0x10: strcpy(insn[i],"tlb"); type=NI;
8359           switch(source[i]&0x3f)
8360           {
8361             case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8362             case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8363             case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8364             case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8365 #ifdef PCSX
8366             case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8367 #else
8368             case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8369 #endif
8370           }
8371         }
8372         break;
8373       case 0x11: strcpy(insn[i],"cop1"); type=NI;
8374         op2=(source[i]>>21)&0x1f;
8375         switch(op2)
8376         {
8377           case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8378           case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8379           case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8380           case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8381           case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8382           case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8383           case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8384           switch((source[i]>>16)&0x3)
8385           {
8386             case 0x00: strcpy(insn[i],"BC1F"); break;
8387             case 0x01: strcpy(insn[i],"BC1T"); break;
8388             case 0x02: strcpy(insn[i],"BC1FL"); break;
8389             case 0x03: strcpy(insn[i],"BC1TL"); break;
8390           }
8391           break;
8392           case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8393           switch(source[i]&0x3f)
8394           {
8395             case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8396             case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8397             case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8398             case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8399             case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8400             case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8401             case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8402             case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8403             case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8404             case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8405             case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8406             case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8407             case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8408             case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8409             case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8410             case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8411             case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8412             case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8413             case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8414             case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8415             case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8416             case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8417             case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8418             case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8419             case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8420             case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8421             case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8422             case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8423             case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8424             case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8425             case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8426             case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8427             case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8428             case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8429             case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8430           }
8431           break;
8432           case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8433           switch(source[i]&0x3f)
8434           {
8435             case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8436             case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8437             case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8438             case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8439             case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8440             case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8441             case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8442             case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8443             case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8444             case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8445             case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8446             case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8447             case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8448             case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8449             case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8450             case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8451             case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8452             case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8453             case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8454             case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8455             case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8456             case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8457             case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8458             case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8459             case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8460             case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8461             case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8462             case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8463             case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8464             case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8465             case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8466             case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8467             case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8468             case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8469             case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8470           }
8471           break;
8472           case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8473           switch(source[i]&0x3f)
8474           {
8475             case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8476             case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8477           }
8478           break;
8479           case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8480           switch(source[i]&0x3f)
8481           {
8482             case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8483             case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8484           }
8485           break;
8486         }
8487         break;
8488 #ifndef FORCE32
8489       case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8490       case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8491       case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8492       case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8493       case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8494       case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8495       case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8496       case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8497 #endif
8498       case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8499       case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8500       case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8501       case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8502       case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8503       case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8504       case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8505 #ifndef FORCE32
8506       case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8507 #endif
8508       case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8509       case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8510       case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8511       case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8512 #ifndef FORCE32
8513       case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8514       case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8515 #endif
8516       case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8517       case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8518       case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8519       case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8520 #ifndef FORCE32
8521       case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8522       case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8523       case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8524 #endif
8525       case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8526       case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8527 #ifndef FORCE32
8528       case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8529       case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8530       case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8531 #endif
8532 #ifdef PCSX
8533       case 0x12: strcpy(insn[i],"COP2"); type=NI;
8534         op2=(source[i]>>21)&0x1f;
8535         //if (op2 & 0x10) {
8536         if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8537           if (gte_handlers[source[i]&0x3f]!=NULL) {
8538             if (gte_regnames[source[i]&0x3f]!=NULL)
8539               strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8540             else
8541               snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8542             type=C2OP;
8543           }
8544         }
8545         else switch(op2)
8546         {
8547           case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8548           case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8549           case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8550           case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8551         }
8552         break;
8553       case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8554       case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8555       case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8556 #endif
8557       default: strcpy(insn[i],"???"); type=NI;
8558         SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8559         break;
8560     }
8561     itype[i]=type;
8562     opcode2[i]=op2;
8563     /* Get registers/immediates */
8564     lt1[i]=0;
8565     us1[i]=0;
8566     us2[i]=0;
8567     dep1[i]=0;
8568     dep2[i]=0;
8569     gte_rs[i]=gte_rt[i]=0;
8570     switch(type) {
8571       case LOAD:
8572         rs1[i]=(source[i]>>21)&0x1f;
8573         rs2[i]=0;
8574         rt1[i]=(source[i]>>16)&0x1f;
8575         rt2[i]=0;
8576         imm[i]=(short)source[i];
8577         break;
8578       case STORE:
8579       case STORELR:
8580         rs1[i]=(source[i]>>21)&0x1f;
8581         rs2[i]=(source[i]>>16)&0x1f;
8582         rt1[i]=0;
8583         rt2[i]=0;
8584         imm[i]=(short)source[i];
8585         if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8586         break;
8587       case LOADLR:
8588         // LWL/LWR only load part of the register,
8589         // therefore the target register must be treated as a source too
8590         rs1[i]=(source[i]>>21)&0x1f;
8591         rs2[i]=(source[i]>>16)&0x1f;
8592         rt1[i]=(source[i]>>16)&0x1f;
8593         rt2[i]=0;
8594         imm[i]=(short)source[i];
8595         if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8596         if(op==0x26) dep1[i]=rt1[i]; // LWR
8597         break;
8598       case IMM16:
8599         if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8600         else rs1[i]=(source[i]>>21)&0x1f;
8601         rs2[i]=0;
8602         rt1[i]=(source[i]>>16)&0x1f;
8603         rt2[i]=0;
8604         if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8605           imm[i]=(unsigned short)source[i];
8606         }else{
8607           imm[i]=(short)source[i];
8608         }
8609         if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8610         if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8611         if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8612         break;
8613       case UJUMP:
8614         rs1[i]=0;
8615         rs2[i]=0;
8616         rt1[i]=0;
8617         rt2[i]=0;
8618         // The JAL instruction writes to r31.
8619         if (op&1) {
8620           rt1[i]=31;
8621         }
8622         rs2[i]=CCREG;
8623         break;
8624       case RJUMP:
8625         rs1[i]=(source[i]>>21)&0x1f;
8626         rs2[i]=0;
8627         rt1[i]=0;
8628         rt2[i]=0;
8629         // The JALR instruction writes to rd.
8630         if (op2&1) {
8631           rt1[i]=(source[i]>>11)&0x1f;
8632         }
8633         rs2[i]=CCREG;
8634         break;
8635       case CJUMP:
8636         rs1[i]=(source[i]>>21)&0x1f;
8637         rs2[i]=(source[i]>>16)&0x1f;
8638         rt1[i]=0;
8639         rt2[i]=0;
8640         if(op&2) { // BGTZ/BLEZ
8641           rs2[i]=0;
8642         }
8643         us1[i]=rs1[i];
8644         us2[i]=rs2[i];
8645         likely[i]=op>>4;
8646         break;
8647       case SJUMP:
8648         rs1[i]=(source[i]>>21)&0x1f;
8649         rs2[i]=CCREG;
8650         rt1[i]=0;
8651         rt2[i]=0;
8652         us1[i]=rs1[i];
8653         if(op2&0x10) { // BxxAL
8654           rt1[i]=31;
8655           // NOTE: If the branch is not taken, r31 is still overwritten
8656         }
8657         likely[i]=(op2&2)>>1;
8658         break;
8659       case FJUMP:
8660         rs1[i]=FSREG;
8661         rs2[i]=CSREG;
8662         rt1[i]=0;
8663         rt2[i]=0;
8664         likely[i]=((source[i])>>17)&1;
8665         break;
8666       case ALU:
8667         rs1[i]=(source[i]>>21)&0x1f; // source
8668         rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8669         rt1[i]=(source[i]>>11)&0x1f; // destination
8670         rt2[i]=0;
8671         if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8672           us1[i]=rs1[i];us2[i]=rs2[i];
8673         }
8674         else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8675           dep1[i]=rs1[i];dep2[i]=rs2[i];
8676         }
8677         else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8678           dep1[i]=rs1[i];dep2[i]=rs2[i];
8679         }
8680         break;
8681       case MULTDIV:
8682         rs1[i]=(source[i]>>21)&0x1f; // source
8683         rs2[i]=(source[i]>>16)&0x1f; // divisor
8684         rt1[i]=HIREG;
8685         rt2[i]=LOREG;
8686         if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8687           us1[i]=rs1[i];us2[i]=rs2[i];
8688         }
8689         break;
8690       case MOV:
8691         rs1[i]=0;
8692         rs2[i]=0;
8693         rt1[i]=0;
8694         rt2[i]=0;
8695         if(op2==0x10) rs1[i]=HIREG; // MFHI
8696         if(op2==0x11) rt1[i]=HIREG; // MTHI
8697         if(op2==0x12) rs1[i]=LOREG; // MFLO
8698         if(op2==0x13) rt1[i]=LOREG; // MTLO
8699         if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8700         if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8701         dep1[i]=rs1[i];
8702         break;
8703       case SHIFT:
8704         rs1[i]=(source[i]>>16)&0x1f; // target of shift
8705         rs2[i]=(source[i]>>21)&0x1f; // shift amount
8706         rt1[i]=(source[i]>>11)&0x1f; // destination
8707         rt2[i]=0;
8708         // DSLLV/DSRLV/DSRAV are 64-bit
8709         if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8710         break;
8711       case SHIFTIMM:
8712         rs1[i]=(source[i]>>16)&0x1f;
8713         rs2[i]=0;
8714         rt1[i]=(source[i]>>11)&0x1f;
8715         rt2[i]=0;
8716         imm[i]=(source[i]>>6)&0x1f;
8717         // DSxx32 instructions
8718         if(op2>=0x3c) imm[i]|=0x20;
8719         // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8720         if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8721         break;
8722       case COP0:
8723         rs1[i]=0;
8724         rs2[i]=0;
8725         rt1[i]=0;
8726         rt2[i]=0;
8727         if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8728         if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8729         if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8730         if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8731         break;
8732       case COP1:
8733         rs1[i]=0;
8734         rs2[i]=0;
8735         rt1[i]=0;
8736         rt2[i]=0;
8737         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8738         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8739         if(op2==5) us1[i]=rs1[i]; // DMTC1
8740         rs2[i]=CSREG;
8741         break;
8742       case COP2:
8743         rs1[i]=0;
8744         rs2[i]=0;
8745         rt1[i]=0;
8746         rt2[i]=0;
8747         if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8748         if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8749         rs2[i]=CSREG;
8750         int gr=(source[i]>>11)&0x1F;
8751         switch(op2)
8752         {
8753           case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8754           case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8755           case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8756           case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8757         }
8758         break;
8759       case C1LS:
8760         rs1[i]=(source[i]>>21)&0x1F;
8761         rs2[i]=CSREG;
8762         rt1[i]=0;
8763         rt2[i]=0;
8764         imm[i]=(short)source[i];
8765         break;
8766       case C2LS:
8767         rs1[i]=(source[i]>>21)&0x1F;
8768         rs2[i]=0;
8769         rt1[i]=0;
8770         rt2[i]=0;
8771         imm[i]=(short)source[i];
8772         if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8773         else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8774         break;
8775       case C2OP:
8776         rs1[i]=0;
8777         rs2[i]=0;
8778         rt1[i]=0;
8779         rt2[i]=0;
8780         gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8781         gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8782         gte_rt[i]|=1ll<<63; // every op changes flags
8783         if((source[i]&0x3f)==GTE_MVMVA) {
8784           int v = (source[i] >> 15) & 3;
8785           gte_rs[i]&=~0xe3fll;
8786           if(v==3) gte_rs[i]|=0xe00ll;
8787           else gte_rs[i]|=3ll<<(v*2);
8788         }
8789         break;
8790       case FLOAT:
8791       case FCONV:
8792         rs1[i]=0;
8793         rs2[i]=CSREG;
8794         rt1[i]=0;
8795         rt2[i]=0;
8796         break;
8797       case FCOMP:
8798         rs1[i]=FSREG;
8799         rs2[i]=CSREG;
8800         rt1[i]=FSREG;
8801         rt2[i]=0;
8802         break;
8803       case SYSCALL:
8804       case HLECALL:
8805       case INTCALL:
8806         rs1[i]=CCREG;
8807         rs2[i]=0;
8808         rt1[i]=0;
8809         rt2[i]=0;
8810         break;
8811       default:
8812         rs1[i]=0;
8813         rs2[i]=0;
8814         rt1[i]=0;
8815         rt2[i]=0;
8816     }
8817     /* Calculate branch target addresses */
8818     if(type==UJUMP)
8819       ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8820     else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8821       ba[i]=start+i*4+8; // Ignore never taken branch
8822     else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8823       ba[i]=start+i*4+8; // Ignore never taken branch
8824     else if(type==CJUMP||type==SJUMP||type==FJUMP)
8825       ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8826     else ba[i]=-1;
8827 #ifdef PCSX
8828     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8829       int do_in_intrp=0;
8830       // branch in delay slot?
8831       if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8832         // don't handle first branch and call interpreter if it's hit
8833         SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8834         do_in_intrp=1;
8835       }
8836       // basic load delay detection
8837       else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8838         int t=(ba[i-1]-start)/4;
8839         if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8840           // jump target wants DS result - potential load delay effect
8841           SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
8842           do_in_intrp=1;
8843           bt[t+1]=1; // expected return from interpreter
8844         }
8845         else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8846               !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8847           // v0 overwrite like this is a sign of trouble, bail out
8848           SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8849           do_in_intrp=1;
8850         }
8851       }
8852       if(do_in_intrp) {
8853         rs1[i-1]=CCREG;
8854         rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8855         ba[i-1]=-1;
8856         itype[i-1]=INTCALL;
8857         done=2;
8858         i--; // don't compile the DS
8859       }
8860     }
8861 #endif
8862     /* Is this the end of the block? */
8863     if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8864       if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8865         done=2;
8866       }
8867       else {
8868         if(stop_after_jal) done=1;
8869         // Stop on BREAK
8870         if((source[i+1]&0xfc00003f)==0x0d) done=1;
8871       }
8872       // Don't recompile stuff that's already compiled
8873       if(check_addr(start+i*4+4)) done=1;
8874       // Don't get too close to the limit
8875       if(i>MAXBLOCK/2) done=1;
8876     }
8877     if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8878     if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8879     if(done==2) {
8880       // Does the block continue due to a branch?
8881       for(j=i-1;j>=0;j--)
8882       {
8883         if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8884         if(ba[j]==start+i*4+4) done=j=0;
8885         if(ba[j]==start+i*4+8) done=j=0;
8886       }
8887     }
8888     //assert(i<MAXBLOCK-1);
8889     if(start+i*4==pagelimit-4) done=1;
8890     assert(start+i*4<pagelimit);
8891     if (i==MAXBLOCK-1) done=1;
8892     // Stop if we're compiling junk
8893     if(itype[i]==NI&&opcode[i]==0x11) {
8894       done=stop_after_jal=1;
8895       SysPrintf("Disabled speculative precompilation\n");
8896     }
8897   }
8898   slen=i;
8899   if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8900     if(start+i*4==pagelimit) {
8901       itype[i-1]=SPAN;
8902     }
8903   }
8904   assert(slen>0);
8905
8906   /* Pass 2 - Register dependencies and branch targets */
8907
8908   unneeded_registers(0,slen-1,0);
8909
8910   /* Pass 3 - Register allocation */
8911
8912   struct regstat current; // Current register allocations/status
8913   current.is32=1;
8914   current.dirty=0;
8915   current.u=unneeded_reg[0];
8916   current.uu=unneeded_reg_upper[0];
8917   clear_all_regs(current.regmap);
8918   alloc_reg(&current,0,CCREG);
8919   dirty_reg(&current,CCREG);
8920   current.isconst=0;
8921   current.wasconst=0;
8922   current.waswritten=0;
8923   int ds=0;
8924   int cc=0;
8925   int hr=-1;
8926
8927 #ifndef FORCE32
8928   provisional_32bit();
8929 #endif
8930   if((u_int)addr&1) {
8931     // First instruction is delay slot
8932     cc=-1;
8933     bt[1]=1;
8934     ds=1;
8935     unneeded_reg[0]=1;
8936     unneeded_reg_upper[0]=1;
8937     current.regmap[HOST_BTREG]=BTREG;
8938   }
8939
8940   for(i=0;i<slen;i++)
8941   {
8942     if(bt[i])
8943     {
8944       int hr;
8945       for(hr=0;hr<HOST_REGS;hr++)
8946       {
8947         // Is this really necessary?
8948         if(current.regmap[hr]==0) current.regmap[hr]=-1;
8949       }
8950       current.isconst=0;
8951       current.waswritten=0;
8952     }
8953     if(i>1)
8954     {
8955       if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8956       {
8957         if(rs1[i-2]==0||rs2[i-2]==0)
8958         {
8959           if(rs1[i-2]) {
8960             current.is32|=1LL<<rs1[i-2];
8961             int hr=get_reg(current.regmap,rs1[i-2]|64);
8962             if(hr>=0) current.regmap[hr]=-1;
8963           }
8964           if(rs2[i-2]) {
8965             current.is32|=1LL<<rs2[i-2];
8966             int hr=get_reg(current.regmap,rs2[i-2]|64);
8967             if(hr>=0) current.regmap[hr]=-1;
8968           }
8969         }
8970       }
8971     }
8972 #ifndef FORCE32
8973     // If something jumps here with 64-bit values
8974     // then promote those registers to 64 bits
8975     if(bt[i])
8976     {
8977       uint64_t temp_is32=current.is32;
8978       for(j=i-1;j>=0;j--)
8979       {
8980         if(ba[j]==start+i*4)
8981           temp_is32&=branch_regs[j].is32;
8982       }
8983       for(j=i;j<slen;j++)
8984       {
8985         if(ba[j]==start+i*4)
8986           //temp_is32=1;
8987           temp_is32&=p32[j];
8988       }
8989       if(temp_is32!=current.is32) {
8990         //printf("dumping 32-bit regs (%x)\n",start+i*4);
8991         #ifndef DESTRUCTIVE_WRITEBACK
8992         if(ds)
8993         #endif
8994         for(hr=0;hr<HOST_REGS;hr++)
8995         {
8996           int r=current.regmap[hr];
8997           if(r>0&&r<64)
8998           {
8999             if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
9000               temp_is32|=1LL<<r;
9001               //printf("restore %d\n",r);
9002             }
9003           }
9004         }
9005         current.is32=temp_is32;
9006       }
9007     }
9008 #else
9009     current.is32=-1LL;
9010 #endif
9011
9012     memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
9013     regs[i].wasconst=current.isconst;
9014     regs[i].was32=current.is32;
9015     regs[i].wasdirty=current.dirty;
9016     regs[i].loadedconst=0;
9017     #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
9018     // To change a dirty register from 32 to 64 bits, we must write
9019     // it out during the previous cycle (for branches, 2 cycles)
9020     if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
9021     {
9022       uint64_t temp_is32=current.is32;
9023       for(j=i-1;j>=0;j--)
9024       {
9025         if(ba[j]==start+i*4+4)
9026           temp_is32&=branch_regs[j].is32;
9027       }
9028       for(j=i;j<slen;j++)
9029       {
9030         if(ba[j]==start+i*4+4)
9031           //temp_is32=1;
9032           temp_is32&=p32[j];
9033       }
9034       if(temp_is32!=current.is32) {
9035         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9036         for(hr=0;hr<HOST_REGS;hr++)
9037         {
9038           int r=current.regmap[hr];
9039           if(r>0)
9040           {
9041             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9042               if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
9043               {
9044                 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
9045                 {
9046                   //printf("dump %d/r%d\n",hr,r);
9047                   current.regmap[hr]=-1;
9048                   if(get_reg(current.regmap,r|64)>=0)
9049                     current.regmap[get_reg(current.regmap,r|64)]=-1;
9050                 }
9051               }
9052             }
9053           }
9054         }
9055       }
9056     }
9057     else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
9058     {
9059       uint64_t temp_is32=current.is32;
9060       for(j=i-1;j>=0;j--)
9061       {
9062         if(ba[j]==start+i*4+8)
9063           temp_is32&=branch_regs[j].is32;
9064       }
9065       for(j=i;j<slen;j++)
9066       {
9067         if(ba[j]==start+i*4+8)
9068           //temp_is32=1;
9069           temp_is32&=p32[j];
9070       }
9071       if(temp_is32!=current.is32) {
9072         //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9073         for(hr=0;hr<HOST_REGS;hr++)
9074         {
9075           int r=current.regmap[hr];
9076           if(r>0)
9077           {
9078             if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9079               if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
9080               {
9081                 //printf("dump %d/r%d\n",hr,r);
9082                 current.regmap[hr]=-1;
9083                 if(get_reg(current.regmap,r|64)>=0)
9084                   current.regmap[get_reg(current.regmap,r|64)]=-1;
9085               }
9086             }
9087           }
9088         }
9089       }
9090     }
9091     #endif
9092     if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9093       if(i+1<slen) {
9094         current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9095         current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9096         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9097         current.u|=1;
9098         current.uu|=1;
9099       } else {
9100         current.u=1;
9101         current.uu=1;
9102       }
9103     } else {
9104       if(i+1<slen) {
9105         current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9106         current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9107         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9108         current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9109         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9110         current.u|=1;
9111         current.uu|=1;
9112       } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
9113     }
9114     is_ds[i]=ds;
9115     if(ds) {
9116       ds=0; // Skip delay slot, already allocated as part of branch
9117       // ...but we need to alloc it in case something jumps here
9118       if(i+1<slen) {
9119         current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9120         current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9121       }else{
9122         current.u=branch_unneeded_reg[i-1];
9123         current.uu=branch_unneeded_reg_upper[i-1];
9124       }
9125       current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9126       current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9127       if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9128       current.u|=1;
9129       current.uu|=1;
9130       struct regstat temp;
9131       memcpy(&temp,&current,sizeof(current));
9132       temp.wasdirty=temp.dirty;
9133       temp.was32=temp.is32;
9134       // TODO: Take into account unconditional branches, as below
9135       delayslot_alloc(&temp,i);
9136       memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9137       regs[i].wasdirty=temp.wasdirty;
9138       regs[i].was32=temp.was32;
9139       regs[i].dirty=temp.dirty;
9140       regs[i].is32=temp.is32;
9141       regs[i].isconst=0;
9142       regs[i].wasconst=0;
9143       current.isconst=0;
9144       // Create entry (branch target) regmap
9145       for(hr=0;hr<HOST_REGS;hr++)
9146       {
9147         int r=temp.regmap[hr];
9148         if(r>=0) {
9149           if(r!=regmap_pre[i][hr]) {
9150             regs[i].regmap_entry[hr]=-1;
9151           }
9152           else
9153           {
9154             if(r<64){
9155               if((current.u>>r)&1) {
9156                 regs[i].regmap_entry[hr]=-1;
9157                 regs[i].regmap[hr]=-1;
9158                 //Don't clear regs in the delay slot as the branch might need them
9159                 //current.regmap[hr]=-1;
9160               }else
9161                 regs[i].regmap_entry[hr]=r;
9162             }
9163             else {
9164               if((current.uu>>(r&63))&1) {
9165                 regs[i].regmap_entry[hr]=-1;
9166                 regs[i].regmap[hr]=-1;
9167                 //Don't clear regs in the delay slot as the branch might need them
9168                 //current.regmap[hr]=-1;
9169               }else
9170                 regs[i].regmap_entry[hr]=r;
9171             }
9172           }
9173         } else {
9174           // First instruction expects CCREG to be allocated
9175           if(i==0&&hr==HOST_CCREG)
9176             regs[i].regmap_entry[hr]=CCREG;
9177           else
9178             regs[i].regmap_entry[hr]=-1;
9179         }
9180       }
9181     }
9182     else { // Not delay slot
9183       switch(itype[i]) {
9184         case UJUMP:
9185           //current.isconst=0; // DEBUG
9186           //current.wasconst=0; // DEBUG
9187           //regs[i].wasconst=0; // DEBUG
9188           clear_const(&current,rt1[i]);
9189           alloc_cc(&current,i);
9190           dirty_reg(&current,CCREG);
9191           if (rt1[i]==31) {
9192             alloc_reg(&current,i,31);
9193             dirty_reg(&current,31);
9194             //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9195             //assert(rt1[i+1]!=rt1[i]);
9196             #ifdef REG_PREFETCH
9197             alloc_reg(&current,i,PTEMP);
9198             #endif
9199             //current.is32|=1LL<<rt1[i];
9200           }
9201           ooo[i]=1;
9202           delayslot_alloc(&current,i+1);
9203           //current.isconst=0; // DEBUG
9204           ds=1;
9205           //printf("i=%d, isconst=%x\n",i,current.isconst);
9206           break;
9207         case RJUMP:
9208           //current.isconst=0;
9209           //current.wasconst=0;
9210           //regs[i].wasconst=0;
9211           clear_const(&current,rs1[i]);
9212           clear_const(&current,rt1[i]);
9213           alloc_cc(&current,i);
9214           dirty_reg(&current,CCREG);
9215           if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9216             alloc_reg(&current,i,rs1[i]);
9217             if (rt1[i]!=0) {
9218               alloc_reg(&current,i,rt1[i]);
9219               dirty_reg(&current,rt1[i]);
9220               assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9221               assert(rt1[i+1]!=rt1[i]);
9222               #ifdef REG_PREFETCH
9223               alloc_reg(&current,i,PTEMP);
9224               #endif
9225             }
9226             #ifdef USE_MINI_HT
9227             if(rs1[i]==31) { // JALR
9228               alloc_reg(&current,i,RHASH);
9229               #ifndef HOST_IMM_ADDR32
9230               alloc_reg(&current,i,RHTBL);
9231               #endif
9232             }
9233             #endif
9234             delayslot_alloc(&current,i+1);
9235           } else {
9236             // The delay slot overwrites our source register,
9237             // allocate a temporary register to hold the old value.
9238             current.isconst=0;
9239             current.wasconst=0;
9240             regs[i].wasconst=0;
9241             delayslot_alloc(&current,i+1);
9242             current.isconst=0;
9243             alloc_reg(&current,i,RTEMP);
9244           }
9245           //current.isconst=0; // DEBUG
9246           ooo[i]=1;
9247           ds=1;
9248           break;
9249         case CJUMP:
9250           //current.isconst=0;
9251           //current.wasconst=0;
9252           //regs[i].wasconst=0;
9253           clear_const(&current,rs1[i]);
9254           clear_const(&current,rs2[i]);
9255           if((opcode[i]&0x3E)==4) // BEQ/BNE
9256           {
9257             alloc_cc(&current,i);
9258             dirty_reg(&current,CCREG);
9259             if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9260             if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9261             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9262             {
9263               if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9264               if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9265             }
9266             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9267                (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9268               // The delay slot overwrites one of our conditions.
9269               // Allocate the branch condition registers instead.
9270               current.isconst=0;
9271               current.wasconst=0;
9272               regs[i].wasconst=0;
9273               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9274               if(rs2[i]) alloc_reg(&current,i,rs2[i]);
9275               if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9276               {
9277                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9278                 if(rs2[i]) alloc_reg64(&current,i,rs2[i]);
9279               }
9280             }
9281             else
9282             {
9283               ooo[i]=1;
9284               delayslot_alloc(&current,i+1);
9285             }
9286           }
9287           else
9288           if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9289           {
9290             alloc_cc(&current,i);
9291             dirty_reg(&current,CCREG);
9292             alloc_reg(&current,i,rs1[i]);
9293             if(!(current.is32>>rs1[i]&1))
9294             {
9295               alloc_reg64(&current,i,rs1[i]);
9296             }
9297             if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9298               // The delay slot overwrites one of our conditions.
9299               // Allocate the branch condition registers instead.
9300               current.isconst=0;
9301               current.wasconst=0;
9302               regs[i].wasconst=0;
9303               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9304               if(!((current.is32>>rs1[i])&1))
9305               {
9306                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9307               }
9308             }
9309             else
9310             {
9311               ooo[i]=1;
9312               delayslot_alloc(&current,i+1);
9313             }
9314           }
9315           else
9316           // Don't alloc the delay slot yet because we might not execute it
9317           if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9318           {
9319             current.isconst=0;
9320             current.wasconst=0;
9321             regs[i].wasconst=0;
9322             alloc_cc(&current,i);
9323             dirty_reg(&current,CCREG);
9324             alloc_reg(&current,i,rs1[i]);
9325             alloc_reg(&current,i,rs2[i]);
9326             if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9327             {
9328               alloc_reg64(&current,i,rs1[i]);
9329               alloc_reg64(&current,i,rs2[i]);
9330             }
9331           }
9332           else
9333           if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9334           {
9335             current.isconst=0;
9336             current.wasconst=0;
9337             regs[i].wasconst=0;
9338             alloc_cc(&current,i);
9339             dirty_reg(&current,CCREG);
9340             alloc_reg(&current,i,rs1[i]);
9341             if(!(current.is32>>rs1[i]&1))
9342             {
9343               alloc_reg64(&current,i,rs1[i]);
9344             }
9345           }
9346           ds=1;
9347           //current.isconst=0;
9348           break;
9349         case SJUMP:
9350           //current.isconst=0;
9351           //current.wasconst=0;
9352           //regs[i].wasconst=0;
9353           clear_const(&current,rs1[i]);
9354           clear_const(&current,rt1[i]);
9355           //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9356           if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9357           {
9358             alloc_cc(&current,i);
9359             dirty_reg(&current,CCREG);
9360             alloc_reg(&current,i,rs1[i]);
9361             if(!(current.is32>>rs1[i]&1))
9362             {
9363               alloc_reg64(&current,i,rs1[i]);
9364             }
9365             if (rt1[i]==31) { // BLTZAL/BGEZAL
9366               alloc_reg(&current,i,31);
9367               dirty_reg(&current,31);
9368               //#ifdef REG_PREFETCH
9369               //alloc_reg(&current,i,PTEMP);
9370               //#endif
9371               //current.is32|=1LL<<rt1[i];
9372             }
9373             if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9374                ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9375               // Allocate the branch condition registers instead.
9376               current.isconst=0;
9377               current.wasconst=0;
9378               regs[i].wasconst=0;
9379               if(rs1[i]) alloc_reg(&current,i,rs1[i]);
9380               if(!((current.is32>>rs1[i])&1))
9381               {
9382                 if(rs1[i]) alloc_reg64(&current,i,rs1[i]);
9383               }
9384             }
9385             else
9386             {
9387               ooo[i]=1;
9388               delayslot_alloc(&current,i+1);
9389             }
9390           }
9391           else
9392           // Don't alloc the delay slot yet because we might not execute it
9393           if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9394           {
9395             current.isconst=0;
9396             current.wasconst=0;
9397             regs[i].wasconst=0;
9398             alloc_cc(&current,i);
9399             dirty_reg(&current,CCREG);
9400             alloc_reg(&current,i,rs1[i]);
9401             if(!(current.is32>>rs1[i]&1))
9402             {
9403               alloc_reg64(&current,i,rs1[i]);
9404             }
9405           }
9406           ds=1;
9407           //current.isconst=0;
9408           break;
9409         case FJUMP:
9410           current.isconst=0;
9411           current.wasconst=0;
9412           regs[i].wasconst=0;
9413           if(likely[i]==0) // BC1F/BC1T
9414           {
9415             // TODO: Theoretically we can run out of registers here on x86.
9416             // The delay slot can allocate up to six, and we need to check
9417             // CSREG before executing the delay slot.  Possibly we can drop
9418             // the cycle count and then reload it after checking that the
9419             // FPU is in a usable state, or don't do out-of-order execution.
9420             alloc_cc(&current,i);
9421             dirty_reg(&current,CCREG);
9422             alloc_reg(&current,i,FSREG);
9423             alloc_reg(&current,i,CSREG);
9424             if(itype[i+1]==FCOMP) {
9425               // The delay slot overwrites the branch condition.
9426               // Allocate the branch condition registers instead.
9427               alloc_cc(&current,i);
9428               dirty_reg(&current,CCREG);
9429               alloc_reg(&current,i,CSREG);
9430               alloc_reg(&current,i,FSREG);
9431             }
9432             else {
9433               ooo[i]=1;
9434               delayslot_alloc(&current,i+1);
9435               alloc_reg(&current,i+1,CSREG);
9436             }
9437           }
9438           else
9439           // Don't alloc the delay slot yet because we might not execute it
9440           if(likely[i]) // BC1FL/BC1TL
9441           {
9442             alloc_cc(&current,i);
9443             dirty_reg(&current,CCREG);
9444             alloc_reg(&current,i,CSREG);
9445             alloc_reg(&current,i,FSREG);
9446           }
9447           ds=1;
9448           current.isconst=0;
9449           break;
9450         case IMM16:
9451           imm16_alloc(&current,i);
9452           break;
9453         case LOAD:
9454         case LOADLR:
9455           load_alloc(&current,i);
9456           break;
9457         case STORE:
9458         case STORELR:
9459           store_alloc(&current,i);
9460           break;
9461         case ALU:
9462           alu_alloc(&current,i);
9463           break;
9464         case SHIFT:
9465           shift_alloc(&current,i);
9466           break;
9467         case MULTDIV:
9468           multdiv_alloc(&current,i);
9469           break;
9470         case SHIFTIMM:
9471           shiftimm_alloc(&current,i);
9472           break;
9473         case MOV:
9474           mov_alloc(&current,i);
9475           break;
9476         case COP0:
9477           cop0_alloc(&current,i);
9478           break;
9479         case COP1:
9480         case COP2:
9481           cop1_alloc(&current,i);
9482           break;
9483         case C1LS:
9484           c1ls_alloc(&current,i);
9485           break;
9486         case C2LS:
9487           c2ls_alloc(&current,i);
9488           break;
9489         case C2OP:
9490           c2op_alloc(&current,i);
9491           break;
9492         case FCONV:
9493           fconv_alloc(&current,i);
9494           break;
9495         case FLOAT:
9496           float_alloc(&current,i);
9497           break;
9498         case FCOMP:
9499           fcomp_alloc(&current,i);
9500           break;
9501         case SYSCALL:
9502         case HLECALL:
9503         case INTCALL:
9504           syscall_alloc(&current,i);
9505           break;
9506         case SPAN:
9507           pagespan_alloc(&current,i);
9508           break;
9509       }
9510
9511       // Drop the upper half of registers that have become 32-bit
9512       current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9513       if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9514         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9515         if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9516         current.uu|=1;
9517       } else {
9518         current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9519         current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9520         if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9521         current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9522         current.uu|=1;
9523       }
9524
9525       // Create entry (branch target) regmap
9526       for(hr=0;hr<HOST_REGS;hr++)
9527       {
9528         int r,or,er;
9529         r=current.regmap[hr];
9530         if(r>=0) {
9531           if(r!=regmap_pre[i][hr]) {
9532             // TODO: delay slot (?)
9533             or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9534             if(or<0||(r&63)>=TEMPREG){
9535               regs[i].regmap_entry[hr]=-1;
9536             }
9537             else
9538             {
9539               // Just move it to a different register
9540               regs[i].regmap_entry[hr]=r;
9541               // If it was dirty before, it's still dirty
9542               if((regs[i].wasdirty>>or)&1) dirty_reg(&current,r&63);
9543             }
9544           }
9545           else
9546           {
9547             // Unneeded
9548             if(r==0){
9549               regs[i].regmap_entry[hr]=0;
9550             }
9551             else
9552             if(r<64){
9553               if((current.u>>r)&1) {
9554                 regs[i].regmap_entry[hr]=-1;
9555                 //regs[i].regmap[hr]=-1;
9556                 current.regmap[hr]=-1;
9557               }else
9558                 regs[i].regmap_entry[hr]=r;
9559             }
9560             else {
9561               if((current.uu>>(r&63))&1) {
9562                 regs[i].regmap_entry[hr]=-1;
9563                 //regs[i].regmap[hr]=-1;
9564                 current.regmap[hr]=-1;
9565               }else
9566                 regs[i].regmap_entry[hr]=r;
9567             }
9568           }
9569         } else {
9570           // Branches expect CCREG to be allocated at the target
9571           if(regmap_pre[i][hr]==CCREG)
9572             regs[i].regmap_entry[hr]=CCREG;
9573           else
9574             regs[i].regmap_entry[hr]=-1;
9575         }
9576       }
9577       memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9578     }
9579
9580     if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9581       current.waswritten|=1<<rs1[i-1];
9582     current.waswritten&=~(1<<rt1[i]);
9583     current.waswritten&=~(1<<rt2[i]);
9584     if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9585       current.waswritten&=~(1<<rs1[i]);
9586
9587     /* Branch post-alloc */
9588     if(i>0)
9589     {
9590       current.was32=current.is32;
9591       current.wasdirty=current.dirty;
9592       switch(itype[i-1]) {
9593         case UJUMP:
9594           memcpy(&branch_regs[i-1],&current,sizeof(current));
9595           branch_regs[i-1].isconst=0;
9596           branch_regs[i-1].wasconst=0;
9597           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9598           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9599           alloc_cc(&branch_regs[i-1],i-1);
9600           dirty_reg(&branch_regs[i-1],CCREG);
9601           if(rt1[i-1]==31) { // JAL
9602             alloc_reg(&branch_regs[i-1],i-1,31);
9603             dirty_reg(&branch_regs[i-1],31);
9604             branch_regs[i-1].is32|=1LL<<31;
9605           }
9606           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9607           memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9608           break;
9609         case RJUMP:
9610           memcpy(&branch_regs[i-1],&current,sizeof(current));
9611           branch_regs[i-1].isconst=0;
9612           branch_regs[i-1].wasconst=0;
9613           branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9614           branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9615           alloc_cc(&branch_regs[i-1],i-1);
9616           dirty_reg(&branch_regs[i-1],CCREG);
9617           alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9618           if(rt1[i-1]!=0) { // JALR
9619             alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9620             dirty_reg(&branch_regs[i-1],rt1[i-1]);
9621             branch_regs[i-1].is32|=1LL<<rt1[i-1];
9622           }
9623           #ifdef USE_MINI_HT
9624           if(rs1[i-1]==31) { // JALR
9625             alloc_reg(&branch_regs[i-1],i-1,RHASH);
9626             #ifndef HOST_IMM_ADDR32
9627             alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9628             #endif
9629           }
9630           #endif
9631           memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9632           memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9633           break;
9634         case CJUMP:
9635           if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9636           {
9637             alloc_cc(&current,i-1);
9638             dirty_reg(&current,CCREG);
9639             if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9640                (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9641               // The delay slot overwrote one of our conditions
9642               // Delay slot goes after the test (in order)
9643               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9644               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9645               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9646               current.u|=1;
9647               current.uu|=1;
9648               delayslot_alloc(&current,i);
9649               current.isconst=0;
9650             }
9651             else
9652             {
9653               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9654               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9655               // Alloc the branch condition registers
9656               if(rs1[i-1]) alloc_reg(&current,i-1,rs1[i-1]);
9657               if(rs2[i-1]) alloc_reg(&current,i-1,rs2[i-1]);
9658               if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9659               {
9660                 if(rs1[i-1]) alloc_reg64(&current,i-1,rs1[i-1]);
9661                 if(rs2[i-1]) alloc_reg64(&current,i-1,rs2[i-1]);
9662               }
9663             }
9664             memcpy(&branch_regs[i-1],&current,sizeof(current));
9665             branch_regs[i-1].isconst=0;
9666             branch_regs[i-1].wasconst=0;
9667             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9668             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9669           }
9670           else
9671           if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9672           {
9673             alloc_cc(&current,i-1);
9674             dirty_reg(&current,CCREG);
9675             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9676               // The delay slot overwrote the branch condition
9677               // Delay slot goes after the test (in order)
9678               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9679               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9680               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9681               current.u|=1;
9682               current.uu|=1;
9683               delayslot_alloc(&current,i);
9684               current.isconst=0;
9685             }
9686             else
9687             {
9688               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9689               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9690               // Alloc the branch condition register
9691               alloc_reg(&current,i-1,rs1[i-1]);
9692               if(!(current.is32>>rs1[i-1]&1))
9693               {
9694                 alloc_reg64(&current,i-1,rs1[i-1]);
9695               }
9696             }
9697             memcpy(&branch_regs[i-1],&current,sizeof(current));
9698             branch_regs[i-1].isconst=0;
9699             branch_regs[i-1].wasconst=0;
9700             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9701             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9702           }
9703           else
9704           // Alloc the delay slot in case the branch is taken
9705           if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9706           {
9707             memcpy(&branch_regs[i-1],&current,sizeof(current));
9708             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9709             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9710             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9711             alloc_cc(&branch_regs[i-1],i);
9712             dirty_reg(&branch_regs[i-1],CCREG);
9713             delayslot_alloc(&branch_regs[i-1],i);
9714             branch_regs[i-1].isconst=0;
9715             alloc_reg(&current,i,CCREG); // Not taken path
9716             dirty_reg(&current,CCREG);
9717             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9718           }
9719           else
9720           if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9721           {
9722             memcpy(&branch_regs[i-1],&current,sizeof(current));
9723             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9724             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9725             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9726             alloc_cc(&branch_regs[i-1],i);
9727             dirty_reg(&branch_regs[i-1],CCREG);
9728             delayslot_alloc(&branch_regs[i-1],i);
9729             branch_regs[i-1].isconst=0;
9730             alloc_reg(&current,i,CCREG); // Not taken path
9731             dirty_reg(&current,CCREG);
9732             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9733           }
9734           break;
9735         case SJUMP:
9736           //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9737           if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9738           {
9739             alloc_cc(&current,i-1);
9740             dirty_reg(&current,CCREG);
9741             if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9742               // The delay slot overwrote the branch condition
9743               // Delay slot goes after the test (in order)
9744               current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9745               current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9746               if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9747               current.u|=1;
9748               current.uu|=1;
9749               delayslot_alloc(&current,i);
9750               current.isconst=0;
9751             }
9752             else
9753             {
9754               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9755               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9756               // Alloc the branch condition register
9757               alloc_reg(&current,i-1,rs1[i-1]);
9758               if(!(current.is32>>rs1[i-1]&1))
9759               {
9760                 alloc_reg64(&current,i-1,rs1[i-1]);
9761               }
9762             }
9763             memcpy(&branch_regs[i-1],&current,sizeof(current));
9764             branch_regs[i-1].isconst=0;
9765             branch_regs[i-1].wasconst=0;
9766             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9767             memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9768           }
9769           else
9770           // Alloc the delay slot in case the branch is taken
9771           if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9772           {
9773             memcpy(&branch_regs[i-1],&current,sizeof(current));
9774             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9775             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9776             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9777             alloc_cc(&branch_regs[i-1],i);
9778             dirty_reg(&branch_regs[i-1],CCREG);
9779             delayslot_alloc(&branch_regs[i-1],i);
9780             branch_regs[i-1].isconst=0;
9781             alloc_reg(&current,i,CCREG); // Not taken path
9782             dirty_reg(&current,CCREG);
9783             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9784           }
9785           // FIXME: BLTZAL/BGEZAL
9786           if(opcode2[i-1]&0x10) { // BxxZAL
9787             alloc_reg(&branch_regs[i-1],i-1,31);
9788             dirty_reg(&branch_regs[i-1],31);
9789             branch_regs[i-1].is32|=1LL<<31;
9790           }
9791           break;
9792         case FJUMP:
9793           if(likely[i-1]==0) // BC1F/BC1T
9794           {
9795             alloc_cc(&current,i-1);
9796             dirty_reg(&current,CCREG);
9797             if(itype[i]==FCOMP) {
9798               // The delay slot overwrote the branch condition
9799               // Delay slot goes after the test (in order)
9800               delayslot_alloc(&current,i);
9801               current.isconst=0;
9802             }
9803             else
9804             {
9805               current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9806               current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9807               // Alloc the branch condition register
9808               alloc_reg(&current,i-1,FSREG);
9809             }
9810             memcpy(&branch_regs[i-1],&current,sizeof(current));
9811             memcpy(&branch_regs[i-1].regmap_entry,&current.regmap,sizeof(current.regmap));
9812           }
9813           else // BC1FL/BC1TL
9814           {
9815             // Alloc the delay slot in case the branch is taken
9816             memcpy(&branch_regs[i-1],&current,sizeof(current));
9817             branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9818             branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9819             if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9820             alloc_cc(&branch_regs[i-1],i);
9821             dirty_reg(&branch_regs[i-1],CCREG);
9822             delayslot_alloc(&branch_regs[i-1],i);
9823             branch_regs[i-1].isconst=0;
9824             alloc_reg(&current,i,CCREG); // Not taken path
9825             dirty_reg(&current,CCREG);
9826             memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9827           }
9828           break;
9829       }
9830
9831       if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9832       {
9833         if(rt1[i-1]==31) // JAL/JALR
9834         {
9835           // Subroutine call will return here, don't alloc any registers
9836           current.is32=1;
9837           current.dirty=0;
9838           clear_all_regs(current.regmap);
9839           alloc_reg(&current,i,CCREG);
9840           dirty_reg(&current,CCREG);
9841         }
9842         else if(i+1<slen)
9843         {
9844           // Internal branch will jump here, match registers to caller
9845           current.is32=0x3FFFFFFFFLL;
9846           current.dirty=0;
9847           clear_all_regs(current.regmap);
9848           alloc_reg(&current,i,CCREG);
9849           dirty_reg(&current,CCREG);
9850           for(j=i-1;j>=0;j--)
9851           {
9852             if(ba[j]==start+i*4+4) {
9853               memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9854               current.is32=branch_regs[j].is32;
9855               current.dirty=branch_regs[j].dirty;
9856               break;
9857             }
9858           }
9859           while(j>=0) {
9860             if(ba[j]==start+i*4+4) {
9861               for(hr=0;hr<HOST_REGS;hr++) {
9862                 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9863                   current.regmap[hr]=-1;
9864                 }
9865                 current.is32&=branch_regs[j].is32;
9866                 current.dirty&=branch_regs[j].dirty;
9867               }
9868             }
9869             j--;
9870           }
9871         }
9872       }
9873     }
9874
9875     // Count cycles in between branches
9876     ccadj[i]=cc;
9877     if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9878     {
9879       cc=0;
9880     }
9881 #if defined(PCSX) && !defined(DRC_DBG)
9882     else if(itype[i]==C2OP&&gte_cycletab[source[i]&0x3f]>2)
9883     {
9884       // GTE runs in parallel until accessed, divide by 2 for a rough guess
9885       cc+=gte_cycletab[source[i]&0x3f]/2;
9886     }
9887     else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
9888     {
9889       cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9890     }
9891     else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i])
9892     {
9893       cc+=4;
9894     }
9895     else if(itype[i]==C2LS)
9896     {
9897       cc+=4;
9898     }
9899 #endif
9900     else
9901     {
9902       cc++;
9903     }
9904
9905     flush_dirty_uppers(&current);
9906     if(!is_ds[i]) {
9907       regs[i].is32=current.is32;
9908       regs[i].dirty=current.dirty;
9909       regs[i].isconst=current.isconst;
9910       memcpy(constmap[i],current_constmap,sizeof(current_constmap));
9911     }
9912     for(hr=0;hr<HOST_REGS;hr++) {
9913       if(hr!=EXCLUDE_REG&&regs[i].regmap[hr]>=0) {
9914         if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9915           regs[i].wasconst&=~(1<<hr);
9916         }
9917       }
9918     }
9919     if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9920     regs[i].waswritten=current.waswritten;
9921   }
9922
9923   /* Pass 4 - Cull unused host registers */
9924
9925   uint64_t nr=0;
9926
9927   for (i=slen-1;i>=0;i--)
9928   {
9929     int hr;
9930     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9931     {
9932       if(ba[i]<start || ba[i]>=(start+slen*4))
9933       {
9934         // Branch out of this block, don't need anything
9935         nr=0;
9936       }
9937       else
9938       {
9939         // Internal branch
9940         // Need whatever matches the target
9941         nr=0;
9942         int t=(ba[i]-start)>>2;
9943         for(hr=0;hr<HOST_REGS;hr++)
9944         {
9945           if(regs[i].regmap_entry[hr]>=0) {
9946             if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9947           }
9948         }
9949       }
9950       // Conditional branch may need registers for following instructions
9951       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9952       {
9953         if(i<slen-2) {
9954           nr|=needed_reg[i+2];
9955           for(hr=0;hr<HOST_REGS;hr++)
9956           {
9957             if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9958             //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9959           }
9960         }
9961       }
9962       // Don't need stuff which is overwritten
9963       //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9964       //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9965       // Merge in delay slot
9966       for(hr=0;hr<HOST_REGS;hr++)
9967       {
9968         if(!likely[i]) {
9969           // These are overwritten unless the branch is "likely"
9970           // and the delay slot is nullified if not taken
9971           if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9972           if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9973         }
9974         if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9975         if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9976         if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9977         if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9978         if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9979         if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9980         if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9981         if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9982         if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9983           if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9984           if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9985         }
9986         if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9987           if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9988           if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9989         }
9990         if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9991           if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9992           if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9993         }
9994       }
9995     }
9996     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9997     {
9998       // SYSCALL instruction (software interrupt)
9999       nr=0;
10000     }
10001     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10002     {
10003       // ERET instruction (return from interrupt)
10004       nr=0;
10005     }
10006     else // Non-branch
10007     {
10008       if(i<slen-1) {
10009         for(hr=0;hr<HOST_REGS;hr++) {
10010           if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
10011           if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
10012           if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
10013           if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
10014         }
10015       }
10016     }
10017     for(hr=0;hr<HOST_REGS;hr++)
10018     {
10019       // Overwritten registers are not needed
10020       if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10021       if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10022       if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10023       // Source registers are needed
10024       if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10025       if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10026       if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
10027       if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
10028       if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10029       if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10030       if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10031       if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10032       if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
10033         if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10034         if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10035       }
10036       if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
10037         if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10038         if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10039       }
10040       if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
10041         if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
10042         if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
10043       }
10044       // Don't store a register immediately after writing it,
10045       // may prevent dual-issue.
10046       // But do so if this is a branch target, otherwise we
10047       // might have to load the register before the branch.
10048       if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
10049         if((regmap_pre[i][hr]>0&&regmap_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
10050            (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
10051           if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10052           if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10053         }
10054         if((regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
10055            (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
10056           if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10057           if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10058         }
10059       }
10060     }
10061     // Cycle count is needed at branches.  Assume it is needed at the target too.
10062     if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
10063       if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10064       if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10065     }
10066     // Save it
10067     needed_reg[i]=nr;
10068
10069     // Deallocate unneeded registers
10070     for(hr=0;hr<HOST_REGS;hr++)
10071     {
10072       if(!((nr>>hr)&1)) {
10073         if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
10074         if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10075            (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10076            (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
10077         {
10078           if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10079           {
10080             if(likely[i]) {
10081               regs[i].regmap[hr]=-1;
10082               regs[i].isconst&=~(1<<hr);
10083               if(i<slen-2) {
10084                 regmap_pre[i+2][hr]=-1;
10085                 regs[i+2].wasconst&=~(1<<hr);
10086               }
10087             }
10088           }
10089         }
10090         if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10091         {
10092           int d1=0,d2=0,map=0,temp=0;
10093           if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10094           {
10095             d1=dep1[i+1];
10096             d2=dep2[i+1];
10097           }
10098           if(using_tlb) {
10099             if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10100                itype[i+1]==STORE || itype[i+1]==STORELR ||
10101                itype[i+1]==C1LS || itype[i+1]==C2LS)
10102             map=TLREG;
10103           } else
10104           if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10105              (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10106             map=INVCP;
10107           }
10108           if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10109              itype[i+1]==C1LS || itype[i+1]==C2LS)
10110             temp=FTEMP;
10111           if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10112              (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10113              (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10114              (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10115              (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10116              regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10117              (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10118              regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10119              regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10120              regs[i].regmap[hr]!=map )
10121           {
10122             regs[i].regmap[hr]=-1;
10123             regs[i].isconst&=~(1<<hr);
10124             if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10125                (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10126                (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10127                (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10128                (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10129                branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10130                (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10131                branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10132                branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10133                branch_regs[i].regmap[hr]!=map)
10134             {
10135               branch_regs[i].regmap[hr]=-1;
10136               branch_regs[i].regmap_entry[hr]=-1;
10137               if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10138               {
10139                 if(!likely[i]&&i<slen-2) {
10140                   regmap_pre[i+2][hr]=-1;
10141                   regs[i+2].wasconst&=~(1<<hr);
10142                 }
10143               }
10144             }
10145           }
10146         }
10147         else
10148         {
10149           // Non-branch
10150           if(i>0)
10151           {
10152             int d1=0,d2=0,map=-1,temp=-1;
10153             if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10154             {
10155               d1=dep1[i];
10156               d2=dep2[i];
10157             }
10158             if(using_tlb) {
10159               if(itype[i]==LOAD || itype[i]==LOADLR ||
10160                  itype[i]==STORE || itype[i]==STORELR ||
10161                  itype[i]==C1LS || itype[i]==C2LS)
10162               map=TLREG;
10163             } else if(itype[i]==STORE || itype[i]==STORELR ||
10164                       (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10165               map=INVCP;
10166             }
10167             if(itype[i]==LOADLR || itype[i]==STORELR ||
10168                itype[i]==C1LS || itype[i]==C2LS)
10169               temp=FTEMP;
10170             if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10171                (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10172                (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10173                regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10174                (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10175                (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10176             {
10177               if(i<slen-1&&!is_ds[i]) {
10178                 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10179                 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10180                 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10181                 {
10182                   SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10183                   assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10184                 }
10185                 regmap_pre[i+1][hr]=-1;
10186                 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10187                 regs[i+1].wasconst&=~(1<<hr);
10188               }
10189               regs[i].regmap[hr]=-1;
10190               regs[i].isconst&=~(1<<hr);
10191             }
10192           }
10193         }
10194       }
10195     }
10196   }
10197
10198   /* Pass 5 - Pre-allocate registers */
10199
10200   // If a register is allocated during a loop, try to allocate it for the
10201   // entire loop, if possible.  This avoids loading/storing registers
10202   // inside of the loop.
10203
10204   signed char f_regmap[HOST_REGS];
10205   clear_all_regs(f_regmap);
10206   for(i=0;i<slen-1;i++)
10207   {
10208     if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10209     {
10210       if(ba[i]>=start && ba[i]<(start+i*4))
10211       if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10212       ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10213       ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10214       ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10215       ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10216       ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10217       {
10218         int t=(ba[i]-start)>>2;
10219         if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10220         if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10221         for(hr=0;hr<HOST_REGS;hr++)
10222         {
10223           if(regs[i].regmap[hr]>64) {
10224             if(!((regs[i].dirty>>hr)&1))
10225               f_regmap[hr]=regs[i].regmap[hr];
10226             else f_regmap[hr]=-1;
10227           }
10228           else if(regs[i].regmap[hr]>=0) {
10229             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10230               // dealloc old register
10231               int n;
10232               for(n=0;n<HOST_REGS;n++)
10233               {
10234                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10235               }
10236               // and alloc new one
10237               f_regmap[hr]=regs[i].regmap[hr];
10238             }
10239           }
10240           if(branch_regs[i].regmap[hr]>64) {
10241             if(!((branch_regs[i].dirty>>hr)&1))
10242               f_regmap[hr]=branch_regs[i].regmap[hr];
10243             else f_regmap[hr]=-1;
10244           }
10245           else if(branch_regs[i].regmap[hr]>=0) {
10246             if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10247               // dealloc old register
10248               int n;
10249               for(n=0;n<HOST_REGS;n++)
10250               {
10251                 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10252               }
10253               // and alloc new one
10254               f_regmap[hr]=branch_regs[i].regmap[hr];
10255             }
10256           }
10257           if(ooo[i]) {
10258             if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10259               f_regmap[hr]=branch_regs[i].regmap[hr];
10260           }else{
10261             if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10262               f_regmap[hr]=branch_regs[i].regmap[hr];
10263           }
10264           // Avoid dirty->clean transition
10265           #ifdef DESTRUCTIVE_WRITEBACK
10266           if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10267           #endif
10268           // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10269           // case above, however it's always a good idea.  We can't hoist the
10270           // load if the register was already allocated, so there's no point
10271           // wasting time analyzing most of these cases.  It only "succeeds"
10272           // when the mapping was different and the load can be replaced with
10273           // a mov, which is of negligible benefit.  So such cases are
10274           // skipped below.
10275           if(f_regmap[hr]>0) {
10276             if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10277               int r=f_regmap[hr];
10278               for(j=t;j<=i;j++)
10279               {
10280                 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10281                 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10282                 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10283                 if(r>63) {
10284                   // NB This can exclude the case where the upper-half
10285                   // register is lower numbered than the lower-half
10286                   // register.  Not sure if it's worth fixing...
10287                   if(get_reg(regs[j].regmap,r&63)<0) break;
10288                   if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10289                   if(regs[j].is32&(1LL<<(r&63))) break;
10290                 }
10291                 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10292                   //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10293                   int k;
10294                   if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10295                     if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10296                     if(r>63) {
10297                       if(get_reg(regs[i].regmap,r&63)<0) break;
10298                       if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10299                     }
10300                     k=i;
10301                     while(k>1&&regs[k-1].regmap[hr]==-1) {
10302                       if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10303                         //printf("no free regs for store %x\n",start+(k-1)*4);
10304                         break;
10305                       }
10306                       if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10307                         //printf("no-match due to different register\n");
10308                         break;
10309                       }
10310                       if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10311                         //printf("no-match due to branch\n");
10312                         break;
10313                       }
10314                       // call/ret fast path assumes no registers allocated
10315                       if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10316                         break;
10317                       }
10318                       if(r>63) {
10319                         // NB This can exclude the case where the upper-half
10320                         // register is lower numbered than the lower-half
10321                         // register.  Not sure if it's worth fixing...
10322                         if(get_reg(regs[k-1].regmap,r&63)<0) break;
10323                         if(regs[k-1].is32&(1LL<<(r&63))) break;
10324                       }
10325                       k--;
10326                     }
10327                     if(i<slen-1) {
10328                       if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10329                         (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10330                         //printf("bad match after branch\n");
10331                         break;
10332                       }
10333                     }
10334                     if(regs[k-1].regmap[hr]==f_regmap[hr]&&regmap_pre[k][hr]==f_regmap[hr]) {
10335                       //printf("Extend r%d, %x ->\n",hr,start+k*4);
10336                       while(k<i) {
10337                         regs[k].regmap_entry[hr]=f_regmap[hr];
10338                         regs[k].regmap[hr]=f_regmap[hr];
10339                         regmap_pre[k+1][hr]=f_regmap[hr];
10340                         regs[k].wasdirty&=~(1<<hr);
10341                         regs[k].dirty&=~(1<<hr);
10342                         regs[k].wasdirty|=(1<<hr)&regs[k-1].dirty;
10343                         regs[k].dirty|=(1<<hr)&regs[k].wasdirty;
10344                         regs[k].wasconst&=~(1<<hr);
10345                         regs[k].isconst&=~(1<<hr);
10346                         k++;
10347                       }
10348                     }
10349                     else {
10350                       //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10351                       break;
10352                     }
10353                     assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10354                     if(regs[i-1].regmap[hr]==f_regmap[hr]&&regmap_pre[i][hr]==f_regmap[hr]) {
10355                       //printf("OK fill %x (r%d)\n",start+i*4,hr);
10356                       regs[i].regmap_entry[hr]=f_regmap[hr];
10357                       regs[i].regmap[hr]=f_regmap[hr];
10358                       regs[i].wasdirty&=~(1<<hr);
10359                       regs[i].dirty&=~(1<<hr);
10360                       regs[i].wasdirty|=(1<<hr)&regs[i-1].dirty;
10361                       regs[i].dirty|=(1<<hr)&regs[i-1].dirty;
10362                       regs[i].wasconst&=~(1<<hr);
10363                       regs[i].isconst&=~(1<<hr);
10364                       branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10365                       branch_regs[i].wasdirty&=~(1<<hr);
10366                       branch_regs[i].wasdirty|=(1<<hr)&regs[i].dirty;
10367                       branch_regs[i].regmap[hr]=f_regmap[hr];
10368                       branch_regs[i].dirty&=~(1<<hr);
10369                       branch_regs[i].dirty|=(1<<hr)&regs[i].dirty;
10370                       branch_regs[i].wasconst&=~(1<<hr);
10371                       branch_regs[i].isconst&=~(1<<hr);
10372                       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10373                         regmap_pre[i+2][hr]=f_regmap[hr];
10374                         regs[i+2].wasdirty&=~(1<<hr);
10375                         regs[i+2].wasdirty|=(1<<hr)&regs[i].dirty;
10376                         assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10377                           (regs[i+2].was32&(1LL<<f_regmap[hr])));
10378                       }
10379                     }
10380                   }
10381                   for(k=t;k<j;k++) {
10382                     // Alloc register clean at beginning of loop,
10383                     // but may dirty it in pass 6
10384                     regs[k].regmap_entry[hr]=f_regmap[hr];
10385                     regs[k].regmap[hr]=f_regmap[hr];
10386                     regs[k].dirty&=~(1<<hr);
10387                     regs[k].wasconst&=~(1<<hr);
10388                     regs[k].isconst&=~(1<<hr);
10389                     if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10390                       branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10391                       branch_regs[k].regmap[hr]=f_regmap[hr];
10392                       branch_regs[k].dirty&=~(1<<hr);
10393                       branch_regs[k].wasconst&=~(1<<hr);
10394                       branch_regs[k].isconst&=~(1<<hr);
10395                       if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10396                         regmap_pre[k+2][hr]=f_regmap[hr];
10397                         regs[k+2].wasdirty&=~(1<<hr);
10398                         assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10399                           (regs[k+2].was32&(1LL<<f_regmap[hr])));
10400                       }
10401                     }
10402                     else
10403                     {
10404                       regmap_pre[k+1][hr]=f_regmap[hr];
10405                       regs[k+1].wasdirty&=~(1<<hr);
10406                     }
10407                   }
10408                   if(regs[j].regmap[hr]==f_regmap[hr])
10409                     regs[j].regmap_entry[hr]=f_regmap[hr];
10410                   break;
10411                 }
10412                 if(j==i) break;
10413                 if(regs[j].regmap[hr]>=0)
10414                   break;
10415                 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10416                   //printf("no-match due to different register\n");
10417                   break;
10418                 }
10419                 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10420                   //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10421                   break;
10422                 }
10423                 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10424                 {
10425                   // Stop on unconditional branch
10426                   break;
10427                 }
10428                 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10429                 {
10430                   if(ooo[j]) {
10431                     if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10432                       break;
10433                   }else{
10434                     if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10435                       break;
10436                   }
10437                   if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10438                     //printf("no-match due to different register (branch)\n");
10439                     break;
10440                   }
10441                 }
10442                 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10443                   //printf("No free regs for store %x\n",start+j*4);
10444                   break;
10445                 }
10446                 if(f_regmap[hr]>=64) {
10447                   if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10448                     break;
10449                   }
10450                   else
10451                   {
10452                     if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10453                       break;
10454                     }
10455                   }
10456                 }
10457               }
10458             }
10459           }
10460         }
10461       }
10462     }else{
10463       // Non branch or undetermined branch target
10464       for(hr=0;hr<HOST_REGS;hr++)
10465       {
10466         if(hr!=EXCLUDE_REG) {
10467           if(regs[i].regmap[hr]>64) {
10468             if(!((regs[i].dirty>>hr)&1))
10469               f_regmap[hr]=regs[i].regmap[hr];
10470           }
10471           else if(regs[i].regmap[hr]>=0) {
10472             if(f_regmap[hr]!=regs[i].regmap[hr]) {
10473               // dealloc old register
10474               int n;
10475               for(n=0;n<HOST_REGS;n++)
10476               {
10477                 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10478               }
10479               // and alloc new one
10480               f_regmap[hr]=regs[i].regmap[hr];
10481             }
10482           }
10483         }
10484       }
10485       // Try to restore cycle count at branch targets
10486       if(bt[i]) {
10487         for(j=i;j<slen-1;j++) {
10488           if(regs[j].regmap[HOST_CCREG]!=-1) break;
10489           if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10490             //printf("no free regs for store %x\n",start+j*4);
10491             break;
10492           }
10493         }
10494         if(regs[j].regmap[HOST_CCREG]==CCREG) {
10495           int k=i;
10496           //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10497           while(k<j) {
10498             regs[k].regmap_entry[HOST_CCREG]=CCREG;
10499             regs[k].regmap[HOST_CCREG]=CCREG;
10500             regmap_pre[k+1][HOST_CCREG]=CCREG;
10501             regs[k+1].wasdirty|=1<<HOST_CCREG;
10502             regs[k].dirty|=1<<HOST_CCREG;
10503             regs[k].wasconst&=~(1<<HOST_CCREG);
10504             regs[k].isconst&=~(1<<HOST_CCREG);
10505             k++;
10506           }
10507           regs[j].regmap_entry[HOST_CCREG]=CCREG;
10508         }
10509         // Work backwards from the branch target
10510         if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10511         {
10512           //printf("Extend backwards\n");
10513           int k;
10514           k=i;
10515           while(regs[k-1].regmap[HOST_CCREG]==-1) {
10516             if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10517               //printf("no free regs for store %x\n",start+(k-1)*4);
10518               break;
10519             }
10520             k--;
10521           }
10522           if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10523             //printf("Extend CC, %x ->\n",start+k*4);
10524             while(k<=i) {
10525               regs[k].regmap_entry[HOST_CCREG]=CCREG;
10526               regs[k].regmap[HOST_CCREG]=CCREG;
10527               regmap_pre[k+1][HOST_CCREG]=CCREG;
10528               regs[k+1].wasdirty|=1<<HOST_CCREG;
10529               regs[k].dirty|=1<<HOST_CCREG;
10530               regs[k].wasconst&=~(1<<HOST_CCREG);
10531               regs[k].isconst&=~(1<<HOST_CCREG);
10532               k++;
10533             }
10534           }
10535           else {
10536             //printf("Fail Extend CC, %x ->\n",start+k*4);
10537           }
10538         }
10539       }
10540       if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10541          itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10542          itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10543          itype[i]!=FCONV&&itype[i]!=FCOMP)
10544       {
10545         memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10546       }
10547     }
10548   }
10549
10550   // Cache memory offset or tlb map pointer if a register is available
10551   #ifndef HOST_IMM_ADDR32
10552   #ifndef RAM_OFFSET
10553   if(using_tlb)
10554   #endif
10555   {
10556     int earliest_available[HOST_REGS];
10557     int loop_start[HOST_REGS];
10558     int score[HOST_REGS];
10559     int end[HOST_REGS];
10560     int reg=using_tlb?MMREG:ROREG;
10561
10562     // Init
10563     for(hr=0;hr<HOST_REGS;hr++) {
10564       score[hr]=0;earliest_available[hr]=0;
10565       loop_start[hr]=MAXBLOCK;
10566     }
10567     for(i=0;i<slen-1;i++)
10568     {
10569       // Can't do anything if no registers are available
10570       if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10571         for(hr=0;hr<HOST_REGS;hr++) {
10572           score[hr]=0;earliest_available[hr]=i+1;
10573           loop_start[hr]=MAXBLOCK;
10574         }
10575       }
10576       if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10577         if(!ooo[i]) {
10578           if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10579             for(hr=0;hr<HOST_REGS;hr++) {
10580               score[hr]=0;earliest_available[hr]=i+1;
10581               loop_start[hr]=MAXBLOCK;
10582             }
10583           }
10584         }else{
10585           if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10586             for(hr=0;hr<HOST_REGS;hr++) {
10587               score[hr]=0;earliest_available[hr]=i+1;
10588               loop_start[hr]=MAXBLOCK;
10589             }
10590           }
10591         }
10592       }
10593       // Mark unavailable registers
10594       for(hr=0;hr<HOST_REGS;hr++) {
10595         if(regs[i].regmap[hr]>=0) {
10596           score[hr]=0;earliest_available[hr]=i+1;
10597           loop_start[hr]=MAXBLOCK;
10598         }
10599         if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10600           if(branch_regs[i].regmap[hr]>=0) {
10601             score[hr]=0;earliest_available[hr]=i+2;
10602             loop_start[hr]=MAXBLOCK;
10603           }
10604         }
10605       }
10606       // No register allocations after unconditional jumps
10607       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10608       {
10609         for(hr=0;hr<HOST_REGS;hr++) {
10610           score[hr]=0;earliest_available[hr]=i+2;
10611           loop_start[hr]=MAXBLOCK;
10612         }
10613         i++; // Skip delay slot too
10614         //printf("skip delay slot: %x\n",start+i*4);
10615       }
10616       else
10617       // Possible match
10618       if(itype[i]==LOAD||itype[i]==LOADLR||
10619          itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10620         for(hr=0;hr<HOST_REGS;hr++) {
10621           if(hr!=EXCLUDE_REG) {
10622             end[hr]=i-1;
10623             for(j=i;j<slen-1;j++) {
10624               if(regs[j].regmap[hr]>=0) break;
10625               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10626                 if(branch_regs[j].regmap[hr]>=0) break;
10627                 if(ooo[j]) {
10628                   if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10629                 }else{
10630                   if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10631                 }
10632               }
10633               else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10634               if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10635                 int t=(ba[j]-start)>>2;
10636                 if(t<j&&t>=earliest_available[hr]) {
10637                   if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10638                     // Score a point for hoisting loop invariant
10639                     if(t<loop_start[hr]) loop_start[hr]=t;
10640                     //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10641                     score[hr]++;
10642                     end[hr]=j;
10643                   }
10644                 }
10645                 else if(t<j) {
10646                   if(regs[t].regmap[hr]==reg) {
10647                     // Score a point if the branch target matches this register
10648                     score[hr]++;
10649                     end[hr]=j;
10650                   }
10651                 }
10652                 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10653                    itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10654                   score[hr]++;
10655                   end[hr]=j;
10656                 }
10657               }
10658               if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10659               {
10660                 // Stop on unconditional branch
10661                 break;
10662               }
10663               else
10664               if(itype[j]==LOAD||itype[j]==LOADLR||
10665                  itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10666                 score[hr]++;
10667                 end[hr]=j;
10668               }
10669             }
10670           }
10671         }
10672         // Find highest score and allocate that register
10673         int maxscore=0;
10674         for(hr=0;hr<HOST_REGS;hr++) {
10675           if(hr!=EXCLUDE_REG) {
10676             if(score[hr]>score[maxscore]) {
10677               maxscore=hr;
10678               //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10679             }
10680           }
10681         }
10682         if(score[maxscore]>1)
10683         {
10684           if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10685           for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10686             //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10687             assert(regs[j].regmap[maxscore]<0);
10688             if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10689             regs[j].regmap[maxscore]=reg;
10690             regs[j].dirty&=~(1<<maxscore);
10691             regs[j].wasconst&=~(1<<maxscore);
10692             regs[j].isconst&=~(1<<maxscore);
10693             if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10694               branch_regs[j].regmap[maxscore]=reg;
10695               branch_regs[j].wasdirty&=~(1<<maxscore);
10696               branch_regs[j].dirty&=~(1<<maxscore);
10697               branch_regs[j].wasconst&=~(1<<maxscore);
10698               branch_regs[j].isconst&=~(1<<maxscore);
10699               if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10700                 regmap_pre[j+2][maxscore]=reg;
10701                 regs[j+2].wasdirty&=~(1<<maxscore);
10702               }
10703               // loop optimization (loop_preload)
10704               int t=(ba[j]-start)>>2;
10705               if(t==loop_start[maxscore]) {
10706                 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10707                   regs[t].regmap_entry[maxscore]=reg;
10708               }
10709             }
10710             else
10711             {
10712               if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10713                 regmap_pre[j+1][maxscore]=reg;
10714                 regs[j+1].wasdirty&=~(1<<maxscore);
10715               }
10716             }
10717           }
10718           i=j-1;
10719           if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10720           for(hr=0;hr<HOST_REGS;hr++) {
10721             score[hr]=0;earliest_available[hr]=i+i;
10722             loop_start[hr]=MAXBLOCK;
10723           }
10724         }
10725       }
10726     }
10727   }
10728   #endif
10729
10730   // This allocates registers (if possible) one instruction prior
10731   // to use, which can avoid a load-use penalty on certain CPUs.
10732   for(i=0;i<slen-1;i++)
10733   {
10734     if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10735     {
10736       if(!bt[i+1])
10737       {
10738         if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10739            ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10740         {
10741           if(rs1[i+1]) {
10742             if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10743             {
10744               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10745               {
10746                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10747                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10748                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10749                 regs[i].isconst&=~(1<<hr);
10750                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10751                 constmap[i][hr]=constmap[i+1][hr];
10752                 regs[i+1].wasdirty&=~(1<<hr);
10753                 regs[i].dirty&=~(1<<hr);
10754               }
10755             }
10756           }
10757           if(rs2[i+1]) {
10758             if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10759             {
10760               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10761               {
10762                 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10763                 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10764                 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10765                 regs[i].isconst&=~(1<<hr);
10766                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10767                 constmap[i][hr]=constmap[i+1][hr];
10768                 regs[i+1].wasdirty&=~(1<<hr);
10769                 regs[i].dirty&=~(1<<hr);
10770               }
10771             }
10772           }
10773           // Preload target address for load instruction (non-constant)
10774           if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10775             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10776             {
10777               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10778               {
10779                 regs[i].regmap[hr]=rs1[i+1];
10780                 regmap_pre[i+1][hr]=rs1[i+1];
10781                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10782                 regs[i].isconst&=~(1<<hr);
10783                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10784                 constmap[i][hr]=constmap[i+1][hr];
10785                 regs[i+1].wasdirty&=~(1<<hr);
10786                 regs[i].dirty&=~(1<<hr);
10787               }
10788             }
10789           }
10790           // Load source into target register
10791           if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10792             if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10793             {
10794               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10795               {
10796                 regs[i].regmap[hr]=rs1[i+1];
10797                 regmap_pre[i+1][hr]=rs1[i+1];
10798                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10799                 regs[i].isconst&=~(1<<hr);
10800                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10801                 constmap[i][hr]=constmap[i+1][hr];
10802                 regs[i+1].wasdirty&=~(1<<hr);
10803                 regs[i].dirty&=~(1<<hr);
10804               }
10805             }
10806           }
10807           // Preload map address
10808           #ifndef HOST_IMM_ADDR32
10809           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10810             hr=get_reg(regs[i+1].regmap,TLREG);
10811             if(hr>=0) {
10812               int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10813               if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10814                 int nr;
10815                 if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10816                 {
10817                   regs[i].regmap[hr]=MGEN1+((i+1)&1);
10818                   regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10819                   regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10820                   regs[i].isconst&=~(1<<hr);
10821                   regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10822                   constmap[i][hr]=constmap[i+1][hr];
10823                   regs[i+1].wasdirty&=~(1<<hr);
10824                   regs[i].dirty&=~(1<<hr);
10825                 }
10826                 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10827                 {
10828                   // move it to another register
10829                   regs[i+1].regmap[hr]=-1;
10830                   regmap_pre[i+2][hr]=-1;
10831                   regs[i+1].regmap[nr]=TLREG;
10832                   regmap_pre[i+2][nr]=TLREG;
10833                   regs[i].regmap[nr]=MGEN1+((i+1)&1);
10834                   regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10835                   regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10836                   regs[i].isconst&=~(1<<nr);
10837                   regs[i+1].isconst&=~(1<<nr);
10838                   regs[i].dirty&=~(1<<nr);
10839                   regs[i+1].wasdirty&=~(1<<nr);
10840                   regs[i+1].dirty&=~(1<<nr);
10841                   regs[i+2].wasdirty&=~(1<<nr);
10842                 }
10843               }
10844             }
10845           }
10846           #endif
10847           // Address for store instruction (non-constant)
10848           if(itype[i+1]==STORE||itype[i+1]==STORELR
10849              ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10850             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10851               hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10852               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10853               else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10854               assert(hr>=0);
10855               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10856               {
10857                 regs[i].regmap[hr]=rs1[i+1];
10858                 regmap_pre[i+1][hr]=rs1[i+1];
10859                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10860                 regs[i].isconst&=~(1<<hr);
10861                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10862                 constmap[i][hr]=constmap[i+1][hr];
10863                 regs[i+1].wasdirty&=~(1<<hr);
10864                 regs[i].dirty&=~(1<<hr);
10865               }
10866             }
10867           }
10868           if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10869             if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10870               int nr;
10871               hr=get_reg(regs[i+1].regmap,FTEMP);
10872               assert(hr>=0);
10873               if(regs[i].regmap[hr]<0&&regs[i+1].regmap_entry[hr]<0)
10874               {
10875                 regs[i].regmap[hr]=rs1[i+1];
10876                 regmap_pre[i+1][hr]=rs1[i+1];
10877                 regs[i+1].regmap_entry[hr]=rs1[i+1];
10878                 regs[i].isconst&=~(1<<hr);
10879                 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10880                 constmap[i][hr]=constmap[i+1][hr];
10881                 regs[i+1].wasdirty&=~(1<<hr);
10882                 regs[i].dirty&=~(1<<hr);
10883               }
10884               else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10885               {
10886                 // move it to another register
10887                 regs[i+1].regmap[hr]=-1;
10888                 regmap_pre[i+2][hr]=-1;
10889                 regs[i+1].regmap[nr]=FTEMP;
10890                 regmap_pre[i+2][nr]=FTEMP;
10891                 regs[i].regmap[nr]=rs1[i+1];
10892                 regmap_pre[i+1][nr]=rs1[i+1];
10893                 regs[i+1].regmap_entry[nr]=rs1[i+1];
10894                 regs[i].isconst&=~(1<<nr);
10895                 regs[i+1].isconst&=~(1<<nr);
10896                 regs[i].dirty&=~(1<<nr);
10897                 regs[i+1].wasdirty&=~(1<<nr);
10898                 regs[i+1].dirty&=~(1<<nr);
10899                 regs[i+2].wasdirty&=~(1<<nr);
10900               }
10901             }
10902           }
10903           if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10904             if(itype[i+1]==LOAD)
10905               hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10906             if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10907               hr=get_reg(regs[i+1].regmap,FTEMP);
10908             if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10909               hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10910               if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10911             }
10912             if(hr>=0&&regs[i].regmap[hr]<0) {
10913               int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10914               if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10915                 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10916                 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10917                 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10918                 regs[i].isconst&=~(1<<hr);
10919                 regs[i+1].wasdirty&=~(1<<hr);
10920                 regs[i].dirty&=~(1<<hr);
10921               }
10922             }
10923           }
10924         }
10925       }
10926     }
10927   }
10928
10929   /* Pass 6 - Optimize clean/dirty state */
10930   clean_registers(0,slen-1,1);
10931
10932   /* Pass 7 - Identify 32-bit registers */
10933 #ifndef FORCE32
10934   provisional_r32();
10935
10936   u_int r32=0;
10937
10938   for (i=slen-1;i>=0;i--)
10939   {
10940     int hr;
10941     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10942     {
10943       if(ba[i]<start || ba[i]>=(start+slen*4))
10944       {
10945         // Branch out of this block, don't need anything
10946         r32=0;
10947       }
10948       else
10949       {
10950         // Internal branch
10951         // Need whatever matches the target
10952         // (and doesn't get overwritten by the delay slot instruction)
10953         r32=0;
10954         int t=(ba[i]-start)>>2;
10955         if(ba[i]>start+i*4) {
10956           // Forward branch
10957           if(!(requires_32bit[t]&~regs[i].was32))
10958             r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10959         }else{
10960           // Backward branch
10961           //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10962           //  r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10963           if(!(pr32[t]&~regs[i].was32))
10964             r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10965         }
10966       }
10967       // Conditional branch may need registers for following instructions
10968       if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10969       {
10970         if(i<slen-2) {
10971           r32|=requires_32bit[i+2];
10972           r32&=regs[i].was32;
10973           // Mark this address as a branch target since it may be called
10974           // upon return from interrupt
10975           bt[i+2]=1;
10976         }
10977       }
10978       // Merge in delay slot
10979       if(!likely[i]) {
10980         // These are overwritten unless the branch is "likely"
10981         // and the delay slot is nullified if not taken
10982         r32&=~(1LL<<rt1[i+1]);
10983         r32&=~(1LL<<rt2[i+1]);
10984       }
10985       // Assume these are needed (delay slot)
10986       if(us1[i+1]>0)
10987       {
10988         if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10989       }
10990       if(us2[i+1]>0)
10991       {
10992         if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10993       }
10994       if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10995       {
10996         if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10997       }
10998       if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10999       {
11000         if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
11001       }
11002     }
11003     else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
11004     {
11005       // SYSCALL instruction (software interrupt)
11006       r32=0;
11007     }
11008     else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
11009     {
11010       // ERET instruction (return from interrupt)
11011       r32=0;
11012     }
11013     // Check 32 bits
11014     r32&=~(1LL<<rt1[i]);
11015     r32&=~(1LL<<rt2[i]);
11016     if(us1[i]>0)
11017     {
11018       if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
11019     }
11020     if(us2[i]>0)
11021     {
11022       if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
11023     }
11024     if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
11025     {
11026       if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
11027     }
11028     if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
11029     {
11030       if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
11031     }
11032     requires_32bit[i]=r32;
11033
11034     // Dirty registers which are 32-bit, require 32-bit input
11035     // as they will be written as 32-bit values
11036     for(hr=0;hr<HOST_REGS;hr++)
11037     {
11038       if(regs[i].regmap_entry[hr]>0&&regs[i].regmap_entry[hr]<64) {
11039         if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
11040           if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
11041           requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
11042         }
11043       }
11044     }
11045     //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
11046   }
11047 #else
11048   for (i=slen-1;i>=0;i--)
11049   {
11050     if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11051     {
11052       // Conditional branch
11053       if((source[i]>>16)!=0x1000&&i<slen-2) {
11054         // Mark this address as a branch target since it may be called
11055         // upon return from interrupt
11056         bt[i+2]=1;
11057       }
11058     }
11059   }
11060 #endif
11061
11062   if(itype[slen-1]==SPAN) {
11063     bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
11064   }
11065
11066 #ifdef DISASM
11067   /* Debug/disassembly */
11068   for(i=0;i<slen;i++)
11069   {
11070     printf("U:");
11071     int r;
11072     for(r=1;r<=CCREG;r++) {
11073       if((unneeded_reg[i]>>r)&1) {
11074         if(r==HIREG) printf(" HI");
11075         else if(r==LOREG) printf(" LO");
11076         else printf(" r%d",r);
11077       }
11078     }
11079 #ifndef FORCE32
11080     printf(" UU:");
11081     for(r=1;r<=CCREG;r++) {
11082       if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
11083         if(r==HIREG) printf(" HI");
11084         else if(r==LOREG) printf(" LO");
11085         else printf(" r%d",r);
11086       }
11087     }
11088     printf(" 32:");
11089     for(r=0;r<=CCREG;r++) {
11090       //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11091       if((regs[i].was32>>r)&1) {
11092         if(r==CCREG) printf(" CC");
11093         else if(r==HIREG) printf(" HI");
11094         else if(r==LOREG) printf(" LO");
11095         else printf(" r%d",r);
11096       }
11097     }
11098 #endif
11099     printf("\n");
11100     #if defined(__i386__) || defined(__x86_64__)
11101     printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11102     #endif
11103     #ifdef __arm__
11104     printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11105     #endif
11106     printf("needs: ");
11107     if(needed_reg[i]&1) printf("eax ");
11108     if((needed_reg[i]>>1)&1) printf("ecx ");
11109     if((needed_reg[i]>>2)&1) printf("edx ");
11110     if((needed_reg[i]>>3)&1) printf("ebx ");
11111     if((needed_reg[i]>>5)&1) printf("ebp ");
11112     if((needed_reg[i]>>6)&1) printf("esi ");
11113     if((needed_reg[i]>>7)&1) printf("edi ");
11114     printf("r:");
11115     for(r=0;r<=CCREG;r++) {
11116       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11117       if((requires_32bit[i]>>r)&1) {
11118         if(r==CCREG) printf(" CC");
11119         else if(r==HIREG) printf(" HI");
11120         else if(r==LOREG) printf(" LO");
11121         else printf(" r%d",r);
11122       }
11123     }
11124     printf("\n");
11125     /*printf("pr:");
11126     for(r=0;r<=CCREG;r++) {
11127       //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11128       if((pr32[i]>>r)&1) {
11129         if(r==CCREG) printf(" CC");
11130         else if(r==HIREG) printf(" HI");
11131         else if(r==LOREG) printf(" LO");
11132         else printf(" r%d",r);
11133       }
11134     }
11135     if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11136     printf("\n");*/
11137     #if defined(__i386__) || defined(__x86_64__)
11138     printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11139     printf("dirty: ");
11140     if(regs[i].wasdirty&1) printf("eax ");
11141     if((regs[i].wasdirty>>1)&1) printf("ecx ");
11142     if((regs[i].wasdirty>>2)&1) printf("edx ");
11143     if((regs[i].wasdirty>>3)&1) printf("ebx ");
11144     if((regs[i].wasdirty>>5)&1) printf("ebp ");
11145     if((regs[i].wasdirty>>6)&1) printf("esi ");
11146     if((regs[i].wasdirty>>7)&1) printf("edi ");
11147     #endif
11148     #ifdef __arm__
11149     printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11150     printf("dirty: ");
11151     if(regs[i].wasdirty&1) printf("r0 ");
11152     if((regs[i].wasdirty>>1)&1) printf("r1 ");
11153     if((regs[i].wasdirty>>2)&1) printf("r2 ");
11154     if((regs[i].wasdirty>>3)&1) printf("r3 ");
11155     if((regs[i].wasdirty>>4)&1) printf("r4 ");
11156     if((regs[i].wasdirty>>5)&1) printf("r5 ");
11157     if((regs[i].wasdirty>>6)&1) printf("r6 ");
11158     if((regs[i].wasdirty>>7)&1) printf("r7 ");
11159     if((regs[i].wasdirty>>8)&1) printf("r8 ");
11160     if((regs[i].wasdirty>>9)&1) printf("r9 ");
11161     if((regs[i].wasdirty>>10)&1) printf("r10 ");
11162     if((regs[i].wasdirty>>12)&1) printf("r12 ");
11163     #endif
11164     printf("\n");
11165     disassemble_inst(i);
11166     //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11167     #if defined(__i386__) || defined(__x86_64__)
11168     printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11169     if(regs[i].dirty&1) printf("eax ");
11170     if((regs[i].dirty>>1)&1) printf("ecx ");
11171     if((regs[i].dirty>>2)&1) printf("edx ");
11172     if((regs[i].dirty>>3)&1) printf("ebx ");
11173     if((regs[i].dirty>>5)&1) printf("ebp ");
11174     if((regs[i].dirty>>6)&1) printf("esi ");
11175     if((regs[i].dirty>>7)&1) printf("edi ");
11176     #endif
11177     #ifdef __arm__
11178     printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11179     if(regs[i].dirty&1) printf("r0 ");
11180     if((regs[i].dirty>>1)&1) printf("r1 ");
11181     if((regs[i].dirty>>2)&1) printf("r2 ");
11182     if((regs[i].dirty>>3)&1) printf("r3 ");
11183     if((regs[i].dirty>>4)&1) printf("r4 ");
11184     if((regs[i].dirty>>5)&1) printf("r5 ");
11185     if((regs[i].dirty>>6)&1) printf("r6 ");
11186     if((regs[i].dirty>>7)&1) printf("r7 ");
11187     if((regs[i].dirty>>8)&1) printf("r8 ");
11188     if((regs[i].dirty>>9)&1) printf("r9 ");
11189     if((regs[i].dirty>>10)&1) printf("r10 ");
11190     if((regs[i].dirty>>12)&1) printf("r12 ");
11191     #endif
11192     printf("\n");
11193     if(regs[i].isconst) {
11194       printf("constants: ");
11195       #if defined(__i386__) || defined(__x86_64__)
11196       if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11197       if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11198       if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11199       if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11200       if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11201       if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11202       if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11203       #endif
11204       #ifdef __arm__
11205       if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11206       if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11207       if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11208       if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11209       if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11210       if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11211       if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11212       if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11213       if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11214       if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11215       if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11216       if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11217       #endif
11218       printf("\n");
11219     }
11220 #ifndef FORCE32
11221     printf(" 32:");
11222     for(r=0;r<=CCREG;r++) {
11223       if((regs[i].is32>>r)&1) {
11224         if(r==CCREG) printf(" CC");
11225         else if(r==HIREG) printf(" HI");
11226         else if(r==LOREG) printf(" LO");
11227         else printf(" r%d",r);
11228       }
11229     }
11230     printf("\n");
11231 #endif
11232     /*printf(" p32:");
11233     for(r=0;r<=CCREG;r++) {
11234       if((p32[i]>>r)&1) {
11235         if(r==CCREG) printf(" CC");
11236         else if(r==HIREG) printf(" HI");
11237         else if(r==LOREG) printf(" LO");
11238         else printf(" r%d",r);
11239       }
11240     }
11241     if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11242     else printf("\n");*/
11243     if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11244       #if defined(__i386__) || defined(__x86_64__)
11245       printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11246       if(branch_regs[i].dirty&1) printf("eax ");
11247       if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11248       if((branch_regs[i].dirty>>2)&1) printf("edx ");
11249       if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11250       if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11251       if((branch_regs[i].dirty>>6)&1) printf("esi ");
11252       if((branch_regs[i].dirty>>7)&1) printf("edi ");
11253       #endif
11254       #ifdef __arm__
11255       printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11256       if(branch_regs[i].dirty&1) printf("r0 ");
11257       if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11258       if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11259       if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11260       if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11261       if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11262       if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11263       if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11264       if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11265       if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11266       if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11267       if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11268       #endif
11269 #ifndef FORCE32
11270       printf(" 32:");
11271       for(r=0;r<=CCREG;r++) {
11272         if((branch_regs[i].is32>>r)&1) {
11273           if(r==CCREG) printf(" CC");
11274           else if(r==HIREG) printf(" HI");
11275           else if(r==LOREG) printf(" LO");
11276           else printf(" r%d",r);
11277         }
11278       }
11279       printf("\n");
11280 #endif
11281     }
11282   }
11283 #endif // DISASM
11284
11285   /* Pass 8 - Assembly */
11286   linkcount=0;stubcount=0;
11287   ds=0;is_delayslot=0;
11288   cop1_usable=0;
11289   uint64_t is32_pre=0;
11290   u_int dirty_pre=0;
11291   u_int beginning=(u_int)out;
11292   if((u_int)addr&1) {
11293     ds=1;
11294     pagespan_ds();
11295   }
11296   u_int instr_addr0_override=0;
11297
11298 #ifdef PCSX
11299   if (start == 0x80030000) {
11300     // nasty hack for fastbios thing
11301     // override block entry to this code
11302     instr_addr0_override=(u_int)out;
11303     emit_movimm(start,0);
11304     // abuse io address var as a flag that we
11305     // have already returned here once
11306     emit_readword((int)&address,1);
11307     emit_writeword(0,(int)&pcaddr);
11308     emit_writeword(0,(int)&address);
11309     emit_cmp(0,1);
11310     emit_jne((int)new_dyna_leave);
11311   }
11312 #endif
11313   for(i=0;i<slen;i++)
11314   {
11315     //if(ds) printf("ds: ");
11316     disassemble_inst(i);
11317     if(ds) {
11318       ds=0; // Skip delay slot
11319       if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11320       instr_addr[i]=0;
11321     } else {
11322       speculate_register_values(i);
11323       #ifndef DESTRUCTIVE_WRITEBACK
11324       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11325       {
11326         wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11327               unneeded_reg[i],unneeded_reg_upper[i]);
11328         wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11329               unneeded_reg[i],unneeded_reg_upper[i]);
11330       }
11331       if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11332         is32_pre=branch_regs[i].is32;
11333         dirty_pre=branch_regs[i].dirty;
11334       }else{
11335         is32_pre=regs[i].is32;
11336         dirty_pre=regs[i].dirty;
11337       }
11338       #endif
11339       // write back
11340       if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11341       {
11342         wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11343                       unneeded_reg[i],unneeded_reg_upper[i]);
11344         loop_preload(regmap_pre[i],regs[i].regmap_entry);
11345       }
11346       // branch target entry point
11347       instr_addr[i]=(u_int)out;
11348       assem_debug("<->\n");
11349       // load regs
11350       if(regs[i].regmap_entry[HOST_CCREG]==CCREG&&regs[i].regmap[HOST_CCREG]!=CCREG)
11351         wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11352       load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11353       address_generation(i,&regs[i],regs[i].regmap_entry);
11354       load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11355       if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11356       {
11357         // Load the delay slot registers if necessary
11358         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11359           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11360         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11361           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11362         if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11363           load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11364       }
11365       else if(i+1<slen)
11366       {
11367         // Preload registers for following instruction
11368         if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11369           if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11370             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11371         if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11372           if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11373             load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11374       }
11375       // TODO: if(is_ooo(i)) address_generation(i+1);
11376       if(itype[i]==CJUMP||itype[i]==FJUMP)
11377         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11378       if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11379         load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11380       if(bt[i]) cop1_usable=0;
11381       // assemble
11382       switch(itype[i]) {
11383         case ALU:
11384           alu_assemble(i,&regs[i]);break;
11385         case IMM16:
11386           imm16_assemble(i,&regs[i]);break;
11387         case SHIFT:
11388           shift_assemble(i,&regs[i]);break;
11389         case SHIFTIMM:
11390           shiftimm_assemble(i,&regs[i]);break;
11391         case LOAD:
11392           load_assemble(i,&regs[i]);break;
11393         case LOADLR:
11394           loadlr_assemble(i,&regs[i]);break;
11395         case STORE:
11396           store_assemble(i,&regs[i]);break;
11397         case STORELR:
11398           storelr_assemble(i,&regs[i]);break;
11399         case COP0:
11400           cop0_assemble(i,&regs[i]);break;
11401         case COP1:
11402           cop1_assemble(i,&regs[i]);break;
11403         case C1LS:
11404           c1ls_assemble(i,&regs[i]);break;
11405         case COP2:
11406           cop2_assemble(i,&regs[i]);break;
11407         case C2LS:
11408           c2ls_assemble(i,&regs[i]);break;
11409         case C2OP:
11410           c2op_assemble(i,&regs[i]);break;
11411         case FCONV:
11412           fconv_assemble(i,&regs[i]);break;
11413         case FLOAT:
11414           float_assemble(i,&regs[i]);break;
11415         case FCOMP:
11416           fcomp_assemble(i,&regs[i]);break;
11417         case MULTDIV:
11418           multdiv_assemble(i,&regs[i]);break;
11419         case MOV:
11420           mov_assemble(i,&regs[i]);break;
11421         case SYSCALL:
11422           syscall_assemble(i,&regs[i]);break;
11423         case HLECALL:
11424           hlecall_assemble(i,&regs[i]);break;
11425         case INTCALL:
11426           intcall_assemble(i,&regs[i]);break;
11427         case UJUMP:
11428           ujump_assemble(i,&regs[i]);ds=1;break;
11429         case RJUMP:
11430           rjump_assemble(i,&regs[i]);ds=1;break;
11431         case CJUMP:
11432           cjump_assemble(i,&regs[i]);ds=1;break;
11433         case SJUMP:
11434           sjump_assemble(i,&regs[i]);ds=1;break;
11435         case FJUMP:
11436           fjump_assemble(i,&regs[i]);ds=1;break;
11437         case SPAN:
11438           pagespan_assemble(i,&regs[i]);break;
11439       }
11440       if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11441         literal_pool(1024);
11442       else
11443         literal_pool_jumpover(256);
11444     }
11445   }
11446   //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11447   // If the block did not end with an unconditional branch,
11448   // add a jump to the next instruction.
11449   if(i>1) {
11450     if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11451       assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11452       assert(i==slen);
11453       if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11454         store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11455         if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11456           emit_loadreg(CCREG,HOST_CCREG);
11457         emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11458       }
11459       else if(!likely[i-2])
11460       {
11461         store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11462         assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11463       }
11464       else
11465       {
11466         store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11467         assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11468       }
11469       add_to_linker((int)out,start+i*4,0);
11470       emit_jmp(0);
11471     }
11472   }
11473   else
11474   {
11475     assert(i>0);
11476     assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11477     store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11478     if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11479       emit_loadreg(CCREG,HOST_CCREG);
11480     emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11481     add_to_linker((int)out,start+i*4,0);
11482     emit_jmp(0);
11483   }
11484
11485   // TODO: delay slot stubs?
11486   // Stubs
11487   for(i=0;i<stubcount;i++)
11488   {
11489     switch(stubs[i][0])
11490     {
11491       case LOADB_STUB:
11492       case LOADH_STUB:
11493       case LOADW_STUB:
11494       case LOADD_STUB:
11495       case LOADBU_STUB:
11496       case LOADHU_STUB:
11497         do_readstub(i);break;
11498       case STOREB_STUB:
11499       case STOREH_STUB:
11500       case STOREW_STUB:
11501       case STORED_STUB:
11502         do_writestub(i);break;
11503       case CC_STUB:
11504         do_ccstub(i);break;
11505       case INVCODE_STUB:
11506         do_invstub(i);break;
11507       case FP_STUB:
11508         do_cop1stub(i);break;
11509       case STORELR_STUB:
11510         do_unalignedwritestub(i);break;
11511     }
11512   }
11513
11514   if (instr_addr0_override)
11515     instr_addr[0] = instr_addr0_override;
11516
11517   /* Pass 9 - Linker */
11518   for(i=0;i<linkcount;i++)
11519   {
11520     assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11521     literal_pool(64);
11522     if(!link_addr[i][2])
11523     {
11524       void *stub=out;
11525       void *addr=check_addr(link_addr[i][1]);
11526       emit_extjump(link_addr[i][0],link_addr[i][1]);
11527       if(addr) {
11528         set_jump_target(link_addr[i][0],(int)addr);
11529         add_link(link_addr[i][1],stub);
11530       }
11531       else set_jump_target(link_addr[i][0],(int)stub);
11532     }
11533     else
11534     {
11535       // Internal branch
11536       int target=(link_addr[i][1]-start)>>2;
11537       assert(target>=0&&target<slen);
11538       assert(instr_addr[target]);
11539       //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11540       //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11541       //#else
11542       set_jump_target(link_addr[i][0],instr_addr[target]);
11543       //#endif
11544     }
11545   }
11546   // External Branch Targets (jump_in)
11547   if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11548   for(i=0;i<slen;i++)
11549   {
11550     if(bt[i]||i==0)
11551     {
11552       if(instr_addr[i]) // TODO - delay slots (=null)
11553       {
11554         u_int vaddr=start+i*4;
11555         u_int page=get_page(vaddr);
11556         u_int vpage=get_vpage(vaddr);
11557         literal_pool(256);
11558         {
11559           assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11560           assem_debug("jump_in: %x\n",start+i*4);
11561           ll_add(jump_dirty+vpage,vaddr,(void *)out);
11562           int entry_point=do_dirty_stub(i);
11563           ll_add_flags(jump_in+page,vaddr,state_rflags,(void *)entry_point);
11564           // If there was an existing entry in the hash table,
11565           // replace it with the new address.
11566           // Don't add new entries.  We'll insert the
11567           // ones that actually get used in check_addr().
11568           int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11569           if(ht_bin[0]==vaddr) {
11570             ht_bin[1]=entry_point;
11571           }
11572           if(ht_bin[2]==vaddr) {
11573             ht_bin[3]=entry_point;
11574           }
11575         }
11576       }
11577     }
11578   }
11579   // Write out the literal pool if necessary
11580   literal_pool(0);
11581   #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11582   // Align code
11583   if(((u_int)out)&7) emit_addnop(13);
11584   #endif
11585   assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11586   //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11587   memcpy(copy,source,slen*4);
11588   copy+=slen*4;
11589
11590   #ifdef __arm__
11591   __clear_cache((void *)beginning,out);
11592   #endif
11593
11594   // If we're within 256K of the end of the buffer,
11595   // start over from the beginning. (Is 256K enough?)
11596   if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11597
11598   // Trap writes to any of the pages we compiled
11599   for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11600     invalid_code[i]=0;
11601 #ifndef DISABLE_TLB
11602     memory_map[i]|=0x40000000;
11603     if((signed int)start>=(signed int)0xC0000000) {
11604       assert(using_tlb);
11605       j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11606       invalid_code[j]=0;
11607       memory_map[j]|=0x40000000;
11608       //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11609     }
11610 #endif
11611   }
11612   inv_code_start=inv_code_end=~0;
11613 #ifdef PCSX
11614   // for PCSX we need to mark all mirrors too
11615   if(get_page(start)<(RAM_SIZE>>12))
11616     for(i=start>>12;i<=(start+slen*4)>>12;i++)
11617       invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11618       invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11619       invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11620 #endif
11621
11622   /* Pass 10 - Free memory by expiring oldest blocks */
11623
11624   int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11625   while(expirep!=end)
11626   {
11627     int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11628     int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11629     inv_debug("EXP: Phase %d\n",expirep);
11630     switch((expirep>>11)&3)
11631     {
11632       case 0:
11633         // Clear jump_in and jump_dirty
11634         ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11635         ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11636         ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11637         ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11638         break;
11639       case 1:
11640         // Clear pointers
11641         ll_kill_pointers(jump_out[expirep&2047],base,shift);
11642         ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11643         break;
11644       case 2:
11645         // Clear hash table
11646         for(i=0;i<32;i++) {
11647           int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11648           if((ht_bin[3]>>shift)==(base>>shift) ||
11649              ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11650             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11651             ht_bin[2]=ht_bin[3]=-1;
11652           }
11653           if((ht_bin[1]>>shift)==(base>>shift) ||
11654              ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11655             inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11656             ht_bin[0]=ht_bin[2];
11657             ht_bin[1]=ht_bin[3];
11658             ht_bin[2]=ht_bin[3]=-1;
11659           }
11660         }
11661         break;
11662       case 3:
11663         // Clear jump_out
11664         #ifdef __arm__
11665         if((expirep&2047)==0)
11666           do_clear_cache();
11667         #endif
11668         ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11669         ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11670         break;
11671     }
11672     expirep=(expirep+1)&65535;
11673   }
11674   return 0;
11675 }
11676
11677 // vim:shiftwidth=2:expandtab