1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2010 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
25 #include "emu_if.h" //emulator interface
30 #include "assem_x86.h"
33 #include "assem_x64.h"
36 #include "assem_arm.h"
40 #define MAX_OUTPUT_BLOCK_SIZE 262144
41 #define CLOCK_DIVIDER 2
45 signed char regmap_entry[HOST_REGS];
46 signed char regmap[HOST_REGS];
55 uint64_t constmap[HOST_REGS];
63 struct ll_entry *next;
69 char insn[MAXBLOCK][10];
70 u_char itype[MAXBLOCK];
71 u_char opcode[MAXBLOCK];
72 u_char opcode2[MAXBLOCK];
80 u_char dep1[MAXBLOCK];
81 u_char dep2[MAXBLOCK];
85 char likely[MAXBLOCK];
87 uint64_t unneeded_reg[MAXBLOCK];
88 uint64_t unneeded_reg_upper[MAXBLOCK];
89 uint64_t branch_unneeded_reg[MAXBLOCK];
90 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
91 uint64_t p32[MAXBLOCK];
92 uint64_t pr32[MAXBLOCK];
93 signed char regmap_pre[MAXBLOCK][HOST_REGS];
94 signed char regmap[MAXBLOCK][HOST_REGS];
95 signed char regmap_entry[MAXBLOCK][HOST_REGS];
96 uint64_t constmap[MAXBLOCK][HOST_REGS];
97 uint64_t known_value[HOST_REGS];
99 struct regstat regs[MAXBLOCK];
100 struct regstat branch_regs[MAXBLOCK];
101 u_int needed_reg[MAXBLOCK];
102 uint64_t requires_32bit[MAXBLOCK];
103 u_int wont_dirty[MAXBLOCK];
104 u_int will_dirty[MAXBLOCK];
107 u_int instr_addr[MAXBLOCK];
108 u_int link_addr[MAXBLOCK][3];
110 u_int stubs[MAXBLOCK*3][8];
112 u_int literals[1024][2];
117 struct ll_entry *jump_in[4096];
118 struct ll_entry *jump_out[4096];
119 struct ll_entry *jump_dirty[4096];
120 u_int hash_table[65536][4] __attribute__((aligned(16)));
121 char shadow[1048576] __attribute__((aligned(16)));
125 u_int stop_after_jal;
126 extern u_char restore_candidate[512];
127 extern int cycle_count;
129 /* registers that may be allocated */
131 #define HIREG 32 // hi
132 #define LOREG 33 // lo
133 #define FSREG 34 // FPU status (FCSR)
134 #define CSREG 35 // Coprocessor status
135 #define CCREG 36 // Cycle count
136 #define INVCP 37 // Pointer to invalid_code
138 #define FTEMP 38 // FPU/LDL/LDR temporary register
139 #define PTEMP 39 // Prefetch temporary register
140 #define TLREG 40 // TLB mapping offset
141 #define RHASH 41 // Return address hash
142 #define RHTBL 42 // Return address hash table address
143 #define RTEMP 43 // JR/JALR address register
145 #define AGEN1 44 // Address generation temporary register
146 #define AGEN2 45 // Address generation temporary register
147 #define MGEN1 46 // Maptable address generation temporary register
148 #define MGEN2 47 // Maptable address generation temporary register
149 #define BTREG 48 // Branch target temporary register
151 /* instruction types */
152 #define NOP 0 // No operation
153 #define LOAD 1 // Load
154 #define STORE 2 // Store
155 #define LOADLR 3 // Unaligned load
156 #define STORELR 4 // Unaligned store
157 #define MOV 5 // Move
158 #define ALU 6 // Arithmetic/logic
159 #define MULTDIV 7 // Multiply/divide
160 #define SHIFT 8 // Shift by register
161 #define SHIFTIMM 9// Shift by immediate
162 #define IMM16 10 // 16-bit immediate
163 #define RJUMP 11 // Unconditional jump to register
164 #define UJUMP 12 // Unconditional jump
165 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
166 #define SJUMP 14 // Conditional branch (regimm format)
167 #define COP0 15 // Coprocessor 0
168 #define COP1 16 // Coprocessor 1
169 #define C1LS 17 // Coprocessor 1 load/store
170 #define FJUMP 18 // Conditional branch (floating point)
171 #define FLOAT 19 // Floating point unit
172 #define FCONV 20 // Convert integer to float
173 #define FCOMP 21 // Floating point compare (sets FSREG)
174 #define SYSCALL 22// SYSCALL
175 #define OTHER 23 // Other
176 #define SPAN 24 // Branch/delay slot spans 2 pages
177 #define NI 25 // Not implemented
178 #define HLECALL 26// PCSX fake opcodes for HLE
179 #define COP2 27 // Coprocessor 2 move
180 #define C2LS 28 // Coprocessor 2 load/store
181 #define C2OP 29 // Coprocessor 2 operation
182 #define INTCALL 30// Call interpreter to handle rare corner cases
191 #define LOADBU_STUB 7
192 #define LOADHU_STUB 8
193 #define STOREB_STUB 9
194 #define STOREH_STUB 10
195 #define STOREW_STUB 11
196 #define STORED_STUB 12
197 #define STORELR_STUB 13
198 #define INVCODE_STUB 14
206 int new_recompile_block(int addr);
207 void *get_addr_ht(u_int vaddr);
208 void invalidate_block(u_int block);
209 void invalidate_addr(u_int addr);
210 void remove_hash(int vaddr);
213 void dyna_linker_ds();
215 void verify_code_vm();
216 void verify_code_ds();
219 void fp_exception_ds();
221 void jump_syscall_hle();
225 void new_dyna_leave();
230 void read_nomem_new();
231 void read_nomemb_new();
232 void read_nomemh_new();
233 void read_nomemd_new();
234 void write_nomem_new();
235 void write_nomemb_new();
236 void write_nomemh_new();
237 void write_nomemd_new();
238 void write_rdram_new();
239 void write_rdramb_new();
240 void write_rdramh_new();
241 void write_rdramd_new();
242 extern u_int memory_map[1048576];
244 // Needed by assembler
245 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
246 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
247 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
248 void load_all_regs(signed char i_regmap[]);
249 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
250 void load_regs_entry(int t);
251 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
255 //#define DEBUG_CYCLE_COUNT 1
258 //#define assem_debug printf
259 //#define inv_debug printf
260 #define assem_debug nullf
261 #define inv_debug nullf
263 static void tlb_hacks()
267 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
271 switch (ROM_HEADER->Country_code&0xFF)
283 // Unknown country code
287 u_int rom_addr=(u_int)rom;
289 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
290 // in the lower 4G of memory to use this hack. Copy it if necessary.
291 if((void *)rom>(void *)0xffffffff) {
292 munmap(ROM_COPY, 67108864);
293 if(mmap(ROM_COPY, 12582912,
294 PROT_READ | PROT_WRITE,
295 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
296 -1, 0) <= 0) {printf("mmap() failed\n");}
297 memcpy(ROM_COPY,rom,12582912);
298 rom_addr=(u_int)ROM_COPY;
302 for(n=0x7F000;n<0x80000;n++) {
303 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
310 static u_int get_page(u_int vaddr)
312 u_int page=(vaddr^0x80000000)>>12;
314 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
316 if(page>2048) page=2048+(page&2047);
320 static u_int get_vpage(u_int vaddr)
322 u_int vpage=(vaddr^0x80000000)>>12;
324 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
326 if(vpage>2048) vpage=2048+(vpage&2047);
330 // Get address from virtual address
331 // This is called from the recompiled JR/JALR instructions
332 void *get_addr(u_int vaddr)
334 u_int page=get_page(vaddr);
335 u_int vpage=get_vpage(vaddr);
336 struct ll_entry *head;
337 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
340 if(head->vaddr==vaddr&&head->reg32==0) {
341 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
342 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
345 ht_bin[1]=(int)head->addr;
351 head=jump_dirty[vpage];
353 if(head->vaddr==vaddr&&head->reg32==0) {
354 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
355 // Don't restore blocks which are about to expire from the cache
356 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
357 if(verify_dirty(head->addr)) {
358 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
359 invalid_code[vaddr>>12]=0;
360 memory_map[vaddr>>12]|=0x40000000;
363 if(tlb_LUT_r[vaddr>>12]) {
364 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
365 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
368 restore_candidate[vpage>>3]|=1<<(vpage&7);
370 else restore_candidate[page>>3]|=1<<(page&7);
371 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
372 if(ht_bin[0]==vaddr) {
373 ht_bin[1]=(int)head->addr; // Replace existing entry
379 ht_bin[1]=(int)head->addr;
387 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
388 int r=new_recompile_block(vaddr);
389 if(r==0) return get_addr(vaddr);
390 // Execute in unmapped page, generate pagefault execption
392 Cause=(vaddr<<31)|0x8;
393 EPC=(vaddr&1)?vaddr-5:vaddr;
395 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
396 EntryHi=BadVAddr&0xFFFFE000;
397 return get_addr_ht(0x80000000);
399 // Look up address in hash table first
400 void *get_addr_ht(u_int vaddr)
402 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
403 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
404 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
405 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
406 return get_addr(vaddr);
409 void *get_addr_32(u_int vaddr,u_int flags)
412 return get_addr(vaddr);
414 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
415 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
416 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
417 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
418 u_int page=get_page(vaddr);
419 u_int vpage=get_vpage(vaddr);
420 struct ll_entry *head;
423 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
424 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
426 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
428 ht_bin[1]=(int)head->addr;
430 }else if(ht_bin[2]==-1) {
431 ht_bin[3]=(int)head->addr;
434 //ht_bin[3]=ht_bin[1];
435 //ht_bin[2]=ht_bin[0];
436 //ht_bin[1]=(int)head->addr;
443 head=jump_dirty[vpage];
445 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
446 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
447 // Don't restore blocks which are about to expire from the cache
448 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
449 if(verify_dirty(head->addr)) {
450 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
451 invalid_code[vaddr>>12]=0;
452 memory_map[vaddr>>12]|=0x40000000;
455 if(tlb_LUT_r[vaddr>>12]) {
456 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
457 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
460 restore_candidate[vpage>>3]|=1<<(vpage&7);
462 else restore_candidate[page>>3]|=1<<(page&7);
464 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
466 ht_bin[1]=(int)head->addr;
468 }else if(ht_bin[2]==-1) {
469 ht_bin[3]=(int)head->addr;
472 //ht_bin[3]=ht_bin[1];
473 //ht_bin[2]=ht_bin[0];
474 //ht_bin[1]=(int)head->addr;
482 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
483 int r=new_recompile_block(vaddr);
484 if(r==0) return get_addr(vaddr);
485 // Execute in unmapped page, generate pagefault execption
487 Cause=(vaddr<<31)|0x8;
488 EPC=(vaddr&1)?vaddr-5:vaddr;
490 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
491 EntryHi=BadVAddr&0xFFFFE000;
492 return get_addr_ht(0x80000000);
496 void clear_all_regs(signed char regmap[])
499 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
502 signed char get_reg(signed char regmap[],int r)
505 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
509 // Find a register that is available for two consecutive cycles
510 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
513 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
517 int count_free_regs(signed char regmap[])
521 for(hr=0;hr<HOST_REGS;hr++)
523 if(hr!=EXCLUDE_REG) {
524 if(regmap[hr]<0) count++;
530 void dirty_reg(struct regstat *cur,signed char reg)
534 for (hr=0;hr<HOST_REGS;hr++) {
535 if((cur->regmap[hr]&63)==reg) {
541 // If we dirty the lower half of a 64 bit register which is now being
542 // sign-extended, we need to dump the upper half.
543 // Note: Do this only after completion of the instruction, because
544 // some instructions may need to read the full 64-bit value even if
545 // overwriting it (eg SLTI, DSRA32).
546 static void flush_dirty_uppers(struct regstat *cur)
549 for (hr=0;hr<HOST_REGS;hr++) {
550 if((cur->dirty>>hr)&1) {
553 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
558 void set_const(struct regstat *cur,signed char reg,uint64_t value)
562 for (hr=0;hr<HOST_REGS;hr++) {
563 if(cur->regmap[hr]==reg) {
565 cur->constmap[hr]=value;
567 else if((cur->regmap[hr]^64)==reg) {
569 cur->constmap[hr]=value>>32;
574 void clear_const(struct regstat *cur,signed char reg)
578 for (hr=0;hr<HOST_REGS;hr++) {
579 if((cur->regmap[hr]&63)==reg) {
580 cur->isconst&=~(1<<hr);
585 int is_const(struct regstat *cur,signed char reg)
589 for (hr=0;hr<HOST_REGS;hr++) {
590 if((cur->regmap[hr]&63)==reg) {
591 return (cur->isconst>>hr)&1;
596 uint64_t get_const(struct regstat *cur,signed char reg)
600 for (hr=0;hr<HOST_REGS;hr++) {
601 if(cur->regmap[hr]==reg) {
602 return cur->constmap[hr];
605 printf("Unknown constant in r%d\n",reg);
609 // Least soon needed registers
610 // Look at the next ten instructions and see which registers
611 // will be used. Try not to reallocate these.
612 void lsn(u_char hsn[], int i, int *preferred_reg)
622 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
624 // Don't go past an unconditonal jump
631 if(rs1[i+j]) hsn[rs1[i+j]]=j;
632 if(rs2[i+j]) hsn[rs2[i+j]]=j;
633 if(rt1[i+j]) hsn[rt1[i+j]]=j;
634 if(rt2[i+j]) hsn[rt2[i+j]]=j;
635 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
636 // Stores can allocate zero
640 // On some architectures stores need invc_ptr
641 #if defined(HOST_IMM8)
642 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
646 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
654 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
656 // Follow first branch
657 int t=(ba[i+b]-start)>>2;
658 j=7-b;if(t+j>=slen) j=slen-t-1;
661 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
662 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
663 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
664 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
667 // TODO: preferred register based on backward branch
669 // Delay slot should preferably not overwrite branch conditions or cycle count
670 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
671 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
672 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
678 // Coprocessor load/store needs FTEMP, even if not declared
679 if(itype[i]==C1LS||itype[i]==C2LS) {
682 // Load L/R also uses FTEMP as a temporary register
683 if(itype[i]==LOADLR) {
686 // Also SWL/SWR/SDL/SDR
687 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
690 // Don't remove the TLB registers either
691 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
694 // Don't remove the miniht registers
695 if(itype[i]==UJUMP||itype[i]==RJUMP)
702 // We only want to allocate registers if we're going to use them again soon
703 int needed_again(int r, int i)
709 u_char hsn[MAXREG+1];
712 memset(hsn,10,sizeof(hsn));
713 lsn(hsn,i,&preferred_reg);
715 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
717 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
718 return 0; // Don't need any registers if exiting the block
726 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
728 // Don't go past an unconditonal jump
732 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
739 if(rs1[i+j]==r) rn=j;
740 if(rs2[i+j]==r) rn=j;
741 if((unneeded_reg[i+j]>>r)&1) rn=10;
742 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
750 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
752 // Follow first branch
754 int t=(ba[i+b]-start)>>2;
755 j=7-b;if(t+j>=slen) j=slen-t-1;
758 if(!((unneeded_reg[t+j]>>r)&1)) {
759 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
760 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
766 for(hr=0;hr<HOST_REGS;hr++) {
767 if(hr!=EXCLUDE_REG) {
768 if(rn<hsn[hr]) return 1;
774 // Try to match register allocations at the end of a loop with those
776 int loop_reg(int i, int r, int hr)
785 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
787 // Don't go past an unconditonal jump
794 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
799 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
800 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
801 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
803 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
805 int t=(ba[i+k]-start)>>2;
806 int reg=get_reg(regs[t].regmap_entry,r);
807 if(reg>=0) return reg;
808 //reg=get_reg(regs[t+1].regmap_entry,r);
809 //if(reg>=0) return reg;
817 // Allocate every register, preserving source/target regs
818 void alloc_all(struct regstat *cur,int i)
822 for(hr=0;hr<HOST_REGS;hr++) {
823 if(hr!=EXCLUDE_REG) {
824 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
825 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
828 cur->dirty&=~(1<<hr);
831 if((cur->regmap[hr]&63)==0)
834 cur->dirty&=~(1<<hr);
841 void div64(int64_t dividend,int64_t divisor)
845 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
846 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
848 void divu64(uint64_t dividend,uint64_t divisor)
852 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
853 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
856 void mult64(uint64_t m1,uint64_t m2)
858 unsigned long long int op1, op2, op3, op4;
859 unsigned long long int result1, result2, result3, result4;
860 unsigned long long int temp1, temp2, temp3, temp4;
876 op1 = op2 & 0xFFFFFFFF;
877 op2 = (op2 >> 32) & 0xFFFFFFFF;
878 op3 = op4 & 0xFFFFFFFF;
879 op4 = (op4 >> 32) & 0xFFFFFFFF;
882 temp2 = (temp1 >> 32) + op1 * op4;
884 temp4 = (temp3 >> 32) + op2 * op4;
886 result1 = temp1 & 0xFFFFFFFF;
887 result2 = temp2 + (temp3 & 0xFFFFFFFF);
888 result3 = (result2 >> 32) + temp4;
889 result4 = (result3 >> 32);
891 lo = result1 | (result2 << 32);
892 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
901 void multu64(uint64_t m1,uint64_t m2)
903 unsigned long long int op1, op2, op3, op4;
904 unsigned long long int result1, result2, result3, result4;
905 unsigned long long int temp1, temp2, temp3, temp4;
907 op1 = m1 & 0xFFFFFFFF;
908 op2 = (m1 >> 32) & 0xFFFFFFFF;
909 op3 = m2 & 0xFFFFFFFF;
910 op4 = (m2 >> 32) & 0xFFFFFFFF;
913 temp2 = (temp1 >> 32) + op1 * op4;
915 temp4 = (temp3 >> 32) + op2 * op4;
917 result1 = temp1 & 0xFFFFFFFF;
918 result2 = temp2 + (temp3 & 0xFFFFFFFF);
919 result3 = (result2 >> 32) + temp4;
920 result4 = (result3 >> 32);
922 lo = result1 | (result2 << 32);
923 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
925 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
926 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
929 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
937 else original=loaded;
940 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
943 original>>=64-(bits^56);
944 original<<=64-(bits^56);
948 else original=loaded;
953 #include "assem_x86.c"
956 #include "assem_x64.c"
959 #include "assem_arm.c"
962 // Add virtual address mapping to linked list
963 void ll_add(struct ll_entry **head,int vaddr,void *addr)
965 struct ll_entry *new_entry;
966 new_entry=malloc(sizeof(struct ll_entry));
967 assert(new_entry!=NULL);
968 new_entry->vaddr=vaddr;
970 new_entry->addr=addr;
971 new_entry->next=*head;
975 // Add virtual address mapping for 32-bit compiled block
976 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
978 ll_add(head,vaddr,addr);
980 (*head)->reg32=reg32;
984 // Check if an address is already compiled
985 // but don't return addresses which are about to expire from the cache
986 void *check_addr(u_int vaddr)
988 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
989 if(ht_bin[0]==vaddr) {
990 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
991 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
993 if(ht_bin[2]==vaddr) {
994 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
995 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
997 u_int page=get_page(vaddr);
998 struct ll_entry *head;
1001 if(head->vaddr==vaddr&&head->reg32==0) {
1002 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1003 // Update existing entry with current address
1004 if(ht_bin[0]==vaddr) {
1005 ht_bin[1]=(int)head->addr;
1008 if(ht_bin[2]==vaddr) {
1009 ht_bin[3]=(int)head->addr;
1012 // Insert into hash table with low priority.
1013 // Don't evict existing entries, as they are probably
1014 // addresses that are being accessed frequently.
1016 ht_bin[1]=(int)head->addr;
1018 }else if(ht_bin[2]==-1) {
1019 ht_bin[3]=(int)head->addr;
1030 void remove_hash(int vaddr)
1032 //printf("remove hash: %x\n",vaddr);
1033 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1034 if(ht_bin[2]==vaddr) {
1035 ht_bin[2]=ht_bin[3]=-1;
1037 if(ht_bin[0]==vaddr) {
1038 ht_bin[0]=ht_bin[2];
1039 ht_bin[1]=ht_bin[3];
1040 ht_bin[2]=ht_bin[3]=-1;
1044 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1046 struct ll_entry *next;
1048 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1049 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1051 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1052 remove_hash((*head)->vaddr);
1059 head=&((*head)->next);
1064 // Remove all entries from linked list
1065 void ll_clear(struct ll_entry **head)
1067 struct ll_entry *cur;
1068 struct ll_entry *next;
1079 // Dereference the pointers and remove if it matches
1080 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1082 u_int old_host_addr=0;
1084 int ptr=get_pointer(head->addr);
1085 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1086 if(((ptr>>shift)==(addr>>shift)) ||
1087 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1089 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1090 u_int host_addr=(u_int)kill_pointer(head->addr);
1092 if((host_addr>>12)!=(old_host_addr>>12)) {
1094 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1096 old_host_addr=host_addr;
1103 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1107 // This is called when we write to a compiled block (see do_invstub)
1108 void invalidate_page(u_int page)
1110 struct ll_entry *head;
1111 struct ll_entry *next;
1112 u_int old_host_addr=0;
1116 inv_debug("INVALIDATE: %x\n",head->vaddr);
1117 remove_hash(head->vaddr);
1122 head=jump_out[page];
1125 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1126 u_int host_addr=(u_int)kill_pointer(head->addr);
1128 if((host_addr>>12)!=(old_host_addr>>12)) {
1130 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1132 old_host_addr=host_addr;
1140 __clear_cache((void *)(old_host_addr&~0xfff),(void *)(old_host_addr|0xfff));
1143 void invalidate_block(u_int block)
1145 u_int page=get_page(block<<12);
1146 u_int vpage=get_vpage(block<<12);
1147 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1148 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1151 struct ll_entry *head;
1152 head=jump_dirty[vpage];
1153 //printf("page=%d vpage=%d\n",page,vpage);
1156 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1157 get_bounds((int)head->addr,&start,&end);
1158 //printf("start: %x end: %x\n",start,end);
1159 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1160 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1161 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1162 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1166 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1167 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1168 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1169 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1176 //printf("first=%d last=%d\n",first,last);
1177 invalidate_page(page);
1178 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1179 assert(last<page+5);
1180 // Invalidate the adjacent pages if a block crosses a 4K boundary
1182 invalidate_page(first);
1185 for(first=page+1;first<last;first++) {
1186 invalidate_page(first);
1189 // Don't trap writes
1190 invalid_code[block]=1;
1192 // If there is a valid TLB entry for this page, remove write protect
1193 if(tlb_LUT_w[block]) {
1194 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1195 // CHECK: Is this right?
1196 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1197 u_int real_block=tlb_LUT_w[block]>>12;
1198 invalid_code[real_block]=1;
1199 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1201 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1205 memset(mini_ht,-1,sizeof(mini_ht));
1208 void invalidate_addr(u_int addr)
1210 invalidate_block(addr>>12);
1212 void invalidate_all_pages()
1215 for(page=0;page<4096;page++)
1216 invalidate_page(page);
1217 for(page=0;page<1048576;page++)
1218 if(!invalid_code[page]) {
1219 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1220 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1223 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1226 memset(mini_ht,-1,sizeof(mini_ht));
1230 for(page=0;page<0x100000;page++) {
1231 if(tlb_LUT_r[page]) {
1232 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1233 if(!tlb_LUT_w[page]||!invalid_code[page])
1234 memory_map[page]|=0x40000000; // Write protect
1236 else memory_map[page]=-1;
1237 if(page==0x80000) page=0xC0000;
1243 // Add an entry to jump_out after making a link
1244 void add_link(u_int vaddr,void *src)
1246 u_int page=get_page(vaddr);
1247 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1248 ll_add(jump_out+page,vaddr,src);
1249 //int ptr=get_pointer(src);
1250 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1253 // If a code block was found to be unmodified (bit was set in
1254 // restore_candidate) and it remains unmodified (bit is clear
1255 // in invalid_code) then move the entries for that 4K page from
1256 // the dirty list to the clean list.
1257 void clean_blocks(u_int page)
1259 struct ll_entry *head;
1260 inv_debug("INV: clean_blocks page=%d\n",page);
1261 head=jump_dirty[page];
1263 if(!invalid_code[head->vaddr>>12]) {
1264 // Don't restore blocks which are about to expire from the cache
1265 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1267 if(verify_dirty((int)head->addr)) {
1268 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1271 get_bounds((int)head->addr,&start,&end);
1272 if(start-(u_int)rdram<RAM_SIZE) {
1273 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1274 inv|=invalid_code[i];
1277 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1278 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1279 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1280 if(addr<start||addr>=end) inv=1;
1282 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1286 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1287 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1290 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1292 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1293 //printf("page=%x, addr=%x\n",page,head->vaddr);
1294 //assert(head->vaddr>>12==(page|0x80000));
1295 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1296 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1298 if(ht_bin[0]==head->vaddr) {
1299 ht_bin[1]=(int)clean_addr; // Replace existing entry
1301 if(ht_bin[2]==head->vaddr) {
1302 ht_bin[3]=(int)clean_addr; // Replace existing entry
1315 void mov_alloc(struct regstat *current,int i)
1317 // Note: Don't need to actually alloc the source registers
1318 if((~current->is32>>rs1[i])&1) {
1319 //alloc_reg64(current,i,rs1[i]);
1320 alloc_reg64(current,i,rt1[i]);
1321 current->is32&=~(1LL<<rt1[i]);
1323 //alloc_reg(current,i,rs1[i]);
1324 alloc_reg(current,i,rt1[i]);
1325 current->is32|=(1LL<<rt1[i]);
1327 clear_const(current,rs1[i]);
1328 clear_const(current,rt1[i]);
1329 dirty_reg(current,rt1[i]);
1332 void shiftimm_alloc(struct regstat *current,int i)
1334 clear_const(current,rs1[i]);
1335 clear_const(current,rt1[i]);
1336 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1339 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1341 alloc_reg(current,i,rt1[i]);
1342 current->is32|=1LL<<rt1[i];
1343 dirty_reg(current,rt1[i]);
1346 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1349 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1350 alloc_reg64(current,i,rt1[i]);
1351 current->is32&=~(1LL<<rt1[i]);
1352 dirty_reg(current,rt1[i]);
1355 if(opcode2[i]==0x3c) // DSLL32
1358 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1359 alloc_reg64(current,i,rt1[i]);
1360 current->is32&=~(1LL<<rt1[i]);
1361 dirty_reg(current,rt1[i]);
1364 if(opcode2[i]==0x3e) // DSRL32
1367 alloc_reg64(current,i,rs1[i]);
1369 alloc_reg64(current,i,rt1[i]);
1370 current->is32&=~(1LL<<rt1[i]);
1372 alloc_reg(current,i,rt1[i]);
1373 current->is32|=1LL<<rt1[i];
1375 dirty_reg(current,rt1[i]);
1378 if(opcode2[i]==0x3f) // DSRA32
1381 alloc_reg64(current,i,rs1[i]);
1382 alloc_reg(current,i,rt1[i]);
1383 current->is32|=1LL<<rt1[i];
1384 dirty_reg(current,rt1[i]);
1389 void shift_alloc(struct regstat *current,int i)
1392 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1394 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1395 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1396 alloc_reg(current,i,rt1[i]);
1397 if(rt1[i]==rs2[i]) alloc_reg_temp(current,i,-1);
1398 current->is32|=1LL<<rt1[i];
1399 } else { // DSLLV/DSRLV/DSRAV
1400 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1401 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1402 alloc_reg64(current,i,rt1[i]);
1403 current->is32&=~(1LL<<rt1[i]);
1404 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1405 alloc_reg_temp(current,i,-1);
1407 clear_const(current,rs1[i]);
1408 clear_const(current,rs2[i]);
1409 clear_const(current,rt1[i]);
1410 dirty_reg(current,rt1[i]);
1414 void alu_alloc(struct regstat *current,int i)
1416 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1418 if(rs1[i]&&rs2[i]) {
1419 alloc_reg(current,i,rs1[i]);
1420 alloc_reg(current,i,rs2[i]);
1423 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1424 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1426 alloc_reg(current,i,rt1[i]);
1428 current->is32|=1LL<<rt1[i];
1430 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1432 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1434 alloc_reg64(current,i,rs1[i]);
1435 alloc_reg64(current,i,rs2[i]);
1436 alloc_reg(current,i,rt1[i]);
1438 alloc_reg(current,i,rs1[i]);
1439 alloc_reg(current,i,rs2[i]);
1440 alloc_reg(current,i,rt1[i]);
1443 current->is32|=1LL<<rt1[i];
1445 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1447 if(rs1[i]&&rs2[i]) {
1448 alloc_reg(current,i,rs1[i]);
1449 alloc_reg(current,i,rs2[i]);
1453 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1454 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1456 alloc_reg(current,i,rt1[i]);
1457 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1459 if(!((current->uu>>rt1[i])&1)) {
1460 alloc_reg64(current,i,rt1[i]);
1462 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1463 if(rs1[i]&&rs2[i]) {
1464 alloc_reg64(current,i,rs1[i]);
1465 alloc_reg64(current,i,rs2[i]);
1469 // Is is really worth it to keep 64-bit values in registers?
1471 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1472 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1476 current->is32&=~(1LL<<rt1[i]);
1478 current->is32|=1LL<<rt1[i];
1482 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1484 if(rs1[i]&&rs2[i]) {
1485 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1486 alloc_reg64(current,i,rs1[i]);
1487 alloc_reg64(current,i,rs2[i]);
1488 alloc_reg64(current,i,rt1[i]);
1490 alloc_reg(current,i,rs1[i]);
1491 alloc_reg(current,i,rs2[i]);
1492 alloc_reg(current,i,rt1[i]);
1496 alloc_reg(current,i,rt1[i]);
1497 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1498 // DADD used as move, or zeroing
1499 // If we have a 64-bit source, then make the target 64 bits too
1500 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1501 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1502 alloc_reg64(current,i,rt1[i]);
1503 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1504 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1505 alloc_reg64(current,i,rt1[i]);
1507 if(opcode2[i]>=0x2e&&rs2[i]) {
1508 // DSUB used as negation - 64-bit result
1509 // If we have a 32-bit register, extend it to 64 bits
1510 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1511 alloc_reg64(current,i,rt1[i]);
1515 if(rs1[i]&&rs2[i]) {
1516 current->is32&=~(1LL<<rt1[i]);
1518 current->is32&=~(1LL<<rt1[i]);
1519 if((current->is32>>rs1[i])&1)
1520 current->is32|=1LL<<rt1[i];
1522 current->is32&=~(1LL<<rt1[i]);
1523 if((current->is32>>rs2[i])&1)
1524 current->is32|=1LL<<rt1[i];
1526 current->is32|=1LL<<rt1[i];
1530 clear_const(current,rs1[i]);
1531 clear_const(current,rs2[i]);
1532 clear_const(current,rt1[i]);
1533 dirty_reg(current,rt1[i]);
1536 void imm16_alloc(struct regstat *current,int i)
1538 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1540 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1541 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1542 current->is32&=~(1LL<<rt1[i]);
1543 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1544 // TODO: Could preserve the 32-bit flag if the immediate is zero
1545 alloc_reg64(current,i,rt1[i]);
1546 alloc_reg64(current,i,rs1[i]);
1548 clear_const(current,rs1[i]);
1549 clear_const(current,rt1[i]);
1551 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1552 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1553 current->is32|=1LL<<rt1[i];
1554 clear_const(current,rs1[i]);
1555 clear_const(current,rt1[i]);
1557 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1558 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1559 if(rs1[i]!=rt1[i]) {
1560 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1561 alloc_reg64(current,i,rt1[i]);
1562 current->is32&=~(1LL<<rt1[i]);
1565 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1566 if(is_const(current,rs1[i])) {
1567 int v=get_const(current,rs1[i]);
1568 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1569 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1570 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1572 else clear_const(current,rt1[i]);
1574 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1575 if(is_const(current,rs1[i])) {
1576 int v=get_const(current,rs1[i]);
1577 set_const(current,rt1[i],v+imm[i]);
1579 else clear_const(current,rt1[i]);
1580 current->is32|=1LL<<rt1[i];
1583 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1584 current->is32|=1LL<<rt1[i];
1586 dirty_reg(current,rt1[i]);
1589 void load_alloc(struct regstat *current,int i)
1591 clear_const(current,rt1[i]);
1592 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1593 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1594 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1596 alloc_reg(current,i,rt1[i]);
1597 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1599 current->is32&=~(1LL<<rt1[i]);
1600 alloc_reg64(current,i,rt1[i]);
1602 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1604 current->is32&=~(1LL<<rt1[i]);
1605 alloc_reg64(current,i,rt1[i]);
1606 alloc_all(current,i);
1607 alloc_reg64(current,i,FTEMP);
1609 else current->is32|=1LL<<rt1[i];
1610 dirty_reg(current,rt1[i]);
1611 // If using TLB, need a register for pointer to the mapping table
1612 if(using_tlb) alloc_reg(current,i,TLREG);
1613 // LWL/LWR need a temporary register for the old value
1614 if(opcode[i]==0x22||opcode[i]==0x26)
1616 alloc_reg(current,i,FTEMP);
1617 alloc_reg_temp(current,i,-1);
1622 // Load to r0 (dummy load)
1623 // but we still need a register to calculate the address
1624 alloc_reg_temp(current,i,-1);
1628 void store_alloc(struct regstat *current,int i)
1630 clear_const(current,rs2[i]);
1631 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1632 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1633 alloc_reg(current,i,rs2[i]);
1634 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1635 alloc_reg64(current,i,rs2[i]);
1636 if(rs2[i]) alloc_reg(current,i,FTEMP);
1638 // If using TLB, need a register for pointer to the mapping table
1639 if(using_tlb) alloc_reg(current,i,TLREG);
1640 #if defined(HOST_IMM8)
1641 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1642 else alloc_reg(current,i,INVCP);
1644 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1645 alloc_reg(current,i,FTEMP);
1647 // We need a temporary register for address generation
1648 alloc_reg_temp(current,i,-1);
1651 void c1ls_alloc(struct regstat *current,int i)
1653 //clear_const(current,rs1[i]); // FIXME
1654 clear_const(current,rt1[i]);
1655 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1656 alloc_reg(current,i,CSREG); // Status
1657 alloc_reg(current,i,FTEMP);
1658 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1659 alloc_reg64(current,i,FTEMP);
1661 // If using TLB, need a register for pointer to the mapping table
1662 if(using_tlb) alloc_reg(current,i,TLREG);
1663 #if defined(HOST_IMM8)
1664 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1665 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1666 alloc_reg(current,i,INVCP);
1668 // We need a temporary register for address generation
1669 alloc_reg_temp(current,i,-1);
1672 void c2ls_alloc(struct regstat *current,int i)
1674 clear_const(current,rt1[i]);
1675 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1676 alloc_reg(current,i,FTEMP);
1677 // If using TLB, need a register for pointer to the mapping table
1678 if(using_tlb) alloc_reg(current,i,TLREG);
1679 #if defined(HOST_IMM8)
1680 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1681 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1682 alloc_reg(current,i,INVCP);
1684 // We need a temporary register for address generation
1685 alloc_reg_temp(current,i,-1);
1688 #ifndef multdiv_alloc
1689 void multdiv_alloc(struct regstat *current,int i)
1696 // case 0x1D: DMULTU
1699 clear_const(current,rs1[i]);
1700 clear_const(current,rs2[i]);
1703 if((opcode2[i]&4)==0) // 32-bit
1705 current->u&=~(1LL<<HIREG);
1706 current->u&=~(1LL<<LOREG);
1707 alloc_reg(current,i,HIREG);
1708 alloc_reg(current,i,LOREG);
1709 alloc_reg(current,i,rs1[i]);
1710 alloc_reg(current,i,rs2[i]);
1711 current->is32|=1LL<<HIREG;
1712 current->is32|=1LL<<LOREG;
1713 dirty_reg(current,HIREG);
1714 dirty_reg(current,LOREG);
1718 current->u&=~(1LL<<HIREG);
1719 current->u&=~(1LL<<LOREG);
1720 current->uu&=~(1LL<<HIREG);
1721 current->uu&=~(1LL<<LOREG);
1722 alloc_reg64(current,i,HIREG);
1723 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1724 alloc_reg64(current,i,rs1[i]);
1725 alloc_reg64(current,i,rs2[i]);
1726 alloc_all(current,i);
1727 current->is32&=~(1LL<<HIREG);
1728 current->is32&=~(1LL<<LOREG);
1729 dirty_reg(current,HIREG);
1730 dirty_reg(current,LOREG);
1735 // Multiply by zero is zero.
1736 // MIPS does not have a divide by zero exception.
1737 // The result is undefined, we return zero.
1738 alloc_reg(current,i,HIREG);
1739 alloc_reg(current,i,LOREG);
1740 current->is32|=1LL<<HIREG;
1741 current->is32|=1LL<<LOREG;
1742 dirty_reg(current,HIREG);
1743 dirty_reg(current,LOREG);
1748 void cop0_alloc(struct regstat *current,int i)
1750 if(opcode2[i]==0) // MFC0
1753 clear_const(current,rt1[i]);
1754 alloc_all(current,i);
1755 alloc_reg(current,i,rt1[i]);
1756 current->is32|=1LL<<rt1[i];
1757 dirty_reg(current,rt1[i]);
1760 else if(opcode2[i]==4) // MTC0
1763 clear_const(current,rs1[i]);
1764 alloc_reg(current,i,rs1[i]);
1765 alloc_all(current,i);
1768 alloc_all(current,i); // FIXME: Keep r0
1770 alloc_reg(current,i,0);
1775 // TLBR/TLBWI/TLBWR/TLBP/ERET
1776 assert(opcode2[i]==0x10);
1777 alloc_all(current,i);
1781 void cop1_alloc(struct regstat *current,int i)
1783 alloc_reg(current,i,CSREG); // Load status
1784 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1787 clear_const(current,rt1[i]);
1789 alloc_reg64(current,i,rt1[i]); // DMFC1
1790 current->is32&=~(1LL<<rt1[i]);
1792 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1793 current->is32|=1LL<<rt1[i];
1795 dirty_reg(current,rt1[i]);
1796 alloc_reg_temp(current,i,-1);
1798 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1801 clear_const(current,rs1[i]);
1803 alloc_reg64(current,i,rs1[i]); // DMTC1
1805 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1806 alloc_reg_temp(current,i,-1);
1810 alloc_reg(current,i,0);
1811 alloc_reg_temp(current,i,-1);
1815 void fconv_alloc(struct regstat *current,int i)
1817 alloc_reg(current,i,CSREG); // Load status
1818 alloc_reg_temp(current,i,-1);
1820 void float_alloc(struct regstat *current,int i)
1822 alloc_reg(current,i,CSREG); // Load status
1823 alloc_reg_temp(current,i,-1);
1825 void c2op_alloc(struct regstat *current,int i)
1827 alloc_reg_temp(current,i,-1);
1829 void fcomp_alloc(struct regstat *current,int i)
1831 alloc_reg(current,i,CSREG); // Load status
1832 alloc_reg(current,i,FSREG); // Load flags
1833 dirty_reg(current,FSREG); // Flag will be modified
1834 alloc_reg_temp(current,i,-1);
1837 void syscall_alloc(struct regstat *current,int i)
1839 alloc_cc(current,i);
1840 dirty_reg(current,CCREG);
1841 alloc_all(current,i);
1845 void delayslot_alloc(struct regstat *current,int i)
1856 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1857 printf("Disabled speculative precompilation\n");
1861 imm16_alloc(current,i);
1865 load_alloc(current,i);
1869 store_alloc(current,i);
1872 alu_alloc(current,i);
1875 shift_alloc(current,i);
1878 multdiv_alloc(current,i);
1881 shiftimm_alloc(current,i);
1884 mov_alloc(current,i);
1887 cop0_alloc(current,i);
1891 cop1_alloc(current,i);
1894 c1ls_alloc(current,i);
1897 c2ls_alloc(current,i);
1900 fconv_alloc(current,i);
1903 float_alloc(current,i);
1906 fcomp_alloc(current,i);
1909 c2op_alloc(current,i);
1914 // Special case where a branch and delay slot span two pages in virtual memory
1915 static void pagespan_alloc(struct regstat *current,int i)
1918 current->wasconst=0;
1920 alloc_all(current,i);
1921 alloc_cc(current,i);
1922 dirty_reg(current,CCREG);
1923 if(opcode[i]==3) // JAL
1925 alloc_reg(current,i,31);
1926 dirty_reg(current,31);
1928 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1930 alloc_reg(current,i,rs1[i]);
1932 alloc_reg(current,i,rt1[i]);
1933 dirty_reg(current,rt1[i]);
1936 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1938 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1939 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1940 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1942 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1943 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1947 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1949 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1950 if(!((current->is32>>rs1[i])&1))
1952 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1956 if(opcode[i]==0x11) // BC1
1958 alloc_reg(current,i,FSREG);
1959 alloc_reg(current,i,CSREG);
1964 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
1966 stubs[stubcount][0]=type;
1967 stubs[stubcount][1]=addr;
1968 stubs[stubcount][2]=retaddr;
1969 stubs[stubcount][3]=a;
1970 stubs[stubcount][4]=b;
1971 stubs[stubcount][5]=c;
1972 stubs[stubcount][6]=d;
1973 stubs[stubcount][7]=e;
1977 // Write out a single register
1978 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1981 for(hr=0;hr<HOST_REGS;hr++) {
1982 if(hr!=EXCLUDE_REG) {
1983 if((regmap[hr]&63)==r) {
1986 emit_storereg(r,hr);
1988 if((is32>>regmap[hr])&1) {
1989 emit_sarimm(hr,31,hr);
1990 emit_storereg(r|64,hr);
1994 emit_storereg(r|64,hr);
2004 //if(!tracedebug) return 0;
2007 for(i=0;i<2097152;i++) {
2008 unsigned int temp=sum;
2011 sum^=((u_int *)rdram)[i];
2020 sum^=((u_int *)reg)[i];
2028 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2030 #ifndef DISABLE_COP1
2033 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2043 void memdebug(int i)
2045 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2046 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2049 //if(Count>=-2084597794) {
2050 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2052 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2053 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2054 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2057 printf("TRACE: %x\n",(&i)[-1]);
2061 printf("TRACE: %x \n",(&j)[10]);
2062 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2066 //printf("TRACE: %x\n",(&i)[-1]);
2069 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2071 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2074 void alu_assemble(int i,struct regstat *i_regs)
2076 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2078 signed char s1,s2,t;
2079 t=get_reg(i_regs->regmap,rt1[i]);
2081 s1=get_reg(i_regs->regmap,rs1[i]);
2082 s2=get_reg(i_regs->regmap,rs2[i]);
2083 if(rs1[i]&&rs2[i]) {
2086 if(opcode2[i]&2) emit_sub(s1,s2,t);
2087 else emit_add(s1,s2,t);
2090 if(s1>=0) emit_mov(s1,t);
2091 else emit_loadreg(rs1[i],t);
2095 if(opcode2[i]&2) emit_neg(s2,t);
2096 else emit_mov(s2,t);
2099 emit_loadreg(rs2[i],t);
2100 if(opcode2[i]&2) emit_neg(t,t);
2103 else emit_zeroreg(t);
2107 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2109 signed char s1l,s2l,s1h,s2h,tl,th;
2110 tl=get_reg(i_regs->regmap,rt1[i]);
2111 th=get_reg(i_regs->regmap,rt1[i]|64);
2113 s1l=get_reg(i_regs->regmap,rs1[i]);
2114 s2l=get_reg(i_regs->regmap,rs2[i]);
2115 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2116 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2117 if(rs1[i]&&rs2[i]) {
2120 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2121 else emit_adds(s1l,s2l,tl);
2123 #ifdef INVERTED_CARRY
2124 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2126 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2128 else emit_add(s1h,s2h,th);
2132 if(s1l>=0) emit_mov(s1l,tl);
2133 else emit_loadreg(rs1[i],tl);
2135 if(s1h>=0) emit_mov(s1h,th);
2136 else emit_loadreg(rs1[i]|64,th);
2141 if(opcode2[i]&2) emit_negs(s2l,tl);
2142 else emit_mov(s2l,tl);
2145 emit_loadreg(rs2[i],tl);
2146 if(opcode2[i]&2) emit_negs(tl,tl);
2149 #ifdef INVERTED_CARRY
2150 if(s2h>=0) emit_mov(s2h,th);
2151 else emit_loadreg(rs2[i]|64,th);
2153 emit_adcimm(-1,th); // x86 has inverted carry flag
2158 if(s2h>=0) emit_rscimm(s2h,0,th);
2160 emit_loadreg(rs2[i]|64,th);
2161 emit_rscimm(th,0,th);
2164 if(s2h>=0) emit_mov(s2h,th);
2165 else emit_loadreg(rs2[i]|64,th);
2172 if(th>=0) emit_zeroreg(th);
2177 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2179 signed char s1l,s1h,s2l,s2h,t;
2180 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2182 t=get_reg(i_regs->regmap,rt1[i]);
2185 s1l=get_reg(i_regs->regmap,rs1[i]);
2186 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2187 s2l=get_reg(i_regs->regmap,rs2[i]);
2188 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2189 if(rs2[i]==0) // rx<r0
2192 if(opcode2[i]==0x2a) // SLT
2193 emit_shrimm(s1h,31,t);
2194 else // SLTU (unsigned can not be less than zero)
2197 else if(rs1[i]==0) // r0<rx
2200 if(opcode2[i]==0x2a) // SLT
2201 emit_set_gz64_32(s2h,s2l,t);
2202 else // SLTU (set if not zero)
2203 emit_set_nz64_32(s2h,s2l,t);
2206 assert(s1l>=0);assert(s1h>=0);
2207 assert(s2l>=0);assert(s2h>=0);
2208 if(opcode2[i]==0x2a) // SLT
2209 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2211 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2215 t=get_reg(i_regs->regmap,rt1[i]);
2218 s1l=get_reg(i_regs->regmap,rs1[i]);
2219 s2l=get_reg(i_regs->regmap,rs2[i]);
2220 if(rs2[i]==0) // rx<r0
2223 if(opcode2[i]==0x2a) // SLT
2224 emit_shrimm(s1l,31,t);
2225 else // SLTU (unsigned can not be less than zero)
2228 else if(rs1[i]==0) // r0<rx
2231 if(opcode2[i]==0x2a) // SLT
2232 emit_set_gz32(s2l,t);
2233 else // SLTU (set if not zero)
2234 emit_set_nz32(s2l,t);
2237 assert(s1l>=0);assert(s2l>=0);
2238 if(opcode2[i]==0x2a) // SLT
2239 emit_set_if_less32(s1l,s2l,t);
2241 emit_set_if_carry32(s1l,s2l,t);
2247 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2249 signed char s1l,s1h,s2l,s2h,th,tl;
2250 tl=get_reg(i_regs->regmap,rt1[i]);
2251 th=get_reg(i_regs->regmap,rt1[i]|64);
2252 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2256 s1l=get_reg(i_regs->regmap,rs1[i]);
2257 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2258 s2l=get_reg(i_regs->regmap,rs2[i]);
2259 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2260 if(rs1[i]&&rs2[i]) {
2261 assert(s1l>=0);assert(s1h>=0);
2262 assert(s2l>=0);assert(s2h>=0);
2263 if(opcode2[i]==0x24) { // AND
2264 emit_and(s1l,s2l,tl);
2265 emit_and(s1h,s2h,th);
2267 if(opcode2[i]==0x25) { // OR
2268 emit_or(s1l,s2l,tl);
2269 emit_or(s1h,s2h,th);
2271 if(opcode2[i]==0x26) { // XOR
2272 emit_xor(s1l,s2l,tl);
2273 emit_xor(s1h,s2h,th);
2275 if(opcode2[i]==0x27) { // NOR
2276 emit_or(s1l,s2l,tl);
2277 emit_or(s1h,s2h,th);
2284 if(opcode2[i]==0x24) { // AND
2288 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2290 if(s1l>=0) emit_mov(s1l,tl);
2291 else emit_loadreg(rs1[i],tl);
2292 if(s1h>=0) emit_mov(s1h,th);
2293 else emit_loadreg(rs1[i]|64,th);
2297 if(s2l>=0) emit_mov(s2l,tl);
2298 else emit_loadreg(rs2[i],tl);
2299 if(s2h>=0) emit_mov(s2h,th);
2300 else emit_loadreg(rs2[i]|64,th);
2307 if(opcode2[i]==0x27) { // NOR
2309 if(s1l>=0) emit_not(s1l,tl);
2311 emit_loadreg(rs1[i],tl);
2314 if(s1h>=0) emit_not(s1h,th);
2316 emit_loadreg(rs1[i]|64,th);
2322 if(s2l>=0) emit_not(s2l,tl);
2324 emit_loadreg(rs2[i],tl);
2327 if(s2h>=0) emit_not(s2h,th);
2329 emit_loadreg(rs2[i]|64,th);
2345 s1l=get_reg(i_regs->regmap,rs1[i]);
2346 s2l=get_reg(i_regs->regmap,rs2[i]);
2347 if(rs1[i]&&rs2[i]) {
2350 if(opcode2[i]==0x24) { // AND
2351 emit_and(s1l,s2l,tl);
2353 if(opcode2[i]==0x25) { // OR
2354 emit_or(s1l,s2l,tl);
2356 if(opcode2[i]==0x26) { // XOR
2357 emit_xor(s1l,s2l,tl);
2359 if(opcode2[i]==0x27) { // NOR
2360 emit_or(s1l,s2l,tl);
2366 if(opcode2[i]==0x24) { // AND
2369 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2371 if(s1l>=0) emit_mov(s1l,tl);
2372 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2376 if(s2l>=0) emit_mov(s2l,tl);
2377 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2379 else emit_zeroreg(tl);
2381 if(opcode2[i]==0x27) { // NOR
2383 if(s1l>=0) emit_not(s1l,tl);
2385 emit_loadreg(rs1[i],tl);
2391 if(s2l>=0) emit_not(s2l,tl);
2393 emit_loadreg(rs2[i],tl);
2397 else emit_movimm(-1,tl);
2406 void imm16_assemble(int i,struct regstat *i_regs)
2408 if (opcode[i]==0x0f) { // LUI
2411 t=get_reg(i_regs->regmap,rt1[i]);
2414 if(!((i_regs->isconst>>t)&1))
2415 emit_movimm(imm[i]<<16,t);
2419 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2422 t=get_reg(i_regs->regmap,rt1[i]);
2423 s=get_reg(i_regs->regmap,rs1[i]);
2428 if(!((i_regs->isconst>>t)&1)) {
2430 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2431 emit_addimm(t,imm[i],t);
2433 if(!((i_regs->wasconst>>s)&1))
2434 emit_addimm(s,imm[i],t);
2436 emit_movimm(constmap[i][s]+imm[i],t);
2442 if(!((i_regs->isconst>>t)&1))
2443 emit_movimm(imm[i],t);
2448 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2450 signed char sh,sl,th,tl;
2451 th=get_reg(i_regs->regmap,rt1[i]|64);
2452 tl=get_reg(i_regs->regmap,rt1[i]);
2453 sh=get_reg(i_regs->regmap,rs1[i]|64);
2454 sl=get_reg(i_regs->regmap,rs1[i]);
2460 emit_addimm64_32(sh,sl,imm[i],th,tl);
2463 emit_addimm(sl,imm[i],tl);
2466 emit_movimm(imm[i],tl);
2467 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2472 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2474 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2475 signed char sh,sl,t;
2476 t=get_reg(i_regs->regmap,rt1[i]);
2477 sh=get_reg(i_regs->regmap,rs1[i]|64);
2478 sl=get_reg(i_regs->regmap,rs1[i]);
2482 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2483 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2484 if(opcode[i]==0x0a) { // SLTI
2486 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2487 emit_slti32(t,imm[i],t);
2489 emit_slti32(sl,imm[i],t);
2494 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2495 emit_sltiu32(t,imm[i],t);
2497 emit_sltiu32(sl,imm[i],t);
2502 if(opcode[i]==0x0a) // SLTI
2503 emit_slti64_32(sh,sl,imm[i],t);
2505 emit_sltiu64_32(sh,sl,imm[i],t);
2508 // SLTI(U) with r0 is just stupid,
2509 // nonetheless examples can be found
2510 if(opcode[i]==0x0a) // SLTI
2511 if(0<imm[i]) emit_movimm(1,t);
2512 else emit_zeroreg(t);
2515 if(imm[i]) emit_movimm(1,t);
2516 else emit_zeroreg(t);
2522 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2524 signed char sh,sl,th,tl;
2525 th=get_reg(i_regs->regmap,rt1[i]|64);
2526 tl=get_reg(i_regs->regmap,rt1[i]);
2527 sh=get_reg(i_regs->regmap,rs1[i]|64);
2528 sl=get_reg(i_regs->regmap,rs1[i]);
2529 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2530 if(opcode[i]==0x0c) //ANDI
2534 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2535 emit_andimm(tl,imm[i],tl);
2537 if(!((i_regs->wasconst>>sl)&1))
2538 emit_andimm(sl,imm[i],tl);
2540 emit_movimm(constmap[i][sl]&imm[i],tl);
2545 if(th>=0) emit_zeroreg(th);
2551 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2555 emit_loadreg(rs1[i]|64,th);
2560 if(opcode[i]==0x0d) //ORI
2562 emit_orimm(tl,imm[i],tl);
2564 if(!((i_regs->wasconst>>sl)&1))
2565 emit_orimm(sl,imm[i],tl);
2567 emit_movimm(constmap[i][sl]|imm[i],tl);
2569 if(opcode[i]==0x0e) //XORI
2571 emit_xorimm(tl,imm[i],tl);
2573 if(!((i_regs->wasconst>>sl)&1))
2574 emit_xorimm(sl,imm[i],tl);
2576 emit_movimm(constmap[i][sl]^imm[i],tl);
2580 emit_movimm(imm[i],tl);
2581 if(th>=0) emit_zeroreg(th);
2589 void shiftimm_assemble(int i,struct regstat *i_regs)
2591 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2595 t=get_reg(i_regs->regmap,rt1[i]);
2596 s=get_reg(i_regs->regmap,rs1[i]);
2605 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2607 if(opcode2[i]==0) // SLL
2609 emit_shlimm(s<0?t:s,imm[i],t);
2611 if(opcode2[i]==2) // SRL
2613 emit_shrimm(s<0?t:s,imm[i],t);
2615 if(opcode2[i]==3) // SRA
2617 emit_sarimm(s<0?t:s,imm[i],t);
2621 if(s>=0 && s!=t) emit_mov(s,t);
2625 //emit_storereg(rt1[i],t); //DEBUG
2628 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2631 signed char sh,sl,th,tl;
2632 th=get_reg(i_regs->regmap,rt1[i]|64);
2633 tl=get_reg(i_regs->regmap,rt1[i]);
2634 sh=get_reg(i_regs->regmap,rs1[i]|64);
2635 sl=get_reg(i_regs->regmap,rs1[i]);
2640 if(th>=0) emit_zeroreg(th);
2647 if(opcode2[i]==0x38) // DSLL
2649 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2650 emit_shlimm(sl,imm[i],tl);
2652 if(opcode2[i]==0x3a) // DSRL
2654 emit_shrdimm(sl,sh,imm[i],tl);
2655 if(th>=0) emit_shrimm(sh,imm[i],th);
2657 if(opcode2[i]==0x3b) // DSRA
2659 emit_shrdimm(sl,sh,imm[i],tl);
2660 if(th>=0) emit_sarimm(sh,imm[i],th);
2664 if(sl!=tl) emit_mov(sl,tl);
2665 if(th>=0&&sh!=th) emit_mov(sh,th);
2671 if(opcode2[i]==0x3c) // DSLL32
2674 signed char sl,tl,th;
2675 tl=get_reg(i_regs->regmap,rt1[i]);
2676 th=get_reg(i_regs->regmap,rt1[i]|64);
2677 sl=get_reg(i_regs->regmap,rs1[i]);
2686 emit_shlimm(th,imm[i]&31,th);
2691 if(opcode2[i]==0x3e) // DSRL32
2694 signed char sh,tl,th;
2695 tl=get_reg(i_regs->regmap,rt1[i]);
2696 th=get_reg(i_regs->regmap,rt1[i]|64);
2697 sh=get_reg(i_regs->regmap,rs1[i]|64);
2701 if(th>=0) emit_zeroreg(th);
2704 emit_shrimm(tl,imm[i]&31,tl);
2709 if(opcode2[i]==0x3f) // DSRA32
2713 tl=get_reg(i_regs->regmap,rt1[i]);
2714 sh=get_reg(i_regs->regmap,rs1[i]|64);
2720 emit_sarimm(tl,imm[i]&31,tl);
2727 #ifndef shift_assemble
2728 void shift_assemble(int i,struct regstat *i_regs)
2730 printf("Need shift_assemble for this architecture.\n");
2735 void load_assemble(int i,struct regstat *i_regs)
2737 int s,th,tl,addr,map=-1;
2740 int memtarget=0,c=0;
2742 th=get_reg(i_regs->regmap,rt1[i]|64);
2743 tl=get_reg(i_regs->regmap,rt1[i]);
2744 s=get_reg(i_regs->regmap,rs1[i]);
2746 for(hr=0;hr<HOST_REGS;hr++) {
2747 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2749 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2751 c=(i_regs->wasconst>>s)&1;
2752 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2753 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2755 //printf("load_assemble: c=%d\n",c);
2756 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2757 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2759 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2761 // could be FIFO, must perform the read
2763 assem_debug("(forced read)\n");
2764 tl=get_reg(i_regs->regmap,-1);
2768 if(offset||s<0||c) addr=tl;
2774 if(th>=0) reglist&=~(1<<th);
2777 //#define R29_HACK 1
2779 // Strmnnrmn's speed hack
2780 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2783 emit_cmpimm(addr,RAM_SIZE);
2785 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
2786 // Hint to branch predictor that the branch is unlikely to be taken
2788 emit_jno_unlikely(0);
2796 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2797 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2798 map=get_reg(i_regs->regmap,TLREG);
2800 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2801 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2803 if (opcode[i]==0x20) { // LB
2805 #ifdef HOST_IMM_ADDR32
2807 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2811 //emit_xorimm(addr,3,tl);
2812 //gen_tlb_addr_r(tl,map);
2813 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2815 #ifdef BIG_ENDIAN_MIPS
2816 if(!c) emit_xorimm(addr,3,tl);
2817 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2819 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2820 else if (tl!=addr) emit_mov(addr,tl);
2822 emit_movsbl_indexed_tlb(x,tl,map,tl);
2825 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2828 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2830 if (opcode[i]==0x21) { // LH
2832 #ifdef HOST_IMM_ADDR32
2834 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2839 #ifdef BIG_ENDIAN_MIPS
2840 if(!c) emit_xorimm(addr,2,tl);
2841 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2843 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2844 else if (tl!=addr) emit_mov(addr,tl);
2847 //emit_movswl_indexed_tlb(x,tl,map,tl);
2850 gen_tlb_addr_r(tl,map);
2851 emit_movswl_indexed(x,tl,tl);
2853 emit_movswl_indexed((int)rdram-0x80000000+x,tl,tl);
2856 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2859 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2861 if (opcode[i]==0x23) { // LW
2863 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2864 #ifdef HOST_IMM_ADDR32
2866 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2869 emit_readword_indexed_tlb(0,addr,map,tl);
2871 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2874 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2876 if (opcode[i]==0x24) { // LBU
2878 #ifdef HOST_IMM_ADDR32
2880 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2884 //emit_xorimm(addr,3,tl);
2885 //gen_tlb_addr_r(tl,map);
2886 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2888 #ifdef BIG_ENDIAN_MIPS
2889 if(!c) emit_xorimm(addr,3,tl);
2890 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2892 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2893 else if (tl!=addr) emit_mov(addr,tl);
2895 emit_movzbl_indexed_tlb(x,tl,map,tl);
2898 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2901 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2903 if (opcode[i]==0x25) { // LHU
2905 #ifdef HOST_IMM_ADDR32
2907 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2912 #ifdef BIG_ENDIAN_MIPS
2913 if(!c) emit_xorimm(addr,2,tl);
2914 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2916 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
2917 else if (tl!=addr) emit_mov(addr,tl);
2920 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2923 gen_tlb_addr_r(tl,map);
2924 emit_movzwl_indexed(x,tl,tl);
2926 emit_movzwl_indexed((int)rdram-0x80000000+x,tl,tl);
2928 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2932 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2934 if (opcode[i]==0x27) { // LWU
2937 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2938 #ifdef HOST_IMM_ADDR32
2940 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2943 emit_readword_indexed_tlb(0,addr,map,tl);
2945 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2948 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2952 if (opcode[i]==0x37) { // LD
2954 //gen_tlb_addr_r(tl,map);
2955 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2956 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2957 #ifdef HOST_IMM_ADDR32
2959 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2962 emit_readdword_indexed_tlb(0,addr,map,th,tl);
2964 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2967 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2969 //emit_storereg(rt1[i],tl); // DEBUG
2971 //if(opcode[i]==0x23)
2972 //if(opcode[i]==0x24)
2973 //if(opcode[i]==0x23||opcode[i]==0x24)
2974 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
2978 emit_readword((int)&last_count,ECX);
2980 if(get_reg(i_regs->regmap,CCREG)<0)
2981 emit_loadreg(CCREG,HOST_CCREG);
2982 emit_add(HOST_CCREG,ECX,HOST_CCREG);
2983 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
2984 emit_writeword(HOST_CCREG,(int)&Count);
2987 if(get_reg(i_regs->regmap,CCREG)<0)
2988 emit_loadreg(CCREG,0);
2990 emit_mov(HOST_CCREG,0);
2992 emit_addimm(0,2*ccadj[i],0);
2993 emit_writeword(0,(int)&Count);
2995 emit_call((int)memdebug);
2997 restore_regs(0x100f);
3001 #ifndef loadlr_assemble
3002 void loadlr_assemble(int i,struct regstat *i_regs)
3004 printf("Need loadlr_assemble for this architecture.\n");
3009 void store_assemble(int i,struct regstat *i_regs)
3014 int jaddr=0,jaddr2,type;
3015 int memtarget=0,c=0;
3016 int agr=AGEN1+(i&1);
3018 th=get_reg(i_regs->regmap,rs2[i]|64);
3019 tl=get_reg(i_regs->regmap,rs2[i]);
3020 s=get_reg(i_regs->regmap,rs1[i]);
3021 temp=get_reg(i_regs->regmap,agr);
3022 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3025 c=(i_regs->wasconst>>s)&1;
3026 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3027 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3031 for(hr=0;hr<HOST_REGS;hr++) {
3032 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3034 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3035 if(offset||s<0||c) addr=temp;
3040 // Strmnnrmn's speed hack
3042 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3044 emit_cmpimm(addr,RAM_SIZE);
3045 #ifdef DESTRUCTIVE_SHIFT
3046 if(s==addr) emit_mov(s,temp);
3049 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3053 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3054 // Hint to branch predictor that the branch is unlikely to be taken
3056 emit_jno_unlikely(0);
3064 if (opcode[i]==0x28) x=3; // SB
3065 if (opcode[i]==0x29) x=2; // SH
3066 map=get_reg(i_regs->regmap,TLREG);
3068 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3069 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3072 if (opcode[i]==0x28) { // SB
3075 #ifdef BIG_ENDIAN_MIPS
3076 if(!c) emit_xorimm(addr,3,temp);
3077 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3079 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3080 else if (addr!=temp) emit_mov(addr,temp);
3082 //gen_tlb_addr_w(temp,map);
3083 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3084 emit_writebyte_indexed_tlb(tl,x,temp,map,temp);
3088 if (opcode[i]==0x29) { // SH
3091 #ifdef BIG_ENDIAN_MIPS
3092 if(!c) emit_xorimm(addr,2,temp);
3093 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3095 if(c) x=(constmap[i][s]+offset)-(constmap[i][s]+offset);
3096 else if (addr!=temp) emit_mov(addr,temp);
3099 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3102 gen_tlb_addr_w(temp,map);
3103 emit_writehword_indexed(tl,x,temp);
3105 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,temp);
3109 if (opcode[i]==0x2B) { // SW
3111 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3112 emit_writeword_indexed_tlb(tl,0,addr,map,temp);
3115 if (opcode[i]==0x3F) { // SD
3119 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3120 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3121 emit_writedword_indexed_tlb(th,tl,0,addr,map,temp);
3124 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3125 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3126 emit_writedword_indexed_tlb(tl,tl,0,addr,map,temp);
3131 if(!using_tlb&&(!c||memtarget))
3132 // addr could be a temp, make sure it survives STORE*_STUB
3135 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3136 } else if(!memtarget) {
3137 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3141 #ifdef DESTRUCTIVE_SHIFT
3142 // The x86 shift operation is 'destructive'; it overwrites the
3143 // source register, so we need to make a copy first and use that.
3146 #if defined(HOST_IMM8)
3147 int ir=get_reg(i_regs->regmap,INVCP);
3149 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3151 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3155 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3158 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3159 //if(opcode[i]==0x2B || opcode[i]==0x28)
3160 //if(opcode[i]==0x2B || opcode[i]==0x29)
3161 //if(opcode[i]==0x2B)
3162 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3166 emit_readword((int)&last_count,ECX);
3168 if(get_reg(i_regs->regmap,CCREG)<0)
3169 emit_loadreg(CCREG,HOST_CCREG);
3170 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3171 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3172 emit_writeword(HOST_CCREG,(int)&Count);
3175 if(get_reg(i_regs->regmap,CCREG)<0)
3176 emit_loadreg(CCREG,0);
3178 emit_mov(HOST_CCREG,0);
3180 emit_addimm(0,2*ccadj[i],0);
3181 emit_writeword(0,(int)&Count);
3183 emit_call((int)memdebug);
3185 restore_regs(0x100f);
3189 void storelr_assemble(int i,struct regstat *i_regs)
3196 int case1,case2,case3;
3197 int done0,done1,done2;
3199 int agr=AGEN1+(i&1);
3201 th=get_reg(i_regs->regmap,rs2[i]|64);
3202 tl=get_reg(i_regs->regmap,rs2[i]);
3203 s=get_reg(i_regs->regmap,rs1[i]);
3204 temp=get_reg(i_regs->regmap,agr);
3205 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3208 c=(i_regs->isconst>>s)&1;
3209 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3210 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3213 for(hr=0;hr<HOST_REGS;hr++) {
3214 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3220 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3221 if(!offset&&s!=temp) emit_mov(s,temp);
3227 if(!memtarget||!rs1[i]) {
3232 if((u_int)rdram!=0x80000000)
3233 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3235 int map=get_reg(i_regs->regmap,TLREG);
3237 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3238 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3239 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3240 if(!jaddr&&!memtarget) {
3244 gen_tlb_addr_w(temp,map);
3247 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3248 temp2=get_reg(i_regs->regmap,FTEMP);
3249 if(!rs2[i]) temp2=th=tl;
3252 #ifndef BIG_ENDIAN_MIPS
3253 emit_xorimm(temp,3,temp);
3255 emit_testimm(temp,2);
3258 emit_testimm(temp,1);
3262 if (opcode[i]==0x2A) { // SWL
3263 emit_writeword_indexed(tl,0,temp);
3265 if (opcode[i]==0x2E) { // SWR
3266 emit_writebyte_indexed(tl,3,temp);
3268 if (opcode[i]==0x2C) { // SDL
3269 emit_writeword_indexed(th,0,temp);
3270 if(rs2[i]) emit_mov(tl,temp2);
3272 if (opcode[i]==0x2D) { // SDR
3273 emit_writebyte_indexed(tl,3,temp);
3274 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3279 set_jump_target(case1,(int)out);
3280 if (opcode[i]==0x2A) { // SWL
3281 // Write 3 msb into three least significant bytes
3282 if(rs2[i]) emit_rorimm(tl,8,tl);
3283 emit_writehword_indexed(tl,-1,temp);
3284 if(rs2[i]) emit_rorimm(tl,16,tl);
3285 emit_writebyte_indexed(tl,1,temp);
3286 if(rs2[i]) emit_rorimm(tl,8,tl);
3288 if (opcode[i]==0x2E) { // SWR
3289 // Write two lsb into two most significant bytes
3290 emit_writehword_indexed(tl,1,temp);
3292 if (opcode[i]==0x2C) { // SDL
3293 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3294 // Write 3 msb into three least significant bytes
3295 if(rs2[i]) emit_rorimm(th,8,th);
3296 emit_writehword_indexed(th,-1,temp);
3297 if(rs2[i]) emit_rorimm(th,16,th);
3298 emit_writebyte_indexed(th,1,temp);
3299 if(rs2[i]) emit_rorimm(th,8,th);
3301 if (opcode[i]==0x2D) { // SDR
3302 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3303 // Write two lsb into two most significant bytes
3304 emit_writehword_indexed(tl,1,temp);
3309 set_jump_target(case2,(int)out);
3310 emit_testimm(temp,1);
3313 if (opcode[i]==0x2A) { // SWL
3314 // Write two msb into two least significant bytes
3315 if(rs2[i]) emit_rorimm(tl,16,tl);
3316 emit_writehword_indexed(tl,-2,temp);
3317 if(rs2[i]) emit_rorimm(tl,16,tl);
3319 if (opcode[i]==0x2E) { // SWR
3320 // Write 3 lsb into three most significant bytes
3321 emit_writebyte_indexed(tl,-1,temp);
3322 if(rs2[i]) emit_rorimm(tl,8,tl);
3323 emit_writehword_indexed(tl,0,temp);
3324 if(rs2[i]) emit_rorimm(tl,24,tl);
3326 if (opcode[i]==0x2C) { // SDL
3327 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3328 // Write two msb into two least significant bytes
3329 if(rs2[i]) emit_rorimm(th,16,th);
3330 emit_writehword_indexed(th,-2,temp);
3331 if(rs2[i]) emit_rorimm(th,16,th);
3333 if (opcode[i]==0x2D) { // SDR
3334 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3335 // Write 3 lsb into three most significant bytes
3336 emit_writebyte_indexed(tl,-1,temp);
3337 if(rs2[i]) emit_rorimm(tl,8,tl);
3338 emit_writehword_indexed(tl,0,temp);
3339 if(rs2[i]) emit_rorimm(tl,24,tl);
3344 set_jump_target(case3,(int)out);
3345 if (opcode[i]==0x2A) { // SWL
3346 // Write msb into least significant byte
3347 if(rs2[i]) emit_rorimm(tl,24,tl);
3348 emit_writebyte_indexed(tl,-3,temp);
3349 if(rs2[i]) emit_rorimm(tl,8,tl);
3351 if (opcode[i]==0x2E) { // SWR
3352 // Write entire word
3353 emit_writeword_indexed(tl,-3,temp);
3355 if (opcode[i]==0x2C) { // SDL
3356 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3357 // Write msb into least significant byte
3358 if(rs2[i]) emit_rorimm(th,24,th);
3359 emit_writebyte_indexed(th,-3,temp);
3360 if(rs2[i]) emit_rorimm(th,8,th);
3362 if (opcode[i]==0x2D) { // SDR
3363 if(rs2[i]) emit_mov(th,temp2);
3364 // Write entire word
3365 emit_writeword_indexed(tl,-3,temp);
3367 set_jump_target(done0,(int)out);
3368 set_jump_target(done1,(int)out);
3369 set_jump_target(done2,(int)out);
3370 if (opcode[i]==0x2C) { // SDL
3371 emit_testimm(temp,4);
3374 emit_andimm(temp,~3,temp);
3375 emit_writeword_indexed(temp2,4,temp);
3376 set_jump_target(done0,(int)out);
3378 if (opcode[i]==0x2D) { // SDR
3379 emit_testimm(temp,4);
3382 emit_andimm(temp,~3,temp);
3383 emit_writeword_indexed(temp2,-4,temp);
3384 set_jump_target(done0,(int)out);
3387 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3390 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3391 #if defined(HOST_IMM8)
3392 int ir=get_reg(i_regs->regmap,INVCP);
3394 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3396 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3400 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3404 //save_regs(0x100f);
3405 emit_readword((int)&last_count,ECX);
3406 if(get_reg(i_regs->regmap,CCREG)<0)
3407 emit_loadreg(CCREG,HOST_CCREG);
3408 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3409 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3410 emit_writeword(HOST_CCREG,(int)&Count);
3411 emit_call((int)memdebug);
3413 //restore_regs(0x100f);
3417 void c1ls_assemble(int i,struct regstat *i_regs)
3419 #ifndef DISABLE_COP1
3425 int jaddr,jaddr2=0,jaddr3,type;
3426 int agr=AGEN1+(i&1);
3428 th=get_reg(i_regs->regmap,FTEMP|64);
3429 tl=get_reg(i_regs->regmap,FTEMP);
3430 s=get_reg(i_regs->regmap,rs1[i]);
3431 temp=get_reg(i_regs->regmap,agr);
3432 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3437 for(hr=0;hr<HOST_REGS;hr++) {
3438 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3440 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3441 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3443 // Loads use a temporary register which we need to save
3446 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3450 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3451 //else c=(i_regs->wasconst>>s)&1;
3452 if(s>=0) c=(i_regs->wasconst>>s)&1;
3453 // Check cop1 unusable
3455 signed char rs=get_reg(i_regs->regmap,CSREG);
3457 emit_testimm(rs,0x20000000);
3460 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3463 if (opcode[i]==0x39) { // SWC1 (get float address)
3464 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3466 if (opcode[i]==0x3D) { // SDC1 (get double address)
3467 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3469 // Generate address + offset
3472 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3476 map=get_reg(i_regs->regmap,TLREG);
3478 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3479 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3481 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3482 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3485 if (opcode[i]==0x39) { // SWC1 (read float)
3486 emit_readword_indexed(0,tl,tl);
3488 if (opcode[i]==0x3D) { // SDC1 (read double)
3489 emit_readword_indexed(4,tl,th);
3490 emit_readword_indexed(0,tl,tl);
3492 if (opcode[i]==0x31) { // LWC1 (get target address)
3493 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3495 if (opcode[i]==0x35) { // LDC1 (get target address)
3496 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3503 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3505 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3507 #ifdef DESTRUCTIVE_SHIFT
3508 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3509 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3513 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3514 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3516 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3517 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3520 if (opcode[i]==0x31) { // LWC1
3521 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3522 //gen_tlb_addr_r(ar,map);
3523 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3524 #ifdef HOST_IMM_ADDR32
3525 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3528 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3531 if (opcode[i]==0x35) { // LDC1
3533 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3534 //gen_tlb_addr_r(ar,map);
3535 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3536 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3537 #ifdef HOST_IMM_ADDR32
3538 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3541 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3544 if (opcode[i]==0x39) { // SWC1
3545 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3546 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3549 if (opcode[i]==0x3D) { // SDC1
3551 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3552 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3553 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3557 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3558 #ifndef DESTRUCTIVE_SHIFT
3559 temp=offset||c||s<0?ar:s;
3561 #if defined(HOST_IMM8)
3562 int ir=get_reg(i_regs->regmap,INVCP);
3564 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3566 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3570 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3573 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3574 if (opcode[i]==0x31) { // LWC1 (write float)
3575 emit_writeword_indexed(tl,0,temp);
3577 if (opcode[i]==0x35) { // LDC1 (write double)
3578 emit_writeword_indexed(th,4,temp);
3579 emit_writeword_indexed(tl,0,temp);
3581 //if(opcode[i]==0x39)
3582 /*if(opcode[i]==0x39||opcode[i]==0x31)
3585 emit_readword((int)&last_count,ECX);
3586 if(get_reg(i_regs->regmap,CCREG)<0)
3587 emit_loadreg(CCREG,HOST_CCREG);
3588 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3589 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3590 emit_writeword(HOST_CCREG,(int)&Count);
3591 emit_call((int)memdebug);
3595 cop1_unusable(i, i_regs);
3599 void c2ls_assemble(int i,struct regstat *i_regs)
3604 int memtarget=0,c=0;
3605 int jaddr,jaddr2=0,jaddr3,type;
3606 int agr=AGEN1+(i&1);
3608 u_int copr=(source[i]>>16)&0x1f;
3609 s=get_reg(i_regs->regmap,rs1[i]);
3610 tl=get_reg(i_regs->regmap,FTEMP);
3616 for(hr=0;hr<HOST_REGS;hr++) {
3617 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3619 if(i_regs->regmap[HOST_CCREG]==CCREG)
3620 reglist&=~(1<<HOST_CCREG);
3623 if (opcode[i]==0x3a) { // SWC2
3624 ar=get_reg(i_regs->regmap,agr);
3625 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3630 if(s>=0) c=(i_regs->wasconst>>s)&1;
3631 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3632 if (!offset&&!c&&s>=0) ar=s;
3635 if (opcode[i]==0x3a) { // SWC2
3636 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3644 emit_jmp(0); // inline_readstub/inline_writestub?
3648 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3652 if (opcode[i]==0x32) { // LWC2
3653 #ifdef HOST_IMM_ADDR32
3654 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3657 emit_readword_indexed(0,ar,tl);
3659 if (opcode[i]==0x3a) { // SWC2
3660 #ifdef DESTRUCTIVE_SHIFT
3661 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3663 emit_writeword_indexed(tl,0,ar);
3667 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3668 if (opcode[i]==0x3a) { // SWC2
3669 #if defined(HOST_IMM8)
3670 int ir=get_reg(i_regs->regmap,INVCP);
3672 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3674 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3678 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3680 if (opcode[i]==0x32) { // LWC2
3681 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3685 #ifndef multdiv_assemble
3686 void multdiv_assemble(int i,struct regstat *i_regs)
3688 printf("Need multdiv_assemble for this architecture.\n");
3693 void mov_assemble(int i,struct regstat *i_regs)
3695 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3696 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3699 signed char sh,sl,th,tl;
3700 th=get_reg(i_regs->regmap,rt1[i]|64);
3701 tl=get_reg(i_regs->regmap,rt1[i]);
3704 sh=get_reg(i_regs->regmap,rs1[i]|64);
3705 sl=get_reg(i_regs->regmap,rs1[i]);
3706 if(sl>=0) emit_mov(sl,tl);
3707 else emit_loadreg(rs1[i],tl);
3709 if(sh>=0) emit_mov(sh,th);
3710 else emit_loadreg(rs1[i]|64,th);
3716 #ifndef fconv_assemble
3717 void fconv_assemble(int i,struct regstat *i_regs)
3719 printf("Need fconv_assemble for this architecture.\n");
3725 void float_assemble(int i,struct regstat *i_regs)
3727 printf("Need float_assemble for this architecture.\n");
3732 void syscall_assemble(int i,struct regstat *i_regs)
3734 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3735 assert(ccreg==HOST_CCREG);
3736 assert(!is_delayslot);
3737 emit_movimm(start+i*4,EAX); // Get PC
3738 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3739 emit_jmp((int)jump_syscall_hle); // XXX
3742 void hlecall_assemble(int i,struct regstat *i_regs)
3744 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3745 assert(ccreg==HOST_CCREG);
3746 assert(!is_delayslot);
3747 emit_movimm(start+i*4+4,0); // Get PC
3748 emit_movimm((int)psxHLEt[source[i]&7],1);
3749 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG); // XXX
3750 emit_jmp((int)jump_hlecall);
3753 void intcall_assemble(int i,struct regstat *i_regs)
3755 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3756 assert(ccreg==HOST_CCREG);
3757 assert(!is_delayslot);
3758 emit_movimm(start+i*4,0); // Get PC
3759 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*ccadj[i],HOST_CCREG);
3760 emit_jmp((int)jump_intcall);
3763 void ds_assemble(int i,struct regstat *i_regs)
3768 alu_assemble(i,i_regs);break;
3770 imm16_assemble(i,i_regs);break;
3772 shift_assemble(i,i_regs);break;
3774 shiftimm_assemble(i,i_regs);break;
3776 load_assemble(i,i_regs);break;
3778 loadlr_assemble(i,i_regs);break;
3780 store_assemble(i,i_regs);break;
3782 storelr_assemble(i,i_regs);break;
3784 cop0_assemble(i,i_regs);break;
3786 cop1_assemble(i,i_regs);break;
3788 c1ls_assemble(i,i_regs);break;
3790 cop2_assemble(i,i_regs);break;
3792 c2ls_assemble(i,i_regs);break;
3794 c2op_assemble(i,i_regs);break;
3796 fconv_assemble(i,i_regs);break;
3798 float_assemble(i,i_regs);break;
3800 fcomp_assemble(i,i_regs);break;
3802 multdiv_assemble(i,i_regs);break;
3804 mov_assemble(i,i_regs);break;
3814 printf("Jump in the delay slot. This is probably a bug.\n");
3819 // Is the branch target a valid internal jump?
3820 int internal_branch(uint64_t i_is32,int addr)
3822 if(addr&1) return 0; // Indirect (register) jump
3823 if(addr>=start && addr<start+slen*4-4)
3825 int t=(addr-start)>>2;
3826 // Delay slots are not valid branch targets
3827 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3828 // 64 -> 32 bit transition requires a recompile
3829 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3831 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3832 else printf("optimizable: yes\n");
3834 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3835 if(requires_32bit[t]&~i_is32) return 0;
3841 #ifndef wb_invalidate
3842 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3843 uint64_t u,uint64_t uu)
3846 for(hr=0;hr<HOST_REGS;hr++) {
3847 if(hr!=EXCLUDE_REG) {
3848 if(pre[hr]!=entry[hr]) {
3851 if(get_reg(entry,pre[hr])<0) {
3853 if(!((u>>pre[hr])&1)) {
3854 emit_storereg(pre[hr],hr);
3855 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3856 emit_sarimm(hr,31,hr);
3857 emit_storereg(pre[hr]|64,hr);
3861 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3862 emit_storereg(pre[hr],hr);
3871 // Move from one register to another (no writeback)
3872 for(hr=0;hr<HOST_REGS;hr++) {
3873 if(hr!=EXCLUDE_REG) {
3874 if(pre[hr]!=entry[hr]) {
3875 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3877 if((nr=get_reg(entry,pre[hr]))>=0) {
3887 // Load the specified registers
3888 // This only loads the registers given as arguments because
3889 // we don't want to load things that will be overwritten
3890 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3894 for(hr=0;hr<HOST_REGS;hr++) {
3895 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3896 if(entry[hr]!=regmap[hr]) {
3897 if(regmap[hr]==rs1||regmap[hr]==rs2)
3904 emit_loadreg(regmap[hr],hr);
3911 for(hr=0;hr<HOST_REGS;hr++) {
3912 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3913 if(entry[hr]!=regmap[hr]) {
3914 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3916 assert(regmap[hr]!=64);
3917 if((is32>>(regmap[hr]&63))&1) {
3918 int lr=get_reg(regmap,regmap[hr]-64);
3920 emit_sarimm(lr,31,hr);
3922 emit_loadreg(regmap[hr],hr);
3926 emit_loadreg(regmap[hr],hr);
3934 // Load registers prior to the start of a loop
3935 // so that they are not loaded within the loop
3936 static void loop_preload(signed char pre[],signed char entry[])
3939 for(hr=0;hr<HOST_REGS;hr++) {
3940 if(hr!=EXCLUDE_REG) {
3941 if(pre[hr]!=entry[hr]) {
3943 if(get_reg(pre,entry[hr])<0) {
3944 assem_debug("loop preload:\n");
3945 //printf("loop preload: %d\n",hr);
3949 else if(entry[hr]<TEMPREG)
3951 emit_loadreg(entry[hr],hr);
3953 else if(entry[hr]-64<TEMPREG)
3955 emit_loadreg(entry[hr],hr);
3964 // Generate address for load/store instruction
3965 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3966 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3968 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3970 int agr=AGEN1+(i&1);
3971 int mgr=MGEN1+(i&1);
3972 if(itype[i]==LOAD) {
3973 ra=get_reg(i_regs->regmap,rt1[i]);
3974 //if(rt1[i]) assert(ra>=0);
3976 if(itype[i]==LOADLR) {
3977 ra=get_reg(i_regs->regmap,FTEMP);
3979 if(itype[i]==STORE||itype[i]==STORELR) {
3980 ra=get_reg(i_regs->regmap,agr);
3981 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3983 if(itype[i]==C1LS||itype[i]==C2LS) {
3984 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3985 ra=get_reg(i_regs->regmap,FTEMP);
3986 else { // SWC1/SDC1/SWC2/SDC2
3987 ra=get_reg(i_regs->regmap,agr);
3988 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3991 int rs=get_reg(i_regs->regmap,rs1[i]);
3992 int rm=get_reg(i_regs->regmap,TLREG);
3995 int c=(i_regs->wasconst>>rs)&1;
3997 // Using r0 as a base address
3999 if(!entry||entry[rm]!=mgr) {
4000 generate_map_const(offset,rm);
4001 } // else did it in the previous cycle
4003 if(!entry||entry[ra]!=agr) {
4004 if (opcode[i]==0x22||opcode[i]==0x26) {
4005 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4006 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4007 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4009 emit_movimm(offset,ra);
4011 } // else did it in the previous cycle
4014 if(!entry||entry[ra]!=rs1[i])
4015 emit_loadreg(rs1[i],ra);
4016 //if(!entry||entry[ra]!=rs1[i])
4017 // printf("poor load scheduling!\n");
4021 if(!entry||entry[rm]!=mgr) {
4022 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4023 // Stores to memory go thru the mapper to detect self-modifying
4024 // code, loads don't.
4025 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4026 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4027 generate_map_const(constmap[i][rs]+offset,rm);
4029 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4030 generate_map_const(constmap[i][rs]+offset,rm);
4034 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4035 if(!entry||entry[ra]!=agr) {
4036 if (opcode[i]==0x22||opcode[i]==0x26) {
4037 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4038 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4039 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4041 #ifdef HOST_IMM_ADDR32
4042 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4043 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4045 emit_movimm(constmap[i][rs]+offset,ra);
4047 } // else did it in the previous cycle
4048 } // else load_consts already did it
4050 if(offset&&!c&&rs1[i]) {
4052 emit_addimm(rs,offset,ra);
4054 emit_addimm(ra,offset,ra);
4059 // Preload constants for next instruction
4060 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4062 #ifndef HOST_IMM_ADDR32
4064 agr=MGEN1+((i+1)&1);
4065 ra=get_reg(i_regs->regmap,agr);
4067 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4068 int offset=imm[i+1];
4069 int c=(regs[i+1].wasconst>>rs)&1;
4071 if(itype[i+1]==STORE||itype[i+1]==STORELR
4072 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4073 // Stores to memory go thru the mapper to detect self-modifying
4074 // code, loads don't.
4075 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4076 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4077 generate_map_const(constmap[i+1][rs]+offset,ra);
4079 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4080 generate_map_const(constmap[i+1][rs]+offset,ra);
4083 /*else if(rs1[i]==0) {
4084 generate_map_const(offset,ra);
4089 agr=AGEN1+((i+1)&1);
4090 ra=get_reg(i_regs->regmap,agr);
4092 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4093 int offset=imm[i+1];
4094 int c=(regs[i+1].wasconst>>rs)&1;
4095 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4096 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4097 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4098 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4099 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4101 #ifdef HOST_IMM_ADDR32
4102 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4103 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4105 emit_movimm(constmap[i+1][rs]+offset,ra);
4108 else if(rs1[i+1]==0) {
4109 // Using r0 as a base address
4110 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4111 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4112 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4113 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4115 emit_movimm(offset,ra);
4122 int get_final_value(int hr, int i, int *value)
4124 int reg=regs[i].regmap[hr];
4126 if(regs[i+1].regmap[hr]!=reg) break;
4127 if(!((regs[i+1].isconst>>hr)&1)) break;
4132 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4133 *value=constmap[i][hr];
4137 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4138 // Load in delay slot, out-of-order execution
4139 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4141 #ifdef HOST_IMM_ADDR32
4142 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4144 // Precompute load address
4145 *value=constmap[i][hr]+imm[i+2];
4149 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4151 #ifdef HOST_IMM_ADDR32
4152 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4154 // Precompute load address
4155 *value=constmap[i][hr]+imm[i+1];
4156 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4161 *value=constmap[i][hr];
4162 //printf("c=%x\n",(int)constmap[i][hr]);
4163 if(i==slen-1) return 1;
4165 return !((unneeded_reg[i+1]>>reg)&1);
4167 return !((unneeded_reg_upper[i+1]>>reg)&1);
4171 // Load registers with known constants
4172 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4176 for(hr=0;hr<HOST_REGS;hr++) {
4177 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4178 //if(entry[hr]!=regmap[hr]) {
4179 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4180 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4182 if(get_final_value(hr,i,&value)) {
4187 emit_movimm(value,hr);
4195 for(hr=0;hr<HOST_REGS;hr++) {
4196 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4197 //if(entry[hr]!=regmap[hr]) {
4198 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4199 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4200 if((is32>>(regmap[hr]&63))&1) {
4201 int lr=get_reg(regmap,regmap[hr]-64);
4203 emit_sarimm(lr,31,hr);
4208 if(get_final_value(hr,i,&value)) {
4213 emit_movimm(value,hr);
4222 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4226 for(hr=0;hr<HOST_REGS;hr++) {
4227 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4228 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4229 int value=constmap[i][hr];
4234 emit_movimm(value,hr);
4240 for(hr=0;hr<HOST_REGS;hr++) {
4241 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4242 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4243 if((is32>>(regmap[hr]&63))&1) {
4244 int lr=get_reg(regmap,regmap[hr]-64);
4246 emit_sarimm(lr,31,hr);
4250 int value=constmap[i][hr];
4255 emit_movimm(value,hr);
4263 // Write out all dirty registers (except cycle count)
4264 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4267 for(hr=0;hr<HOST_REGS;hr++) {
4268 if(hr!=EXCLUDE_REG) {
4269 if(i_regmap[hr]>0) {
4270 if(i_regmap[hr]!=CCREG) {
4271 if((i_dirty>>hr)&1) {
4272 if(i_regmap[hr]<64) {
4273 emit_storereg(i_regmap[hr],hr);
4275 if( ((i_is32>>i_regmap[hr])&1) ) {
4276 #ifdef DESTRUCTIVE_WRITEBACK
4277 emit_sarimm(hr,31,hr);
4278 emit_storereg(i_regmap[hr]|64,hr);
4280 emit_sarimm(hr,31,HOST_TEMPREG);
4281 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4286 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4287 emit_storereg(i_regmap[hr],hr);
4296 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4297 // This writes the registers not written by store_regs_bt
4298 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4301 int t=(addr-start)>>2;
4302 for(hr=0;hr<HOST_REGS;hr++) {
4303 if(hr!=EXCLUDE_REG) {
4304 if(i_regmap[hr]>0) {
4305 if(i_regmap[hr]!=CCREG) {
4306 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4307 if((i_dirty>>hr)&1) {
4308 if(i_regmap[hr]<64) {
4309 emit_storereg(i_regmap[hr],hr);
4311 if( ((i_is32>>i_regmap[hr])&1) ) {
4312 #ifdef DESTRUCTIVE_WRITEBACK
4313 emit_sarimm(hr,31,hr);
4314 emit_storereg(i_regmap[hr]|64,hr);
4316 emit_sarimm(hr,31,HOST_TEMPREG);
4317 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4322 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4323 emit_storereg(i_regmap[hr],hr);
4334 // Load all registers (except cycle count)
4335 void load_all_regs(signed char i_regmap[])
4338 for(hr=0;hr<HOST_REGS;hr++) {
4339 if(hr!=EXCLUDE_REG) {
4340 if(i_regmap[hr]==0) {
4344 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4346 emit_loadreg(i_regmap[hr],hr);
4352 // Load all current registers also needed by next instruction
4353 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4356 for(hr=0;hr<HOST_REGS;hr++) {
4357 if(hr!=EXCLUDE_REG) {
4358 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4359 if(i_regmap[hr]==0) {
4363 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG)
4365 emit_loadreg(i_regmap[hr],hr);
4372 // Load all regs, storing cycle count if necessary
4373 void load_regs_entry(int t)
4376 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER,HOST_CCREG);
4377 else if(ccadj[t]) emit_addimm(HOST_CCREG,-ccadj[t]*CLOCK_DIVIDER,HOST_CCREG);
4378 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4379 emit_storereg(CCREG,HOST_CCREG);
4382 for(hr=0;hr<HOST_REGS;hr++) {
4383 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4384 if(regs[t].regmap_entry[hr]==0) {
4387 else if(regs[t].regmap_entry[hr]!=CCREG)
4389 emit_loadreg(regs[t].regmap_entry[hr],hr);
4394 for(hr=0;hr<HOST_REGS;hr++) {
4395 if(regs[t].regmap_entry[hr]>=64) {
4396 assert(regs[t].regmap_entry[hr]!=64);
4397 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4398 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4400 emit_loadreg(regs[t].regmap_entry[hr],hr);
4404 emit_sarimm(lr,31,hr);
4409 emit_loadreg(regs[t].regmap_entry[hr],hr);
4415 // Store dirty registers prior to branch
4416 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4418 if(internal_branch(i_is32,addr))
4420 int t=(addr-start)>>2;
4422 for(hr=0;hr<HOST_REGS;hr++) {
4423 if(hr!=EXCLUDE_REG) {
4424 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4425 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4426 if((i_dirty>>hr)&1) {
4427 if(i_regmap[hr]<64) {
4428 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4429 emit_storereg(i_regmap[hr],hr);
4430 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4431 #ifdef DESTRUCTIVE_WRITEBACK
4432 emit_sarimm(hr,31,hr);
4433 emit_storereg(i_regmap[hr]|64,hr);
4435 emit_sarimm(hr,31,HOST_TEMPREG);
4436 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4441 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4442 emit_storereg(i_regmap[hr],hr);
4453 // Branch out of this block, write out all dirty regs
4454 wb_dirtys(i_regmap,i_is32,i_dirty);
4458 // Load all needed registers for branch target
4459 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4461 //if(addr>=start && addr<(start+slen*4))
4462 if(internal_branch(i_is32,addr))
4464 int t=(addr-start)>>2;
4466 // Store the cycle count before loading something else
4467 if(i_regmap[HOST_CCREG]!=CCREG) {
4468 assert(i_regmap[HOST_CCREG]==-1);
4470 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4471 emit_storereg(CCREG,HOST_CCREG);
4474 for(hr=0;hr<HOST_REGS;hr++) {
4475 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<64) {
4476 #ifdef DESTRUCTIVE_WRITEBACK
4477 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4479 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4481 if(regs[t].regmap_entry[hr]==0) {
4484 else if(regs[t].regmap_entry[hr]!=CCREG)
4486 emit_loadreg(regs[t].regmap_entry[hr],hr);
4492 for(hr=0;hr<HOST_REGS;hr++) {
4493 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64) {
4494 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4495 assert(regs[t].regmap_entry[hr]!=64);
4496 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4497 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4499 emit_loadreg(regs[t].regmap_entry[hr],hr);
4503 emit_sarimm(lr,31,hr);
4508 emit_loadreg(regs[t].regmap_entry[hr],hr);
4511 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4512 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4514 emit_sarimm(lr,31,hr);
4521 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4523 if(addr>=start && addr<start+slen*4-4)
4525 int t=(addr-start)>>2;
4527 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4528 for(hr=0;hr<HOST_REGS;hr++)
4532 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4534 if(regs[t].regmap_entry[hr]!=-1)
4543 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4548 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4553 else // Same register but is it 32-bit or dirty?
4556 if(!((regs[t].dirty>>hr)&1))
4560 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4562 //printf("%x: dirty no match\n",addr);
4567 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4569 //printf("%x: is32 no match\n",addr);
4575 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4576 if(requires_32bit[t]&~i_is32) return 0;
4577 // Delay slots are not valid branch targets
4578 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4579 // Delay slots require additional processing, so do not match
4580 if(is_ds[t]) return 0;
4585 for(hr=0;hr<HOST_REGS;hr++)
4591 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4605 // Used when a branch jumps into the delay slot of another branch
4606 void ds_assemble_entry(int i)
4608 int t=(ba[i]-start)>>2;
4609 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4610 assem_debug("Assemble delay slot at %x\n",ba[i]);
4611 assem_debug("<->\n");
4612 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4613 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4614 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4615 address_generation(t,®s[t],regs[t].regmap_entry);
4616 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4617 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4622 alu_assemble(t,®s[t]);break;
4624 imm16_assemble(t,®s[t]);break;
4626 shift_assemble(t,®s[t]);break;
4628 shiftimm_assemble(t,®s[t]);break;
4630 load_assemble(t,®s[t]);break;
4632 loadlr_assemble(t,®s[t]);break;
4634 store_assemble(t,®s[t]);break;
4636 storelr_assemble(t,®s[t]);break;
4638 cop0_assemble(t,®s[t]);break;
4640 cop1_assemble(t,®s[t]);break;
4642 c1ls_assemble(t,®s[t]);break;
4644 cop2_assemble(t,®s[t]);break;
4646 c2ls_assemble(t,®s[t]);break;
4648 c2op_assemble(t,®s[t]);break;
4650 fconv_assemble(t,®s[t]);break;
4652 float_assemble(t,®s[t]);break;
4654 fcomp_assemble(t,®s[t]);break;
4656 multdiv_assemble(t,®s[t]);break;
4658 mov_assemble(t,®s[t]);break;
4668 printf("Jump in the delay slot. This is probably a bug.\n");
4670 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4671 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4672 if(internal_branch(regs[t].is32,ba[i]+4))
4673 assem_debug("branch: internal\n");
4675 assem_debug("branch: external\n");
4676 assert(internal_branch(regs[t].is32,ba[i]+4));
4677 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4681 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4690 //if(ba[i]>=start && ba[i]<(start+slen*4))
4691 if(internal_branch(branch_regs[i].is32,ba[i]))
4693 int t=(ba[i]-start)>>2;
4694 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4702 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4704 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4706 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4707 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4711 else if(*adj==0||invert) {
4712 emit_addimm_and_set_flags(CLOCK_DIVIDER*(count+2),HOST_CCREG);
4718 emit_cmpimm(HOST_CCREG,-2*(count+2));
4722 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4725 void do_ccstub(int n)
4728 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4729 set_jump_target(stubs[n][1],(int)out);
4731 if(stubs[n][6]==NULLDS) {
4732 // Delay slot instruction is nullified ("likely" branch)
4733 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4735 else if(stubs[n][6]!=TAKEN) {
4736 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4739 if(internal_branch(branch_regs[i].is32,ba[i]))
4740 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4744 // Save PC as return address
4745 emit_movimm(stubs[n][5],EAX);
4746 emit_writeword(EAX,(int)&pcaddr);
4750 // Return address depends on which way the branch goes
4751 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4753 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4754 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4755 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4756 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4766 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4770 #ifdef DESTRUCTIVE_WRITEBACK
4772 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4773 emit_loadreg(rs1[i],s1l);
4776 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4777 emit_loadreg(rs2[i],s1l);
4780 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4781 emit_loadreg(rs2[i],s2l);
4784 int addr,alt,ntaddr;
4787 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4788 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4789 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4797 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4798 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4799 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4805 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4809 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4810 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4811 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4817 assert(hr<HOST_REGS);
4819 if((opcode[i]&0x2f)==4) // BEQ
4821 #ifdef HAVE_CMOV_IMM
4823 if(s2l>=0) emit_cmp(s1l,s2l);
4824 else emit_test(s1l,s1l);
4825 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4830 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4832 if(s2h>=0) emit_cmp(s1h,s2h);
4833 else emit_test(s1h,s1h);
4834 emit_cmovne_reg(alt,addr);
4836 if(s2l>=0) emit_cmp(s1l,s2l);
4837 else emit_test(s1l,s1l);
4838 emit_cmovne_reg(alt,addr);
4841 if((opcode[i]&0x2f)==5) // BNE
4843 #ifdef HAVE_CMOV_IMM
4845 if(s2l>=0) emit_cmp(s1l,s2l);
4846 else emit_test(s1l,s1l);
4847 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4852 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4854 if(s2h>=0) emit_cmp(s1h,s2h);
4855 else emit_test(s1h,s1h);
4856 emit_cmovne_reg(alt,addr);
4858 if(s2l>=0) emit_cmp(s1l,s2l);
4859 else emit_test(s1l,s1l);
4860 emit_cmovne_reg(alt,addr);
4863 if((opcode[i]&0x2f)==6) // BLEZ
4865 //emit_movimm(ba[i],alt);
4866 //emit_movimm(start+i*4+8,addr);
4867 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4869 if(s1h>=0) emit_mov(addr,ntaddr);
4870 emit_cmovl_reg(alt,addr);
4873 emit_cmovne_reg(ntaddr,addr);
4874 emit_cmovs_reg(alt,addr);
4877 if((opcode[i]&0x2f)==7) // BGTZ
4879 //emit_movimm(ba[i],addr);
4880 //emit_movimm(start+i*4+8,ntaddr);
4881 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4883 if(s1h>=0) emit_mov(addr,alt);
4884 emit_cmovl_reg(ntaddr,addr);
4887 emit_cmovne_reg(alt,addr);
4888 emit_cmovs_reg(ntaddr,addr);
4891 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4893 //emit_movimm(ba[i],alt);
4894 //emit_movimm(start+i*4+8,addr);
4895 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4896 if(s1h>=0) emit_test(s1h,s1h);
4897 else emit_test(s1l,s1l);
4898 emit_cmovs_reg(alt,addr);
4900 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4902 //emit_movimm(ba[i],addr);
4903 //emit_movimm(start+i*4+8,alt);
4904 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4905 if(s1h>=0) emit_test(s1h,s1h);
4906 else emit_test(s1l,s1l);
4907 emit_cmovs_reg(alt,addr);
4909 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4910 if(source[i]&0x10000) // BC1T
4912 //emit_movimm(ba[i],alt);
4913 //emit_movimm(start+i*4+8,addr);
4914 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4915 emit_testimm(s1l,0x800000);
4916 emit_cmovne_reg(alt,addr);
4920 //emit_movimm(ba[i],addr);
4921 //emit_movimm(start+i*4+8,alt);
4922 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4923 emit_testimm(s1l,0x800000);
4924 emit_cmovne_reg(alt,addr);
4927 emit_writeword(addr,(int)&pcaddr);
4932 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4933 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4934 r=get_reg(branch_regs[i].regmap,RTEMP);
4936 emit_writeword(r,(int)&pcaddr);
4938 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
4940 // Update cycle count
4941 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4942 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4943 emit_call((int)cc_interrupt);
4944 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_DIVIDER*stubs[n][3],HOST_CCREG);
4945 if(stubs[n][6]==TAKEN) {
4946 if(internal_branch(branch_regs[i].is32,ba[i]))
4947 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4948 else if(itype[i]==RJUMP) {
4949 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4950 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4952 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4954 }else if(stubs[n][6]==NOTTAKEN) {
4955 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4956 else load_all_regs(branch_regs[i].regmap);
4957 }else if(stubs[n][6]==NULLDS) {
4958 // Delay slot instruction is nullified ("likely" branch)
4959 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4960 else load_all_regs(regs[i].regmap);
4962 load_all_regs(branch_regs[i].regmap);
4964 emit_jmp(stubs[n][2]); // return address
4966 /* This works but uses a lot of memory...
4967 emit_readword((int)&last_count,ECX);
4968 emit_add(HOST_CCREG,ECX,EAX);
4969 emit_writeword(EAX,(int)&Count);
4970 emit_call((int)gen_interupt);
4971 emit_readword((int)&Count,HOST_CCREG);
4972 emit_readword((int)&next_interupt,EAX);
4973 emit_readword((int)&pending_exception,EBX);
4974 emit_writeword(EAX,(int)&last_count);
4975 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
4977 int jne_instr=(int)out;
4979 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
4980 load_all_regs(branch_regs[i].regmap);
4981 emit_jmp(stubs[n][2]); // return address
4982 set_jump_target(jne_instr,(int)out);
4983 emit_readword((int)&pcaddr,EAX);
4984 // Call get_addr_ht instead of doing the hash table here.
4985 // This code is executed infrequently and takes up a lot of space
4986 // so smaller is better.
4987 emit_storereg(CCREG,HOST_CCREG);
4989 emit_call((int)get_addr_ht);
4990 emit_loadreg(CCREG,HOST_CCREG);
4991 emit_addimm(ESP,4,ESP);
4995 add_to_linker(int addr,int target,int ext)
4997 link_addr[linkcount][0]=addr;
4998 link_addr[linkcount][1]=target;
4999 link_addr[linkcount][2]=ext;
5003 void ujump_assemble(int i,struct regstat *i_regs)
5005 signed char *i_regmap=i_regs->regmap;
5006 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5007 address_generation(i+1,i_regs,regs[i].regmap_entry);
5009 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5010 if(rt1[i]==31&&temp>=0)
5012 int return_address=start+i*4+8;
5013 if(get_reg(branch_regs[i].regmap,31)>0)
5014 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5017 ds_assemble(i+1,i_regs);
5018 uint64_t bc_unneeded=branch_regs[i].u;
5019 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5020 bc_unneeded|=1|(1LL<<rt1[i]);
5021 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5022 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5023 bc_unneeded,bc_unneeded_upper);
5024 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5027 unsigned int return_address;
5028 assert(rt1[i+1]!=31);
5029 assert(rt2[i+1]!=31);
5030 rt=get_reg(branch_regs[i].regmap,31);
5031 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5033 return_address=start+i*4+8;
5036 if(internal_branch(branch_regs[i].is32,return_address)) {
5038 if(temp==EXCLUDE_REG||temp>=HOST_REGS||
5039 branch_regs[i].regmap[temp]>=0)
5041 temp=get_reg(branch_regs[i].regmap,-1);
5044 if(temp<0) temp=HOST_TEMPREG;
5046 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5047 else emit_movimm(return_address,rt);
5055 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5058 emit_movimm(return_address,rt); // PC into link register
5060 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5066 cc=get_reg(branch_regs[i].regmap,CCREG);
5067 assert(cc==HOST_CCREG);
5068 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5070 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5072 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5073 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5074 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5075 if(internal_branch(branch_regs[i].is32,ba[i]))
5076 assem_debug("branch: internal\n");
5078 assem_debug("branch: external\n");
5079 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5080 ds_assemble_entry(i);
5083 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5088 void rjump_assemble(int i,struct regstat *i_regs)
5090 signed char *i_regmap=i_regs->regmap;
5093 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5095 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5096 // Delay slot abuse, make a copy of the branch address register
5097 temp=get_reg(branch_regs[i].regmap,RTEMP);
5099 assert(regs[i].regmap[temp]==RTEMP);
5103 address_generation(i+1,i_regs,regs[i].regmap_entry);
5107 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5108 int return_address=start+i*4+8;
5109 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5115 int rh=get_reg(regs[i].regmap,RHASH);
5116 if(rh>=0) do_preload_rhash(rh);
5119 ds_assemble(i+1,i_regs);
5120 uint64_t bc_unneeded=branch_regs[i].u;
5121 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5122 bc_unneeded|=1|(1LL<<rt1[i]);
5123 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5124 bc_unneeded&=~(1LL<<rs1[i]);
5125 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5126 bc_unneeded,bc_unneeded_upper);
5127 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5129 int rt,return_address;
5130 assert(rt1[i+1]!=rt1[i]);
5131 assert(rt2[i+1]!=rt1[i]);
5132 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5133 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5135 return_address=start+i*4+8;
5139 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5142 emit_movimm(return_address,rt); // PC into link register
5144 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5147 cc=get_reg(branch_regs[i].regmap,CCREG);
5148 assert(cc==HOST_CCREG);
5150 int rh=get_reg(branch_regs[i].regmap,RHASH);
5151 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5153 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5154 do_preload_rhtbl(ht);
5158 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5159 #ifdef DESTRUCTIVE_WRITEBACK
5160 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5161 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5162 emit_loadreg(rs1[i],rs);
5167 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5171 do_miniht_load(ht,rh);
5174 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5175 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5177 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5178 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5180 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5183 do_miniht_jump(rs,rh,ht);
5188 //if(rs!=EAX) emit_mov(rs,EAX);
5189 //emit_jmp((int)jump_vaddr_eax);
5190 emit_jmp(jump_vaddr_reg[rs]);
5195 emit_shrimm(rs,16,rs);
5196 emit_xor(temp,rs,rs);
5197 emit_movzwl_reg(rs,rs);
5198 emit_shlimm(rs,4,rs);
5199 emit_cmpmem_indexed((int)hash_table,rs,temp);
5200 emit_jne((int)out+14);
5201 emit_readword_indexed((int)hash_table+4,rs,rs);
5203 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5204 emit_addimm_no_flags(8,rs);
5205 emit_jeq((int)out-17);
5206 // No hit on hash table, call compiler
5209 #ifdef DEBUG_CYCLE_COUNT
5210 emit_readword((int)&last_count,ECX);
5211 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5212 emit_readword((int)&next_interupt,ECX);
5213 emit_writeword(HOST_CCREG,(int)&Count);
5214 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5215 emit_writeword(ECX,(int)&last_count);
5218 emit_storereg(CCREG,HOST_CCREG);
5219 emit_call((int)get_addr);
5220 emit_loadreg(CCREG,HOST_CCREG);
5221 emit_addimm(ESP,4,ESP);
5223 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5224 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5228 void cjump_assemble(int i,struct regstat *i_regs)
5230 signed char *i_regmap=i_regs->regmap;
5233 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5234 assem_debug("match=%d\n",match);
5235 int s1h,s1l,s2h,s2l;
5236 int prev_cop1_usable=cop1_usable;
5237 int unconditional=0,nop=0;
5241 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5242 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5243 if(likely[i]) ooo=0;
5244 if(!match) invert=1;
5245 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5246 if(i>(ba[i]-start)>>2) invert=1;
5250 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
5251 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1])))
5253 // Write-after-read dependency prevents out of order execution
5254 // First test branch condition, then execute delay slot, then branch
5259 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5260 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5261 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5262 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5265 s1l=get_reg(i_regmap,rs1[i]);
5266 s1h=get_reg(i_regmap,rs1[i]|64);
5267 s2l=get_reg(i_regmap,rs2[i]);
5268 s2h=get_reg(i_regmap,rs2[i]|64);
5270 if(rs1[i]==0&&rs2[i]==0)
5272 if(opcode[i]&1) nop=1;
5273 else unconditional=1;
5274 //assert(opcode[i]!=5);
5275 //assert(opcode[i]!=7);
5276 //assert(opcode[i]!=0x15);
5277 //assert(opcode[i]!=0x17);
5283 only32=(regs[i].was32>>rs2[i])&1;
5288 only32=(regs[i].was32>>rs1[i])&1;
5291 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5295 // Out of order execution (delay slot first)
5297 address_generation(i+1,i_regs,regs[i].regmap_entry);
5298 ds_assemble(i+1,i_regs);
5300 uint64_t bc_unneeded=branch_regs[i].u;
5301 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5302 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5303 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5305 bc_unneeded_upper|=1;
5306 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5307 bc_unneeded,bc_unneeded_upper);
5308 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5309 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5310 cc=get_reg(branch_regs[i].regmap,CCREG);
5311 assert(cc==HOST_CCREG);
5313 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5314 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5315 //assem_debug("cycle count (adj)\n");
5317 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5318 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5319 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5320 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5322 assem_debug("branch: internal\n");
5324 assem_debug("branch: external\n");
5325 if(internal&&is_ds[(ba[i]-start)>>2]) {
5326 ds_assemble_entry(i);
5329 add_to_linker((int)out,ba[i],internal);
5332 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5333 if(((u_int)out)&7) emit_addnop(0);
5338 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5341 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5344 int taken=0,nottaken=0,nottaken1=0;
5345 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5346 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5350 if(opcode[i]==4) // BEQ
5352 if(s2h>=0) emit_cmp(s1h,s2h);
5353 else emit_test(s1h,s1h);
5357 if(opcode[i]==5) // BNE
5359 if(s2h>=0) emit_cmp(s1h,s2h);
5360 else emit_test(s1h,s1h);
5361 if(invert) taken=(int)out;
5362 else add_to_linker((int)out,ba[i],internal);
5365 if(opcode[i]==6) // BLEZ
5368 if(invert) taken=(int)out;
5369 else add_to_linker((int)out,ba[i],internal);
5374 if(opcode[i]==7) // BGTZ
5379 if(invert) taken=(int)out;
5380 else add_to_linker((int)out,ba[i],internal);
5385 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5387 if(opcode[i]==4) // BEQ
5389 if(s2l>=0) emit_cmp(s1l,s2l);
5390 else emit_test(s1l,s1l);
5395 add_to_linker((int)out,ba[i],internal);
5399 if(opcode[i]==5) // BNE
5401 if(s2l>=0) emit_cmp(s1l,s2l);
5402 else emit_test(s1l,s1l);
5407 add_to_linker((int)out,ba[i],internal);
5411 if(opcode[i]==6) // BLEZ
5418 add_to_linker((int)out,ba[i],internal);
5422 if(opcode[i]==7) // BGTZ
5429 add_to_linker((int)out,ba[i],internal);
5434 if(taken) set_jump_target(taken,(int)out);
5435 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5436 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5438 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5439 add_to_linker((int)out,ba[i],internal);
5442 add_to_linker((int)out,ba[i],internal*2);
5448 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5449 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5450 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5452 assem_debug("branch: internal\n");
5454 assem_debug("branch: external\n");
5455 if(internal&&is_ds[(ba[i]-start)>>2]) {
5456 ds_assemble_entry(i);
5459 add_to_linker((int)out,ba[i],internal);
5463 set_jump_target(nottaken,(int)out);
5466 if(nottaken1) set_jump_target(nottaken1,(int)out);
5468 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5470 } // (!unconditional)
5474 // In-order execution (branch first)
5475 //if(likely[i]) printf("IOL\n");
5478 int taken=0,nottaken=0,nottaken1=0;
5479 if(!unconditional&&!nop) {
5483 if((opcode[i]&0x2f)==4) // BEQ
5485 if(s2h>=0) emit_cmp(s1h,s2h);
5486 else emit_test(s1h,s1h);
5490 if((opcode[i]&0x2f)==5) // BNE
5492 if(s2h>=0) emit_cmp(s1h,s2h);
5493 else emit_test(s1h,s1h);
5497 if((opcode[i]&0x2f)==6) // BLEZ
5505 if((opcode[i]&0x2f)==7) // BGTZ
5515 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5517 if((opcode[i]&0x2f)==4) // BEQ
5519 if(s2l>=0) emit_cmp(s1l,s2l);
5520 else emit_test(s1l,s1l);
5524 if((opcode[i]&0x2f)==5) // BNE
5526 if(s2l>=0) emit_cmp(s1l,s2l);
5527 else emit_test(s1l,s1l);
5531 if((opcode[i]&0x2f)==6) // BLEZ
5537 if((opcode[i]&0x2f)==7) // BGTZ
5543 } // if(!unconditional)
5545 uint64_t ds_unneeded=branch_regs[i].u;
5546 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5547 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5548 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5549 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5551 ds_unneeded_upper|=1;
5554 if(taken) set_jump_target(taken,(int)out);
5555 assem_debug("1:\n");
5556 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5557 ds_unneeded,ds_unneeded_upper);
5559 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5560 address_generation(i+1,&branch_regs[i],0);
5561 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5562 ds_assemble(i+1,&branch_regs[i]);
5563 cc=get_reg(branch_regs[i].regmap,CCREG);
5565 emit_loadreg(CCREG,cc=HOST_CCREG);
5566 // CHECK: Is the following instruction (fall thru) allocated ok?
5568 assert(cc==HOST_CCREG);
5569 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5570 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5571 assem_debug("cycle count (adj)\n");
5572 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5573 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5575 assem_debug("branch: internal\n");
5577 assem_debug("branch: external\n");
5578 if(internal&&is_ds[(ba[i]-start)>>2]) {
5579 ds_assemble_entry(i);
5582 add_to_linker((int)out,ba[i],internal);
5587 cop1_usable=prev_cop1_usable;
5588 if(!unconditional) {
5589 if(nottaken1) set_jump_target(nottaken1,(int)out);
5590 set_jump_target(nottaken,(int)out);
5591 assem_debug("2:\n");
5593 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5594 ds_unneeded,ds_unneeded_upper);
5595 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5596 address_generation(i+1,&branch_regs[i],0);
5597 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5598 ds_assemble(i+1,&branch_regs[i]);
5600 cc=get_reg(branch_regs[i].regmap,CCREG);
5601 if(cc==-1&&!likely[i]) {
5602 // Cycle count isn't in a register, temporarily load it then write it out
5603 emit_loadreg(CCREG,HOST_CCREG);
5604 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5607 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5608 emit_storereg(CCREG,HOST_CCREG);
5611 cc=get_reg(i_regmap,CCREG);
5612 assert(cc==HOST_CCREG);
5613 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5616 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5622 void sjump_assemble(int i,struct regstat *i_regs)
5624 signed char *i_regmap=i_regs->regmap;
5627 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5628 assem_debug("smatch=%d\n",match);
5630 int prev_cop1_usable=cop1_usable;
5631 int unconditional=0,nevertaken=0;
5635 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5636 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5637 if(likely[i]) ooo=0;
5638 if(!match) invert=1;
5639 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5640 if(i>(ba[i]-start)>>2) invert=1;
5643 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5644 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5647 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))
5649 // Write-after-read dependency prevents out of order execution
5650 // First test branch condition, then execute delay slot, then branch
5653 assert(opcode2[i]<0x10||ooo); // FIXME (BxxZALL)
5656 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5657 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5660 s1l=get_reg(i_regmap,rs1[i]);
5661 s1h=get_reg(i_regmap,rs1[i]|64);
5665 if(opcode2[i]&1) unconditional=1;
5667 // These are never taken (r0 is never less than zero)
5668 //assert(opcode2[i]!=0);
5669 //assert(opcode2[i]!=2);
5670 //assert(opcode2[i]!=0x10);
5671 //assert(opcode2[i]!=0x12);
5674 only32=(regs[i].was32>>rs1[i])&1;
5678 // Out of order execution (delay slot first)
5680 address_generation(i+1,i_regs,regs[i].regmap_entry);
5681 ds_assemble(i+1,i_regs);
5683 uint64_t bc_unneeded=branch_regs[i].u;
5684 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5685 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5686 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5688 bc_unneeded_upper|=1;
5689 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5690 bc_unneeded,bc_unneeded_upper);
5691 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5692 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5694 int rt,return_address;
5695 assert(rt1[i+1]!=31);
5696 assert(rt2[i+1]!=31);
5697 rt=get_reg(branch_regs[i].regmap,31);
5698 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5700 // Save the PC even if the branch is not taken
5701 return_address=start+i*4+8;
5702 emit_movimm(return_address,rt); // PC into link register
5704 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5708 cc=get_reg(branch_regs[i].regmap,CCREG);
5709 assert(cc==HOST_CCREG);
5711 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5712 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5713 assem_debug("cycle count (adj)\n");
5715 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5716 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5717 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5718 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5720 assem_debug("branch: internal\n");
5722 assem_debug("branch: external\n");
5723 if(internal&&is_ds[(ba[i]-start)>>2]) {
5724 ds_assemble_entry(i);
5727 add_to_linker((int)out,ba[i],internal);
5730 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5731 if(((u_int)out)&7) emit_addnop(0);
5735 else if(nevertaken) {
5736 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5739 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5743 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5744 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5748 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5755 add_to_linker((int)out,ba[i],internal);
5759 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5766 add_to_linker((int)out,ba[i],internal);
5774 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5781 add_to_linker((int)out,ba[i],internal);
5785 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5792 add_to_linker((int)out,ba[i],internal);
5799 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5800 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5802 emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5803 add_to_linker((int)out,ba[i],internal);
5806 add_to_linker((int)out,ba[i],internal*2);
5812 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
5813 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5814 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5816 assem_debug("branch: internal\n");
5818 assem_debug("branch: external\n");
5819 if(internal&&is_ds[(ba[i]-start)>>2]) {
5820 ds_assemble_entry(i);
5823 add_to_linker((int)out,ba[i],internal);
5827 set_jump_target(nottaken,(int)out);
5831 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
5833 } // (!unconditional)
5837 // In-order execution (branch first)
5840 if(!unconditional) {
5841 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5845 if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5851 if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5861 if((opcode2[i]&0x1d)==0) // BLTZ/BLTZL
5867 if((opcode2[i]&0x1d)==1) // BGEZ/BGEZL
5874 } // if(!unconditional)
5876 uint64_t ds_unneeded=branch_regs[i].u;
5877 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5878 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5879 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5880 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5882 ds_unneeded_upper|=1;
5885 //assem_debug("1:\n");
5886 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5887 ds_unneeded,ds_unneeded_upper);
5889 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5890 address_generation(i+1,&branch_regs[i],0);
5891 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5892 ds_assemble(i+1,&branch_regs[i]);
5893 cc=get_reg(branch_regs[i].regmap,CCREG);
5895 emit_loadreg(CCREG,cc=HOST_CCREG);
5896 // CHECK: Is the following instruction (fall thru) allocated ok?
5898 assert(cc==HOST_CCREG);
5899 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5900 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5901 assem_debug("cycle count (adj)\n");
5902 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
5903 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5905 assem_debug("branch: internal\n");
5907 assem_debug("branch: external\n");
5908 if(internal&&is_ds[(ba[i]-start)>>2]) {
5909 ds_assemble_entry(i);
5912 add_to_linker((int)out,ba[i],internal);
5917 cop1_usable=prev_cop1_usable;
5918 if(!unconditional) {
5919 set_jump_target(nottaken,(int)out);
5920 assem_debug("1:\n");
5922 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5923 ds_unneeded,ds_unneeded_upper);
5924 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5925 address_generation(i+1,&branch_regs[i],0);
5926 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5927 ds_assemble(i+1,&branch_regs[i]);
5929 cc=get_reg(branch_regs[i].regmap,CCREG);
5930 if(cc==-1&&!likely[i]) {
5931 // Cycle count isn't in a register, temporarily load it then write it out
5932 emit_loadreg(CCREG,HOST_CCREG);
5933 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
5936 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5937 emit_storereg(CCREG,HOST_CCREG);
5940 cc=get_reg(i_regmap,CCREG);
5941 assert(cc==HOST_CCREG);
5942 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
5945 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5951 void fjump_assemble(int i,struct regstat *i_regs)
5953 signed char *i_regmap=i_regs->regmap;
5956 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5957 assem_debug("fmatch=%d\n",match);
5962 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5963 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5964 if(likely[i]) ooo=0;
5965 if(!match) invert=1;
5966 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5967 if(i>(ba[i]-start)>>2) invert=1;
5971 if(itype[i+1]==FCOMP)
5973 // Write-after-read dependency prevents out of order execution
5974 // First test branch condition, then execute delay slot, then branch
5979 fs=get_reg(branch_regs[i].regmap,FSREG);
5980 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5983 fs=get_reg(i_regmap,FSREG);
5986 // Check cop1 unusable
5988 cs=get_reg(i_regmap,CSREG);
5990 emit_testimm(cs,0x20000000);
5993 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
5998 // Out of order execution (delay slot first)
6000 ds_assemble(i+1,i_regs);
6002 uint64_t bc_unneeded=branch_regs[i].u;
6003 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6004 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6005 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6007 bc_unneeded_upper|=1;
6008 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6009 bc_unneeded,bc_unneeded_upper);
6010 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6011 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6012 cc=get_reg(branch_regs[i].regmap,CCREG);
6013 assert(cc==HOST_CCREG);
6014 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6015 assem_debug("cycle count (adj)\n");
6018 if(adj&&!invert) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6021 emit_testimm(fs,0x800000);
6022 if(source[i]&0x10000) // BC1T
6028 add_to_linker((int)out,ba[i],internal);
6037 add_to_linker((int)out,ba[i],internal);
6045 if(adj) emit_addimm(cc,-CLOCK_DIVIDER*adj,cc);
6046 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6047 else if(match) emit_addnop(13);
6049 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6050 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6052 assem_debug("branch: internal\n");
6054 assem_debug("branch: external\n");
6055 if(internal&&is_ds[(ba[i]-start)>>2]) {
6056 ds_assemble_entry(i);
6059 add_to_linker((int)out,ba[i],internal);
6062 set_jump_target(nottaken,(int)out);
6066 if(!invert) emit_addimm(cc,CLOCK_DIVIDER*adj,cc);
6068 } // (!unconditional)
6072 // In-order execution (branch first)
6076 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6079 emit_testimm(fs,0x800000);
6080 if(source[i]&0x10000) // BC1T
6091 } // if(!unconditional)
6093 uint64_t ds_unneeded=branch_regs[i].u;
6094 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6095 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6096 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6097 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6099 ds_unneeded_upper|=1;
6101 //assem_debug("1:\n");
6102 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6103 ds_unneeded,ds_unneeded_upper);
6105 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6106 address_generation(i+1,&branch_regs[i],0);
6107 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6108 ds_assemble(i+1,&branch_regs[i]);
6109 cc=get_reg(branch_regs[i].regmap,CCREG);
6111 emit_loadreg(CCREG,cc=HOST_CCREG);
6112 // CHECK: Is the following instruction (fall thru) allocated ok?
6114 assert(cc==HOST_CCREG);
6115 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6116 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6117 assem_debug("cycle count (adj)\n");
6118 if(adj) emit_addimm(cc,CLOCK_DIVIDER*(ccadj[i]+2-adj),cc);
6119 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6121 assem_debug("branch: internal\n");
6123 assem_debug("branch: external\n");
6124 if(internal&&is_ds[(ba[i]-start)>>2]) {
6125 ds_assemble_entry(i);
6128 add_to_linker((int)out,ba[i],internal);
6133 if(1) { // <- FIXME (don't need this)
6134 set_jump_target(nottaken,(int)out);
6135 assem_debug("1:\n");
6137 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6138 ds_unneeded,ds_unneeded_upper);
6139 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6140 address_generation(i+1,&branch_regs[i],0);
6141 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6142 ds_assemble(i+1,&branch_regs[i]);
6144 cc=get_reg(branch_regs[i].regmap,CCREG);
6145 if(cc==-1&&!likely[i]) {
6146 // Cycle count isn't in a register, temporarily load it then write it out
6147 emit_loadreg(CCREG,HOST_CCREG);
6148 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6151 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6152 emit_storereg(CCREG,HOST_CCREG);
6155 cc=get_reg(i_regmap,CCREG);
6156 assert(cc==HOST_CCREG);
6157 emit_addimm_and_set_flags(CLOCK_DIVIDER*(ccadj[i]+2),cc);
6160 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6166 static void pagespan_assemble(int i,struct regstat *i_regs)
6168 int s1l=get_reg(i_regs->regmap,rs1[i]);
6169 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6170 int s2l=get_reg(i_regs->regmap,rs2[i]);
6171 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6172 void *nt_branch=NULL;
6175 int unconditional=0;
6185 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6189 int addr,alt,ntaddr;
6190 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6194 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6195 (i_regs->regmap[hr]&63)!=rs1[i] &&
6196 (i_regs->regmap[hr]&63)!=rs2[i] )
6205 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6206 (i_regs->regmap[hr]&63)!=rs1[i] &&
6207 (i_regs->regmap[hr]&63)!=rs2[i] )
6213 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6217 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6218 (i_regs->regmap[hr]&63)!=rs1[i] &&
6219 (i_regs->regmap[hr]&63)!=rs2[i] )
6226 assert(hr<HOST_REGS);
6227 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6228 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6230 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i]+2),HOST_CCREG);
6231 if(opcode[i]==2) // J
6235 if(opcode[i]==3) // JAL
6238 int rt=get_reg(i_regs->regmap,31);
6239 emit_movimm(start+i*4+8,rt);
6242 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6245 if(opcode2[i]==9) // JALR
6247 int rt=get_reg(i_regs->regmap,rt1[i]);
6248 emit_movimm(start+i*4+8,rt);
6251 if((opcode[i]&0x3f)==4) // BEQ
6258 #ifdef HAVE_CMOV_IMM
6260 if(s2l>=0) emit_cmp(s1l,s2l);
6261 else emit_test(s1l,s1l);
6262 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6268 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6270 if(s2h>=0) emit_cmp(s1h,s2h);
6271 else emit_test(s1h,s1h);
6272 emit_cmovne_reg(alt,addr);
6274 if(s2l>=0) emit_cmp(s1l,s2l);
6275 else emit_test(s1l,s1l);
6276 emit_cmovne_reg(alt,addr);
6279 if((opcode[i]&0x3f)==5) // BNE
6281 #ifdef HAVE_CMOV_IMM
6283 if(s2l>=0) emit_cmp(s1l,s2l);
6284 else emit_test(s1l,s1l);
6285 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6291 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6293 if(s2h>=0) emit_cmp(s1h,s2h);
6294 else emit_test(s1h,s1h);
6295 emit_cmovne_reg(alt,addr);
6297 if(s2l>=0) emit_cmp(s1l,s2l);
6298 else emit_test(s1l,s1l);
6299 emit_cmovne_reg(alt,addr);
6302 if((opcode[i]&0x3f)==0x14) // BEQL
6305 if(s2h>=0) emit_cmp(s1h,s2h);
6306 else emit_test(s1h,s1h);
6310 if(s2l>=0) emit_cmp(s1l,s2l);
6311 else emit_test(s1l,s1l);
6312 if(nottaken) set_jump_target(nottaken,(int)out);
6316 if((opcode[i]&0x3f)==0x15) // BNEL
6319 if(s2h>=0) emit_cmp(s1h,s2h);
6320 else emit_test(s1h,s1h);
6324 if(s2l>=0) emit_cmp(s1l,s2l);
6325 else emit_test(s1l,s1l);
6328 if(taken) set_jump_target(taken,(int)out);
6330 if((opcode[i]&0x3f)==6) // BLEZ
6332 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6334 if(s1h>=0) emit_mov(addr,ntaddr);
6335 emit_cmovl_reg(alt,addr);
6338 emit_cmovne_reg(ntaddr,addr);
6339 emit_cmovs_reg(alt,addr);
6342 if((opcode[i]&0x3f)==7) // BGTZ
6344 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6346 if(s1h>=0) emit_mov(addr,alt);
6347 emit_cmovl_reg(ntaddr,addr);
6350 emit_cmovne_reg(alt,addr);
6351 emit_cmovs_reg(ntaddr,addr);
6354 if((opcode[i]&0x3f)==0x16) // BLEZL
6356 assert((opcode[i]&0x3f)!=0x16);
6358 if((opcode[i]&0x3f)==0x17) // BGTZL
6360 assert((opcode[i]&0x3f)!=0x17);
6362 assert(opcode[i]!=1); // BLTZ/BGEZ
6364 //FIXME: Check CSREG
6365 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6366 if((source[i]&0x30000)==0) // BC1F
6368 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6369 emit_testimm(s1l,0x800000);
6370 emit_cmovne_reg(alt,addr);
6372 if((source[i]&0x30000)==0x10000) // BC1T
6374 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6375 emit_testimm(s1l,0x800000);
6376 emit_cmovne_reg(alt,addr);
6378 if((source[i]&0x30000)==0x20000) // BC1FL
6380 emit_testimm(s1l,0x800000);
6384 if((source[i]&0x30000)==0x30000) // BC1TL
6386 emit_testimm(s1l,0x800000);
6392 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6393 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6394 if(likely[i]||unconditional)
6396 emit_movimm(ba[i],HOST_BTREG);
6398 else if(addr!=HOST_BTREG)
6400 emit_mov(addr,HOST_BTREG);
6402 void *branch_addr=out;
6404 int target_addr=start+i*4+5;
6406 void *compiled_target_addr=check_addr(target_addr);
6407 emit_extjump_ds((int)branch_addr,target_addr);
6408 if(compiled_target_addr) {
6409 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6410 add_link(target_addr,stub);
6412 else set_jump_target((int)branch_addr,(int)stub);
6415 set_jump_target((int)nottaken,(int)out);
6416 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6417 void *branch_addr=out;
6419 int target_addr=start+i*4+8;
6421 void *compiled_target_addr=check_addr(target_addr);
6422 emit_extjump_ds((int)branch_addr,target_addr);
6423 if(compiled_target_addr) {
6424 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6425 add_link(target_addr,stub);
6427 else set_jump_target((int)branch_addr,(int)stub);
6431 // Assemble the delay slot for the above
6432 static void pagespan_ds()
6434 assem_debug("initial delay slot:\n");
6435 u_int vaddr=start+1;
6436 u_int page=get_page(vaddr);
6437 u_int vpage=get_vpage(vaddr);
6438 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6440 ll_add(jump_in+page,vaddr,(void *)out);
6441 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6442 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6443 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6444 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6445 emit_writeword(HOST_BTREG,(int)&branch_target);
6446 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6447 address_generation(0,®s[0],regs[0].regmap_entry);
6448 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6449 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6454 alu_assemble(0,®s[0]);break;
6456 imm16_assemble(0,®s[0]);break;
6458 shift_assemble(0,®s[0]);break;
6460 shiftimm_assemble(0,®s[0]);break;
6462 load_assemble(0,®s[0]);break;
6464 loadlr_assemble(0,®s[0]);break;
6466 store_assemble(0,®s[0]);break;
6468 storelr_assemble(0,®s[0]);break;
6470 cop0_assemble(0,®s[0]);break;
6472 cop1_assemble(0,®s[0]);break;
6474 c1ls_assemble(0,®s[0]);break;
6476 cop2_assemble(0,®s[0]);break;
6478 c2ls_assemble(0,®s[0]);break;
6480 c2op_assemble(0,®s[0]);break;
6482 fconv_assemble(0,®s[0]);break;
6484 float_assemble(0,®s[0]);break;
6486 fcomp_assemble(0,®s[0]);break;
6488 multdiv_assemble(0,®s[0]);break;
6490 mov_assemble(0,®s[0]);break;
6500 printf("Jump in the delay slot. This is probably a bug.\n");
6502 int btaddr=get_reg(regs[0].regmap,BTREG);
6504 btaddr=get_reg(regs[0].regmap,-1);
6505 emit_readword((int)&branch_target,btaddr);
6507 assert(btaddr!=HOST_CCREG);
6508 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6510 emit_movimm(start+4,HOST_TEMPREG);
6511 emit_cmp(btaddr,HOST_TEMPREG);
6513 emit_cmpimm(btaddr,start+4);
6515 int branch=(int)out;
6517 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6518 emit_jmp(jump_vaddr_reg[btaddr]);
6519 set_jump_target(branch,(int)out);
6520 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6521 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6524 // Basic liveness analysis for MIPS registers
6525 void unneeded_registers(int istart,int iend,int r)
6529 uint64_t temp_u,temp_uu;
6534 u=unneeded_reg[iend+1];
6535 uu=unneeded_reg_upper[iend+1];
6538 for (i=iend;i>=istart;i--)
6540 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6541 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6543 // If subroutine call, flag return address as a possible branch target
6544 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6546 if(ba[i]<start || ba[i]>=(start+slen*4))
6548 // Branch out of this block, flush all regs
6552 if(itype[i]==UJUMP&&rt1[i]==31)
6554 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6556 if(itype[i]==RJUMP&&rs1[i]==31)
6558 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6560 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6561 if(itype[i]==UJUMP&&rt1[i]==31)
6563 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6564 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6566 if(itype[i]==RJUMP&&rs1[i]==31)
6568 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6569 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6572 branch_unneeded_reg[i]=u;
6573 branch_unneeded_reg_upper[i]=uu;
6574 // Merge in delay slot
6575 tdep=(~uu>>rt1[i+1])&1;
6576 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6577 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6578 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6579 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6580 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6582 // If branch is "likely" (and conditional)
6583 // then we skip the delay slot on the fall-thru path
6586 u&=unneeded_reg[i+2];
6587 uu&=unneeded_reg_upper[i+2];
6598 // Internal branch, flag target
6599 bt[(ba[i]-start)>>2]=1;
6600 if(ba[i]<=start+i*4) {
6602 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6604 // Unconditional branch
6607 // Conditional branch (not taken case)
6608 temp_u=unneeded_reg[i+2];
6609 temp_uu=unneeded_reg_upper[i+2];
6611 // Merge in delay slot
6612 tdep=(~temp_uu>>rt1[i+1])&1;
6613 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6614 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6615 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6616 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6617 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6618 temp_u|=1;temp_uu|=1;
6619 // If branch is "likely" (and conditional)
6620 // then we skip the delay slot on the fall-thru path
6623 temp_u&=unneeded_reg[i+2];
6624 temp_uu&=unneeded_reg_upper[i+2];
6632 tdep=(~temp_uu>>rt1[i])&1;
6633 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6634 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6635 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6636 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6637 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6638 temp_u|=1;temp_uu|=1;
6639 unneeded_reg[i]=temp_u;
6640 unneeded_reg_upper[i]=temp_uu;
6641 // Only go three levels deep. This recursion can take an
6642 // excessive amount of time if there are a lot of nested loops.
6644 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6646 unneeded_reg[(ba[i]-start)>>2]=1;
6647 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6650 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6652 // Unconditional branch
6653 u=unneeded_reg[(ba[i]-start)>>2];
6654 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6655 branch_unneeded_reg[i]=u;
6656 branch_unneeded_reg_upper[i]=uu;
6659 //branch_unneeded_reg[i]=u;
6660 //branch_unneeded_reg_upper[i]=uu;
6661 // Merge in delay slot
6662 tdep=(~uu>>rt1[i+1])&1;
6663 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6664 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6665 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6666 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6667 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6670 // Conditional branch
6671 b=unneeded_reg[(ba[i]-start)>>2];
6672 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6673 branch_unneeded_reg[i]=b;
6674 branch_unneeded_reg_upper[i]=bu;
6677 //branch_unneeded_reg[i]=b;
6678 //branch_unneeded_reg_upper[i]=bu;
6679 // Branch delay slot
6680 tdep=(~uu>>rt1[i+1])&1;
6681 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6682 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6683 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6684 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6685 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6687 // If branch is "likely" then we skip the
6688 // delay slot on the fall-thru path
6693 u&=unneeded_reg[i+2];
6694 uu&=unneeded_reg_upper[i+2];
6705 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6706 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6707 //branch_unneeded_reg[i]=1;
6708 //branch_unneeded_reg_upper[i]=1;
6710 branch_unneeded_reg[i]=1;
6711 branch_unneeded_reg_upper[i]=1;
6717 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6719 // SYSCALL instruction (software interrupt)
6723 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6725 // ERET instruction (return from interrupt)
6730 tdep=(~uu>>rt1[i])&1;
6731 // Written registers are unneeded
6736 // Accessed registers are needed
6741 // Source-target dependencies
6742 uu&=~(tdep<<dep1[i]);
6743 uu&=~(tdep<<dep2[i]);
6744 // R0 is always unneeded
6748 unneeded_reg_upper[i]=uu;
6750 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6753 for(r=1;r<=CCREG;r++) {
6754 if((unneeded_reg[i]>>r)&1) {
6755 if(r==HIREG) printf(" HI");
6756 else if(r==LOREG) printf(" LO");
6757 else printf(" r%d",r);
6761 for(r=1;r<=CCREG;r++) {
6762 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6763 if(r==HIREG) printf(" HI");
6764 else if(r==LOREG) printf(" LO");
6765 else printf(" r%d",r);
6771 for (i=iend;i>=istart;i--)
6773 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6778 // Identify registers which are likely to contain 32-bit values
6779 // This is used to predict whether any branches will jump to a
6780 // location with 64-bit values in registers.
6781 static void provisional_32bit()
6785 uint64_t lastbranch=1;
6790 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
6791 if(i>1) is32=lastbranch;
6797 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
6799 if(i>2) is32=lastbranch;
6803 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
6805 if(rs1[i-2]==0||rs2[i-2]==0)
6808 is32|=1LL<<rs1[i-2];
6811 is32|=1LL<<rs2[i-2];
6816 // If something jumps here with 64-bit values
6817 // then promote those registers to 64 bits
6820 uint64_t temp_is32=is32;
6823 if(ba[j]==start+i*4)
6824 //temp_is32&=branch_regs[j].is32;
6829 if(ba[j]==start+i*4)
6840 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
6841 // Branches don't write registers, consider the delay slot instead.
6852 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
6853 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
6862 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
6863 if(op==0x22) is32|=1LL<<rt; // LWL
6866 if (op==0x08||op==0x09|| // ADDI/ADDIU
6867 op==0x0a||op==0x0b|| // SLTI/SLTIU
6873 if(op==0x18||op==0x19) { // DADDI/DADDIU
6876 // is32|=((is32>>s1)&1LL)<<rt;
6878 if(op==0x0d||op==0x0e) { // ORI/XORI
6879 uint64_t sr=((is32>>s1)&1LL);
6895 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
6898 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
6901 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
6902 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
6906 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
6911 uint64_t sr=((is32>>s1)&1LL);
6916 uint64_t sr=((is32>>s2)&1LL);
6924 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
6929 uint64_t sr=((is32>>s1)&1LL);
6939 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
6940 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
6943 is32|=(1LL<<HIREG)|(1LL<<LOREG);
6948 uint64_t sr=((is32>>s1)&1LL);
6954 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
6955 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
6959 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
6960 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
6963 if(op2==0) is32|=1LL<<rt; // MFC0
6967 if(op2==0) is32|=1LL<<rt; // MFC1
6968 if(op2==1) is32&=~(1LL<<rt); // DMFC1
6969 if(op2==2) is32|=1LL<<rt; // CFC1
6991 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
6993 if(rt1[i-1]==31) // JAL/JALR
6995 // Subroutine call will return here, don't alloc any registers
7000 // Internal branch will jump here, match registers to caller
7008 // Identify registers which may be assumed to contain 32-bit values
7009 // and where optimizations will rely on this.
7010 // This is used to determine whether backward branches can safely
7011 // jump to a location with 64-bit values in registers.
7012 static void provisional_r32()
7017 for (i=slen-1;i>=0;i--)
7020 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7022 if(ba[i]<start || ba[i]>=(start+slen*4))
7024 // Branch out of this block, don't need anything
7030 // Need whatever matches the target
7031 // (and doesn't get overwritten by the delay slot instruction)
7033 int t=(ba[i]-start)>>2;
7034 if(ba[i]>start+i*4) {
7036 //if(!(requires_32bit[t]&~regs[i].was32))
7037 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7038 if(!(pr32[t]&~regs[i].was32))
7039 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7042 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7043 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7046 // Conditional branch may need registers for following instructions
7047 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7050 //r32|=requires_32bit[i+2];
7053 // Mark this address as a branch target since it may be called
7054 // upon return from interrupt
7058 // Merge in delay slot
7060 // These are overwritten unless the branch is "likely"
7061 // and the delay slot is nullified if not taken
7062 r32&=~(1LL<<rt1[i+1]);
7063 r32&=~(1LL<<rt2[i+1]);
7065 // Assume these are needed (delay slot)
7068 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7072 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7074 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7076 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7078 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7080 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7083 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7085 // SYSCALL instruction (software interrupt)
7088 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7090 // ERET instruction (return from interrupt)
7094 r32&=~(1LL<<rt1[i]);
7095 r32&=~(1LL<<rt2[i]);
7098 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7102 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7104 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7106 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7108 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7110 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7112 //requires_32bit[i]=r32;
7115 // Dirty registers which are 32-bit, require 32-bit input
7116 // as they will be written as 32-bit values
7117 for(hr=0;hr<HOST_REGS;hr++)
7119 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7120 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7121 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7122 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7123 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7130 // Write back dirty registers as soon as we will no longer modify them,
7131 // so that we don't end up with lots of writes at the branches.
7132 void clean_registers(int istart,int iend,int wr)
7136 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7137 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7139 will_dirty_i=will_dirty_next=0;
7140 wont_dirty_i=wont_dirty_next=0;
7142 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7143 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7145 for (i=iend;i>=istart;i--)
7147 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7149 if(ba[i]<start || ba[i]>=(start+slen*4))
7151 // Branch out of this block, flush all regs
7152 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7154 // Unconditional branch
7157 // Merge in delay slot (will dirty)
7158 for(r=0;r<HOST_REGS;r++) {
7159 if(r!=EXCLUDE_REG) {
7160 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7161 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7162 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7163 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7164 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7165 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7166 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7167 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7168 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7169 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7170 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7171 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7172 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7173 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7179 // Conditional branch
7181 wont_dirty_i=wont_dirty_next;
7182 // Merge in delay slot (will dirty)
7183 for(r=0;r<HOST_REGS;r++) {
7184 if(r!=EXCLUDE_REG) {
7186 // Might not dirty if likely branch is not taken
7187 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7188 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7189 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7190 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7191 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7192 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7193 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7194 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7195 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7196 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7197 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7198 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7199 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7200 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7205 // Merge in delay slot (wont dirty)
7206 for(r=0;r<HOST_REGS;r++) {
7207 if(r!=EXCLUDE_REG) {
7208 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7209 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7210 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7211 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7212 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7213 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7214 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7215 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7216 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7217 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7221 #ifndef DESTRUCTIVE_WRITEBACK
7222 branch_regs[i].dirty&=wont_dirty_i;
7224 branch_regs[i].dirty|=will_dirty_i;
7230 if(ba[i]<=start+i*4) {
7232 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7234 // Unconditional branch
7237 // Merge in delay slot (will dirty)
7238 for(r=0;r<HOST_REGS;r++) {
7239 if(r!=EXCLUDE_REG) {
7240 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7241 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7242 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7243 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7244 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7245 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7246 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7247 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7248 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7249 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7250 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7251 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7252 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7253 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7257 // Conditional branch (not taken case)
7258 temp_will_dirty=will_dirty_next;
7259 temp_wont_dirty=wont_dirty_next;
7260 // Merge in delay slot (will dirty)
7261 for(r=0;r<HOST_REGS;r++) {
7262 if(r!=EXCLUDE_REG) {
7264 // Will not dirty if likely branch is not taken
7265 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7266 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7267 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7268 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7269 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7270 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7271 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7272 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7273 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7274 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7275 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7276 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7277 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7278 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7283 // Merge in delay slot (wont dirty)
7284 for(r=0;r<HOST_REGS;r++) {
7285 if(r!=EXCLUDE_REG) {
7286 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7287 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7288 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7289 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7290 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7291 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7292 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7293 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7294 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7295 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7298 // Deal with changed mappings
7300 for(r=0;r<HOST_REGS;r++) {
7301 if(r!=EXCLUDE_REG) {
7302 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7303 temp_will_dirty&=~(1<<r);
7304 temp_wont_dirty&=~(1<<r);
7305 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7306 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7307 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7309 temp_will_dirty|=1<<r;
7310 temp_wont_dirty|=1<<r;
7317 will_dirty[i]=temp_will_dirty;
7318 wont_dirty[i]=temp_wont_dirty;
7319 clean_registers((ba[i]-start)>>2,i-1,0);
7321 // Limit recursion. It can take an excessive amount
7322 // of time if there are a lot of nested loops.
7323 will_dirty[(ba[i]-start)>>2]=0;
7324 wont_dirty[(ba[i]-start)>>2]=-1;
7329 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7331 // Unconditional branch
7334 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7335 for(r=0;r<HOST_REGS;r++) {
7336 if(r!=EXCLUDE_REG) {
7337 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7338 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7339 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7344 // Merge in delay slot
7345 for(r=0;r<HOST_REGS;r++) {
7346 if(r!=EXCLUDE_REG) {
7347 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7348 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7349 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7350 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7351 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7352 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7353 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7354 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7355 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7356 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7357 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7358 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7359 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7360 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7364 // Conditional branch
7365 will_dirty_i=will_dirty_next;
7366 wont_dirty_i=wont_dirty_next;
7367 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7368 for(r=0;r<HOST_REGS;r++) {
7369 if(r!=EXCLUDE_REG) {
7370 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7371 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7372 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7376 will_dirty_i&=~(1<<r);
7378 // Treat delay slot as part of branch too
7379 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7380 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7381 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7385 will_dirty[i+1]&=~(1<<r);
7390 // Merge in delay slot
7391 for(r=0;r<HOST_REGS;r++) {
7392 if(r!=EXCLUDE_REG) {
7394 // Might not dirty if likely branch is not taken
7395 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7396 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7397 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7398 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7399 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7400 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7401 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7402 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7403 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7404 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7405 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7406 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7407 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7408 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7413 // Merge in delay slot
7414 for(r=0;r<HOST_REGS;r++) {
7415 if(r!=EXCLUDE_REG) {
7416 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7417 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7418 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7419 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7420 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7421 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7422 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7423 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7424 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7425 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7429 #ifndef DESTRUCTIVE_WRITEBACK
7430 branch_regs[i].dirty&=wont_dirty_i;
7432 branch_regs[i].dirty|=will_dirty_i;
7437 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7439 // SYSCALL instruction (software interrupt)
7443 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7445 // ERET instruction (return from interrupt)
7449 will_dirty_next=will_dirty_i;
7450 wont_dirty_next=wont_dirty_i;
7451 for(r=0;r<HOST_REGS;r++) {
7452 if(r!=EXCLUDE_REG) {
7453 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7454 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7455 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7456 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7457 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7458 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7459 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7460 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7462 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7464 // Don't store a register immediately after writing it,
7465 // may prevent dual-issue.
7466 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7467 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7473 will_dirty[i]=will_dirty_i;
7474 wont_dirty[i]=wont_dirty_i;
7475 // Mark registers that won't be dirtied as not dirty
7477 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7478 for(r=0;r<HOST_REGS;r++) {
7479 if((will_dirty_i>>r)&1) {
7485 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7486 regs[i].dirty|=will_dirty_i;
7487 #ifndef DESTRUCTIVE_WRITEBACK
7488 regs[i].dirty&=wont_dirty_i;
7489 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7491 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7492 for(r=0;r<HOST_REGS;r++) {
7493 if(r!=EXCLUDE_REG) {
7494 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7495 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7496 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7504 for(r=0;r<HOST_REGS;r++) {
7505 if(r!=EXCLUDE_REG) {
7506 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7507 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7508 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7516 // Deal with changed mappings
7517 temp_will_dirty=will_dirty_i;
7518 temp_wont_dirty=wont_dirty_i;
7519 for(r=0;r<HOST_REGS;r++) {
7520 if(r!=EXCLUDE_REG) {
7522 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7524 #ifndef DESTRUCTIVE_WRITEBACK
7525 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7527 regs[i].wasdirty|=will_dirty_i&(1<<r);
7530 else if((nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7531 // Register moved to a different register
7532 will_dirty_i&=~(1<<r);
7533 wont_dirty_i&=~(1<<r);
7534 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7535 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7537 #ifndef DESTRUCTIVE_WRITEBACK
7538 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7540 regs[i].wasdirty|=will_dirty_i&(1<<r);
7544 will_dirty_i&=~(1<<r);
7545 wont_dirty_i&=~(1<<r);
7546 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7547 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7548 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7551 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7560 void disassemble_inst(int i)
7562 if (bt[i]) printf("*"); else printf(" ");
7565 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7567 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7569 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7571 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7573 if (opcode[i]==0x9&&rt1[i]!=31)
7574 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7576 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7579 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7581 if(opcode[i]==0xf) //LUI
7582 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7584 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7588 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7592 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7596 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7599 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7602 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7605 if((opcode2[i]&0x1d)==0x10)
7606 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7607 else if((opcode2[i]&0x1d)==0x11)
7608 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7610 printf (" %x: %s\n",start+i*4,insn[i]);
7614 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7615 else if(opcode2[i]==4)
7616 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7617 else printf (" %x: %s\n",start+i*4,insn[i]);
7621 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7622 else if(opcode2[i]>3)
7623 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7624 else printf (" %x: %s\n",start+i*4,insn[i]);
7628 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7629 else if(opcode2[i]>3)
7630 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7631 else printf (" %x: %s\n",start+i*4,insn[i]);
7634 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7637 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7640 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7643 //printf (" %s %8x\n",insn[i],source[i]);
7644 printf (" %x: %s\n",start+i*4,insn[i]);
7648 void new_dynarec_init()
7650 printf("Init new dynarec\n");
7651 out=(u_char *)BASE_ADDR;
7652 if (mmap (out, 1<<TARGET_SIZE_2,
7653 PROT_READ | PROT_WRITE | PROT_EXEC,
7654 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7655 -1, 0) <= 0) {printf("mmap() failed\n");}
7657 rdword=&readmem_dword;
7658 fake_pc.f.r.rs=&readmem_dword;
7659 fake_pc.f.r.rt=&readmem_dword;
7660 fake_pc.f.r.rd=&readmem_dword;
7663 for(n=0x80000;n<0x80800;n++)
7665 for(n=0;n<65536;n++)
7666 hash_table[n][0]=hash_table[n][2]=-1;
7667 memset(mini_ht,-1,sizeof(mini_ht));
7668 memset(restore_candidate,0,sizeof(restore_candidate));
7670 expirep=16384; // Expiry pointer, +2 blocks
7671 pending_exception=0;
7674 // Copy this into local area so we don't have to put it in every literal pool
7675 invc_ptr=invalid_code;
7680 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7682 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7683 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7684 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7687 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
7688 writemem[n] = write_nomem_new;
7689 writememb[n] = write_nomemb_new;
7690 writememh[n] = write_nomemh_new;
7692 writememd[n] = write_nomemd_new;
7694 readmem[n] = read_nomem_new;
7695 readmemb[n] = read_nomemb_new;
7696 readmemh[n] = read_nomemh_new;
7698 readmemd[n] = read_nomemd_new;
7701 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
7702 writemem[n] = write_rdram_new;
7703 writememb[n] = write_rdramb_new;
7704 writememh[n] = write_rdramh_new;
7706 writememd[n] = write_rdramd_new;
7709 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
7710 writemem[n] = write_nomem_new;
7711 writememb[n] = write_nomemb_new;
7712 writememh[n] = write_nomemh_new;
7714 writememd[n] = write_nomemd_new;
7716 readmem[n] = read_nomem_new;
7717 readmemb[n] = read_nomemb_new;
7718 readmemh[n] = read_nomemh_new;
7720 readmemd[n] = read_nomemd_new;
7728 void new_dynarec_cleanup()
7731 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
7732 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7733 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7734 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7736 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
7740 int new_recompile_block(int addr)
7743 if(addr==0x800cd050) {
7745 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
7747 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
7750 //if(Count==365117028) tracedebug=1;
7751 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7752 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
7753 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7755 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7756 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7757 /*if(Count>=312978186) {
7761 start = (u_int)addr&~3;
7762 //assert(((u_int)addr&1)==0);
7764 if (Config.HLE && start == 0x80001000) // hlecall
7766 // XXX: is this enough? Maybe check hleSoftCall?
7767 u_int beginning=(u_int)out;
7768 u_int page=get_page(start);
7769 invalid_code[start>>12]=0;
7770 emit_movimm(start,0);
7771 emit_writeword(0,(int)&pcaddr);
7772 emit_jmp((int)new_dyna_leave);
7774 __clear_cache((void *)beginning,out);
7776 ll_add(jump_in+page,start,(void *)beginning);
7779 else if ((u_int)addr < 0x00200000 ||
7780 (0xa0000000 <= addr && addr < 0xa0200000)) {
7781 // used for BIOS calls mostly?
7782 source = (u_int *)((u_int)rdram+(start&0x1fffff));
7783 pagelimit = (addr&0xa0000000)|0x00200000;
7785 else if (!Config.HLE && (
7786 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7787 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7789 source = (u_int *)((u_int)psxR+(start&0x7ffff));
7790 pagelimit = (addr&0xfff00000)|0x80000;
7795 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
7796 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
7797 pagelimit = 0xa4001000;
7801 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
7802 source = (u_int *)((u_int)rdram+start-0x80000000);
7803 pagelimit = 0x80000000+RAM_SIZE;
7806 else if ((signed int)addr >= (signed int)0xC0000000) {
7807 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
7808 //if(tlb_LUT_r[start>>12])
7809 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
7810 if((signed int)memory_map[start>>12]>=0) {
7811 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
7812 pagelimit=(start+4096)&0xFFFFF000;
7813 int map=memory_map[start>>12];
7816 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
7817 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
7819 assem_debug("pagelimit=%x\n",pagelimit);
7820 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
7823 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
7824 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
7825 return -1; // Caller will invoke exception handler
7827 //printf("source= %x\n",(int)source);
7831 printf("Compile at bogus memory address: %x \n", (int)addr);
7835 /* Pass 1: disassemble */
7836 /* Pass 2: register dependencies, branch targets */
7837 /* Pass 3: register allocation */
7838 /* Pass 4: branch dependencies */
7839 /* Pass 5: pre-alloc */
7840 /* Pass 6: optimize clean/dirty state */
7841 /* Pass 7: flag 32-bit registers */
7842 /* Pass 8: assembly */
7843 /* Pass 9: linker */
7844 /* Pass 10: garbage collection / free memory */
7848 unsigned int type,op,op2;
7850 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7852 /* Pass 1 disassembly */
7854 for(i=0;!done;i++) {
7855 bt[i]=0;likely[i]=0;op2=0;
7856 opcode[i]=op=source[i]>>26;
7859 case 0x00: strcpy(insn[i],"special"); type=NI;
7863 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7864 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7865 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7866 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7867 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7868 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7869 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7870 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7871 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7872 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7873 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7874 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7875 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7876 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7877 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7878 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7879 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7880 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7881 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7882 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7883 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7884 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7885 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7886 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7887 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7888 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7889 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7890 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7891 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7892 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7893 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7894 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7895 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7896 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7897 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7898 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7899 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7900 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7901 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7902 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7903 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7904 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7905 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7906 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7907 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7908 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7909 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7910 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7911 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7912 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7913 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7914 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7917 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7918 op2=(source[i]>>16)&0x1f;
7921 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7922 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7923 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7924 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7925 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7926 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7927 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7928 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7929 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7930 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7931 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7932 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7933 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7934 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7937 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7938 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7939 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7940 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7941 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7942 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7943 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7944 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7945 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7946 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7947 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7948 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7949 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7950 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7951 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7952 op2=(source[i]>>21)&0x1f;
7955 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7956 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7957 case 0x10: strcpy(insn[i],"tlb"); type=NI;
7958 switch(source[i]&0x3f)
7960 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7961 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7962 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7963 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7965 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7967 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7972 case 0x11: strcpy(insn[i],"cop1"); type=NI;
7973 op2=(source[i]>>21)&0x1f;
7976 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7977 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7978 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7979 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7980 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7981 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7982 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7983 switch((source[i]>>16)&0x3)
7985 case 0x00: strcpy(insn[i],"BC1F"); break;
7986 case 0x01: strcpy(insn[i],"BC1T"); break;
7987 case 0x02: strcpy(insn[i],"BC1FL"); break;
7988 case 0x03: strcpy(insn[i],"BC1TL"); break;
7991 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7992 switch(source[i]&0x3f)
7994 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7995 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7996 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7997 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7998 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7999 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8000 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8001 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8002 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8003 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8004 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8005 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8006 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8007 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8008 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8009 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8010 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8011 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8012 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8013 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8014 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8015 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8016 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8017 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8018 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8019 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8020 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8021 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8022 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8023 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8024 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8025 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8026 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8027 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8028 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8031 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8032 switch(source[i]&0x3f)
8034 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8035 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8036 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8037 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8038 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8039 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8040 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8041 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8042 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8043 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8044 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8045 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8046 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8047 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8048 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8049 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8050 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8051 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8052 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8053 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8054 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8055 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8056 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8057 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8058 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8059 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8060 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8061 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8062 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8063 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8064 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8065 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8066 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8067 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8068 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8071 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8072 switch(source[i]&0x3f)
8074 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8075 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8078 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8079 switch(source[i]&0x3f)
8081 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8082 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8087 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8088 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8089 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8090 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8092 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8093 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8094 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8095 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8097 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8098 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8099 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8100 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8101 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8102 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8103 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8104 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8105 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8106 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8107 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8108 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8110 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8111 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8113 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8114 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8115 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8116 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8118 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8119 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8120 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8122 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8123 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8125 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8126 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8127 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8130 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8131 op2=(source[i]>>21)&0x1f;
8134 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8135 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8136 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8137 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8139 if (gte_handlers[source[i]&0x3f]!=NULL) {
8140 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8146 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8147 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8148 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8150 default: strcpy(insn[i],"???"); type=NI;
8151 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8155 /* detect branch in delay slot early */
8156 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8157 opcode[i+1]=source[i+1]>>26;
8158 opcode2[i+1]=source[i+1]&0x3f;
8159 if((0<opcode[i+1]&&opcode[i+1]<8)||(opcode[i+1]==0&&(opcode2[i+1]==8||opcode2[i+1]==9))) {
8160 printf("branch in delay slot @%08x (%08x)\n", addr + i*4+4, addr);
8161 // don't handle first branch and call interpreter if it's hit
8168 /* Get registers/immediates */
8176 rs1[i]=(source[i]>>21)&0x1f;
8178 rt1[i]=(source[i]>>16)&0x1f;
8180 imm[i]=(short)source[i];
8184 rs1[i]=(source[i]>>21)&0x1f;
8185 rs2[i]=(source[i]>>16)&0x1f;
8188 imm[i]=(short)source[i];
8189 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8192 // LWL/LWR only load part of the register,
8193 // therefore the target register must be treated as a source too
8194 rs1[i]=(source[i]>>21)&0x1f;
8195 rs2[i]=(source[i]>>16)&0x1f;
8196 rt1[i]=(source[i]>>16)&0x1f;
8198 imm[i]=(short)source[i];
8199 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8200 if(op==0x26) dep1[i]=rt1[i]; // LWR
8203 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8204 else rs1[i]=(source[i]>>21)&0x1f;
8206 rt1[i]=(source[i]>>16)&0x1f;
8208 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8209 imm[i]=(unsigned short)source[i];
8211 imm[i]=(short)source[i];
8213 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8214 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8215 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8222 // The JAL instruction writes to r31.
8229 rs1[i]=(source[i]>>21)&0x1f;
8233 // The JALR instruction writes to rd.
8235 rt1[i]=(source[i]>>11)&0x1f;
8240 rs1[i]=(source[i]>>21)&0x1f;
8241 rs2[i]=(source[i]>>16)&0x1f;
8244 if(op&2) { // BGTZ/BLEZ
8252 rs1[i]=(source[i]>>21)&0x1f;
8257 if(op2&0x10) { // BxxAL
8259 // NOTE: If the branch is not taken, r31 is still overwritten
8261 likely[i]=(op2&2)>>1;
8268 likely[i]=((source[i])>>17)&1;
8271 rs1[i]=(source[i]>>21)&0x1f; // source
8272 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8273 rt1[i]=(source[i]>>11)&0x1f; // destination
8275 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8276 us1[i]=rs1[i];us2[i]=rs2[i];
8278 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8279 dep1[i]=rs1[i];dep2[i]=rs2[i];
8281 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8282 dep1[i]=rs1[i];dep2[i]=rs2[i];
8286 rs1[i]=(source[i]>>21)&0x1f; // source
8287 rs2[i]=(source[i]>>16)&0x1f; // divisor
8290 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8291 us1[i]=rs1[i];us2[i]=rs2[i];
8299 if(op2==0x10) rs1[i]=HIREG; // MFHI
8300 if(op2==0x11) rt1[i]=HIREG; // MTHI
8301 if(op2==0x12) rs1[i]=LOREG; // MFLO
8302 if(op2==0x13) rt1[i]=LOREG; // MTLO
8303 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8304 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8308 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8309 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8310 rt1[i]=(source[i]>>11)&0x1f; // destination
8312 // DSLLV/DSRLV/DSRAV are 64-bit
8313 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8316 rs1[i]=(source[i]>>16)&0x1f;
8318 rt1[i]=(source[i]>>11)&0x1f;
8320 imm[i]=(source[i]>>6)&0x1f;
8321 // DSxx32 instructions
8322 if(op2>=0x3c) imm[i]|=0x20;
8323 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8324 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8331 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8332 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8333 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8334 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8342 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8343 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8344 if(op2==5) us1[i]=rs1[i]; // DMTC1
8348 rs1[i]=(source[i]>>21)&0x1F;
8352 imm[i]=(short)source[i];
8355 rs1[i]=(source[i]>>21)&0x1F;
8359 imm[i]=(short)source[i];
8388 /* Calculate branch target addresses */
8390 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8391 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8392 ba[i]=start+i*4+8; // Ignore never taken branch
8393 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8394 ba[i]=start+i*4+8; // Ignore never taken branch
8395 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8396 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8398 /* Is this the end of the block? */
8399 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8400 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8404 if(stop_after_jal) done=1;
8406 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8408 // Don't recompile stuff that's already compiled
8409 if(check_addr(start+i*4+4)) done=1;
8410 // Don't get too close to the limit
8411 if(i>MAXBLOCK/2) done=1;
8413 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8414 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8416 // Does the block continue due to a branch?
8419 if(ba[j]==start+i*4+4) done=j=0;
8420 if(ba[j]==start+i*4+8) done=j=0;
8423 //assert(i<MAXBLOCK-1);
8424 if(start+i*4==pagelimit-4) done=1;
8425 assert(start+i*4<pagelimit);
8426 if (i==MAXBLOCK-1) done=1;
8427 // Stop if we're compiling junk
8428 if(itype[i]==NI&&opcode[i]==0x11) {
8429 done=stop_after_jal=1;
8430 printf("Disabled speculative precompilation\n");
8434 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8435 if(start+i*4==pagelimit) {
8441 /* Pass 2 - Register dependencies and branch targets */
8443 unneeded_registers(0,slen-1,0);
8445 /* Pass 3 - Register allocation */
8447 struct regstat current; // Current register allocations/status
8450 current.u=unneeded_reg[0];
8451 current.uu=unneeded_reg_upper[0];
8452 clear_all_regs(current.regmap);
8453 alloc_reg(¤t,0,CCREG);
8454 dirty_reg(¤t,CCREG);
8461 provisional_32bit();
8464 // First instruction is delay slot
8469 unneeded_reg_upper[0]=1;
8470 current.regmap[HOST_BTREG]=BTREG;
8478 for(hr=0;hr<HOST_REGS;hr++)
8480 // Is this really necessary?
8481 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8487 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8489 if(rs1[i-2]==0||rs2[i-2]==0)
8492 current.is32|=1LL<<rs1[i-2];
8493 int hr=get_reg(current.regmap,rs1[i-2]|64);
8494 if(hr>=0) current.regmap[hr]=-1;
8497 current.is32|=1LL<<rs2[i-2];
8498 int hr=get_reg(current.regmap,rs2[i-2]|64);
8499 if(hr>=0) current.regmap[hr]=-1;
8504 // If something jumps here with 64-bit values
8505 // then promote those registers to 64 bits
8508 uint64_t temp_is32=current.is32;
8511 if(ba[j]==start+i*4)
8512 temp_is32&=branch_regs[j].is32;
8516 if(ba[j]==start+i*4)
8520 if(temp_is32!=current.is32) {
8521 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8522 #ifdef DESTRUCTIVE_WRITEBACK
8523 for(hr=0;hr<HOST_REGS;hr++)
8525 int r=current.regmap[hr];
8528 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8530 //printf("restore %d\n",r);
8535 current.is32=temp_is32;
8539 memset(p32, 0xff, sizeof(p32));
8543 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8544 regs[i].wasconst=current.isconst;
8545 regs[i].was32=current.is32;
8546 regs[i].wasdirty=current.dirty;
8547 #ifdef DESTRUCTIVE_WRITEBACK
8548 // To change a dirty register from 32 to 64 bits, we must write
8549 // it out during the previous cycle (for branches, 2 cycles)
8550 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8552 uint64_t temp_is32=current.is32;
8555 if(ba[j]==start+i*4+4)
8556 temp_is32&=branch_regs[j].is32;
8560 if(ba[j]==start+i*4+4)
8564 if(temp_is32!=current.is32) {
8565 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8566 for(hr=0;hr<HOST_REGS;hr++)
8568 int r=current.regmap[hr];
8571 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8572 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8574 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8576 //printf("dump %d/r%d\n",hr,r);
8577 current.regmap[hr]=-1;
8578 if(get_reg(current.regmap,r|64)>=0)
8579 current.regmap[get_reg(current.regmap,r|64)]=-1;
8587 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8589 uint64_t temp_is32=current.is32;
8592 if(ba[j]==start+i*4+8)
8593 temp_is32&=branch_regs[j].is32;
8597 if(ba[j]==start+i*4+8)
8601 if(temp_is32!=current.is32) {
8602 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8603 for(hr=0;hr<HOST_REGS;hr++)
8605 int r=current.regmap[hr];
8608 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8609 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8611 //printf("dump %d/r%d\n",hr,r);
8612 current.regmap[hr]=-1;
8613 if(get_reg(current.regmap,r|64)>=0)
8614 current.regmap[get_reg(current.regmap,r|64)]=-1;
8622 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8624 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8625 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8626 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8635 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
8636 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8637 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8638 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8639 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8642 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
8646 ds=0; // Skip delay slot, already allocated as part of branch
8647 // ...but we need to alloc it in case something jumps here
8649 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
8650 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
8652 current.u=branch_unneeded_reg[i-1];
8653 current.uu=branch_unneeded_reg_upper[i-1];
8655 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
8656 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8657 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8660 struct regstat temp;
8661 memcpy(&temp,¤t,sizeof(current));
8662 temp.wasdirty=temp.dirty;
8663 temp.was32=temp.is32;
8664 // TODO: Take into account unconditional branches, as below
8665 delayslot_alloc(&temp,i);
8666 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
8667 regs[i].wasdirty=temp.wasdirty;
8668 regs[i].was32=temp.was32;
8669 regs[i].dirty=temp.dirty;
8670 regs[i].is32=temp.is32;
8674 // Create entry (branch target) regmap
8675 for(hr=0;hr<HOST_REGS;hr++)
8677 int r=temp.regmap[hr];
8679 if(r!=regmap_pre[i][hr]) {
8680 regs[i].regmap_entry[hr]=-1;
8685 if((current.u>>r)&1) {
8686 regs[i].regmap_entry[hr]=-1;
8687 regs[i].regmap[hr]=-1;
8688 //Don't clear regs in the delay slot as the branch might need them
8689 //current.regmap[hr]=-1;
8691 regs[i].regmap_entry[hr]=r;
8694 if((current.uu>>(r&63))&1) {
8695 regs[i].regmap_entry[hr]=-1;
8696 regs[i].regmap[hr]=-1;
8697 //Don't clear regs in the delay slot as the branch might need them
8698 //current.regmap[hr]=-1;
8700 regs[i].regmap_entry[hr]=r;
8704 // First instruction expects CCREG to be allocated
8705 if(i==0&&hr==HOST_CCREG)
8706 regs[i].regmap_entry[hr]=CCREG;
8708 regs[i].regmap_entry[hr]=-1;
8712 else { // Not delay slot
8715 //current.isconst=0; // DEBUG
8716 //current.wasconst=0; // DEBUG
8717 //regs[i].wasconst=0; // DEBUG
8718 clear_const(¤t,rt1[i]);
8719 alloc_cc(¤t,i);
8720 dirty_reg(¤t,CCREG);
8722 alloc_reg(¤t,i,31);
8723 dirty_reg(¤t,31);
8724 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8725 assert(rt1[i+1]!=rt1[i]);
8727 alloc_reg(¤t,i,PTEMP);
8729 //current.is32|=1LL<<rt1[i];
8731 delayslot_alloc(¤t,i+1);
8732 //current.isconst=0; // DEBUG
8734 //printf("i=%d, isconst=%x\n",i,current.isconst);
8737 //current.isconst=0;
8738 //current.wasconst=0;
8739 //regs[i].wasconst=0;
8740 clear_const(¤t,rs1[i]);
8741 clear_const(¤t,rt1[i]);
8742 alloc_cc(¤t,i);
8743 dirty_reg(¤t,CCREG);
8744 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8745 alloc_reg(¤t,i,rs1[i]);
8747 alloc_reg(¤t,i,rt1[i]);
8748 dirty_reg(¤t,rt1[i]);
8749 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8750 assert(rt1[i+1]!=rt1[i]);
8752 alloc_reg(¤t,i,PTEMP);
8756 if(rs1[i]==31) { // JALR
8757 alloc_reg(¤t,i,RHASH);
8758 #ifndef HOST_IMM_ADDR32
8759 alloc_reg(¤t,i,RHTBL);
8763 delayslot_alloc(¤t,i+1);
8765 // The delay slot overwrites our source register,
8766 // allocate a temporary register to hold the old value.
8770 delayslot_alloc(¤t,i+1);
8772 alloc_reg(¤t,i,RTEMP);
8774 //current.isconst=0; // DEBUG
8778 //current.isconst=0;
8779 //current.wasconst=0;
8780 //regs[i].wasconst=0;
8781 clear_const(¤t,rs1[i]);
8782 clear_const(¤t,rs2[i]);
8783 if((opcode[i]&0x3E)==4) // BEQ/BNE
8785 alloc_cc(¤t,i);
8786 dirty_reg(¤t,CCREG);
8787 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8788 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8789 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8791 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8792 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8794 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8795 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8796 // The delay slot overwrites one of our conditions.
8797 // Allocate the branch condition registers instead.
8798 // Note that such a sequence of instructions could
8799 // be considered a bug since the branch can not be
8800 // re-executed if an exception occurs.
8804 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8805 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8806 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8808 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8809 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8812 else delayslot_alloc(¤t,i+1);
8815 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8817 alloc_cc(¤t,i);
8818 dirty_reg(¤t,CCREG);
8819 alloc_reg(¤t,i,rs1[i]);
8820 if(!(current.is32>>rs1[i]&1))
8822 alloc_reg64(¤t,i,rs1[i]);
8824 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8825 // The delay slot overwrites one of our conditions.
8826 // Allocate the branch condition registers instead.
8827 // Note that such a sequence of instructions could
8828 // be considered a bug since the branch can not be
8829 // re-executed if an exception occurs.
8833 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8834 if(!((current.is32>>rs1[i])&1))
8836 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8839 else delayslot_alloc(¤t,i+1);
8842 // Don't alloc the delay slot yet because we might not execute it
8843 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8848 alloc_cc(¤t,i);
8849 dirty_reg(¤t,CCREG);
8850 alloc_reg(¤t,i,rs1[i]);
8851 alloc_reg(¤t,i,rs2[i]);
8852 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8854 alloc_reg64(¤t,i,rs1[i]);
8855 alloc_reg64(¤t,i,rs2[i]);
8859 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8864 alloc_cc(¤t,i);
8865 dirty_reg(¤t,CCREG);
8866 alloc_reg(¤t,i,rs1[i]);
8867 if(!(current.is32>>rs1[i]&1))
8869 alloc_reg64(¤t,i,rs1[i]);
8873 //current.isconst=0;
8876 //current.isconst=0;
8877 //current.wasconst=0;
8878 //regs[i].wasconst=0;
8879 clear_const(¤t,rs1[i]);
8880 clear_const(¤t,rt1[i]);
8881 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8882 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8884 alloc_cc(¤t,i);
8885 dirty_reg(¤t,CCREG);
8886 alloc_reg(¤t,i,rs1[i]);
8887 if(!(current.is32>>rs1[i]&1))
8889 alloc_reg64(¤t,i,rs1[i]);
8891 if (rt1[i]==31) { // BLTZAL/BGEZAL
8892 alloc_reg(¤t,i,31);
8893 dirty_reg(¤t,31);
8894 assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8895 //#ifdef REG_PREFETCH
8896 //alloc_reg(¤t,i,PTEMP);
8898 //current.is32|=1LL<<rt1[i];
8900 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8901 // The delay slot overwrites the branch condition.
8902 // Allocate the branch condition registers instead.
8903 // Note that such a sequence of instructions could
8904 // be considered a bug since the branch can not be
8905 // re-executed if an exception occurs.
8909 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8910 if(!((current.is32>>rs1[i])&1))
8912 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8915 else delayslot_alloc(¤t,i+1);
8918 // Don't alloc the delay slot yet because we might not execute it
8919 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8924 alloc_cc(¤t,i);
8925 dirty_reg(¤t,CCREG);
8926 alloc_reg(¤t,i,rs1[i]);
8927 if(!(current.is32>>rs1[i]&1))
8929 alloc_reg64(¤t,i,rs1[i]);
8933 //current.isconst=0;
8939 if(likely[i]==0) // BC1F/BC1T
8941 // TODO: Theoretically we can run out of registers here on x86.
8942 // The delay slot can allocate up to six, and we need to check
8943 // CSREG before executing the delay slot. Possibly we can drop
8944 // the cycle count and then reload it after checking that the
8945 // FPU is in a usable state, or don't do out-of-order execution.
8946 alloc_cc(¤t,i);
8947 dirty_reg(¤t,CCREG);
8948 alloc_reg(¤t,i,FSREG);
8949 alloc_reg(¤t,i,CSREG);
8950 if(itype[i+1]==FCOMP) {
8951 // The delay slot overwrites the branch condition.
8952 // Allocate the branch condition registers instead.
8953 // Note that such a sequence of instructions could
8954 // be considered a bug since the branch can not be
8955 // re-executed if an exception occurs.
8956 alloc_cc(¤t,i);
8957 dirty_reg(¤t,CCREG);
8958 alloc_reg(¤t,i,CSREG);
8959 alloc_reg(¤t,i,FSREG);
8962 delayslot_alloc(¤t,i+1);
8963 alloc_reg(¤t,i+1,CSREG);
8967 // Don't alloc the delay slot yet because we might not execute it
8968 if(likely[i]) // BC1FL/BC1TL
8970 alloc_cc(¤t,i);
8971 dirty_reg(¤t,CCREG);
8972 alloc_reg(¤t,i,CSREG);
8973 alloc_reg(¤t,i,FSREG);
8979 imm16_alloc(¤t,i);
8983 load_alloc(¤t,i);
8987 store_alloc(¤t,i);
8990 alu_alloc(¤t,i);
8993 shift_alloc(¤t,i);
8996 multdiv_alloc(¤t,i);
8999 shiftimm_alloc(¤t,i);
9002 mov_alloc(¤t,i);
9005 cop0_alloc(¤t,i);
9009 cop1_alloc(¤t,i);
9012 c1ls_alloc(¤t,i);
9015 c2ls_alloc(¤t,i);
9018 c2op_alloc(¤t,i);
9021 fconv_alloc(¤t,i);
9024 float_alloc(¤t,i);
9027 fcomp_alloc(¤t,i);
9032 syscall_alloc(¤t,i);
9035 pagespan_alloc(¤t,i);
9039 // Drop the upper half of registers that have become 32-bit
9040 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9041 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9042 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9043 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9046 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9047 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9048 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9049 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9053 // Create entry (branch target) regmap
9054 for(hr=0;hr<HOST_REGS;hr++)
9057 r=current.regmap[hr];
9059 if(r!=regmap_pre[i][hr]) {
9060 // TODO: delay slot (?)
9061 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9062 if(or<0||(r&63)>=TEMPREG){
9063 regs[i].regmap_entry[hr]=-1;
9067 // Just move it to a different register
9068 regs[i].regmap_entry[hr]=r;
9069 // If it was dirty before, it's still dirty
9070 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9077 regs[i].regmap_entry[hr]=0;
9081 if((current.u>>r)&1) {
9082 regs[i].regmap_entry[hr]=-1;
9083 //regs[i].regmap[hr]=-1;
9084 current.regmap[hr]=-1;
9086 regs[i].regmap_entry[hr]=r;
9089 if((current.uu>>(r&63))&1) {
9090 regs[i].regmap_entry[hr]=-1;
9091 //regs[i].regmap[hr]=-1;
9092 current.regmap[hr]=-1;
9094 regs[i].regmap_entry[hr]=r;
9098 // Branches expect CCREG to be allocated at the target
9099 if(regmap_pre[i][hr]==CCREG)
9100 regs[i].regmap_entry[hr]=CCREG;
9102 regs[i].regmap_entry[hr]=-1;
9105 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9107 /* Branch post-alloc */
9110 current.was32=current.is32;
9111 current.wasdirty=current.dirty;
9112 switch(itype[i-1]) {
9114 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9115 branch_regs[i-1].isconst=0;
9116 branch_regs[i-1].wasconst=0;
9117 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9118 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9119 alloc_cc(&branch_regs[i-1],i-1);
9120 dirty_reg(&branch_regs[i-1],CCREG);
9121 if(rt1[i-1]==31) { // JAL
9122 alloc_reg(&branch_regs[i-1],i-1,31);
9123 dirty_reg(&branch_regs[i-1],31);
9124 branch_regs[i-1].is32|=1LL<<31;
9126 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9127 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9130 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9131 branch_regs[i-1].isconst=0;
9132 branch_regs[i-1].wasconst=0;
9133 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9134 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9135 alloc_cc(&branch_regs[i-1],i-1);
9136 dirty_reg(&branch_regs[i-1],CCREG);
9137 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9138 if(rt1[i-1]!=0) { // JALR
9139 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9140 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9141 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9144 if(rs1[i-1]==31) { // JALR
9145 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9146 #ifndef HOST_IMM_ADDR32
9147 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9151 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9152 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9155 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9157 alloc_cc(¤t,i-1);
9158 dirty_reg(¤t,CCREG);
9159 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9160 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9161 // The delay slot overwrote one of our conditions
9162 // Delay slot goes after the test (in order)
9163 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9164 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9165 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9168 delayslot_alloc(¤t,i);
9173 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9174 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9175 // Alloc the branch condition registers
9176 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9177 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9178 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9180 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9181 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9184 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9185 branch_regs[i-1].isconst=0;
9186 branch_regs[i-1].wasconst=0;
9187 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9188 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9191 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9193 alloc_cc(¤t,i-1);
9194 dirty_reg(¤t,CCREG);
9195 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9196 // The delay slot overwrote the branch condition
9197 // Delay slot goes after the test (in order)
9198 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9199 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9200 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9203 delayslot_alloc(¤t,i);
9208 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9209 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9210 // Alloc the branch condition register
9211 alloc_reg(¤t,i-1,rs1[i-1]);
9212 if(!(current.is32>>rs1[i-1]&1))
9214 alloc_reg64(¤t,i-1,rs1[i-1]);
9217 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9218 branch_regs[i-1].isconst=0;
9219 branch_regs[i-1].wasconst=0;
9220 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9221 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9224 // Alloc the delay slot in case the branch is taken
9225 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9227 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9228 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9229 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9230 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9231 alloc_cc(&branch_regs[i-1],i);
9232 dirty_reg(&branch_regs[i-1],CCREG);
9233 delayslot_alloc(&branch_regs[i-1],i);
9234 branch_regs[i-1].isconst=0;
9235 alloc_reg(¤t,i,CCREG); // Not taken path
9236 dirty_reg(¤t,CCREG);
9237 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9240 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9242 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9243 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9244 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9245 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9246 alloc_cc(&branch_regs[i-1],i);
9247 dirty_reg(&branch_regs[i-1],CCREG);
9248 delayslot_alloc(&branch_regs[i-1],i);
9249 branch_regs[i-1].isconst=0;
9250 alloc_reg(¤t,i,CCREG); // Not taken path
9251 dirty_reg(¤t,CCREG);
9252 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9256 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9257 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9259 alloc_cc(¤t,i-1);
9260 dirty_reg(¤t,CCREG);
9261 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9262 // The delay slot overwrote the branch condition
9263 // Delay slot goes after the test (in order)
9264 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9265 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9266 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9269 delayslot_alloc(¤t,i);
9274 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9275 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9276 // Alloc the branch condition register
9277 alloc_reg(¤t,i-1,rs1[i-1]);
9278 if(!(current.is32>>rs1[i-1]&1))
9280 alloc_reg64(¤t,i-1,rs1[i-1]);
9283 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9284 branch_regs[i-1].isconst=0;
9285 branch_regs[i-1].wasconst=0;
9286 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9287 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9290 // Alloc the delay slot in case the branch is taken
9291 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9293 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9294 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9295 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9296 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9297 alloc_cc(&branch_regs[i-1],i);
9298 dirty_reg(&branch_regs[i-1],CCREG);
9299 delayslot_alloc(&branch_regs[i-1],i);
9300 branch_regs[i-1].isconst=0;
9301 alloc_reg(¤t,i,CCREG); // Not taken path
9302 dirty_reg(¤t,CCREG);
9303 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9305 // FIXME: BLTZAL/BGEZAL
9306 if(opcode2[i-1]&0x10) { // BxxZAL
9307 alloc_reg(&branch_regs[i-1],i-1,31);
9308 dirty_reg(&branch_regs[i-1],31);
9309 branch_regs[i-1].is32|=1LL<<31;
9313 if(likely[i-1]==0) // BC1F/BC1T
9315 alloc_cc(¤t,i-1);
9316 dirty_reg(¤t,CCREG);
9317 if(itype[i]==FCOMP) {
9318 // The delay slot overwrote the branch condition
9319 // Delay slot goes after the test (in order)
9320 delayslot_alloc(¤t,i);
9325 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9326 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9327 // Alloc the branch condition register
9328 alloc_reg(¤t,i-1,FSREG);
9330 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9331 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9335 // Alloc the delay slot in case the branch is taken
9336 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9337 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9338 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9339 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9340 alloc_cc(&branch_regs[i-1],i);
9341 dirty_reg(&branch_regs[i-1],CCREG);
9342 delayslot_alloc(&branch_regs[i-1],i);
9343 branch_regs[i-1].isconst=0;
9344 alloc_reg(¤t,i,CCREG); // Not taken path
9345 dirty_reg(¤t,CCREG);
9346 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9351 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9353 if(rt1[i-1]==31) // JAL/JALR
9355 // Subroutine call will return here, don't alloc any registers
9358 clear_all_regs(current.regmap);
9359 alloc_reg(¤t,i,CCREG);
9360 dirty_reg(¤t,CCREG);
9364 // Internal branch will jump here, match registers to caller
9365 current.is32=0x3FFFFFFFFLL;
9367 clear_all_regs(current.regmap);
9368 alloc_reg(¤t,i,CCREG);
9369 dirty_reg(¤t,CCREG);
9372 if(ba[j]==start+i*4+4) {
9373 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9374 current.is32=branch_regs[j].is32;
9375 current.dirty=branch_regs[j].dirty;
9380 if(ba[j]==start+i*4+4) {
9381 for(hr=0;hr<HOST_REGS;hr++) {
9382 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9383 current.regmap[hr]=-1;
9385 current.is32&=branch_regs[j].is32;
9386 current.dirty&=branch_regs[j].dirty;
9395 // Count cycles in between branches
9397 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9406 flush_dirty_uppers(¤t);
9408 regs[i].is32=current.is32;
9409 regs[i].dirty=current.dirty;
9410 regs[i].isconst=current.isconst;
9411 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9413 for(hr=0;hr<HOST_REGS;hr++) {
9414 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9415 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9416 regs[i].wasconst&=~(1<<hr);
9420 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9423 /* Pass 4 - Cull unused host registers */
9427 for (i=slen-1;i>=0;i--)
9430 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9432 if(ba[i]<start || ba[i]>=(start+slen*4))
9434 // Branch out of this block, don't need anything
9440 // Need whatever matches the target
9442 int t=(ba[i]-start)>>2;
9443 for(hr=0;hr<HOST_REGS;hr++)
9445 if(regs[i].regmap_entry[hr]>=0) {
9446 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9450 // Conditional branch may need registers for following instructions
9451 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9454 nr|=needed_reg[i+2];
9455 for(hr=0;hr<HOST_REGS;hr++)
9457 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9458 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9462 // Don't need stuff which is overwritten
9463 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9464 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9465 // Merge in delay slot
9466 for(hr=0;hr<HOST_REGS;hr++)
9469 // These are overwritten unless the branch is "likely"
9470 // and the delay slot is nullified if not taken
9471 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9472 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9474 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9475 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9476 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9477 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9478 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9479 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9480 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9481 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9482 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9483 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9484 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9486 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9487 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9488 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9490 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9491 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9492 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9496 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9498 // SYSCALL instruction (software interrupt)
9501 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9503 // ERET instruction (return from interrupt)
9509 for(hr=0;hr<HOST_REGS;hr++) {
9510 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9511 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9512 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9513 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9517 for(hr=0;hr<HOST_REGS;hr++)
9519 // Overwritten registers are not needed
9520 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9521 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9522 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9523 // Source registers are needed
9524 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9525 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9526 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9527 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9528 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9529 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9530 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9531 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9532 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9533 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9534 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9536 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9537 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9538 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9540 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9541 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9542 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9544 // Don't store a register immediately after writing it,
9545 // may prevent dual-issue.
9546 // But do so if this is a branch target, otherwise we
9547 // might have to load the register before the branch.
9548 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9549 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9550 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9551 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9552 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9554 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9555 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9556 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9557 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9561 // Cycle count is needed at branches. Assume it is needed at the target too.
9562 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9563 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9564 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9569 // Deallocate unneeded registers
9570 for(hr=0;hr<HOST_REGS;hr++)
9573 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9574 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9575 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9576 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9578 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9581 regs[i].regmap[hr]=-1;
9582 regs[i].isconst&=~(1<<hr);
9583 if(i<slen-2) regmap_pre[i+2][hr]=-1;
9587 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9589 int d1=0,d2=0,map=0,temp=0;
9590 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
9596 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
9597 itype[i+1]==STORE || itype[i+1]==STORELR ||
9598 itype[i+1]==C1LS || itype[i+1]==C2LS)
9601 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
9602 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9605 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
9606 itype[i+1]==C1LS || itype[i+1]==C2LS)
9608 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9609 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9610 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
9611 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
9612 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9613 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
9614 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
9615 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
9616 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
9617 regs[i].regmap[hr]!=map )
9619 regs[i].regmap[hr]=-1;
9620 regs[i].isconst&=~(1<<hr);
9621 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
9622 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
9623 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
9624 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
9625 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
9626 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
9627 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
9628 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
9629 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
9630 branch_regs[i].regmap[hr]!=map)
9632 branch_regs[i].regmap[hr]=-1;
9633 branch_regs[i].regmap_entry[hr]=-1;
9634 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9636 if(!likely[i]&&i<slen-2) {
9637 regmap_pre[i+2][hr]=-1;
9648 int d1=0,d2=0,map=-1,temp=-1;
9649 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
9655 if(itype[i]==LOAD || itype[i]==LOADLR ||
9656 itype[i]==STORE || itype[i]==STORELR ||
9657 itype[i]==C1LS || itype[i]==C2LS)
9659 } else if(itype[i]==STORE || itype[i]==STORELR ||
9660 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
9663 if(itype[i]==LOADLR || itype[i]==STORELR ||
9664 itype[i]==C1LS || itype[i]==C2LS)
9666 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9667 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
9668 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
9669 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
9670 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
9671 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
9673 if(i<slen-1&&!is_ds[i]) {
9674 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
9675 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
9676 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9678 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9679 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9681 regmap_pre[i+1][hr]=-1;
9682 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9684 regs[i].regmap[hr]=-1;
9685 regs[i].isconst&=~(1<<hr);
9693 /* Pass 5 - Pre-allocate registers */
9695 // If a register is allocated during a loop, try to allocate it for the
9696 // entire loop, if possible. This avoids loading/storing registers
9697 // inside of the loop.
9699 signed char f_regmap[HOST_REGS];
9700 clear_all_regs(f_regmap);
9701 for(i=0;i<slen-1;i++)
9703 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9705 if(ba[i]>=start && ba[i]<(start+i*4))
9706 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9707 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9708 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9709 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9710 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9711 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9713 int t=(ba[i]-start)>>2;
9714 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9715 if(t<2||(itype[t-2]!=UJUMP)) // call/ret assumes no registers allocated
9716 for(hr=0;hr<HOST_REGS;hr++)
9718 if(regs[i].regmap[hr]>64) {
9719 if(!((regs[i].dirty>>hr)&1))
9720 f_regmap[hr]=regs[i].regmap[hr];
9721 else f_regmap[hr]=-1;
9723 else if(regs[i].regmap[hr]>=0) {
9724 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9725 // dealloc old register
9727 for(n=0;n<HOST_REGS;n++)
9729 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9731 // and alloc new one
9732 f_regmap[hr]=regs[i].regmap[hr];
9735 if(branch_regs[i].regmap[hr]>64) {
9736 if(!((branch_regs[i].dirty>>hr)&1))
9737 f_regmap[hr]=branch_regs[i].regmap[hr];
9738 else f_regmap[hr]=-1;
9740 else if(branch_regs[i].regmap[hr]>=0) {
9741 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9742 // dealloc old register
9744 for(n=0;n<HOST_REGS;n++)
9746 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9748 // and alloc new one
9749 f_regmap[hr]=branch_regs[i].regmap[hr];
9752 if(itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9753 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9754 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9755 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9757 // Test both in case the delay slot is ooo,
9758 // could be done better...
9759 if(count_free_regs(branch_regs[i].regmap)<2
9760 ||count_free_regs(regs[i].regmap)<2)
9761 f_regmap[hr]=branch_regs[i].regmap[hr];
9763 // Avoid dirty->clean transition
9764 // #ifdef DESTRUCTIVE_WRITEBACK here?
9765 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9766 if(f_regmap[hr]>0) {
9767 if(regs[t].regmap_entry[hr]<0) {
9771 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9772 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9773 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9775 // NB This can exclude the case where the upper-half
9776 // register is lower numbered than the lower-half
9777 // register. Not sure if it's worth fixing...
9778 if(get_reg(regs[j].regmap,r&63)<0) break;
9779 if(regs[j].is32&(1LL<<(r&63))) break;
9781 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9782 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9784 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9785 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9787 if(get_reg(regs[i].regmap,r&63)<0) break;
9788 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9791 while(k>1&®s[k-1].regmap[hr]==-1) {
9792 if(itype[k-1]==STORE||itype[k-1]==STORELR
9793 ||itype[k-1]==C1LS||itype[k-1]==SHIFT||itype[k-1]==COP1
9794 ||itype[k-1]==FLOAT||itype[k-1]==FCONV||itype[k-1]==FCOMP
9795 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9796 if(count_free_regs(regs[k-1].regmap)<2) {
9797 //printf("no free regs for store %x\n",start+(k-1)*4);
9802 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
9803 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9804 //printf("no-match due to different register\n");
9807 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9808 //printf("no-match due to branch\n");
9811 // call/ret fast path assumes no registers allocated
9812 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)) {
9816 // NB This can exclude the case where the upper-half
9817 // register is lower numbered than the lower-half
9818 // register. Not sure if it's worth fixing...
9819 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9820 if(regs[k-1].is32&(1LL<<(r&63))) break;
9825 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9826 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9827 //printf("bad match after branch\n");
9831 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
9832 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9834 regs[k].regmap_entry[hr]=f_regmap[hr];
9835 regs[k].regmap[hr]=f_regmap[hr];
9836 regmap_pre[k+1][hr]=f_regmap[hr];
9837 regs[k].wasdirty&=~(1<<hr);
9838 regs[k].dirty&=~(1<<hr);
9839 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
9840 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
9841 regs[k].wasconst&=~(1<<hr);
9842 regs[k].isconst&=~(1<<hr);
9847 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9850 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9851 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
9852 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9853 regs[i].regmap_entry[hr]=f_regmap[hr];
9854 regs[i].regmap[hr]=f_regmap[hr];
9855 regs[i].wasdirty&=~(1<<hr);
9856 regs[i].dirty&=~(1<<hr);
9857 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
9858 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
9859 regs[i].wasconst&=~(1<<hr);
9860 regs[i].isconst&=~(1<<hr);
9861 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9862 branch_regs[i].wasdirty&=~(1<<hr);
9863 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
9864 branch_regs[i].regmap[hr]=f_regmap[hr];
9865 branch_regs[i].dirty&=~(1<<hr);
9866 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
9867 branch_regs[i].wasconst&=~(1<<hr);
9868 branch_regs[i].isconst&=~(1<<hr);
9869 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9870 regmap_pre[i+2][hr]=f_regmap[hr];
9871 regs[i+2].wasdirty&=~(1<<hr);
9872 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
9873 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9874 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9879 regs[k].regmap_entry[hr]=f_regmap[hr];
9880 regs[k].regmap[hr]=f_regmap[hr];
9881 regmap_pre[k+1][hr]=f_regmap[hr];
9882 regs[k+1].wasdirty&=~(1<<hr);
9883 regs[k].dirty&=~(1<<hr);
9884 regs[k].wasconst&=~(1<<hr);
9885 regs[k].isconst&=~(1<<hr);
9887 if(regs[j].regmap[hr]==f_regmap[hr])
9888 regs[j].regmap_entry[hr]=f_regmap[hr];
9892 if(regs[j].regmap[hr]>=0)
9894 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9895 //printf("no-match due to different register\n");
9898 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9899 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9902 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9903 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9904 ||itype[j]==FCOMP||itype[j]==FCONV
9905 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9906 if(count_free_regs(regs[j].regmap)<2) {
9907 //printf("No free regs for store %x\n",start+j*4);
9911 else if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9912 if(f_regmap[hr]>=64) {
9913 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9918 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9930 for(hr=0;hr<HOST_REGS;hr++)
9932 if(hr!=EXCLUDE_REG) {
9933 if(regs[i].regmap[hr]>64) {
9934 if(!((regs[i].dirty>>hr)&1))
9935 f_regmap[hr]=regs[i].regmap[hr];
9937 else if(regs[i].regmap[hr]>=0) {
9938 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9939 // dealloc old register
9941 for(n=0;n<HOST_REGS;n++)
9943 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9945 // and alloc new one
9946 f_regmap[hr]=regs[i].regmap[hr];
9949 else if(regs[i].regmap[hr]<0) count++;
9952 // Try to restore cycle count at branch targets
9954 for(j=i;j<slen-1;j++) {
9955 if(regs[j].regmap[HOST_CCREG]!=-1) break;
9956 if(itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS
9957 ||itype[j]==SHIFT||itype[j]==COP1||itype[j]==FLOAT
9958 ||itype[j]==FCOMP||itype[j]==FCONV
9959 ||itype[j]==COP2||itype[j]==C2LS||itype[j]==C2OP) {
9960 if(count_free_regs(regs[j].regmap)<2) {
9961 //printf("no free regs for store %x\n",start+j*4);
9966 if(itype[j]!=NOP&&itype[j]!=MOV&&itype[j]!=ALU&&itype[j]!=SHIFTIMM&&itype[j]!=IMM16&&itype[j]!=LOAD) break;
9968 if(regs[j].regmap[HOST_CCREG]==CCREG) {
9970 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9972 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9973 regs[k].regmap[HOST_CCREG]=CCREG;
9974 regmap_pre[k+1][HOST_CCREG]=CCREG;
9975 regs[k+1].wasdirty|=1<<HOST_CCREG;
9976 regs[k].dirty|=1<<HOST_CCREG;
9977 regs[k].wasconst&=~(1<<HOST_CCREG);
9978 regs[k].isconst&=~(1<<HOST_CCREG);
9981 regs[j].regmap_entry[HOST_CCREG]=CCREG;
9983 // Work backwards from the branch target
9984 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9986 //printf("Extend backwards\n");
9989 while(regs[k-1].regmap[HOST_CCREG]==-1) {
9990 if(itype[k-1]==STORE||itype[k-1]==STORELR||itype[k-1]==C1LS
9991 ||itype[k-1]==SHIFT||itype[k-1]==COP1||itype[k-1]==FLOAT
9992 ||itype[k-1]==FCONV||itype[k-1]==FCOMP
9993 ||itype[k-1]==COP2||itype[k-1]==C2LS||itype[k-1]==C2OP) {
9994 if(count_free_regs(regs[k-1].regmap)<2) {
9995 //printf("no free regs for store %x\n",start+(k-1)*4);
10000 if(itype[k-1]!=NOP&&itype[k-1]!=MOV&&itype[k-1]!=ALU&&itype[k-1]!=SHIFTIMM&&itype[k-1]!=IMM16&&itype[k-1]!=LOAD) break;
10003 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10004 //printf("Extend CC, %x ->\n",start+k*4);
10006 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10007 regs[k].regmap[HOST_CCREG]=CCREG;
10008 regmap_pre[k+1][HOST_CCREG]=CCREG;
10009 regs[k+1].wasdirty|=1<<HOST_CCREG;
10010 regs[k].dirty|=1<<HOST_CCREG;
10011 regs[k].wasconst&=~(1<<HOST_CCREG);
10012 regs[k].isconst&=~(1<<HOST_CCREG);
10017 //printf("Fail Extend CC, %x ->\n",start+k*4);
10021 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10022 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10023 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10024 itype[i]!=FCONV&&itype[i]!=FCOMP&&
10025 itype[i]!=COP2&&itype[i]!=C2LS&&itype[i]!=C2OP)
10027 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10032 // This allocates registers (if possible) one instruction prior
10033 // to use, which can avoid a load-use penalty on certain CPUs.
10034 for(i=0;i<slen-1;i++)
10036 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10040 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10041 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10044 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10046 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10048 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10049 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10050 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10051 regs[i].isconst&=~(1<<hr);
10052 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10053 constmap[i][hr]=constmap[i+1][hr];
10054 regs[i+1].wasdirty&=~(1<<hr);
10055 regs[i].dirty&=~(1<<hr);
10060 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10062 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10064 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10065 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10066 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10067 regs[i].isconst&=~(1<<hr);
10068 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10069 constmap[i][hr]=constmap[i+1][hr];
10070 regs[i+1].wasdirty&=~(1<<hr);
10071 regs[i].dirty&=~(1<<hr);
10075 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10076 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10078 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10080 regs[i].regmap[hr]=rs1[i+1];
10081 regmap_pre[i+1][hr]=rs1[i+1];
10082 regs[i+1].regmap_entry[hr]=rs1[i+1];
10083 regs[i].isconst&=~(1<<hr);
10084 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10085 constmap[i][hr]=constmap[i+1][hr];
10086 regs[i+1].wasdirty&=~(1<<hr);
10087 regs[i].dirty&=~(1<<hr);
10091 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10092 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10094 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10096 regs[i].regmap[hr]=rs1[i+1];
10097 regmap_pre[i+1][hr]=rs1[i+1];
10098 regs[i+1].regmap_entry[hr]=rs1[i+1];
10099 regs[i].isconst&=~(1<<hr);
10100 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10101 constmap[i][hr]=constmap[i+1][hr];
10102 regs[i+1].wasdirty&=~(1<<hr);
10103 regs[i].dirty&=~(1<<hr);
10107 #ifndef HOST_IMM_ADDR32
10108 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10109 hr=get_reg(regs[i+1].regmap,TLREG);
10111 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10112 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10114 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10116 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10117 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10118 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10119 regs[i].isconst&=~(1<<hr);
10120 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10121 constmap[i][hr]=constmap[i+1][hr];
10122 regs[i+1].wasdirty&=~(1<<hr);
10123 regs[i].dirty&=~(1<<hr);
10125 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10127 // move it to another register
10128 regs[i+1].regmap[hr]=-1;
10129 regmap_pre[i+2][hr]=-1;
10130 regs[i+1].regmap[nr]=TLREG;
10131 regmap_pre[i+2][nr]=TLREG;
10132 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10133 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10134 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10135 regs[i].isconst&=~(1<<nr);
10136 regs[i+1].isconst&=~(1<<nr);
10137 regs[i].dirty&=~(1<<nr);
10138 regs[i+1].wasdirty&=~(1<<nr);
10139 regs[i+1].dirty&=~(1<<nr);
10140 regs[i+2].wasdirty&=~(1<<nr);
10146 if(itype[i+1]==STORE||itype[i+1]==STORELR
10147 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10148 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10149 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10150 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10151 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10153 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10155 regs[i].regmap[hr]=rs1[i+1];
10156 regmap_pre[i+1][hr]=rs1[i+1];
10157 regs[i+1].regmap_entry[hr]=rs1[i+1];
10158 regs[i].isconst&=~(1<<hr);
10159 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10160 constmap[i][hr]=constmap[i+1][hr];
10161 regs[i+1].wasdirty&=~(1<<hr);
10162 regs[i].dirty&=~(1<<hr);
10166 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10167 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10169 hr=get_reg(regs[i+1].regmap,FTEMP);
10171 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10173 regs[i].regmap[hr]=rs1[i+1];
10174 regmap_pre[i+1][hr]=rs1[i+1];
10175 regs[i+1].regmap_entry[hr]=rs1[i+1];
10176 regs[i].isconst&=~(1<<hr);
10177 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10178 constmap[i][hr]=constmap[i+1][hr];
10179 regs[i+1].wasdirty&=~(1<<hr);
10180 regs[i].dirty&=~(1<<hr);
10182 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10184 // move it to another register
10185 regs[i+1].regmap[hr]=-1;
10186 regmap_pre[i+2][hr]=-1;
10187 regs[i+1].regmap[nr]=FTEMP;
10188 regmap_pre[i+2][nr]=FTEMP;
10189 regs[i].regmap[nr]=rs1[i+1];
10190 regmap_pre[i+1][nr]=rs1[i+1];
10191 regs[i+1].regmap_entry[nr]=rs1[i+1];
10192 regs[i].isconst&=~(1<<nr);
10193 regs[i+1].isconst&=~(1<<nr);
10194 regs[i].dirty&=~(1<<nr);
10195 regs[i+1].wasdirty&=~(1<<nr);
10196 regs[i+1].dirty&=~(1<<nr);
10197 regs[i+2].wasdirty&=~(1<<nr);
10201 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10202 if(itype[i+1]==LOAD)
10203 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10204 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10205 hr=get_reg(regs[i+1].regmap,FTEMP);
10206 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10207 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10208 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10210 if(hr>=0&®s[i].regmap[hr]<0) {
10211 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10212 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10213 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10214 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10215 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10216 regs[i].isconst&=~(1<<hr);
10217 regs[i+1].wasdirty&=~(1<<hr);
10218 regs[i].dirty&=~(1<<hr);
10227 /* Pass 6 - Optimize clean/dirty state */
10228 clean_registers(0,slen-1,1);
10230 /* Pass 7 - Identify 32-bit registers */
10236 for (i=slen-1;i>=0;i--)
10239 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10241 if(ba[i]<start || ba[i]>=(start+slen*4))
10243 // Branch out of this block, don't need anything
10249 // Need whatever matches the target
10250 // (and doesn't get overwritten by the delay slot instruction)
10252 int t=(ba[i]-start)>>2;
10253 if(ba[i]>start+i*4) {
10255 if(!(requires_32bit[t]&~regs[i].was32))
10256 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10259 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10260 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10261 if(!(pr32[t]&~regs[i].was32))
10262 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10265 // Conditional branch may need registers for following instructions
10266 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10269 r32|=requires_32bit[i+2];
10270 r32&=regs[i].was32;
10271 // Mark this address as a branch target since it may be called
10272 // upon return from interrupt
10276 // Merge in delay slot
10278 // These are overwritten unless the branch is "likely"
10279 // and the delay slot is nullified if not taken
10280 r32&=~(1LL<<rt1[i+1]);
10281 r32&=~(1LL<<rt2[i+1]);
10283 // Assume these are needed (delay slot)
10286 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10290 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10292 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10294 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10296 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10298 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10301 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10303 // SYSCALL instruction (software interrupt)
10306 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10308 // ERET instruction (return from interrupt)
10312 r32&=~(1LL<<rt1[i]);
10313 r32&=~(1LL<<rt2[i]);
10316 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10320 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10322 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10324 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10326 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10328 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10330 requires_32bit[i]=r32;
10332 // Dirty registers which are 32-bit, require 32-bit input
10333 // as they will be written as 32-bit values
10334 for(hr=0;hr<HOST_REGS;hr++)
10336 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10337 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10338 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10339 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10343 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10346 if(itype[slen-1]==SPAN) {
10347 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10350 /* Debug/disassembly */
10351 if((void*)assem_debug==(void*)printf)
10352 for(i=0;i<slen;i++)
10356 for(r=1;r<=CCREG;r++) {
10357 if((unneeded_reg[i]>>r)&1) {
10358 if(r==HIREG) printf(" HI");
10359 else if(r==LOREG) printf(" LO");
10360 else printf(" r%d",r);
10365 for(r=1;r<=CCREG;r++) {
10366 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10367 if(r==HIREG) printf(" HI");
10368 else if(r==LOREG) printf(" LO");
10369 else printf(" r%d",r);
10373 for(r=0;r<=CCREG;r++) {
10374 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10375 if((regs[i].was32>>r)&1) {
10376 if(r==CCREG) printf(" CC");
10377 else if(r==HIREG) printf(" HI");
10378 else if(r==LOREG) printf(" LO");
10379 else printf(" r%d",r);
10384 #if defined(__i386__) || defined(__x86_64__)
10385 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
10388 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
10391 if(needed_reg[i]&1) printf("eax ");
10392 if((needed_reg[i]>>1)&1) printf("ecx ");
10393 if((needed_reg[i]>>2)&1) printf("edx ");
10394 if((needed_reg[i]>>3)&1) printf("ebx ");
10395 if((needed_reg[i]>>5)&1) printf("ebp ");
10396 if((needed_reg[i]>>6)&1) printf("esi ");
10397 if((needed_reg[i]>>7)&1) printf("edi ");
10399 for(r=0;r<=CCREG;r++) {
10400 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10401 if((requires_32bit[i]>>r)&1) {
10402 if(r==CCREG) printf(" CC");
10403 else if(r==HIREG) printf(" HI");
10404 else if(r==LOREG) printf(" LO");
10405 else printf(" r%d",r);
10410 for(r=0;r<=CCREG;r++) {
10411 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
10412 if((pr32[i]>>r)&1) {
10413 if(r==CCREG) printf(" CC");
10414 else if(r==HIREG) printf(" HI");
10415 else if(r==LOREG) printf(" LO");
10416 else printf(" r%d",r);
10419 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
10421 #if defined(__i386__) || defined(__x86_64__)
10422 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
10424 if(regs[i].wasdirty&1) printf("eax ");
10425 if((regs[i].wasdirty>>1)&1) printf("ecx ");
10426 if((regs[i].wasdirty>>2)&1) printf("edx ");
10427 if((regs[i].wasdirty>>3)&1) printf("ebx ");
10428 if((regs[i].wasdirty>>5)&1) printf("ebp ");
10429 if((regs[i].wasdirty>>6)&1) printf("esi ");
10430 if((regs[i].wasdirty>>7)&1) printf("edi ");
10433 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
10435 if(regs[i].wasdirty&1) printf("r0 ");
10436 if((regs[i].wasdirty>>1)&1) printf("r1 ");
10437 if((regs[i].wasdirty>>2)&1) printf("r2 ");
10438 if((regs[i].wasdirty>>3)&1) printf("r3 ");
10439 if((regs[i].wasdirty>>4)&1) printf("r4 ");
10440 if((regs[i].wasdirty>>5)&1) printf("r5 ");
10441 if((regs[i].wasdirty>>6)&1) printf("r6 ");
10442 if((regs[i].wasdirty>>7)&1) printf("r7 ");
10443 if((regs[i].wasdirty>>8)&1) printf("r8 ");
10444 if((regs[i].wasdirty>>9)&1) printf("r9 ");
10445 if((regs[i].wasdirty>>10)&1) printf("r10 ");
10446 if((regs[i].wasdirty>>12)&1) printf("r12 ");
10449 disassemble_inst(i);
10450 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
10451 #if defined(__i386__) || defined(__x86_64__)
10452 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
10453 if(regs[i].dirty&1) printf("eax ");
10454 if((regs[i].dirty>>1)&1) printf("ecx ");
10455 if((regs[i].dirty>>2)&1) printf("edx ");
10456 if((regs[i].dirty>>3)&1) printf("ebx ");
10457 if((regs[i].dirty>>5)&1) printf("ebp ");
10458 if((regs[i].dirty>>6)&1) printf("esi ");
10459 if((regs[i].dirty>>7)&1) printf("edi ");
10462 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
10463 if(regs[i].dirty&1) printf("r0 ");
10464 if((regs[i].dirty>>1)&1) printf("r1 ");
10465 if((regs[i].dirty>>2)&1) printf("r2 ");
10466 if((regs[i].dirty>>3)&1) printf("r3 ");
10467 if((regs[i].dirty>>4)&1) printf("r4 ");
10468 if((regs[i].dirty>>5)&1) printf("r5 ");
10469 if((regs[i].dirty>>6)&1) printf("r6 ");
10470 if((regs[i].dirty>>7)&1) printf("r7 ");
10471 if((regs[i].dirty>>8)&1) printf("r8 ");
10472 if((regs[i].dirty>>9)&1) printf("r9 ");
10473 if((regs[i].dirty>>10)&1) printf("r10 ");
10474 if((regs[i].dirty>>12)&1) printf("r12 ");
10477 if(regs[i].isconst) {
10478 printf("constants: ");
10479 #if defined(__i386__) || defined(__x86_64__)
10480 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
10481 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
10482 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
10483 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
10484 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
10485 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
10486 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
10489 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
10490 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
10491 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
10492 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
10493 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
10494 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
10495 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
10496 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
10497 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
10498 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
10499 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
10500 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
10506 for(r=0;r<=CCREG;r++) {
10507 if((regs[i].is32>>r)&1) {
10508 if(r==CCREG) printf(" CC");
10509 else if(r==HIREG) printf(" HI");
10510 else if(r==LOREG) printf(" LO");
10511 else printf(" r%d",r);
10517 for(r=0;r<=CCREG;r++) {
10518 if((p32[i]>>r)&1) {
10519 if(r==CCREG) printf(" CC");
10520 else if(r==HIREG) printf(" HI");
10521 else if(r==LOREG) printf(" LO");
10522 else printf(" r%d",r);
10525 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
10526 else printf("\n");*/
10527 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10528 #if defined(__i386__) || defined(__x86_64__)
10529 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
10530 if(branch_regs[i].dirty&1) printf("eax ");
10531 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
10532 if((branch_regs[i].dirty>>2)&1) printf("edx ");
10533 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
10534 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
10535 if((branch_regs[i].dirty>>6)&1) printf("esi ");
10536 if((branch_regs[i].dirty>>7)&1) printf("edi ");
10539 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
10540 if(branch_regs[i].dirty&1) printf("r0 ");
10541 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
10542 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
10543 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
10544 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
10545 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
10546 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
10547 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
10548 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
10549 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
10550 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
10551 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
10555 for(r=0;r<=CCREG;r++) {
10556 if((branch_regs[i].is32>>r)&1) {
10557 if(r==CCREG) printf(" CC");
10558 else if(r==HIREG) printf(" HI");
10559 else if(r==LOREG) printf(" LO");
10560 else printf(" r%d",r);
10568 /* Pass 8 - Assembly */
10569 linkcount=0;stubcount=0;
10570 ds=0;is_delayslot=0;
10572 uint64_t is32_pre=0;
10574 u_int beginning=(u_int)out;
10575 if((u_int)addr&1) {
10579 u_int instr_addr0_override=0;
10582 if (start == 0x80030000) {
10583 // nasty hack for fastbios thing
10584 instr_addr0_override=(u_int)out;
10585 emit_movimm(start,0);
10586 emit_readword((int)&pcaddr,1);
10587 emit_writeword(0,(int)&pcaddr);
10589 emit_jne((int)new_dyna_leave);
10592 for(i=0;i<slen;i++)
10594 //if(ds) printf("ds: ");
10595 if((void*)assem_debug==(void*)printf) disassemble_inst(i);
10597 ds=0; // Skip delay slot
10598 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
10601 #ifndef DESTRUCTIVE_WRITEBACK
10602 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10604 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
10605 unneeded_reg[i],unneeded_reg_upper[i]);
10606 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
10607 unneeded_reg[i],unneeded_reg_upper[i]);
10609 is32_pre=regs[i].is32;
10610 dirty_pre=regs[i].dirty;
10613 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
10615 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
10616 unneeded_reg[i],unneeded_reg_upper[i]);
10617 loop_preload(regmap_pre[i],regs[i].regmap_entry);
10619 // branch target entry point
10620 instr_addr[i]=(u_int)out;
10621 assem_debug("<->\n");
10623 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
10624 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
10625 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
10626 address_generation(i,®s[i],regs[i].regmap_entry);
10627 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
10628 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10630 // Load the delay slot registers if necessary
10631 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10632 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10633 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10634 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10635 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
10636 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10640 // Preload registers for following instruction
10641 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
10642 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
10643 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
10644 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
10645 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
10646 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
10648 // TODO: if(is_ooo(i)) address_generation(i+1);
10649 if(itype[i]==CJUMP||itype[i]==FJUMP)
10650 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
10651 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
10652 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
10653 if(bt[i]) cop1_usable=0;
10657 alu_assemble(i,®s[i]);break;
10659 imm16_assemble(i,®s[i]);break;
10661 shift_assemble(i,®s[i]);break;
10663 shiftimm_assemble(i,®s[i]);break;
10665 load_assemble(i,®s[i]);break;
10667 loadlr_assemble(i,®s[i]);break;
10669 store_assemble(i,®s[i]);break;
10671 storelr_assemble(i,®s[i]);break;
10673 cop0_assemble(i,®s[i]);break;
10675 cop1_assemble(i,®s[i]);break;
10677 c1ls_assemble(i,®s[i]);break;
10679 cop2_assemble(i,®s[i]);break;
10681 c2ls_assemble(i,®s[i]);break;
10683 c2op_assemble(i,®s[i]);break;
10685 fconv_assemble(i,®s[i]);break;
10687 float_assemble(i,®s[i]);break;
10689 fcomp_assemble(i,®s[i]);break;
10691 multdiv_assemble(i,®s[i]);break;
10693 mov_assemble(i,®s[i]);break;
10695 syscall_assemble(i,®s[i]);break;
10697 hlecall_assemble(i,®s[i]);break;
10699 intcall_assemble(i,®s[i]);break;
10701 ujump_assemble(i,®s[i]);ds=1;break;
10703 rjump_assemble(i,®s[i]);ds=1;break;
10705 cjump_assemble(i,®s[i]);ds=1;break;
10707 sjump_assemble(i,®s[i]);ds=1;break;
10709 fjump_assemble(i,®s[i]);ds=1;break;
10711 pagespan_assemble(i,®s[i]);break;
10713 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10714 literal_pool(1024);
10716 literal_pool_jumpover(256);
10719 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10720 // If the block did not end with an unconditional branch,
10721 // add a jump to the next instruction.
10723 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10724 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10726 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10727 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10728 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10729 emit_loadreg(CCREG,HOST_CCREG);
10730 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10732 else if(!likely[i-2])
10734 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10735 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10739 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10740 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10742 add_to_linker((int)out,start+i*4,0);
10749 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10750 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10751 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10752 emit_loadreg(CCREG,HOST_CCREG);
10753 emit_addimm(HOST_CCREG,CLOCK_DIVIDER*(ccadj[i-1]+1),HOST_CCREG);
10754 add_to_linker((int)out,start+i*4,0);
10758 // TODO: delay slot stubs?
10760 for(i=0;i<stubcount;i++)
10762 switch(stubs[i][0])
10770 do_readstub(i);break;
10775 do_writestub(i);break;
10777 do_ccstub(i);break;
10779 do_invstub(i);break;
10781 do_cop1stub(i);break;
10783 do_unalignedwritestub(i);break;
10787 if (instr_addr0_override)
10788 instr_addr[0] = instr_addr0_override;
10790 /* Pass 9 - Linker */
10791 for(i=0;i<linkcount;i++)
10793 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10795 if(!link_addr[i][2])
10798 void *addr=check_addr(link_addr[i][1]);
10799 emit_extjump(link_addr[i][0],link_addr[i][1]);
10801 set_jump_target(link_addr[i][0],(int)addr);
10802 add_link(link_addr[i][1],stub);
10804 else set_jump_target(link_addr[i][0],(int)stub);
10809 int target=(link_addr[i][1]-start)>>2;
10810 assert(target>=0&&target<slen);
10811 assert(instr_addr[target]);
10812 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10813 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10815 set_jump_target(link_addr[i][0],instr_addr[target]);
10819 // External Branch Targets (jump_in)
10820 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10821 for(i=0;i<slen;i++)
10825 if(instr_addr[i]) // TODO - delay slots (=null)
10827 u_int vaddr=start+i*4;
10828 u_int page=get_page(vaddr);
10829 u_int vpage=get_vpage(vaddr);
10831 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
10832 if(!requires_32bit[i])
10834 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10835 assem_debug("jump_in: %x\n",start+i*4);
10836 ll_add(jump_dirty+vpage,vaddr,(void *)out);
10837 int entry_point=do_dirty_stub(i);
10838 ll_add(jump_in+page,vaddr,(void *)entry_point);
10839 // If there was an existing entry in the hash table,
10840 // replace it with the new address.
10841 // Don't add new entries. We'll insert the
10842 // ones that actually get used in check_addr().
10843 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
10844 if(ht_bin[0]==vaddr) {
10845 ht_bin[1]=entry_point;
10847 if(ht_bin[2]==vaddr) {
10848 ht_bin[3]=entry_point;
10853 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
10854 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10855 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
10856 //int entry_point=(int)out;
10857 ////assem_debug("entry_point: %x\n",entry_point);
10858 //load_regs_entry(i);
10859 //if(entry_point==(int)out)
10860 // entry_point=instr_addr[i];
10862 // emit_jmp(instr_addr[i]);
10863 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10864 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
10865 int entry_point=do_dirty_stub(i);
10866 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
10871 // Write out the literal pool if necessary
10873 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10875 if(((u_int)out)&7) emit_addnop(13);
10877 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
10878 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10879 memcpy(copy,source,slen*4);
10883 __clear_cache((void *)beginning,out);
10886 // If we're within 256K of the end of the buffer,
10887 // start over from the beginning. (Is 256K enough?)
10888 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10890 // Trap writes to any of the pages we compiled
10891 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10893 #ifndef DISABLE_TLB
10894 memory_map[i]|=0x40000000;
10895 if((signed int)start>=(signed int)0xC0000000) {
10897 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
10899 memory_map[j]|=0x40000000;
10900 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
10905 /* Pass 10 - Free memory by expiring oldest blocks */
10907 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10908 while(expirep!=end)
10910 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10911 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10912 inv_debug("EXP: Phase %d\n",expirep);
10913 switch((expirep>>11)&3)
10916 // Clear jump_in and jump_dirty
10917 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10918 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10919 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10920 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10924 ll_kill_pointers(jump_out[expirep&2047],base,shift);
10925 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10928 // Clear hash table
10929 for(i=0;i<32;i++) {
10930 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
10931 if((ht_bin[3]>>shift)==(base>>shift) ||
10932 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10933 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
10934 ht_bin[2]=ht_bin[3]=-1;
10936 if((ht_bin[1]>>shift)==(base>>shift) ||
10937 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10938 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
10939 ht_bin[0]=ht_bin[2];
10940 ht_bin[1]=ht_bin[3];
10941 ht_bin[2]=ht_bin[3]=-1;
10947 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10948 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10951 expirep=(expirep+1)&65535;
10956 // vim:shiftwidth=2:expandtab