1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
44 #ifdef __BLACKBERRY_QNX__
46 #define __clear_cache(start,end) msync(start, (size_t)((void*)end - (void*)start), MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
47 #elif defined(__MACH__)
48 #include <libkern/OSCacheControl.h>
49 #define __clear_cache mach_clear_cache
50 static void __clear_cache(void *start, void *end) {
51 size_t len = (char *)end - (char *)start;
52 sys_dcache_flush(start, len);
53 sys_icache_invalidate(start, len);
58 #define MAX_OUTPUT_BLOCK_SIZE 262144
62 signed char regmap_entry[HOST_REGS];
63 signed char regmap[HOST_REGS];
72 u_int loadedconst; // host regs that have constants loaded
73 u_int waswritten; // MIPS regs that were used as store base before
81 struct ll_entry *next;
87 char insn[MAXBLOCK][10];
88 u_char itype[MAXBLOCK];
89 u_char opcode[MAXBLOCK];
90 u_char opcode2[MAXBLOCK];
98 u_char dep1[MAXBLOCK];
99 u_char dep2[MAXBLOCK];
100 u_char lt1[MAXBLOCK];
101 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
102 static uint64_t gte_rt[MAXBLOCK];
103 static uint64_t gte_unneeded[MAXBLOCK];
104 static u_int smrv[32]; // speculated MIPS register values
105 static u_int smrv_strong; // mask or regs that are likely to have correct values
106 static u_int smrv_weak; // same, but somewhat less likely
107 static u_int smrv_strong_next; // same, but after current insn executes
108 static u_int smrv_weak_next;
111 char likely[MAXBLOCK];
112 char is_ds[MAXBLOCK];
114 uint64_t unneeded_reg[MAXBLOCK];
115 uint64_t unneeded_reg_upper[MAXBLOCK];
116 uint64_t branch_unneeded_reg[MAXBLOCK];
117 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
118 uint64_t p32[MAXBLOCK];
119 uint64_t pr32[MAXBLOCK];
120 signed char regmap_pre[MAXBLOCK][HOST_REGS];
121 static uint64_t current_constmap[HOST_REGS];
122 static uint64_t constmap[MAXBLOCK][HOST_REGS];
123 static struct regstat regs[MAXBLOCK];
124 static struct regstat branch_regs[MAXBLOCK];
125 signed char minimum_free_regs[MAXBLOCK];
126 u_int needed_reg[MAXBLOCK];
127 uint64_t requires_32bit[MAXBLOCK];
128 u_int wont_dirty[MAXBLOCK];
129 u_int will_dirty[MAXBLOCK];
132 u_int instr_addr[MAXBLOCK];
133 u_int link_addr[MAXBLOCK][3];
135 u_int stubs[MAXBLOCK*3][8];
137 u_int literals[1024][2];
142 struct ll_entry *jump_in[4096];
143 struct ll_entry *jump_out[4096];
144 struct ll_entry *jump_dirty[4096];
145 u_int hash_table[65536][4] __attribute__((aligned(16)));
146 char shadow[1048576] __attribute__((aligned(16)));
152 static const u_int using_tlb=0;
154 int new_dynarec_did_compile;
155 int new_dynarec_hacks;
156 u_int stop_after_jal;
158 static u_int ram_offset;
160 static const u_int ram_offset=0;
162 extern u_char restore_candidate[512];
163 extern int cycle_count;
165 /* registers that may be allocated */
167 #define HIREG 32 // hi
168 #define LOREG 33 // lo
169 #define FSREG 34 // FPU status (FCSR)
170 #define CSREG 35 // Coprocessor status
171 #define CCREG 36 // Cycle count
172 #define INVCP 37 // Pointer to invalid_code
173 #define MMREG 38 // Pointer to memory_map
174 #define ROREG 39 // ram offset (if rdram!=0x80000000)
176 #define FTEMP 40 // FPU temporary register
177 #define PTEMP 41 // Prefetch temporary register
178 #define TLREG 42 // TLB mapping offset
179 #define RHASH 43 // Return address hash
180 #define RHTBL 44 // Return address hash table address
181 #define RTEMP 45 // JR/JALR address register
183 #define AGEN1 46 // Address generation temporary register
184 #define AGEN2 47 // Address generation temporary register
185 #define MGEN1 48 // Maptable address generation temporary register
186 #define MGEN2 49 // Maptable address generation temporary register
187 #define BTREG 50 // Branch target temporary register
189 /* instruction types */
190 #define NOP 0 // No operation
191 #define LOAD 1 // Load
192 #define STORE 2 // Store
193 #define LOADLR 3 // Unaligned load
194 #define STORELR 4 // Unaligned store
195 #define MOV 5 // Move
196 #define ALU 6 // Arithmetic/logic
197 #define MULTDIV 7 // Multiply/divide
198 #define SHIFT 8 // Shift by register
199 #define SHIFTIMM 9// Shift by immediate
200 #define IMM16 10 // 16-bit immediate
201 #define RJUMP 11 // Unconditional jump to register
202 #define UJUMP 12 // Unconditional jump
203 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
204 #define SJUMP 14 // Conditional branch (regimm format)
205 #define COP0 15 // Coprocessor 0
206 #define COP1 16 // Coprocessor 1
207 #define C1LS 17 // Coprocessor 1 load/store
208 #define FJUMP 18 // Conditional branch (floating point)
209 #define FLOAT 19 // Floating point unit
210 #define FCONV 20 // Convert integer to float
211 #define FCOMP 21 // Floating point compare (sets FSREG)
212 #define SYSCALL 22// SYSCALL
213 #define OTHER 23 // Other
214 #define SPAN 24 // Branch/delay slot spans 2 pages
215 #define NI 25 // Not implemented
216 #define HLECALL 26// PCSX fake opcodes for HLE
217 #define COP2 27 // Coprocessor 2 move
218 #define C2LS 28 // Coprocessor 2 load/store
219 #define C2OP 29 // Coprocessor 2 operation
220 #define INTCALL 30// Call interpreter to handle rare corner cases
229 #define LOADBU_STUB 7
230 #define LOADHU_STUB 8
231 #define STOREB_STUB 9
232 #define STOREH_STUB 10
233 #define STOREW_STUB 11
234 #define STORED_STUB 12
235 #define STORELR_STUB 13
236 #define INVCODE_STUB 14
244 int new_recompile_block(int addr);
245 void *get_addr_ht(u_int vaddr);
246 void invalidate_block(u_int block);
247 void invalidate_addr(u_int addr);
248 void remove_hash(int vaddr);
251 void dyna_linker_ds();
253 void verify_code_vm();
254 void verify_code_ds();
257 void fp_exception_ds();
259 void jump_syscall_hle();
263 void new_dyna_leave();
268 void read_nomem_new();
269 void read_nomemb_new();
270 void read_nomemh_new();
271 void read_nomemd_new();
272 void write_nomem_new();
273 void write_nomemb_new();
274 void write_nomemh_new();
275 void write_nomemd_new();
276 void write_rdram_new();
277 void write_rdramb_new();
278 void write_rdramh_new();
279 void write_rdramd_new();
280 extern u_int memory_map[1048576];
282 // Needed by assembler
283 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
284 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
285 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
286 void load_all_regs(signed char i_regmap[]);
287 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
288 void load_regs_entry(int t);
289 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
293 //#define DEBUG_CYCLE_COUNT 1
295 #define NO_CYCLE_PENALTY_THR 12
297 int cycle_multiplier; // 100 for 1.0
299 static int CLOCK_ADJUST(int x)
302 return (x * cycle_multiplier + s * 50) / 100;
305 static void tlb_hacks()
309 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
313 switch (ROM_HEADER->Country_code&0xFF)
325 // Unknown country code
329 u_int rom_addr=(u_int)rom;
331 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
332 // in the lower 4G of memory to use this hack. Copy it if necessary.
333 if((void *)rom>(void *)0xffffffff) {
334 munmap(ROM_COPY, 67108864);
335 if(mmap(ROM_COPY, 12582912,
336 PROT_READ | PROT_WRITE,
337 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
338 -1, 0) <= 0) {printf("mmap() failed\n");}
339 memcpy(ROM_COPY,rom,12582912);
340 rom_addr=(u_int)ROM_COPY;
344 for(n=0x7F000;n<0x80000;n++) {
345 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
352 static u_int get_page(u_int vaddr)
355 u_int page=(vaddr^0x80000000)>>12;
357 u_int page=vaddr&~0xe0000000;
358 if (page < 0x1000000)
359 page &= ~0x0e00000; // RAM mirrors
363 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
365 if(page>2048) page=2048+(page&2047);
370 static u_int get_vpage(u_int vaddr)
372 u_int vpage=(vaddr^0x80000000)>>12;
374 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
376 if(vpage>2048) vpage=2048+(vpage&2047);
380 // no virtual mem in PCSX
381 static u_int get_vpage(u_int vaddr)
383 return get_page(vaddr);
387 // Get address from virtual address
388 // This is called from the recompiled JR/JALR instructions
389 void *get_addr(u_int vaddr)
391 u_int page=get_page(vaddr);
392 u_int vpage=get_vpage(vaddr);
393 struct ll_entry *head;
394 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
397 if(head->vaddr==vaddr&&head->reg32==0) {
398 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
399 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
402 ht_bin[1]=(int)head->addr;
408 head=jump_dirty[vpage];
410 if(head->vaddr==vaddr&&head->reg32==0) {
411 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
412 // Don't restore blocks which are about to expire from the cache
413 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
414 if(verify_dirty(head->addr)) {
415 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
416 invalid_code[vaddr>>12]=0;
417 inv_code_start=inv_code_end=~0;
419 memory_map[vaddr>>12]|=0x40000000;
423 if(tlb_LUT_r[vaddr>>12]) {
424 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
425 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
428 restore_candidate[vpage>>3]|=1<<(vpage&7);
430 else restore_candidate[page>>3]|=1<<(page&7);
431 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
432 if(ht_bin[0]==vaddr) {
433 ht_bin[1]=(int)head->addr; // Replace existing entry
439 ht_bin[1]=(int)head->addr;
447 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
448 int r=new_recompile_block(vaddr);
449 if(r==0) return get_addr(vaddr);
450 // Execute in unmapped page, generate pagefault execption
452 Cause=(vaddr<<31)|0x8;
453 EPC=(vaddr&1)?vaddr-5:vaddr;
455 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
456 EntryHi=BadVAddr&0xFFFFE000;
457 return get_addr_ht(0x80000000);
459 // Look up address in hash table first
460 void *get_addr_ht(u_int vaddr)
462 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
463 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
464 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
465 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
466 return get_addr(vaddr);
469 void *get_addr_32(u_int vaddr,u_int flags)
472 return get_addr(vaddr);
474 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
475 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
476 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
477 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
478 u_int page=get_page(vaddr);
479 u_int vpage=get_vpage(vaddr);
480 struct ll_entry *head;
483 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
484 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
486 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
488 ht_bin[1]=(int)head->addr;
490 }else if(ht_bin[2]==-1) {
491 ht_bin[3]=(int)head->addr;
494 //ht_bin[3]=ht_bin[1];
495 //ht_bin[2]=ht_bin[0];
496 //ht_bin[1]=(int)head->addr;
503 head=jump_dirty[vpage];
505 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
506 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
507 // Don't restore blocks which are about to expire from the cache
508 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
509 if(verify_dirty(head->addr)) {
510 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
511 invalid_code[vaddr>>12]=0;
512 inv_code_start=inv_code_end=~0;
513 memory_map[vaddr>>12]|=0x40000000;
516 if(tlb_LUT_r[vaddr>>12]) {
517 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
518 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
521 restore_candidate[vpage>>3]|=1<<(vpage&7);
523 else restore_candidate[page>>3]|=1<<(page&7);
525 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
527 ht_bin[1]=(int)head->addr;
529 }else if(ht_bin[2]==-1) {
530 ht_bin[3]=(int)head->addr;
533 //ht_bin[3]=ht_bin[1];
534 //ht_bin[2]=ht_bin[0];
535 //ht_bin[1]=(int)head->addr;
543 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
544 int r=new_recompile_block(vaddr);
545 if(r==0) return get_addr(vaddr);
546 // Execute in unmapped page, generate pagefault execption
548 Cause=(vaddr<<31)|0x8;
549 EPC=(vaddr&1)?vaddr-5:vaddr;
551 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
552 EntryHi=BadVAddr&0xFFFFE000;
553 return get_addr_ht(0x80000000);
557 void clear_all_regs(signed char regmap[])
560 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
563 signed char get_reg(signed char regmap[],int r)
566 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
570 // Find a register that is available for two consecutive cycles
571 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
574 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
578 int count_free_regs(signed char regmap[])
582 for(hr=0;hr<HOST_REGS;hr++)
584 if(hr!=EXCLUDE_REG) {
585 if(regmap[hr]<0) count++;
591 void dirty_reg(struct regstat *cur,signed char reg)
595 for (hr=0;hr<HOST_REGS;hr++) {
596 if((cur->regmap[hr]&63)==reg) {
602 // If we dirty the lower half of a 64 bit register which is now being
603 // sign-extended, we need to dump the upper half.
604 // Note: Do this only after completion of the instruction, because
605 // some instructions may need to read the full 64-bit value even if
606 // overwriting it (eg SLTI, DSRA32).
607 static void flush_dirty_uppers(struct regstat *cur)
610 for (hr=0;hr<HOST_REGS;hr++) {
611 if((cur->dirty>>hr)&1) {
614 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
619 void set_const(struct regstat *cur,signed char reg,uint64_t value)
623 for (hr=0;hr<HOST_REGS;hr++) {
624 if(cur->regmap[hr]==reg) {
626 current_constmap[hr]=value;
628 else if((cur->regmap[hr]^64)==reg) {
630 current_constmap[hr]=value>>32;
635 void clear_const(struct regstat *cur,signed char reg)
639 for (hr=0;hr<HOST_REGS;hr++) {
640 if((cur->regmap[hr]&63)==reg) {
641 cur->isconst&=~(1<<hr);
646 int is_const(struct regstat *cur,signed char reg)
651 for (hr=0;hr<HOST_REGS;hr++) {
652 if((cur->regmap[hr]&63)==reg) {
653 return (cur->isconst>>hr)&1;
658 uint64_t get_const(struct regstat *cur,signed char reg)
662 for (hr=0;hr<HOST_REGS;hr++) {
663 if(cur->regmap[hr]==reg) {
664 return current_constmap[hr];
667 SysPrintf("Unknown constant in r%d\n",reg);
671 // Least soon needed registers
672 // Look at the next ten instructions and see which registers
673 // will be used. Try not to reallocate these.
674 void lsn(u_char hsn[], int i, int *preferred_reg)
684 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
686 // Don't go past an unconditonal jump
693 if(rs1[i+j]) hsn[rs1[i+j]]=j;
694 if(rs2[i+j]) hsn[rs2[i+j]]=j;
695 if(rt1[i+j]) hsn[rt1[i+j]]=j;
696 if(rt2[i+j]) hsn[rt2[i+j]]=j;
697 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
698 // Stores can allocate zero
702 // On some architectures stores need invc_ptr
703 #if defined(HOST_IMM8)
704 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
708 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
716 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
718 // Follow first branch
719 int t=(ba[i+b]-start)>>2;
720 j=7-b;if(t+j>=slen) j=slen-t-1;
723 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
724 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
725 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
726 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
729 // TODO: preferred register based on backward branch
731 // Delay slot should preferably not overwrite branch conditions or cycle count
732 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
733 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
734 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
740 // Coprocessor load/store needs FTEMP, even if not declared
741 if(itype[i]==C1LS||itype[i]==C2LS) {
744 // Load L/R also uses FTEMP as a temporary register
745 if(itype[i]==LOADLR) {
748 // Also SWL/SWR/SDL/SDR
749 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
752 // Don't remove the TLB registers either
753 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
756 // Don't remove the miniht registers
757 if(itype[i]==UJUMP||itype[i]==RJUMP)
764 // We only want to allocate registers if we're going to use them again soon
765 int needed_again(int r, int i)
771 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
773 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
774 return 0; // Don't need any registers if exiting the block
782 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
784 // Don't go past an unconditonal jump
788 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
795 if(rs1[i+j]==r) rn=j;
796 if(rs2[i+j]==r) rn=j;
797 if((unneeded_reg[i+j]>>r)&1) rn=10;
798 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
806 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
808 // Follow first branch
810 int t=(ba[i+b]-start)>>2;
811 j=7-b;if(t+j>=slen) j=slen-t-1;
814 if(!((unneeded_reg[t+j]>>r)&1)) {
815 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
816 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
826 // Try to match register allocations at the end of a loop with those
828 int loop_reg(int i, int r, int hr)
837 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
839 // Don't go past an unconditonal jump
846 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
851 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
852 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
853 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
855 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
857 int t=(ba[i+k]-start)>>2;
858 int reg=get_reg(regs[t].regmap_entry,r);
859 if(reg>=0) return reg;
860 //reg=get_reg(regs[t+1].regmap_entry,r);
861 //if(reg>=0) return reg;
869 // Allocate every register, preserving source/target regs
870 void alloc_all(struct regstat *cur,int i)
874 for(hr=0;hr<HOST_REGS;hr++) {
875 if(hr!=EXCLUDE_REG) {
876 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
877 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
880 cur->dirty&=~(1<<hr);
883 if((cur->regmap[hr]&63)==0)
886 cur->dirty&=~(1<<hr);
893 void div64(int64_t dividend,int64_t divisor)
897 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
898 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
900 void divu64(uint64_t dividend,uint64_t divisor)
904 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
905 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
908 void mult64(uint64_t m1,uint64_t m2)
910 unsigned long long int op1, op2, op3, op4;
911 unsigned long long int result1, result2, result3, result4;
912 unsigned long long int temp1, temp2, temp3, temp4;
928 op1 = op2 & 0xFFFFFFFF;
929 op2 = (op2 >> 32) & 0xFFFFFFFF;
930 op3 = op4 & 0xFFFFFFFF;
931 op4 = (op4 >> 32) & 0xFFFFFFFF;
934 temp2 = (temp1 >> 32) + op1 * op4;
936 temp4 = (temp3 >> 32) + op2 * op4;
938 result1 = temp1 & 0xFFFFFFFF;
939 result2 = temp2 + (temp3 & 0xFFFFFFFF);
940 result3 = (result2 >> 32) + temp4;
941 result4 = (result3 >> 32);
943 lo = result1 | (result2 << 32);
944 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
953 void multu64(uint64_t m1,uint64_t m2)
955 unsigned long long int op1, op2, op3, op4;
956 unsigned long long int result1, result2, result3, result4;
957 unsigned long long int temp1, temp2, temp3, temp4;
959 op1 = m1 & 0xFFFFFFFF;
960 op2 = (m1 >> 32) & 0xFFFFFFFF;
961 op3 = m2 & 0xFFFFFFFF;
962 op4 = (m2 >> 32) & 0xFFFFFFFF;
965 temp2 = (temp1 >> 32) + op1 * op4;
967 temp4 = (temp3 >> 32) + op2 * op4;
969 result1 = temp1 & 0xFFFFFFFF;
970 result2 = temp2 + (temp3 & 0xFFFFFFFF);
971 result3 = (result2 >> 32) + temp4;
972 result4 = (result3 >> 32);
974 lo = result1 | (result2 << 32);
975 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
977 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
978 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
981 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
989 else original=loaded;
992 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
995 original>>=64-(bits^56);
996 original<<=64-(bits^56);
1000 else original=loaded;
1006 #include "assem_x86.c"
1009 #include "assem_x64.c"
1012 #include "assem_arm.c"
1015 // Add virtual address mapping to linked list
1016 void ll_add(struct ll_entry **head,int vaddr,void *addr)
1018 struct ll_entry *new_entry;
1019 new_entry=malloc(sizeof(struct ll_entry));
1020 assert(new_entry!=NULL);
1021 new_entry->vaddr=vaddr;
1023 new_entry->addr=addr;
1024 new_entry->next=*head;
1028 // Add virtual address mapping for 32-bit compiled block
1029 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1031 ll_add(head,vaddr,addr);
1033 (*head)->reg32=reg32;
1037 // Check if an address is already compiled
1038 // but don't return addresses which are about to expire from the cache
1039 void *check_addr(u_int vaddr)
1041 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1042 if(ht_bin[0]==vaddr) {
1043 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1044 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1046 if(ht_bin[2]==vaddr) {
1047 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1048 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1050 u_int page=get_page(vaddr);
1051 struct ll_entry *head;
1054 if(head->vaddr==vaddr&&head->reg32==0) {
1055 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1056 // Update existing entry with current address
1057 if(ht_bin[0]==vaddr) {
1058 ht_bin[1]=(int)head->addr;
1061 if(ht_bin[2]==vaddr) {
1062 ht_bin[3]=(int)head->addr;
1065 // Insert into hash table with low priority.
1066 // Don't evict existing entries, as they are probably
1067 // addresses that are being accessed frequently.
1069 ht_bin[1]=(int)head->addr;
1071 }else if(ht_bin[2]==-1) {
1072 ht_bin[3]=(int)head->addr;
1083 void remove_hash(int vaddr)
1085 //printf("remove hash: %x\n",vaddr);
1086 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1087 if(ht_bin[2]==vaddr) {
1088 ht_bin[2]=ht_bin[3]=-1;
1090 if(ht_bin[0]==vaddr) {
1091 ht_bin[0]=ht_bin[2];
1092 ht_bin[1]=ht_bin[3];
1093 ht_bin[2]=ht_bin[3]=-1;
1097 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1099 struct ll_entry *next;
1101 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1102 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1104 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1105 remove_hash((*head)->vaddr);
1112 head=&((*head)->next);
1117 // Remove all entries from linked list
1118 void ll_clear(struct ll_entry **head)
1120 struct ll_entry *cur;
1121 struct ll_entry *next;
1132 // Dereference the pointers and remove if it matches
1133 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1136 int ptr=get_pointer(head->addr);
1137 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1138 if(((ptr>>shift)==(addr>>shift)) ||
1139 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1141 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1142 u_int host_addr=(u_int)kill_pointer(head->addr);
1144 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1151 // This is called when we write to a compiled block (see do_invstub)
1152 void invalidate_page(u_int page)
1154 struct ll_entry *head;
1155 struct ll_entry *next;
1159 inv_debug("INVALIDATE: %x\n",head->vaddr);
1160 remove_hash(head->vaddr);
1165 head=jump_out[page];
1168 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1169 u_int host_addr=(u_int)kill_pointer(head->addr);
1171 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1179 static void invalidate_block_range(u_int block, u_int first, u_int last)
1181 u_int page=get_page(block<<12);
1182 //printf("first=%d last=%d\n",first,last);
1183 invalidate_page(page);
1184 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1185 assert(last<page+5);
1186 // Invalidate the adjacent pages if a block crosses a 4K boundary
1188 invalidate_page(first);
1191 for(first=page+1;first<last;first++) {
1192 invalidate_page(first);
1198 // Don't trap writes
1199 invalid_code[block]=1;
1201 // If there is a valid TLB entry for this page, remove write protect
1202 if(tlb_LUT_w[block]) {
1203 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1204 // CHECK: Is this right?
1205 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1206 u_int real_block=tlb_LUT_w[block]>>12;
1207 invalid_code[real_block]=1;
1208 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1210 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1214 memset(mini_ht,-1,sizeof(mini_ht));
1218 void invalidate_block(u_int block)
1220 u_int page=get_page(block<<12);
1221 u_int vpage=get_vpage(block<<12);
1222 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1223 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1226 struct ll_entry *head;
1227 head=jump_dirty[vpage];
1228 //printf("page=%d vpage=%d\n",page,vpage);
1231 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1232 get_bounds((int)head->addr,&start,&end);
1233 //printf("start: %x end: %x\n",start,end);
1234 if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
1235 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1236 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1237 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1241 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1242 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1243 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1244 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1251 invalidate_block_range(block,first,last);
1254 void invalidate_addr(u_int addr)
1258 // this check is done by the caller
1259 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1260 u_int page=get_vpage(addr);
1261 if(page<2048) { // RAM
1262 struct ll_entry *head;
1263 u_int addr_min=~0, addr_max=0;
1264 u_int mask=RAM_SIZE-1;
1265 u_int addr_main=0x80000000|(addr&mask);
1267 inv_code_start=addr_main&~0xfff;
1268 inv_code_end=addr_main|0xfff;
1271 // must check previous page too because of spans..
1273 inv_code_start-=0x1000;
1275 for(;pg1<=page;pg1++) {
1276 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1278 get_bounds((int)head->addr,&start,&end);
1283 if(start<=addr_main&&addr_main<end) {
1284 if(start<addr_min) addr_min=start;
1285 if(end>addr_max) addr_max=end;
1287 else if(addr_main<start) {
1288 if(start<inv_code_end)
1289 inv_code_end=start-1;
1292 if(end>inv_code_start)
1298 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1299 inv_code_start=inv_code_end=~0;
1300 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1304 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1305 inv_code_end=(addr&~mask)|(inv_code_end&mask);
1306 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1311 invalidate_block(addr>>12);
1314 // This is called when loading a save state.
1315 // Anything could have changed, so invalidate everything.
1316 void invalidate_all_pages()
1319 for(page=0;page<4096;page++)
1320 invalidate_page(page);
1321 for(page=0;page<1048576;page++)
1322 if(!invalid_code[page]) {
1323 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1324 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1327 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1330 memset(mini_ht,-1,sizeof(mini_ht));
1334 for(page=0;page<0x100000;page++) {
1335 if(tlb_LUT_r[page]) {
1336 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1337 if(!tlb_LUT_w[page]||!invalid_code[page])
1338 memory_map[page]|=0x40000000; // Write protect
1340 else memory_map[page]=-1;
1341 if(page==0x80000) page=0xC0000;
1347 // Add an entry to jump_out after making a link
1348 void add_link(u_int vaddr,void *src)
1350 u_int page=get_page(vaddr);
1351 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1352 int *ptr=(int *)(src+4);
1353 assert((*ptr&0x0fff0000)==0x059f0000);
1354 ll_add(jump_out+page,vaddr,src);
1355 //int ptr=get_pointer(src);
1356 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1359 // If a code block was found to be unmodified (bit was set in
1360 // restore_candidate) and it remains unmodified (bit is clear
1361 // in invalid_code) then move the entries for that 4K page from
1362 // the dirty list to the clean list.
1363 void clean_blocks(u_int page)
1365 struct ll_entry *head;
1366 inv_debug("INV: clean_blocks page=%d\n",page);
1367 head=jump_dirty[page];
1369 if(!invalid_code[head->vaddr>>12]) {
1370 // Don't restore blocks which are about to expire from the cache
1371 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1373 if(verify_dirty((int)head->addr)) {
1374 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1377 get_bounds((int)head->addr,&start,&end);
1378 if(start-(u_int)rdram<RAM_SIZE) {
1379 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1380 inv|=invalid_code[i];
1384 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1385 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1386 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1387 if(addr<start||addr>=end) inv=1;
1390 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1394 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1395 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1398 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1400 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1401 //printf("page=%x, addr=%x\n",page,head->vaddr);
1402 //assert(head->vaddr>>12==(page|0x80000));
1403 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1404 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1406 if(ht_bin[0]==head->vaddr) {
1407 ht_bin[1]=(int)clean_addr; // Replace existing entry
1409 if(ht_bin[2]==head->vaddr) {
1410 ht_bin[3]=(int)clean_addr; // Replace existing entry
1423 void mov_alloc(struct regstat *current,int i)
1425 // Note: Don't need to actually alloc the source registers
1426 if((~current->is32>>rs1[i])&1) {
1427 //alloc_reg64(current,i,rs1[i]);
1428 alloc_reg64(current,i,rt1[i]);
1429 current->is32&=~(1LL<<rt1[i]);
1431 //alloc_reg(current,i,rs1[i]);
1432 alloc_reg(current,i,rt1[i]);
1433 current->is32|=(1LL<<rt1[i]);
1435 clear_const(current,rs1[i]);
1436 clear_const(current,rt1[i]);
1437 dirty_reg(current,rt1[i]);
1440 void shiftimm_alloc(struct regstat *current,int i)
1442 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1445 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1447 alloc_reg(current,i,rt1[i]);
1448 current->is32|=1LL<<rt1[i];
1449 dirty_reg(current,rt1[i]);
1450 if(is_const(current,rs1[i])) {
1451 int v=get_const(current,rs1[i]);
1452 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1453 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1454 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1456 else clear_const(current,rt1[i]);
1461 clear_const(current,rs1[i]);
1462 clear_const(current,rt1[i]);
1465 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1468 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1469 alloc_reg64(current,i,rt1[i]);
1470 current->is32&=~(1LL<<rt1[i]);
1471 dirty_reg(current,rt1[i]);
1474 if(opcode2[i]==0x3c) // DSLL32
1477 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1478 alloc_reg64(current,i,rt1[i]);
1479 current->is32&=~(1LL<<rt1[i]);
1480 dirty_reg(current,rt1[i]);
1483 if(opcode2[i]==0x3e) // DSRL32
1486 alloc_reg64(current,i,rs1[i]);
1488 alloc_reg64(current,i,rt1[i]);
1489 current->is32&=~(1LL<<rt1[i]);
1491 alloc_reg(current,i,rt1[i]);
1492 current->is32|=1LL<<rt1[i];
1494 dirty_reg(current,rt1[i]);
1497 if(opcode2[i]==0x3f) // DSRA32
1500 alloc_reg64(current,i,rs1[i]);
1501 alloc_reg(current,i,rt1[i]);
1502 current->is32|=1LL<<rt1[i];
1503 dirty_reg(current,rt1[i]);
1508 void shift_alloc(struct regstat *current,int i)
1511 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1513 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1514 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1515 alloc_reg(current,i,rt1[i]);
1516 if(rt1[i]==rs2[i]) {
1517 alloc_reg_temp(current,i,-1);
1518 minimum_free_regs[i]=1;
1520 current->is32|=1LL<<rt1[i];
1521 } else { // DSLLV/DSRLV/DSRAV
1522 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1523 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1524 alloc_reg64(current,i,rt1[i]);
1525 current->is32&=~(1LL<<rt1[i]);
1526 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1528 alloc_reg_temp(current,i,-1);
1529 minimum_free_regs[i]=1;
1532 clear_const(current,rs1[i]);
1533 clear_const(current,rs2[i]);
1534 clear_const(current,rt1[i]);
1535 dirty_reg(current,rt1[i]);
1539 void alu_alloc(struct regstat *current,int i)
1541 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1543 if(rs1[i]&&rs2[i]) {
1544 alloc_reg(current,i,rs1[i]);
1545 alloc_reg(current,i,rs2[i]);
1548 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1549 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1551 alloc_reg(current,i,rt1[i]);
1553 current->is32|=1LL<<rt1[i];
1555 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1557 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1559 alloc_reg64(current,i,rs1[i]);
1560 alloc_reg64(current,i,rs2[i]);
1561 alloc_reg(current,i,rt1[i]);
1563 alloc_reg(current,i,rs1[i]);
1564 alloc_reg(current,i,rs2[i]);
1565 alloc_reg(current,i,rt1[i]);
1568 current->is32|=1LL<<rt1[i];
1570 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1572 if(rs1[i]&&rs2[i]) {
1573 alloc_reg(current,i,rs1[i]);
1574 alloc_reg(current,i,rs2[i]);
1578 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1579 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1581 alloc_reg(current,i,rt1[i]);
1582 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1584 if(!((current->uu>>rt1[i])&1)) {
1585 alloc_reg64(current,i,rt1[i]);
1587 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1588 if(rs1[i]&&rs2[i]) {
1589 alloc_reg64(current,i,rs1[i]);
1590 alloc_reg64(current,i,rs2[i]);
1594 // Is is really worth it to keep 64-bit values in registers?
1596 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1597 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1601 current->is32&=~(1LL<<rt1[i]);
1603 current->is32|=1LL<<rt1[i];
1607 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1609 if(rs1[i]&&rs2[i]) {
1610 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1611 alloc_reg64(current,i,rs1[i]);
1612 alloc_reg64(current,i,rs2[i]);
1613 alloc_reg64(current,i,rt1[i]);
1615 alloc_reg(current,i,rs1[i]);
1616 alloc_reg(current,i,rs2[i]);
1617 alloc_reg(current,i,rt1[i]);
1621 alloc_reg(current,i,rt1[i]);
1622 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1623 // DADD used as move, or zeroing
1624 // If we have a 64-bit source, then make the target 64 bits too
1625 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1626 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1627 alloc_reg64(current,i,rt1[i]);
1628 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1629 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1630 alloc_reg64(current,i,rt1[i]);
1632 if(opcode2[i]>=0x2e&&rs2[i]) {
1633 // DSUB used as negation - 64-bit result
1634 // If we have a 32-bit register, extend it to 64 bits
1635 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1636 alloc_reg64(current,i,rt1[i]);
1640 if(rs1[i]&&rs2[i]) {
1641 current->is32&=~(1LL<<rt1[i]);
1643 current->is32&=~(1LL<<rt1[i]);
1644 if((current->is32>>rs1[i])&1)
1645 current->is32|=1LL<<rt1[i];
1647 current->is32&=~(1LL<<rt1[i]);
1648 if((current->is32>>rs2[i])&1)
1649 current->is32|=1LL<<rt1[i];
1651 current->is32|=1LL<<rt1[i];
1655 clear_const(current,rs1[i]);
1656 clear_const(current,rs2[i]);
1657 clear_const(current,rt1[i]);
1658 dirty_reg(current,rt1[i]);
1661 void imm16_alloc(struct regstat *current,int i)
1663 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1665 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1666 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1667 current->is32&=~(1LL<<rt1[i]);
1668 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1669 // TODO: Could preserve the 32-bit flag if the immediate is zero
1670 alloc_reg64(current,i,rt1[i]);
1671 alloc_reg64(current,i,rs1[i]);
1673 clear_const(current,rs1[i]);
1674 clear_const(current,rt1[i]);
1676 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1677 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1678 current->is32|=1LL<<rt1[i];
1679 clear_const(current,rs1[i]);
1680 clear_const(current,rt1[i]);
1682 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1683 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1684 if(rs1[i]!=rt1[i]) {
1685 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1686 alloc_reg64(current,i,rt1[i]);
1687 current->is32&=~(1LL<<rt1[i]);
1690 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1691 if(is_const(current,rs1[i])) {
1692 int v=get_const(current,rs1[i]);
1693 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1694 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1695 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1697 else clear_const(current,rt1[i]);
1699 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1700 if(is_const(current,rs1[i])) {
1701 int v=get_const(current,rs1[i]);
1702 set_const(current,rt1[i],v+imm[i]);
1704 else clear_const(current,rt1[i]);
1705 current->is32|=1LL<<rt1[i];
1708 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1709 current->is32|=1LL<<rt1[i];
1711 dirty_reg(current,rt1[i]);
1714 void load_alloc(struct regstat *current,int i)
1716 clear_const(current,rt1[i]);
1717 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1718 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1719 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1720 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1721 alloc_reg(current,i,rt1[i]);
1722 assert(get_reg(current->regmap,rt1[i])>=0);
1723 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1725 current->is32&=~(1LL<<rt1[i]);
1726 alloc_reg64(current,i,rt1[i]);
1728 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1730 current->is32&=~(1LL<<rt1[i]);
1731 alloc_reg64(current,i,rt1[i]);
1732 alloc_all(current,i);
1733 alloc_reg64(current,i,FTEMP);
1734 minimum_free_regs[i]=HOST_REGS;
1736 else current->is32|=1LL<<rt1[i];
1737 dirty_reg(current,rt1[i]);
1738 // If using TLB, need a register for pointer to the mapping table
1739 if(using_tlb) alloc_reg(current,i,TLREG);
1740 // LWL/LWR need a temporary register for the old value
1741 if(opcode[i]==0x22||opcode[i]==0x26)
1743 alloc_reg(current,i,FTEMP);
1744 alloc_reg_temp(current,i,-1);
1745 minimum_free_regs[i]=1;
1750 // Load to r0 or unneeded register (dummy load)
1751 // but we still need a register to calculate the address
1752 if(opcode[i]==0x22||opcode[i]==0x26)
1754 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1756 // If using TLB, need a register for pointer to the mapping table
1757 if(using_tlb) alloc_reg(current,i,TLREG);
1758 alloc_reg_temp(current,i,-1);
1759 minimum_free_regs[i]=1;
1760 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1762 alloc_all(current,i);
1763 alloc_reg64(current,i,FTEMP);
1764 minimum_free_regs[i]=HOST_REGS;
1769 void store_alloc(struct regstat *current,int i)
1771 clear_const(current,rs2[i]);
1772 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1773 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1774 alloc_reg(current,i,rs2[i]);
1775 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1776 alloc_reg64(current,i,rs2[i]);
1777 if(rs2[i]) alloc_reg(current,i,FTEMP);
1779 // If using TLB, need a register for pointer to the mapping table
1780 if(using_tlb) alloc_reg(current,i,TLREG);
1781 #if defined(HOST_IMM8)
1782 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1783 else alloc_reg(current,i,INVCP);
1785 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1786 alloc_reg(current,i,FTEMP);
1788 // We need a temporary register for address generation
1789 alloc_reg_temp(current,i,-1);
1790 minimum_free_regs[i]=1;
1793 void c1ls_alloc(struct regstat *current,int i)
1795 //clear_const(current,rs1[i]); // FIXME
1796 clear_const(current,rt1[i]);
1797 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1798 alloc_reg(current,i,CSREG); // Status
1799 alloc_reg(current,i,FTEMP);
1800 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1801 alloc_reg64(current,i,FTEMP);
1803 // If using TLB, need a register for pointer to the mapping table
1804 if(using_tlb) alloc_reg(current,i,TLREG);
1805 #if defined(HOST_IMM8)
1806 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1807 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1808 alloc_reg(current,i,INVCP);
1810 // We need a temporary register for address generation
1811 alloc_reg_temp(current,i,-1);
1814 void c2ls_alloc(struct regstat *current,int i)
1816 clear_const(current,rt1[i]);
1817 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1818 alloc_reg(current,i,FTEMP);
1819 // If using TLB, need a register for pointer to the mapping table
1820 if(using_tlb) alloc_reg(current,i,TLREG);
1821 #if defined(HOST_IMM8)
1822 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1823 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1824 alloc_reg(current,i,INVCP);
1826 // We need a temporary register for address generation
1827 alloc_reg_temp(current,i,-1);
1828 minimum_free_regs[i]=1;
1831 #ifndef multdiv_alloc
1832 void multdiv_alloc(struct regstat *current,int i)
1839 // case 0x1D: DMULTU
1842 clear_const(current,rs1[i]);
1843 clear_const(current,rs2[i]);
1846 if((opcode2[i]&4)==0) // 32-bit
1848 current->u&=~(1LL<<HIREG);
1849 current->u&=~(1LL<<LOREG);
1850 alloc_reg(current,i,HIREG);
1851 alloc_reg(current,i,LOREG);
1852 alloc_reg(current,i,rs1[i]);
1853 alloc_reg(current,i,rs2[i]);
1854 current->is32|=1LL<<HIREG;
1855 current->is32|=1LL<<LOREG;
1856 dirty_reg(current,HIREG);
1857 dirty_reg(current,LOREG);
1861 current->u&=~(1LL<<HIREG);
1862 current->u&=~(1LL<<LOREG);
1863 current->uu&=~(1LL<<HIREG);
1864 current->uu&=~(1LL<<LOREG);
1865 alloc_reg64(current,i,HIREG);
1866 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1867 alloc_reg64(current,i,rs1[i]);
1868 alloc_reg64(current,i,rs2[i]);
1869 alloc_all(current,i);
1870 current->is32&=~(1LL<<HIREG);
1871 current->is32&=~(1LL<<LOREG);
1872 dirty_reg(current,HIREG);
1873 dirty_reg(current,LOREG);
1874 minimum_free_regs[i]=HOST_REGS;
1879 // Multiply by zero is zero.
1880 // MIPS does not have a divide by zero exception.
1881 // The result is undefined, we return zero.
1882 alloc_reg(current,i,HIREG);
1883 alloc_reg(current,i,LOREG);
1884 current->is32|=1LL<<HIREG;
1885 current->is32|=1LL<<LOREG;
1886 dirty_reg(current,HIREG);
1887 dirty_reg(current,LOREG);
1892 void cop0_alloc(struct regstat *current,int i)
1894 if(opcode2[i]==0) // MFC0
1897 clear_const(current,rt1[i]);
1898 alloc_all(current,i);
1899 alloc_reg(current,i,rt1[i]);
1900 current->is32|=1LL<<rt1[i];
1901 dirty_reg(current,rt1[i]);
1904 else if(opcode2[i]==4) // MTC0
1907 clear_const(current,rs1[i]);
1908 alloc_reg(current,i,rs1[i]);
1909 alloc_all(current,i);
1912 alloc_all(current,i); // FIXME: Keep r0
1914 alloc_reg(current,i,0);
1919 // TLBR/TLBWI/TLBWR/TLBP/ERET
1920 assert(opcode2[i]==0x10);
1921 alloc_all(current,i);
1923 minimum_free_regs[i]=HOST_REGS;
1926 void cop1_alloc(struct regstat *current,int i)
1928 alloc_reg(current,i,CSREG); // Load status
1929 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1932 clear_const(current,rt1[i]);
1934 alloc_reg64(current,i,rt1[i]); // DMFC1
1935 current->is32&=~(1LL<<rt1[i]);
1937 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1938 current->is32|=1LL<<rt1[i];
1940 dirty_reg(current,rt1[i]);
1942 alloc_reg_temp(current,i,-1);
1944 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1947 clear_const(current,rs1[i]);
1949 alloc_reg64(current,i,rs1[i]); // DMTC1
1951 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1952 alloc_reg_temp(current,i,-1);
1956 alloc_reg(current,i,0);
1957 alloc_reg_temp(current,i,-1);
1960 minimum_free_regs[i]=1;
1962 void fconv_alloc(struct regstat *current,int i)
1964 alloc_reg(current,i,CSREG); // Load status
1965 alloc_reg_temp(current,i,-1);
1966 minimum_free_regs[i]=1;
1968 void float_alloc(struct regstat *current,int i)
1970 alloc_reg(current,i,CSREG); // Load status
1971 alloc_reg_temp(current,i,-1);
1972 minimum_free_regs[i]=1;
1974 void c2op_alloc(struct regstat *current,int i)
1976 alloc_reg_temp(current,i,-1);
1978 void fcomp_alloc(struct regstat *current,int i)
1980 alloc_reg(current,i,CSREG); // Load status
1981 alloc_reg(current,i,FSREG); // Load flags
1982 dirty_reg(current,FSREG); // Flag will be modified
1983 alloc_reg_temp(current,i,-1);
1984 minimum_free_regs[i]=1;
1987 void syscall_alloc(struct regstat *current,int i)
1989 alloc_cc(current,i);
1990 dirty_reg(current,CCREG);
1991 alloc_all(current,i);
1992 minimum_free_regs[i]=HOST_REGS;
1996 void delayslot_alloc(struct regstat *current,int i)
2007 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
2008 SysPrintf("Disabled speculative precompilation\n");
2012 imm16_alloc(current,i);
2016 load_alloc(current,i);
2020 store_alloc(current,i);
2023 alu_alloc(current,i);
2026 shift_alloc(current,i);
2029 multdiv_alloc(current,i);
2032 shiftimm_alloc(current,i);
2035 mov_alloc(current,i);
2038 cop0_alloc(current,i);
2042 cop1_alloc(current,i);
2045 c1ls_alloc(current,i);
2048 c2ls_alloc(current,i);
2051 fconv_alloc(current,i);
2054 float_alloc(current,i);
2057 fcomp_alloc(current,i);
2060 c2op_alloc(current,i);
2065 // Special case where a branch and delay slot span two pages in virtual memory
2066 static void pagespan_alloc(struct regstat *current,int i)
2069 current->wasconst=0;
2071 minimum_free_regs[i]=HOST_REGS;
2072 alloc_all(current,i);
2073 alloc_cc(current,i);
2074 dirty_reg(current,CCREG);
2075 if(opcode[i]==3) // JAL
2077 alloc_reg(current,i,31);
2078 dirty_reg(current,31);
2080 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2082 alloc_reg(current,i,rs1[i]);
2084 alloc_reg(current,i,rt1[i]);
2085 dirty_reg(current,rt1[i]);
2088 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2090 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2091 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2092 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2094 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2095 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2099 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2101 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2102 if(!((current->is32>>rs1[i])&1))
2104 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2108 if(opcode[i]==0x11) // BC1
2110 alloc_reg(current,i,FSREG);
2111 alloc_reg(current,i,CSREG);
2116 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2118 stubs[stubcount][0]=type;
2119 stubs[stubcount][1]=addr;
2120 stubs[stubcount][2]=retaddr;
2121 stubs[stubcount][3]=a;
2122 stubs[stubcount][4]=b;
2123 stubs[stubcount][5]=c;
2124 stubs[stubcount][6]=d;
2125 stubs[stubcount][7]=e;
2129 // Write out a single register
2130 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2133 for(hr=0;hr<HOST_REGS;hr++) {
2134 if(hr!=EXCLUDE_REG) {
2135 if((regmap[hr]&63)==r) {
2138 emit_storereg(r,hr);
2140 if((is32>>regmap[hr])&1) {
2141 emit_sarimm(hr,31,hr);
2142 emit_storereg(r|64,hr);
2146 emit_storereg(r|64,hr);
2156 //if(!tracedebug) return 0;
2159 for(i=0;i<2097152;i++) {
2160 unsigned int temp=sum;
2163 sum^=((u_int *)rdram)[i];
2172 sum^=((u_int *)reg)[i];
2180 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2182 #ifndef DISABLE_COP1
2185 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2195 void memdebug(int i)
2197 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2198 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2201 //if(Count>=-2084597794) {
2202 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2204 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2205 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2206 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2209 printf("TRACE: %x\n",(&i)[-1]);
2213 printf("TRACE: %x \n",(&j)[10]);
2214 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2218 //printf("TRACE: %x\n",(&i)[-1]);
2221 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2223 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2226 void alu_assemble(int i,struct regstat *i_regs)
2228 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2230 signed char s1,s2,t;
2231 t=get_reg(i_regs->regmap,rt1[i]);
2233 s1=get_reg(i_regs->regmap,rs1[i]);
2234 s2=get_reg(i_regs->regmap,rs2[i]);
2235 if(rs1[i]&&rs2[i]) {
2238 if(opcode2[i]&2) emit_sub(s1,s2,t);
2239 else emit_add(s1,s2,t);
2242 if(s1>=0) emit_mov(s1,t);
2243 else emit_loadreg(rs1[i],t);
2247 if(opcode2[i]&2) emit_neg(s2,t);
2248 else emit_mov(s2,t);
2251 emit_loadreg(rs2[i],t);
2252 if(opcode2[i]&2) emit_neg(t,t);
2255 else emit_zeroreg(t);
2259 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2261 signed char s1l,s2l,s1h,s2h,tl,th;
2262 tl=get_reg(i_regs->regmap,rt1[i]);
2263 th=get_reg(i_regs->regmap,rt1[i]|64);
2265 s1l=get_reg(i_regs->regmap,rs1[i]);
2266 s2l=get_reg(i_regs->regmap,rs2[i]);
2267 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2268 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2269 if(rs1[i]&&rs2[i]) {
2272 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2273 else emit_adds(s1l,s2l,tl);
2275 #ifdef INVERTED_CARRY
2276 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2278 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2280 else emit_add(s1h,s2h,th);
2284 if(s1l>=0) emit_mov(s1l,tl);
2285 else emit_loadreg(rs1[i],tl);
2287 if(s1h>=0) emit_mov(s1h,th);
2288 else emit_loadreg(rs1[i]|64,th);
2293 if(opcode2[i]&2) emit_negs(s2l,tl);
2294 else emit_mov(s2l,tl);
2297 emit_loadreg(rs2[i],tl);
2298 if(opcode2[i]&2) emit_negs(tl,tl);
2301 #ifdef INVERTED_CARRY
2302 if(s2h>=0) emit_mov(s2h,th);
2303 else emit_loadreg(rs2[i]|64,th);
2305 emit_adcimm(-1,th); // x86 has inverted carry flag
2310 if(s2h>=0) emit_rscimm(s2h,0,th);
2312 emit_loadreg(rs2[i]|64,th);
2313 emit_rscimm(th,0,th);
2316 if(s2h>=0) emit_mov(s2h,th);
2317 else emit_loadreg(rs2[i]|64,th);
2324 if(th>=0) emit_zeroreg(th);
2329 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2331 signed char s1l,s1h,s2l,s2h,t;
2332 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2334 t=get_reg(i_regs->regmap,rt1[i]);
2337 s1l=get_reg(i_regs->regmap,rs1[i]);
2338 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2339 s2l=get_reg(i_regs->regmap,rs2[i]);
2340 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2341 if(rs2[i]==0) // rx<r0
2344 if(opcode2[i]==0x2a) // SLT
2345 emit_shrimm(s1h,31,t);
2346 else // SLTU (unsigned can not be less than zero)
2349 else if(rs1[i]==0) // r0<rx
2352 if(opcode2[i]==0x2a) // SLT
2353 emit_set_gz64_32(s2h,s2l,t);
2354 else // SLTU (set if not zero)
2355 emit_set_nz64_32(s2h,s2l,t);
2358 assert(s1l>=0);assert(s1h>=0);
2359 assert(s2l>=0);assert(s2h>=0);
2360 if(opcode2[i]==0x2a) // SLT
2361 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2363 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2367 t=get_reg(i_regs->regmap,rt1[i]);
2370 s1l=get_reg(i_regs->regmap,rs1[i]);
2371 s2l=get_reg(i_regs->regmap,rs2[i]);
2372 if(rs2[i]==0) // rx<r0
2375 if(opcode2[i]==0x2a) // SLT
2376 emit_shrimm(s1l,31,t);
2377 else // SLTU (unsigned can not be less than zero)
2380 else if(rs1[i]==0) // r0<rx
2383 if(opcode2[i]==0x2a) // SLT
2384 emit_set_gz32(s2l,t);
2385 else // SLTU (set if not zero)
2386 emit_set_nz32(s2l,t);
2389 assert(s1l>=0);assert(s2l>=0);
2390 if(opcode2[i]==0x2a) // SLT
2391 emit_set_if_less32(s1l,s2l,t);
2393 emit_set_if_carry32(s1l,s2l,t);
2399 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2401 signed char s1l,s1h,s2l,s2h,th,tl;
2402 tl=get_reg(i_regs->regmap,rt1[i]);
2403 th=get_reg(i_regs->regmap,rt1[i]|64);
2404 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2408 s1l=get_reg(i_regs->regmap,rs1[i]);
2409 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2410 s2l=get_reg(i_regs->regmap,rs2[i]);
2411 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2412 if(rs1[i]&&rs2[i]) {
2413 assert(s1l>=0);assert(s1h>=0);
2414 assert(s2l>=0);assert(s2h>=0);
2415 if(opcode2[i]==0x24) { // AND
2416 emit_and(s1l,s2l,tl);
2417 emit_and(s1h,s2h,th);
2419 if(opcode2[i]==0x25) { // OR
2420 emit_or(s1l,s2l,tl);
2421 emit_or(s1h,s2h,th);
2423 if(opcode2[i]==0x26) { // XOR
2424 emit_xor(s1l,s2l,tl);
2425 emit_xor(s1h,s2h,th);
2427 if(opcode2[i]==0x27) { // NOR
2428 emit_or(s1l,s2l,tl);
2429 emit_or(s1h,s2h,th);
2436 if(opcode2[i]==0x24) { // AND
2440 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2442 if(s1l>=0) emit_mov(s1l,tl);
2443 else emit_loadreg(rs1[i],tl);
2444 if(s1h>=0) emit_mov(s1h,th);
2445 else emit_loadreg(rs1[i]|64,th);
2449 if(s2l>=0) emit_mov(s2l,tl);
2450 else emit_loadreg(rs2[i],tl);
2451 if(s2h>=0) emit_mov(s2h,th);
2452 else emit_loadreg(rs2[i]|64,th);
2459 if(opcode2[i]==0x27) { // NOR
2461 if(s1l>=0) emit_not(s1l,tl);
2463 emit_loadreg(rs1[i],tl);
2466 if(s1h>=0) emit_not(s1h,th);
2468 emit_loadreg(rs1[i]|64,th);
2474 if(s2l>=0) emit_not(s2l,tl);
2476 emit_loadreg(rs2[i],tl);
2479 if(s2h>=0) emit_not(s2h,th);
2481 emit_loadreg(rs2[i]|64,th);
2497 s1l=get_reg(i_regs->regmap,rs1[i]);
2498 s2l=get_reg(i_regs->regmap,rs2[i]);
2499 if(rs1[i]&&rs2[i]) {
2502 if(opcode2[i]==0x24) { // AND
2503 emit_and(s1l,s2l,tl);
2505 if(opcode2[i]==0x25) { // OR
2506 emit_or(s1l,s2l,tl);
2508 if(opcode2[i]==0x26) { // XOR
2509 emit_xor(s1l,s2l,tl);
2511 if(opcode2[i]==0x27) { // NOR
2512 emit_or(s1l,s2l,tl);
2518 if(opcode2[i]==0x24) { // AND
2521 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2523 if(s1l>=0) emit_mov(s1l,tl);
2524 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2528 if(s2l>=0) emit_mov(s2l,tl);
2529 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2531 else emit_zeroreg(tl);
2533 if(opcode2[i]==0x27) { // NOR
2535 if(s1l>=0) emit_not(s1l,tl);
2537 emit_loadreg(rs1[i],tl);
2543 if(s2l>=0) emit_not(s2l,tl);
2545 emit_loadreg(rs2[i],tl);
2549 else emit_movimm(-1,tl);
2558 void imm16_assemble(int i,struct regstat *i_regs)
2560 if (opcode[i]==0x0f) { // LUI
2563 t=get_reg(i_regs->regmap,rt1[i]);
2566 if(!((i_regs->isconst>>t)&1))
2567 emit_movimm(imm[i]<<16,t);
2571 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2574 t=get_reg(i_regs->regmap,rt1[i]);
2575 s=get_reg(i_regs->regmap,rs1[i]);
2580 if(!((i_regs->isconst>>t)&1)) {
2582 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2583 emit_addimm(t,imm[i],t);
2585 if(!((i_regs->wasconst>>s)&1))
2586 emit_addimm(s,imm[i],t);
2588 emit_movimm(constmap[i][s]+imm[i],t);
2594 if(!((i_regs->isconst>>t)&1))
2595 emit_movimm(imm[i],t);
2600 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2602 signed char sh,sl,th,tl;
2603 th=get_reg(i_regs->regmap,rt1[i]|64);
2604 tl=get_reg(i_regs->regmap,rt1[i]);
2605 sh=get_reg(i_regs->regmap,rs1[i]|64);
2606 sl=get_reg(i_regs->regmap,rs1[i]);
2612 emit_addimm64_32(sh,sl,imm[i],th,tl);
2615 emit_addimm(sl,imm[i],tl);
2618 emit_movimm(imm[i],tl);
2619 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2624 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2626 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2627 signed char sh,sl,t;
2628 t=get_reg(i_regs->regmap,rt1[i]);
2629 sh=get_reg(i_regs->regmap,rs1[i]|64);
2630 sl=get_reg(i_regs->regmap,rs1[i]);
2634 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2635 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2636 if(opcode[i]==0x0a) { // SLTI
2638 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2639 emit_slti32(t,imm[i],t);
2641 emit_slti32(sl,imm[i],t);
2646 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2647 emit_sltiu32(t,imm[i],t);
2649 emit_sltiu32(sl,imm[i],t);
2654 if(opcode[i]==0x0a) // SLTI
2655 emit_slti64_32(sh,sl,imm[i],t);
2657 emit_sltiu64_32(sh,sl,imm[i],t);
2660 // SLTI(U) with r0 is just stupid,
2661 // nonetheless examples can be found
2662 if(opcode[i]==0x0a) // SLTI
2663 if(0<imm[i]) emit_movimm(1,t);
2664 else emit_zeroreg(t);
2667 if(imm[i]) emit_movimm(1,t);
2668 else emit_zeroreg(t);
2674 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2676 signed char sh,sl,th,tl;
2677 th=get_reg(i_regs->regmap,rt1[i]|64);
2678 tl=get_reg(i_regs->regmap,rt1[i]);
2679 sh=get_reg(i_regs->regmap,rs1[i]|64);
2680 sl=get_reg(i_regs->regmap,rs1[i]);
2681 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2682 if(opcode[i]==0x0c) //ANDI
2686 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2687 emit_andimm(tl,imm[i],tl);
2689 if(!((i_regs->wasconst>>sl)&1))
2690 emit_andimm(sl,imm[i],tl);
2692 emit_movimm(constmap[i][sl]&imm[i],tl);
2697 if(th>=0) emit_zeroreg(th);
2703 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2707 emit_loadreg(rs1[i]|64,th);
2712 if(opcode[i]==0x0d) //ORI
2714 emit_orimm(tl,imm[i],tl);
2716 if(!((i_regs->wasconst>>sl)&1))
2717 emit_orimm(sl,imm[i],tl);
2719 emit_movimm(constmap[i][sl]|imm[i],tl);
2721 if(opcode[i]==0x0e) //XORI
2723 emit_xorimm(tl,imm[i],tl);
2725 if(!((i_regs->wasconst>>sl)&1))
2726 emit_xorimm(sl,imm[i],tl);
2728 emit_movimm(constmap[i][sl]^imm[i],tl);
2732 emit_movimm(imm[i],tl);
2733 if(th>=0) emit_zeroreg(th);
2741 void shiftimm_assemble(int i,struct regstat *i_regs)
2743 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2747 t=get_reg(i_regs->regmap,rt1[i]);
2748 s=get_reg(i_regs->regmap,rs1[i]);
2750 if(t>=0&&!((i_regs->isconst>>t)&1)){
2757 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2759 if(opcode2[i]==0) // SLL
2761 emit_shlimm(s<0?t:s,imm[i],t);
2763 if(opcode2[i]==2) // SRL
2765 emit_shrimm(s<0?t:s,imm[i],t);
2767 if(opcode2[i]==3) // SRA
2769 emit_sarimm(s<0?t:s,imm[i],t);
2773 if(s>=0 && s!=t) emit_mov(s,t);
2777 //emit_storereg(rt1[i],t); //DEBUG
2780 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2783 signed char sh,sl,th,tl;
2784 th=get_reg(i_regs->regmap,rt1[i]|64);
2785 tl=get_reg(i_regs->regmap,rt1[i]);
2786 sh=get_reg(i_regs->regmap,rs1[i]|64);
2787 sl=get_reg(i_regs->regmap,rs1[i]);
2792 if(th>=0) emit_zeroreg(th);
2799 if(opcode2[i]==0x38) // DSLL
2801 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2802 emit_shlimm(sl,imm[i],tl);
2804 if(opcode2[i]==0x3a) // DSRL
2806 emit_shrdimm(sl,sh,imm[i],tl);
2807 if(th>=0) emit_shrimm(sh,imm[i],th);
2809 if(opcode2[i]==0x3b) // DSRA
2811 emit_shrdimm(sl,sh,imm[i],tl);
2812 if(th>=0) emit_sarimm(sh,imm[i],th);
2816 if(sl!=tl) emit_mov(sl,tl);
2817 if(th>=0&&sh!=th) emit_mov(sh,th);
2823 if(opcode2[i]==0x3c) // DSLL32
2826 signed char sl,tl,th;
2827 tl=get_reg(i_regs->regmap,rt1[i]);
2828 th=get_reg(i_regs->regmap,rt1[i]|64);
2829 sl=get_reg(i_regs->regmap,rs1[i]);
2838 emit_shlimm(th,imm[i]&31,th);
2843 if(opcode2[i]==0x3e) // DSRL32
2846 signed char sh,tl,th;
2847 tl=get_reg(i_regs->regmap,rt1[i]);
2848 th=get_reg(i_regs->regmap,rt1[i]|64);
2849 sh=get_reg(i_regs->regmap,rs1[i]|64);
2853 if(th>=0) emit_zeroreg(th);
2856 emit_shrimm(tl,imm[i]&31,tl);
2861 if(opcode2[i]==0x3f) // DSRA32
2865 tl=get_reg(i_regs->regmap,rt1[i]);
2866 sh=get_reg(i_regs->regmap,rs1[i]|64);
2872 emit_sarimm(tl,imm[i]&31,tl);
2879 #ifndef shift_assemble
2880 void shift_assemble(int i,struct regstat *i_regs)
2882 printf("Need shift_assemble for this architecture.\n");
2887 void load_assemble(int i,struct regstat *i_regs)
2889 int s,th,tl,addr,map=-1;
2892 int memtarget=0,c=0;
2893 int fastload_reg_override=0;
2895 th=get_reg(i_regs->regmap,rt1[i]|64);
2896 tl=get_reg(i_regs->regmap,rt1[i]);
2897 s=get_reg(i_regs->regmap,rs1[i]);
2899 for(hr=0;hr<HOST_REGS;hr++) {
2900 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2902 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2904 c=(i_regs->wasconst>>s)&1;
2906 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2907 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2910 //printf("load_assemble: c=%d\n",c);
2911 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2912 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2914 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2916 // could be FIFO, must perform the read
2918 assem_debug("(forced read)\n");
2919 tl=get_reg(i_regs->regmap,-1);
2923 if(offset||s<0||c) addr=tl;
2925 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2927 //printf("load_assemble: c=%d\n",c);
2928 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2929 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2931 if(th>=0) reglist&=~(1<<th);
2935 map=get_reg(i_regs->regmap,ROREG);
2936 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2938 //#define R29_HACK 1
2940 // Strmnnrmn's speed hack
2941 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2944 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2947 else if(ram_offset&&memtarget) {
2948 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2949 fastload_reg_override=HOST_TEMPREG;
2953 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2954 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2955 map=get_reg(i_regs->regmap,TLREG);
2958 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2959 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2961 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2962 if (opcode[i]==0x20) { // LB
2965 #ifdef HOST_IMM_ADDR32
2967 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2971 //emit_xorimm(addr,3,tl);
2972 //gen_tlb_addr_r(tl,map);
2973 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2975 #ifdef BIG_ENDIAN_MIPS
2976 if(!c) emit_xorimm(addr,3,tl);
2977 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2981 if(fastload_reg_override) a=fastload_reg_override;
2983 emit_movsbl_indexed_tlb(x,a,map,tl);
2987 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2990 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2992 if (opcode[i]==0x21) { // LH
2995 #ifdef HOST_IMM_ADDR32
2997 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
3002 #ifdef BIG_ENDIAN_MIPS
3003 if(!c) emit_xorimm(addr,2,tl);
3004 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3008 if(fastload_reg_override) a=fastload_reg_override;
3010 //emit_movswl_indexed_tlb(x,tl,map,tl);
3013 gen_tlb_addr_r(a,map);
3014 emit_movswl_indexed(x,a,tl);
3016 #if 1 //def RAM_OFFSET
3017 emit_movswl_indexed(x,a,tl);
3019 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
3025 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3028 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3030 if (opcode[i]==0x23) { // LW
3034 if(fastload_reg_override) a=fastload_reg_override;
3035 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3036 #ifdef HOST_IMM_ADDR32
3038 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3041 emit_readword_indexed_tlb(0,a,map,tl);
3044 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3047 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3049 if (opcode[i]==0x24) { // LBU
3052 #ifdef HOST_IMM_ADDR32
3054 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3058 //emit_xorimm(addr,3,tl);
3059 //gen_tlb_addr_r(tl,map);
3060 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3062 #ifdef BIG_ENDIAN_MIPS
3063 if(!c) emit_xorimm(addr,3,tl);
3064 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3068 if(fastload_reg_override) a=fastload_reg_override;
3070 emit_movzbl_indexed_tlb(x,a,map,tl);
3074 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3077 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3079 if (opcode[i]==0x25) { // LHU
3082 #ifdef HOST_IMM_ADDR32
3084 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3089 #ifdef BIG_ENDIAN_MIPS
3090 if(!c) emit_xorimm(addr,2,tl);
3091 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3095 if(fastload_reg_override) a=fastload_reg_override;
3097 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3100 gen_tlb_addr_r(a,map);
3101 emit_movzwl_indexed(x,a,tl);
3103 #if 1 //def RAM_OFFSET
3104 emit_movzwl_indexed(x,a,tl);
3106 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3112 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3115 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3117 if (opcode[i]==0x27) { // LWU
3122 if(fastload_reg_override) a=fastload_reg_override;
3123 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3124 #ifdef HOST_IMM_ADDR32
3126 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3129 emit_readword_indexed_tlb(0,a,map,tl);
3132 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3135 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3139 if (opcode[i]==0x37) { // LD
3143 if(fastload_reg_override) a=fastload_reg_override;
3144 //gen_tlb_addr_r(tl,map);
3145 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3146 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3147 #ifdef HOST_IMM_ADDR32
3149 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3152 emit_readdword_indexed_tlb(0,a,map,th,tl);
3155 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3158 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3161 //emit_storereg(rt1[i],tl); // DEBUG
3162 //if(opcode[i]==0x23)
3163 //if(opcode[i]==0x24)
3164 //if(opcode[i]==0x23||opcode[i]==0x24)
3165 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3169 emit_readword((int)&last_count,ECX);
3171 if(get_reg(i_regs->regmap,CCREG)<0)
3172 emit_loadreg(CCREG,HOST_CCREG);
3173 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3174 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3175 emit_writeword(HOST_CCREG,(int)&Count);
3178 if(get_reg(i_regs->regmap,CCREG)<0)
3179 emit_loadreg(CCREG,0);
3181 emit_mov(HOST_CCREG,0);
3183 emit_addimm(0,2*ccadj[i],0);
3184 emit_writeword(0,(int)&Count);
3186 emit_call((int)memdebug);
3188 restore_regs(0x100f);
3192 #ifndef loadlr_assemble
3193 void loadlr_assemble(int i,struct regstat *i_regs)
3195 printf("Need loadlr_assemble for this architecture.\n");
3200 void store_assemble(int i,struct regstat *i_regs)
3205 int jaddr=0,jaddr2,type;
3206 int memtarget=0,c=0;
3207 int agr=AGEN1+(i&1);
3208 int faststore_reg_override=0;
3210 th=get_reg(i_regs->regmap,rs2[i]|64);
3211 tl=get_reg(i_regs->regmap,rs2[i]);
3212 s=get_reg(i_regs->regmap,rs1[i]);
3213 temp=get_reg(i_regs->regmap,agr);
3214 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3217 c=(i_regs->wasconst>>s)&1;
3219 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3220 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3225 for(hr=0;hr<HOST_REGS;hr++) {
3226 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3228 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3229 if(offset||s<0||c) addr=temp;
3235 // Strmnnrmn's speed hack
3236 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3238 emit_cmpimm(addr,RAM_SIZE);
3239 #ifdef DESTRUCTIVE_SHIFT
3240 if(s==addr) emit_mov(s,temp);
3244 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3248 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3249 // Hint to branch predictor that the branch is unlikely to be taken
3251 emit_jno_unlikely(0);
3257 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3260 else if(ram_offset&&memtarget) {
3261 emit_addimm(addr,ram_offset,HOST_TEMPREG);
3262 faststore_reg_override=HOST_TEMPREG;
3266 if (opcode[i]==0x28) x=3; // SB
3267 if (opcode[i]==0x29) x=2; // SH
3268 map=get_reg(i_regs->regmap,TLREG);
3271 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3272 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3275 if (opcode[i]==0x28) { // SB
3278 #ifdef BIG_ENDIAN_MIPS
3279 if(!c) emit_xorimm(addr,3,temp);
3280 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3284 if(faststore_reg_override) a=faststore_reg_override;
3285 //gen_tlb_addr_w(temp,map);
3286 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3287 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3291 if (opcode[i]==0x29) { // SH
3294 #ifdef BIG_ENDIAN_MIPS
3295 if(!c) emit_xorimm(addr,2,temp);
3296 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3300 if(faststore_reg_override) a=faststore_reg_override;
3302 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3305 gen_tlb_addr_w(a,map);
3306 emit_writehword_indexed(tl,x,a);
3308 //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3309 emit_writehword_indexed(tl,x,a);
3313 if (opcode[i]==0x2B) { // SW
3316 if(faststore_reg_override) a=faststore_reg_override;
3317 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3318 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3322 if (opcode[i]==0x3F) { // SD
3325 if(faststore_reg_override) a=faststore_reg_override;
3328 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3329 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3330 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3333 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3334 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3335 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3342 // PCSX store handlers don't check invcode again
3344 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3348 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3350 #ifdef DESTRUCTIVE_SHIFT
3351 // The x86 shift operation is 'destructive'; it overwrites the
3352 // source register, so we need to make a copy first and use that.
3355 #if defined(HOST_IMM8)
3356 int ir=get_reg(i_regs->regmap,INVCP);
3358 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3360 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3362 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3363 emit_callne(invalidate_addr_reg[addr]);
3367 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3371 u_int addr_val=constmap[i][s]+offset;
3373 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3374 } else if(c&&!memtarget) {
3375 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3377 // basic current block modification detection..
3378 // not looking back as that should be in mips cache already
3379 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3380 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3381 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3382 if(i_regs->regmap==regs[i].regmap) {
3383 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3384 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3385 emit_movimm(start+i*4+4,0);
3386 emit_writeword(0,(int)&pcaddr);
3387 emit_jmp((int)do_interrupt);
3390 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3391 //if(opcode[i]==0x2B || opcode[i]==0x28)
3392 //if(opcode[i]==0x2B || opcode[i]==0x29)
3393 //if(opcode[i]==0x2B)
3394 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3402 emit_readword((int)&last_count,ECX);
3404 if(get_reg(i_regs->regmap,CCREG)<0)
3405 emit_loadreg(CCREG,HOST_CCREG);
3406 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3407 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3408 emit_writeword(HOST_CCREG,(int)&Count);
3411 if(get_reg(i_regs->regmap,CCREG)<0)
3412 emit_loadreg(CCREG,0);
3414 emit_mov(HOST_CCREG,0);
3416 emit_addimm(0,2*ccadj[i],0);
3417 emit_writeword(0,(int)&Count);
3419 emit_call((int)memdebug);
3424 restore_regs(0x100f);
3429 void storelr_assemble(int i,struct regstat *i_regs)
3436 int case1,case2,case3;
3437 int done0,done1,done2;
3438 int memtarget=0,c=0;
3439 int agr=AGEN1+(i&1);
3441 th=get_reg(i_regs->regmap,rs2[i]|64);
3442 tl=get_reg(i_regs->regmap,rs2[i]);
3443 s=get_reg(i_regs->regmap,rs1[i]);
3444 temp=get_reg(i_regs->regmap,agr);
3445 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3448 c=(i_regs->isconst>>s)&1;
3450 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3451 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3455 for(hr=0;hr<HOST_REGS;hr++) {
3456 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3461 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3462 if(!offset&&s!=temp) emit_mov(s,temp);
3468 if(!memtarget||!rs1[i]) {
3474 int map=get_reg(i_regs->regmap,ROREG);
3475 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3476 gen_tlb_addr_w(temp,map);
3478 if((u_int)rdram!=0x80000000)
3479 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3482 int map=get_reg(i_regs->regmap,TLREG);
3485 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3486 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3487 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3488 if(!jaddr&&!memtarget) {
3492 gen_tlb_addr_w(temp,map);
3495 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3496 temp2=get_reg(i_regs->regmap,FTEMP);
3497 if(!rs2[i]) temp2=th=tl;
3500 #ifndef BIG_ENDIAN_MIPS
3501 emit_xorimm(temp,3,temp);
3503 emit_testimm(temp,2);
3506 emit_testimm(temp,1);
3510 if (opcode[i]==0x2A) { // SWL
3511 emit_writeword_indexed(tl,0,temp);
3513 if (opcode[i]==0x2E) { // SWR
3514 emit_writebyte_indexed(tl,3,temp);
3516 if (opcode[i]==0x2C) { // SDL
3517 emit_writeword_indexed(th,0,temp);
3518 if(rs2[i]) emit_mov(tl,temp2);
3520 if (opcode[i]==0x2D) { // SDR
3521 emit_writebyte_indexed(tl,3,temp);
3522 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3527 set_jump_target(case1,(int)out);
3528 if (opcode[i]==0x2A) { // SWL
3529 // Write 3 msb into three least significant bytes
3530 if(rs2[i]) emit_rorimm(tl,8,tl);
3531 emit_writehword_indexed(tl,-1,temp);
3532 if(rs2[i]) emit_rorimm(tl,16,tl);
3533 emit_writebyte_indexed(tl,1,temp);
3534 if(rs2[i]) emit_rorimm(tl,8,tl);
3536 if (opcode[i]==0x2E) { // SWR
3537 // Write two lsb into two most significant bytes
3538 emit_writehword_indexed(tl,1,temp);
3540 if (opcode[i]==0x2C) { // SDL
3541 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3542 // Write 3 msb into three least significant bytes
3543 if(rs2[i]) emit_rorimm(th,8,th);
3544 emit_writehword_indexed(th,-1,temp);
3545 if(rs2[i]) emit_rorimm(th,16,th);
3546 emit_writebyte_indexed(th,1,temp);
3547 if(rs2[i]) emit_rorimm(th,8,th);
3549 if (opcode[i]==0x2D) { // SDR
3550 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3551 // Write two lsb into two most significant bytes
3552 emit_writehword_indexed(tl,1,temp);
3557 set_jump_target(case2,(int)out);
3558 emit_testimm(temp,1);
3561 if (opcode[i]==0x2A) { // SWL
3562 // Write two msb into two least significant bytes
3563 if(rs2[i]) emit_rorimm(tl,16,tl);
3564 emit_writehword_indexed(tl,-2,temp);
3565 if(rs2[i]) emit_rorimm(tl,16,tl);
3567 if (opcode[i]==0x2E) { // SWR
3568 // Write 3 lsb into three most significant bytes
3569 emit_writebyte_indexed(tl,-1,temp);
3570 if(rs2[i]) emit_rorimm(tl,8,tl);
3571 emit_writehword_indexed(tl,0,temp);
3572 if(rs2[i]) emit_rorimm(tl,24,tl);
3574 if (opcode[i]==0x2C) { // SDL
3575 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3576 // Write two msb into two least significant bytes
3577 if(rs2[i]) emit_rorimm(th,16,th);
3578 emit_writehword_indexed(th,-2,temp);
3579 if(rs2[i]) emit_rorimm(th,16,th);
3581 if (opcode[i]==0x2D) { // SDR
3582 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3583 // Write 3 lsb into three most significant bytes
3584 emit_writebyte_indexed(tl,-1,temp);
3585 if(rs2[i]) emit_rorimm(tl,8,tl);
3586 emit_writehword_indexed(tl,0,temp);
3587 if(rs2[i]) emit_rorimm(tl,24,tl);
3592 set_jump_target(case3,(int)out);
3593 if (opcode[i]==0x2A) { // SWL
3594 // Write msb into least significant byte
3595 if(rs2[i]) emit_rorimm(tl,24,tl);
3596 emit_writebyte_indexed(tl,-3,temp);
3597 if(rs2[i]) emit_rorimm(tl,8,tl);
3599 if (opcode[i]==0x2E) { // SWR
3600 // Write entire word
3601 emit_writeword_indexed(tl,-3,temp);
3603 if (opcode[i]==0x2C) { // SDL
3604 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3605 // Write msb into least significant byte
3606 if(rs2[i]) emit_rorimm(th,24,th);
3607 emit_writebyte_indexed(th,-3,temp);
3608 if(rs2[i]) emit_rorimm(th,8,th);
3610 if (opcode[i]==0x2D) { // SDR
3611 if(rs2[i]) emit_mov(th,temp2);
3612 // Write entire word
3613 emit_writeword_indexed(tl,-3,temp);
3615 set_jump_target(done0,(int)out);
3616 set_jump_target(done1,(int)out);
3617 set_jump_target(done2,(int)out);
3618 if (opcode[i]==0x2C) { // SDL
3619 emit_testimm(temp,4);
3622 emit_andimm(temp,~3,temp);
3623 emit_writeword_indexed(temp2,4,temp);
3624 set_jump_target(done0,(int)out);
3626 if (opcode[i]==0x2D) { // SDR
3627 emit_testimm(temp,4);
3630 emit_andimm(temp,~3,temp);
3631 emit_writeword_indexed(temp2,-4,temp);
3632 set_jump_target(done0,(int)out);
3635 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3636 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3638 int map=get_reg(i_regs->regmap,ROREG);
3639 if(map<0) map=HOST_TEMPREG;
3640 gen_orig_addr_w(temp,map);
3642 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3644 #if defined(HOST_IMM8)
3645 int ir=get_reg(i_regs->regmap,INVCP);
3647 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3649 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3651 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3652 emit_callne(invalidate_addr_reg[temp]);
3656 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3661 //save_regs(0x100f);
3662 emit_readword((int)&last_count,ECX);
3663 if(get_reg(i_regs->regmap,CCREG)<0)
3664 emit_loadreg(CCREG,HOST_CCREG);
3665 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3666 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3667 emit_writeword(HOST_CCREG,(int)&Count);
3668 emit_call((int)memdebug);
3670 //restore_regs(0x100f);
3674 void c1ls_assemble(int i,struct regstat *i_regs)
3676 #ifndef DISABLE_COP1
3682 int jaddr,jaddr2=0,jaddr3,type;
3683 int agr=AGEN1+(i&1);
3685 th=get_reg(i_regs->regmap,FTEMP|64);
3686 tl=get_reg(i_regs->regmap,FTEMP);
3687 s=get_reg(i_regs->regmap,rs1[i]);
3688 temp=get_reg(i_regs->regmap,agr);
3689 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3694 for(hr=0;hr<HOST_REGS;hr++) {
3695 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3697 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3698 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3700 // Loads use a temporary register which we need to save
3703 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3707 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3708 //else c=(i_regs->wasconst>>s)&1;
3709 if(s>=0) c=(i_regs->wasconst>>s)&1;
3710 // Check cop1 unusable
3712 signed char rs=get_reg(i_regs->regmap,CSREG);
3714 emit_testimm(rs,0x20000000);
3717 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3720 if (opcode[i]==0x39) { // SWC1 (get float address)
3721 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3723 if (opcode[i]==0x3D) { // SDC1 (get double address)
3724 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3726 // Generate address + offset
3729 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3733 map=get_reg(i_regs->regmap,TLREG);
3736 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3737 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3739 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3740 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3743 if (opcode[i]==0x39) { // SWC1 (read float)
3744 emit_readword_indexed(0,tl,tl);
3746 if (opcode[i]==0x3D) { // SDC1 (read double)
3747 emit_readword_indexed(4,tl,th);
3748 emit_readword_indexed(0,tl,tl);
3750 if (opcode[i]==0x31) { // LWC1 (get target address)
3751 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3753 if (opcode[i]==0x35) { // LDC1 (get target address)
3754 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3761 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3763 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3765 #ifdef DESTRUCTIVE_SHIFT
3766 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3767 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3771 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3772 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3774 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3775 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3778 if (opcode[i]==0x31) { // LWC1
3779 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3780 //gen_tlb_addr_r(ar,map);
3781 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3782 #ifdef HOST_IMM_ADDR32
3783 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3786 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3789 if (opcode[i]==0x35) { // LDC1
3791 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3792 //gen_tlb_addr_r(ar,map);
3793 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3794 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3795 #ifdef HOST_IMM_ADDR32
3796 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3799 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3802 if (opcode[i]==0x39) { // SWC1
3803 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3804 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3807 if (opcode[i]==0x3D) { // SDC1
3809 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3810 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3811 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3814 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3815 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3816 #ifndef DESTRUCTIVE_SHIFT
3817 temp=offset||c||s<0?ar:s;
3819 #if defined(HOST_IMM8)
3820 int ir=get_reg(i_regs->regmap,INVCP);
3822 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3824 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3826 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3827 emit_callne(invalidate_addr_reg[temp]);
3831 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3835 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3836 if (opcode[i]==0x31) { // LWC1 (write float)
3837 emit_writeword_indexed(tl,0,temp);
3839 if (opcode[i]==0x35) { // LDC1 (write double)
3840 emit_writeword_indexed(th,4,temp);
3841 emit_writeword_indexed(tl,0,temp);
3843 //if(opcode[i]==0x39)
3844 /*if(opcode[i]==0x39||opcode[i]==0x31)
3847 emit_readword((int)&last_count,ECX);
3848 if(get_reg(i_regs->regmap,CCREG)<0)
3849 emit_loadreg(CCREG,HOST_CCREG);
3850 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3851 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3852 emit_writeword(HOST_CCREG,(int)&Count);
3853 emit_call((int)memdebug);
3857 cop1_unusable(i, i_regs);
3861 void c2ls_assemble(int i,struct regstat *i_regs)
3866 int memtarget=0,c=0;
3867 int jaddr2=0,jaddr3,type;
3868 int agr=AGEN1+(i&1);
3869 int fastio_reg_override=0;
3871 u_int copr=(source[i]>>16)&0x1f;
3872 s=get_reg(i_regs->regmap,rs1[i]);
3873 tl=get_reg(i_regs->regmap,FTEMP);
3879 for(hr=0;hr<HOST_REGS;hr++) {
3880 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3882 if(i_regs->regmap[HOST_CCREG]==CCREG)
3883 reglist&=~(1<<HOST_CCREG);
3886 if (opcode[i]==0x3a) { // SWC2
3887 ar=get_reg(i_regs->regmap,agr);
3888 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3893 if(s>=0) c=(i_regs->wasconst>>s)&1;
3894 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3895 if (!offset&&!c&&s>=0) ar=s;
3898 if (opcode[i]==0x3a) { // SWC2
3899 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3907 emit_jmp(0); // inline_readstub/inline_writestub?
3911 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3913 else if(ram_offset&&memtarget) {
3914 emit_addimm(ar,ram_offset,HOST_TEMPREG);
3915 fastio_reg_override=HOST_TEMPREG;
3917 if (opcode[i]==0x32) { // LWC2
3918 #ifdef HOST_IMM_ADDR32
3919 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3923 if(fastio_reg_override) a=fastio_reg_override;
3924 emit_readword_indexed(0,a,tl);
3926 if (opcode[i]==0x3a) { // SWC2
3927 #ifdef DESTRUCTIVE_SHIFT
3928 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3931 if(fastio_reg_override) a=fastio_reg_override;
3932 emit_writeword_indexed(tl,0,a);
3936 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3937 if(opcode[i]==0x3a) // SWC2
3938 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3939 #if defined(HOST_IMM8)
3940 int ir=get_reg(i_regs->regmap,INVCP);
3942 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3944 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3946 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3947 emit_callne(invalidate_addr_reg[ar]);
3951 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3954 if (opcode[i]==0x32) { // LWC2
3955 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3959 #ifndef multdiv_assemble
3960 void multdiv_assemble(int i,struct regstat *i_regs)
3962 printf("Need multdiv_assemble for this architecture.\n");
3967 void mov_assemble(int i,struct regstat *i_regs)
3969 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3970 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3972 signed char sh,sl,th,tl;
3973 th=get_reg(i_regs->regmap,rt1[i]|64);
3974 tl=get_reg(i_regs->regmap,rt1[i]);
3977 sh=get_reg(i_regs->regmap,rs1[i]|64);
3978 sl=get_reg(i_regs->regmap,rs1[i]);
3979 if(sl>=0) emit_mov(sl,tl);
3980 else emit_loadreg(rs1[i],tl);
3982 if(sh>=0) emit_mov(sh,th);
3983 else emit_loadreg(rs1[i]|64,th);
3989 #ifndef fconv_assemble
3990 void fconv_assemble(int i,struct regstat *i_regs)
3992 printf("Need fconv_assemble for this architecture.\n");
3998 void float_assemble(int i,struct regstat *i_regs)
4000 printf("Need float_assemble for this architecture.\n");
4005 void syscall_assemble(int i,struct regstat *i_regs)
4007 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4008 assert(ccreg==HOST_CCREG);
4009 assert(!is_delayslot);
4010 emit_movimm(start+i*4,EAX); // Get PC
4011 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
4012 emit_jmp((int)jump_syscall_hle); // XXX
4015 void hlecall_assemble(int i,struct regstat *i_regs)
4017 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4018 assert(ccreg==HOST_CCREG);
4019 assert(!is_delayslot);
4020 emit_movimm(start+i*4+4,0); // Get PC
4021 emit_movimm((int)psxHLEt[source[i]&7],1);
4022 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
4023 emit_jmp((int)jump_hlecall);
4026 void intcall_assemble(int i,struct regstat *i_regs)
4028 signed char ccreg=get_reg(i_regs->regmap,CCREG);
4029 assert(ccreg==HOST_CCREG);
4030 assert(!is_delayslot);
4031 emit_movimm(start+i*4,0); // Get PC
4032 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
4033 emit_jmp((int)jump_intcall);
4036 void ds_assemble(int i,struct regstat *i_regs)
4038 speculate_register_values(i);
4042 alu_assemble(i,i_regs);break;
4044 imm16_assemble(i,i_regs);break;
4046 shift_assemble(i,i_regs);break;
4048 shiftimm_assemble(i,i_regs);break;
4050 load_assemble(i,i_regs);break;
4052 loadlr_assemble(i,i_regs);break;
4054 store_assemble(i,i_regs);break;
4056 storelr_assemble(i,i_regs);break;
4058 cop0_assemble(i,i_regs);break;
4060 cop1_assemble(i,i_regs);break;
4062 c1ls_assemble(i,i_regs);break;
4064 cop2_assemble(i,i_regs);break;
4066 c2ls_assemble(i,i_regs);break;
4068 c2op_assemble(i,i_regs);break;
4070 fconv_assemble(i,i_regs);break;
4072 float_assemble(i,i_regs);break;
4074 fcomp_assemble(i,i_regs);break;
4076 multdiv_assemble(i,i_regs);break;
4078 mov_assemble(i,i_regs);break;
4088 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4093 // Is the branch target a valid internal jump?
4094 int internal_branch(uint64_t i_is32,int addr)
4096 if(addr&1) return 0; // Indirect (register) jump
4097 if(addr>=start && addr<start+slen*4-4)
4099 int t=(addr-start)>>2;
4100 // Delay slots are not valid branch targets
4101 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4102 // 64 -> 32 bit transition requires a recompile
4103 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4105 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4106 else printf("optimizable: yes\n");
4108 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4110 if(requires_32bit[t]&~i_is32) return 0;
4118 #ifndef wb_invalidate
4119 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4120 uint64_t u,uint64_t uu)
4123 for(hr=0;hr<HOST_REGS;hr++) {
4124 if(hr!=EXCLUDE_REG) {
4125 if(pre[hr]!=entry[hr]) {
4128 if(get_reg(entry,pre[hr])<0) {
4130 if(!((u>>pre[hr])&1)) {
4131 emit_storereg(pre[hr],hr);
4132 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4133 emit_sarimm(hr,31,hr);
4134 emit_storereg(pre[hr]|64,hr);
4138 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4139 emit_storereg(pre[hr],hr);
4148 // Move from one register to another (no writeback)
4149 for(hr=0;hr<HOST_REGS;hr++) {
4150 if(hr!=EXCLUDE_REG) {
4151 if(pre[hr]!=entry[hr]) {
4152 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4154 if((nr=get_reg(entry,pre[hr]))>=0) {
4164 // Load the specified registers
4165 // This only loads the registers given as arguments because
4166 // we don't want to load things that will be overwritten
4167 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4171 for(hr=0;hr<HOST_REGS;hr++) {
4172 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4173 if(entry[hr]!=regmap[hr]) {
4174 if(regmap[hr]==rs1||regmap[hr]==rs2)
4181 emit_loadreg(regmap[hr],hr);
4188 for(hr=0;hr<HOST_REGS;hr++) {
4189 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4190 if(entry[hr]!=regmap[hr]) {
4191 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4193 assert(regmap[hr]!=64);
4194 if((is32>>(regmap[hr]&63))&1) {
4195 int lr=get_reg(regmap,regmap[hr]-64);
4197 emit_sarimm(lr,31,hr);
4199 emit_loadreg(regmap[hr],hr);
4203 emit_loadreg(regmap[hr],hr);
4211 // Load registers prior to the start of a loop
4212 // so that they are not loaded within the loop
4213 static void loop_preload(signed char pre[],signed char entry[])
4216 for(hr=0;hr<HOST_REGS;hr++) {
4217 if(hr!=EXCLUDE_REG) {
4218 if(pre[hr]!=entry[hr]) {
4220 if(get_reg(pre,entry[hr])<0) {
4221 assem_debug("loop preload:\n");
4222 //printf("loop preload: %d\n",hr);
4226 else if(entry[hr]<TEMPREG)
4228 emit_loadreg(entry[hr],hr);
4230 else if(entry[hr]-64<TEMPREG)
4232 emit_loadreg(entry[hr],hr);
4241 // Generate address for load/store instruction
4242 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4243 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4245 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4247 int agr=AGEN1+(i&1);
4248 int mgr=MGEN1+(i&1);
4249 if(itype[i]==LOAD) {
4250 ra=get_reg(i_regs->regmap,rt1[i]);
4251 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4254 if(itype[i]==LOADLR) {
4255 ra=get_reg(i_regs->regmap,FTEMP);
4257 if(itype[i]==STORE||itype[i]==STORELR) {
4258 ra=get_reg(i_regs->regmap,agr);
4259 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4261 if(itype[i]==C1LS||itype[i]==C2LS) {
4262 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4263 ra=get_reg(i_regs->regmap,FTEMP);
4264 else { // SWC1/SDC1/SWC2/SDC2
4265 ra=get_reg(i_regs->regmap,agr);
4266 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4269 int rs=get_reg(i_regs->regmap,rs1[i]);
4270 int rm=get_reg(i_regs->regmap,TLREG);
4273 int c=(i_regs->wasconst>>rs)&1;
4275 // Using r0 as a base address
4277 if(!entry||entry[rm]!=mgr) {
4278 generate_map_const(offset,rm);
4279 } // else did it in the previous cycle
4281 if(!entry||entry[ra]!=agr) {
4282 if (opcode[i]==0x22||opcode[i]==0x26) {
4283 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4284 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4285 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4287 emit_movimm(offset,ra);
4289 } // else did it in the previous cycle
4292 if(!entry||entry[ra]!=rs1[i])
4293 emit_loadreg(rs1[i],ra);
4294 //if(!entry||entry[ra]!=rs1[i])
4295 // printf("poor load scheduling!\n");
4300 if(!entry||entry[rm]!=mgr) {
4301 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4302 // Stores to memory go thru the mapper to detect self-modifying
4303 // code, loads don't.
4304 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4305 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4306 generate_map_const(constmap[i][rs]+offset,rm);
4308 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4309 generate_map_const(constmap[i][rs]+offset,rm);
4314 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4315 if(!entry||entry[ra]!=agr) {
4316 if (opcode[i]==0x22||opcode[i]==0x26) {
4317 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4318 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4319 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4321 #ifdef HOST_IMM_ADDR32
4322 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4323 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4325 emit_movimm(constmap[i][rs]+offset,ra);
4326 regs[i].loadedconst|=1<<ra;
4328 } // else did it in the previous cycle
4329 } // else load_consts already did it
4331 if(offset&&!c&&rs1[i]) {
4333 emit_addimm(rs,offset,ra);
4335 emit_addimm(ra,offset,ra);
4340 // Preload constants for next instruction
4341 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4343 #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4345 agr=MGEN1+((i+1)&1);
4346 ra=get_reg(i_regs->regmap,agr);
4348 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4349 int offset=imm[i+1];
4350 int c=(regs[i+1].wasconst>>rs)&1;
4352 if(itype[i+1]==STORE||itype[i+1]==STORELR
4353 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4354 // Stores to memory go thru the mapper to detect self-modifying
4355 // code, loads don't.
4356 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4357 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4358 generate_map_const(constmap[i+1][rs]+offset,ra);
4360 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4361 generate_map_const(constmap[i+1][rs]+offset,ra);
4364 /*else if(rs1[i]==0) {
4365 generate_map_const(offset,ra);
4370 agr=AGEN1+((i+1)&1);
4371 ra=get_reg(i_regs->regmap,agr);
4373 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4374 int offset=imm[i+1];
4375 int c=(regs[i+1].wasconst>>rs)&1;
4376 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4377 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4378 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4379 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4380 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4382 #ifdef HOST_IMM_ADDR32
4383 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4384 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4386 emit_movimm(constmap[i+1][rs]+offset,ra);
4387 regs[i+1].loadedconst|=1<<ra;
4390 else if(rs1[i+1]==0) {
4391 // Using r0 as a base address
4392 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4393 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4394 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4395 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4397 emit_movimm(offset,ra);
4404 int get_final_value(int hr, int i, int *value)
4406 int reg=regs[i].regmap[hr];
4408 if(regs[i+1].regmap[hr]!=reg) break;
4409 if(!((regs[i+1].isconst>>hr)&1)) break;
4414 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4415 *value=constmap[i][hr];
4419 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4420 // Load in delay slot, out-of-order execution
4421 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4423 #ifdef HOST_IMM_ADDR32
4424 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4426 // Precompute load address
4427 *value=constmap[i][hr]+imm[i+2];
4431 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4433 #ifdef HOST_IMM_ADDR32
4434 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4436 // Precompute load address
4437 *value=constmap[i][hr]+imm[i+1];
4438 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4443 *value=constmap[i][hr];
4444 //printf("c=%x\n",(int)constmap[i][hr]);
4445 if(i==slen-1) return 1;
4447 return !((unneeded_reg[i+1]>>reg)&1);
4449 return !((unneeded_reg_upper[i+1]>>reg)&1);
4453 // Load registers with known constants
4454 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4457 // propagate loaded constant flags
4459 regs[i].loadedconst=0;
4461 for(hr=0;hr<HOST_REGS;hr++) {
4462 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4463 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4465 regs[i].loadedconst|=1<<hr;
4470 for(hr=0;hr<HOST_REGS;hr++) {
4471 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4472 //if(entry[hr]!=regmap[hr]) {
4473 if(!((regs[i].loadedconst>>hr)&1)) {
4474 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4475 int value,similar=0;
4476 if(get_final_value(hr,i,&value)) {
4477 // see if some other register has similar value
4478 for(hr2=0;hr2<HOST_REGS;hr2++) {
4479 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4480 if(is_similar_value(value,constmap[i][hr2])) {
4488 if(get_final_value(hr2,i,&value2)) // is this needed?
4489 emit_movimm_from(value2,hr2,value,hr);
4491 emit_movimm(value,hr);
4497 emit_movimm(value,hr);
4500 regs[i].loadedconst|=1<<hr;
4506 for(hr=0;hr<HOST_REGS;hr++) {
4507 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4508 //if(entry[hr]!=regmap[hr]) {
4509 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4510 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4511 if((is32>>(regmap[hr]&63))&1) {
4512 int lr=get_reg(regmap,regmap[hr]-64);
4514 emit_sarimm(lr,31,hr);
4519 if(get_final_value(hr,i,&value)) {
4524 emit_movimm(value,hr);
4533 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4537 for(hr=0;hr<HOST_REGS;hr++) {
4538 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4539 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4540 int value=constmap[i][hr];
4545 emit_movimm(value,hr);
4551 for(hr=0;hr<HOST_REGS;hr++) {
4552 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4553 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4554 if((is32>>(regmap[hr]&63))&1) {
4555 int lr=get_reg(regmap,regmap[hr]-64);
4557 emit_sarimm(lr,31,hr);
4561 int value=constmap[i][hr];
4566 emit_movimm(value,hr);
4574 // Write out all dirty registers (except cycle count)
4575 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4578 for(hr=0;hr<HOST_REGS;hr++) {
4579 if(hr!=EXCLUDE_REG) {
4580 if(i_regmap[hr]>0) {
4581 if(i_regmap[hr]!=CCREG) {
4582 if((i_dirty>>hr)&1) {
4583 if(i_regmap[hr]<64) {
4584 emit_storereg(i_regmap[hr],hr);
4586 if( ((i_is32>>i_regmap[hr])&1) ) {
4587 #ifdef DESTRUCTIVE_WRITEBACK
4588 emit_sarimm(hr,31,hr);
4589 emit_storereg(i_regmap[hr]|64,hr);
4591 emit_sarimm(hr,31,HOST_TEMPREG);
4592 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4597 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4598 emit_storereg(i_regmap[hr],hr);
4607 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4608 // This writes the registers not written by store_regs_bt
4609 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4612 int t=(addr-start)>>2;
4613 for(hr=0;hr<HOST_REGS;hr++) {
4614 if(hr!=EXCLUDE_REG) {
4615 if(i_regmap[hr]>0) {
4616 if(i_regmap[hr]!=CCREG) {
4617 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4618 if((i_dirty>>hr)&1) {
4619 if(i_regmap[hr]<64) {
4620 emit_storereg(i_regmap[hr],hr);
4622 if( ((i_is32>>i_regmap[hr])&1) ) {
4623 #ifdef DESTRUCTIVE_WRITEBACK
4624 emit_sarimm(hr,31,hr);
4625 emit_storereg(i_regmap[hr]|64,hr);
4627 emit_sarimm(hr,31,HOST_TEMPREG);
4628 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4633 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4634 emit_storereg(i_regmap[hr],hr);
4645 // Load all registers (except cycle count)
4646 void load_all_regs(signed char i_regmap[])
4649 for(hr=0;hr<HOST_REGS;hr++) {
4650 if(hr!=EXCLUDE_REG) {
4651 if(i_regmap[hr]==0) {
4655 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4657 emit_loadreg(i_regmap[hr],hr);
4663 // Load all current registers also needed by next instruction
4664 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4667 for(hr=0;hr<HOST_REGS;hr++) {
4668 if(hr!=EXCLUDE_REG) {
4669 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4670 if(i_regmap[hr]==0) {
4674 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4676 emit_loadreg(i_regmap[hr],hr);
4683 // Load all regs, storing cycle count if necessary
4684 void load_regs_entry(int t)
4687 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4688 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4689 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4690 emit_storereg(CCREG,HOST_CCREG);
4693 for(hr=0;hr<HOST_REGS;hr++) {
4694 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4695 if(regs[t].regmap_entry[hr]==0) {
4698 else if(regs[t].regmap_entry[hr]!=CCREG)
4700 emit_loadreg(regs[t].regmap_entry[hr],hr);
4705 for(hr=0;hr<HOST_REGS;hr++) {
4706 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4707 assert(regs[t].regmap_entry[hr]!=64);
4708 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4709 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4711 emit_loadreg(regs[t].regmap_entry[hr],hr);
4715 emit_sarimm(lr,31,hr);
4720 emit_loadreg(regs[t].regmap_entry[hr],hr);
4726 // Store dirty registers prior to branch
4727 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4729 if(internal_branch(i_is32,addr))
4731 int t=(addr-start)>>2;
4733 for(hr=0;hr<HOST_REGS;hr++) {
4734 if(hr!=EXCLUDE_REG) {
4735 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4736 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4737 if((i_dirty>>hr)&1) {
4738 if(i_regmap[hr]<64) {
4739 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4740 emit_storereg(i_regmap[hr],hr);
4741 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4742 #ifdef DESTRUCTIVE_WRITEBACK
4743 emit_sarimm(hr,31,hr);
4744 emit_storereg(i_regmap[hr]|64,hr);
4746 emit_sarimm(hr,31,HOST_TEMPREG);
4747 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4752 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4753 emit_storereg(i_regmap[hr],hr);
4764 // Branch out of this block, write out all dirty regs
4765 wb_dirtys(i_regmap,i_is32,i_dirty);
4769 // Load all needed registers for branch target
4770 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4772 //if(addr>=start && addr<(start+slen*4))
4773 if(internal_branch(i_is32,addr))
4775 int t=(addr-start)>>2;
4777 // Store the cycle count before loading something else
4778 if(i_regmap[HOST_CCREG]!=CCREG) {
4779 assert(i_regmap[HOST_CCREG]==-1);
4781 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4782 emit_storereg(CCREG,HOST_CCREG);
4785 for(hr=0;hr<HOST_REGS;hr++) {
4786 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4787 #ifdef DESTRUCTIVE_WRITEBACK
4788 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4790 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4792 if(regs[t].regmap_entry[hr]==0) {
4795 else if(regs[t].regmap_entry[hr]!=CCREG)
4797 emit_loadreg(regs[t].regmap_entry[hr],hr);
4803 for(hr=0;hr<HOST_REGS;hr++) {
4804 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4805 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4806 assert(regs[t].regmap_entry[hr]!=64);
4807 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4808 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4810 emit_loadreg(regs[t].regmap_entry[hr],hr);
4814 emit_sarimm(lr,31,hr);
4819 emit_loadreg(regs[t].regmap_entry[hr],hr);
4822 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4823 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4825 emit_sarimm(lr,31,hr);
4832 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4834 if(addr>=start && addr<start+slen*4-4)
4836 int t=(addr-start)>>2;
4838 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4839 for(hr=0;hr<HOST_REGS;hr++)
4843 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4845 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4852 if(i_regmap[hr]<TEMPREG)
4854 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4857 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4859 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4864 else // Same register but is it 32-bit or dirty?
4867 if(!((regs[t].dirty>>hr)&1))
4871 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4873 //printf("%x: dirty no match\n",addr);
4878 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4880 //printf("%x: is32 no match\n",addr);
4886 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4888 if(requires_32bit[t]&~i_is32) return 0;
4890 // Delay slots are not valid branch targets
4891 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4892 // Delay slots require additional processing, so do not match
4893 if(is_ds[t]) return 0;
4898 for(hr=0;hr<HOST_REGS;hr++)
4904 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4918 // Used when a branch jumps into the delay slot of another branch
4919 void ds_assemble_entry(int i)
4921 int t=(ba[i]-start)>>2;
4922 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4923 assem_debug("Assemble delay slot at %x\n",ba[i]);
4924 assem_debug("<->\n");
4925 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4926 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4927 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4928 address_generation(t,®s[t],regs[t].regmap_entry);
4929 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4930 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4935 alu_assemble(t,®s[t]);break;
4937 imm16_assemble(t,®s[t]);break;
4939 shift_assemble(t,®s[t]);break;
4941 shiftimm_assemble(t,®s[t]);break;
4943 load_assemble(t,®s[t]);break;
4945 loadlr_assemble(t,®s[t]);break;
4947 store_assemble(t,®s[t]);break;
4949 storelr_assemble(t,®s[t]);break;
4951 cop0_assemble(t,®s[t]);break;
4953 cop1_assemble(t,®s[t]);break;
4955 c1ls_assemble(t,®s[t]);break;
4957 cop2_assemble(t,®s[t]);break;
4959 c2ls_assemble(t,®s[t]);break;
4961 c2op_assemble(t,®s[t]);break;
4963 fconv_assemble(t,®s[t]);break;
4965 float_assemble(t,®s[t]);break;
4967 fcomp_assemble(t,®s[t]);break;
4969 multdiv_assemble(t,®s[t]);break;
4971 mov_assemble(t,®s[t]);break;
4981 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4983 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4984 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4985 if(internal_branch(regs[t].is32,ba[i]+4))
4986 assem_debug("branch: internal\n");
4988 assem_debug("branch: external\n");
4989 assert(internal_branch(regs[t].is32,ba[i]+4));
4990 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4994 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
5004 //if(ba[i]>=start && ba[i]<(start+slen*4))
5005 if(internal_branch(branch_regs[i].is32,ba[i]))
5008 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
5016 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
5018 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
5020 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
5021 emit_andimm(HOST_CCREG,3,HOST_CCREG);
5025 else if(*adj==0||invert) {
5026 int cycles=CLOCK_ADJUST(count+2);
5030 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
5031 cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
5033 emit_addimm_and_set_flags(cycles,HOST_CCREG);
5039 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
5043 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
5046 void do_ccstub(int n)
5049 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
5050 set_jump_target(stubs[n][1],(int)out);
5052 if(stubs[n][6]==NULLDS) {
5053 // Delay slot instruction is nullified ("likely" branch)
5054 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
5056 else if(stubs[n][6]!=TAKEN) {
5057 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
5060 if(internal_branch(branch_regs[i].is32,ba[i]))
5061 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5065 // Save PC as return address
5066 emit_movimm(stubs[n][5],EAX);
5067 emit_writeword(EAX,(int)&pcaddr);
5071 // Return address depends on which way the branch goes
5072 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5074 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5075 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5076 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5077 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5087 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5091 #ifdef DESTRUCTIVE_WRITEBACK
5093 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5094 emit_loadreg(rs1[i],s1l);
5097 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5098 emit_loadreg(rs2[i],s1l);
5101 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5102 emit_loadreg(rs2[i],s2l);
5105 int addr=-1,alt=-1,ntaddr=-1;
5108 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5109 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5110 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5118 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5119 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5120 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5126 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5130 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5131 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5132 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5138 assert(hr<HOST_REGS);
5140 if((opcode[i]&0x2f)==4) // BEQ
5142 #ifdef HAVE_CMOV_IMM
5144 if(s2l>=0) emit_cmp(s1l,s2l);
5145 else emit_test(s1l,s1l);
5146 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5151 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5153 if(s2h>=0) emit_cmp(s1h,s2h);
5154 else emit_test(s1h,s1h);
5155 emit_cmovne_reg(alt,addr);
5157 if(s2l>=0) emit_cmp(s1l,s2l);
5158 else emit_test(s1l,s1l);
5159 emit_cmovne_reg(alt,addr);
5162 if((opcode[i]&0x2f)==5) // BNE
5164 #ifdef HAVE_CMOV_IMM
5166 if(s2l>=0) emit_cmp(s1l,s2l);
5167 else emit_test(s1l,s1l);
5168 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5173 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5175 if(s2h>=0) emit_cmp(s1h,s2h);
5176 else emit_test(s1h,s1h);
5177 emit_cmovne_reg(alt,addr);
5179 if(s2l>=0) emit_cmp(s1l,s2l);
5180 else emit_test(s1l,s1l);
5181 emit_cmovne_reg(alt,addr);
5184 if((opcode[i]&0x2f)==6) // BLEZ
5186 //emit_movimm(ba[i],alt);
5187 //emit_movimm(start+i*4+8,addr);
5188 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5190 if(s1h>=0) emit_mov(addr,ntaddr);
5191 emit_cmovl_reg(alt,addr);
5194 emit_cmovne_reg(ntaddr,addr);
5195 emit_cmovs_reg(alt,addr);
5198 if((opcode[i]&0x2f)==7) // BGTZ
5200 //emit_movimm(ba[i],addr);
5201 //emit_movimm(start+i*4+8,ntaddr);
5202 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5204 if(s1h>=0) emit_mov(addr,alt);
5205 emit_cmovl_reg(ntaddr,addr);
5208 emit_cmovne_reg(alt,addr);
5209 emit_cmovs_reg(ntaddr,addr);
5212 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5214 //emit_movimm(ba[i],alt);
5215 //emit_movimm(start+i*4+8,addr);
5216 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5217 if(s1h>=0) emit_test(s1h,s1h);
5218 else emit_test(s1l,s1l);
5219 emit_cmovs_reg(alt,addr);
5221 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5223 //emit_movimm(ba[i],addr);
5224 //emit_movimm(start+i*4+8,alt);
5225 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5226 if(s1h>=0) emit_test(s1h,s1h);
5227 else emit_test(s1l,s1l);
5228 emit_cmovs_reg(alt,addr);
5230 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5231 if(source[i]&0x10000) // BC1T
5233 //emit_movimm(ba[i],alt);
5234 //emit_movimm(start+i*4+8,addr);
5235 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5236 emit_testimm(s1l,0x800000);
5237 emit_cmovne_reg(alt,addr);
5241 //emit_movimm(ba[i],addr);
5242 //emit_movimm(start+i*4+8,alt);
5243 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5244 emit_testimm(s1l,0x800000);
5245 emit_cmovne_reg(alt,addr);
5248 emit_writeword(addr,(int)&pcaddr);
5253 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5254 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5255 r=get_reg(branch_regs[i].regmap,RTEMP);
5257 emit_writeword(r,(int)&pcaddr);
5259 else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
5261 // Update cycle count
5262 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5263 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5264 emit_call((int)cc_interrupt);
5265 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5266 if(stubs[n][6]==TAKEN) {
5267 if(internal_branch(branch_regs[i].is32,ba[i]))
5268 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5269 else if(itype[i]==RJUMP) {
5270 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5271 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5273 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5275 }else if(stubs[n][6]==NOTTAKEN) {
5276 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5277 else load_all_regs(branch_regs[i].regmap);
5278 }else if(stubs[n][6]==NULLDS) {
5279 // Delay slot instruction is nullified ("likely" branch)
5280 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5281 else load_all_regs(regs[i].regmap);
5283 load_all_regs(branch_regs[i].regmap);
5285 emit_jmp(stubs[n][2]); // return address
5287 /* This works but uses a lot of memory...
5288 emit_readword((int)&last_count,ECX);
5289 emit_add(HOST_CCREG,ECX,EAX);
5290 emit_writeword(EAX,(int)&Count);
5291 emit_call((int)gen_interupt);
5292 emit_readword((int)&Count,HOST_CCREG);
5293 emit_readword((int)&next_interupt,EAX);
5294 emit_readword((int)&pending_exception,EBX);
5295 emit_writeword(EAX,(int)&last_count);
5296 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5298 int jne_instr=(int)out;
5300 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5301 load_all_regs(branch_regs[i].regmap);
5302 emit_jmp(stubs[n][2]); // return address
5303 set_jump_target(jne_instr,(int)out);
5304 emit_readword((int)&pcaddr,EAX);
5305 // Call get_addr_ht instead of doing the hash table here.
5306 // This code is executed infrequently and takes up a lot of space
5307 // so smaller is better.
5308 emit_storereg(CCREG,HOST_CCREG);
5310 emit_call((int)get_addr_ht);
5311 emit_loadreg(CCREG,HOST_CCREG);
5312 emit_addimm(ESP,4,ESP);
5316 add_to_linker(int addr,int target,int ext)
5318 link_addr[linkcount][0]=addr;
5319 link_addr[linkcount][1]=target;
5320 link_addr[linkcount][2]=ext;
5324 static void ujump_assemble_write_ra(int i)
5327 unsigned int return_address;
5328 rt=get_reg(branch_regs[i].regmap,31);
5329 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5331 return_address=start+i*4+8;
5334 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5335 int temp=-1; // note: must be ds-safe
5339 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5340 else emit_movimm(return_address,rt);
5348 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5351 emit_movimm(return_address,rt); // PC into link register
5353 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5359 void ujump_assemble(int i,struct regstat *i_regs)
5361 signed char *i_regmap=i_regs->regmap;
5363 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5364 address_generation(i+1,i_regs,regs[i].regmap_entry);
5366 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5367 if(rt1[i]==31&&temp>=0)
5369 int return_address=start+i*4+8;
5370 if(get_reg(branch_regs[i].regmap,31)>0)
5371 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5374 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5375 ujump_assemble_write_ra(i); // writeback ra for DS
5378 ds_assemble(i+1,i_regs);
5379 uint64_t bc_unneeded=branch_regs[i].u;
5380 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5381 bc_unneeded|=1|(1LL<<rt1[i]);
5382 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5383 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5384 bc_unneeded,bc_unneeded_upper);
5385 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5386 if(!ra_done&&rt1[i]==31)
5387 ujump_assemble_write_ra(i);
5389 cc=get_reg(branch_regs[i].regmap,CCREG);
5390 assert(cc==HOST_CCREG);
5391 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5393 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5395 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5396 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5397 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5398 if(internal_branch(branch_regs[i].is32,ba[i]))
5399 assem_debug("branch: internal\n");
5401 assem_debug("branch: external\n");
5402 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5403 ds_assemble_entry(i);
5406 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5411 static void rjump_assemble_write_ra(int i)
5413 int rt,return_address;
5414 assert(rt1[i+1]!=rt1[i]);
5415 assert(rt2[i+1]!=rt1[i]);
5416 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5417 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5419 return_address=start+i*4+8;
5423 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5426 emit_movimm(return_address,rt); // PC into link register
5428 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5432 void rjump_assemble(int i,struct regstat *i_regs)
5434 signed char *i_regmap=i_regs->regmap;
5438 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5440 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5441 // Delay slot abuse, make a copy of the branch address register
5442 temp=get_reg(branch_regs[i].regmap,RTEMP);
5444 assert(regs[i].regmap[temp]==RTEMP);
5448 address_generation(i+1,i_regs,regs[i].regmap_entry);
5452 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5453 int return_address=start+i*4+8;
5454 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5460 int rh=get_reg(regs[i].regmap,RHASH);
5461 if(rh>=0) do_preload_rhash(rh);
5464 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5465 rjump_assemble_write_ra(i);
5468 ds_assemble(i+1,i_regs);
5469 uint64_t bc_unneeded=branch_regs[i].u;
5470 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5471 bc_unneeded|=1|(1LL<<rt1[i]);
5472 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5473 bc_unneeded&=~(1LL<<rs1[i]);
5474 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5475 bc_unneeded,bc_unneeded_upper);
5476 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5477 if(!ra_done&&rt1[i]!=0)
5478 rjump_assemble_write_ra(i);
5479 cc=get_reg(branch_regs[i].regmap,CCREG);
5480 assert(cc==HOST_CCREG);
5482 int rh=get_reg(branch_regs[i].regmap,RHASH);
5483 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5485 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5486 do_preload_rhtbl(ht);
5490 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5491 #ifdef DESTRUCTIVE_WRITEBACK
5492 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5493 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5494 emit_loadreg(rs1[i],rs);
5499 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5503 do_miniht_load(ht,rh);
5506 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5507 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5509 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5510 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5512 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5513 // special case for RFE
5518 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5521 do_miniht_jump(rs,rh,ht);
5526 //if(rs!=EAX) emit_mov(rs,EAX);
5527 //emit_jmp((int)jump_vaddr_eax);
5528 emit_jmp(jump_vaddr_reg[rs]);
5533 emit_shrimm(rs,16,rs);
5534 emit_xor(temp,rs,rs);
5535 emit_movzwl_reg(rs,rs);
5536 emit_shlimm(rs,4,rs);
5537 emit_cmpmem_indexed((int)hash_table,rs,temp);
5538 emit_jne((int)out+14);
5539 emit_readword_indexed((int)hash_table+4,rs,rs);
5541 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5542 emit_addimm_no_flags(8,rs);
5543 emit_jeq((int)out-17);
5544 // No hit on hash table, call compiler
5547 #ifdef DEBUG_CYCLE_COUNT
5548 emit_readword((int)&last_count,ECX);
5549 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5550 emit_readword((int)&next_interupt,ECX);
5551 emit_writeword(HOST_CCREG,(int)&Count);
5552 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5553 emit_writeword(ECX,(int)&last_count);
5556 emit_storereg(CCREG,HOST_CCREG);
5557 emit_call((int)get_addr);
5558 emit_loadreg(CCREG,HOST_CCREG);
5559 emit_addimm(ESP,4,ESP);
5561 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5562 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5566 void cjump_assemble(int i,struct regstat *i_regs)
5568 signed char *i_regmap=i_regs->regmap;
5571 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5572 assem_debug("match=%d\n",match);
5573 int s1h,s1l,s2h,s2l;
5574 int prev_cop1_usable=cop1_usable;
5575 int unconditional=0,nop=0;
5578 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5579 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5580 if(!match) invert=1;
5581 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5582 if(i>(ba[i]-start)>>2) invert=1;
5586 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5587 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5588 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5589 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5592 s1l=get_reg(i_regmap,rs1[i]);
5593 s1h=get_reg(i_regmap,rs1[i]|64);
5594 s2l=get_reg(i_regmap,rs2[i]);
5595 s2h=get_reg(i_regmap,rs2[i]|64);
5597 if(rs1[i]==0&&rs2[i]==0)
5599 if(opcode[i]&1) nop=1;
5600 else unconditional=1;
5601 //assert(opcode[i]!=5);
5602 //assert(opcode[i]!=7);
5603 //assert(opcode[i]!=0x15);
5604 //assert(opcode[i]!=0x17);
5610 only32=(regs[i].was32>>rs2[i])&1;
5615 only32=(regs[i].was32>>rs1[i])&1;
5618 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5622 // Out of order execution (delay slot first)
5624 address_generation(i+1,i_regs,regs[i].regmap_entry);
5625 ds_assemble(i+1,i_regs);
5627 uint64_t bc_unneeded=branch_regs[i].u;
5628 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5629 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5630 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5632 bc_unneeded_upper|=1;
5633 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5634 bc_unneeded,bc_unneeded_upper);
5635 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5636 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5637 cc=get_reg(branch_regs[i].regmap,CCREG);
5638 assert(cc==HOST_CCREG);
5640 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5641 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5642 //assem_debug("cycle count (adj)\n");
5644 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5645 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5646 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5647 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5649 assem_debug("branch: internal\n");
5651 assem_debug("branch: external\n");
5652 if(internal&&is_ds[(ba[i]-start)>>2]) {
5653 ds_assemble_entry(i);
5656 add_to_linker((int)out,ba[i],internal);
5659 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5660 if(((u_int)out)&7) emit_addnop(0);
5665 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5668 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5671 int taken=0,nottaken=0,nottaken1=0;
5672 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5673 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5677 if(opcode[i]==4) // BEQ
5679 if(s2h>=0) emit_cmp(s1h,s2h);
5680 else emit_test(s1h,s1h);
5684 if(opcode[i]==5) // BNE
5686 if(s2h>=0) emit_cmp(s1h,s2h);
5687 else emit_test(s1h,s1h);
5688 if(invert) taken=(int)out;
5689 else add_to_linker((int)out,ba[i],internal);
5692 if(opcode[i]==6) // BLEZ
5695 if(invert) taken=(int)out;
5696 else add_to_linker((int)out,ba[i],internal);
5701 if(opcode[i]==7) // BGTZ
5706 if(invert) taken=(int)out;
5707 else add_to_linker((int)out,ba[i],internal);
5712 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5714 if(opcode[i]==4) // BEQ
5716 if(s2l>=0) emit_cmp(s1l,s2l);
5717 else emit_test(s1l,s1l);
5722 add_to_linker((int)out,ba[i],internal);
5726 if(opcode[i]==5) // BNE
5728 if(s2l>=0) emit_cmp(s1l,s2l);
5729 else emit_test(s1l,s1l);
5734 add_to_linker((int)out,ba[i],internal);
5738 if(opcode[i]==6) // BLEZ
5745 add_to_linker((int)out,ba[i],internal);
5749 if(opcode[i]==7) // BGTZ
5756 add_to_linker((int)out,ba[i],internal);
5761 if(taken) set_jump_target(taken,(int)out);
5762 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5763 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5765 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5766 add_to_linker((int)out,ba[i],internal);
5769 add_to_linker((int)out,ba[i],internal*2);
5775 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5776 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5777 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5779 assem_debug("branch: internal\n");
5781 assem_debug("branch: external\n");
5782 if(internal&&is_ds[(ba[i]-start)>>2]) {
5783 ds_assemble_entry(i);
5786 add_to_linker((int)out,ba[i],internal);
5790 set_jump_target(nottaken,(int)out);
5793 if(nottaken1) set_jump_target(nottaken1,(int)out);
5795 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5797 } // (!unconditional)
5801 // In-order execution (branch first)
5802 //if(likely[i]) printf("IOL\n");
5805 int taken=0,nottaken=0,nottaken1=0;
5806 if(!unconditional&&!nop) {
5810 if((opcode[i]&0x2f)==4) // BEQ
5812 if(s2h>=0) emit_cmp(s1h,s2h);
5813 else emit_test(s1h,s1h);
5817 if((opcode[i]&0x2f)==5) // BNE
5819 if(s2h>=0) emit_cmp(s1h,s2h);
5820 else emit_test(s1h,s1h);
5824 if((opcode[i]&0x2f)==6) // BLEZ
5832 if((opcode[i]&0x2f)==7) // BGTZ
5842 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5844 if((opcode[i]&0x2f)==4) // BEQ
5846 if(s2l>=0) emit_cmp(s1l,s2l);
5847 else emit_test(s1l,s1l);
5851 if((opcode[i]&0x2f)==5) // BNE
5853 if(s2l>=0) emit_cmp(s1l,s2l);
5854 else emit_test(s1l,s1l);
5858 if((opcode[i]&0x2f)==6) // BLEZ
5864 if((opcode[i]&0x2f)==7) // BGTZ
5870 } // if(!unconditional)
5872 uint64_t ds_unneeded=branch_regs[i].u;
5873 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5874 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5875 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5876 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5878 ds_unneeded_upper|=1;
5881 if(taken) set_jump_target(taken,(int)out);
5882 assem_debug("1:\n");
5883 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5884 ds_unneeded,ds_unneeded_upper);
5886 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5887 address_generation(i+1,&branch_regs[i],0);
5888 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5889 ds_assemble(i+1,&branch_regs[i]);
5890 cc=get_reg(branch_regs[i].regmap,CCREG);
5892 emit_loadreg(CCREG,cc=HOST_CCREG);
5893 // CHECK: Is the following instruction (fall thru) allocated ok?
5895 assert(cc==HOST_CCREG);
5896 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5897 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5898 assem_debug("cycle count (adj)\n");
5899 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5900 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5902 assem_debug("branch: internal\n");
5904 assem_debug("branch: external\n");
5905 if(internal&&is_ds[(ba[i]-start)>>2]) {
5906 ds_assemble_entry(i);
5909 add_to_linker((int)out,ba[i],internal);
5914 cop1_usable=prev_cop1_usable;
5915 if(!unconditional) {
5916 if(nottaken1) set_jump_target(nottaken1,(int)out);
5917 set_jump_target(nottaken,(int)out);
5918 assem_debug("2:\n");
5920 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5921 ds_unneeded,ds_unneeded_upper);
5922 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5923 address_generation(i+1,&branch_regs[i],0);
5924 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5925 ds_assemble(i+1,&branch_regs[i]);
5927 cc=get_reg(branch_regs[i].regmap,CCREG);
5928 if(cc==-1&&!likely[i]) {
5929 // Cycle count isn't in a register, temporarily load it then write it out
5930 emit_loadreg(CCREG,HOST_CCREG);
5931 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5934 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5935 emit_storereg(CCREG,HOST_CCREG);
5938 cc=get_reg(i_regmap,CCREG);
5939 assert(cc==HOST_CCREG);
5940 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5943 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5949 void sjump_assemble(int i,struct regstat *i_regs)
5951 signed char *i_regmap=i_regs->regmap;
5954 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5955 assem_debug("smatch=%d\n",match);
5957 int prev_cop1_usable=cop1_usable;
5958 int unconditional=0,nevertaken=0;
5961 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5962 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5963 if(!match) invert=1;
5964 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5965 if(i>(ba[i]-start)>>2) invert=1;
5968 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5969 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5972 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5973 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5976 s1l=get_reg(i_regmap,rs1[i]);
5977 s1h=get_reg(i_regmap,rs1[i]|64);
5981 if(opcode2[i]&1) unconditional=1;
5983 // These are never taken (r0 is never less than zero)
5984 //assert(opcode2[i]!=0);
5985 //assert(opcode2[i]!=2);
5986 //assert(opcode2[i]!=0x10);
5987 //assert(opcode2[i]!=0x12);
5990 only32=(regs[i].was32>>rs1[i])&1;
5994 // Out of order execution (delay slot first)
5996 address_generation(i+1,i_regs,regs[i].regmap_entry);
5997 ds_assemble(i+1,i_regs);
5999 uint64_t bc_unneeded=branch_regs[i].u;
6000 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6001 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6002 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6004 bc_unneeded_upper|=1;
6005 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6006 bc_unneeded,bc_unneeded_upper);
6007 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6008 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6010 int rt,return_address;
6011 rt=get_reg(branch_regs[i].regmap,31);
6012 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6014 // Save the PC even if the branch is not taken
6015 return_address=start+i*4+8;
6016 emit_movimm(return_address,rt); // PC into link register
6018 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6022 cc=get_reg(branch_regs[i].regmap,CCREG);
6023 assert(cc==HOST_CCREG);
6025 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6026 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
6027 assem_debug("cycle count (adj)\n");
6029 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
6030 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
6031 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6032 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6034 assem_debug("branch: internal\n");
6036 assem_debug("branch: external\n");
6037 if(internal&&is_ds[(ba[i]-start)>>2]) {
6038 ds_assemble_entry(i);
6041 add_to_linker((int)out,ba[i],internal);
6044 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6045 if(((u_int)out)&7) emit_addnop(0);
6049 else if(nevertaken) {
6050 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6053 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6057 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6058 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6062 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6069 add_to_linker((int)out,ba[i],internal);
6073 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6080 add_to_linker((int)out,ba[i],internal);
6088 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6095 add_to_linker((int)out,ba[i],internal);
6099 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6106 add_to_linker((int)out,ba[i],internal);
6113 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6114 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6116 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6117 add_to_linker((int)out,ba[i],internal);
6120 add_to_linker((int)out,ba[i],internal*2);
6126 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6127 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6128 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6130 assem_debug("branch: internal\n");
6132 assem_debug("branch: external\n");
6133 if(internal&&is_ds[(ba[i]-start)>>2]) {
6134 ds_assemble_entry(i);
6137 add_to_linker((int)out,ba[i],internal);
6141 set_jump_target(nottaken,(int)out);
6145 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6147 } // (!unconditional)
6151 // In-order execution (branch first)
6155 int rt,return_address;
6156 rt=get_reg(branch_regs[i].regmap,31);
6158 // Save the PC even if the branch is not taken
6159 return_address=start+i*4+8;
6160 emit_movimm(return_address,rt); // PC into link register
6162 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6166 if(!unconditional) {
6167 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6171 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6177 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6187 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6193 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6200 } // if(!unconditional)
6202 uint64_t ds_unneeded=branch_regs[i].u;
6203 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6204 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6205 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6206 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6208 ds_unneeded_upper|=1;
6211 //assem_debug("1:\n");
6212 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6213 ds_unneeded,ds_unneeded_upper);
6215 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6216 address_generation(i+1,&branch_regs[i],0);
6217 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6218 ds_assemble(i+1,&branch_regs[i]);
6219 cc=get_reg(branch_regs[i].regmap,CCREG);
6221 emit_loadreg(CCREG,cc=HOST_CCREG);
6222 // CHECK: Is the following instruction (fall thru) allocated ok?
6224 assert(cc==HOST_CCREG);
6225 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6226 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6227 assem_debug("cycle count (adj)\n");
6228 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6229 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6231 assem_debug("branch: internal\n");
6233 assem_debug("branch: external\n");
6234 if(internal&&is_ds[(ba[i]-start)>>2]) {
6235 ds_assemble_entry(i);
6238 add_to_linker((int)out,ba[i],internal);
6243 cop1_usable=prev_cop1_usable;
6244 if(!unconditional) {
6245 set_jump_target(nottaken,(int)out);
6246 assem_debug("1:\n");
6248 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6249 ds_unneeded,ds_unneeded_upper);
6250 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6251 address_generation(i+1,&branch_regs[i],0);
6252 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6253 ds_assemble(i+1,&branch_regs[i]);
6255 cc=get_reg(branch_regs[i].regmap,CCREG);
6256 if(cc==-1&&!likely[i]) {
6257 // Cycle count isn't in a register, temporarily load it then write it out
6258 emit_loadreg(CCREG,HOST_CCREG);
6259 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6262 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6263 emit_storereg(CCREG,HOST_CCREG);
6266 cc=get_reg(i_regmap,CCREG);
6267 assert(cc==HOST_CCREG);
6268 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6271 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6277 void fjump_assemble(int i,struct regstat *i_regs)
6279 signed char *i_regmap=i_regs->regmap;
6282 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6283 assem_debug("fmatch=%d\n",match);
6287 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6288 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6289 if(!match) invert=1;
6290 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6291 if(i>(ba[i]-start)>>2) invert=1;
6295 fs=get_reg(branch_regs[i].regmap,FSREG);
6296 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6299 fs=get_reg(i_regmap,FSREG);
6302 // Check cop1 unusable
6304 cs=get_reg(i_regmap,CSREG);
6306 emit_testimm(cs,0x20000000);
6309 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6314 // Out of order execution (delay slot first)
6316 ds_assemble(i+1,i_regs);
6318 uint64_t bc_unneeded=branch_regs[i].u;
6319 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6320 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6321 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6323 bc_unneeded_upper|=1;
6324 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6325 bc_unneeded,bc_unneeded_upper);
6326 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6327 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6328 cc=get_reg(branch_regs[i].regmap,CCREG);
6329 assert(cc==HOST_CCREG);
6330 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6331 assem_debug("cycle count (adj)\n");
6334 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6337 emit_testimm(fs,0x800000);
6338 if(source[i]&0x10000) // BC1T
6344 add_to_linker((int)out,ba[i],internal);
6353 add_to_linker((int)out,ba[i],internal);
6361 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6362 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6363 else if(match) emit_addnop(13);
6365 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6366 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6368 assem_debug("branch: internal\n");
6370 assem_debug("branch: external\n");
6371 if(internal&&is_ds[(ba[i]-start)>>2]) {
6372 ds_assemble_entry(i);
6375 add_to_linker((int)out,ba[i],internal);
6378 set_jump_target(nottaken,(int)out);
6382 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6384 } // (!unconditional)
6388 // In-order execution (branch first)
6392 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6395 emit_testimm(fs,0x800000);
6396 if(source[i]&0x10000) // BC1T
6407 } // if(!unconditional)
6409 uint64_t ds_unneeded=branch_regs[i].u;
6410 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6411 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6412 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6413 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6415 ds_unneeded_upper|=1;
6417 //assem_debug("1:\n");
6418 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6419 ds_unneeded,ds_unneeded_upper);
6421 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6422 address_generation(i+1,&branch_regs[i],0);
6423 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6424 ds_assemble(i+1,&branch_regs[i]);
6425 cc=get_reg(branch_regs[i].regmap,CCREG);
6427 emit_loadreg(CCREG,cc=HOST_CCREG);
6428 // CHECK: Is the following instruction (fall thru) allocated ok?
6430 assert(cc==HOST_CCREG);
6431 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6432 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6433 assem_debug("cycle count (adj)\n");
6434 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6435 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6437 assem_debug("branch: internal\n");
6439 assem_debug("branch: external\n");
6440 if(internal&&is_ds[(ba[i]-start)>>2]) {
6441 ds_assemble_entry(i);
6444 add_to_linker((int)out,ba[i],internal);
6449 if(1) { // <- FIXME (don't need this)
6450 set_jump_target(nottaken,(int)out);
6451 assem_debug("1:\n");
6453 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6454 ds_unneeded,ds_unneeded_upper);
6455 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6456 address_generation(i+1,&branch_regs[i],0);
6457 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6458 ds_assemble(i+1,&branch_regs[i]);
6460 cc=get_reg(branch_regs[i].regmap,CCREG);
6461 if(cc==-1&&!likely[i]) {
6462 // Cycle count isn't in a register, temporarily load it then write it out
6463 emit_loadreg(CCREG,HOST_CCREG);
6464 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6467 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6468 emit_storereg(CCREG,HOST_CCREG);
6471 cc=get_reg(i_regmap,CCREG);
6472 assert(cc==HOST_CCREG);
6473 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6476 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6482 static void pagespan_assemble(int i,struct regstat *i_regs)
6484 int s1l=get_reg(i_regs->regmap,rs1[i]);
6485 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6486 int s2l=get_reg(i_regs->regmap,rs2[i]);
6487 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6488 void *nt_branch=NULL;
6491 int unconditional=0;
6501 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6505 int addr,alt,ntaddr;
6506 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6510 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6511 (i_regs->regmap[hr]&63)!=rs1[i] &&
6512 (i_regs->regmap[hr]&63)!=rs2[i] )
6521 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6522 (i_regs->regmap[hr]&63)!=rs1[i] &&
6523 (i_regs->regmap[hr]&63)!=rs2[i] )
6529 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6533 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6534 (i_regs->regmap[hr]&63)!=rs1[i] &&
6535 (i_regs->regmap[hr]&63)!=rs2[i] )
6542 assert(hr<HOST_REGS);
6543 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6544 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6546 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6547 if(opcode[i]==2) // J
6551 if(opcode[i]==3) // JAL
6554 int rt=get_reg(i_regs->regmap,31);
6555 emit_movimm(start+i*4+8,rt);
6558 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6561 if(opcode2[i]==9) // JALR
6563 int rt=get_reg(i_regs->regmap,rt1[i]);
6564 emit_movimm(start+i*4+8,rt);
6567 if((opcode[i]&0x3f)==4) // BEQ
6574 #ifdef HAVE_CMOV_IMM
6576 if(s2l>=0) emit_cmp(s1l,s2l);
6577 else emit_test(s1l,s1l);
6578 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6584 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6586 if(s2h>=0) emit_cmp(s1h,s2h);
6587 else emit_test(s1h,s1h);
6588 emit_cmovne_reg(alt,addr);
6590 if(s2l>=0) emit_cmp(s1l,s2l);
6591 else emit_test(s1l,s1l);
6592 emit_cmovne_reg(alt,addr);
6595 if((opcode[i]&0x3f)==5) // BNE
6597 #ifdef HAVE_CMOV_IMM
6599 if(s2l>=0) emit_cmp(s1l,s2l);
6600 else emit_test(s1l,s1l);
6601 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6607 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6609 if(s2h>=0) emit_cmp(s1h,s2h);
6610 else emit_test(s1h,s1h);
6611 emit_cmovne_reg(alt,addr);
6613 if(s2l>=0) emit_cmp(s1l,s2l);
6614 else emit_test(s1l,s1l);
6615 emit_cmovne_reg(alt,addr);
6618 if((opcode[i]&0x3f)==0x14) // BEQL
6621 if(s2h>=0) emit_cmp(s1h,s2h);
6622 else emit_test(s1h,s1h);
6626 if(s2l>=0) emit_cmp(s1l,s2l);
6627 else emit_test(s1l,s1l);
6628 if(nottaken) set_jump_target(nottaken,(int)out);
6632 if((opcode[i]&0x3f)==0x15) // BNEL
6635 if(s2h>=0) emit_cmp(s1h,s2h);
6636 else emit_test(s1h,s1h);
6640 if(s2l>=0) emit_cmp(s1l,s2l);
6641 else emit_test(s1l,s1l);
6644 if(taken) set_jump_target(taken,(int)out);
6646 if((opcode[i]&0x3f)==6) // BLEZ
6648 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6650 if(s1h>=0) emit_mov(addr,ntaddr);
6651 emit_cmovl_reg(alt,addr);
6654 emit_cmovne_reg(ntaddr,addr);
6655 emit_cmovs_reg(alt,addr);
6658 if((opcode[i]&0x3f)==7) // BGTZ
6660 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6662 if(s1h>=0) emit_mov(addr,alt);
6663 emit_cmovl_reg(ntaddr,addr);
6666 emit_cmovne_reg(alt,addr);
6667 emit_cmovs_reg(ntaddr,addr);
6670 if((opcode[i]&0x3f)==0x16) // BLEZL
6672 assert((opcode[i]&0x3f)!=0x16);
6674 if((opcode[i]&0x3f)==0x17) // BGTZL
6676 assert((opcode[i]&0x3f)!=0x17);
6678 assert(opcode[i]!=1); // BLTZ/BGEZ
6680 //FIXME: Check CSREG
6681 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6682 if((source[i]&0x30000)==0) // BC1F
6684 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6685 emit_testimm(s1l,0x800000);
6686 emit_cmovne_reg(alt,addr);
6688 if((source[i]&0x30000)==0x10000) // BC1T
6690 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6691 emit_testimm(s1l,0x800000);
6692 emit_cmovne_reg(alt,addr);
6694 if((source[i]&0x30000)==0x20000) // BC1FL
6696 emit_testimm(s1l,0x800000);
6700 if((source[i]&0x30000)==0x30000) // BC1TL
6702 emit_testimm(s1l,0x800000);
6708 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6709 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6710 if(likely[i]||unconditional)
6712 emit_movimm(ba[i],HOST_BTREG);
6714 else if(addr!=HOST_BTREG)
6716 emit_mov(addr,HOST_BTREG);
6718 void *branch_addr=out;
6720 int target_addr=start+i*4+5;
6722 void *compiled_target_addr=check_addr(target_addr);
6723 emit_extjump_ds((int)branch_addr,target_addr);
6724 if(compiled_target_addr) {
6725 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6726 add_link(target_addr,stub);
6728 else set_jump_target((int)branch_addr,(int)stub);
6731 set_jump_target((int)nottaken,(int)out);
6732 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6733 void *branch_addr=out;
6735 int target_addr=start+i*4+8;
6737 void *compiled_target_addr=check_addr(target_addr);
6738 emit_extjump_ds((int)branch_addr,target_addr);
6739 if(compiled_target_addr) {
6740 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6741 add_link(target_addr,stub);
6743 else set_jump_target((int)branch_addr,(int)stub);
6747 // Assemble the delay slot for the above
6748 static void pagespan_ds()
6750 assem_debug("initial delay slot:\n");
6751 u_int vaddr=start+1;
6752 u_int page=get_page(vaddr);
6753 u_int vpage=get_vpage(vaddr);
6754 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6756 ll_add(jump_in+page,vaddr,(void *)out);
6757 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6758 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6759 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6760 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6761 emit_writeword(HOST_BTREG,(int)&branch_target);
6762 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6763 address_generation(0,®s[0],regs[0].regmap_entry);
6764 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6765 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6770 alu_assemble(0,®s[0]);break;
6772 imm16_assemble(0,®s[0]);break;
6774 shift_assemble(0,®s[0]);break;
6776 shiftimm_assemble(0,®s[0]);break;
6778 load_assemble(0,®s[0]);break;
6780 loadlr_assemble(0,®s[0]);break;
6782 store_assemble(0,®s[0]);break;
6784 storelr_assemble(0,®s[0]);break;
6786 cop0_assemble(0,®s[0]);break;
6788 cop1_assemble(0,®s[0]);break;
6790 c1ls_assemble(0,®s[0]);break;
6792 cop2_assemble(0,®s[0]);break;
6794 c2ls_assemble(0,®s[0]);break;
6796 c2op_assemble(0,®s[0]);break;
6798 fconv_assemble(0,®s[0]);break;
6800 float_assemble(0,®s[0]);break;
6802 fcomp_assemble(0,®s[0]);break;
6804 multdiv_assemble(0,®s[0]);break;
6806 mov_assemble(0,®s[0]);break;
6816 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
6818 int btaddr=get_reg(regs[0].regmap,BTREG);
6820 btaddr=get_reg(regs[0].regmap,-1);
6821 emit_readword((int)&branch_target,btaddr);
6823 assert(btaddr!=HOST_CCREG);
6824 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6826 emit_movimm(start+4,HOST_TEMPREG);
6827 emit_cmp(btaddr,HOST_TEMPREG);
6829 emit_cmpimm(btaddr,start+4);
6831 int branch=(int)out;
6833 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6834 emit_jmp(jump_vaddr_reg[btaddr]);
6835 set_jump_target(branch,(int)out);
6836 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6837 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6840 // Basic liveness analysis for MIPS registers
6841 void unneeded_registers(int istart,int iend,int r)
6844 uint64_t u,uu,gte_u,b,bu,gte_bu;
6845 uint64_t temp_u,temp_uu,temp_gte_u=0;
6847 uint64_t gte_u_unknown=0;
6848 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6852 gte_u=gte_u_unknown;
6854 u=unneeded_reg[iend+1];
6855 uu=unneeded_reg_upper[iend+1];
6857 gte_u=gte_unneeded[iend+1];
6860 for (i=iend;i>=istart;i--)
6862 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6863 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6865 // If subroutine call, flag return address as a possible branch target
6866 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6868 if(ba[i]<start || ba[i]>=(start+slen*4))
6870 // Branch out of this block, flush all regs
6873 gte_u=gte_u_unknown;
6875 if(itype[i]==UJUMP&&rt1[i]==31)
6877 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6879 if(itype[i]==RJUMP&&rs1[i]==31)
6881 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6883 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6884 if(itype[i]==UJUMP&&rt1[i]==31)
6886 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6887 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6889 if(itype[i]==RJUMP&&rs1[i]==31)
6891 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6892 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6895 branch_unneeded_reg[i]=u;
6896 branch_unneeded_reg_upper[i]=uu;
6897 // Merge in delay slot
6898 tdep=(~uu>>rt1[i+1])&1;
6899 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6900 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6901 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6902 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6903 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6906 gte_u&=~gte_rs[i+1];
6907 // If branch is "likely" (and conditional)
6908 // then we skip the delay slot on the fall-thru path
6911 u&=unneeded_reg[i+2];
6912 uu&=unneeded_reg_upper[i+2];
6913 gte_u&=gte_unneeded[i+2];
6919 gte_u=gte_u_unknown;
6925 // Internal branch, flag target
6926 bt[(ba[i]-start)>>2]=1;
6927 if(ba[i]<=start+i*4) {
6929 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6931 // Unconditional branch
6935 // Conditional branch (not taken case)
6936 temp_u=unneeded_reg[i+2];
6937 temp_uu=unneeded_reg_upper[i+2];
6938 temp_gte_u&=gte_unneeded[i+2];
6940 // Merge in delay slot
6941 tdep=(~temp_uu>>rt1[i+1])&1;
6942 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6943 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6944 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6945 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6946 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6947 temp_u|=1;temp_uu|=1;
6948 temp_gte_u|=gte_rt[i+1];
6949 temp_gte_u&=~gte_rs[i+1];
6950 // If branch is "likely" (and conditional)
6951 // then we skip the delay slot on the fall-thru path
6954 temp_u&=unneeded_reg[i+2];
6955 temp_uu&=unneeded_reg_upper[i+2];
6956 temp_gte_u&=gte_unneeded[i+2];
6962 temp_gte_u=gte_u_unknown;
6965 tdep=(~temp_uu>>rt1[i])&1;
6966 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6967 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6968 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6969 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6970 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6971 temp_u|=1;temp_uu|=1;
6972 temp_gte_u|=gte_rt[i];
6973 temp_gte_u&=~gte_rs[i];
6974 unneeded_reg[i]=temp_u;
6975 unneeded_reg_upper[i]=temp_uu;
6976 gte_unneeded[i]=temp_gte_u;
6977 // Only go three levels deep. This recursion can take an
6978 // excessive amount of time if there are a lot of nested loops.
6980 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6982 unneeded_reg[(ba[i]-start)>>2]=1;
6983 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6984 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6987 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6989 // Unconditional branch
6990 u=unneeded_reg[(ba[i]-start)>>2];
6991 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6992 gte_u=gte_unneeded[(ba[i]-start)>>2];
6993 branch_unneeded_reg[i]=u;
6994 branch_unneeded_reg_upper[i]=uu;
6997 //branch_unneeded_reg[i]=u;
6998 //branch_unneeded_reg_upper[i]=uu;
6999 // Merge in delay slot
7000 tdep=(~uu>>rt1[i+1])&1;
7001 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7002 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7003 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7004 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
7005 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
7008 gte_u&=~gte_rs[i+1];
7010 // Conditional branch
7011 b=unneeded_reg[(ba[i]-start)>>2];
7012 bu=unneeded_reg_upper[(ba[i]-start)>>2];
7013 gte_bu=gte_unneeded[(ba[i]-start)>>2];
7014 branch_unneeded_reg[i]=b;
7015 branch_unneeded_reg_upper[i]=bu;
7018 //branch_unneeded_reg[i]=b;
7019 //branch_unneeded_reg_upper[i]=bu;
7020 // Branch delay slot
7021 tdep=(~uu>>rt1[i+1])&1;
7022 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7023 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
7024 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7025 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
7026 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
7028 gte_bu|=gte_rt[i+1];
7029 gte_bu&=~gte_rs[i+1];
7030 // If branch is "likely" then we skip the
7031 // delay slot on the fall-thru path
7037 u&=unneeded_reg[i+2];
7038 uu&=unneeded_reg_upper[i+2];
7039 gte_u&=gte_unneeded[i+2];
7051 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7052 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
7053 //branch_unneeded_reg[i]=1;
7054 //branch_unneeded_reg_upper[i]=1;
7056 branch_unneeded_reg[i]=1;
7057 branch_unneeded_reg_upper[i]=1;
7063 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7065 // SYSCALL instruction (software interrupt)
7069 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7071 // ERET instruction (return from interrupt)
7076 tdep=(~uu>>rt1[i])&1;
7077 // Written registers are unneeded
7083 // Accessed registers are needed
7089 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
7090 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7091 // Source-target dependencies
7092 uu&=~(tdep<<dep1[i]);
7093 uu&=~(tdep<<dep2[i]);
7094 // R0 is always unneeded
7098 unneeded_reg_upper[i]=uu;
7099 gte_unneeded[i]=gte_u;
7101 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7104 for(r=1;r<=CCREG;r++) {
7105 if((unneeded_reg[i]>>r)&1) {
7106 if(r==HIREG) printf(" HI");
7107 else if(r==LOREG) printf(" LO");
7108 else printf(" r%d",r);
7112 for(r=1;r<=CCREG;r++) {
7113 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7114 if(r==HIREG) printf(" HI");
7115 else if(r==LOREG) printf(" LO");
7116 else printf(" r%d",r);
7122 for (i=iend;i>=istart;i--)
7124 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7129 // Identify registers which are likely to contain 32-bit values
7130 // This is used to predict whether any branches will jump to a
7131 // location with 64-bit values in registers.
7132 static void provisional_32bit()
7136 uint64_t lastbranch=1;
7141 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7142 if(i>1) is32=lastbranch;
7148 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7150 if(i>2) is32=lastbranch;
7154 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7156 if(rs1[i-2]==0||rs2[i-2]==0)
7159 is32|=1LL<<rs1[i-2];
7162 is32|=1LL<<rs2[i-2];
7167 // If something jumps here with 64-bit values
7168 // then promote those registers to 64 bits
7171 uint64_t temp_is32=is32;
7174 if(ba[j]==start+i*4)
7175 //temp_is32&=branch_regs[j].is32;
7180 if(ba[j]==start+i*4)
7191 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7192 // Branches don't write registers, consider the delay slot instead.
7203 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7204 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7213 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7214 if(op==0x22) is32|=1LL<<rt; // LWL
7217 if (op==0x08||op==0x09|| // ADDI/ADDIU
7218 op==0x0a||op==0x0b|| // SLTI/SLTIU
7224 if(op==0x18||op==0x19) { // DADDI/DADDIU
7227 // is32|=((is32>>s1)&1LL)<<rt;
7229 if(op==0x0d||op==0x0e) { // ORI/XORI
7230 uint64_t sr=((is32>>s1)&1LL);
7246 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7249 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7252 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7253 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7257 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7262 uint64_t sr=((is32>>s1)&1LL);
7267 uint64_t sr=((is32>>s2)&1LL);
7275 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7280 uint64_t sr=((is32>>s1)&1LL);
7290 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7291 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7294 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7299 uint64_t sr=((is32>>s1)&1LL);
7305 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7306 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7310 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7311 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7314 if(op2==0) is32|=1LL<<rt; // MFC0
7318 if(op2==0) is32|=1LL<<rt; // MFC1
7319 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7320 if(op2==2) is32|=1LL<<rt; // CFC1
7342 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7344 if(rt1[i-1]==31) // JAL/JALR
7346 // Subroutine call will return here, don't alloc any registers
7351 // Internal branch will jump here, match registers to caller
7359 // Identify registers which may be assumed to contain 32-bit values
7360 // and where optimizations will rely on this.
7361 // This is used to determine whether backward branches can safely
7362 // jump to a location with 64-bit values in registers.
7363 static void provisional_r32()
7368 for (i=slen-1;i>=0;i--)
7371 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7373 if(ba[i]<start || ba[i]>=(start+slen*4))
7375 // Branch out of this block, don't need anything
7381 // Need whatever matches the target
7382 // (and doesn't get overwritten by the delay slot instruction)
7384 int t=(ba[i]-start)>>2;
7385 if(ba[i]>start+i*4) {
7387 //if(!(requires_32bit[t]&~regs[i].was32))
7388 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7389 if(!(pr32[t]&~regs[i].was32))
7390 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7393 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7394 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7397 // Conditional branch may need registers for following instructions
7398 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7401 //r32|=requires_32bit[i+2];
7404 // Mark this address as a branch target since it may be called
7405 // upon return from interrupt
7409 // Merge in delay slot
7411 // These are overwritten unless the branch is "likely"
7412 // and the delay slot is nullified if not taken
7413 r32&=~(1LL<<rt1[i+1]);
7414 r32&=~(1LL<<rt2[i+1]);
7416 // Assume these are needed (delay slot)
7419 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7423 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7425 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7427 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7429 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7431 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7434 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7436 // SYSCALL instruction (software interrupt)
7439 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7441 // ERET instruction (return from interrupt)
7445 r32&=~(1LL<<rt1[i]);
7446 r32&=~(1LL<<rt2[i]);
7449 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7453 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7455 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7457 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7459 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7461 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7463 //requires_32bit[i]=r32;
7466 // Dirty registers which are 32-bit, require 32-bit input
7467 // as they will be written as 32-bit values
7468 for(hr=0;hr<HOST_REGS;hr++)
7470 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7471 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7472 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7473 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7474 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7481 // Write back dirty registers as soon as we will no longer modify them,
7482 // so that we don't end up with lots of writes at the branches.
7483 void clean_registers(int istart,int iend,int wr)
7487 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7488 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7490 will_dirty_i=will_dirty_next=0;
7491 wont_dirty_i=wont_dirty_next=0;
7493 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7494 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7496 for (i=iend;i>=istart;i--)
7498 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7500 if(ba[i]<start || ba[i]>=(start+slen*4))
7502 // Branch out of this block, flush all regs
7503 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7505 // Unconditional branch
7508 // Merge in delay slot (will dirty)
7509 for(r=0;r<HOST_REGS;r++) {
7510 if(r!=EXCLUDE_REG) {
7511 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7512 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7513 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7514 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7515 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7516 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7517 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7518 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7519 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7520 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7521 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7522 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7523 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7524 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7530 // Conditional branch
7532 wont_dirty_i=wont_dirty_next;
7533 // Merge in delay slot (will dirty)
7534 for(r=0;r<HOST_REGS;r++) {
7535 if(r!=EXCLUDE_REG) {
7537 // Might not dirty if likely branch is not taken
7538 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7539 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7540 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7541 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7542 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7543 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7544 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7545 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7546 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7547 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7548 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7549 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7550 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7551 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7556 // Merge in delay slot (wont dirty)
7557 for(r=0;r<HOST_REGS;r++) {
7558 if(r!=EXCLUDE_REG) {
7559 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7560 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7561 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7562 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7563 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7564 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7565 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7566 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7567 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7568 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7572 #ifndef DESTRUCTIVE_WRITEBACK
7573 branch_regs[i].dirty&=wont_dirty_i;
7575 branch_regs[i].dirty|=will_dirty_i;
7581 if(ba[i]<=start+i*4) {
7583 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7585 // Unconditional branch
7588 // Merge in delay slot (will dirty)
7589 for(r=0;r<HOST_REGS;r++) {
7590 if(r!=EXCLUDE_REG) {
7591 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7592 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7593 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7594 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7595 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7596 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7597 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7598 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7599 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7600 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7601 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7602 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7603 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7604 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7608 // Conditional branch (not taken case)
7609 temp_will_dirty=will_dirty_next;
7610 temp_wont_dirty=wont_dirty_next;
7611 // Merge in delay slot (will dirty)
7612 for(r=0;r<HOST_REGS;r++) {
7613 if(r!=EXCLUDE_REG) {
7615 // Will not dirty if likely branch is not taken
7616 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7617 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7618 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7619 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7620 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7621 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7622 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7623 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7624 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7625 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7626 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7627 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7628 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7629 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7634 // Merge in delay slot (wont dirty)
7635 for(r=0;r<HOST_REGS;r++) {
7636 if(r!=EXCLUDE_REG) {
7637 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7638 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7639 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7640 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7641 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7642 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7643 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7644 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7645 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7646 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7649 // Deal with changed mappings
7651 for(r=0;r<HOST_REGS;r++) {
7652 if(r!=EXCLUDE_REG) {
7653 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7654 temp_will_dirty&=~(1<<r);
7655 temp_wont_dirty&=~(1<<r);
7656 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7657 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7658 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7660 temp_will_dirty|=1<<r;
7661 temp_wont_dirty|=1<<r;
7668 will_dirty[i]=temp_will_dirty;
7669 wont_dirty[i]=temp_wont_dirty;
7670 clean_registers((ba[i]-start)>>2,i-1,0);
7672 // Limit recursion. It can take an excessive amount
7673 // of time if there are a lot of nested loops.
7674 will_dirty[(ba[i]-start)>>2]=0;
7675 wont_dirty[(ba[i]-start)>>2]=-1;
7680 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7682 // Unconditional branch
7685 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7686 for(r=0;r<HOST_REGS;r++) {
7687 if(r!=EXCLUDE_REG) {
7688 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7689 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7690 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7692 if(branch_regs[i].regmap[r]>=0) {
7693 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7694 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7699 // Merge in delay slot
7700 for(r=0;r<HOST_REGS;r++) {
7701 if(r!=EXCLUDE_REG) {
7702 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7703 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7704 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7705 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7706 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7707 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7708 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7709 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7710 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7711 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7712 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7713 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7714 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7715 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7719 // Conditional branch
7720 will_dirty_i=will_dirty_next;
7721 wont_dirty_i=wont_dirty_next;
7722 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7723 for(r=0;r<HOST_REGS;r++) {
7724 if(r!=EXCLUDE_REG) {
7725 signed char target_reg=branch_regs[i].regmap[r];
7726 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7727 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7728 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7730 else if(target_reg>=0) {
7731 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7732 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7734 // Treat delay slot as part of branch too
7735 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7736 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7737 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7741 will_dirty[i+1]&=~(1<<r);
7746 // Merge in delay slot
7747 for(r=0;r<HOST_REGS;r++) {
7748 if(r!=EXCLUDE_REG) {
7750 // Might not dirty if likely branch is not taken
7751 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7752 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7753 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7754 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7755 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7756 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7757 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7758 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7759 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7760 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7761 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7762 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7763 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7764 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7769 // Merge in delay slot (won't dirty)
7770 for(r=0;r<HOST_REGS;r++) {
7771 if(r!=EXCLUDE_REG) {
7772 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7773 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7774 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7775 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7776 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7777 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7778 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7779 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7780 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7781 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7785 #ifndef DESTRUCTIVE_WRITEBACK
7786 branch_regs[i].dirty&=wont_dirty_i;
7788 branch_regs[i].dirty|=will_dirty_i;
7793 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7795 // SYSCALL instruction (software interrupt)
7799 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7801 // ERET instruction (return from interrupt)
7805 will_dirty_next=will_dirty_i;
7806 wont_dirty_next=wont_dirty_i;
7807 for(r=0;r<HOST_REGS;r++) {
7808 if(r!=EXCLUDE_REG) {
7809 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7810 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7811 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7812 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7813 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7814 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7815 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7816 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7818 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7820 // Don't store a register immediately after writing it,
7821 // may prevent dual-issue.
7822 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7823 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7829 will_dirty[i]=will_dirty_i;
7830 wont_dirty[i]=wont_dirty_i;
7831 // Mark registers that won't be dirtied as not dirty
7833 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7834 for(r=0;r<HOST_REGS;r++) {
7835 if((will_dirty_i>>r)&1) {
7841 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7842 regs[i].dirty|=will_dirty_i;
7843 #ifndef DESTRUCTIVE_WRITEBACK
7844 regs[i].dirty&=wont_dirty_i;
7845 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7847 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7848 for(r=0;r<HOST_REGS;r++) {
7849 if(r!=EXCLUDE_REG) {
7850 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7851 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7852 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7860 for(r=0;r<HOST_REGS;r++) {
7861 if(r!=EXCLUDE_REG) {
7862 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7863 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7864 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7872 // Deal with changed mappings
7873 temp_will_dirty=will_dirty_i;
7874 temp_wont_dirty=wont_dirty_i;
7875 for(r=0;r<HOST_REGS;r++) {
7876 if(r!=EXCLUDE_REG) {
7878 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7880 #ifndef DESTRUCTIVE_WRITEBACK
7881 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7883 regs[i].wasdirty|=will_dirty_i&(1<<r);
7886 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7887 // Register moved to a different register
7888 will_dirty_i&=~(1<<r);
7889 wont_dirty_i&=~(1<<r);
7890 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7891 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7893 #ifndef DESTRUCTIVE_WRITEBACK
7894 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7896 regs[i].wasdirty|=will_dirty_i&(1<<r);
7900 will_dirty_i&=~(1<<r);
7901 wont_dirty_i&=~(1<<r);
7902 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7903 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7904 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7907 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7917 void disassemble_inst(int i)
7919 if (bt[i]) printf("*"); else printf(" ");
7922 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7924 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7926 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7928 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7930 if (opcode[i]==0x9&&rt1[i]!=31)
7931 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7933 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7936 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7938 if(opcode[i]==0xf) //LUI
7939 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7941 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7945 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7949 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7953 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7956 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7959 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7962 if((opcode2[i]&0x1d)==0x10)
7963 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7964 else if((opcode2[i]&0x1d)==0x11)
7965 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7967 printf (" %x: %s\n",start+i*4,insn[i]);
7971 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7972 else if(opcode2[i]==4)
7973 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7974 else printf (" %x: %s\n",start+i*4,insn[i]);
7978 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7979 else if(opcode2[i]>3)
7980 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7981 else printf (" %x: %s\n",start+i*4,insn[i]);
7985 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7986 else if(opcode2[i]>3)
7987 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7988 else printf (" %x: %s\n",start+i*4,insn[i]);
7991 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7994 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7997 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
8000 //printf (" %s %8x\n",insn[i],source[i]);
8001 printf (" %x: %s\n",start+i*4,insn[i]);
8005 static void disassemble_inst(int i) {}
8008 // clear the state completely, instead of just marking
8009 // things invalid like invalidate_all_pages() does
8010 void new_dynarec_clear_full()
8013 out=(u_char *)BASE_ADDR;
8014 memset(invalid_code,1,sizeof(invalid_code));
8015 memset(hash_table,0xff,sizeof(hash_table));
8016 memset(mini_ht,-1,sizeof(mini_ht));
8017 memset(restore_candidate,0,sizeof(restore_candidate));
8018 memset(shadow,0,sizeof(shadow));
8020 expirep=16384; // Expiry pointer, +2 blocks
8021 pending_exception=0;
8024 inv_code_start=inv_code_end=~0;
8028 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
8030 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
8031 memory_map[n]=((u_int)rdram-0x80000000)>>2;
8032 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
8035 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8036 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8037 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8040 void new_dynarec_init()
8042 printf("Init new dynarec\n");
8043 out=(u_char *)BASE_ADDR;
8045 if (mmap (out, 1<<TARGET_SIZE_2,
8046 PROT_READ | PROT_WRITE | PROT_EXEC,
8047 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
8048 -1, 0) <= 0) {SysPrintf("mmap() failed\n");}
8050 // not all systems allow execute in data segment by default
8051 if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
8052 SysPrintf("mprotect() failed\n");
8055 rdword=&readmem_dword;
8056 fake_pc.f.r.rs=&readmem_dword;
8057 fake_pc.f.r.rt=&readmem_dword;
8058 fake_pc.f.r.rd=&readmem_dword;
8061 cycle_multiplier=200;
8062 new_dynarec_clear_full();
8064 // Copy this into local area so we don't have to put it in every literal pool
8065 invc_ptr=invalid_code;
8068 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8069 writemem[n] = write_nomem_new;
8070 writememb[n] = write_nomemb_new;
8071 writememh[n] = write_nomemh_new;
8073 writememd[n] = write_nomemd_new;
8075 readmem[n] = read_nomem_new;
8076 readmemb[n] = read_nomemb_new;
8077 readmemh[n] = read_nomemh_new;
8079 readmemd[n] = read_nomemd_new;
8082 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8083 writemem[n] = write_rdram_new;
8084 writememb[n] = write_rdramb_new;
8085 writememh[n] = write_rdramh_new;
8087 writememd[n] = write_rdramd_new;
8090 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8091 writemem[n] = write_nomem_new;
8092 writememb[n] = write_nomemb_new;
8093 writememh[n] = write_nomemh_new;
8095 writememd[n] = write_nomemd_new;
8097 readmem[n] = read_nomem_new;
8098 readmemb[n] = read_nomemb_new;
8099 readmemh[n] = read_nomemh_new;
8101 readmemd[n] = read_nomemd_new;
8108 ram_offset=(u_int)rdram-0x80000000;
8111 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
8114 void new_dynarec_cleanup()
8118 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {SysPrintf("munmap() failed\n");}
8120 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8121 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8122 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8124 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
8128 int new_recompile_block(int addr)
8131 if(addr==0x800cd050) {
8133 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8135 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8138 //if(Count==365117028) tracedebug=1;
8139 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8140 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8141 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8143 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8144 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8145 /*if(Count>=312978186) {
8149 start = (u_int)addr&~3;
8150 //assert(((u_int)addr&1)==0);
8151 new_dynarec_did_compile=1;
8153 if (Config.HLE && start == 0x80001000) // hlecall
8155 // XXX: is this enough? Maybe check hleSoftCall?
8156 u_int beginning=(u_int)out;
8157 u_int page=get_page(start);
8158 invalid_code[start>>12]=0;
8159 emit_movimm(start,0);
8160 emit_writeword(0,(int)&pcaddr);
8161 emit_jmp((int)new_dyna_leave);
8164 __clear_cache((void *)beginning,out);
8166 ll_add(jump_in+page,start,(void *)beginning);
8169 else if ((u_int)addr < 0x00200000 ||
8170 (0xa0000000 <= addr && addr < 0xa0200000)) {
8171 // used for BIOS calls mostly?
8172 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8173 pagelimit = (addr&0xa0000000)|0x00200000;
8175 else if (!Config.HLE && (
8176 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8177 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8179 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8180 pagelimit = (addr&0xfff00000)|0x80000;
8185 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8186 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8187 pagelimit = 0xa4001000;
8191 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8192 source = (u_int *)((u_int)rdram+start-0x80000000);
8193 pagelimit = 0x80000000+RAM_SIZE;
8196 else if ((signed int)addr >= (signed int)0xC0000000) {
8197 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8198 //if(tlb_LUT_r[start>>12])
8199 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8200 if((signed int)memory_map[start>>12]>=0) {
8201 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8202 pagelimit=(start+4096)&0xFFFFF000;
8203 int map=memory_map[start>>12];
8206 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8207 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8209 assem_debug("pagelimit=%x\n",pagelimit);
8210 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8213 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8214 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8215 return -1; // Caller will invoke exception handler
8217 //printf("source= %x\n",(int)source);
8221 SysPrintf("Compile at bogus memory address: %x \n", (int)addr);
8225 /* Pass 1: disassemble */
8226 /* Pass 2: register dependencies, branch targets */
8227 /* Pass 3: register allocation */
8228 /* Pass 4: branch dependencies */
8229 /* Pass 5: pre-alloc */
8230 /* Pass 6: optimize clean/dirty state */
8231 /* Pass 7: flag 32-bit registers */
8232 /* Pass 8: assembly */
8233 /* Pass 9: linker */
8234 /* Pass 10: garbage collection / free memory */
8238 unsigned int type,op,op2;
8240 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8242 /* Pass 1 disassembly */
8244 for(i=0;!done;i++) {
8245 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8246 minimum_free_regs[i]=0;
8247 opcode[i]=op=source[i]>>26;
8250 case 0x00: strcpy(insn[i],"special"); type=NI;
8254 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8255 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8256 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8257 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8258 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8259 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8260 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8261 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8262 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8263 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8264 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8265 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8266 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8267 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8268 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8269 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8270 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8271 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8272 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8273 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8274 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8275 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8276 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8277 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8278 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8279 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8280 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8281 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8282 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8283 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8284 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8285 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8286 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8287 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8288 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8290 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8291 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8292 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8293 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8294 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8295 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8296 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8297 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8298 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8299 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8300 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8301 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8302 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8303 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8304 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8305 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8306 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8310 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8311 op2=(source[i]>>16)&0x1f;
8314 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8315 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8316 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8317 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8318 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8319 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8320 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8321 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8322 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8323 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8324 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8325 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8326 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8327 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8330 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8331 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8332 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8333 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8334 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8335 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8336 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8337 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8338 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8339 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8340 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8341 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8342 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8343 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8344 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8345 op2=(source[i]>>21)&0x1f;
8348 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8349 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8350 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8351 switch(source[i]&0x3f)
8353 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8354 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8355 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8356 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8358 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8360 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8365 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8366 op2=(source[i]>>21)&0x1f;
8369 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8370 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8371 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8372 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8373 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8374 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8375 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8376 switch((source[i]>>16)&0x3)
8378 case 0x00: strcpy(insn[i],"BC1F"); break;
8379 case 0x01: strcpy(insn[i],"BC1T"); break;
8380 case 0x02: strcpy(insn[i],"BC1FL"); break;
8381 case 0x03: strcpy(insn[i],"BC1TL"); break;
8384 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8385 switch(source[i]&0x3f)
8387 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8388 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8389 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8390 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8391 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8392 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8393 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8394 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8395 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8396 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8397 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8398 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8399 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8400 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8401 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8402 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8403 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8404 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8405 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8406 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8407 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8408 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8409 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8410 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8411 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8412 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8413 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8414 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8415 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8416 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8417 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8418 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8419 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8420 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8421 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8424 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8425 switch(source[i]&0x3f)
8427 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8428 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8429 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8430 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8431 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8432 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8433 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8434 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8435 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8436 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8437 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8438 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8439 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8440 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8441 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8442 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8443 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8444 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8445 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8446 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8447 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8448 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8449 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8450 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8451 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8452 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8453 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8454 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8455 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8456 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8457 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8458 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8459 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8460 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8461 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8464 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8465 switch(source[i]&0x3f)
8467 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8468 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8471 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8472 switch(source[i]&0x3f)
8474 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8475 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8481 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8482 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8483 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8484 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8485 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8486 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8487 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8488 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8490 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8491 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8492 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8493 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8494 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8495 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8496 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8498 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8500 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8501 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8502 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8503 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8505 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8506 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8508 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8509 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8510 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8511 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8513 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8514 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8515 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8517 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8518 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8520 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8521 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8522 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8525 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8526 op2=(source[i]>>21)&0x1f;
8528 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8529 if (gte_handlers[source[i]&0x3f]!=NULL) {
8530 if (gte_regnames[source[i]&0x3f]!=NULL)
8531 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8533 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8539 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8540 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8541 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8542 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8545 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8546 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8547 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8549 default: strcpy(insn[i],"???"); type=NI;
8550 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8555 /* Get registers/immediates */
8561 gte_rs[i]=gte_rt[i]=0;
8564 rs1[i]=(source[i]>>21)&0x1f;
8566 rt1[i]=(source[i]>>16)&0x1f;
8568 imm[i]=(short)source[i];
8572 rs1[i]=(source[i]>>21)&0x1f;
8573 rs2[i]=(source[i]>>16)&0x1f;
8576 imm[i]=(short)source[i];
8577 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8580 // LWL/LWR only load part of the register,
8581 // therefore the target register must be treated as a source too
8582 rs1[i]=(source[i]>>21)&0x1f;
8583 rs2[i]=(source[i]>>16)&0x1f;
8584 rt1[i]=(source[i]>>16)&0x1f;
8586 imm[i]=(short)source[i];
8587 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8588 if(op==0x26) dep1[i]=rt1[i]; // LWR
8591 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8592 else rs1[i]=(source[i]>>21)&0x1f;
8594 rt1[i]=(source[i]>>16)&0x1f;
8596 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8597 imm[i]=(unsigned short)source[i];
8599 imm[i]=(short)source[i];
8601 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8602 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8603 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8610 // The JAL instruction writes to r31.
8617 rs1[i]=(source[i]>>21)&0x1f;
8621 // The JALR instruction writes to rd.
8623 rt1[i]=(source[i]>>11)&0x1f;
8628 rs1[i]=(source[i]>>21)&0x1f;
8629 rs2[i]=(source[i]>>16)&0x1f;
8632 if(op&2) { // BGTZ/BLEZ
8640 rs1[i]=(source[i]>>21)&0x1f;
8645 if(op2&0x10) { // BxxAL
8647 // NOTE: If the branch is not taken, r31 is still overwritten
8649 likely[i]=(op2&2)>>1;
8656 likely[i]=((source[i])>>17)&1;
8659 rs1[i]=(source[i]>>21)&0x1f; // source
8660 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8661 rt1[i]=(source[i]>>11)&0x1f; // destination
8663 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8664 us1[i]=rs1[i];us2[i]=rs2[i];
8666 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8667 dep1[i]=rs1[i];dep2[i]=rs2[i];
8669 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8670 dep1[i]=rs1[i];dep2[i]=rs2[i];
8674 rs1[i]=(source[i]>>21)&0x1f; // source
8675 rs2[i]=(source[i]>>16)&0x1f; // divisor
8678 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8679 us1[i]=rs1[i];us2[i]=rs2[i];
8687 if(op2==0x10) rs1[i]=HIREG; // MFHI
8688 if(op2==0x11) rt1[i]=HIREG; // MTHI
8689 if(op2==0x12) rs1[i]=LOREG; // MFLO
8690 if(op2==0x13) rt1[i]=LOREG; // MTLO
8691 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8692 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8696 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8697 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8698 rt1[i]=(source[i]>>11)&0x1f; // destination
8700 // DSLLV/DSRLV/DSRAV are 64-bit
8701 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8704 rs1[i]=(source[i]>>16)&0x1f;
8706 rt1[i]=(source[i]>>11)&0x1f;
8708 imm[i]=(source[i]>>6)&0x1f;
8709 // DSxx32 instructions
8710 if(op2>=0x3c) imm[i]|=0x20;
8711 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8712 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8719 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8720 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8721 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8722 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8729 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8730 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8731 if(op2==5) us1[i]=rs1[i]; // DMTC1
8739 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8740 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8742 int gr=(source[i]>>11)&0x1F;
8745 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8746 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8747 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8748 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8752 rs1[i]=(source[i]>>21)&0x1F;
8756 imm[i]=(short)source[i];
8759 rs1[i]=(source[i]>>21)&0x1F;
8763 imm[i]=(short)source[i];
8764 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8765 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8772 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8773 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8774 gte_rt[i]|=1ll<<63; // every op changes flags
8775 if((source[i]&0x3f)==GTE_MVMVA) {
8776 int v = (source[i] >> 15) & 3;
8777 gte_rs[i]&=~0xe3fll;
8778 if(v==3) gte_rs[i]|=0xe00ll;
8779 else gte_rs[i]|=3ll<<(v*2);
8809 /* Calculate branch target addresses */
8811 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8812 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8813 ba[i]=start+i*4+8; // Ignore never taken branch
8814 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8815 ba[i]=start+i*4+8; // Ignore never taken branch
8816 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8817 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8820 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8822 // branch in delay slot?
8823 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8824 // don't handle first branch and call interpreter if it's hit
8825 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8828 // basic load delay detection
8829 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8830 int t=(ba[i-1]-start)/4;
8831 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8832 // jump target wants DS result - potential load delay effect
8833 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
8835 bt[t+1]=1; // expected return from interpreter
8837 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8838 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8839 // v0 overwrite like this is a sign of trouble, bail out
8840 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8846 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8850 i--; // don't compile the DS
8854 /* Is this the end of the block? */
8855 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8856 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8860 if(stop_after_jal) done=1;
8862 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8864 // Don't recompile stuff that's already compiled
8865 if(check_addr(start+i*4+4)) done=1;
8866 // Don't get too close to the limit
8867 if(i>MAXBLOCK/2) done=1;
8869 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8870 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8872 // Does the block continue due to a branch?
8875 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8876 if(ba[j]==start+i*4+4) done=j=0;
8877 if(ba[j]==start+i*4+8) done=j=0;
8880 //assert(i<MAXBLOCK-1);
8881 if(start+i*4==pagelimit-4) done=1;
8882 assert(start+i*4<pagelimit);
8883 if (i==MAXBLOCK-1) done=1;
8884 // Stop if we're compiling junk
8885 if(itype[i]==NI&&opcode[i]==0x11) {
8886 done=stop_after_jal=1;
8887 SysPrintf("Disabled speculative precompilation\n");
8891 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8892 if(start+i*4==pagelimit) {
8898 /* Pass 2 - Register dependencies and branch targets */
8900 unneeded_registers(0,slen-1,0);
8902 /* Pass 3 - Register allocation */
8904 struct regstat current; // Current register allocations/status
8907 current.u=unneeded_reg[0];
8908 current.uu=unneeded_reg_upper[0];
8909 clear_all_regs(current.regmap);
8910 alloc_reg(¤t,0,CCREG);
8911 dirty_reg(¤t,CCREG);
8914 current.waswritten=0;
8920 provisional_32bit();
8923 // First instruction is delay slot
8928 unneeded_reg_upper[0]=1;
8929 current.regmap[HOST_BTREG]=BTREG;
8937 for(hr=0;hr<HOST_REGS;hr++)
8939 // Is this really necessary?
8940 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8943 current.waswritten=0;
8947 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8949 if(rs1[i-2]==0||rs2[i-2]==0)
8952 current.is32|=1LL<<rs1[i-2];
8953 int hr=get_reg(current.regmap,rs1[i-2]|64);
8954 if(hr>=0) current.regmap[hr]=-1;
8957 current.is32|=1LL<<rs2[i-2];
8958 int hr=get_reg(current.regmap,rs2[i-2]|64);
8959 if(hr>=0) current.regmap[hr]=-1;
8965 // If something jumps here with 64-bit values
8966 // then promote those registers to 64 bits
8969 uint64_t temp_is32=current.is32;
8972 if(ba[j]==start+i*4)
8973 temp_is32&=branch_regs[j].is32;
8977 if(ba[j]==start+i*4)
8981 if(temp_is32!=current.is32) {
8982 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8983 #ifndef DESTRUCTIVE_WRITEBACK
8986 for(hr=0;hr<HOST_REGS;hr++)
8988 int r=current.regmap[hr];
8991 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8993 //printf("restore %d\n",r);
8997 current.is32=temp_is32;
9004 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
9005 regs[i].wasconst=current.isconst;
9006 regs[i].was32=current.is32;
9007 regs[i].wasdirty=current.dirty;
9008 regs[i].loadedconst=0;
9009 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
9010 // To change a dirty register from 32 to 64 bits, we must write
9011 // it out during the previous cycle (for branches, 2 cycles)
9012 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
9014 uint64_t temp_is32=current.is32;
9017 if(ba[j]==start+i*4+4)
9018 temp_is32&=branch_regs[j].is32;
9022 if(ba[j]==start+i*4+4)
9026 if(temp_is32!=current.is32) {
9027 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9028 for(hr=0;hr<HOST_REGS;hr++)
9030 int r=current.regmap[hr];
9033 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9034 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
9036 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
9038 //printf("dump %d/r%d\n",hr,r);
9039 current.regmap[hr]=-1;
9040 if(get_reg(current.regmap,r|64)>=0)
9041 current.regmap[get_reg(current.regmap,r|64)]=-1;
9049 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
9051 uint64_t temp_is32=current.is32;
9054 if(ba[j]==start+i*4+8)
9055 temp_is32&=branch_regs[j].is32;
9059 if(ba[j]==start+i*4+8)
9063 if(temp_is32!=current.is32) {
9064 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9065 for(hr=0;hr<HOST_REGS;hr++)
9067 int r=current.regmap[hr];
9070 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9071 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
9073 //printf("dump %d/r%d\n",hr,r);
9074 current.regmap[hr]=-1;
9075 if(get_reg(current.regmap,r|64)>=0)
9076 current.regmap[get_reg(current.regmap,r|64)]=-1;
9084 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9086 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9087 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9088 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9097 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9098 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9099 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9100 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9101 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9104 } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
9108 ds=0; // Skip delay slot, already allocated as part of branch
9109 // ...but we need to alloc it in case something jumps here
9111 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9112 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9114 current.u=branch_unneeded_reg[i-1];
9115 current.uu=branch_unneeded_reg_upper[i-1];
9117 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9118 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9119 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9122 struct regstat temp;
9123 memcpy(&temp,¤t,sizeof(current));
9124 temp.wasdirty=temp.dirty;
9125 temp.was32=temp.is32;
9126 // TODO: Take into account unconditional branches, as below
9127 delayslot_alloc(&temp,i);
9128 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9129 regs[i].wasdirty=temp.wasdirty;
9130 regs[i].was32=temp.was32;
9131 regs[i].dirty=temp.dirty;
9132 regs[i].is32=temp.is32;
9136 // Create entry (branch target) regmap
9137 for(hr=0;hr<HOST_REGS;hr++)
9139 int r=temp.regmap[hr];
9141 if(r!=regmap_pre[i][hr]) {
9142 regs[i].regmap_entry[hr]=-1;
9147 if((current.u>>r)&1) {
9148 regs[i].regmap_entry[hr]=-1;
9149 regs[i].regmap[hr]=-1;
9150 //Don't clear regs in the delay slot as the branch might need them
9151 //current.regmap[hr]=-1;
9153 regs[i].regmap_entry[hr]=r;
9156 if((current.uu>>(r&63))&1) {
9157 regs[i].regmap_entry[hr]=-1;
9158 regs[i].regmap[hr]=-1;
9159 //Don't clear regs in the delay slot as the branch might need them
9160 //current.regmap[hr]=-1;
9162 regs[i].regmap_entry[hr]=r;
9166 // First instruction expects CCREG to be allocated
9167 if(i==0&&hr==HOST_CCREG)
9168 regs[i].regmap_entry[hr]=CCREG;
9170 regs[i].regmap_entry[hr]=-1;
9174 else { // Not delay slot
9177 //current.isconst=0; // DEBUG
9178 //current.wasconst=0; // DEBUG
9179 //regs[i].wasconst=0; // DEBUG
9180 clear_const(¤t,rt1[i]);
9181 alloc_cc(¤t,i);
9182 dirty_reg(¤t,CCREG);
9184 alloc_reg(¤t,i,31);
9185 dirty_reg(¤t,31);
9186 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9187 //assert(rt1[i+1]!=rt1[i]);
9189 alloc_reg(¤t,i,PTEMP);
9191 //current.is32|=1LL<<rt1[i];
9194 delayslot_alloc(¤t,i+1);
9195 //current.isconst=0; // DEBUG
9197 //printf("i=%d, isconst=%x\n",i,current.isconst);
9200 //current.isconst=0;
9201 //current.wasconst=0;
9202 //regs[i].wasconst=0;
9203 clear_const(¤t,rs1[i]);
9204 clear_const(¤t,rt1[i]);
9205 alloc_cc(¤t,i);
9206 dirty_reg(¤t,CCREG);
9207 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9208 alloc_reg(¤t,i,rs1[i]);
9210 alloc_reg(¤t,i,rt1[i]);
9211 dirty_reg(¤t,rt1[i]);
9212 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9213 assert(rt1[i+1]!=rt1[i]);
9215 alloc_reg(¤t,i,PTEMP);
9219 if(rs1[i]==31) { // JALR
9220 alloc_reg(¤t,i,RHASH);
9221 #ifndef HOST_IMM_ADDR32
9222 alloc_reg(¤t,i,RHTBL);
9226 delayslot_alloc(¤t,i+1);
9228 // The delay slot overwrites our source register,
9229 // allocate a temporary register to hold the old value.
9233 delayslot_alloc(¤t,i+1);
9235 alloc_reg(¤t,i,RTEMP);
9237 //current.isconst=0; // DEBUG
9242 //current.isconst=0;
9243 //current.wasconst=0;
9244 //regs[i].wasconst=0;
9245 clear_const(¤t,rs1[i]);
9246 clear_const(¤t,rs2[i]);
9247 if((opcode[i]&0x3E)==4) // BEQ/BNE
9249 alloc_cc(¤t,i);
9250 dirty_reg(¤t,CCREG);
9251 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9252 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9253 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9255 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9256 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9258 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9259 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9260 // The delay slot overwrites one of our conditions.
9261 // Allocate the branch condition registers instead.
9265 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9266 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9267 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9269 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9270 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9276 delayslot_alloc(¤t,i+1);
9280 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9282 alloc_cc(¤t,i);
9283 dirty_reg(¤t,CCREG);
9284 alloc_reg(¤t,i,rs1[i]);
9285 if(!(current.is32>>rs1[i]&1))
9287 alloc_reg64(¤t,i,rs1[i]);
9289 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9290 // The delay slot overwrites one of our conditions.
9291 // Allocate the branch condition registers instead.
9295 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9296 if(!((current.is32>>rs1[i])&1))
9298 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9304 delayslot_alloc(¤t,i+1);
9308 // Don't alloc the delay slot yet because we might not execute it
9309 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9314 alloc_cc(¤t,i);
9315 dirty_reg(¤t,CCREG);
9316 alloc_reg(¤t,i,rs1[i]);
9317 alloc_reg(¤t,i,rs2[i]);
9318 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9320 alloc_reg64(¤t,i,rs1[i]);
9321 alloc_reg64(¤t,i,rs2[i]);
9325 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9330 alloc_cc(¤t,i);
9331 dirty_reg(¤t,CCREG);
9332 alloc_reg(¤t,i,rs1[i]);
9333 if(!(current.is32>>rs1[i]&1))
9335 alloc_reg64(¤t,i,rs1[i]);
9339 //current.isconst=0;
9342 //current.isconst=0;
9343 //current.wasconst=0;
9344 //regs[i].wasconst=0;
9345 clear_const(¤t,rs1[i]);
9346 clear_const(¤t,rt1[i]);
9347 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9348 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9350 alloc_cc(¤t,i);
9351 dirty_reg(¤t,CCREG);
9352 alloc_reg(¤t,i,rs1[i]);
9353 if(!(current.is32>>rs1[i]&1))
9355 alloc_reg64(¤t,i,rs1[i]);
9357 if (rt1[i]==31) { // BLTZAL/BGEZAL
9358 alloc_reg(¤t,i,31);
9359 dirty_reg(¤t,31);
9360 //#ifdef REG_PREFETCH
9361 //alloc_reg(¤t,i,PTEMP);
9363 //current.is32|=1LL<<rt1[i];
9365 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9366 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9367 // Allocate the branch condition registers instead.
9371 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9372 if(!((current.is32>>rs1[i])&1))
9374 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9380 delayslot_alloc(¤t,i+1);
9384 // Don't alloc the delay slot yet because we might not execute it
9385 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9390 alloc_cc(¤t,i);
9391 dirty_reg(¤t,CCREG);
9392 alloc_reg(¤t,i,rs1[i]);
9393 if(!(current.is32>>rs1[i]&1))
9395 alloc_reg64(¤t,i,rs1[i]);
9399 //current.isconst=0;
9405 if(likely[i]==0) // BC1F/BC1T
9407 // TODO: Theoretically we can run out of registers here on x86.
9408 // The delay slot can allocate up to six, and we need to check
9409 // CSREG before executing the delay slot. Possibly we can drop
9410 // the cycle count and then reload it after checking that the
9411 // FPU is in a usable state, or don't do out-of-order execution.
9412 alloc_cc(¤t,i);
9413 dirty_reg(¤t,CCREG);
9414 alloc_reg(¤t,i,FSREG);
9415 alloc_reg(¤t,i,CSREG);
9416 if(itype[i+1]==FCOMP) {
9417 // The delay slot overwrites the branch condition.
9418 // Allocate the branch condition registers instead.
9419 alloc_cc(¤t,i);
9420 dirty_reg(¤t,CCREG);
9421 alloc_reg(¤t,i,CSREG);
9422 alloc_reg(¤t,i,FSREG);
9426 delayslot_alloc(¤t,i+1);
9427 alloc_reg(¤t,i+1,CSREG);
9431 // Don't alloc the delay slot yet because we might not execute it
9432 if(likely[i]) // BC1FL/BC1TL
9434 alloc_cc(¤t,i);
9435 dirty_reg(¤t,CCREG);
9436 alloc_reg(¤t,i,CSREG);
9437 alloc_reg(¤t,i,FSREG);
9443 imm16_alloc(¤t,i);
9447 load_alloc(¤t,i);
9451 store_alloc(¤t,i);
9454 alu_alloc(¤t,i);
9457 shift_alloc(¤t,i);
9460 multdiv_alloc(¤t,i);
9463 shiftimm_alloc(¤t,i);
9466 mov_alloc(¤t,i);
9469 cop0_alloc(¤t,i);
9473 cop1_alloc(¤t,i);
9476 c1ls_alloc(¤t,i);
9479 c2ls_alloc(¤t,i);
9482 c2op_alloc(¤t,i);
9485 fconv_alloc(¤t,i);
9488 float_alloc(¤t,i);
9491 fcomp_alloc(¤t,i);
9496 syscall_alloc(¤t,i);
9499 pagespan_alloc(¤t,i);
9503 // Drop the upper half of registers that have become 32-bit
9504 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9505 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9506 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9507 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9510 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9511 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9512 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9513 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9517 // Create entry (branch target) regmap
9518 for(hr=0;hr<HOST_REGS;hr++)
9521 r=current.regmap[hr];
9523 if(r!=regmap_pre[i][hr]) {
9524 // TODO: delay slot (?)
9525 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9526 if(or<0||(r&63)>=TEMPREG){
9527 regs[i].regmap_entry[hr]=-1;
9531 // Just move it to a different register
9532 regs[i].regmap_entry[hr]=r;
9533 // If it was dirty before, it's still dirty
9534 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9541 regs[i].regmap_entry[hr]=0;
9545 if((current.u>>r)&1) {
9546 regs[i].regmap_entry[hr]=-1;
9547 //regs[i].regmap[hr]=-1;
9548 current.regmap[hr]=-1;
9550 regs[i].regmap_entry[hr]=r;
9553 if((current.uu>>(r&63))&1) {
9554 regs[i].regmap_entry[hr]=-1;
9555 //regs[i].regmap[hr]=-1;
9556 current.regmap[hr]=-1;
9558 regs[i].regmap_entry[hr]=r;
9562 // Branches expect CCREG to be allocated at the target
9563 if(regmap_pre[i][hr]==CCREG)
9564 regs[i].regmap_entry[hr]=CCREG;
9566 regs[i].regmap_entry[hr]=-1;
9569 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9572 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9573 current.waswritten|=1<<rs1[i-1];
9574 current.waswritten&=~(1<<rt1[i]);
9575 current.waswritten&=~(1<<rt2[i]);
9576 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9577 current.waswritten&=~(1<<rs1[i]);
9579 /* Branch post-alloc */
9582 current.was32=current.is32;
9583 current.wasdirty=current.dirty;
9584 switch(itype[i-1]) {
9586 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9587 branch_regs[i-1].isconst=0;
9588 branch_regs[i-1].wasconst=0;
9589 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9590 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9591 alloc_cc(&branch_regs[i-1],i-1);
9592 dirty_reg(&branch_regs[i-1],CCREG);
9593 if(rt1[i-1]==31) { // JAL
9594 alloc_reg(&branch_regs[i-1],i-1,31);
9595 dirty_reg(&branch_regs[i-1],31);
9596 branch_regs[i-1].is32|=1LL<<31;
9598 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9599 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9602 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9603 branch_regs[i-1].isconst=0;
9604 branch_regs[i-1].wasconst=0;
9605 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9606 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9607 alloc_cc(&branch_regs[i-1],i-1);
9608 dirty_reg(&branch_regs[i-1],CCREG);
9609 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9610 if(rt1[i-1]!=0) { // JALR
9611 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9612 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9613 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9616 if(rs1[i-1]==31) { // JALR
9617 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9618 #ifndef HOST_IMM_ADDR32
9619 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9623 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9624 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9627 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9629 alloc_cc(¤t,i-1);
9630 dirty_reg(¤t,CCREG);
9631 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9632 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9633 // The delay slot overwrote one of our conditions
9634 // Delay slot goes after the test (in order)
9635 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9636 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9637 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9640 delayslot_alloc(¤t,i);
9645 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9646 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9647 // Alloc the branch condition registers
9648 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9649 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9650 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9652 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9653 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9656 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9657 branch_regs[i-1].isconst=0;
9658 branch_regs[i-1].wasconst=0;
9659 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9660 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9663 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9665 alloc_cc(¤t,i-1);
9666 dirty_reg(¤t,CCREG);
9667 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9668 // The delay slot overwrote the branch condition
9669 // Delay slot goes after the test (in order)
9670 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9671 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9672 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9675 delayslot_alloc(¤t,i);
9680 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9681 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9682 // Alloc the branch condition register
9683 alloc_reg(¤t,i-1,rs1[i-1]);
9684 if(!(current.is32>>rs1[i-1]&1))
9686 alloc_reg64(¤t,i-1,rs1[i-1]);
9689 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9690 branch_regs[i-1].isconst=0;
9691 branch_regs[i-1].wasconst=0;
9692 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9693 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9696 // Alloc the delay slot in case the branch is taken
9697 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9699 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9700 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9701 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9702 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9703 alloc_cc(&branch_regs[i-1],i);
9704 dirty_reg(&branch_regs[i-1],CCREG);
9705 delayslot_alloc(&branch_regs[i-1],i);
9706 branch_regs[i-1].isconst=0;
9707 alloc_reg(¤t,i,CCREG); // Not taken path
9708 dirty_reg(¤t,CCREG);
9709 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9712 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9714 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9715 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9716 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9717 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9718 alloc_cc(&branch_regs[i-1],i);
9719 dirty_reg(&branch_regs[i-1],CCREG);
9720 delayslot_alloc(&branch_regs[i-1],i);
9721 branch_regs[i-1].isconst=0;
9722 alloc_reg(¤t,i,CCREG); // Not taken path
9723 dirty_reg(¤t,CCREG);
9724 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9728 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9729 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9731 alloc_cc(¤t,i-1);
9732 dirty_reg(¤t,CCREG);
9733 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9734 // The delay slot overwrote the branch condition
9735 // Delay slot goes after the test (in order)
9736 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9737 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9738 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9741 delayslot_alloc(¤t,i);
9746 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9747 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9748 // Alloc the branch condition register
9749 alloc_reg(¤t,i-1,rs1[i-1]);
9750 if(!(current.is32>>rs1[i-1]&1))
9752 alloc_reg64(¤t,i-1,rs1[i-1]);
9755 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9756 branch_regs[i-1].isconst=0;
9757 branch_regs[i-1].wasconst=0;
9758 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9759 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9762 // Alloc the delay slot in case the branch is taken
9763 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9765 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9766 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9767 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9768 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9769 alloc_cc(&branch_regs[i-1],i);
9770 dirty_reg(&branch_regs[i-1],CCREG);
9771 delayslot_alloc(&branch_regs[i-1],i);
9772 branch_regs[i-1].isconst=0;
9773 alloc_reg(¤t,i,CCREG); // Not taken path
9774 dirty_reg(¤t,CCREG);
9775 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9777 // FIXME: BLTZAL/BGEZAL
9778 if(opcode2[i-1]&0x10) { // BxxZAL
9779 alloc_reg(&branch_regs[i-1],i-1,31);
9780 dirty_reg(&branch_regs[i-1],31);
9781 branch_regs[i-1].is32|=1LL<<31;
9785 if(likely[i-1]==0) // BC1F/BC1T
9787 alloc_cc(¤t,i-1);
9788 dirty_reg(¤t,CCREG);
9789 if(itype[i]==FCOMP) {
9790 // The delay slot overwrote the branch condition
9791 // Delay slot goes after the test (in order)
9792 delayslot_alloc(¤t,i);
9797 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9798 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9799 // Alloc the branch condition register
9800 alloc_reg(¤t,i-1,FSREG);
9802 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9803 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9807 // Alloc the delay slot in case the branch is taken
9808 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9809 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9810 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9811 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9812 alloc_cc(&branch_regs[i-1],i);
9813 dirty_reg(&branch_regs[i-1],CCREG);
9814 delayslot_alloc(&branch_regs[i-1],i);
9815 branch_regs[i-1].isconst=0;
9816 alloc_reg(¤t,i,CCREG); // Not taken path
9817 dirty_reg(¤t,CCREG);
9818 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9823 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9825 if(rt1[i-1]==31) // JAL/JALR
9827 // Subroutine call will return here, don't alloc any registers
9830 clear_all_regs(current.regmap);
9831 alloc_reg(¤t,i,CCREG);
9832 dirty_reg(¤t,CCREG);
9836 // Internal branch will jump here, match registers to caller
9837 current.is32=0x3FFFFFFFFLL;
9839 clear_all_regs(current.regmap);
9840 alloc_reg(¤t,i,CCREG);
9841 dirty_reg(¤t,CCREG);
9844 if(ba[j]==start+i*4+4) {
9845 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9846 current.is32=branch_regs[j].is32;
9847 current.dirty=branch_regs[j].dirty;
9852 if(ba[j]==start+i*4+4) {
9853 for(hr=0;hr<HOST_REGS;hr++) {
9854 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9855 current.regmap[hr]=-1;
9857 current.is32&=branch_regs[j].is32;
9858 current.dirty&=branch_regs[j].dirty;
9867 // Count cycles in between branches
9869 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9873 #if defined(PCSX) && !defined(DRC_DBG)
9874 else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
9876 // GTE runs in parallel until accessed, divide by 2 for a rough guess
9877 cc+=gte_cycletab[source[i]&0x3f]/2;
9879 else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
9881 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9883 else if(itype[i]==C2LS)
9893 flush_dirty_uppers(¤t);
9895 regs[i].is32=current.is32;
9896 regs[i].dirty=current.dirty;
9897 regs[i].isconst=current.isconst;
9898 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
9900 for(hr=0;hr<HOST_REGS;hr++) {
9901 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9902 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9903 regs[i].wasconst&=~(1<<hr);
9907 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9908 regs[i].waswritten=current.waswritten;
9911 /* Pass 4 - Cull unused host registers */
9915 for (i=slen-1;i>=0;i--)
9918 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9920 if(ba[i]<start || ba[i]>=(start+slen*4))
9922 // Branch out of this block, don't need anything
9928 // Need whatever matches the target
9930 int t=(ba[i]-start)>>2;
9931 for(hr=0;hr<HOST_REGS;hr++)
9933 if(regs[i].regmap_entry[hr]>=0) {
9934 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9938 // Conditional branch may need registers for following instructions
9939 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9942 nr|=needed_reg[i+2];
9943 for(hr=0;hr<HOST_REGS;hr++)
9945 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9946 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9950 // Don't need stuff which is overwritten
9951 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9952 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9953 // Merge in delay slot
9954 for(hr=0;hr<HOST_REGS;hr++)
9957 // These are overwritten unless the branch is "likely"
9958 // and the delay slot is nullified if not taken
9959 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9960 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9962 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9963 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9964 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9965 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9966 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9967 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9968 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9969 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9970 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9971 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9972 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9974 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9975 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9976 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9978 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9979 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9980 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9984 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9986 // SYSCALL instruction (software interrupt)
9989 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9991 // ERET instruction (return from interrupt)
9997 for(hr=0;hr<HOST_REGS;hr++) {
9998 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9999 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
10000 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
10001 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
10005 for(hr=0;hr<HOST_REGS;hr++)
10007 // Overwritten registers are not needed
10008 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10009 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10010 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
10011 // Source registers are needed
10012 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10013 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10014 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
10015 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
10016 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10017 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10018 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10019 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
10020 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
10021 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10022 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10024 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
10025 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10026 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10028 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
10029 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
10030 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
10032 // Don't store a register immediately after writing it,
10033 // may prevent dual-issue.
10034 // But do so if this is a branch target, otherwise we
10035 // might have to load the register before the branch.
10036 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
10037 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
10038 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
10039 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10040 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
10042 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
10043 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
10044 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10045 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
10049 // Cycle count is needed at branches. Assume it is needed at the target too.
10050 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
10051 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10052 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10057 // Deallocate unneeded registers
10058 for(hr=0;hr<HOST_REGS;hr++)
10060 if(!((nr>>hr)&1)) {
10061 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
10062 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10063 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10064 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
10066 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10069 regs[i].regmap[hr]=-1;
10070 regs[i].isconst&=~(1<<hr);
10072 regmap_pre[i+2][hr]=-1;
10073 regs[i+2].wasconst&=~(1<<hr);
10078 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10080 int d1=0,d2=0,map=0,temp=0;
10081 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10087 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10088 itype[i+1]==STORE || itype[i+1]==STORELR ||
10089 itype[i+1]==C1LS || itype[i+1]==C2LS)
10092 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10093 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10096 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10097 itype[i+1]==C1LS || itype[i+1]==C2LS)
10099 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10100 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10101 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10102 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10103 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10104 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10105 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10106 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10107 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10108 regs[i].regmap[hr]!=map )
10110 regs[i].regmap[hr]=-1;
10111 regs[i].isconst&=~(1<<hr);
10112 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10113 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10114 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10115 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10116 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10117 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10118 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10119 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10120 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10121 branch_regs[i].regmap[hr]!=map)
10123 branch_regs[i].regmap[hr]=-1;
10124 branch_regs[i].regmap_entry[hr]=-1;
10125 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10127 if(!likely[i]&&i<slen-2) {
10128 regmap_pre[i+2][hr]=-1;
10129 regs[i+2].wasconst&=~(1<<hr);
10140 int d1=0,d2=0,map=-1,temp=-1;
10141 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10147 if(itype[i]==LOAD || itype[i]==LOADLR ||
10148 itype[i]==STORE || itype[i]==STORELR ||
10149 itype[i]==C1LS || itype[i]==C2LS)
10151 } else if(itype[i]==STORE || itype[i]==STORELR ||
10152 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10155 if(itype[i]==LOADLR || itype[i]==STORELR ||
10156 itype[i]==C1LS || itype[i]==C2LS)
10158 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10159 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10160 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10161 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10162 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10163 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10165 if(i<slen-1&&!is_ds[i]) {
10166 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10167 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10168 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10170 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10171 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10173 regmap_pre[i+1][hr]=-1;
10174 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10175 regs[i+1].wasconst&=~(1<<hr);
10177 regs[i].regmap[hr]=-1;
10178 regs[i].isconst&=~(1<<hr);
10186 /* Pass 5 - Pre-allocate registers */
10188 // If a register is allocated during a loop, try to allocate it for the
10189 // entire loop, if possible. This avoids loading/storing registers
10190 // inside of the loop.
10192 signed char f_regmap[HOST_REGS];
10193 clear_all_regs(f_regmap);
10194 for(i=0;i<slen-1;i++)
10196 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10198 if(ba[i]>=start && ba[i]<(start+i*4))
10199 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10200 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10201 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10202 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10203 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10204 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10206 int t=(ba[i]-start)>>2;
10207 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10208 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10209 for(hr=0;hr<HOST_REGS;hr++)
10211 if(regs[i].regmap[hr]>64) {
10212 if(!((regs[i].dirty>>hr)&1))
10213 f_regmap[hr]=regs[i].regmap[hr];
10214 else f_regmap[hr]=-1;
10216 else if(regs[i].regmap[hr]>=0) {
10217 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10218 // dealloc old register
10220 for(n=0;n<HOST_REGS;n++)
10222 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10224 // and alloc new one
10225 f_regmap[hr]=regs[i].regmap[hr];
10228 if(branch_regs[i].regmap[hr]>64) {
10229 if(!((branch_regs[i].dirty>>hr)&1))
10230 f_regmap[hr]=branch_regs[i].regmap[hr];
10231 else f_regmap[hr]=-1;
10233 else if(branch_regs[i].regmap[hr]>=0) {
10234 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10235 // dealloc old register
10237 for(n=0;n<HOST_REGS;n++)
10239 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10241 // and alloc new one
10242 f_regmap[hr]=branch_regs[i].regmap[hr];
10246 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10247 f_regmap[hr]=branch_regs[i].regmap[hr];
10249 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10250 f_regmap[hr]=branch_regs[i].regmap[hr];
10252 // Avoid dirty->clean transition
10253 #ifdef DESTRUCTIVE_WRITEBACK
10254 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10256 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10257 // case above, however it's always a good idea. We can't hoist the
10258 // load if the register was already allocated, so there's no point
10259 // wasting time analyzing most of these cases. It only "succeeds"
10260 // when the mapping was different and the load can be replaced with
10261 // a mov, which is of negligible benefit. So such cases are
10263 if(f_regmap[hr]>0) {
10264 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10265 int r=f_regmap[hr];
10268 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10269 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10270 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10272 // NB This can exclude the case where the upper-half
10273 // register is lower numbered than the lower-half
10274 // register. Not sure if it's worth fixing...
10275 if(get_reg(regs[j].regmap,r&63)<0) break;
10276 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10277 if(regs[j].is32&(1LL<<(r&63))) break;
10279 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10280 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10282 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10283 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10285 if(get_reg(regs[i].regmap,r&63)<0) break;
10286 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10289 while(k>1&®s[k-1].regmap[hr]==-1) {
10290 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10291 //printf("no free regs for store %x\n",start+(k-1)*4);
10294 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10295 //printf("no-match due to different register\n");
10298 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10299 //printf("no-match due to branch\n");
10302 // call/ret fast path assumes no registers allocated
10303 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10307 // NB This can exclude the case where the upper-half
10308 // register is lower numbered than the lower-half
10309 // register. Not sure if it's worth fixing...
10310 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10311 if(regs[k-1].is32&(1LL<<(r&63))) break;
10316 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10317 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10318 //printf("bad match after branch\n");
10322 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10323 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10325 regs[k].regmap_entry[hr]=f_regmap[hr];
10326 regs[k].regmap[hr]=f_regmap[hr];
10327 regmap_pre[k+1][hr]=f_regmap[hr];
10328 regs[k].wasdirty&=~(1<<hr);
10329 regs[k].dirty&=~(1<<hr);
10330 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10331 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10332 regs[k].wasconst&=~(1<<hr);
10333 regs[k].isconst&=~(1<<hr);
10338 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10341 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10342 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10343 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10344 regs[i].regmap_entry[hr]=f_regmap[hr];
10345 regs[i].regmap[hr]=f_regmap[hr];
10346 regs[i].wasdirty&=~(1<<hr);
10347 regs[i].dirty&=~(1<<hr);
10348 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10349 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10350 regs[i].wasconst&=~(1<<hr);
10351 regs[i].isconst&=~(1<<hr);
10352 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10353 branch_regs[i].wasdirty&=~(1<<hr);
10354 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10355 branch_regs[i].regmap[hr]=f_regmap[hr];
10356 branch_regs[i].dirty&=~(1<<hr);
10357 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10358 branch_regs[i].wasconst&=~(1<<hr);
10359 branch_regs[i].isconst&=~(1<<hr);
10360 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10361 regmap_pre[i+2][hr]=f_regmap[hr];
10362 regs[i+2].wasdirty&=~(1<<hr);
10363 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10364 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10365 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10370 // Alloc register clean at beginning of loop,
10371 // but may dirty it in pass 6
10372 regs[k].regmap_entry[hr]=f_regmap[hr];
10373 regs[k].regmap[hr]=f_regmap[hr];
10374 regs[k].dirty&=~(1<<hr);
10375 regs[k].wasconst&=~(1<<hr);
10376 regs[k].isconst&=~(1<<hr);
10377 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10378 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10379 branch_regs[k].regmap[hr]=f_regmap[hr];
10380 branch_regs[k].dirty&=~(1<<hr);
10381 branch_regs[k].wasconst&=~(1<<hr);
10382 branch_regs[k].isconst&=~(1<<hr);
10383 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10384 regmap_pre[k+2][hr]=f_regmap[hr];
10385 regs[k+2].wasdirty&=~(1<<hr);
10386 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10387 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10392 regmap_pre[k+1][hr]=f_regmap[hr];
10393 regs[k+1].wasdirty&=~(1<<hr);
10396 if(regs[j].regmap[hr]==f_regmap[hr])
10397 regs[j].regmap_entry[hr]=f_regmap[hr];
10401 if(regs[j].regmap[hr]>=0)
10403 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10404 //printf("no-match due to different register\n");
10407 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10408 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10411 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10413 // Stop on unconditional branch
10416 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10419 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10422 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10425 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10426 //printf("no-match due to different register (branch)\n");
10430 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10431 //printf("No free regs for store %x\n",start+j*4);
10434 if(f_regmap[hr]>=64) {
10435 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10440 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10451 // Non branch or undetermined branch target
10452 for(hr=0;hr<HOST_REGS;hr++)
10454 if(hr!=EXCLUDE_REG) {
10455 if(regs[i].regmap[hr]>64) {
10456 if(!((regs[i].dirty>>hr)&1))
10457 f_regmap[hr]=regs[i].regmap[hr];
10459 else if(regs[i].regmap[hr]>=0) {
10460 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10461 // dealloc old register
10463 for(n=0;n<HOST_REGS;n++)
10465 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10467 // and alloc new one
10468 f_regmap[hr]=regs[i].regmap[hr];
10473 // Try to restore cycle count at branch targets
10475 for(j=i;j<slen-1;j++) {
10476 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10477 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10478 //printf("no free regs for store %x\n",start+j*4);
10482 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10484 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10486 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10487 regs[k].regmap[HOST_CCREG]=CCREG;
10488 regmap_pre[k+1][HOST_CCREG]=CCREG;
10489 regs[k+1].wasdirty|=1<<HOST_CCREG;
10490 regs[k].dirty|=1<<HOST_CCREG;
10491 regs[k].wasconst&=~(1<<HOST_CCREG);
10492 regs[k].isconst&=~(1<<HOST_CCREG);
10495 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10497 // Work backwards from the branch target
10498 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10500 //printf("Extend backwards\n");
10503 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10504 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10505 //printf("no free regs for store %x\n",start+(k-1)*4);
10510 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10511 //printf("Extend CC, %x ->\n",start+k*4);
10513 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10514 regs[k].regmap[HOST_CCREG]=CCREG;
10515 regmap_pre[k+1][HOST_CCREG]=CCREG;
10516 regs[k+1].wasdirty|=1<<HOST_CCREG;
10517 regs[k].dirty|=1<<HOST_CCREG;
10518 regs[k].wasconst&=~(1<<HOST_CCREG);
10519 regs[k].isconst&=~(1<<HOST_CCREG);
10524 //printf("Fail Extend CC, %x ->\n",start+k*4);
10528 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10529 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10530 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10531 itype[i]!=FCONV&&itype[i]!=FCOMP)
10533 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10538 // Cache memory offset or tlb map pointer if a register is available
10539 #ifndef HOST_IMM_ADDR32
10544 int earliest_available[HOST_REGS];
10545 int loop_start[HOST_REGS];
10546 int score[HOST_REGS];
10547 int end[HOST_REGS];
10548 int reg=using_tlb?MMREG:ROREG;
10551 for(hr=0;hr<HOST_REGS;hr++) {
10552 score[hr]=0;earliest_available[hr]=0;
10553 loop_start[hr]=MAXBLOCK;
10555 for(i=0;i<slen-1;i++)
10557 // Can't do anything if no registers are available
10558 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10559 for(hr=0;hr<HOST_REGS;hr++) {
10560 score[hr]=0;earliest_available[hr]=i+1;
10561 loop_start[hr]=MAXBLOCK;
10564 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10566 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10567 for(hr=0;hr<HOST_REGS;hr++) {
10568 score[hr]=0;earliest_available[hr]=i+1;
10569 loop_start[hr]=MAXBLOCK;
10573 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10574 for(hr=0;hr<HOST_REGS;hr++) {
10575 score[hr]=0;earliest_available[hr]=i+1;
10576 loop_start[hr]=MAXBLOCK;
10581 // Mark unavailable registers
10582 for(hr=0;hr<HOST_REGS;hr++) {
10583 if(regs[i].regmap[hr]>=0) {
10584 score[hr]=0;earliest_available[hr]=i+1;
10585 loop_start[hr]=MAXBLOCK;
10587 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10588 if(branch_regs[i].regmap[hr]>=0) {
10589 score[hr]=0;earliest_available[hr]=i+2;
10590 loop_start[hr]=MAXBLOCK;
10594 // No register allocations after unconditional jumps
10595 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10597 for(hr=0;hr<HOST_REGS;hr++) {
10598 score[hr]=0;earliest_available[hr]=i+2;
10599 loop_start[hr]=MAXBLOCK;
10601 i++; // Skip delay slot too
10602 //printf("skip delay slot: %x\n",start+i*4);
10606 if(itype[i]==LOAD||itype[i]==LOADLR||
10607 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10608 for(hr=0;hr<HOST_REGS;hr++) {
10609 if(hr!=EXCLUDE_REG) {
10611 for(j=i;j<slen-1;j++) {
10612 if(regs[j].regmap[hr]>=0) break;
10613 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10614 if(branch_regs[j].regmap[hr]>=0) break;
10616 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10618 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10621 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10622 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10623 int t=(ba[j]-start)>>2;
10624 if(t<j&&t>=earliest_available[hr]) {
10625 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10626 // Score a point for hoisting loop invariant
10627 if(t<loop_start[hr]) loop_start[hr]=t;
10628 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10634 if(regs[t].regmap[hr]==reg) {
10635 // Score a point if the branch target matches this register
10640 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10641 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10646 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10648 // Stop on unconditional branch
10652 if(itype[j]==LOAD||itype[j]==LOADLR||
10653 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10660 // Find highest score and allocate that register
10662 for(hr=0;hr<HOST_REGS;hr++) {
10663 if(hr!=EXCLUDE_REG) {
10664 if(score[hr]>score[maxscore]) {
10666 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10670 if(score[maxscore]>1)
10672 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10673 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10674 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10675 assert(regs[j].regmap[maxscore]<0);
10676 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10677 regs[j].regmap[maxscore]=reg;
10678 regs[j].dirty&=~(1<<maxscore);
10679 regs[j].wasconst&=~(1<<maxscore);
10680 regs[j].isconst&=~(1<<maxscore);
10681 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10682 branch_regs[j].regmap[maxscore]=reg;
10683 branch_regs[j].wasdirty&=~(1<<maxscore);
10684 branch_regs[j].dirty&=~(1<<maxscore);
10685 branch_regs[j].wasconst&=~(1<<maxscore);
10686 branch_regs[j].isconst&=~(1<<maxscore);
10687 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10688 regmap_pre[j+2][maxscore]=reg;
10689 regs[j+2].wasdirty&=~(1<<maxscore);
10691 // loop optimization (loop_preload)
10692 int t=(ba[j]-start)>>2;
10693 if(t==loop_start[maxscore]) {
10694 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10695 regs[t].regmap_entry[maxscore]=reg;
10700 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10701 regmap_pre[j+1][maxscore]=reg;
10702 regs[j+1].wasdirty&=~(1<<maxscore);
10707 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10708 for(hr=0;hr<HOST_REGS;hr++) {
10709 score[hr]=0;earliest_available[hr]=i+i;
10710 loop_start[hr]=MAXBLOCK;
10718 // This allocates registers (if possible) one instruction prior
10719 // to use, which can avoid a load-use penalty on certain CPUs.
10720 for(i=0;i<slen-1;i++)
10722 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10726 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10727 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10730 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10732 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10734 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10735 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10736 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10737 regs[i].isconst&=~(1<<hr);
10738 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10739 constmap[i][hr]=constmap[i+1][hr];
10740 regs[i+1].wasdirty&=~(1<<hr);
10741 regs[i].dirty&=~(1<<hr);
10746 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10748 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10750 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10751 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10752 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10753 regs[i].isconst&=~(1<<hr);
10754 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10755 constmap[i][hr]=constmap[i+1][hr];
10756 regs[i+1].wasdirty&=~(1<<hr);
10757 regs[i].dirty&=~(1<<hr);
10761 // Preload target address for load instruction (non-constant)
10762 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10763 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10765 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10767 regs[i].regmap[hr]=rs1[i+1];
10768 regmap_pre[i+1][hr]=rs1[i+1];
10769 regs[i+1].regmap_entry[hr]=rs1[i+1];
10770 regs[i].isconst&=~(1<<hr);
10771 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10772 constmap[i][hr]=constmap[i+1][hr];
10773 regs[i+1].wasdirty&=~(1<<hr);
10774 regs[i].dirty&=~(1<<hr);
10778 // Load source into target register
10779 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10780 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10782 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10784 regs[i].regmap[hr]=rs1[i+1];
10785 regmap_pre[i+1][hr]=rs1[i+1];
10786 regs[i+1].regmap_entry[hr]=rs1[i+1];
10787 regs[i].isconst&=~(1<<hr);
10788 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10789 constmap[i][hr]=constmap[i+1][hr];
10790 regs[i+1].wasdirty&=~(1<<hr);
10791 regs[i].dirty&=~(1<<hr);
10795 // Preload map address
10796 #ifndef HOST_IMM_ADDR32
10797 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10798 hr=get_reg(regs[i+1].regmap,TLREG);
10800 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10801 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10803 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10805 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10806 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10807 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10808 regs[i].isconst&=~(1<<hr);
10809 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10810 constmap[i][hr]=constmap[i+1][hr];
10811 regs[i+1].wasdirty&=~(1<<hr);
10812 regs[i].dirty&=~(1<<hr);
10814 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10816 // move it to another register
10817 regs[i+1].regmap[hr]=-1;
10818 regmap_pre[i+2][hr]=-1;
10819 regs[i+1].regmap[nr]=TLREG;
10820 regmap_pre[i+2][nr]=TLREG;
10821 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10822 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10823 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10824 regs[i].isconst&=~(1<<nr);
10825 regs[i+1].isconst&=~(1<<nr);
10826 regs[i].dirty&=~(1<<nr);
10827 regs[i+1].wasdirty&=~(1<<nr);
10828 regs[i+1].dirty&=~(1<<nr);
10829 regs[i+2].wasdirty&=~(1<<nr);
10835 // Address for store instruction (non-constant)
10836 if(itype[i+1]==STORE||itype[i+1]==STORELR
10837 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10838 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10839 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10840 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10841 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10843 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10845 regs[i].regmap[hr]=rs1[i+1];
10846 regmap_pre[i+1][hr]=rs1[i+1];
10847 regs[i+1].regmap_entry[hr]=rs1[i+1];
10848 regs[i].isconst&=~(1<<hr);
10849 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10850 constmap[i][hr]=constmap[i+1][hr];
10851 regs[i+1].wasdirty&=~(1<<hr);
10852 regs[i].dirty&=~(1<<hr);
10856 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10857 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10859 hr=get_reg(regs[i+1].regmap,FTEMP);
10861 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10863 regs[i].regmap[hr]=rs1[i+1];
10864 regmap_pre[i+1][hr]=rs1[i+1];
10865 regs[i+1].regmap_entry[hr]=rs1[i+1];
10866 regs[i].isconst&=~(1<<hr);
10867 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10868 constmap[i][hr]=constmap[i+1][hr];
10869 regs[i+1].wasdirty&=~(1<<hr);
10870 regs[i].dirty&=~(1<<hr);
10872 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10874 // move it to another register
10875 regs[i+1].regmap[hr]=-1;
10876 regmap_pre[i+2][hr]=-1;
10877 regs[i+1].regmap[nr]=FTEMP;
10878 regmap_pre[i+2][nr]=FTEMP;
10879 regs[i].regmap[nr]=rs1[i+1];
10880 regmap_pre[i+1][nr]=rs1[i+1];
10881 regs[i+1].regmap_entry[nr]=rs1[i+1];
10882 regs[i].isconst&=~(1<<nr);
10883 regs[i+1].isconst&=~(1<<nr);
10884 regs[i].dirty&=~(1<<nr);
10885 regs[i+1].wasdirty&=~(1<<nr);
10886 regs[i+1].dirty&=~(1<<nr);
10887 regs[i+2].wasdirty&=~(1<<nr);
10891 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10892 if(itype[i+1]==LOAD)
10893 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10894 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10895 hr=get_reg(regs[i+1].regmap,FTEMP);
10896 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10897 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10898 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10900 if(hr>=0&®s[i].regmap[hr]<0) {
10901 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10902 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10903 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10904 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10905 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10906 regs[i].isconst&=~(1<<hr);
10907 regs[i+1].wasdirty&=~(1<<hr);
10908 regs[i].dirty&=~(1<<hr);
10917 /* Pass 6 - Optimize clean/dirty state */
10918 clean_registers(0,slen-1,1);
10920 /* Pass 7 - Identify 32-bit registers */
10926 for (i=slen-1;i>=0;i--)
10929 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10931 if(ba[i]<start || ba[i]>=(start+slen*4))
10933 // Branch out of this block, don't need anything
10939 // Need whatever matches the target
10940 // (and doesn't get overwritten by the delay slot instruction)
10942 int t=(ba[i]-start)>>2;
10943 if(ba[i]>start+i*4) {
10945 if(!(requires_32bit[t]&~regs[i].was32))
10946 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10949 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10950 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10951 if(!(pr32[t]&~regs[i].was32))
10952 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10955 // Conditional branch may need registers for following instructions
10956 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10959 r32|=requires_32bit[i+2];
10960 r32&=regs[i].was32;
10961 // Mark this address as a branch target since it may be called
10962 // upon return from interrupt
10966 // Merge in delay slot
10968 // These are overwritten unless the branch is "likely"
10969 // and the delay slot is nullified if not taken
10970 r32&=~(1LL<<rt1[i+1]);
10971 r32&=~(1LL<<rt2[i+1]);
10973 // Assume these are needed (delay slot)
10976 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10980 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10982 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10984 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10986 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10988 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10991 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10993 // SYSCALL instruction (software interrupt)
10996 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10998 // ERET instruction (return from interrupt)
11002 r32&=~(1LL<<rt1[i]);
11003 r32&=~(1LL<<rt2[i]);
11006 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
11010 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
11012 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
11014 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
11016 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
11018 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
11020 requires_32bit[i]=r32;
11022 // Dirty registers which are 32-bit, require 32-bit input
11023 // as they will be written as 32-bit values
11024 for(hr=0;hr<HOST_REGS;hr++)
11026 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
11027 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
11028 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
11029 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
11033 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
11036 for (i=slen-1;i>=0;i--)
11038 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11040 // Conditional branch
11041 if((source[i]>>16)!=0x1000&&i<slen-2) {
11042 // Mark this address as a branch target since it may be called
11043 // upon return from interrupt
11050 if(itype[slen-1]==SPAN) {
11051 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
11055 /* Debug/disassembly */
11056 for(i=0;i<slen;i++)
11060 for(r=1;r<=CCREG;r++) {
11061 if((unneeded_reg[i]>>r)&1) {
11062 if(r==HIREG) printf(" HI");
11063 else if(r==LOREG) printf(" LO");
11064 else printf(" r%d",r);
11069 for(r=1;r<=CCREG;r++) {
11070 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
11071 if(r==HIREG) printf(" HI");
11072 else if(r==LOREG) printf(" LO");
11073 else printf(" r%d",r);
11077 for(r=0;r<=CCREG;r++) {
11078 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11079 if((regs[i].was32>>r)&1) {
11080 if(r==CCREG) printf(" CC");
11081 else if(r==HIREG) printf(" HI");
11082 else if(r==LOREG) printf(" LO");
11083 else printf(" r%d",r);
11088 #if defined(__i386__) || defined(__x86_64__)
11089 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11092 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11095 if(needed_reg[i]&1) printf("eax ");
11096 if((needed_reg[i]>>1)&1) printf("ecx ");
11097 if((needed_reg[i]>>2)&1) printf("edx ");
11098 if((needed_reg[i]>>3)&1) printf("ebx ");
11099 if((needed_reg[i]>>5)&1) printf("ebp ");
11100 if((needed_reg[i]>>6)&1) printf("esi ");
11101 if((needed_reg[i]>>7)&1) printf("edi ");
11103 for(r=0;r<=CCREG;r++) {
11104 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11105 if((requires_32bit[i]>>r)&1) {
11106 if(r==CCREG) printf(" CC");
11107 else if(r==HIREG) printf(" HI");
11108 else if(r==LOREG) printf(" LO");
11109 else printf(" r%d",r);
11114 for(r=0;r<=CCREG;r++) {
11115 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11116 if((pr32[i]>>r)&1) {
11117 if(r==CCREG) printf(" CC");
11118 else if(r==HIREG) printf(" HI");
11119 else if(r==LOREG) printf(" LO");
11120 else printf(" r%d",r);
11123 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11125 #if defined(__i386__) || defined(__x86_64__)
11126 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11128 if(regs[i].wasdirty&1) printf("eax ");
11129 if((regs[i].wasdirty>>1)&1) printf("ecx ");
11130 if((regs[i].wasdirty>>2)&1) printf("edx ");
11131 if((regs[i].wasdirty>>3)&1) printf("ebx ");
11132 if((regs[i].wasdirty>>5)&1) printf("ebp ");
11133 if((regs[i].wasdirty>>6)&1) printf("esi ");
11134 if((regs[i].wasdirty>>7)&1) printf("edi ");
11137 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11139 if(regs[i].wasdirty&1) printf("r0 ");
11140 if((regs[i].wasdirty>>1)&1) printf("r1 ");
11141 if((regs[i].wasdirty>>2)&1) printf("r2 ");
11142 if((regs[i].wasdirty>>3)&1) printf("r3 ");
11143 if((regs[i].wasdirty>>4)&1) printf("r4 ");
11144 if((regs[i].wasdirty>>5)&1) printf("r5 ");
11145 if((regs[i].wasdirty>>6)&1) printf("r6 ");
11146 if((regs[i].wasdirty>>7)&1) printf("r7 ");
11147 if((regs[i].wasdirty>>8)&1) printf("r8 ");
11148 if((regs[i].wasdirty>>9)&1) printf("r9 ");
11149 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11150 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11153 disassemble_inst(i);
11154 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11155 #if defined(__i386__) || defined(__x86_64__)
11156 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11157 if(regs[i].dirty&1) printf("eax ");
11158 if((regs[i].dirty>>1)&1) printf("ecx ");
11159 if((regs[i].dirty>>2)&1) printf("edx ");
11160 if((regs[i].dirty>>3)&1) printf("ebx ");
11161 if((regs[i].dirty>>5)&1) printf("ebp ");
11162 if((regs[i].dirty>>6)&1) printf("esi ");
11163 if((regs[i].dirty>>7)&1) printf("edi ");
11166 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11167 if(regs[i].dirty&1) printf("r0 ");
11168 if((regs[i].dirty>>1)&1) printf("r1 ");
11169 if((regs[i].dirty>>2)&1) printf("r2 ");
11170 if((regs[i].dirty>>3)&1) printf("r3 ");
11171 if((regs[i].dirty>>4)&1) printf("r4 ");
11172 if((regs[i].dirty>>5)&1) printf("r5 ");
11173 if((regs[i].dirty>>6)&1) printf("r6 ");
11174 if((regs[i].dirty>>7)&1) printf("r7 ");
11175 if((regs[i].dirty>>8)&1) printf("r8 ");
11176 if((regs[i].dirty>>9)&1) printf("r9 ");
11177 if((regs[i].dirty>>10)&1) printf("r10 ");
11178 if((regs[i].dirty>>12)&1) printf("r12 ");
11181 if(regs[i].isconst) {
11182 printf("constants: ");
11183 #if defined(__i386__) || defined(__x86_64__)
11184 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11185 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11186 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11187 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11188 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11189 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11190 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11193 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11194 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11195 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11196 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11197 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11198 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11199 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11200 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11201 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11202 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11203 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11204 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11210 for(r=0;r<=CCREG;r++) {
11211 if((regs[i].is32>>r)&1) {
11212 if(r==CCREG) printf(" CC");
11213 else if(r==HIREG) printf(" HI");
11214 else if(r==LOREG) printf(" LO");
11215 else printf(" r%d",r);
11221 for(r=0;r<=CCREG;r++) {
11222 if((p32[i]>>r)&1) {
11223 if(r==CCREG) printf(" CC");
11224 else if(r==HIREG) printf(" HI");
11225 else if(r==LOREG) printf(" LO");
11226 else printf(" r%d",r);
11229 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11230 else printf("\n");*/
11231 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11232 #if defined(__i386__) || defined(__x86_64__)
11233 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11234 if(branch_regs[i].dirty&1) printf("eax ");
11235 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11236 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11237 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11238 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11239 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11240 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11243 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11244 if(branch_regs[i].dirty&1) printf("r0 ");
11245 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11246 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11247 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11248 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11249 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11250 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11251 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11252 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11253 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11254 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11255 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11259 for(r=0;r<=CCREG;r++) {
11260 if((branch_regs[i].is32>>r)&1) {
11261 if(r==CCREG) printf(" CC");
11262 else if(r==HIREG) printf(" HI");
11263 else if(r==LOREG) printf(" LO");
11264 else printf(" r%d",r);
11273 /* Pass 8 - Assembly */
11274 linkcount=0;stubcount=0;
11275 ds=0;is_delayslot=0;
11277 uint64_t is32_pre=0;
11279 u_int beginning=(u_int)out;
11280 if((u_int)addr&1) {
11284 u_int instr_addr0_override=0;
11287 if (start == 0x80030000) {
11288 // nasty hack for fastbios thing
11289 // override block entry to this code
11290 instr_addr0_override=(u_int)out;
11291 emit_movimm(start,0);
11292 // abuse io address var as a flag that we
11293 // have already returned here once
11294 emit_readword((int)&address,1);
11295 emit_writeword(0,(int)&pcaddr);
11296 emit_writeword(0,(int)&address);
11298 emit_jne((int)new_dyna_leave);
11301 for(i=0;i<slen;i++)
11303 //if(ds) printf("ds: ");
11304 disassemble_inst(i);
11306 ds=0; // Skip delay slot
11307 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11310 speculate_register_values(i);
11311 #ifndef DESTRUCTIVE_WRITEBACK
11312 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11314 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11315 unneeded_reg[i],unneeded_reg_upper[i]);
11316 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11317 unneeded_reg[i],unneeded_reg_upper[i]);
11319 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11320 is32_pre=branch_regs[i].is32;
11321 dirty_pre=branch_regs[i].dirty;
11323 is32_pre=regs[i].is32;
11324 dirty_pre=regs[i].dirty;
11328 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11330 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11331 unneeded_reg[i],unneeded_reg_upper[i]);
11332 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11334 // branch target entry point
11335 instr_addr[i]=(u_int)out;
11336 assem_debug("<->\n");
11338 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11339 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11340 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11341 address_generation(i,®s[i],regs[i].regmap_entry);
11342 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11343 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11345 // Load the delay slot registers if necessary
11346 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11347 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11348 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11349 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11350 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11351 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11355 // Preload registers for following instruction
11356 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11357 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11358 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11359 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11360 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11361 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11363 // TODO: if(is_ooo(i)) address_generation(i+1);
11364 if(itype[i]==CJUMP||itype[i]==FJUMP)
11365 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11366 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11367 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11368 if(bt[i]) cop1_usable=0;
11372 alu_assemble(i,®s[i]);break;
11374 imm16_assemble(i,®s[i]);break;
11376 shift_assemble(i,®s[i]);break;
11378 shiftimm_assemble(i,®s[i]);break;
11380 load_assemble(i,®s[i]);break;
11382 loadlr_assemble(i,®s[i]);break;
11384 store_assemble(i,®s[i]);break;
11386 storelr_assemble(i,®s[i]);break;
11388 cop0_assemble(i,®s[i]);break;
11390 cop1_assemble(i,®s[i]);break;
11392 c1ls_assemble(i,®s[i]);break;
11394 cop2_assemble(i,®s[i]);break;
11396 c2ls_assemble(i,®s[i]);break;
11398 c2op_assemble(i,®s[i]);break;
11400 fconv_assemble(i,®s[i]);break;
11402 float_assemble(i,®s[i]);break;
11404 fcomp_assemble(i,®s[i]);break;
11406 multdiv_assemble(i,®s[i]);break;
11408 mov_assemble(i,®s[i]);break;
11410 syscall_assemble(i,®s[i]);break;
11412 hlecall_assemble(i,®s[i]);break;
11414 intcall_assemble(i,®s[i]);break;
11416 ujump_assemble(i,®s[i]);ds=1;break;
11418 rjump_assemble(i,®s[i]);ds=1;break;
11420 cjump_assemble(i,®s[i]);ds=1;break;
11422 sjump_assemble(i,®s[i]);ds=1;break;
11424 fjump_assemble(i,®s[i]);ds=1;break;
11426 pagespan_assemble(i,®s[i]);break;
11428 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11429 literal_pool(1024);
11431 literal_pool_jumpover(256);
11434 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11435 // If the block did not end with an unconditional branch,
11436 // add a jump to the next instruction.
11438 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11439 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11441 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11442 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11443 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11444 emit_loadreg(CCREG,HOST_CCREG);
11445 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11447 else if(!likely[i-2])
11449 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11450 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11454 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11455 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11457 add_to_linker((int)out,start+i*4,0);
11464 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11465 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11466 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11467 emit_loadreg(CCREG,HOST_CCREG);
11468 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11469 add_to_linker((int)out,start+i*4,0);
11473 // TODO: delay slot stubs?
11475 for(i=0;i<stubcount;i++)
11477 switch(stubs[i][0])
11485 do_readstub(i);break;
11490 do_writestub(i);break;
11492 do_ccstub(i);break;
11494 do_invstub(i);break;
11496 do_cop1stub(i);break;
11498 do_unalignedwritestub(i);break;
11502 if (instr_addr0_override)
11503 instr_addr[0] = instr_addr0_override;
11505 /* Pass 9 - Linker */
11506 for(i=0;i<linkcount;i++)
11508 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11510 if(!link_addr[i][2])
11513 void *addr=check_addr(link_addr[i][1]);
11514 emit_extjump(link_addr[i][0],link_addr[i][1]);
11516 set_jump_target(link_addr[i][0],(int)addr);
11517 add_link(link_addr[i][1],stub);
11519 else set_jump_target(link_addr[i][0],(int)stub);
11524 int target=(link_addr[i][1]-start)>>2;
11525 assert(target>=0&&target<slen);
11526 assert(instr_addr[target]);
11527 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11528 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11530 set_jump_target(link_addr[i][0],instr_addr[target]);
11534 // External Branch Targets (jump_in)
11535 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11536 for(i=0;i<slen;i++)
11540 if(instr_addr[i]) // TODO - delay slots (=null)
11542 u_int vaddr=start+i*4;
11543 u_int page=get_page(vaddr);
11544 u_int vpage=get_vpage(vaddr);
11546 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11548 if(!requires_32bit[i])
11553 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11554 assem_debug("jump_in: %x\n",start+i*4);
11555 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11556 int entry_point=do_dirty_stub(i);
11557 ll_add(jump_in+page,vaddr,(void *)entry_point);
11558 // If there was an existing entry in the hash table,
11559 // replace it with the new address.
11560 // Don't add new entries. We'll insert the
11561 // ones that actually get used in check_addr().
11562 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11563 if(ht_bin[0]==vaddr) {
11564 ht_bin[1]=entry_point;
11566 if(ht_bin[2]==vaddr) {
11567 ht_bin[3]=entry_point;
11572 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11573 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11574 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11575 //int entry_point=(int)out;
11576 ////assem_debug("entry_point: %x\n",entry_point);
11577 //load_regs_entry(i);
11578 //if(entry_point==(int)out)
11579 // entry_point=instr_addr[i];
11581 // emit_jmp(instr_addr[i]);
11582 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11583 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11584 int entry_point=do_dirty_stub(i);
11585 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11590 // Write out the literal pool if necessary
11592 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11594 if(((u_int)out)&7) emit_addnop(13);
11596 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11597 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11598 memcpy(copy,source,slen*4);
11602 __clear_cache((void *)beginning,out);
11605 // If we're within 256K of the end of the buffer,
11606 // start over from the beginning. (Is 256K enough?)
11607 if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11609 // Trap writes to any of the pages we compiled
11610 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11612 #ifndef DISABLE_TLB
11613 memory_map[i]|=0x40000000;
11614 if((signed int)start>=(signed int)0xC0000000) {
11616 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11618 memory_map[j]|=0x40000000;
11619 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11623 inv_code_start=inv_code_end=~0;
11625 // for PCSX we need to mark all mirrors too
11626 if(get_page(start)<(RAM_SIZE>>12))
11627 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11628 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11629 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11630 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11633 /* Pass 10 - Free memory by expiring oldest blocks */
11635 int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11636 while(expirep!=end)
11638 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11639 int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11640 inv_debug("EXP: Phase %d\n",expirep);
11641 switch((expirep>>11)&3)
11644 // Clear jump_in and jump_dirty
11645 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11646 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11647 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11648 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11652 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11653 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11656 // Clear hash table
11657 for(i=0;i<32;i++) {
11658 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11659 if((ht_bin[3]>>shift)==(base>>shift) ||
11660 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11661 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11662 ht_bin[2]=ht_bin[3]=-1;
11664 if((ht_bin[1]>>shift)==(base>>shift) ||
11665 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11666 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11667 ht_bin[0]=ht_bin[2];
11668 ht_bin[1]=ht_bin[3];
11669 ht_bin[2]=ht_bin[3]=-1;
11676 if((expirep&2047)==0)
11679 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11680 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11683 expirep=(expirep+1)&65535;
11688 // vim:shiftwidth=2:expandtab