1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
49 signed char regmap_entry[HOST_REGS];
50 signed char regmap[HOST_REGS];
59 u_int loadedconst; // host regs that have constants loaded
60 u_int waswritten; // MIPS regs that were used as store base before
68 struct ll_entry *next;
74 char insn[MAXBLOCK][10];
75 u_char itype[MAXBLOCK];
76 u_char opcode[MAXBLOCK];
77 u_char opcode2[MAXBLOCK];
85 u_char dep1[MAXBLOCK];
86 u_char dep2[MAXBLOCK];
88 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89 static uint64_t gte_rt[MAXBLOCK];
90 static uint64_t gte_unneeded[MAXBLOCK];
91 static u_int smrv[32]; // speculated MIPS register values
92 static u_int smrv_strong; // mask or regs that are likely to have correct values
93 static u_int smrv_weak; // same, but somewhat less likely
94 static u_int smrv_strong_next; // same, but after current insn executes
95 static u_int smrv_weak_next;
98 char likely[MAXBLOCK];
101 uint64_t unneeded_reg[MAXBLOCK];
102 uint64_t unneeded_reg_upper[MAXBLOCK];
103 uint64_t branch_unneeded_reg[MAXBLOCK];
104 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
105 uint64_t p32[MAXBLOCK];
106 uint64_t pr32[MAXBLOCK];
107 signed char regmap_pre[MAXBLOCK][HOST_REGS];
108 static uint64_t current_constmap[HOST_REGS];
109 static uint64_t constmap[MAXBLOCK][HOST_REGS];
110 static struct regstat regs[MAXBLOCK];
111 static struct regstat branch_regs[MAXBLOCK];
112 signed char minimum_free_regs[MAXBLOCK];
113 u_int needed_reg[MAXBLOCK];
114 uint64_t requires_32bit[MAXBLOCK];
115 u_int wont_dirty[MAXBLOCK];
116 u_int will_dirty[MAXBLOCK];
119 u_int instr_addr[MAXBLOCK];
120 u_int link_addr[MAXBLOCK][3];
122 u_int stubs[MAXBLOCK*3][8];
124 u_int literals[1024][2];
129 struct ll_entry *jump_in[4096];
130 struct ll_entry *jump_out[4096];
131 struct ll_entry *jump_dirty[4096];
132 u_int hash_table[65536][4] __attribute__((aligned(16)));
133 char shadow[1048576] __attribute__((aligned(16)));
139 static const u_int using_tlb=0;
141 int new_dynarec_did_compile;
142 int new_dynarec_hacks;
143 u_int stop_after_jal;
144 extern u_char restore_candidate[512];
145 extern int cycle_count;
147 /* registers that may be allocated */
149 #define HIREG 32 // hi
150 #define LOREG 33 // lo
151 #define FSREG 34 // FPU status (FCSR)
152 #define CSREG 35 // Coprocessor status
153 #define CCREG 36 // Cycle count
154 #define INVCP 37 // Pointer to invalid_code
155 #define MMREG 38 // Pointer to memory_map
156 #define ROREG 39 // ram offset (if rdram!=0x80000000)
158 #define FTEMP 40 // FPU temporary register
159 #define PTEMP 41 // Prefetch temporary register
160 #define TLREG 42 // TLB mapping offset
161 #define RHASH 43 // Return address hash
162 #define RHTBL 44 // Return address hash table address
163 #define RTEMP 45 // JR/JALR address register
165 #define AGEN1 46 // Address generation temporary register
166 #define AGEN2 47 // Address generation temporary register
167 #define MGEN1 48 // Maptable address generation temporary register
168 #define MGEN2 49 // Maptable address generation temporary register
169 #define BTREG 50 // Branch target temporary register
171 /* instruction types */
172 #define NOP 0 // No operation
173 #define LOAD 1 // Load
174 #define STORE 2 // Store
175 #define LOADLR 3 // Unaligned load
176 #define STORELR 4 // Unaligned store
177 #define MOV 5 // Move
178 #define ALU 6 // Arithmetic/logic
179 #define MULTDIV 7 // Multiply/divide
180 #define SHIFT 8 // Shift by register
181 #define SHIFTIMM 9// Shift by immediate
182 #define IMM16 10 // 16-bit immediate
183 #define RJUMP 11 // Unconditional jump to register
184 #define UJUMP 12 // Unconditional jump
185 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
186 #define SJUMP 14 // Conditional branch (regimm format)
187 #define COP0 15 // Coprocessor 0
188 #define COP1 16 // Coprocessor 1
189 #define C1LS 17 // Coprocessor 1 load/store
190 #define FJUMP 18 // Conditional branch (floating point)
191 #define FLOAT 19 // Floating point unit
192 #define FCONV 20 // Convert integer to float
193 #define FCOMP 21 // Floating point compare (sets FSREG)
194 #define SYSCALL 22// SYSCALL
195 #define OTHER 23 // Other
196 #define SPAN 24 // Branch/delay slot spans 2 pages
197 #define NI 25 // Not implemented
198 #define HLECALL 26// PCSX fake opcodes for HLE
199 #define COP2 27 // Coprocessor 2 move
200 #define C2LS 28 // Coprocessor 2 load/store
201 #define C2OP 29 // Coprocessor 2 operation
202 #define INTCALL 30// Call interpreter to handle rare corner cases
211 #define LOADBU_STUB 7
212 #define LOADHU_STUB 8
213 #define STOREB_STUB 9
214 #define STOREH_STUB 10
215 #define STOREW_STUB 11
216 #define STORED_STUB 12
217 #define STORELR_STUB 13
218 #define INVCODE_STUB 14
226 int new_recompile_block(int addr);
227 void *get_addr_ht(u_int vaddr);
228 void invalidate_block(u_int block);
229 void invalidate_addr(u_int addr);
230 void remove_hash(int vaddr);
233 void dyna_linker_ds();
235 void verify_code_vm();
236 void verify_code_ds();
239 void fp_exception_ds();
241 void jump_syscall_hle();
245 void new_dyna_leave();
250 void read_nomem_new();
251 void read_nomemb_new();
252 void read_nomemh_new();
253 void read_nomemd_new();
254 void write_nomem_new();
255 void write_nomemb_new();
256 void write_nomemh_new();
257 void write_nomemd_new();
258 void write_rdram_new();
259 void write_rdramb_new();
260 void write_rdramh_new();
261 void write_rdramd_new();
262 extern u_int memory_map[1048576];
264 // Needed by assembler
265 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
266 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
267 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
268 void load_all_regs(signed char i_regmap[]);
269 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
270 void load_regs_entry(int t);
271 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
275 //#define DEBUG_CYCLE_COUNT 1
277 int cycle_multiplier; // 100 for 1.0
279 static int CLOCK_ADJUST(int x)
282 return (x * cycle_multiplier + s * 50) / 100;
285 static void tlb_hacks()
289 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
293 switch (ROM_HEADER->Country_code&0xFF)
305 // Unknown country code
309 u_int rom_addr=(u_int)rom;
311 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
312 // in the lower 4G of memory to use this hack. Copy it if necessary.
313 if((void *)rom>(void *)0xffffffff) {
314 munmap(ROM_COPY, 67108864);
315 if(mmap(ROM_COPY, 12582912,
316 PROT_READ | PROT_WRITE,
317 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
318 -1, 0) <= 0) {printf("mmap() failed\n");}
319 memcpy(ROM_COPY,rom,12582912);
320 rom_addr=(u_int)ROM_COPY;
324 for(n=0x7F000;n<0x80000;n++) {
325 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
332 static u_int get_page(u_int vaddr)
335 u_int page=(vaddr^0x80000000)>>12;
337 u_int page=vaddr&~0xe0000000;
338 if (page < 0x1000000)
339 page &= ~0x0e00000; // RAM mirrors
343 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
345 if(page>2048) page=2048+(page&2047);
350 static u_int get_vpage(u_int vaddr)
352 u_int vpage=(vaddr^0x80000000)>>12;
354 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
356 if(vpage>2048) vpage=2048+(vpage&2047);
360 // no virtual mem in PCSX
361 static u_int get_vpage(u_int vaddr)
363 return get_page(vaddr);
367 // Get address from virtual address
368 // This is called from the recompiled JR/JALR instructions
369 void *get_addr(u_int vaddr)
371 u_int page=get_page(vaddr);
372 u_int vpage=get_vpage(vaddr);
373 struct ll_entry *head;
374 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
377 if(head->vaddr==vaddr&&head->reg32==0) {
378 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
379 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
382 ht_bin[1]=(int)head->addr;
388 head=jump_dirty[vpage];
390 if(head->vaddr==vaddr&&head->reg32==0) {
391 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
392 // Don't restore blocks which are about to expire from the cache
393 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
394 if(verify_dirty(head->addr)) {
395 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
396 invalid_code[vaddr>>12]=0;
397 inv_code_start=inv_code_end=~0;
399 memory_map[vaddr>>12]|=0x40000000;
403 if(tlb_LUT_r[vaddr>>12]) {
404 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
405 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
408 restore_candidate[vpage>>3]|=1<<(vpage&7);
410 else restore_candidate[page>>3]|=1<<(page&7);
411 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
412 if(ht_bin[0]==vaddr) {
413 ht_bin[1]=(int)head->addr; // Replace existing entry
419 ht_bin[1]=(int)head->addr;
427 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
428 int r=new_recompile_block(vaddr);
429 if(r==0) return get_addr(vaddr);
430 // Execute in unmapped page, generate pagefault execption
432 Cause=(vaddr<<31)|0x8;
433 EPC=(vaddr&1)?vaddr-5:vaddr;
435 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
436 EntryHi=BadVAddr&0xFFFFE000;
437 return get_addr_ht(0x80000000);
439 // Look up address in hash table first
440 void *get_addr_ht(u_int vaddr)
442 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
443 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
444 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
445 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
446 return get_addr(vaddr);
449 void *get_addr_32(u_int vaddr,u_int flags)
452 return get_addr(vaddr);
454 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
455 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
456 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
457 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
458 u_int page=get_page(vaddr);
459 u_int vpage=get_vpage(vaddr);
460 struct ll_entry *head;
463 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
464 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
466 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
468 ht_bin[1]=(int)head->addr;
470 }else if(ht_bin[2]==-1) {
471 ht_bin[3]=(int)head->addr;
474 //ht_bin[3]=ht_bin[1];
475 //ht_bin[2]=ht_bin[0];
476 //ht_bin[1]=(int)head->addr;
483 head=jump_dirty[vpage];
485 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
486 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
487 // Don't restore blocks which are about to expire from the cache
488 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
489 if(verify_dirty(head->addr)) {
490 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
491 invalid_code[vaddr>>12]=0;
492 inv_code_start=inv_code_end=~0;
493 memory_map[vaddr>>12]|=0x40000000;
496 if(tlb_LUT_r[vaddr>>12]) {
497 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
498 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
501 restore_candidate[vpage>>3]|=1<<(vpage&7);
503 else restore_candidate[page>>3]|=1<<(page&7);
505 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
507 ht_bin[1]=(int)head->addr;
509 }else if(ht_bin[2]==-1) {
510 ht_bin[3]=(int)head->addr;
513 //ht_bin[3]=ht_bin[1];
514 //ht_bin[2]=ht_bin[0];
515 //ht_bin[1]=(int)head->addr;
523 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
524 int r=new_recompile_block(vaddr);
525 if(r==0) return get_addr(vaddr);
526 // Execute in unmapped page, generate pagefault execption
528 Cause=(vaddr<<31)|0x8;
529 EPC=(vaddr&1)?vaddr-5:vaddr;
531 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
532 EntryHi=BadVAddr&0xFFFFE000;
533 return get_addr_ht(0x80000000);
537 void clear_all_regs(signed char regmap[])
540 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
543 signed char get_reg(signed char regmap[],int r)
546 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
550 // Find a register that is available for two consecutive cycles
551 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
554 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
558 int count_free_regs(signed char regmap[])
562 for(hr=0;hr<HOST_REGS;hr++)
564 if(hr!=EXCLUDE_REG) {
565 if(regmap[hr]<0) count++;
571 void dirty_reg(struct regstat *cur,signed char reg)
575 for (hr=0;hr<HOST_REGS;hr++) {
576 if((cur->regmap[hr]&63)==reg) {
582 // If we dirty the lower half of a 64 bit register which is now being
583 // sign-extended, we need to dump the upper half.
584 // Note: Do this only after completion of the instruction, because
585 // some instructions may need to read the full 64-bit value even if
586 // overwriting it (eg SLTI, DSRA32).
587 static void flush_dirty_uppers(struct regstat *cur)
590 for (hr=0;hr<HOST_REGS;hr++) {
591 if((cur->dirty>>hr)&1) {
594 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
599 void set_const(struct regstat *cur,signed char reg,uint64_t value)
603 for (hr=0;hr<HOST_REGS;hr++) {
604 if(cur->regmap[hr]==reg) {
606 current_constmap[hr]=value;
608 else if((cur->regmap[hr]^64)==reg) {
610 current_constmap[hr]=value>>32;
615 void clear_const(struct regstat *cur,signed char reg)
619 for (hr=0;hr<HOST_REGS;hr++) {
620 if((cur->regmap[hr]&63)==reg) {
621 cur->isconst&=~(1<<hr);
626 int is_const(struct regstat *cur,signed char reg)
631 for (hr=0;hr<HOST_REGS;hr++) {
632 if((cur->regmap[hr]&63)==reg) {
633 return (cur->isconst>>hr)&1;
638 uint64_t get_const(struct regstat *cur,signed char reg)
642 for (hr=0;hr<HOST_REGS;hr++) {
643 if(cur->regmap[hr]==reg) {
644 return current_constmap[hr];
647 printf("Unknown constant in r%d\n",reg);
651 // Least soon needed registers
652 // Look at the next ten instructions and see which registers
653 // will be used. Try not to reallocate these.
654 void lsn(u_char hsn[], int i, int *preferred_reg)
664 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
666 // Don't go past an unconditonal jump
673 if(rs1[i+j]) hsn[rs1[i+j]]=j;
674 if(rs2[i+j]) hsn[rs2[i+j]]=j;
675 if(rt1[i+j]) hsn[rt1[i+j]]=j;
676 if(rt2[i+j]) hsn[rt2[i+j]]=j;
677 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
678 // Stores can allocate zero
682 // On some architectures stores need invc_ptr
683 #if defined(HOST_IMM8)
684 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
688 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
696 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
698 // Follow first branch
699 int t=(ba[i+b]-start)>>2;
700 j=7-b;if(t+j>=slen) j=slen-t-1;
703 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
704 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
705 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
706 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
709 // TODO: preferred register based on backward branch
711 // Delay slot should preferably not overwrite branch conditions or cycle count
712 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
713 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
714 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
720 // Coprocessor load/store needs FTEMP, even if not declared
721 if(itype[i]==C1LS||itype[i]==C2LS) {
724 // Load L/R also uses FTEMP as a temporary register
725 if(itype[i]==LOADLR) {
728 // Also SWL/SWR/SDL/SDR
729 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
732 // Don't remove the TLB registers either
733 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
736 // Don't remove the miniht registers
737 if(itype[i]==UJUMP||itype[i]==RJUMP)
744 // We only want to allocate registers if we're going to use them again soon
745 int needed_again(int r, int i)
751 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
753 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
754 return 0; // Don't need any registers if exiting the block
762 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
764 // Don't go past an unconditonal jump
768 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
775 if(rs1[i+j]==r) rn=j;
776 if(rs2[i+j]==r) rn=j;
777 if((unneeded_reg[i+j]>>r)&1) rn=10;
778 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
786 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
788 // Follow first branch
790 int t=(ba[i+b]-start)>>2;
791 j=7-b;if(t+j>=slen) j=slen-t-1;
794 if(!((unneeded_reg[t+j]>>r)&1)) {
795 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
796 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
806 // Try to match register allocations at the end of a loop with those
808 int loop_reg(int i, int r, int hr)
817 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
819 // Don't go past an unconditonal jump
826 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
831 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
832 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
833 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
835 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
837 int t=(ba[i+k]-start)>>2;
838 int reg=get_reg(regs[t].regmap_entry,r);
839 if(reg>=0) return reg;
840 //reg=get_reg(regs[t+1].regmap_entry,r);
841 //if(reg>=0) return reg;
849 // Allocate every register, preserving source/target regs
850 void alloc_all(struct regstat *cur,int i)
854 for(hr=0;hr<HOST_REGS;hr++) {
855 if(hr!=EXCLUDE_REG) {
856 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
857 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
860 cur->dirty&=~(1<<hr);
863 if((cur->regmap[hr]&63)==0)
866 cur->dirty&=~(1<<hr);
873 void div64(int64_t dividend,int64_t divisor)
877 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
878 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
880 void divu64(uint64_t dividend,uint64_t divisor)
884 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
885 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
888 void mult64(uint64_t m1,uint64_t m2)
890 unsigned long long int op1, op2, op3, op4;
891 unsigned long long int result1, result2, result3, result4;
892 unsigned long long int temp1, temp2, temp3, temp4;
908 op1 = op2 & 0xFFFFFFFF;
909 op2 = (op2 >> 32) & 0xFFFFFFFF;
910 op3 = op4 & 0xFFFFFFFF;
911 op4 = (op4 >> 32) & 0xFFFFFFFF;
914 temp2 = (temp1 >> 32) + op1 * op4;
916 temp4 = (temp3 >> 32) + op2 * op4;
918 result1 = temp1 & 0xFFFFFFFF;
919 result2 = temp2 + (temp3 & 0xFFFFFFFF);
920 result3 = (result2 >> 32) + temp4;
921 result4 = (result3 >> 32);
923 lo = result1 | (result2 << 32);
924 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
933 void multu64(uint64_t m1,uint64_t m2)
935 unsigned long long int op1, op2, op3, op4;
936 unsigned long long int result1, result2, result3, result4;
937 unsigned long long int temp1, temp2, temp3, temp4;
939 op1 = m1 & 0xFFFFFFFF;
940 op2 = (m1 >> 32) & 0xFFFFFFFF;
941 op3 = m2 & 0xFFFFFFFF;
942 op4 = (m2 >> 32) & 0xFFFFFFFF;
945 temp2 = (temp1 >> 32) + op1 * op4;
947 temp4 = (temp3 >> 32) + op2 * op4;
949 result1 = temp1 & 0xFFFFFFFF;
950 result2 = temp2 + (temp3 & 0xFFFFFFFF);
951 result3 = (result2 >> 32) + temp4;
952 result4 = (result3 >> 32);
954 lo = result1 | (result2 << 32);
955 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
957 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
958 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
961 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
969 else original=loaded;
972 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
975 original>>=64-(bits^56);
976 original<<=64-(bits^56);
980 else original=loaded;
986 #include "assem_x86.c"
989 #include "assem_x64.c"
992 #include "assem_arm.c"
995 // Add virtual address mapping to linked list
996 void ll_add(struct ll_entry **head,int vaddr,void *addr)
998 struct ll_entry *new_entry;
999 new_entry=malloc(sizeof(struct ll_entry));
1000 assert(new_entry!=NULL);
1001 new_entry->vaddr=vaddr;
1003 new_entry->addr=addr;
1004 new_entry->next=*head;
1008 // Add virtual address mapping for 32-bit compiled block
1009 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1011 ll_add(head,vaddr,addr);
1013 (*head)->reg32=reg32;
1017 // Check if an address is already compiled
1018 // but don't return addresses which are about to expire from the cache
1019 void *check_addr(u_int vaddr)
1021 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1022 if(ht_bin[0]==vaddr) {
1023 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1024 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1026 if(ht_bin[2]==vaddr) {
1027 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1028 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1030 u_int page=get_page(vaddr);
1031 struct ll_entry *head;
1034 if(head->vaddr==vaddr&&head->reg32==0) {
1035 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1036 // Update existing entry with current address
1037 if(ht_bin[0]==vaddr) {
1038 ht_bin[1]=(int)head->addr;
1041 if(ht_bin[2]==vaddr) {
1042 ht_bin[3]=(int)head->addr;
1045 // Insert into hash table with low priority.
1046 // Don't evict existing entries, as they are probably
1047 // addresses that are being accessed frequently.
1049 ht_bin[1]=(int)head->addr;
1051 }else if(ht_bin[2]==-1) {
1052 ht_bin[3]=(int)head->addr;
1063 void remove_hash(int vaddr)
1065 //printf("remove hash: %x\n",vaddr);
1066 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1067 if(ht_bin[2]==vaddr) {
1068 ht_bin[2]=ht_bin[3]=-1;
1070 if(ht_bin[0]==vaddr) {
1071 ht_bin[0]=ht_bin[2];
1072 ht_bin[1]=ht_bin[3];
1073 ht_bin[2]=ht_bin[3]=-1;
1077 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1079 struct ll_entry *next;
1081 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1082 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1084 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1085 remove_hash((*head)->vaddr);
1092 head=&((*head)->next);
1097 // Remove all entries from linked list
1098 void ll_clear(struct ll_entry **head)
1100 struct ll_entry *cur;
1101 struct ll_entry *next;
1112 // Dereference the pointers and remove if it matches
1113 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1116 int ptr=get_pointer(head->addr);
1117 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1118 if(((ptr>>shift)==(addr>>shift)) ||
1119 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1121 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1122 u_int host_addr=(u_int)kill_pointer(head->addr);
1124 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1131 // This is called when we write to a compiled block (see do_invstub)
1132 void invalidate_page(u_int page)
1134 struct ll_entry *head;
1135 struct ll_entry *next;
1139 inv_debug("INVALIDATE: %x\n",head->vaddr);
1140 remove_hash(head->vaddr);
1145 head=jump_out[page];
1148 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1149 u_int host_addr=(u_int)kill_pointer(head->addr);
1151 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1159 static void invalidate_block_range(u_int block, u_int first, u_int last)
1161 u_int page=get_page(block<<12);
1162 //printf("first=%d last=%d\n",first,last);
1163 invalidate_page(page);
1164 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1165 assert(last<page+5);
1166 // Invalidate the adjacent pages if a block crosses a 4K boundary
1168 invalidate_page(first);
1171 for(first=page+1;first<last;first++) {
1172 invalidate_page(first);
1178 // Don't trap writes
1179 invalid_code[block]=1;
1181 // If there is a valid TLB entry for this page, remove write protect
1182 if(tlb_LUT_w[block]) {
1183 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1184 // CHECK: Is this right?
1185 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1186 u_int real_block=tlb_LUT_w[block]>>12;
1187 invalid_code[real_block]=1;
1188 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1190 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1194 memset(mini_ht,-1,sizeof(mini_ht));
1198 void invalidate_block(u_int block)
1200 u_int page=get_page(block<<12);
1201 u_int vpage=get_vpage(block<<12);
1202 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1203 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1206 struct ll_entry *head;
1207 head=jump_dirty[vpage];
1208 //printf("page=%d vpage=%d\n",page,vpage);
1211 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1212 get_bounds((int)head->addr,&start,&end);
1213 //printf("start: %x end: %x\n",start,end);
1214 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1215 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1216 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1217 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1221 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1222 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1223 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1224 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1231 invalidate_block_range(block,first,last);
1234 void invalidate_addr(u_int addr)
1238 // this check is done by the caller
1239 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1240 u_int page=get_vpage(addr);
1241 if(page<2048) { // RAM
1242 struct ll_entry *head;
1243 u_int addr_min=~0, addr_max=0;
1244 int mask=RAM_SIZE-1;
1246 inv_code_start=addr&~0xfff;
1247 inv_code_end=addr|0xfff;
1250 // must check previous page too because of spans..
1252 inv_code_start-=0x1000;
1254 for(;pg1<=page;pg1++) {
1255 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1257 get_bounds((int)head->addr,&start,&end);
1258 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1259 if(start<addr_min) addr_min=start;
1260 if(end>addr_max) addr_max=end;
1262 else if(addr<start) {
1263 if(start<inv_code_end)
1264 inv_code_end=start-1;
1267 if(end>inv_code_start)
1273 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1274 inv_code_start=inv_code_end=~0;
1275 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1279 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1284 invalidate_block(addr>>12);
1287 // This is called when loading a save state.
1288 // Anything could have changed, so invalidate everything.
1289 void invalidate_all_pages()
1292 for(page=0;page<4096;page++)
1293 invalidate_page(page);
1294 for(page=0;page<1048576;page++)
1295 if(!invalid_code[page]) {
1296 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1297 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1300 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1303 memset(mini_ht,-1,sizeof(mini_ht));
1307 for(page=0;page<0x100000;page++) {
1308 if(tlb_LUT_r[page]) {
1309 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1310 if(!tlb_LUT_w[page]||!invalid_code[page])
1311 memory_map[page]|=0x40000000; // Write protect
1313 else memory_map[page]=-1;
1314 if(page==0x80000) page=0xC0000;
1320 // Add an entry to jump_out after making a link
1321 void add_link(u_int vaddr,void *src)
1323 u_int page=get_page(vaddr);
1324 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1325 int *ptr=(int *)(src+4);
1326 assert((*ptr&0x0fff0000)==0x059f0000);
1327 ll_add(jump_out+page,vaddr,src);
1328 //int ptr=get_pointer(src);
1329 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1332 // If a code block was found to be unmodified (bit was set in
1333 // restore_candidate) and it remains unmodified (bit is clear
1334 // in invalid_code) then move the entries for that 4K page from
1335 // the dirty list to the clean list.
1336 void clean_blocks(u_int page)
1338 struct ll_entry *head;
1339 inv_debug("INV: clean_blocks page=%d\n",page);
1340 head=jump_dirty[page];
1342 if(!invalid_code[head->vaddr>>12]) {
1343 // Don't restore blocks which are about to expire from the cache
1344 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1346 if(verify_dirty((int)head->addr)) {
1347 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1350 get_bounds((int)head->addr,&start,&end);
1351 if(start-(u_int)rdram<RAM_SIZE) {
1352 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1353 inv|=invalid_code[i];
1357 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1358 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1359 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1360 if(addr<start||addr>=end) inv=1;
1363 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1367 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1368 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1371 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1373 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1374 //printf("page=%x, addr=%x\n",page,head->vaddr);
1375 //assert(head->vaddr>>12==(page|0x80000));
1376 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1377 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1379 if(ht_bin[0]==head->vaddr) {
1380 ht_bin[1]=(int)clean_addr; // Replace existing entry
1382 if(ht_bin[2]==head->vaddr) {
1383 ht_bin[3]=(int)clean_addr; // Replace existing entry
1396 void mov_alloc(struct regstat *current,int i)
1398 // Note: Don't need to actually alloc the source registers
1399 if((~current->is32>>rs1[i])&1) {
1400 //alloc_reg64(current,i,rs1[i]);
1401 alloc_reg64(current,i,rt1[i]);
1402 current->is32&=~(1LL<<rt1[i]);
1404 //alloc_reg(current,i,rs1[i]);
1405 alloc_reg(current,i,rt1[i]);
1406 current->is32|=(1LL<<rt1[i]);
1408 clear_const(current,rs1[i]);
1409 clear_const(current,rt1[i]);
1410 dirty_reg(current,rt1[i]);
1413 void shiftimm_alloc(struct regstat *current,int i)
1415 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1418 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1420 alloc_reg(current,i,rt1[i]);
1421 current->is32|=1LL<<rt1[i];
1422 dirty_reg(current,rt1[i]);
1423 if(is_const(current,rs1[i])) {
1424 int v=get_const(current,rs1[i]);
1425 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1426 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1427 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1429 else clear_const(current,rt1[i]);
1434 clear_const(current,rs1[i]);
1435 clear_const(current,rt1[i]);
1438 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1441 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1442 alloc_reg64(current,i,rt1[i]);
1443 current->is32&=~(1LL<<rt1[i]);
1444 dirty_reg(current,rt1[i]);
1447 if(opcode2[i]==0x3c) // DSLL32
1450 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1451 alloc_reg64(current,i,rt1[i]);
1452 current->is32&=~(1LL<<rt1[i]);
1453 dirty_reg(current,rt1[i]);
1456 if(opcode2[i]==0x3e) // DSRL32
1459 alloc_reg64(current,i,rs1[i]);
1461 alloc_reg64(current,i,rt1[i]);
1462 current->is32&=~(1LL<<rt1[i]);
1464 alloc_reg(current,i,rt1[i]);
1465 current->is32|=1LL<<rt1[i];
1467 dirty_reg(current,rt1[i]);
1470 if(opcode2[i]==0x3f) // DSRA32
1473 alloc_reg64(current,i,rs1[i]);
1474 alloc_reg(current,i,rt1[i]);
1475 current->is32|=1LL<<rt1[i];
1476 dirty_reg(current,rt1[i]);
1481 void shift_alloc(struct regstat *current,int i)
1484 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1486 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1487 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1488 alloc_reg(current,i,rt1[i]);
1489 if(rt1[i]==rs2[i]) {
1490 alloc_reg_temp(current,i,-1);
1491 minimum_free_regs[i]=1;
1493 current->is32|=1LL<<rt1[i];
1494 } else { // DSLLV/DSRLV/DSRAV
1495 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1496 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1497 alloc_reg64(current,i,rt1[i]);
1498 current->is32&=~(1LL<<rt1[i]);
1499 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1501 alloc_reg_temp(current,i,-1);
1502 minimum_free_regs[i]=1;
1505 clear_const(current,rs1[i]);
1506 clear_const(current,rs2[i]);
1507 clear_const(current,rt1[i]);
1508 dirty_reg(current,rt1[i]);
1512 void alu_alloc(struct regstat *current,int i)
1514 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1516 if(rs1[i]&&rs2[i]) {
1517 alloc_reg(current,i,rs1[i]);
1518 alloc_reg(current,i,rs2[i]);
1521 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1522 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1524 alloc_reg(current,i,rt1[i]);
1526 current->is32|=1LL<<rt1[i];
1528 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1530 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1532 alloc_reg64(current,i,rs1[i]);
1533 alloc_reg64(current,i,rs2[i]);
1534 alloc_reg(current,i,rt1[i]);
1536 alloc_reg(current,i,rs1[i]);
1537 alloc_reg(current,i,rs2[i]);
1538 alloc_reg(current,i,rt1[i]);
1541 current->is32|=1LL<<rt1[i];
1543 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1545 if(rs1[i]&&rs2[i]) {
1546 alloc_reg(current,i,rs1[i]);
1547 alloc_reg(current,i,rs2[i]);
1551 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1552 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1554 alloc_reg(current,i,rt1[i]);
1555 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1557 if(!((current->uu>>rt1[i])&1)) {
1558 alloc_reg64(current,i,rt1[i]);
1560 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1561 if(rs1[i]&&rs2[i]) {
1562 alloc_reg64(current,i,rs1[i]);
1563 alloc_reg64(current,i,rs2[i]);
1567 // Is is really worth it to keep 64-bit values in registers?
1569 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1570 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1574 current->is32&=~(1LL<<rt1[i]);
1576 current->is32|=1LL<<rt1[i];
1580 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1582 if(rs1[i]&&rs2[i]) {
1583 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1584 alloc_reg64(current,i,rs1[i]);
1585 alloc_reg64(current,i,rs2[i]);
1586 alloc_reg64(current,i,rt1[i]);
1588 alloc_reg(current,i,rs1[i]);
1589 alloc_reg(current,i,rs2[i]);
1590 alloc_reg(current,i,rt1[i]);
1594 alloc_reg(current,i,rt1[i]);
1595 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1596 // DADD used as move, or zeroing
1597 // If we have a 64-bit source, then make the target 64 bits too
1598 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1599 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1600 alloc_reg64(current,i,rt1[i]);
1601 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1602 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1603 alloc_reg64(current,i,rt1[i]);
1605 if(opcode2[i]>=0x2e&&rs2[i]) {
1606 // DSUB used as negation - 64-bit result
1607 // If we have a 32-bit register, extend it to 64 bits
1608 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1609 alloc_reg64(current,i,rt1[i]);
1613 if(rs1[i]&&rs2[i]) {
1614 current->is32&=~(1LL<<rt1[i]);
1616 current->is32&=~(1LL<<rt1[i]);
1617 if((current->is32>>rs1[i])&1)
1618 current->is32|=1LL<<rt1[i];
1620 current->is32&=~(1LL<<rt1[i]);
1621 if((current->is32>>rs2[i])&1)
1622 current->is32|=1LL<<rt1[i];
1624 current->is32|=1LL<<rt1[i];
1628 clear_const(current,rs1[i]);
1629 clear_const(current,rs2[i]);
1630 clear_const(current,rt1[i]);
1631 dirty_reg(current,rt1[i]);
1634 void imm16_alloc(struct regstat *current,int i)
1636 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1638 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1639 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1640 current->is32&=~(1LL<<rt1[i]);
1641 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1642 // TODO: Could preserve the 32-bit flag if the immediate is zero
1643 alloc_reg64(current,i,rt1[i]);
1644 alloc_reg64(current,i,rs1[i]);
1646 clear_const(current,rs1[i]);
1647 clear_const(current,rt1[i]);
1649 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1650 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1651 current->is32|=1LL<<rt1[i];
1652 clear_const(current,rs1[i]);
1653 clear_const(current,rt1[i]);
1655 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1656 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1657 if(rs1[i]!=rt1[i]) {
1658 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1659 alloc_reg64(current,i,rt1[i]);
1660 current->is32&=~(1LL<<rt1[i]);
1663 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1664 if(is_const(current,rs1[i])) {
1665 int v=get_const(current,rs1[i]);
1666 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1667 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1668 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1670 else clear_const(current,rt1[i]);
1672 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1673 if(is_const(current,rs1[i])) {
1674 int v=get_const(current,rs1[i]);
1675 set_const(current,rt1[i],v+imm[i]);
1677 else clear_const(current,rt1[i]);
1678 current->is32|=1LL<<rt1[i];
1681 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1682 current->is32|=1LL<<rt1[i];
1684 dirty_reg(current,rt1[i]);
1687 void load_alloc(struct regstat *current,int i)
1689 clear_const(current,rt1[i]);
1690 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1691 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1692 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1693 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1694 alloc_reg(current,i,rt1[i]);
1695 assert(get_reg(current->regmap,rt1[i])>=0);
1696 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1698 current->is32&=~(1LL<<rt1[i]);
1699 alloc_reg64(current,i,rt1[i]);
1701 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1703 current->is32&=~(1LL<<rt1[i]);
1704 alloc_reg64(current,i,rt1[i]);
1705 alloc_all(current,i);
1706 alloc_reg64(current,i,FTEMP);
1707 minimum_free_regs[i]=HOST_REGS;
1709 else current->is32|=1LL<<rt1[i];
1710 dirty_reg(current,rt1[i]);
1711 // If using TLB, need a register for pointer to the mapping table
1712 if(using_tlb) alloc_reg(current,i,TLREG);
1713 // LWL/LWR need a temporary register for the old value
1714 if(opcode[i]==0x22||opcode[i]==0x26)
1716 alloc_reg(current,i,FTEMP);
1717 alloc_reg_temp(current,i,-1);
1718 minimum_free_regs[i]=1;
1723 // Load to r0 or unneeded register (dummy load)
1724 // but we still need a register to calculate the address
1725 if(opcode[i]==0x22||opcode[i]==0x26)
1727 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1729 // If using TLB, need a register for pointer to the mapping table
1730 if(using_tlb) alloc_reg(current,i,TLREG);
1731 alloc_reg_temp(current,i,-1);
1732 minimum_free_regs[i]=1;
1733 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1735 alloc_all(current,i);
1736 alloc_reg64(current,i,FTEMP);
1737 minimum_free_regs[i]=HOST_REGS;
1742 void store_alloc(struct regstat *current,int i)
1744 clear_const(current,rs2[i]);
1745 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1746 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1747 alloc_reg(current,i,rs2[i]);
1748 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1749 alloc_reg64(current,i,rs2[i]);
1750 if(rs2[i]) alloc_reg(current,i,FTEMP);
1752 // If using TLB, need a register for pointer to the mapping table
1753 if(using_tlb) alloc_reg(current,i,TLREG);
1754 #if defined(HOST_IMM8)
1755 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1756 else alloc_reg(current,i,INVCP);
1758 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1759 alloc_reg(current,i,FTEMP);
1761 // We need a temporary register for address generation
1762 alloc_reg_temp(current,i,-1);
1763 minimum_free_regs[i]=1;
1766 void c1ls_alloc(struct regstat *current,int i)
1768 //clear_const(current,rs1[i]); // FIXME
1769 clear_const(current,rt1[i]);
1770 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1771 alloc_reg(current,i,CSREG); // Status
1772 alloc_reg(current,i,FTEMP);
1773 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1774 alloc_reg64(current,i,FTEMP);
1776 // If using TLB, need a register for pointer to the mapping table
1777 if(using_tlb) alloc_reg(current,i,TLREG);
1778 #if defined(HOST_IMM8)
1779 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1780 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1781 alloc_reg(current,i,INVCP);
1783 // We need a temporary register for address generation
1784 alloc_reg_temp(current,i,-1);
1787 void c2ls_alloc(struct regstat *current,int i)
1789 clear_const(current,rt1[i]);
1790 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1791 alloc_reg(current,i,FTEMP);
1792 // If using TLB, need a register for pointer to the mapping table
1793 if(using_tlb) alloc_reg(current,i,TLREG);
1794 #if defined(HOST_IMM8)
1795 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1796 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1797 alloc_reg(current,i,INVCP);
1799 // We need a temporary register for address generation
1800 alloc_reg_temp(current,i,-1);
1801 minimum_free_regs[i]=1;
1804 #ifndef multdiv_alloc
1805 void multdiv_alloc(struct regstat *current,int i)
1812 // case 0x1D: DMULTU
1815 clear_const(current,rs1[i]);
1816 clear_const(current,rs2[i]);
1819 if((opcode2[i]&4)==0) // 32-bit
1821 current->u&=~(1LL<<HIREG);
1822 current->u&=~(1LL<<LOREG);
1823 alloc_reg(current,i,HIREG);
1824 alloc_reg(current,i,LOREG);
1825 alloc_reg(current,i,rs1[i]);
1826 alloc_reg(current,i,rs2[i]);
1827 current->is32|=1LL<<HIREG;
1828 current->is32|=1LL<<LOREG;
1829 dirty_reg(current,HIREG);
1830 dirty_reg(current,LOREG);
1834 current->u&=~(1LL<<HIREG);
1835 current->u&=~(1LL<<LOREG);
1836 current->uu&=~(1LL<<HIREG);
1837 current->uu&=~(1LL<<LOREG);
1838 alloc_reg64(current,i,HIREG);
1839 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1840 alloc_reg64(current,i,rs1[i]);
1841 alloc_reg64(current,i,rs2[i]);
1842 alloc_all(current,i);
1843 current->is32&=~(1LL<<HIREG);
1844 current->is32&=~(1LL<<LOREG);
1845 dirty_reg(current,HIREG);
1846 dirty_reg(current,LOREG);
1847 minimum_free_regs[i]=HOST_REGS;
1852 // Multiply by zero is zero.
1853 // MIPS does not have a divide by zero exception.
1854 // The result is undefined, we return zero.
1855 alloc_reg(current,i,HIREG);
1856 alloc_reg(current,i,LOREG);
1857 current->is32|=1LL<<HIREG;
1858 current->is32|=1LL<<LOREG;
1859 dirty_reg(current,HIREG);
1860 dirty_reg(current,LOREG);
1865 void cop0_alloc(struct regstat *current,int i)
1867 if(opcode2[i]==0) // MFC0
1870 clear_const(current,rt1[i]);
1871 alloc_all(current,i);
1872 alloc_reg(current,i,rt1[i]);
1873 current->is32|=1LL<<rt1[i];
1874 dirty_reg(current,rt1[i]);
1877 else if(opcode2[i]==4) // MTC0
1880 clear_const(current,rs1[i]);
1881 alloc_reg(current,i,rs1[i]);
1882 alloc_all(current,i);
1885 alloc_all(current,i); // FIXME: Keep r0
1887 alloc_reg(current,i,0);
1892 // TLBR/TLBWI/TLBWR/TLBP/ERET
1893 assert(opcode2[i]==0x10);
1894 alloc_all(current,i);
1896 minimum_free_regs[i]=HOST_REGS;
1899 void cop1_alloc(struct regstat *current,int i)
1901 alloc_reg(current,i,CSREG); // Load status
1902 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1905 clear_const(current,rt1[i]);
1907 alloc_reg64(current,i,rt1[i]); // DMFC1
1908 current->is32&=~(1LL<<rt1[i]);
1910 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1911 current->is32|=1LL<<rt1[i];
1913 dirty_reg(current,rt1[i]);
1915 alloc_reg_temp(current,i,-1);
1917 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1920 clear_const(current,rs1[i]);
1922 alloc_reg64(current,i,rs1[i]); // DMTC1
1924 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1925 alloc_reg_temp(current,i,-1);
1929 alloc_reg(current,i,0);
1930 alloc_reg_temp(current,i,-1);
1933 minimum_free_regs[i]=1;
1935 void fconv_alloc(struct regstat *current,int i)
1937 alloc_reg(current,i,CSREG); // Load status
1938 alloc_reg_temp(current,i,-1);
1939 minimum_free_regs[i]=1;
1941 void float_alloc(struct regstat *current,int i)
1943 alloc_reg(current,i,CSREG); // Load status
1944 alloc_reg_temp(current,i,-1);
1945 minimum_free_regs[i]=1;
1947 void c2op_alloc(struct regstat *current,int i)
1949 alloc_reg_temp(current,i,-1);
1951 void fcomp_alloc(struct regstat *current,int i)
1953 alloc_reg(current,i,CSREG); // Load status
1954 alloc_reg(current,i,FSREG); // Load flags
1955 dirty_reg(current,FSREG); // Flag will be modified
1956 alloc_reg_temp(current,i,-1);
1957 minimum_free_regs[i]=1;
1960 void syscall_alloc(struct regstat *current,int i)
1962 alloc_cc(current,i);
1963 dirty_reg(current,CCREG);
1964 alloc_all(current,i);
1965 minimum_free_regs[i]=HOST_REGS;
1969 void delayslot_alloc(struct regstat *current,int i)
1980 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1981 printf("Disabled speculative precompilation\n");
1985 imm16_alloc(current,i);
1989 load_alloc(current,i);
1993 store_alloc(current,i);
1996 alu_alloc(current,i);
1999 shift_alloc(current,i);
2002 multdiv_alloc(current,i);
2005 shiftimm_alloc(current,i);
2008 mov_alloc(current,i);
2011 cop0_alloc(current,i);
2015 cop1_alloc(current,i);
2018 c1ls_alloc(current,i);
2021 c2ls_alloc(current,i);
2024 fconv_alloc(current,i);
2027 float_alloc(current,i);
2030 fcomp_alloc(current,i);
2033 c2op_alloc(current,i);
2038 // Special case where a branch and delay slot span two pages in virtual memory
2039 static void pagespan_alloc(struct regstat *current,int i)
2042 current->wasconst=0;
2044 minimum_free_regs[i]=HOST_REGS;
2045 alloc_all(current,i);
2046 alloc_cc(current,i);
2047 dirty_reg(current,CCREG);
2048 if(opcode[i]==3) // JAL
2050 alloc_reg(current,i,31);
2051 dirty_reg(current,31);
2053 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2055 alloc_reg(current,i,rs1[i]);
2057 alloc_reg(current,i,rt1[i]);
2058 dirty_reg(current,rt1[i]);
2061 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2063 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2064 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2065 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2067 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2068 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2072 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2074 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2075 if(!((current->is32>>rs1[i])&1))
2077 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2081 if(opcode[i]==0x11) // BC1
2083 alloc_reg(current,i,FSREG);
2084 alloc_reg(current,i,CSREG);
2089 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2091 stubs[stubcount][0]=type;
2092 stubs[stubcount][1]=addr;
2093 stubs[stubcount][2]=retaddr;
2094 stubs[stubcount][3]=a;
2095 stubs[stubcount][4]=b;
2096 stubs[stubcount][5]=c;
2097 stubs[stubcount][6]=d;
2098 stubs[stubcount][7]=e;
2102 // Write out a single register
2103 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2106 for(hr=0;hr<HOST_REGS;hr++) {
2107 if(hr!=EXCLUDE_REG) {
2108 if((regmap[hr]&63)==r) {
2111 emit_storereg(r,hr);
2113 if((is32>>regmap[hr])&1) {
2114 emit_sarimm(hr,31,hr);
2115 emit_storereg(r|64,hr);
2119 emit_storereg(r|64,hr);
2129 //if(!tracedebug) return 0;
2132 for(i=0;i<2097152;i++) {
2133 unsigned int temp=sum;
2136 sum^=((u_int *)rdram)[i];
2145 sum^=((u_int *)reg)[i];
2153 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2155 #ifndef DISABLE_COP1
2158 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2168 void memdebug(int i)
2170 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2171 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2174 //if(Count>=-2084597794) {
2175 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2177 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2178 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2179 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2182 printf("TRACE: %x\n",(&i)[-1]);
2186 printf("TRACE: %x \n",(&j)[10]);
2187 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2191 //printf("TRACE: %x\n",(&i)[-1]);
2194 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2196 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2199 void alu_assemble(int i,struct regstat *i_regs)
2201 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2203 signed char s1,s2,t;
2204 t=get_reg(i_regs->regmap,rt1[i]);
2206 s1=get_reg(i_regs->regmap,rs1[i]);
2207 s2=get_reg(i_regs->regmap,rs2[i]);
2208 if(rs1[i]&&rs2[i]) {
2211 if(opcode2[i]&2) emit_sub(s1,s2,t);
2212 else emit_add(s1,s2,t);
2215 if(s1>=0) emit_mov(s1,t);
2216 else emit_loadreg(rs1[i],t);
2220 if(opcode2[i]&2) emit_neg(s2,t);
2221 else emit_mov(s2,t);
2224 emit_loadreg(rs2[i],t);
2225 if(opcode2[i]&2) emit_neg(t,t);
2228 else emit_zeroreg(t);
2232 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2234 signed char s1l,s2l,s1h,s2h,tl,th;
2235 tl=get_reg(i_regs->regmap,rt1[i]);
2236 th=get_reg(i_regs->regmap,rt1[i]|64);
2238 s1l=get_reg(i_regs->regmap,rs1[i]);
2239 s2l=get_reg(i_regs->regmap,rs2[i]);
2240 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2241 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2242 if(rs1[i]&&rs2[i]) {
2245 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2246 else emit_adds(s1l,s2l,tl);
2248 #ifdef INVERTED_CARRY
2249 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2251 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2253 else emit_add(s1h,s2h,th);
2257 if(s1l>=0) emit_mov(s1l,tl);
2258 else emit_loadreg(rs1[i],tl);
2260 if(s1h>=0) emit_mov(s1h,th);
2261 else emit_loadreg(rs1[i]|64,th);
2266 if(opcode2[i]&2) emit_negs(s2l,tl);
2267 else emit_mov(s2l,tl);
2270 emit_loadreg(rs2[i],tl);
2271 if(opcode2[i]&2) emit_negs(tl,tl);
2274 #ifdef INVERTED_CARRY
2275 if(s2h>=0) emit_mov(s2h,th);
2276 else emit_loadreg(rs2[i]|64,th);
2278 emit_adcimm(-1,th); // x86 has inverted carry flag
2283 if(s2h>=0) emit_rscimm(s2h,0,th);
2285 emit_loadreg(rs2[i]|64,th);
2286 emit_rscimm(th,0,th);
2289 if(s2h>=0) emit_mov(s2h,th);
2290 else emit_loadreg(rs2[i]|64,th);
2297 if(th>=0) emit_zeroreg(th);
2302 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2304 signed char s1l,s1h,s2l,s2h,t;
2305 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2307 t=get_reg(i_regs->regmap,rt1[i]);
2310 s1l=get_reg(i_regs->regmap,rs1[i]);
2311 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2312 s2l=get_reg(i_regs->regmap,rs2[i]);
2313 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2314 if(rs2[i]==0) // rx<r0
2317 if(opcode2[i]==0x2a) // SLT
2318 emit_shrimm(s1h,31,t);
2319 else // SLTU (unsigned can not be less than zero)
2322 else if(rs1[i]==0) // r0<rx
2325 if(opcode2[i]==0x2a) // SLT
2326 emit_set_gz64_32(s2h,s2l,t);
2327 else // SLTU (set if not zero)
2328 emit_set_nz64_32(s2h,s2l,t);
2331 assert(s1l>=0);assert(s1h>=0);
2332 assert(s2l>=0);assert(s2h>=0);
2333 if(opcode2[i]==0x2a) // SLT
2334 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2336 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2340 t=get_reg(i_regs->regmap,rt1[i]);
2343 s1l=get_reg(i_regs->regmap,rs1[i]);
2344 s2l=get_reg(i_regs->regmap,rs2[i]);
2345 if(rs2[i]==0) // rx<r0
2348 if(opcode2[i]==0x2a) // SLT
2349 emit_shrimm(s1l,31,t);
2350 else // SLTU (unsigned can not be less than zero)
2353 else if(rs1[i]==0) // r0<rx
2356 if(opcode2[i]==0x2a) // SLT
2357 emit_set_gz32(s2l,t);
2358 else // SLTU (set if not zero)
2359 emit_set_nz32(s2l,t);
2362 assert(s1l>=0);assert(s2l>=0);
2363 if(opcode2[i]==0x2a) // SLT
2364 emit_set_if_less32(s1l,s2l,t);
2366 emit_set_if_carry32(s1l,s2l,t);
2372 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2374 signed char s1l,s1h,s2l,s2h,th,tl;
2375 tl=get_reg(i_regs->regmap,rt1[i]);
2376 th=get_reg(i_regs->regmap,rt1[i]|64);
2377 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2381 s1l=get_reg(i_regs->regmap,rs1[i]);
2382 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2383 s2l=get_reg(i_regs->regmap,rs2[i]);
2384 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2385 if(rs1[i]&&rs2[i]) {
2386 assert(s1l>=0);assert(s1h>=0);
2387 assert(s2l>=0);assert(s2h>=0);
2388 if(opcode2[i]==0x24) { // AND
2389 emit_and(s1l,s2l,tl);
2390 emit_and(s1h,s2h,th);
2392 if(opcode2[i]==0x25) { // OR
2393 emit_or(s1l,s2l,tl);
2394 emit_or(s1h,s2h,th);
2396 if(opcode2[i]==0x26) { // XOR
2397 emit_xor(s1l,s2l,tl);
2398 emit_xor(s1h,s2h,th);
2400 if(opcode2[i]==0x27) { // NOR
2401 emit_or(s1l,s2l,tl);
2402 emit_or(s1h,s2h,th);
2409 if(opcode2[i]==0x24) { // AND
2413 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2415 if(s1l>=0) emit_mov(s1l,tl);
2416 else emit_loadreg(rs1[i],tl);
2417 if(s1h>=0) emit_mov(s1h,th);
2418 else emit_loadreg(rs1[i]|64,th);
2422 if(s2l>=0) emit_mov(s2l,tl);
2423 else emit_loadreg(rs2[i],tl);
2424 if(s2h>=0) emit_mov(s2h,th);
2425 else emit_loadreg(rs2[i]|64,th);
2432 if(opcode2[i]==0x27) { // NOR
2434 if(s1l>=0) emit_not(s1l,tl);
2436 emit_loadreg(rs1[i],tl);
2439 if(s1h>=0) emit_not(s1h,th);
2441 emit_loadreg(rs1[i]|64,th);
2447 if(s2l>=0) emit_not(s2l,tl);
2449 emit_loadreg(rs2[i],tl);
2452 if(s2h>=0) emit_not(s2h,th);
2454 emit_loadreg(rs2[i]|64,th);
2470 s1l=get_reg(i_regs->regmap,rs1[i]);
2471 s2l=get_reg(i_regs->regmap,rs2[i]);
2472 if(rs1[i]&&rs2[i]) {
2475 if(opcode2[i]==0x24) { // AND
2476 emit_and(s1l,s2l,tl);
2478 if(opcode2[i]==0x25) { // OR
2479 emit_or(s1l,s2l,tl);
2481 if(opcode2[i]==0x26) { // XOR
2482 emit_xor(s1l,s2l,tl);
2484 if(opcode2[i]==0x27) { // NOR
2485 emit_or(s1l,s2l,tl);
2491 if(opcode2[i]==0x24) { // AND
2494 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2496 if(s1l>=0) emit_mov(s1l,tl);
2497 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2501 if(s2l>=0) emit_mov(s2l,tl);
2502 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2504 else emit_zeroreg(tl);
2506 if(opcode2[i]==0x27) { // NOR
2508 if(s1l>=0) emit_not(s1l,tl);
2510 emit_loadreg(rs1[i],tl);
2516 if(s2l>=0) emit_not(s2l,tl);
2518 emit_loadreg(rs2[i],tl);
2522 else emit_movimm(-1,tl);
2531 void imm16_assemble(int i,struct regstat *i_regs)
2533 if (opcode[i]==0x0f) { // LUI
2536 t=get_reg(i_regs->regmap,rt1[i]);
2539 if(!((i_regs->isconst>>t)&1))
2540 emit_movimm(imm[i]<<16,t);
2544 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2547 t=get_reg(i_regs->regmap,rt1[i]);
2548 s=get_reg(i_regs->regmap,rs1[i]);
2553 if(!((i_regs->isconst>>t)&1)) {
2555 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2556 emit_addimm(t,imm[i],t);
2558 if(!((i_regs->wasconst>>s)&1))
2559 emit_addimm(s,imm[i],t);
2561 emit_movimm(constmap[i][s]+imm[i],t);
2567 if(!((i_regs->isconst>>t)&1))
2568 emit_movimm(imm[i],t);
2573 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2575 signed char sh,sl,th,tl;
2576 th=get_reg(i_regs->regmap,rt1[i]|64);
2577 tl=get_reg(i_regs->regmap,rt1[i]);
2578 sh=get_reg(i_regs->regmap,rs1[i]|64);
2579 sl=get_reg(i_regs->regmap,rs1[i]);
2585 emit_addimm64_32(sh,sl,imm[i],th,tl);
2588 emit_addimm(sl,imm[i],tl);
2591 emit_movimm(imm[i],tl);
2592 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2597 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2599 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2600 signed char sh,sl,t;
2601 t=get_reg(i_regs->regmap,rt1[i]);
2602 sh=get_reg(i_regs->regmap,rs1[i]|64);
2603 sl=get_reg(i_regs->regmap,rs1[i]);
2607 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2608 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2609 if(opcode[i]==0x0a) { // SLTI
2611 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2612 emit_slti32(t,imm[i],t);
2614 emit_slti32(sl,imm[i],t);
2619 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2620 emit_sltiu32(t,imm[i],t);
2622 emit_sltiu32(sl,imm[i],t);
2627 if(opcode[i]==0x0a) // SLTI
2628 emit_slti64_32(sh,sl,imm[i],t);
2630 emit_sltiu64_32(sh,sl,imm[i],t);
2633 // SLTI(U) with r0 is just stupid,
2634 // nonetheless examples can be found
2635 if(opcode[i]==0x0a) // SLTI
2636 if(0<imm[i]) emit_movimm(1,t);
2637 else emit_zeroreg(t);
2640 if(imm[i]) emit_movimm(1,t);
2641 else emit_zeroreg(t);
2647 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2649 signed char sh,sl,th,tl;
2650 th=get_reg(i_regs->regmap,rt1[i]|64);
2651 tl=get_reg(i_regs->regmap,rt1[i]);
2652 sh=get_reg(i_regs->regmap,rs1[i]|64);
2653 sl=get_reg(i_regs->regmap,rs1[i]);
2654 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2655 if(opcode[i]==0x0c) //ANDI
2659 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2660 emit_andimm(tl,imm[i],tl);
2662 if(!((i_regs->wasconst>>sl)&1))
2663 emit_andimm(sl,imm[i],tl);
2665 emit_movimm(constmap[i][sl]&imm[i],tl);
2670 if(th>=0) emit_zeroreg(th);
2676 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2680 emit_loadreg(rs1[i]|64,th);
2685 if(opcode[i]==0x0d) //ORI
2687 emit_orimm(tl,imm[i],tl);
2689 if(!((i_regs->wasconst>>sl)&1))
2690 emit_orimm(sl,imm[i],tl);
2692 emit_movimm(constmap[i][sl]|imm[i],tl);
2694 if(opcode[i]==0x0e) //XORI
2696 emit_xorimm(tl,imm[i],tl);
2698 if(!((i_regs->wasconst>>sl)&1))
2699 emit_xorimm(sl,imm[i],tl);
2701 emit_movimm(constmap[i][sl]^imm[i],tl);
2705 emit_movimm(imm[i],tl);
2706 if(th>=0) emit_zeroreg(th);
2714 void shiftimm_assemble(int i,struct regstat *i_regs)
2716 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2720 t=get_reg(i_regs->regmap,rt1[i]);
2721 s=get_reg(i_regs->regmap,rs1[i]);
2723 if(t>=0&&!((i_regs->isconst>>t)&1)){
2730 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2732 if(opcode2[i]==0) // SLL
2734 emit_shlimm(s<0?t:s,imm[i],t);
2736 if(opcode2[i]==2) // SRL
2738 emit_shrimm(s<0?t:s,imm[i],t);
2740 if(opcode2[i]==3) // SRA
2742 emit_sarimm(s<0?t:s,imm[i],t);
2746 if(s>=0 && s!=t) emit_mov(s,t);
2750 //emit_storereg(rt1[i],t); //DEBUG
2753 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2756 signed char sh,sl,th,tl;
2757 th=get_reg(i_regs->regmap,rt1[i]|64);
2758 tl=get_reg(i_regs->regmap,rt1[i]);
2759 sh=get_reg(i_regs->regmap,rs1[i]|64);
2760 sl=get_reg(i_regs->regmap,rs1[i]);
2765 if(th>=0) emit_zeroreg(th);
2772 if(opcode2[i]==0x38) // DSLL
2774 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2775 emit_shlimm(sl,imm[i],tl);
2777 if(opcode2[i]==0x3a) // DSRL
2779 emit_shrdimm(sl,sh,imm[i],tl);
2780 if(th>=0) emit_shrimm(sh,imm[i],th);
2782 if(opcode2[i]==0x3b) // DSRA
2784 emit_shrdimm(sl,sh,imm[i],tl);
2785 if(th>=0) emit_sarimm(sh,imm[i],th);
2789 if(sl!=tl) emit_mov(sl,tl);
2790 if(th>=0&&sh!=th) emit_mov(sh,th);
2796 if(opcode2[i]==0x3c) // DSLL32
2799 signed char sl,tl,th;
2800 tl=get_reg(i_regs->regmap,rt1[i]);
2801 th=get_reg(i_regs->regmap,rt1[i]|64);
2802 sl=get_reg(i_regs->regmap,rs1[i]);
2811 emit_shlimm(th,imm[i]&31,th);
2816 if(opcode2[i]==0x3e) // DSRL32
2819 signed char sh,tl,th;
2820 tl=get_reg(i_regs->regmap,rt1[i]);
2821 th=get_reg(i_regs->regmap,rt1[i]|64);
2822 sh=get_reg(i_regs->regmap,rs1[i]|64);
2826 if(th>=0) emit_zeroreg(th);
2829 emit_shrimm(tl,imm[i]&31,tl);
2834 if(opcode2[i]==0x3f) // DSRA32
2838 tl=get_reg(i_regs->regmap,rt1[i]);
2839 sh=get_reg(i_regs->regmap,rs1[i]|64);
2845 emit_sarimm(tl,imm[i]&31,tl);
2852 #ifndef shift_assemble
2853 void shift_assemble(int i,struct regstat *i_regs)
2855 printf("Need shift_assemble for this architecture.\n");
2860 void load_assemble(int i,struct regstat *i_regs)
2862 int s,th,tl,addr,map=-1;
2865 int memtarget=0,c=0;
2866 int fastload_reg_override=0;
2868 th=get_reg(i_regs->regmap,rt1[i]|64);
2869 tl=get_reg(i_regs->regmap,rt1[i]);
2870 s=get_reg(i_regs->regmap,rs1[i]);
2872 for(hr=0;hr<HOST_REGS;hr++) {
2873 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2875 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2877 c=(i_regs->wasconst>>s)&1;
2879 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2880 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2883 //printf("load_assemble: c=%d\n",c);
2884 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2885 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2887 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2889 // could be FIFO, must perform the read
2891 assem_debug("(forced read)\n");
2892 tl=get_reg(i_regs->regmap,-1);
2896 if(offset||s<0||c) addr=tl;
2898 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2900 //printf("load_assemble: c=%d\n",c);
2901 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2902 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2904 if(th>=0) reglist&=~(1<<th);
2908 map=get_reg(i_regs->regmap,ROREG);
2909 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2911 //#define R29_HACK 1
2913 // Strmnnrmn's speed hack
2914 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2917 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2922 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2923 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2924 map=get_reg(i_regs->regmap,TLREG);
2927 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2928 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2930 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2931 if (opcode[i]==0x20) { // LB
2934 #ifdef HOST_IMM_ADDR32
2936 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2940 //emit_xorimm(addr,3,tl);
2941 //gen_tlb_addr_r(tl,map);
2942 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2944 #ifdef BIG_ENDIAN_MIPS
2945 if(!c) emit_xorimm(addr,3,tl);
2946 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2950 if(fastload_reg_override) a=fastload_reg_override;
2952 emit_movsbl_indexed_tlb(x,a,map,tl);
2956 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2959 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2961 if (opcode[i]==0x21) { // LH
2964 #ifdef HOST_IMM_ADDR32
2966 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2971 #ifdef BIG_ENDIAN_MIPS
2972 if(!c) emit_xorimm(addr,2,tl);
2973 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2977 if(fastload_reg_override) a=fastload_reg_override;
2979 //emit_movswl_indexed_tlb(x,tl,map,tl);
2982 gen_tlb_addr_r(a,map);
2983 emit_movswl_indexed(x,a,tl);
2986 emit_movswl_indexed(x,a,tl);
2988 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2994 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2997 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2999 if (opcode[i]==0x23) { // LW
3003 if(fastload_reg_override) a=fastload_reg_override;
3004 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3005 #ifdef HOST_IMM_ADDR32
3007 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3010 emit_readword_indexed_tlb(0,a,map,tl);
3013 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3016 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3018 if (opcode[i]==0x24) { // LBU
3021 #ifdef HOST_IMM_ADDR32
3023 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3027 //emit_xorimm(addr,3,tl);
3028 //gen_tlb_addr_r(tl,map);
3029 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3031 #ifdef BIG_ENDIAN_MIPS
3032 if(!c) emit_xorimm(addr,3,tl);
3033 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3037 if(fastload_reg_override) a=fastload_reg_override;
3039 emit_movzbl_indexed_tlb(x,a,map,tl);
3043 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3046 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3048 if (opcode[i]==0x25) { // LHU
3051 #ifdef HOST_IMM_ADDR32
3053 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3058 #ifdef BIG_ENDIAN_MIPS
3059 if(!c) emit_xorimm(addr,2,tl);
3060 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3064 if(fastload_reg_override) a=fastload_reg_override;
3066 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3069 gen_tlb_addr_r(a,map);
3070 emit_movzwl_indexed(x,a,tl);
3073 emit_movzwl_indexed(x,a,tl);
3075 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3081 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3084 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3086 if (opcode[i]==0x27) { // LWU
3091 if(fastload_reg_override) a=fastload_reg_override;
3092 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3093 #ifdef HOST_IMM_ADDR32
3095 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3098 emit_readword_indexed_tlb(0,a,map,tl);
3101 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3104 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3108 if (opcode[i]==0x37) { // LD
3112 if(fastload_reg_override) a=fastload_reg_override;
3113 //gen_tlb_addr_r(tl,map);
3114 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3115 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3116 #ifdef HOST_IMM_ADDR32
3118 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3121 emit_readdword_indexed_tlb(0,a,map,th,tl);
3124 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3127 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3130 //emit_storereg(rt1[i],tl); // DEBUG
3131 //if(opcode[i]==0x23)
3132 //if(opcode[i]==0x24)
3133 //if(opcode[i]==0x23||opcode[i]==0x24)
3134 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3138 emit_readword((int)&last_count,ECX);
3140 if(get_reg(i_regs->regmap,CCREG)<0)
3141 emit_loadreg(CCREG,HOST_CCREG);
3142 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3143 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3144 emit_writeword(HOST_CCREG,(int)&Count);
3147 if(get_reg(i_regs->regmap,CCREG)<0)
3148 emit_loadreg(CCREG,0);
3150 emit_mov(HOST_CCREG,0);
3152 emit_addimm(0,2*ccadj[i],0);
3153 emit_writeword(0,(int)&Count);
3155 emit_call((int)memdebug);
3157 restore_regs(0x100f);
3161 #ifndef loadlr_assemble
3162 void loadlr_assemble(int i,struct regstat *i_regs)
3164 printf("Need loadlr_assemble for this architecture.\n");
3169 void store_assemble(int i,struct regstat *i_regs)
3174 int jaddr=0,jaddr2,type;
3175 int memtarget=0,c=0;
3176 int agr=AGEN1+(i&1);
3177 int faststore_reg_override=0;
3179 th=get_reg(i_regs->regmap,rs2[i]|64);
3180 tl=get_reg(i_regs->regmap,rs2[i]);
3181 s=get_reg(i_regs->regmap,rs1[i]);
3182 temp=get_reg(i_regs->regmap,agr);
3183 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3186 c=(i_regs->wasconst>>s)&1;
3188 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3189 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3194 for(hr=0;hr<HOST_REGS;hr++) {
3195 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3197 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3198 if(offset||s<0||c) addr=temp;
3204 // Strmnnrmn's speed hack
3205 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3207 emit_cmpimm(addr,RAM_SIZE);
3208 #ifdef DESTRUCTIVE_SHIFT
3209 if(s==addr) emit_mov(s,temp);
3213 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3217 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3218 // Hint to branch predictor that the branch is unlikely to be taken
3220 emit_jno_unlikely(0);
3226 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3231 if (opcode[i]==0x28) x=3; // SB
3232 if (opcode[i]==0x29) x=2; // SH
3233 map=get_reg(i_regs->regmap,TLREG);
3236 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3237 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3240 if (opcode[i]==0x28) { // SB
3243 #ifdef BIG_ENDIAN_MIPS
3244 if(!c) emit_xorimm(addr,3,temp);
3245 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3249 if(faststore_reg_override) a=faststore_reg_override;
3250 //gen_tlb_addr_w(temp,map);
3251 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3252 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3256 if (opcode[i]==0x29) { // SH
3259 #ifdef BIG_ENDIAN_MIPS
3260 if(!c) emit_xorimm(addr,2,temp);
3261 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3265 if(faststore_reg_override) a=faststore_reg_override;
3267 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3270 gen_tlb_addr_w(a,map);
3271 emit_writehword_indexed(tl,x,a);
3273 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3277 if (opcode[i]==0x2B) { // SW
3280 if(faststore_reg_override) a=faststore_reg_override;
3281 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3282 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3286 if (opcode[i]==0x3F) { // SD
3289 if(faststore_reg_override) a=faststore_reg_override;
3292 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3293 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3294 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3297 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3298 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3299 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3306 // PCSX store handlers don't check invcode again
3308 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3312 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3314 #ifdef DESTRUCTIVE_SHIFT
3315 // The x86 shift operation is 'destructive'; it overwrites the
3316 // source register, so we need to make a copy first and use that.
3319 #if defined(HOST_IMM8)
3320 int ir=get_reg(i_regs->regmap,INVCP);
3322 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3324 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3326 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3327 emit_callne(invalidate_addr_reg[addr]);
3331 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3336 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3337 } else if(c&&!memtarget) {
3338 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3340 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3341 //if(opcode[i]==0x2B || opcode[i]==0x28)
3342 //if(opcode[i]==0x2B || opcode[i]==0x29)
3343 //if(opcode[i]==0x2B)
3344 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3352 emit_readword((int)&last_count,ECX);
3354 if(get_reg(i_regs->regmap,CCREG)<0)
3355 emit_loadreg(CCREG,HOST_CCREG);
3356 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3357 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3358 emit_writeword(HOST_CCREG,(int)&Count);
3361 if(get_reg(i_regs->regmap,CCREG)<0)
3362 emit_loadreg(CCREG,0);
3364 emit_mov(HOST_CCREG,0);
3366 emit_addimm(0,2*ccadj[i],0);
3367 emit_writeword(0,(int)&Count);
3369 emit_call((int)memdebug);
3374 restore_regs(0x100f);
3379 void storelr_assemble(int i,struct regstat *i_regs)
3386 int case1,case2,case3;
3387 int done0,done1,done2;
3388 int memtarget=0,c=0;
3389 int agr=AGEN1+(i&1);
3391 th=get_reg(i_regs->regmap,rs2[i]|64);
3392 tl=get_reg(i_regs->regmap,rs2[i]);
3393 s=get_reg(i_regs->regmap,rs1[i]);
3394 temp=get_reg(i_regs->regmap,agr);
3395 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3398 c=(i_regs->isconst>>s)&1;
3400 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3401 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3405 for(hr=0;hr<HOST_REGS;hr++) {
3406 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3411 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3412 if(!offset&&s!=temp) emit_mov(s,temp);
3418 if(!memtarget||!rs1[i]) {
3424 int map=get_reg(i_regs->regmap,ROREG);
3425 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3426 gen_tlb_addr_w(temp,map);
3428 if((u_int)rdram!=0x80000000)
3429 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3432 int map=get_reg(i_regs->regmap,TLREG);
3435 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3436 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3437 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3438 if(!jaddr&&!memtarget) {
3442 gen_tlb_addr_w(temp,map);
3445 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3446 temp2=get_reg(i_regs->regmap,FTEMP);
3447 if(!rs2[i]) temp2=th=tl;
3450 #ifndef BIG_ENDIAN_MIPS
3451 emit_xorimm(temp,3,temp);
3453 emit_testimm(temp,2);
3456 emit_testimm(temp,1);
3460 if (opcode[i]==0x2A) { // SWL
3461 emit_writeword_indexed(tl,0,temp);
3463 if (opcode[i]==0x2E) { // SWR
3464 emit_writebyte_indexed(tl,3,temp);
3466 if (opcode[i]==0x2C) { // SDL
3467 emit_writeword_indexed(th,0,temp);
3468 if(rs2[i]) emit_mov(tl,temp2);
3470 if (opcode[i]==0x2D) { // SDR
3471 emit_writebyte_indexed(tl,3,temp);
3472 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3477 set_jump_target(case1,(int)out);
3478 if (opcode[i]==0x2A) { // SWL
3479 // Write 3 msb into three least significant bytes
3480 if(rs2[i]) emit_rorimm(tl,8,tl);
3481 emit_writehword_indexed(tl,-1,temp);
3482 if(rs2[i]) emit_rorimm(tl,16,tl);
3483 emit_writebyte_indexed(tl,1,temp);
3484 if(rs2[i]) emit_rorimm(tl,8,tl);
3486 if (opcode[i]==0x2E) { // SWR
3487 // Write two lsb into two most significant bytes
3488 emit_writehword_indexed(tl,1,temp);
3490 if (opcode[i]==0x2C) { // SDL
3491 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3492 // Write 3 msb into three least significant bytes
3493 if(rs2[i]) emit_rorimm(th,8,th);
3494 emit_writehword_indexed(th,-1,temp);
3495 if(rs2[i]) emit_rorimm(th,16,th);
3496 emit_writebyte_indexed(th,1,temp);
3497 if(rs2[i]) emit_rorimm(th,8,th);
3499 if (opcode[i]==0x2D) { // SDR
3500 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3501 // Write two lsb into two most significant bytes
3502 emit_writehword_indexed(tl,1,temp);
3507 set_jump_target(case2,(int)out);
3508 emit_testimm(temp,1);
3511 if (opcode[i]==0x2A) { // SWL
3512 // Write two msb into two least significant bytes
3513 if(rs2[i]) emit_rorimm(tl,16,tl);
3514 emit_writehword_indexed(tl,-2,temp);
3515 if(rs2[i]) emit_rorimm(tl,16,tl);
3517 if (opcode[i]==0x2E) { // SWR
3518 // Write 3 lsb into three most significant bytes
3519 emit_writebyte_indexed(tl,-1,temp);
3520 if(rs2[i]) emit_rorimm(tl,8,tl);
3521 emit_writehword_indexed(tl,0,temp);
3522 if(rs2[i]) emit_rorimm(tl,24,tl);
3524 if (opcode[i]==0x2C) { // SDL
3525 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3526 // Write two msb into two least significant bytes
3527 if(rs2[i]) emit_rorimm(th,16,th);
3528 emit_writehword_indexed(th,-2,temp);
3529 if(rs2[i]) emit_rorimm(th,16,th);
3531 if (opcode[i]==0x2D) { // SDR
3532 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3533 // Write 3 lsb into three most significant bytes
3534 emit_writebyte_indexed(tl,-1,temp);
3535 if(rs2[i]) emit_rorimm(tl,8,tl);
3536 emit_writehword_indexed(tl,0,temp);
3537 if(rs2[i]) emit_rorimm(tl,24,tl);
3542 set_jump_target(case3,(int)out);
3543 if (opcode[i]==0x2A) { // SWL
3544 // Write msb into least significant byte
3545 if(rs2[i]) emit_rorimm(tl,24,tl);
3546 emit_writebyte_indexed(tl,-3,temp);
3547 if(rs2[i]) emit_rorimm(tl,8,tl);
3549 if (opcode[i]==0x2E) { // SWR
3550 // Write entire word
3551 emit_writeword_indexed(tl,-3,temp);
3553 if (opcode[i]==0x2C) { // SDL
3554 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3555 // Write msb into least significant byte
3556 if(rs2[i]) emit_rorimm(th,24,th);
3557 emit_writebyte_indexed(th,-3,temp);
3558 if(rs2[i]) emit_rorimm(th,8,th);
3560 if (opcode[i]==0x2D) { // SDR
3561 if(rs2[i]) emit_mov(th,temp2);
3562 // Write entire word
3563 emit_writeword_indexed(tl,-3,temp);
3565 set_jump_target(done0,(int)out);
3566 set_jump_target(done1,(int)out);
3567 set_jump_target(done2,(int)out);
3568 if (opcode[i]==0x2C) { // SDL
3569 emit_testimm(temp,4);
3572 emit_andimm(temp,~3,temp);
3573 emit_writeword_indexed(temp2,4,temp);
3574 set_jump_target(done0,(int)out);
3576 if (opcode[i]==0x2D) { // SDR
3577 emit_testimm(temp,4);
3580 emit_andimm(temp,~3,temp);
3581 emit_writeword_indexed(temp2,-4,temp);
3582 set_jump_target(done0,(int)out);
3585 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3586 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3588 int map=get_reg(i_regs->regmap,ROREG);
3589 if(map<0) map=HOST_TEMPREG;
3590 gen_orig_addr_w(temp,map);
3592 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3594 #if defined(HOST_IMM8)
3595 int ir=get_reg(i_regs->regmap,INVCP);
3597 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3599 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3601 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3602 emit_callne(invalidate_addr_reg[temp]);
3606 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3611 //save_regs(0x100f);
3612 emit_readword((int)&last_count,ECX);
3613 if(get_reg(i_regs->regmap,CCREG)<0)
3614 emit_loadreg(CCREG,HOST_CCREG);
3615 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3616 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3617 emit_writeword(HOST_CCREG,(int)&Count);
3618 emit_call((int)memdebug);
3620 //restore_regs(0x100f);
3624 void c1ls_assemble(int i,struct regstat *i_regs)
3626 #ifndef DISABLE_COP1
3632 int jaddr,jaddr2=0,jaddr3,type;
3633 int agr=AGEN1+(i&1);
3635 th=get_reg(i_regs->regmap,FTEMP|64);
3636 tl=get_reg(i_regs->regmap,FTEMP);
3637 s=get_reg(i_regs->regmap,rs1[i]);
3638 temp=get_reg(i_regs->regmap,agr);
3639 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3644 for(hr=0;hr<HOST_REGS;hr++) {
3645 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3647 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3648 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3650 // Loads use a temporary register which we need to save
3653 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3657 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3658 //else c=(i_regs->wasconst>>s)&1;
3659 if(s>=0) c=(i_regs->wasconst>>s)&1;
3660 // Check cop1 unusable
3662 signed char rs=get_reg(i_regs->regmap,CSREG);
3664 emit_testimm(rs,0x20000000);
3667 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3670 if (opcode[i]==0x39) { // SWC1 (get float address)
3671 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3673 if (opcode[i]==0x3D) { // SDC1 (get double address)
3674 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3676 // Generate address + offset
3679 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3683 map=get_reg(i_regs->regmap,TLREG);
3686 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3687 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3689 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3690 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3693 if (opcode[i]==0x39) { // SWC1 (read float)
3694 emit_readword_indexed(0,tl,tl);
3696 if (opcode[i]==0x3D) { // SDC1 (read double)
3697 emit_readword_indexed(4,tl,th);
3698 emit_readword_indexed(0,tl,tl);
3700 if (opcode[i]==0x31) { // LWC1 (get target address)
3701 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3703 if (opcode[i]==0x35) { // LDC1 (get target address)
3704 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3711 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3713 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3715 #ifdef DESTRUCTIVE_SHIFT
3716 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3717 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3721 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3722 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3724 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3725 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3728 if (opcode[i]==0x31) { // LWC1
3729 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3730 //gen_tlb_addr_r(ar,map);
3731 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3732 #ifdef HOST_IMM_ADDR32
3733 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3736 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3739 if (opcode[i]==0x35) { // LDC1
3741 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3742 //gen_tlb_addr_r(ar,map);
3743 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3744 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3745 #ifdef HOST_IMM_ADDR32
3746 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3749 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3752 if (opcode[i]==0x39) { // SWC1
3753 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3754 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3757 if (opcode[i]==0x3D) { // SDC1
3759 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3760 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3761 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3764 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3765 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3766 #ifndef DESTRUCTIVE_SHIFT
3767 temp=offset||c||s<0?ar:s;
3769 #if defined(HOST_IMM8)
3770 int ir=get_reg(i_regs->regmap,INVCP);
3772 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3774 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3776 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3777 emit_callne(invalidate_addr_reg[temp]);
3781 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3785 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3786 if (opcode[i]==0x31) { // LWC1 (write float)
3787 emit_writeword_indexed(tl,0,temp);
3789 if (opcode[i]==0x35) { // LDC1 (write double)
3790 emit_writeword_indexed(th,4,temp);
3791 emit_writeword_indexed(tl,0,temp);
3793 //if(opcode[i]==0x39)
3794 /*if(opcode[i]==0x39||opcode[i]==0x31)
3797 emit_readword((int)&last_count,ECX);
3798 if(get_reg(i_regs->regmap,CCREG)<0)
3799 emit_loadreg(CCREG,HOST_CCREG);
3800 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3801 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3802 emit_writeword(HOST_CCREG,(int)&Count);
3803 emit_call((int)memdebug);
3807 cop1_unusable(i, i_regs);
3811 void c2ls_assemble(int i,struct regstat *i_regs)
3816 int memtarget=0,c=0;
3817 int jaddr2=0,jaddr3,type;
3818 int agr=AGEN1+(i&1);
3819 int fastio_reg_override=0;
3821 u_int copr=(source[i]>>16)&0x1f;
3822 s=get_reg(i_regs->regmap,rs1[i]);
3823 tl=get_reg(i_regs->regmap,FTEMP);
3829 for(hr=0;hr<HOST_REGS;hr++) {
3830 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3832 if(i_regs->regmap[HOST_CCREG]==CCREG)
3833 reglist&=~(1<<HOST_CCREG);
3836 if (opcode[i]==0x3a) { // SWC2
3837 ar=get_reg(i_regs->regmap,agr);
3838 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3843 if(s>=0) c=(i_regs->wasconst>>s)&1;
3844 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3845 if (!offset&&!c&&s>=0) ar=s;
3848 if (opcode[i]==0x3a) { // SWC2
3849 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3857 emit_jmp(0); // inline_readstub/inline_writestub?
3861 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3863 if (opcode[i]==0x32) { // LWC2
3864 #ifdef HOST_IMM_ADDR32
3865 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3869 if(fastio_reg_override) a=fastio_reg_override;
3870 emit_readword_indexed(0,a,tl);
3872 if (opcode[i]==0x3a) { // SWC2
3873 #ifdef DESTRUCTIVE_SHIFT
3874 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3877 if(fastio_reg_override) a=fastio_reg_override;
3878 emit_writeword_indexed(tl,0,a);
3882 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3883 if(opcode[i]==0x3a) // SWC2
3884 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3885 #if defined(HOST_IMM8)
3886 int ir=get_reg(i_regs->regmap,INVCP);
3888 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3890 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3892 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3893 emit_callne(invalidate_addr_reg[ar]);
3897 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3900 if (opcode[i]==0x32) { // LWC2
3901 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3905 #ifndef multdiv_assemble
3906 void multdiv_assemble(int i,struct regstat *i_regs)
3908 printf("Need multdiv_assemble for this architecture.\n");
3913 void mov_assemble(int i,struct regstat *i_regs)
3915 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3916 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3918 signed char sh,sl,th,tl;
3919 th=get_reg(i_regs->regmap,rt1[i]|64);
3920 tl=get_reg(i_regs->regmap,rt1[i]);
3923 sh=get_reg(i_regs->regmap,rs1[i]|64);
3924 sl=get_reg(i_regs->regmap,rs1[i]);
3925 if(sl>=0) emit_mov(sl,tl);
3926 else emit_loadreg(rs1[i],tl);
3928 if(sh>=0) emit_mov(sh,th);
3929 else emit_loadreg(rs1[i]|64,th);
3935 #ifndef fconv_assemble
3936 void fconv_assemble(int i,struct regstat *i_regs)
3938 printf("Need fconv_assemble for this architecture.\n");
3944 void float_assemble(int i,struct regstat *i_regs)
3946 printf("Need float_assemble for this architecture.\n");
3951 void syscall_assemble(int i,struct regstat *i_regs)
3953 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3954 assert(ccreg==HOST_CCREG);
3955 assert(!is_delayslot);
3956 emit_movimm(start+i*4,EAX); // Get PC
3957 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3958 emit_jmp((int)jump_syscall_hle); // XXX
3961 void hlecall_assemble(int i,struct regstat *i_regs)
3963 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3964 assert(ccreg==HOST_CCREG);
3965 assert(!is_delayslot);
3966 emit_movimm(start+i*4+4,0); // Get PC
3967 emit_movimm((int)psxHLEt[source[i]&7],1);
3968 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3969 emit_jmp((int)jump_hlecall);
3972 void intcall_assemble(int i,struct regstat *i_regs)
3974 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3975 assert(ccreg==HOST_CCREG);
3976 assert(!is_delayslot);
3977 emit_movimm(start+i*4,0); // Get PC
3978 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3979 emit_jmp((int)jump_intcall);
3982 void ds_assemble(int i,struct regstat *i_regs)
3984 speculate_register_values(i);
3988 alu_assemble(i,i_regs);break;
3990 imm16_assemble(i,i_regs);break;
3992 shift_assemble(i,i_regs);break;
3994 shiftimm_assemble(i,i_regs);break;
3996 load_assemble(i,i_regs);break;
3998 loadlr_assemble(i,i_regs);break;
4000 store_assemble(i,i_regs);break;
4002 storelr_assemble(i,i_regs);break;
4004 cop0_assemble(i,i_regs);break;
4006 cop1_assemble(i,i_regs);break;
4008 c1ls_assemble(i,i_regs);break;
4010 cop2_assemble(i,i_regs);break;
4012 c2ls_assemble(i,i_regs);break;
4014 c2op_assemble(i,i_regs);break;
4016 fconv_assemble(i,i_regs);break;
4018 float_assemble(i,i_regs);break;
4020 fcomp_assemble(i,i_regs);break;
4022 multdiv_assemble(i,i_regs);break;
4024 mov_assemble(i,i_regs);break;
4034 printf("Jump in the delay slot. This is probably a bug.\n");
4039 // Is the branch target a valid internal jump?
4040 int internal_branch(uint64_t i_is32,int addr)
4042 if(addr&1) return 0; // Indirect (register) jump
4043 if(addr>=start && addr<start+slen*4-4)
4045 int t=(addr-start)>>2;
4046 // Delay slots are not valid branch targets
4047 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4048 // 64 -> 32 bit transition requires a recompile
4049 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4051 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4052 else printf("optimizable: yes\n");
4054 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4056 if(requires_32bit[t]&~i_is32) return 0;
4064 #ifndef wb_invalidate
4065 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4066 uint64_t u,uint64_t uu)
4069 for(hr=0;hr<HOST_REGS;hr++) {
4070 if(hr!=EXCLUDE_REG) {
4071 if(pre[hr]!=entry[hr]) {
4074 if(get_reg(entry,pre[hr])<0) {
4076 if(!((u>>pre[hr])&1)) {
4077 emit_storereg(pre[hr],hr);
4078 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4079 emit_sarimm(hr,31,hr);
4080 emit_storereg(pre[hr]|64,hr);
4084 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4085 emit_storereg(pre[hr],hr);
4094 // Move from one register to another (no writeback)
4095 for(hr=0;hr<HOST_REGS;hr++) {
4096 if(hr!=EXCLUDE_REG) {
4097 if(pre[hr]!=entry[hr]) {
4098 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4100 if((nr=get_reg(entry,pre[hr]))>=0) {
4110 // Load the specified registers
4111 // This only loads the registers given as arguments because
4112 // we don't want to load things that will be overwritten
4113 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4117 for(hr=0;hr<HOST_REGS;hr++) {
4118 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4119 if(entry[hr]!=regmap[hr]) {
4120 if(regmap[hr]==rs1||regmap[hr]==rs2)
4127 emit_loadreg(regmap[hr],hr);
4134 for(hr=0;hr<HOST_REGS;hr++) {
4135 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4136 if(entry[hr]!=regmap[hr]) {
4137 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4139 assert(regmap[hr]!=64);
4140 if((is32>>(regmap[hr]&63))&1) {
4141 int lr=get_reg(regmap,regmap[hr]-64);
4143 emit_sarimm(lr,31,hr);
4145 emit_loadreg(regmap[hr],hr);
4149 emit_loadreg(regmap[hr],hr);
4157 // Load registers prior to the start of a loop
4158 // so that they are not loaded within the loop
4159 static void loop_preload(signed char pre[],signed char entry[])
4162 for(hr=0;hr<HOST_REGS;hr++) {
4163 if(hr!=EXCLUDE_REG) {
4164 if(pre[hr]!=entry[hr]) {
4166 if(get_reg(pre,entry[hr])<0) {
4167 assem_debug("loop preload:\n");
4168 //printf("loop preload: %d\n",hr);
4172 else if(entry[hr]<TEMPREG)
4174 emit_loadreg(entry[hr],hr);
4176 else if(entry[hr]-64<TEMPREG)
4178 emit_loadreg(entry[hr],hr);
4187 // Generate address for load/store instruction
4188 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4189 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4191 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4193 int agr=AGEN1+(i&1);
4194 int mgr=MGEN1+(i&1);
4195 if(itype[i]==LOAD) {
4196 ra=get_reg(i_regs->regmap,rt1[i]);
4197 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4200 if(itype[i]==LOADLR) {
4201 ra=get_reg(i_regs->regmap,FTEMP);
4203 if(itype[i]==STORE||itype[i]==STORELR) {
4204 ra=get_reg(i_regs->regmap,agr);
4205 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4207 if(itype[i]==C1LS||itype[i]==C2LS) {
4208 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4209 ra=get_reg(i_regs->regmap,FTEMP);
4210 else { // SWC1/SDC1/SWC2/SDC2
4211 ra=get_reg(i_regs->regmap,agr);
4212 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4215 int rs=get_reg(i_regs->regmap,rs1[i]);
4216 int rm=get_reg(i_regs->regmap,TLREG);
4219 int c=(i_regs->wasconst>>rs)&1;
4221 // Using r0 as a base address
4223 if(!entry||entry[rm]!=mgr) {
4224 generate_map_const(offset,rm);
4225 } // else did it in the previous cycle
4227 if(!entry||entry[ra]!=agr) {
4228 if (opcode[i]==0x22||opcode[i]==0x26) {
4229 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4230 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4231 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4233 emit_movimm(offset,ra);
4235 } // else did it in the previous cycle
4238 if(!entry||entry[ra]!=rs1[i])
4239 emit_loadreg(rs1[i],ra);
4240 //if(!entry||entry[ra]!=rs1[i])
4241 // printf("poor load scheduling!\n");
4246 if(!entry||entry[rm]!=mgr) {
4247 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4248 // Stores to memory go thru the mapper to detect self-modifying
4249 // code, loads don't.
4250 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4251 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4252 generate_map_const(constmap[i][rs]+offset,rm);
4254 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4255 generate_map_const(constmap[i][rs]+offset,rm);
4260 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4261 if(!entry||entry[ra]!=agr) {
4262 if (opcode[i]==0x22||opcode[i]==0x26) {
4263 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4264 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4265 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4267 #ifdef HOST_IMM_ADDR32
4268 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4269 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4271 emit_movimm(constmap[i][rs]+offset,ra);
4272 regs[i].loadedconst|=1<<ra;
4274 } // else did it in the previous cycle
4275 } // else load_consts already did it
4277 if(offset&&!c&&rs1[i]) {
4279 emit_addimm(rs,offset,ra);
4281 emit_addimm(ra,offset,ra);
4286 // Preload constants for next instruction
4287 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4289 #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4291 agr=MGEN1+((i+1)&1);
4292 ra=get_reg(i_regs->regmap,agr);
4294 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4295 int offset=imm[i+1];
4296 int c=(regs[i+1].wasconst>>rs)&1;
4298 if(itype[i+1]==STORE||itype[i+1]==STORELR
4299 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4300 // Stores to memory go thru the mapper to detect self-modifying
4301 // code, loads don't.
4302 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4303 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4304 generate_map_const(constmap[i+1][rs]+offset,ra);
4306 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4307 generate_map_const(constmap[i+1][rs]+offset,ra);
4310 /*else if(rs1[i]==0) {
4311 generate_map_const(offset,ra);
4316 agr=AGEN1+((i+1)&1);
4317 ra=get_reg(i_regs->regmap,agr);
4319 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4320 int offset=imm[i+1];
4321 int c=(regs[i+1].wasconst>>rs)&1;
4322 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4323 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4324 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4325 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4326 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4328 #ifdef HOST_IMM_ADDR32
4329 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4330 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4332 emit_movimm(constmap[i+1][rs]+offset,ra);
4333 regs[i+1].loadedconst|=1<<ra;
4336 else if(rs1[i+1]==0) {
4337 // Using r0 as a base address
4338 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4339 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4340 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4341 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4343 emit_movimm(offset,ra);
4350 int get_final_value(int hr, int i, int *value)
4352 int reg=regs[i].regmap[hr];
4354 if(regs[i+1].regmap[hr]!=reg) break;
4355 if(!((regs[i+1].isconst>>hr)&1)) break;
4360 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4361 *value=constmap[i][hr];
4365 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4366 // Load in delay slot, out-of-order execution
4367 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4369 #ifdef HOST_IMM_ADDR32
4370 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4372 // Precompute load address
4373 *value=constmap[i][hr]+imm[i+2];
4377 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4379 #ifdef HOST_IMM_ADDR32
4380 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4382 // Precompute load address
4383 *value=constmap[i][hr]+imm[i+1];
4384 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4389 *value=constmap[i][hr];
4390 //printf("c=%x\n",(int)constmap[i][hr]);
4391 if(i==slen-1) return 1;
4393 return !((unneeded_reg[i+1]>>reg)&1);
4395 return !((unneeded_reg_upper[i+1]>>reg)&1);
4399 // Load registers with known constants
4400 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4403 // propagate loaded constant flags
4405 regs[i].loadedconst=0;
4407 for(hr=0;hr<HOST_REGS;hr++) {
4408 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4409 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4411 regs[i].loadedconst|=1<<hr;
4416 for(hr=0;hr<HOST_REGS;hr++) {
4417 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4418 //if(entry[hr]!=regmap[hr]) {
4419 if(!((regs[i].loadedconst>>hr)&1)) {
4420 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4421 int value,similar=0;
4422 if(get_final_value(hr,i,&value)) {
4423 // see if some other register has similar value
4424 for(hr2=0;hr2<HOST_REGS;hr2++) {
4425 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4426 if(is_similar_value(value,constmap[i][hr2])) {
4434 if(get_final_value(hr2,i,&value2)) // is this needed?
4435 emit_movimm_from(value2,hr2,value,hr);
4437 emit_movimm(value,hr);
4443 emit_movimm(value,hr);
4446 regs[i].loadedconst|=1<<hr;
4452 for(hr=0;hr<HOST_REGS;hr++) {
4453 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4454 //if(entry[hr]!=regmap[hr]) {
4455 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4456 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4457 if((is32>>(regmap[hr]&63))&1) {
4458 int lr=get_reg(regmap,regmap[hr]-64);
4460 emit_sarimm(lr,31,hr);
4465 if(get_final_value(hr,i,&value)) {
4470 emit_movimm(value,hr);
4479 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4483 for(hr=0;hr<HOST_REGS;hr++) {
4484 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4485 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4486 int value=constmap[i][hr];
4491 emit_movimm(value,hr);
4497 for(hr=0;hr<HOST_REGS;hr++) {
4498 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4499 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4500 if((is32>>(regmap[hr]&63))&1) {
4501 int lr=get_reg(regmap,regmap[hr]-64);
4503 emit_sarimm(lr,31,hr);
4507 int value=constmap[i][hr];
4512 emit_movimm(value,hr);
4520 // Write out all dirty registers (except cycle count)
4521 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4524 for(hr=0;hr<HOST_REGS;hr++) {
4525 if(hr!=EXCLUDE_REG) {
4526 if(i_regmap[hr]>0) {
4527 if(i_regmap[hr]!=CCREG) {
4528 if((i_dirty>>hr)&1) {
4529 if(i_regmap[hr]<64) {
4530 emit_storereg(i_regmap[hr],hr);
4532 if( ((i_is32>>i_regmap[hr])&1) ) {
4533 #ifdef DESTRUCTIVE_WRITEBACK
4534 emit_sarimm(hr,31,hr);
4535 emit_storereg(i_regmap[hr]|64,hr);
4537 emit_sarimm(hr,31,HOST_TEMPREG);
4538 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4543 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4544 emit_storereg(i_regmap[hr],hr);
4553 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4554 // This writes the registers not written by store_regs_bt
4555 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4558 int t=(addr-start)>>2;
4559 for(hr=0;hr<HOST_REGS;hr++) {
4560 if(hr!=EXCLUDE_REG) {
4561 if(i_regmap[hr]>0) {
4562 if(i_regmap[hr]!=CCREG) {
4563 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4564 if((i_dirty>>hr)&1) {
4565 if(i_regmap[hr]<64) {
4566 emit_storereg(i_regmap[hr],hr);
4568 if( ((i_is32>>i_regmap[hr])&1) ) {
4569 #ifdef DESTRUCTIVE_WRITEBACK
4570 emit_sarimm(hr,31,hr);
4571 emit_storereg(i_regmap[hr]|64,hr);
4573 emit_sarimm(hr,31,HOST_TEMPREG);
4574 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4579 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4580 emit_storereg(i_regmap[hr],hr);
4591 // Load all registers (except cycle count)
4592 void load_all_regs(signed char i_regmap[])
4595 for(hr=0;hr<HOST_REGS;hr++) {
4596 if(hr!=EXCLUDE_REG) {
4597 if(i_regmap[hr]==0) {
4601 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4603 emit_loadreg(i_regmap[hr],hr);
4609 // Load all current registers also needed by next instruction
4610 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4613 for(hr=0;hr<HOST_REGS;hr++) {
4614 if(hr!=EXCLUDE_REG) {
4615 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4616 if(i_regmap[hr]==0) {
4620 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4622 emit_loadreg(i_regmap[hr],hr);
4629 // Load all regs, storing cycle count if necessary
4630 void load_regs_entry(int t)
4633 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4634 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4635 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4636 emit_storereg(CCREG,HOST_CCREG);
4639 for(hr=0;hr<HOST_REGS;hr++) {
4640 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4641 if(regs[t].regmap_entry[hr]==0) {
4644 else if(regs[t].regmap_entry[hr]!=CCREG)
4646 emit_loadreg(regs[t].regmap_entry[hr],hr);
4651 for(hr=0;hr<HOST_REGS;hr++) {
4652 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4653 assert(regs[t].regmap_entry[hr]!=64);
4654 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4655 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4657 emit_loadreg(regs[t].regmap_entry[hr],hr);
4661 emit_sarimm(lr,31,hr);
4666 emit_loadreg(regs[t].regmap_entry[hr],hr);
4672 // Store dirty registers prior to branch
4673 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4675 if(internal_branch(i_is32,addr))
4677 int t=(addr-start)>>2;
4679 for(hr=0;hr<HOST_REGS;hr++) {
4680 if(hr!=EXCLUDE_REG) {
4681 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4682 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4683 if((i_dirty>>hr)&1) {
4684 if(i_regmap[hr]<64) {
4685 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4686 emit_storereg(i_regmap[hr],hr);
4687 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4688 #ifdef DESTRUCTIVE_WRITEBACK
4689 emit_sarimm(hr,31,hr);
4690 emit_storereg(i_regmap[hr]|64,hr);
4692 emit_sarimm(hr,31,HOST_TEMPREG);
4693 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4698 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4699 emit_storereg(i_regmap[hr],hr);
4710 // Branch out of this block, write out all dirty regs
4711 wb_dirtys(i_regmap,i_is32,i_dirty);
4715 // Load all needed registers for branch target
4716 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4718 //if(addr>=start && addr<(start+slen*4))
4719 if(internal_branch(i_is32,addr))
4721 int t=(addr-start)>>2;
4723 // Store the cycle count before loading something else
4724 if(i_regmap[HOST_CCREG]!=CCREG) {
4725 assert(i_regmap[HOST_CCREG]==-1);
4727 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4728 emit_storereg(CCREG,HOST_CCREG);
4731 for(hr=0;hr<HOST_REGS;hr++) {
4732 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4733 #ifdef DESTRUCTIVE_WRITEBACK
4734 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4736 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4738 if(regs[t].regmap_entry[hr]==0) {
4741 else if(regs[t].regmap_entry[hr]!=CCREG)
4743 emit_loadreg(regs[t].regmap_entry[hr],hr);
4749 for(hr=0;hr<HOST_REGS;hr++) {
4750 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4751 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4752 assert(regs[t].regmap_entry[hr]!=64);
4753 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4754 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4756 emit_loadreg(regs[t].regmap_entry[hr],hr);
4760 emit_sarimm(lr,31,hr);
4765 emit_loadreg(regs[t].regmap_entry[hr],hr);
4768 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4769 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4771 emit_sarimm(lr,31,hr);
4778 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4780 if(addr>=start && addr<start+slen*4-4)
4782 int t=(addr-start)>>2;
4784 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4785 for(hr=0;hr<HOST_REGS;hr++)
4789 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4791 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4798 if(i_regmap[hr]<TEMPREG)
4800 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4803 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4805 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4810 else // Same register but is it 32-bit or dirty?
4813 if(!((regs[t].dirty>>hr)&1))
4817 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4819 //printf("%x: dirty no match\n",addr);
4824 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4826 //printf("%x: is32 no match\n",addr);
4832 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4834 if(requires_32bit[t]&~i_is32) return 0;
4836 // Delay slots are not valid branch targets
4837 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4838 // Delay slots require additional processing, so do not match
4839 if(is_ds[t]) return 0;
4844 for(hr=0;hr<HOST_REGS;hr++)
4850 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4864 // Used when a branch jumps into the delay slot of another branch
4865 void ds_assemble_entry(int i)
4867 int t=(ba[i]-start)>>2;
4868 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4869 assem_debug("Assemble delay slot at %x\n",ba[i]);
4870 assem_debug("<->\n");
4871 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4872 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4873 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4874 address_generation(t,®s[t],regs[t].regmap_entry);
4875 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4876 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4881 alu_assemble(t,®s[t]);break;
4883 imm16_assemble(t,®s[t]);break;
4885 shift_assemble(t,®s[t]);break;
4887 shiftimm_assemble(t,®s[t]);break;
4889 load_assemble(t,®s[t]);break;
4891 loadlr_assemble(t,®s[t]);break;
4893 store_assemble(t,®s[t]);break;
4895 storelr_assemble(t,®s[t]);break;
4897 cop0_assemble(t,®s[t]);break;
4899 cop1_assemble(t,®s[t]);break;
4901 c1ls_assemble(t,®s[t]);break;
4903 cop2_assemble(t,®s[t]);break;
4905 c2ls_assemble(t,®s[t]);break;
4907 c2op_assemble(t,®s[t]);break;
4909 fconv_assemble(t,®s[t]);break;
4911 float_assemble(t,®s[t]);break;
4913 fcomp_assemble(t,®s[t]);break;
4915 multdiv_assemble(t,®s[t]);break;
4917 mov_assemble(t,®s[t]);break;
4927 printf("Jump in the delay slot. This is probably a bug.\n");
4929 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4930 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4931 if(internal_branch(regs[t].is32,ba[i]+4))
4932 assem_debug("branch: internal\n");
4934 assem_debug("branch: external\n");
4935 assert(internal_branch(regs[t].is32,ba[i]+4));
4936 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4940 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4949 //if(ba[i]>=start && ba[i]<(start+slen*4))
4950 if(internal_branch(branch_regs[i].is32,ba[i]))
4952 int t=(ba[i]-start)>>2;
4953 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4961 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4963 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4965 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4966 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4970 else if(*adj==0||invert) {
4971 emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
4977 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4981 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4984 void do_ccstub(int n)
4987 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4988 set_jump_target(stubs[n][1],(int)out);
4990 if(stubs[n][6]==NULLDS) {
4991 // Delay slot instruction is nullified ("likely" branch)
4992 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4994 else if(stubs[n][6]!=TAKEN) {
4995 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4998 if(internal_branch(branch_regs[i].is32,ba[i]))
4999 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5003 // Save PC as return address
5004 emit_movimm(stubs[n][5],EAX);
5005 emit_writeword(EAX,(int)&pcaddr);
5009 // Return address depends on which way the branch goes
5010 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5012 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5013 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5014 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5015 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5025 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5029 #ifdef DESTRUCTIVE_WRITEBACK
5031 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5032 emit_loadreg(rs1[i],s1l);
5035 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5036 emit_loadreg(rs2[i],s1l);
5039 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5040 emit_loadreg(rs2[i],s2l);
5043 int addr=-1,alt=-1,ntaddr=-1;
5046 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5047 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5048 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5056 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5057 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5058 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5064 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5068 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5069 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5070 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5076 assert(hr<HOST_REGS);
5078 if((opcode[i]&0x2f)==4) // BEQ
5080 #ifdef HAVE_CMOV_IMM
5082 if(s2l>=0) emit_cmp(s1l,s2l);
5083 else emit_test(s1l,s1l);
5084 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5089 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5091 if(s2h>=0) emit_cmp(s1h,s2h);
5092 else emit_test(s1h,s1h);
5093 emit_cmovne_reg(alt,addr);
5095 if(s2l>=0) emit_cmp(s1l,s2l);
5096 else emit_test(s1l,s1l);
5097 emit_cmovne_reg(alt,addr);
5100 if((opcode[i]&0x2f)==5) // BNE
5102 #ifdef HAVE_CMOV_IMM
5104 if(s2l>=0) emit_cmp(s1l,s2l);
5105 else emit_test(s1l,s1l);
5106 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5111 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5113 if(s2h>=0) emit_cmp(s1h,s2h);
5114 else emit_test(s1h,s1h);
5115 emit_cmovne_reg(alt,addr);
5117 if(s2l>=0) emit_cmp(s1l,s2l);
5118 else emit_test(s1l,s1l);
5119 emit_cmovne_reg(alt,addr);
5122 if((opcode[i]&0x2f)==6) // BLEZ
5124 //emit_movimm(ba[i],alt);
5125 //emit_movimm(start+i*4+8,addr);
5126 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5128 if(s1h>=0) emit_mov(addr,ntaddr);
5129 emit_cmovl_reg(alt,addr);
5132 emit_cmovne_reg(ntaddr,addr);
5133 emit_cmovs_reg(alt,addr);
5136 if((opcode[i]&0x2f)==7) // BGTZ
5138 //emit_movimm(ba[i],addr);
5139 //emit_movimm(start+i*4+8,ntaddr);
5140 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5142 if(s1h>=0) emit_mov(addr,alt);
5143 emit_cmovl_reg(ntaddr,addr);
5146 emit_cmovne_reg(alt,addr);
5147 emit_cmovs_reg(ntaddr,addr);
5150 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5152 //emit_movimm(ba[i],alt);
5153 //emit_movimm(start+i*4+8,addr);
5154 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5155 if(s1h>=0) emit_test(s1h,s1h);
5156 else emit_test(s1l,s1l);
5157 emit_cmovs_reg(alt,addr);
5159 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5161 //emit_movimm(ba[i],addr);
5162 //emit_movimm(start+i*4+8,alt);
5163 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5164 if(s1h>=0) emit_test(s1h,s1h);
5165 else emit_test(s1l,s1l);
5166 emit_cmovs_reg(alt,addr);
5168 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5169 if(source[i]&0x10000) // BC1T
5171 //emit_movimm(ba[i],alt);
5172 //emit_movimm(start+i*4+8,addr);
5173 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5174 emit_testimm(s1l,0x800000);
5175 emit_cmovne_reg(alt,addr);
5179 //emit_movimm(ba[i],addr);
5180 //emit_movimm(start+i*4+8,alt);
5181 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5182 emit_testimm(s1l,0x800000);
5183 emit_cmovne_reg(alt,addr);
5186 emit_writeword(addr,(int)&pcaddr);
5191 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5192 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5193 r=get_reg(branch_regs[i].regmap,RTEMP);
5195 emit_writeword(r,(int)&pcaddr);
5197 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5199 // Update cycle count
5200 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5201 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5202 emit_call((int)cc_interrupt);
5203 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5204 if(stubs[n][6]==TAKEN) {
5205 if(internal_branch(branch_regs[i].is32,ba[i]))
5206 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5207 else if(itype[i]==RJUMP) {
5208 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5209 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5211 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5213 }else if(stubs[n][6]==NOTTAKEN) {
5214 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5215 else load_all_regs(branch_regs[i].regmap);
5216 }else if(stubs[n][6]==NULLDS) {
5217 // Delay slot instruction is nullified ("likely" branch)
5218 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5219 else load_all_regs(regs[i].regmap);
5221 load_all_regs(branch_regs[i].regmap);
5223 emit_jmp(stubs[n][2]); // return address
5225 /* This works but uses a lot of memory...
5226 emit_readword((int)&last_count,ECX);
5227 emit_add(HOST_CCREG,ECX,EAX);
5228 emit_writeword(EAX,(int)&Count);
5229 emit_call((int)gen_interupt);
5230 emit_readword((int)&Count,HOST_CCREG);
5231 emit_readword((int)&next_interupt,EAX);
5232 emit_readword((int)&pending_exception,EBX);
5233 emit_writeword(EAX,(int)&last_count);
5234 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5236 int jne_instr=(int)out;
5238 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5239 load_all_regs(branch_regs[i].regmap);
5240 emit_jmp(stubs[n][2]); // return address
5241 set_jump_target(jne_instr,(int)out);
5242 emit_readword((int)&pcaddr,EAX);
5243 // Call get_addr_ht instead of doing the hash table here.
5244 // This code is executed infrequently and takes up a lot of space
5245 // so smaller is better.
5246 emit_storereg(CCREG,HOST_CCREG);
5248 emit_call((int)get_addr_ht);
5249 emit_loadreg(CCREG,HOST_CCREG);
5250 emit_addimm(ESP,4,ESP);
5254 add_to_linker(int addr,int target,int ext)
5256 link_addr[linkcount][0]=addr;
5257 link_addr[linkcount][1]=target;
5258 link_addr[linkcount][2]=ext;
5262 static void ujump_assemble_write_ra(int i)
5265 unsigned int return_address;
5266 rt=get_reg(branch_regs[i].regmap,31);
5267 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5269 return_address=start+i*4+8;
5272 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5273 int temp=-1; // note: must be ds-safe
5277 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5278 else emit_movimm(return_address,rt);
5286 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5289 emit_movimm(return_address,rt); // PC into link register
5291 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5297 void ujump_assemble(int i,struct regstat *i_regs)
5299 signed char *i_regmap=i_regs->regmap;
5301 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5302 address_generation(i+1,i_regs,regs[i].regmap_entry);
5304 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5305 if(rt1[i]==31&&temp>=0)
5307 int return_address=start+i*4+8;
5308 if(get_reg(branch_regs[i].regmap,31)>0)
5309 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5312 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5313 ujump_assemble_write_ra(i); // writeback ra for DS
5316 ds_assemble(i+1,i_regs);
5317 uint64_t bc_unneeded=branch_regs[i].u;
5318 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5319 bc_unneeded|=1|(1LL<<rt1[i]);
5320 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5321 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5322 bc_unneeded,bc_unneeded_upper);
5323 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5324 if(!ra_done&&rt1[i]==31)
5325 ujump_assemble_write_ra(i);
5327 cc=get_reg(branch_regs[i].regmap,CCREG);
5328 assert(cc==HOST_CCREG);
5329 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5331 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5333 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5334 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5335 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5336 if(internal_branch(branch_regs[i].is32,ba[i]))
5337 assem_debug("branch: internal\n");
5339 assem_debug("branch: external\n");
5340 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5341 ds_assemble_entry(i);
5344 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5349 static void rjump_assemble_write_ra(int i)
5351 int rt,return_address;
5352 assert(rt1[i+1]!=rt1[i]);
5353 assert(rt2[i+1]!=rt1[i]);
5354 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5355 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5357 return_address=start+i*4+8;
5361 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5364 emit_movimm(return_address,rt); // PC into link register
5366 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5370 void rjump_assemble(int i,struct regstat *i_regs)
5372 signed char *i_regmap=i_regs->regmap;
5376 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5378 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5379 // Delay slot abuse, make a copy of the branch address register
5380 temp=get_reg(branch_regs[i].regmap,RTEMP);
5382 assert(regs[i].regmap[temp]==RTEMP);
5386 address_generation(i+1,i_regs,regs[i].regmap_entry);
5390 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5391 int return_address=start+i*4+8;
5392 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5398 int rh=get_reg(regs[i].regmap,RHASH);
5399 if(rh>=0) do_preload_rhash(rh);
5402 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5403 rjump_assemble_write_ra(i);
5406 ds_assemble(i+1,i_regs);
5407 uint64_t bc_unneeded=branch_regs[i].u;
5408 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5409 bc_unneeded|=1|(1LL<<rt1[i]);
5410 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5411 bc_unneeded&=~(1LL<<rs1[i]);
5412 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5413 bc_unneeded,bc_unneeded_upper);
5414 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5415 if(!ra_done&&rt1[i]!=0)
5416 rjump_assemble_write_ra(i);
5417 cc=get_reg(branch_regs[i].regmap,CCREG);
5418 assert(cc==HOST_CCREG);
5420 int rh=get_reg(branch_regs[i].regmap,RHASH);
5421 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5423 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5424 do_preload_rhtbl(ht);
5428 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5429 #ifdef DESTRUCTIVE_WRITEBACK
5430 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5431 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5432 emit_loadreg(rs1[i],rs);
5437 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5441 do_miniht_load(ht,rh);
5444 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5445 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5447 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5448 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5450 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5451 // special case for RFE
5456 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5459 do_miniht_jump(rs,rh,ht);
5464 //if(rs!=EAX) emit_mov(rs,EAX);
5465 //emit_jmp((int)jump_vaddr_eax);
5466 emit_jmp(jump_vaddr_reg[rs]);
5471 emit_shrimm(rs,16,rs);
5472 emit_xor(temp,rs,rs);
5473 emit_movzwl_reg(rs,rs);
5474 emit_shlimm(rs,4,rs);
5475 emit_cmpmem_indexed((int)hash_table,rs,temp);
5476 emit_jne((int)out+14);
5477 emit_readword_indexed((int)hash_table+4,rs,rs);
5479 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5480 emit_addimm_no_flags(8,rs);
5481 emit_jeq((int)out-17);
5482 // No hit on hash table, call compiler
5485 #ifdef DEBUG_CYCLE_COUNT
5486 emit_readword((int)&last_count,ECX);
5487 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5488 emit_readword((int)&next_interupt,ECX);
5489 emit_writeword(HOST_CCREG,(int)&Count);
5490 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5491 emit_writeword(ECX,(int)&last_count);
5494 emit_storereg(CCREG,HOST_CCREG);
5495 emit_call((int)get_addr);
5496 emit_loadreg(CCREG,HOST_CCREG);
5497 emit_addimm(ESP,4,ESP);
5499 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5500 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5504 void cjump_assemble(int i,struct regstat *i_regs)
5506 signed char *i_regmap=i_regs->regmap;
5509 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5510 assem_debug("match=%d\n",match);
5511 int s1h,s1l,s2h,s2l;
5512 int prev_cop1_usable=cop1_usable;
5513 int unconditional=0,nop=0;
5516 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5517 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5518 if(!match) invert=1;
5519 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5520 if(i>(ba[i]-start)>>2) invert=1;
5524 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5525 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5526 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5527 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5530 s1l=get_reg(i_regmap,rs1[i]);
5531 s1h=get_reg(i_regmap,rs1[i]|64);
5532 s2l=get_reg(i_regmap,rs2[i]);
5533 s2h=get_reg(i_regmap,rs2[i]|64);
5535 if(rs1[i]==0&&rs2[i]==0)
5537 if(opcode[i]&1) nop=1;
5538 else unconditional=1;
5539 //assert(opcode[i]!=5);
5540 //assert(opcode[i]!=7);
5541 //assert(opcode[i]!=0x15);
5542 //assert(opcode[i]!=0x17);
5548 only32=(regs[i].was32>>rs2[i])&1;
5553 only32=(regs[i].was32>>rs1[i])&1;
5556 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5560 // Out of order execution (delay slot first)
5562 address_generation(i+1,i_regs,regs[i].regmap_entry);
5563 ds_assemble(i+1,i_regs);
5565 uint64_t bc_unneeded=branch_regs[i].u;
5566 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5567 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5568 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5570 bc_unneeded_upper|=1;
5571 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5572 bc_unneeded,bc_unneeded_upper);
5573 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5574 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5575 cc=get_reg(branch_regs[i].regmap,CCREG);
5576 assert(cc==HOST_CCREG);
5578 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5579 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5580 //assem_debug("cycle count (adj)\n");
5582 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5583 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5584 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5585 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5587 assem_debug("branch: internal\n");
5589 assem_debug("branch: external\n");
5590 if(internal&&is_ds[(ba[i]-start)>>2]) {
5591 ds_assemble_entry(i);
5594 add_to_linker((int)out,ba[i],internal);
5597 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5598 if(((u_int)out)&7) emit_addnop(0);
5603 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5606 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5609 int taken=0,nottaken=0,nottaken1=0;
5610 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5611 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5615 if(opcode[i]==4) // BEQ
5617 if(s2h>=0) emit_cmp(s1h,s2h);
5618 else emit_test(s1h,s1h);
5622 if(opcode[i]==5) // BNE
5624 if(s2h>=0) emit_cmp(s1h,s2h);
5625 else emit_test(s1h,s1h);
5626 if(invert) taken=(int)out;
5627 else add_to_linker((int)out,ba[i],internal);
5630 if(opcode[i]==6) // BLEZ
5633 if(invert) taken=(int)out;
5634 else add_to_linker((int)out,ba[i],internal);
5639 if(opcode[i]==7) // BGTZ
5644 if(invert) taken=(int)out;
5645 else add_to_linker((int)out,ba[i],internal);
5650 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5652 if(opcode[i]==4) // BEQ
5654 if(s2l>=0) emit_cmp(s1l,s2l);
5655 else emit_test(s1l,s1l);
5660 add_to_linker((int)out,ba[i],internal);
5664 if(opcode[i]==5) // BNE
5666 if(s2l>=0) emit_cmp(s1l,s2l);
5667 else emit_test(s1l,s1l);
5672 add_to_linker((int)out,ba[i],internal);
5676 if(opcode[i]==6) // BLEZ
5683 add_to_linker((int)out,ba[i],internal);
5687 if(opcode[i]==7) // BGTZ
5694 add_to_linker((int)out,ba[i],internal);
5699 if(taken) set_jump_target(taken,(int)out);
5700 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5701 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5703 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5704 add_to_linker((int)out,ba[i],internal);
5707 add_to_linker((int)out,ba[i],internal*2);
5713 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5714 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5715 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5717 assem_debug("branch: internal\n");
5719 assem_debug("branch: external\n");
5720 if(internal&&is_ds[(ba[i]-start)>>2]) {
5721 ds_assemble_entry(i);
5724 add_to_linker((int)out,ba[i],internal);
5728 set_jump_target(nottaken,(int)out);
5731 if(nottaken1) set_jump_target(nottaken1,(int)out);
5733 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5735 } // (!unconditional)
5739 // In-order execution (branch first)
5740 //if(likely[i]) printf("IOL\n");
5743 int taken=0,nottaken=0,nottaken1=0;
5744 if(!unconditional&&!nop) {
5748 if((opcode[i]&0x2f)==4) // BEQ
5750 if(s2h>=0) emit_cmp(s1h,s2h);
5751 else emit_test(s1h,s1h);
5755 if((opcode[i]&0x2f)==5) // BNE
5757 if(s2h>=0) emit_cmp(s1h,s2h);
5758 else emit_test(s1h,s1h);
5762 if((opcode[i]&0x2f)==6) // BLEZ
5770 if((opcode[i]&0x2f)==7) // BGTZ
5780 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5782 if((opcode[i]&0x2f)==4) // BEQ
5784 if(s2l>=0) emit_cmp(s1l,s2l);
5785 else emit_test(s1l,s1l);
5789 if((opcode[i]&0x2f)==5) // BNE
5791 if(s2l>=0) emit_cmp(s1l,s2l);
5792 else emit_test(s1l,s1l);
5796 if((opcode[i]&0x2f)==6) // BLEZ
5802 if((opcode[i]&0x2f)==7) // BGTZ
5808 } // if(!unconditional)
5810 uint64_t ds_unneeded=branch_regs[i].u;
5811 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5812 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5813 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5814 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5816 ds_unneeded_upper|=1;
5819 if(taken) set_jump_target(taken,(int)out);
5820 assem_debug("1:\n");
5821 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5822 ds_unneeded,ds_unneeded_upper);
5824 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5825 address_generation(i+1,&branch_regs[i],0);
5826 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5827 ds_assemble(i+1,&branch_regs[i]);
5828 cc=get_reg(branch_regs[i].regmap,CCREG);
5830 emit_loadreg(CCREG,cc=HOST_CCREG);
5831 // CHECK: Is the following instruction (fall thru) allocated ok?
5833 assert(cc==HOST_CCREG);
5834 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5835 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5836 assem_debug("cycle count (adj)\n");
5837 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5838 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5840 assem_debug("branch: internal\n");
5842 assem_debug("branch: external\n");
5843 if(internal&&is_ds[(ba[i]-start)>>2]) {
5844 ds_assemble_entry(i);
5847 add_to_linker((int)out,ba[i],internal);
5852 cop1_usable=prev_cop1_usable;
5853 if(!unconditional) {
5854 if(nottaken1) set_jump_target(nottaken1,(int)out);
5855 set_jump_target(nottaken,(int)out);
5856 assem_debug("2:\n");
5858 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5859 ds_unneeded,ds_unneeded_upper);
5860 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5861 address_generation(i+1,&branch_regs[i],0);
5862 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5863 ds_assemble(i+1,&branch_regs[i]);
5865 cc=get_reg(branch_regs[i].regmap,CCREG);
5866 if(cc==-1&&!likely[i]) {
5867 // Cycle count isn't in a register, temporarily load it then write it out
5868 emit_loadreg(CCREG,HOST_CCREG);
5869 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5872 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5873 emit_storereg(CCREG,HOST_CCREG);
5876 cc=get_reg(i_regmap,CCREG);
5877 assert(cc==HOST_CCREG);
5878 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5881 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5887 void sjump_assemble(int i,struct regstat *i_regs)
5889 signed char *i_regmap=i_regs->regmap;
5892 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5893 assem_debug("smatch=%d\n",match);
5895 int prev_cop1_usable=cop1_usable;
5896 int unconditional=0,nevertaken=0;
5899 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5900 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5901 if(!match) invert=1;
5902 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5903 if(i>(ba[i]-start)>>2) invert=1;
5906 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5907 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5910 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5911 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5914 s1l=get_reg(i_regmap,rs1[i]);
5915 s1h=get_reg(i_regmap,rs1[i]|64);
5919 if(opcode2[i]&1) unconditional=1;
5921 // These are never taken (r0 is never less than zero)
5922 //assert(opcode2[i]!=0);
5923 //assert(opcode2[i]!=2);
5924 //assert(opcode2[i]!=0x10);
5925 //assert(opcode2[i]!=0x12);
5928 only32=(regs[i].was32>>rs1[i])&1;
5932 // Out of order execution (delay slot first)
5934 address_generation(i+1,i_regs,regs[i].regmap_entry);
5935 ds_assemble(i+1,i_regs);
5937 uint64_t bc_unneeded=branch_regs[i].u;
5938 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5939 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5940 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5942 bc_unneeded_upper|=1;
5943 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5944 bc_unneeded,bc_unneeded_upper);
5945 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5946 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5948 int rt,return_address;
5949 rt=get_reg(branch_regs[i].regmap,31);
5950 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5952 // Save the PC even if the branch is not taken
5953 return_address=start+i*4+8;
5954 emit_movimm(return_address,rt); // PC into link register
5956 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5960 cc=get_reg(branch_regs[i].regmap,CCREG);
5961 assert(cc==HOST_CCREG);
5963 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5964 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5965 assem_debug("cycle count (adj)\n");
5967 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5968 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5969 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5970 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5972 assem_debug("branch: internal\n");
5974 assem_debug("branch: external\n");
5975 if(internal&&is_ds[(ba[i]-start)>>2]) {
5976 ds_assemble_entry(i);
5979 add_to_linker((int)out,ba[i],internal);
5982 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5983 if(((u_int)out)&7) emit_addnop(0);
5987 else if(nevertaken) {
5988 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5991 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5995 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5996 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6000 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6007 add_to_linker((int)out,ba[i],internal);
6011 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6018 add_to_linker((int)out,ba[i],internal);
6026 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6033 add_to_linker((int)out,ba[i],internal);
6037 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6044 add_to_linker((int)out,ba[i],internal);
6051 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6052 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6054 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6055 add_to_linker((int)out,ba[i],internal);
6058 add_to_linker((int)out,ba[i],internal*2);
6064 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6065 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6066 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6068 assem_debug("branch: internal\n");
6070 assem_debug("branch: external\n");
6071 if(internal&&is_ds[(ba[i]-start)>>2]) {
6072 ds_assemble_entry(i);
6075 add_to_linker((int)out,ba[i],internal);
6079 set_jump_target(nottaken,(int)out);
6083 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6085 } // (!unconditional)
6089 // In-order execution (branch first)
6093 int rt,return_address;
6094 rt=get_reg(branch_regs[i].regmap,31);
6096 // Save the PC even if the branch is not taken
6097 return_address=start+i*4+8;
6098 emit_movimm(return_address,rt); // PC into link register
6100 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6104 if(!unconditional) {
6105 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6109 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6115 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6125 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6131 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6138 } // if(!unconditional)
6140 uint64_t ds_unneeded=branch_regs[i].u;
6141 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6142 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6143 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6144 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6146 ds_unneeded_upper|=1;
6149 //assem_debug("1:\n");
6150 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6151 ds_unneeded,ds_unneeded_upper);
6153 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6154 address_generation(i+1,&branch_regs[i],0);
6155 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6156 ds_assemble(i+1,&branch_regs[i]);
6157 cc=get_reg(branch_regs[i].regmap,CCREG);
6159 emit_loadreg(CCREG,cc=HOST_CCREG);
6160 // CHECK: Is the following instruction (fall thru) allocated ok?
6162 assert(cc==HOST_CCREG);
6163 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6164 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6165 assem_debug("cycle count (adj)\n");
6166 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6167 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6169 assem_debug("branch: internal\n");
6171 assem_debug("branch: external\n");
6172 if(internal&&is_ds[(ba[i]-start)>>2]) {
6173 ds_assemble_entry(i);
6176 add_to_linker((int)out,ba[i],internal);
6181 cop1_usable=prev_cop1_usable;
6182 if(!unconditional) {
6183 set_jump_target(nottaken,(int)out);
6184 assem_debug("1:\n");
6186 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6187 ds_unneeded,ds_unneeded_upper);
6188 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6189 address_generation(i+1,&branch_regs[i],0);
6190 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6191 ds_assemble(i+1,&branch_regs[i]);
6193 cc=get_reg(branch_regs[i].regmap,CCREG);
6194 if(cc==-1&&!likely[i]) {
6195 // Cycle count isn't in a register, temporarily load it then write it out
6196 emit_loadreg(CCREG,HOST_CCREG);
6197 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6200 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6201 emit_storereg(CCREG,HOST_CCREG);
6204 cc=get_reg(i_regmap,CCREG);
6205 assert(cc==HOST_CCREG);
6206 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6209 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6215 void fjump_assemble(int i,struct regstat *i_regs)
6217 signed char *i_regmap=i_regs->regmap;
6220 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6221 assem_debug("fmatch=%d\n",match);
6225 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6226 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6227 if(!match) invert=1;
6228 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6229 if(i>(ba[i]-start)>>2) invert=1;
6233 fs=get_reg(branch_regs[i].regmap,FSREG);
6234 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6237 fs=get_reg(i_regmap,FSREG);
6240 // Check cop1 unusable
6242 cs=get_reg(i_regmap,CSREG);
6244 emit_testimm(cs,0x20000000);
6247 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6252 // Out of order execution (delay slot first)
6254 ds_assemble(i+1,i_regs);
6256 uint64_t bc_unneeded=branch_regs[i].u;
6257 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6258 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6259 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6261 bc_unneeded_upper|=1;
6262 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6263 bc_unneeded,bc_unneeded_upper);
6264 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6265 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6266 cc=get_reg(branch_regs[i].regmap,CCREG);
6267 assert(cc==HOST_CCREG);
6268 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6269 assem_debug("cycle count (adj)\n");
6272 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6275 emit_testimm(fs,0x800000);
6276 if(source[i]&0x10000) // BC1T
6282 add_to_linker((int)out,ba[i],internal);
6291 add_to_linker((int)out,ba[i],internal);
6299 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6300 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6301 else if(match) emit_addnop(13);
6303 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6304 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6306 assem_debug("branch: internal\n");
6308 assem_debug("branch: external\n");
6309 if(internal&&is_ds[(ba[i]-start)>>2]) {
6310 ds_assemble_entry(i);
6313 add_to_linker((int)out,ba[i],internal);
6316 set_jump_target(nottaken,(int)out);
6320 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6322 } // (!unconditional)
6326 // In-order execution (branch first)
6330 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6333 emit_testimm(fs,0x800000);
6334 if(source[i]&0x10000) // BC1T
6345 } // if(!unconditional)
6347 uint64_t ds_unneeded=branch_regs[i].u;
6348 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6349 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6350 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6351 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6353 ds_unneeded_upper|=1;
6355 //assem_debug("1:\n");
6356 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6357 ds_unneeded,ds_unneeded_upper);
6359 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6360 address_generation(i+1,&branch_regs[i],0);
6361 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6362 ds_assemble(i+1,&branch_regs[i]);
6363 cc=get_reg(branch_regs[i].regmap,CCREG);
6365 emit_loadreg(CCREG,cc=HOST_CCREG);
6366 // CHECK: Is the following instruction (fall thru) allocated ok?
6368 assert(cc==HOST_CCREG);
6369 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6370 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6371 assem_debug("cycle count (adj)\n");
6372 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6373 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6375 assem_debug("branch: internal\n");
6377 assem_debug("branch: external\n");
6378 if(internal&&is_ds[(ba[i]-start)>>2]) {
6379 ds_assemble_entry(i);
6382 add_to_linker((int)out,ba[i],internal);
6387 if(1) { // <- FIXME (don't need this)
6388 set_jump_target(nottaken,(int)out);
6389 assem_debug("1:\n");
6391 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6392 ds_unneeded,ds_unneeded_upper);
6393 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6394 address_generation(i+1,&branch_regs[i],0);
6395 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6396 ds_assemble(i+1,&branch_regs[i]);
6398 cc=get_reg(branch_regs[i].regmap,CCREG);
6399 if(cc==-1&&!likely[i]) {
6400 // Cycle count isn't in a register, temporarily load it then write it out
6401 emit_loadreg(CCREG,HOST_CCREG);
6402 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6405 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6406 emit_storereg(CCREG,HOST_CCREG);
6409 cc=get_reg(i_regmap,CCREG);
6410 assert(cc==HOST_CCREG);
6411 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6414 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6420 static void pagespan_assemble(int i,struct regstat *i_regs)
6422 int s1l=get_reg(i_regs->regmap,rs1[i]);
6423 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6424 int s2l=get_reg(i_regs->regmap,rs2[i]);
6425 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6426 void *nt_branch=NULL;
6429 int unconditional=0;
6439 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6443 int addr,alt,ntaddr;
6444 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6448 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6449 (i_regs->regmap[hr]&63)!=rs1[i] &&
6450 (i_regs->regmap[hr]&63)!=rs2[i] )
6459 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6460 (i_regs->regmap[hr]&63)!=rs1[i] &&
6461 (i_regs->regmap[hr]&63)!=rs2[i] )
6467 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6471 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6472 (i_regs->regmap[hr]&63)!=rs1[i] &&
6473 (i_regs->regmap[hr]&63)!=rs2[i] )
6480 assert(hr<HOST_REGS);
6481 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6482 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6484 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6485 if(opcode[i]==2) // J
6489 if(opcode[i]==3) // JAL
6492 int rt=get_reg(i_regs->regmap,31);
6493 emit_movimm(start+i*4+8,rt);
6496 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6499 if(opcode2[i]==9) // JALR
6501 int rt=get_reg(i_regs->regmap,rt1[i]);
6502 emit_movimm(start+i*4+8,rt);
6505 if((opcode[i]&0x3f)==4) // BEQ
6512 #ifdef HAVE_CMOV_IMM
6514 if(s2l>=0) emit_cmp(s1l,s2l);
6515 else emit_test(s1l,s1l);
6516 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6522 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6524 if(s2h>=0) emit_cmp(s1h,s2h);
6525 else emit_test(s1h,s1h);
6526 emit_cmovne_reg(alt,addr);
6528 if(s2l>=0) emit_cmp(s1l,s2l);
6529 else emit_test(s1l,s1l);
6530 emit_cmovne_reg(alt,addr);
6533 if((opcode[i]&0x3f)==5) // BNE
6535 #ifdef HAVE_CMOV_IMM
6537 if(s2l>=0) emit_cmp(s1l,s2l);
6538 else emit_test(s1l,s1l);
6539 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6545 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6547 if(s2h>=0) emit_cmp(s1h,s2h);
6548 else emit_test(s1h,s1h);
6549 emit_cmovne_reg(alt,addr);
6551 if(s2l>=0) emit_cmp(s1l,s2l);
6552 else emit_test(s1l,s1l);
6553 emit_cmovne_reg(alt,addr);
6556 if((opcode[i]&0x3f)==0x14) // BEQL
6559 if(s2h>=0) emit_cmp(s1h,s2h);
6560 else emit_test(s1h,s1h);
6564 if(s2l>=0) emit_cmp(s1l,s2l);
6565 else emit_test(s1l,s1l);
6566 if(nottaken) set_jump_target(nottaken,(int)out);
6570 if((opcode[i]&0x3f)==0x15) // BNEL
6573 if(s2h>=0) emit_cmp(s1h,s2h);
6574 else emit_test(s1h,s1h);
6578 if(s2l>=0) emit_cmp(s1l,s2l);
6579 else emit_test(s1l,s1l);
6582 if(taken) set_jump_target(taken,(int)out);
6584 if((opcode[i]&0x3f)==6) // BLEZ
6586 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6588 if(s1h>=0) emit_mov(addr,ntaddr);
6589 emit_cmovl_reg(alt,addr);
6592 emit_cmovne_reg(ntaddr,addr);
6593 emit_cmovs_reg(alt,addr);
6596 if((opcode[i]&0x3f)==7) // BGTZ
6598 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6600 if(s1h>=0) emit_mov(addr,alt);
6601 emit_cmovl_reg(ntaddr,addr);
6604 emit_cmovne_reg(alt,addr);
6605 emit_cmovs_reg(ntaddr,addr);
6608 if((opcode[i]&0x3f)==0x16) // BLEZL
6610 assert((opcode[i]&0x3f)!=0x16);
6612 if((opcode[i]&0x3f)==0x17) // BGTZL
6614 assert((opcode[i]&0x3f)!=0x17);
6616 assert(opcode[i]!=1); // BLTZ/BGEZ
6618 //FIXME: Check CSREG
6619 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6620 if((source[i]&0x30000)==0) // BC1F
6622 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6623 emit_testimm(s1l,0x800000);
6624 emit_cmovne_reg(alt,addr);
6626 if((source[i]&0x30000)==0x10000) // BC1T
6628 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6629 emit_testimm(s1l,0x800000);
6630 emit_cmovne_reg(alt,addr);
6632 if((source[i]&0x30000)==0x20000) // BC1FL
6634 emit_testimm(s1l,0x800000);
6638 if((source[i]&0x30000)==0x30000) // BC1TL
6640 emit_testimm(s1l,0x800000);
6646 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6647 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6648 if(likely[i]||unconditional)
6650 emit_movimm(ba[i],HOST_BTREG);
6652 else if(addr!=HOST_BTREG)
6654 emit_mov(addr,HOST_BTREG);
6656 void *branch_addr=out;
6658 int target_addr=start+i*4+5;
6660 void *compiled_target_addr=check_addr(target_addr);
6661 emit_extjump_ds((int)branch_addr,target_addr);
6662 if(compiled_target_addr) {
6663 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6664 add_link(target_addr,stub);
6666 else set_jump_target((int)branch_addr,(int)stub);
6669 set_jump_target((int)nottaken,(int)out);
6670 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6671 void *branch_addr=out;
6673 int target_addr=start+i*4+8;
6675 void *compiled_target_addr=check_addr(target_addr);
6676 emit_extjump_ds((int)branch_addr,target_addr);
6677 if(compiled_target_addr) {
6678 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6679 add_link(target_addr,stub);
6681 else set_jump_target((int)branch_addr,(int)stub);
6685 // Assemble the delay slot for the above
6686 static void pagespan_ds()
6688 assem_debug("initial delay slot:\n");
6689 u_int vaddr=start+1;
6690 u_int page=get_page(vaddr);
6691 u_int vpage=get_vpage(vaddr);
6692 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6694 ll_add(jump_in+page,vaddr,(void *)out);
6695 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6696 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6697 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6698 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6699 emit_writeword(HOST_BTREG,(int)&branch_target);
6700 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6701 address_generation(0,®s[0],regs[0].regmap_entry);
6702 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6703 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6708 alu_assemble(0,®s[0]);break;
6710 imm16_assemble(0,®s[0]);break;
6712 shift_assemble(0,®s[0]);break;
6714 shiftimm_assemble(0,®s[0]);break;
6716 load_assemble(0,®s[0]);break;
6718 loadlr_assemble(0,®s[0]);break;
6720 store_assemble(0,®s[0]);break;
6722 storelr_assemble(0,®s[0]);break;
6724 cop0_assemble(0,®s[0]);break;
6726 cop1_assemble(0,®s[0]);break;
6728 c1ls_assemble(0,®s[0]);break;
6730 cop2_assemble(0,®s[0]);break;
6732 c2ls_assemble(0,®s[0]);break;
6734 c2op_assemble(0,®s[0]);break;
6736 fconv_assemble(0,®s[0]);break;
6738 float_assemble(0,®s[0]);break;
6740 fcomp_assemble(0,®s[0]);break;
6742 multdiv_assemble(0,®s[0]);break;
6744 mov_assemble(0,®s[0]);break;
6754 printf("Jump in the delay slot. This is probably a bug.\n");
6756 int btaddr=get_reg(regs[0].regmap,BTREG);
6758 btaddr=get_reg(regs[0].regmap,-1);
6759 emit_readword((int)&branch_target,btaddr);
6761 assert(btaddr!=HOST_CCREG);
6762 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6764 emit_movimm(start+4,HOST_TEMPREG);
6765 emit_cmp(btaddr,HOST_TEMPREG);
6767 emit_cmpimm(btaddr,start+4);
6769 int branch=(int)out;
6771 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6772 emit_jmp(jump_vaddr_reg[btaddr]);
6773 set_jump_target(branch,(int)out);
6774 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6775 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6778 // Basic liveness analysis for MIPS registers
6779 void unneeded_registers(int istart,int iend,int r)
6782 uint64_t u,uu,gte_u,b,bu,gte_bu;
6783 uint64_t temp_u,temp_uu,temp_gte_u=0;
6785 uint64_t gte_u_unknown=0;
6786 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6790 gte_u=gte_u_unknown;
6792 u=unneeded_reg[iend+1];
6793 uu=unneeded_reg_upper[iend+1];
6795 gte_u=gte_unneeded[iend+1];
6798 for (i=iend;i>=istart;i--)
6800 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6801 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6803 // If subroutine call, flag return address as a possible branch target
6804 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6806 if(ba[i]<start || ba[i]>=(start+slen*4))
6808 // Branch out of this block, flush all regs
6811 gte_u=gte_u_unknown;
6813 if(itype[i]==UJUMP&&rt1[i]==31)
6815 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6817 if(itype[i]==RJUMP&&rs1[i]==31)
6819 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6821 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6822 if(itype[i]==UJUMP&&rt1[i]==31)
6824 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6825 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6827 if(itype[i]==RJUMP&&rs1[i]==31)
6829 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6830 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6833 branch_unneeded_reg[i]=u;
6834 branch_unneeded_reg_upper[i]=uu;
6835 // Merge in delay slot
6836 tdep=(~uu>>rt1[i+1])&1;
6837 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6838 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6839 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6840 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6841 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6844 gte_u&=~gte_rs[i+1];
6845 // If branch is "likely" (and conditional)
6846 // then we skip the delay slot on the fall-thru path
6849 u&=unneeded_reg[i+2];
6850 uu&=unneeded_reg_upper[i+2];
6851 gte_u&=gte_unneeded[i+2];
6857 gte_u=gte_u_unknown;
6863 // Internal branch, flag target
6864 bt[(ba[i]-start)>>2]=1;
6865 if(ba[i]<=start+i*4) {
6867 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6869 // Unconditional branch
6873 // Conditional branch (not taken case)
6874 temp_u=unneeded_reg[i+2];
6875 temp_uu=unneeded_reg_upper[i+2];
6876 temp_gte_u&=gte_unneeded[i+2];
6878 // Merge in delay slot
6879 tdep=(~temp_uu>>rt1[i+1])&1;
6880 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6881 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6882 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6883 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6884 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6885 temp_u|=1;temp_uu|=1;
6886 temp_gte_u|=gte_rt[i+1];
6887 temp_gte_u&=~gte_rs[i+1];
6888 // If branch is "likely" (and conditional)
6889 // then we skip the delay slot on the fall-thru path
6892 temp_u&=unneeded_reg[i+2];
6893 temp_uu&=unneeded_reg_upper[i+2];
6894 temp_gte_u&=gte_unneeded[i+2];
6900 temp_gte_u=gte_u_unknown;
6903 tdep=(~temp_uu>>rt1[i])&1;
6904 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6905 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6906 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6907 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6908 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6909 temp_u|=1;temp_uu|=1;
6910 temp_gte_u|=gte_rt[i];
6911 temp_gte_u&=~gte_rs[i];
6912 unneeded_reg[i]=temp_u;
6913 unneeded_reg_upper[i]=temp_uu;
6914 gte_unneeded[i]=temp_gte_u;
6915 // Only go three levels deep. This recursion can take an
6916 // excessive amount of time if there are a lot of nested loops.
6918 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6920 unneeded_reg[(ba[i]-start)>>2]=1;
6921 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6922 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6925 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6927 // Unconditional branch
6928 u=unneeded_reg[(ba[i]-start)>>2];
6929 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6930 gte_u=gte_unneeded[(ba[i]-start)>>2];
6931 branch_unneeded_reg[i]=u;
6932 branch_unneeded_reg_upper[i]=uu;
6935 //branch_unneeded_reg[i]=u;
6936 //branch_unneeded_reg_upper[i]=uu;
6937 // Merge in delay slot
6938 tdep=(~uu>>rt1[i+1])&1;
6939 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6940 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6941 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6942 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6943 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6946 gte_u&=~gte_rs[i+1];
6948 // Conditional branch
6949 b=unneeded_reg[(ba[i]-start)>>2];
6950 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6951 gte_bu=gte_unneeded[(ba[i]-start)>>2];
6952 branch_unneeded_reg[i]=b;
6953 branch_unneeded_reg_upper[i]=bu;
6956 //branch_unneeded_reg[i]=b;
6957 //branch_unneeded_reg_upper[i]=bu;
6958 // Branch delay slot
6959 tdep=(~uu>>rt1[i+1])&1;
6960 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6961 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6962 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6963 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6964 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6966 gte_bu|=gte_rt[i+1];
6967 gte_bu&=~gte_rs[i+1];
6968 // If branch is "likely" then we skip the
6969 // delay slot on the fall-thru path
6975 u&=unneeded_reg[i+2];
6976 uu&=unneeded_reg_upper[i+2];
6977 gte_u&=gte_unneeded[i+2];
6989 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6990 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6991 //branch_unneeded_reg[i]=1;
6992 //branch_unneeded_reg_upper[i]=1;
6994 branch_unneeded_reg[i]=1;
6995 branch_unneeded_reg_upper[i]=1;
7001 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7003 // SYSCALL instruction (software interrupt)
7007 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7009 // ERET instruction (return from interrupt)
7014 tdep=(~uu>>rt1[i])&1;
7015 // Written registers are unneeded
7021 // Accessed registers are needed
7027 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
7028 gte_u|=gte_rs[i]; // MFC2/CFC2 to dead register, unneeded
7029 // Source-target dependencies
7030 uu&=~(tdep<<dep1[i]);
7031 uu&=~(tdep<<dep2[i]);
7032 // R0 is always unneeded
7036 unneeded_reg_upper[i]=uu;
7037 gte_unneeded[i]=gte_u;
7039 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7042 for(r=1;r<=CCREG;r++) {
7043 if((unneeded_reg[i]>>r)&1) {
7044 if(r==HIREG) printf(" HI");
7045 else if(r==LOREG) printf(" LO");
7046 else printf(" r%d",r);
7050 for(r=1;r<=CCREG;r++) {
7051 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7052 if(r==HIREG) printf(" HI");
7053 else if(r==LOREG) printf(" LO");
7054 else printf(" r%d",r);
7060 for (i=iend;i>=istart;i--)
7062 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7067 // Identify registers which are likely to contain 32-bit values
7068 // This is used to predict whether any branches will jump to a
7069 // location with 64-bit values in registers.
7070 static void provisional_32bit()
7074 uint64_t lastbranch=1;
7079 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7080 if(i>1) is32=lastbranch;
7086 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7088 if(i>2) is32=lastbranch;
7092 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7094 if(rs1[i-2]==0||rs2[i-2]==0)
7097 is32|=1LL<<rs1[i-2];
7100 is32|=1LL<<rs2[i-2];
7105 // If something jumps here with 64-bit values
7106 // then promote those registers to 64 bits
7109 uint64_t temp_is32=is32;
7112 if(ba[j]==start+i*4)
7113 //temp_is32&=branch_regs[j].is32;
7118 if(ba[j]==start+i*4)
7129 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7130 // Branches don't write registers, consider the delay slot instead.
7141 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7142 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7151 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7152 if(op==0x22) is32|=1LL<<rt; // LWL
7155 if (op==0x08||op==0x09|| // ADDI/ADDIU
7156 op==0x0a||op==0x0b|| // SLTI/SLTIU
7162 if(op==0x18||op==0x19) { // DADDI/DADDIU
7165 // is32|=((is32>>s1)&1LL)<<rt;
7167 if(op==0x0d||op==0x0e) { // ORI/XORI
7168 uint64_t sr=((is32>>s1)&1LL);
7184 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7187 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7190 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7191 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7195 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7200 uint64_t sr=((is32>>s1)&1LL);
7205 uint64_t sr=((is32>>s2)&1LL);
7213 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7218 uint64_t sr=((is32>>s1)&1LL);
7228 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7229 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7232 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7237 uint64_t sr=((is32>>s1)&1LL);
7243 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7244 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7248 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7249 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7252 if(op2==0) is32|=1LL<<rt; // MFC0
7256 if(op2==0) is32|=1LL<<rt; // MFC1
7257 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7258 if(op2==2) is32|=1LL<<rt; // CFC1
7280 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7282 if(rt1[i-1]==31) // JAL/JALR
7284 // Subroutine call will return here, don't alloc any registers
7289 // Internal branch will jump here, match registers to caller
7297 // Identify registers which may be assumed to contain 32-bit values
7298 // and where optimizations will rely on this.
7299 // This is used to determine whether backward branches can safely
7300 // jump to a location with 64-bit values in registers.
7301 static void provisional_r32()
7306 for (i=slen-1;i>=0;i--)
7309 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7311 if(ba[i]<start || ba[i]>=(start+slen*4))
7313 // Branch out of this block, don't need anything
7319 // Need whatever matches the target
7320 // (and doesn't get overwritten by the delay slot instruction)
7322 int t=(ba[i]-start)>>2;
7323 if(ba[i]>start+i*4) {
7325 //if(!(requires_32bit[t]&~regs[i].was32))
7326 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7327 if(!(pr32[t]&~regs[i].was32))
7328 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7331 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7332 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7335 // Conditional branch may need registers for following instructions
7336 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7339 //r32|=requires_32bit[i+2];
7342 // Mark this address as a branch target since it may be called
7343 // upon return from interrupt
7347 // Merge in delay slot
7349 // These are overwritten unless the branch is "likely"
7350 // and the delay slot is nullified if not taken
7351 r32&=~(1LL<<rt1[i+1]);
7352 r32&=~(1LL<<rt2[i+1]);
7354 // Assume these are needed (delay slot)
7357 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7361 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7363 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7365 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7367 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7369 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7372 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7374 // SYSCALL instruction (software interrupt)
7377 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7379 // ERET instruction (return from interrupt)
7383 r32&=~(1LL<<rt1[i]);
7384 r32&=~(1LL<<rt2[i]);
7387 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7391 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7393 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7395 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7397 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7399 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7401 //requires_32bit[i]=r32;
7404 // Dirty registers which are 32-bit, require 32-bit input
7405 // as they will be written as 32-bit values
7406 for(hr=0;hr<HOST_REGS;hr++)
7408 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7409 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7410 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7411 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7412 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7419 // Write back dirty registers as soon as we will no longer modify them,
7420 // so that we don't end up with lots of writes at the branches.
7421 void clean_registers(int istart,int iend,int wr)
7425 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7426 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7428 will_dirty_i=will_dirty_next=0;
7429 wont_dirty_i=wont_dirty_next=0;
7431 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7432 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7434 for (i=iend;i>=istart;i--)
7436 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7438 if(ba[i]<start || ba[i]>=(start+slen*4))
7440 // Branch out of this block, flush all regs
7441 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7443 // Unconditional branch
7446 // Merge in delay slot (will dirty)
7447 for(r=0;r<HOST_REGS;r++) {
7448 if(r!=EXCLUDE_REG) {
7449 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7450 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7451 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7452 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7453 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7454 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7455 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7456 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7457 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7458 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7459 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7460 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7461 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7462 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7468 // Conditional branch
7470 wont_dirty_i=wont_dirty_next;
7471 // Merge in delay slot (will dirty)
7472 for(r=0;r<HOST_REGS;r++) {
7473 if(r!=EXCLUDE_REG) {
7475 // Might not dirty if likely branch is not taken
7476 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7477 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7478 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7479 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7480 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7481 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7482 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7483 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7484 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7485 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7486 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7487 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7488 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7489 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7494 // Merge in delay slot (wont dirty)
7495 for(r=0;r<HOST_REGS;r++) {
7496 if(r!=EXCLUDE_REG) {
7497 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7498 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7499 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7500 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7501 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7502 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7503 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7504 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7505 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7506 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7510 #ifndef DESTRUCTIVE_WRITEBACK
7511 branch_regs[i].dirty&=wont_dirty_i;
7513 branch_regs[i].dirty|=will_dirty_i;
7519 if(ba[i]<=start+i*4) {
7521 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7523 // Unconditional branch
7526 // Merge in delay slot (will dirty)
7527 for(r=0;r<HOST_REGS;r++) {
7528 if(r!=EXCLUDE_REG) {
7529 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7530 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7531 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7532 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7533 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7534 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7535 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7536 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7537 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7538 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7539 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7540 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7541 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7542 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7546 // Conditional branch (not taken case)
7547 temp_will_dirty=will_dirty_next;
7548 temp_wont_dirty=wont_dirty_next;
7549 // Merge in delay slot (will dirty)
7550 for(r=0;r<HOST_REGS;r++) {
7551 if(r!=EXCLUDE_REG) {
7553 // Will not dirty if likely branch is not taken
7554 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7555 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7556 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7557 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7558 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7559 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7560 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7561 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7562 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7563 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7564 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7565 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7566 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7567 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7572 // Merge in delay slot (wont dirty)
7573 for(r=0;r<HOST_REGS;r++) {
7574 if(r!=EXCLUDE_REG) {
7575 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7576 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7577 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7578 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7579 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7580 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7581 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7582 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7583 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7584 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7587 // Deal with changed mappings
7589 for(r=0;r<HOST_REGS;r++) {
7590 if(r!=EXCLUDE_REG) {
7591 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7592 temp_will_dirty&=~(1<<r);
7593 temp_wont_dirty&=~(1<<r);
7594 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7595 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7596 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7598 temp_will_dirty|=1<<r;
7599 temp_wont_dirty|=1<<r;
7606 will_dirty[i]=temp_will_dirty;
7607 wont_dirty[i]=temp_wont_dirty;
7608 clean_registers((ba[i]-start)>>2,i-1,0);
7610 // Limit recursion. It can take an excessive amount
7611 // of time if there are a lot of nested loops.
7612 will_dirty[(ba[i]-start)>>2]=0;
7613 wont_dirty[(ba[i]-start)>>2]=-1;
7618 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7620 // Unconditional branch
7623 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7624 for(r=0;r<HOST_REGS;r++) {
7625 if(r!=EXCLUDE_REG) {
7626 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7627 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7628 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7630 if(branch_regs[i].regmap[r]>=0) {
7631 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7632 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7637 // Merge in delay slot
7638 for(r=0;r<HOST_REGS;r++) {
7639 if(r!=EXCLUDE_REG) {
7640 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7641 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7642 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7643 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7644 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7645 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7646 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7647 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7648 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7649 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7650 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7651 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7652 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7653 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7657 // Conditional branch
7658 will_dirty_i=will_dirty_next;
7659 wont_dirty_i=wont_dirty_next;
7660 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7661 for(r=0;r<HOST_REGS;r++) {
7662 if(r!=EXCLUDE_REG) {
7663 signed char target_reg=branch_regs[i].regmap[r];
7664 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7665 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7666 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7668 else if(target_reg>=0) {
7669 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7670 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7672 // Treat delay slot as part of branch too
7673 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7674 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7675 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7679 will_dirty[i+1]&=~(1<<r);
7684 // Merge in delay slot
7685 for(r=0;r<HOST_REGS;r++) {
7686 if(r!=EXCLUDE_REG) {
7688 // Might not dirty if likely branch is not taken
7689 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7690 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7691 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7692 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7693 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7694 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7695 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7696 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7697 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7698 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7699 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7700 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7701 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7702 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7707 // Merge in delay slot (won't dirty)
7708 for(r=0;r<HOST_REGS;r++) {
7709 if(r!=EXCLUDE_REG) {
7710 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7711 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7712 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7713 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7714 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7715 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7716 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7717 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7718 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7719 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7723 #ifndef DESTRUCTIVE_WRITEBACK
7724 branch_regs[i].dirty&=wont_dirty_i;
7726 branch_regs[i].dirty|=will_dirty_i;
7731 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7733 // SYSCALL instruction (software interrupt)
7737 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7739 // ERET instruction (return from interrupt)
7743 will_dirty_next=will_dirty_i;
7744 wont_dirty_next=wont_dirty_i;
7745 for(r=0;r<HOST_REGS;r++) {
7746 if(r!=EXCLUDE_REG) {
7747 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7748 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7749 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7750 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7751 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7752 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7753 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7754 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7756 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7758 // Don't store a register immediately after writing it,
7759 // may prevent dual-issue.
7760 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7761 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7767 will_dirty[i]=will_dirty_i;
7768 wont_dirty[i]=wont_dirty_i;
7769 // Mark registers that won't be dirtied as not dirty
7771 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7772 for(r=0;r<HOST_REGS;r++) {
7773 if((will_dirty_i>>r)&1) {
7779 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7780 regs[i].dirty|=will_dirty_i;
7781 #ifndef DESTRUCTIVE_WRITEBACK
7782 regs[i].dirty&=wont_dirty_i;
7783 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7785 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7786 for(r=0;r<HOST_REGS;r++) {
7787 if(r!=EXCLUDE_REG) {
7788 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7789 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7790 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7798 for(r=0;r<HOST_REGS;r++) {
7799 if(r!=EXCLUDE_REG) {
7800 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7801 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7802 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7810 // Deal with changed mappings
7811 temp_will_dirty=will_dirty_i;
7812 temp_wont_dirty=wont_dirty_i;
7813 for(r=0;r<HOST_REGS;r++) {
7814 if(r!=EXCLUDE_REG) {
7816 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7818 #ifndef DESTRUCTIVE_WRITEBACK
7819 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7821 regs[i].wasdirty|=will_dirty_i&(1<<r);
7824 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7825 // Register moved to a different register
7826 will_dirty_i&=~(1<<r);
7827 wont_dirty_i&=~(1<<r);
7828 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7829 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7831 #ifndef DESTRUCTIVE_WRITEBACK
7832 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7834 regs[i].wasdirty|=will_dirty_i&(1<<r);
7838 will_dirty_i&=~(1<<r);
7839 wont_dirty_i&=~(1<<r);
7840 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7841 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7842 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7845 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7855 void disassemble_inst(int i)
7857 if (bt[i]) printf("*"); else printf(" ");
7860 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7862 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7864 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7866 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7868 if (opcode[i]==0x9&&rt1[i]!=31)
7869 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7871 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7874 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7876 if(opcode[i]==0xf) //LUI
7877 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7879 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7883 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7887 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7891 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7894 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7897 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7900 if((opcode2[i]&0x1d)==0x10)
7901 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7902 else if((opcode2[i]&0x1d)==0x11)
7903 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7905 printf (" %x: %s\n",start+i*4,insn[i]);
7909 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7910 else if(opcode2[i]==4)
7911 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7912 else printf (" %x: %s\n",start+i*4,insn[i]);
7916 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7917 else if(opcode2[i]>3)
7918 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7919 else printf (" %x: %s\n",start+i*4,insn[i]);
7923 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7924 else if(opcode2[i]>3)
7925 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7926 else printf (" %x: %s\n",start+i*4,insn[i]);
7929 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7932 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7935 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7938 //printf (" %s %8x\n",insn[i],source[i]);
7939 printf (" %x: %s\n",start+i*4,insn[i]);
7943 static void disassemble_inst(int i) {}
7946 // clear the state completely, instead of just marking
7947 // things invalid like invalidate_all_pages() does
7948 void new_dynarec_clear_full()
7951 out=(u_char *)BASE_ADDR;
7952 memset(invalid_code,1,sizeof(invalid_code));
7953 memset(hash_table,0xff,sizeof(hash_table));
7954 memset(mini_ht,-1,sizeof(mini_ht));
7955 memset(restore_candidate,0,sizeof(restore_candidate));
7956 memset(shadow,0,sizeof(shadow));
7958 expirep=16384; // Expiry pointer, +2 blocks
7959 pending_exception=0;
7962 inv_code_start=inv_code_end=~0;
7966 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7968 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7969 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7970 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7973 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7974 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7975 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7978 void new_dynarec_init()
7980 printf("Init new dynarec\n");
7981 out=(u_char *)BASE_ADDR;
7982 if (mmap (out, 1<<TARGET_SIZE_2,
7983 PROT_READ | PROT_WRITE | PROT_EXEC,
7984 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7985 -1, 0) <= 0) {printf("mmap() failed\n");}
7987 rdword=&readmem_dword;
7988 fake_pc.f.r.rs=&readmem_dword;
7989 fake_pc.f.r.rt=&readmem_dword;
7990 fake_pc.f.r.rd=&readmem_dword;
7993 cycle_multiplier=200;
7994 new_dynarec_clear_full();
7996 // Copy this into local area so we don't have to put it in every literal pool
7997 invc_ptr=invalid_code;
8000 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8001 writemem[n] = write_nomem_new;
8002 writememb[n] = write_nomemb_new;
8003 writememh[n] = write_nomemh_new;
8005 writememd[n] = write_nomemd_new;
8007 readmem[n] = read_nomem_new;
8008 readmemb[n] = read_nomemb_new;
8009 readmemh[n] = read_nomemh_new;
8011 readmemd[n] = read_nomemd_new;
8014 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8015 writemem[n] = write_rdram_new;
8016 writememb[n] = write_rdramb_new;
8017 writememh[n] = write_rdramh_new;
8019 writememd[n] = write_rdramd_new;
8022 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8023 writemem[n] = write_nomem_new;
8024 writememb[n] = write_nomemb_new;
8025 writememh[n] = write_nomemh_new;
8027 writememd[n] = write_nomemd_new;
8029 readmem[n] = read_nomem_new;
8030 readmemb[n] = read_nomemb_new;
8031 readmemh[n] = read_nomemh_new;
8033 readmemd[n] = read_nomemd_new;
8041 void new_dynarec_cleanup()
8044 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
8045 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8046 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8047 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8049 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8053 int new_recompile_block(int addr)
8056 if(addr==0x800cd050) {
8058 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8060 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8063 //if(Count==365117028) tracedebug=1;
8064 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8065 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8066 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8068 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8069 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8070 /*if(Count>=312978186) {
8074 start = (u_int)addr&~3;
8075 //assert(((u_int)addr&1)==0);
8076 new_dynarec_did_compile=1;
8078 if (Config.HLE && start == 0x80001000) // hlecall
8080 // XXX: is this enough? Maybe check hleSoftCall?
8081 u_int beginning=(u_int)out;
8082 u_int page=get_page(start);
8083 invalid_code[start>>12]=0;
8084 emit_movimm(start,0);
8085 emit_writeword(0,(int)&pcaddr);
8086 emit_jmp((int)new_dyna_leave);
8089 __clear_cache((void *)beginning,out);
8091 ll_add(jump_in+page,start,(void *)beginning);
8094 else if ((u_int)addr < 0x00200000 ||
8095 (0xa0000000 <= addr && addr < 0xa0200000)) {
8096 // used for BIOS calls mostly?
8097 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8098 pagelimit = (addr&0xa0000000)|0x00200000;
8100 else if (!Config.HLE && (
8101 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8102 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8104 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8105 pagelimit = (addr&0xfff00000)|0x80000;
8110 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8111 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8112 pagelimit = 0xa4001000;
8116 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8117 source = (u_int *)((u_int)rdram+start-0x80000000);
8118 pagelimit = 0x80000000+RAM_SIZE;
8121 else if ((signed int)addr >= (signed int)0xC0000000) {
8122 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8123 //if(tlb_LUT_r[start>>12])
8124 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8125 if((signed int)memory_map[start>>12]>=0) {
8126 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8127 pagelimit=(start+4096)&0xFFFFF000;
8128 int map=memory_map[start>>12];
8131 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8132 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8134 assem_debug("pagelimit=%x\n",pagelimit);
8135 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8138 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8139 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8140 return -1; // Caller will invoke exception handler
8142 //printf("source= %x\n",(int)source);
8146 printf("Compile at bogus memory address: %x \n", (int)addr);
8150 /* Pass 1: disassemble */
8151 /* Pass 2: register dependencies, branch targets */
8152 /* Pass 3: register allocation */
8153 /* Pass 4: branch dependencies */
8154 /* Pass 5: pre-alloc */
8155 /* Pass 6: optimize clean/dirty state */
8156 /* Pass 7: flag 32-bit registers */
8157 /* Pass 8: assembly */
8158 /* Pass 9: linker */
8159 /* Pass 10: garbage collection / free memory */
8163 unsigned int type,op,op2;
8165 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8167 /* Pass 1 disassembly */
8169 for(i=0;!done;i++) {
8170 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8171 minimum_free_regs[i]=0;
8172 opcode[i]=op=source[i]>>26;
8175 case 0x00: strcpy(insn[i],"special"); type=NI;
8179 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8180 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8181 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8182 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8183 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8184 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8185 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8186 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8187 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8188 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8189 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8190 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8191 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8192 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8193 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8194 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8195 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8196 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8197 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8198 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8199 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8200 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8201 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8202 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8203 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8204 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8205 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8206 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8207 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8208 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8209 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8210 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8211 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8212 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8213 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8215 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8216 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8217 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8218 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8219 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8220 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8221 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8222 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8223 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8224 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8225 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8226 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8227 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8228 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8229 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8230 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8231 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8235 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8236 op2=(source[i]>>16)&0x1f;
8239 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8240 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8241 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8242 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8243 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8244 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8245 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8246 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8247 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8248 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8249 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8250 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8251 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8252 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8255 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8256 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8257 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8258 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8259 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8260 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8261 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8262 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8263 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8264 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8265 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8266 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8267 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8268 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8269 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8270 op2=(source[i]>>21)&0x1f;
8273 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8274 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8275 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8276 switch(source[i]&0x3f)
8278 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8279 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8280 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8281 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8283 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8285 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8290 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8291 op2=(source[i]>>21)&0x1f;
8294 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8295 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8296 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8297 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8298 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8299 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8300 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8301 switch((source[i]>>16)&0x3)
8303 case 0x00: strcpy(insn[i],"BC1F"); break;
8304 case 0x01: strcpy(insn[i],"BC1T"); break;
8305 case 0x02: strcpy(insn[i],"BC1FL"); break;
8306 case 0x03: strcpy(insn[i],"BC1TL"); break;
8309 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8310 switch(source[i]&0x3f)
8312 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8313 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8314 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8315 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8316 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8317 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8318 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8319 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8320 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8321 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8322 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8323 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8324 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8325 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8326 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8327 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8328 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8329 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8330 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8331 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8332 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8333 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8334 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8335 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8336 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8337 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8338 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8339 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8340 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8341 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8342 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8343 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8344 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8345 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8346 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8349 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8350 switch(source[i]&0x3f)
8352 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8353 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8354 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8355 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8356 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8357 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8358 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8359 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8360 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8361 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8362 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8363 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8364 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8365 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8366 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8367 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8368 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8369 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8370 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8371 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8372 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8373 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8374 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8375 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8376 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8377 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8378 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8379 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8380 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8381 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8382 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8383 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8384 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8385 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8386 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8389 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8390 switch(source[i]&0x3f)
8392 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8393 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8396 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8397 switch(source[i]&0x3f)
8399 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8400 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8406 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8407 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8408 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8409 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8410 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8411 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8412 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8413 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8415 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8416 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8417 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8418 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8419 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8420 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8421 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8423 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8425 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8426 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8427 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8428 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8430 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8431 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8433 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8434 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8435 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8436 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8438 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8439 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8440 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8442 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8443 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8445 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8446 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8447 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8450 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8451 op2=(source[i]>>21)&0x1f;
8453 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8454 if (gte_handlers[source[i]&0x3f]!=NULL) {
8455 if (gte_regnames[source[i]&0x3f]!=NULL)
8456 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8458 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8464 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8465 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8466 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8467 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8470 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8471 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8472 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8474 default: strcpy(insn[i],"???"); type=NI;
8475 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8480 /* Get registers/immediates */
8486 gte_rs[i]=gte_rt[i]=0;
8489 rs1[i]=(source[i]>>21)&0x1f;
8491 rt1[i]=(source[i]>>16)&0x1f;
8493 imm[i]=(short)source[i];
8497 rs1[i]=(source[i]>>21)&0x1f;
8498 rs2[i]=(source[i]>>16)&0x1f;
8501 imm[i]=(short)source[i];
8502 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8505 // LWL/LWR only load part of the register,
8506 // therefore the target register must be treated as a source too
8507 rs1[i]=(source[i]>>21)&0x1f;
8508 rs2[i]=(source[i]>>16)&0x1f;
8509 rt1[i]=(source[i]>>16)&0x1f;
8511 imm[i]=(short)source[i];
8512 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8513 if(op==0x26) dep1[i]=rt1[i]; // LWR
8516 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8517 else rs1[i]=(source[i]>>21)&0x1f;
8519 rt1[i]=(source[i]>>16)&0x1f;
8521 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8522 imm[i]=(unsigned short)source[i];
8524 imm[i]=(short)source[i];
8526 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8527 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8528 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8535 // The JAL instruction writes to r31.
8542 rs1[i]=(source[i]>>21)&0x1f;
8546 // The JALR instruction writes to rd.
8548 rt1[i]=(source[i]>>11)&0x1f;
8553 rs1[i]=(source[i]>>21)&0x1f;
8554 rs2[i]=(source[i]>>16)&0x1f;
8557 if(op&2) { // BGTZ/BLEZ
8565 rs1[i]=(source[i]>>21)&0x1f;
8570 if(op2&0x10) { // BxxAL
8572 // NOTE: If the branch is not taken, r31 is still overwritten
8574 likely[i]=(op2&2)>>1;
8581 likely[i]=((source[i])>>17)&1;
8584 rs1[i]=(source[i]>>21)&0x1f; // source
8585 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8586 rt1[i]=(source[i]>>11)&0x1f; // destination
8588 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8589 us1[i]=rs1[i];us2[i]=rs2[i];
8591 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8592 dep1[i]=rs1[i];dep2[i]=rs2[i];
8594 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8595 dep1[i]=rs1[i];dep2[i]=rs2[i];
8599 rs1[i]=(source[i]>>21)&0x1f; // source
8600 rs2[i]=(source[i]>>16)&0x1f; // divisor
8603 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8604 us1[i]=rs1[i];us2[i]=rs2[i];
8612 if(op2==0x10) rs1[i]=HIREG; // MFHI
8613 if(op2==0x11) rt1[i]=HIREG; // MTHI
8614 if(op2==0x12) rs1[i]=LOREG; // MFLO
8615 if(op2==0x13) rt1[i]=LOREG; // MTLO
8616 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8617 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8621 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8622 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8623 rt1[i]=(source[i]>>11)&0x1f; // destination
8625 // DSLLV/DSRLV/DSRAV are 64-bit
8626 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8629 rs1[i]=(source[i]>>16)&0x1f;
8631 rt1[i]=(source[i]>>11)&0x1f;
8633 imm[i]=(source[i]>>6)&0x1f;
8634 // DSxx32 instructions
8635 if(op2>=0x3c) imm[i]|=0x20;
8636 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8637 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8644 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8645 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8646 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8647 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8654 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8655 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8656 if(op2==5) us1[i]=rs1[i]; // DMTC1
8664 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8665 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8667 int gr=(source[i]>>11)&0x1F;
8670 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8671 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8672 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8673 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8677 rs1[i]=(source[i]>>21)&0x1F;
8681 imm[i]=(short)source[i];
8684 rs1[i]=(source[i]>>21)&0x1F;
8688 imm[i]=(short)source[i];
8689 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8690 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8697 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8698 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8699 gte_rt[i]|=1ll<<63; // every op changes flags
8700 if((source[i]&0x3f)==GTE_MVMVA) {
8701 int v = (source[i] >> 15) & 3;
8702 gte_rs[i]&=~0xe3fll;
8703 if(v==3) gte_rs[i]|=0xe00ll;
8704 else gte_rs[i]|=3ll<<(v*2);
8734 /* Calculate branch target addresses */
8736 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8737 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8738 ba[i]=start+i*4+8; // Ignore never taken branch
8739 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8740 ba[i]=start+i*4+8; // Ignore never taken branch
8741 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8742 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8745 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8747 // branch in delay slot?
8748 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8749 // don't handle first branch and call interpreter if it's hit
8750 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8753 // basic load delay detection
8754 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8755 int t=(ba[i-1]-start)/4;
8756 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8757 // jump target wants DS result - potential load delay effect
8758 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8760 bt[t+1]=1; // expected return from interpreter
8762 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8763 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8764 // v0 overwrite like this is a sign of trouble, bail out
8765 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8771 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8775 i--; // don't compile the DS
8779 /* Is this the end of the block? */
8780 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8781 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8785 if(stop_after_jal) done=1;
8787 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8789 // Don't recompile stuff that's already compiled
8790 if(check_addr(start+i*4+4)) done=1;
8791 // Don't get too close to the limit
8792 if(i>MAXBLOCK/2) done=1;
8794 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8795 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8797 // Does the block continue due to a branch?
8800 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8801 if(ba[j]==start+i*4+4) done=j=0;
8802 if(ba[j]==start+i*4+8) done=j=0;
8805 //assert(i<MAXBLOCK-1);
8806 if(start+i*4==pagelimit-4) done=1;
8807 assert(start+i*4<pagelimit);
8808 if (i==MAXBLOCK-1) done=1;
8809 // Stop if we're compiling junk
8810 if(itype[i]==NI&&opcode[i]==0x11) {
8811 done=stop_after_jal=1;
8812 printf("Disabled speculative precompilation\n");
8816 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8817 if(start+i*4==pagelimit) {
8823 /* Pass 2 - Register dependencies and branch targets */
8825 unneeded_registers(0,slen-1,0);
8827 /* Pass 3 - Register allocation */
8829 struct regstat current; // Current register allocations/status
8832 current.u=unneeded_reg[0];
8833 current.uu=unneeded_reg_upper[0];
8834 clear_all_regs(current.regmap);
8835 alloc_reg(¤t,0,CCREG);
8836 dirty_reg(¤t,CCREG);
8839 current.waswritten=0;
8845 provisional_32bit();
8848 // First instruction is delay slot
8853 unneeded_reg_upper[0]=1;
8854 current.regmap[HOST_BTREG]=BTREG;
8862 for(hr=0;hr<HOST_REGS;hr++)
8864 // Is this really necessary?
8865 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8868 current.waswritten=0;
8872 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8874 if(rs1[i-2]==0||rs2[i-2]==0)
8877 current.is32|=1LL<<rs1[i-2];
8878 int hr=get_reg(current.regmap,rs1[i-2]|64);
8879 if(hr>=0) current.regmap[hr]=-1;
8882 current.is32|=1LL<<rs2[i-2];
8883 int hr=get_reg(current.regmap,rs2[i-2]|64);
8884 if(hr>=0) current.regmap[hr]=-1;
8890 // If something jumps here with 64-bit values
8891 // then promote those registers to 64 bits
8894 uint64_t temp_is32=current.is32;
8897 if(ba[j]==start+i*4)
8898 temp_is32&=branch_regs[j].is32;
8902 if(ba[j]==start+i*4)
8906 if(temp_is32!=current.is32) {
8907 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8908 #ifndef DESTRUCTIVE_WRITEBACK
8911 for(hr=0;hr<HOST_REGS;hr++)
8913 int r=current.regmap[hr];
8916 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8918 //printf("restore %d\n",r);
8922 current.is32=temp_is32;
8929 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8930 regs[i].wasconst=current.isconst;
8931 regs[i].was32=current.is32;
8932 regs[i].wasdirty=current.dirty;
8933 regs[i].loadedconst=0;
8934 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8935 // To change a dirty register from 32 to 64 bits, we must write
8936 // it out during the previous cycle (for branches, 2 cycles)
8937 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8939 uint64_t temp_is32=current.is32;
8942 if(ba[j]==start+i*4+4)
8943 temp_is32&=branch_regs[j].is32;
8947 if(ba[j]==start+i*4+4)
8951 if(temp_is32!=current.is32) {
8952 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8953 for(hr=0;hr<HOST_REGS;hr++)
8955 int r=current.regmap[hr];
8958 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8959 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8961 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8963 //printf("dump %d/r%d\n",hr,r);
8964 current.regmap[hr]=-1;
8965 if(get_reg(current.regmap,r|64)>=0)
8966 current.regmap[get_reg(current.regmap,r|64)]=-1;
8974 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8976 uint64_t temp_is32=current.is32;
8979 if(ba[j]==start+i*4+8)
8980 temp_is32&=branch_regs[j].is32;
8984 if(ba[j]==start+i*4+8)
8988 if(temp_is32!=current.is32) {
8989 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8990 for(hr=0;hr<HOST_REGS;hr++)
8992 int r=current.regmap[hr];
8995 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8996 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8998 //printf("dump %d/r%d\n",hr,r);
8999 current.regmap[hr]=-1;
9000 if(get_reg(current.regmap,r|64)>=0)
9001 current.regmap[get_reg(current.regmap,r|64)]=-1;
9009 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9011 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9012 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9013 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9022 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9023 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9024 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9025 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9026 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9029 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9033 ds=0; // Skip delay slot, already allocated as part of branch
9034 // ...but we need to alloc it in case something jumps here
9036 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9037 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9039 current.u=branch_unneeded_reg[i-1];
9040 current.uu=branch_unneeded_reg_upper[i-1];
9042 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9043 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9044 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9047 struct regstat temp;
9048 memcpy(&temp,¤t,sizeof(current));
9049 temp.wasdirty=temp.dirty;
9050 temp.was32=temp.is32;
9051 // TODO: Take into account unconditional branches, as below
9052 delayslot_alloc(&temp,i);
9053 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9054 regs[i].wasdirty=temp.wasdirty;
9055 regs[i].was32=temp.was32;
9056 regs[i].dirty=temp.dirty;
9057 regs[i].is32=temp.is32;
9061 // Create entry (branch target) regmap
9062 for(hr=0;hr<HOST_REGS;hr++)
9064 int r=temp.regmap[hr];
9066 if(r!=regmap_pre[i][hr]) {
9067 regs[i].regmap_entry[hr]=-1;
9072 if((current.u>>r)&1) {
9073 regs[i].regmap_entry[hr]=-1;
9074 regs[i].regmap[hr]=-1;
9075 //Don't clear regs in the delay slot as the branch might need them
9076 //current.regmap[hr]=-1;
9078 regs[i].regmap_entry[hr]=r;
9081 if((current.uu>>(r&63))&1) {
9082 regs[i].regmap_entry[hr]=-1;
9083 regs[i].regmap[hr]=-1;
9084 //Don't clear regs in the delay slot as the branch might need them
9085 //current.regmap[hr]=-1;
9087 regs[i].regmap_entry[hr]=r;
9091 // First instruction expects CCREG to be allocated
9092 if(i==0&&hr==HOST_CCREG)
9093 regs[i].regmap_entry[hr]=CCREG;
9095 regs[i].regmap_entry[hr]=-1;
9099 else { // Not delay slot
9102 //current.isconst=0; // DEBUG
9103 //current.wasconst=0; // DEBUG
9104 //regs[i].wasconst=0; // DEBUG
9105 clear_const(¤t,rt1[i]);
9106 alloc_cc(¤t,i);
9107 dirty_reg(¤t,CCREG);
9109 alloc_reg(¤t,i,31);
9110 dirty_reg(¤t,31);
9111 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9112 //assert(rt1[i+1]!=rt1[i]);
9114 alloc_reg(¤t,i,PTEMP);
9116 //current.is32|=1LL<<rt1[i];
9119 delayslot_alloc(¤t,i+1);
9120 //current.isconst=0; // DEBUG
9122 //printf("i=%d, isconst=%x\n",i,current.isconst);
9125 //current.isconst=0;
9126 //current.wasconst=0;
9127 //regs[i].wasconst=0;
9128 clear_const(¤t,rs1[i]);
9129 clear_const(¤t,rt1[i]);
9130 alloc_cc(¤t,i);
9131 dirty_reg(¤t,CCREG);
9132 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9133 alloc_reg(¤t,i,rs1[i]);
9135 alloc_reg(¤t,i,rt1[i]);
9136 dirty_reg(¤t,rt1[i]);
9137 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9138 assert(rt1[i+1]!=rt1[i]);
9140 alloc_reg(¤t,i,PTEMP);
9144 if(rs1[i]==31) { // JALR
9145 alloc_reg(¤t,i,RHASH);
9146 #ifndef HOST_IMM_ADDR32
9147 alloc_reg(¤t,i,RHTBL);
9151 delayslot_alloc(¤t,i+1);
9153 // The delay slot overwrites our source register,
9154 // allocate a temporary register to hold the old value.
9158 delayslot_alloc(¤t,i+1);
9160 alloc_reg(¤t,i,RTEMP);
9162 //current.isconst=0; // DEBUG
9167 //current.isconst=0;
9168 //current.wasconst=0;
9169 //regs[i].wasconst=0;
9170 clear_const(¤t,rs1[i]);
9171 clear_const(¤t,rs2[i]);
9172 if((opcode[i]&0x3E)==4) // BEQ/BNE
9174 alloc_cc(¤t,i);
9175 dirty_reg(¤t,CCREG);
9176 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9177 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9178 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9180 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9181 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9183 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9184 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9185 // The delay slot overwrites one of our conditions.
9186 // Allocate the branch condition registers instead.
9190 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9191 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9192 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9194 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9195 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9201 delayslot_alloc(¤t,i+1);
9205 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9207 alloc_cc(¤t,i);
9208 dirty_reg(¤t,CCREG);
9209 alloc_reg(¤t,i,rs1[i]);
9210 if(!(current.is32>>rs1[i]&1))
9212 alloc_reg64(¤t,i,rs1[i]);
9214 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9215 // The delay slot overwrites one of our conditions.
9216 // Allocate the branch condition registers instead.
9220 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9221 if(!((current.is32>>rs1[i])&1))
9223 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9229 delayslot_alloc(¤t,i+1);
9233 // Don't alloc the delay slot yet because we might not execute it
9234 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9239 alloc_cc(¤t,i);
9240 dirty_reg(¤t,CCREG);
9241 alloc_reg(¤t,i,rs1[i]);
9242 alloc_reg(¤t,i,rs2[i]);
9243 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9245 alloc_reg64(¤t,i,rs1[i]);
9246 alloc_reg64(¤t,i,rs2[i]);
9250 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9255 alloc_cc(¤t,i);
9256 dirty_reg(¤t,CCREG);
9257 alloc_reg(¤t,i,rs1[i]);
9258 if(!(current.is32>>rs1[i]&1))
9260 alloc_reg64(¤t,i,rs1[i]);
9264 //current.isconst=0;
9267 //current.isconst=0;
9268 //current.wasconst=0;
9269 //regs[i].wasconst=0;
9270 clear_const(¤t,rs1[i]);
9271 clear_const(¤t,rt1[i]);
9272 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9273 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9275 alloc_cc(¤t,i);
9276 dirty_reg(¤t,CCREG);
9277 alloc_reg(¤t,i,rs1[i]);
9278 if(!(current.is32>>rs1[i]&1))
9280 alloc_reg64(¤t,i,rs1[i]);
9282 if (rt1[i]==31) { // BLTZAL/BGEZAL
9283 alloc_reg(¤t,i,31);
9284 dirty_reg(¤t,31);
9285 //#ifdef REG_PREFETCH
9286 //alloc_reg(¤t,i,PTEMP);
9288 //current.is32|=1LL<<rt1[i];
9290 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9291 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9292 // Allocate the branch condition registers instead.
9296 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9297 if(!((current.is32>>rs1[i])&1))
9299 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9305 delayslot_alloc(¤t,i+1);
9309 // Don't alloc the delay slot yet because we might not execute it
9310 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9315 alloc_cc(¤t,i);
9316 dirty_reg(¤t,CCREG);
9317 alloc_reg(¤t,i,rs1[i]);
9318 if(!(current.is32>>rs1[i]&1))
9320 alloc_reg64(¤t,i,rs1[i]);
9324 //current.isconst=0;
9330 if(likely[i]==0) // BC1F/BC1T
9332 // TODO: Theoretically we can run out of registers here on x86.
9333 // The delay slot can allocate up to six, and we need to check
9334 // CSREG before executing the delay slot. Possibly we can drop
9335 // the cycle count and then reload it after checking that the
9336 // FPU is in a usable state, or don't do out-of-order execution.
9337 alloc_cc(¤t,i);
9338 dirty_reg(¤t,CCREG);
9339 alloc_reg(¤t,i,FSREG);
9340 alloc_reg(¤t,i,CSREG);
9341 if(itype[i+1]==FCOMP) {
9342 // The delay slot overwrites the branch condition.
9343 // Allocate the branch condition registers instead.
9344 alloc_cc(¤t,i);
9345 dirty_reg(¤t,CCREG);
9346 alloc_reg(¤t,i,CSREG);
9347 alloc_reg(¤t,i,FSREG);
9351 delayslot_alloc(¤t,i+1);
9352 alloc_reg(¤t,i+1,CSREG);
9356 // Don't alloc the delay slot yet because we might not execute it
9357 if(likely[i]) // BC1FL/BC1TL
9359 alloc_cc(¤t,i);
9360 dirty_reg(¤t,CCREG);
9361 alloc_reg(¤t,i,CSREG);
9362 alloc_reg(¤t,i,FSREG);
9368 imm16_alloc(¤t,i);
9372 load_alloc(¤t,i);
9376 store_alloc(¤t,i);
9379 alu_alloc(¤t,i);
9382 shift_alloc(¤t,i);
9385 multdiv_alloc(¤t,i);
9388 shiftimm_alloc(¤t,i);
9391 mov_alloc(¤t,i);
9394 cop0_alloc(¤t,i);
9398 cop1_alloc(¤t,i);
9401 c1ls_alloc(¤t,i);
9404 c2ls_alloc(¤t,i);
9407 c2op_alloc(¤t,i);
9410 fconv_alloc(¤t,i);
9413 float_alloc(¤t,i);
9416 fcomp_alloc(¤t,i);
9421 syscall_alloc(¤t,i);
9424 pagespan_alloc(¤t,i);
9428 // Drop the upper half of registers that have become 32-bit
9429 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9430 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9431 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9432 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9435 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9436 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9437 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9438 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9442 // Create entry (branch target) regmap
9443 for(hr=0;hr<HOST_REGS;hr++)
9446 r=current.regmap[hr];
9448 if(r!=regmap_pre[i][hr]) {
9449 // TODO: delay slot (?)
9450 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9451 if(or<0||(r&63)>=TEMPREG){
9452 regs[i].regmap_entry[hr]=-1;
9456 // Just move it to a different register
9457 regs[i].regmap_entry[hr]=r;
9458 // If it was dirty before, it's still dirty
9459 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9466 regs[i].regmap_entry[hr]=0;
9470 if((current.u>>r)&1) {
9471 regs[i].regmap_entry[hr]=-1;
9472 //regs[i].regmap[hr]=-1;
9473 current.regmap[hr]=-1;
9475 regs[i].regmap_entry[hr]=r;
9478 if((current.uu>>(r&63))&1) {
9479 regs[i].regmap_entry[hr]=-1;
9480 //regs[i].regmap[hr]=-1;
9481 current.regmap[hr]=-1;
9483 regs[i].regmap_entry[hr]=r;
9487 // Branches expect CCREG to be allocated at the target
9488 if(regmap_pre[i][hr]==CCREG)
9489 regs[i].regmap_entry[hr]=CCREG;
9491 regs[i].regmap_entry[hr]=-1;
9494 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9497 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9498 current.waswritten|=1<<rs1[i-1];
9499 current.waswritten&=~(1<<rt1[i]);
9500 current.waswritten&=~(1<<rt2[i]);
9501 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9502 current.waswritten&=~(1<<rs1[i]);
9504 /* Branch post-alloc */
9507 current.was32=current.is32;
9508 current.wasdirty=current.dirty;
9509 switch(itype[i-1]) {
9511 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9512 branch_regs[i-1].isconst=0;
9513 branch_regs[i-1].wasconst=0;
9514 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9515 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9516 alloc_cc(&branch_regs[i-1],i-1);
9517 dirty_reg(&branch_regs[i-1],CCREG);
9518 if(rt1[i-1]==31) { // JAL
9519 alloc_reg(&branch_regs[i-1],i-1,31);
9520 dirty_reg(&branch_regs[i-1],31);
9521 branch_regs[i-1].is32|=1LL<<31;
9523 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9524 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9527 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9528 branch_regs[i-1].isconst=0;
9529 branch_regs[i-1].wasconst=0;
9530 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9531 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9532 alloc_cc(&branch_regs[i-1],i-1);
9533 dirty_reg(&branch_regs[i-1],CCREG);
9534 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9535 if(rt1[i-1]!=0) { // JALR
9536 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9537 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9538 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9541 if(rs1[i-1]==31) { // JALR
9542 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9543 #ifndef HOST_IMM_ADDR32
9544 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9548 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9549 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9552 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9554 alloc_cc(¤t,i-1);
9555 dirty_reg(¤t,CCREG);
9556 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9557 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9558 // The delay slot overwrote one of our conditions
9559 // Delay slot goes after the test (in order)
9560 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9561 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9562 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9565 delayslot_alloc(¤t,i);
9570 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9571 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9572 // Alloc the branch condition registers
9573 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9574 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9575 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9577 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9578 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9581 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9582 branch_regs[i-1].isconst=0;
9583 branch_regs[i-1].wasconst=0;
9584 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9585 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9588 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9590 alloc_cc(¤t,i-1);
9591 dirty_reg(¤t,CCREG);
9592 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9593 // The delay slot overwrote the branch condition
9594 // Delay slot goes after the test (in order)
9595 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9596 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9597 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9600 delayslot_alloc(¤t,i);
9605 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9606 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9607 // Alloc the branch condition register
9608 alloc_reg(¤t,i-1,rs1[i-1]);
9609 if(!(current.is32>>rs1[i-1]&1))
9611 alloc_reg64(¤t,i-1,rs1[i-1]);
9614 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9615 branch_regs[i-1].isconst=0;
9616 branch_regs[i-1].wasconst=0;
9617 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9618 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9621 // Alloc the delay slot in case the branch is taken
9622 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9624 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9625 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9626 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9627 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9628 alloc_cc(&branch_regs[i-1],i);
9629 dirty_reg(&branch_regs[i-1],CCREG);
9630 delayslot_alloc(&branch_regs[i-1],i);
9631 branch_regs[i-1].isconst=0;
9632 alloc_reg(¤t,i,CCREG); // Not taken path
9633 dirty_reg(¤t,CCREG);
9634 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9637 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9639 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9640 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9641 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9642 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9643 alloc_cc(&branch_regs[i-1],i);
9644 dirty_reg(&branch_regs[i-1],CCREG);
9645 delayslot_alloc(&branch_regs[i-1],i);
9646 branch_regs[i-1].isconst=0;
9647 alloc_reg(¤t,i,CCREG); // Not taken path
9648 dirty_reg(¤t,CCREG);
9649 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9653 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9654 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9656 alloc_cc(¤t,i-1);
9657 dirty_reg(¤t,CCREG);
9658 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9659 // The delay slot overwrote the branch condition
9660 // Delay slot goes after the test (in order)
9661 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9662 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9663 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9666 delayslot_alloc(¤t,i);
9671 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9672 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9673 // Alloc the branch condition register
9674 alloc_reg(¤t,i-1,rs1[i-1]);
9675 if(!(current.is32>>rs1[i-1]&1))
9677 alloc_reg64(¤t,i-1,rs1[i-1]);
9680 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9681 branch_regs[i-1].isconst=0;
9682 branch_regs[i-1].wasconst=0;
9683 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9684 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9687 // Alloc the delay slot in case the branch is taken
9688 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9690 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9691 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9692 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9693 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9694 alloc_cc(&branch_regs[i-1],i);
9695 dirty_reg(&branch_regs[i-1],CCREG);
9696 delayslot_alloc(&branch_regs[i-1],i);
9697 branch_regs[i-1].isconst=0;
9698 alloc_reg(¤t,i,CCREG); // Not taken path
9699 dirty_reg(¤t,CCREG);
9700 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9702 // FIXME: BLTZAL/BGEZAL
9703 if(opcode2[i-1]&0x10) { // BxxZAL
9704 alloc_reg(&branch_regs[i-1],i-1,31);
9705 dirty_reg(&branch_regs[i-1],31);
9706 branch_regs[i-1].is32|=1LL<<31;
9710 if(likely[i-1]==0) // BC1F/BC1T
9712 alloc_cc(¤t,i-1);
9713 dirty_reg(¤t,CCREG);
9714 if(itype[i]==FCOMP) {
9715 // The delay slot overwrote the branch condition
9716 // Delay slot goes after the test (in order)
9717 delayslot_alloc(¤t,i);
9722 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9723 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9724 // Alloc the branch condition register
9725 alloc_reg(¤t,i-1,FSREG);
9727 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9728 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9732 // Alloc the delay slot in case the branch is taken
9733 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9734 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9735 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9736 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9737 alloc_cc(&branch_regs[i-1],i);
9738 dirty_reg(&branch_regs[i-1],CCREG);
9739 delayslot_alloc(&branch_regs[i-1],i);
9740 branch_regs[i-1].isconst=0;
9741 alloc_reg(¤t,i,CCREG); // Not taken path
9742 dirty_reg(¤t,CCREG);
9743 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9748 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9750 if(rt1[i-1]==31) // JAL/JALR
9752 // Subroutine call will return here, don't alloc any registers
9755 clear_all_regs(current.regmap);
9756 alloc_reg(¤t,i,CCREG);
9757 dirty_reg(¤t,CCREG);
9761 // Internal branch will jump here, match registers to caller
9762 current.is32=0x3FFFFFFFFLL;
9764 clear_all_regs(current.regmap);
9765 alloc_reg(¤t,i,CCREG);
9766 dirty_reg(¤t,CCREG);
9769 if(ba[j]==start+i*4+4) {
9770 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9771 current.is32=branch_regs[j].is32;
9772 current.dirty=branch_regs[j].dirty;
9777 if(ba[j]==start+i*4+4) {
9778 for(hr=0;hr<HOST_REGS;hr++) {
9779 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9780 current.regmap[hr]=-1;
9782 current.is32&=branch_regs[j].is32;
9783 current.dirty&=branch_regs[j].dirty;
9792 // Count cycles in between branches
9794 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9798 #if defined(PCSX) && !defined(DRC_DBG)
9799 else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
9801 // GTE runs in parallel until accessed, divide by 2 for a rough guess
9802 cc+=gte_cycletab[source[i]&0x3f]/2;
9804 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9806 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9808 else if(itype[i]==C2LS)
9818 flush_dirty_uppers(¤t);
9820 regs[i].is32=current.is32;
9821 regs[i].dirty=current.dirty;
9822 regs[i].isconst=current.isconst;
9823 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
9825 for(hr=0;hr<HOST_REGS;hr++) {
9826 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9827 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9828 regs[i].wasconst&=~(1<<hr);
9832 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9833 regs[i].waswritten=current.waswritten;
9836 /* Pass 4 - Cull unused host registers */
9840 for (i=slen-1;i>=0;i--)
9843 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9845 if(ba[i]<start || ba[i]>=(start+slen*4))
9847 // Branch out of this block, don't need anything
9853 // Need whatever matches the target
9855 int t=(ba[i]-start)>>2;
9856 for(hr=0;hr<HOST_REGS;hr++)
9858 if(regs[i].regmap_entry[hr]>=0) {
9859 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9863 // Conditional branch may need registers for following instructions
9864 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9867 nr|=needed_reg[i+2];
9868 for(hr=0;hr<HOST_REGS;hr++)
9870 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9871 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9875 // Don't need stuff which is overwritten
9876 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9877 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9878 // Merge in delay slot
9879 for(hr=0;hr<HOST_REGS;hr++)
9882 // These are overwritten unless the branch is "likely"
9883 // and the delay slot is nullified if not taken
9884 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9885 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9887 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9888 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9889 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9890 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9891 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9892 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9893 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9894 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9895 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9896 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9897 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9899 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9900 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9901 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9903 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9904 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9905 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9909 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9911 // SYSCALL instruction (software interrupt)
9914 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9916 // ERET instruction (return from interrupt)
9922 for(hr=0;hr<HOST_REGS;hr++) {
9923 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9924 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9925 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9926 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9930 for(hr=0;hr<HOST_REGS;hr++)
9932 // Overwritten registers are not needed
9933 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9934 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9935 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9936 // Source registers are needed
9937 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9938 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9939 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9940 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9941 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9942 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9943 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9944 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9945 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9946 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9947 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9949 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9950 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9951 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9953 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9954 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9955 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9957 // Don't store a register immediately after writing it,
9958 // may prevent dual-issue.
9959 // But do so if this is a branch target, otherwise we
9960 // might have to load the register before the branch.
9961 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9962 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9963 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9964 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9965 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9967 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9968 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9969 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9970 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9974 // Cycle count is needed at branches. Assume it is needed at the target too.
9975 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9976 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9977 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9982 // Deallocate unneeded registers
9983 for(hr=0;hr<HOST_REGS;hr++)
9986 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9987 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9988 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9989 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9991 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9994 regs[i].regmap[hr]=-1;
9995 regs[i].isconst&=~(1<<hr);
9997 regmap_pre[i+2][hr]=-1;
9998 regs[i+2].wasconst&=~(1<<hr);
10003 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10005 int d1=0,d2=0,map=0,temp=0;
10006 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10012 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10013 itype[i+1]==STORE || itype[i+1]==STORELR ||
10014 itype[i+1]==C1LS || itype[i+1]==C2LS)
10017 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10018 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10021 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10022 itype[i+1]==C1LS || itype[i+1]==C2LS)
10024 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10025 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10026 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10027 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10028 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10029 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10030 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10031 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10032 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10033 regs[i].regmap[hr]!=map )
10035 regs[i].regmap[hr]=-1;
10036 regs[i].isconst&=~(1<<hr);
10037 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10038 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10039 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10040 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10041 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10042 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10043 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10044 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10045 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10046 branch_regs[i].regmap[hr]!=map)
10048 branch_regs[i].regmap[hr]=-1;
10049 branch_regs[i].regmap_entry[hr]=-1;
10050 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10052 if(!likely[i]&&i<slen-2) {
10053 regmap_pre[i+2][hr]=-1;
10054 regs[i+2].wasconst&=~(1<<hr);
10065 int d1=0,d2=0,map=-1,temp=-1;
10066 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10072 if(itype[i]==LOAD || itype[i]==LOADLR ||
10073 itype[i]==STORE || itype[i]==STORELR ||
10074 itype[i]==C1LS || itype[i]==C2LS)
10076 } else if(itype[i]==STORE || itype[i]==STORELR ||
10077 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10080 if(itype[i]==LOADLR || itype[i]==STORELR ||
10081 itype[i]==C1LS || itype[i]==C2LS)
10083 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10084 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10085 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10086 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10087 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10088 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10090 if(i<slen-1&&!is_ds[i]) {
10091 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10092 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10093 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10095 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10096 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10098 regmap_pre[i+1][hr]=-1;
10099 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10100 regs[i+1].wasconst&=~(1<<hr);
10102 regs[i].regmap[hr]=-1;
10103 regs[i].isconst&=~(1<<hr);
10111 /* Pass 5 - Pre-allocate registers */
10113 // If a register is allocated during a loop, try to allocate it for the
10114 // entire loop, if possible. This avoids loading/storing registers
10115 // inside of the loop.
10117 signed char f_regmap[HOST_REGS];
10118 clear_all_regs(f_regmap);
10119 for(i=0;i<slen-1;i++)
10121 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10123 if(ba[i]>=start && ba[i]<(start+i*4))
10124 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10125 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10126 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10127 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10128 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10129 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10131 int t=(ba[i]-start)>>2;
10132 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10133 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10134 for(hr=0;hr<HOST_REGS;hr++)
10136 if(regs[i].regmap[hr]>64) {
10137 if(!((regs[i].dirty>>hr)&1))
10138 f_regmap[hr]=regs[i].regmap[hr];
10139 else f_regmap[hr]=-1;
10141 else if(regs[i].regmap[hr]>=0) {
10142 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10143 // dealloc old register
10145 for(n=0;n<HOST_REGS;n++)
10147 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10149 // and alloc new one
10150 f_regmap[hr]=regs[i].regmap[hr];
10153 if(branch_regs[i].regmap[hr]>64) {
10154 if(!((branch_regs[i].dirty>>hr)&1))
10155 f_regmap[hr]=branch_regs[i].regmap[hr];
10156 else f_regmap[hr]=-1;
10158 else if(branch_regs[i].regmap[hr]>=0) {
10159 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10160 // dealloc old register
10162 for(n=0;n<HOST_REGS;n++)
10164 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10166 // and alloc new one
10167 f_regmap[hr]=branch_regs[i].regmap[hr];
10171 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10172 f_regmap[hr]=branch_regs[i].regmap[hr];
10174 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10175 f_regmap[hr]=branch_regs[i].regmap[hr];
10177 // Avoid dirty->clean transition
10178 #ifdef DESTRUCTIVE_WRITEBACK
10179 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10181 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10182 // case above, however it's always a good idea. We can't hoist the
10183 // load if the register was already allocated, so there's no point
10184 // wasting time analyzing most of these cases. It only "succeeds"
10185 // when the mapping was different and the load can be replaced with
10186 // a mov, which is of negligible benefit. So such cases are
10188 if(f_regmap[hr]>0) {
10189 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10190 int r=f_regmap[hr];
10193 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10194 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10195 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10197 // NB This can exclude the case where the upper-half
10198 // register is lower numbered than the lower-half
10199 // register. Not sure if it's worth fixing...
10200 if(get_reg(regs[j].regmap,r&63)<0) break;
10201 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10202 if(regs[j].is32&(1LL<<(r&63))) break;
10204 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10205 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10207 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10208 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10210 if(get_reg(regs[i].regmap,r&63)<0) break;
10211 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10214 while(k>1&®s[k-1].regmap[hr]==-1) {
10215 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10216 //printf("no free regs for store %x\n",start+(k-1)*4);
10219 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10220 //printf("no-match due to different register\n");
10223 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10224 //printf("no-match due to branch\n");
10227 // call/ret fast path assumes no registers allocated
10228 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10232 // NB This can exclude the case where the upper-half
10233 // register is lower numbered than the lower-half
10234 // register. Not sure if it's worth fixing...
10235 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10236 if(regs[k-1].is32&(1LL<<(r&63))) break;
10241 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10242 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10243 //printf("bad match after branch\n");
10247 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10248 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10250 regs[k].regmap_entry[hr]=f_regmap[hr];
10251 regs[k].regmap[hr]=f_regmap[hr];
10252 regmap_pre[k+1][hr]=f_regmap[hr];
10253 regs[k].wasdirty&=~(1<<hr);
10254 regs[k].dirty&=~(1<<hr);
10255 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10256 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10257 regs[k].wasconst&=~(1<<hr);
10258 regs[k].isconst&=~(1<<hr);
10263 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10266 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10267 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10268 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10269 regs[i].regmap_entry[hr]=f_regmap[hr];
10270 regs[i].regmap[hr]=f_regmap[hr];
10271 regs[i].wasdirty&=~(1<<hr);
10272 regs[i].dirty&=~(1<<hr);
10273 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10274 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10275 regs[i].wasconst&=~(1<<hr);
10276 regs[i].isconst&=~(1<<hr);
10277 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10278 branch_regs[i].wasdirty&=~(1<<hr);
10279 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10280 branch_regs[i].regmap[hr]=f_regmap[hr];
10281 branch_regs[i].dirty&=~(1<<hr);
10282 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10283 branch_regs[i].wasconst&=~(1<<hr);
10284 branch_regs[i].isconst&=~(1<<hr);
10285 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10286 regmap_pre[i+2][hr]=f_regmap[hr];
10287 regs[i+2].wasdirty&=~(1<<hr);
10288 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10289 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10290 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10295 // Alloc register clean at beginning of loop,
10296 // but may dirty it in pass 6
10297 regs[k].regmap_entry[hr]=f_regmap[hr];
10298 regs[k].regmap[hr]=f_regmap[hr];
10299 regs[k].dirty&=~(1<<hr);
10300 regs[k].wasconst&=~(1<<hr);
10301 regs[k].isconst&=~(1<<hr);
10302 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10303 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10304 branch_regs[k].regmap[hr]=f_regmap[hr];
10305 branch_regs[k].dirty&=~(1<<hr);
10306 branch_regs[k].wasconst&=~(1<<hr);
10307 branch_regs[k].isconst&=~(1<<hr);
10308 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10309 regmap_pre[k+2][hr]=f_regmap[hr];
10310 regs[k+2].wasdirty&=~(1<<hr);
10311 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10312 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10317 regmap_pre[k+1][hr]=f_regmap[hr];
10318 regs[k+1].wasdirty&=~(1<<hr);
10321 if(regs[j].regmap[hr]==f_regmap[hr])
10322 regs[j].regmap_entry[hr]=f_regmap[hr];
10326 if(regs[j].regmap[hr]>=0)
10328 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10329 //printf("no-match due to different register\n");
10332 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10333 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10336 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10338 // Stop on unconditional branch
10341 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10344 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10347 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10350 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10351 //printf("no-match due to different register (branch)\n");
10355 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10356 //printf("No free regs for store %x\n",start+j*4);
10359 if(f_regmap[hr]>=64) {
10360 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10365 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10376 // Non branch or undetermined branch target
10377 for(hr=0;hr<HOST_REGS;hr++)
10379 if(hr!=EXCLUDE_REG) {
10380 if(regs[i].regmap[hr]>64) {
10381 if(!((regs[i].dirty>>hr)&1))
10382 f_regmap[hr]=regs[i].regmap[hr];
10384 else if(regs[i].regmap[hr]>=0) {
10385 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10386 // dealloc old register
10388 for(n=0;n<HOST_REGS;n++)
10390 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10392 // and alloc new one
10393 f_regmap[hr]=regs[i].regmap[hr];
10398 // Try to restore cycle count at branch targets
10400 for(j=i;j<slen-1;j++) {
10401 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10402 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10403 //printf("no free regs for store %x\n",start+j*4);
10407 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10409 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10411 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10412 regs[k].regmap[HOST_CCREG]=CCREG;
10413 regmap_pre[k+1][HOST_CCREG]=CCREG;
10414 regs[k+1].wasdirty|=1<<HOST_CCREG;
10415 regs[k].dirty|=1<<HOST_CCREG;
10416 regs[k].wasconst&=~(1<<HOST_CCREG);
10417 regs[k].isconst&=~(1<<HOST_CCREG);
10420 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10422 // Work backwards from the branch target
10423 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10425 //printf("Extend backwards\n");
10428 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10429 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10430 //printf("no free regs for store %x\n",start+(k-1)*4);
10435 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10436 //printf("Extend CC, %x ->\n",start+k*4);
10438 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10439 regs[k].regmap[HOST_CCREG]=CCREG;
10440 regmap_pre[k+1][HOST_CCREG]=CCREG;
10441 regs[k+1].wasdirty|=1<<HOST_CCREG;
10442 regs[k].dirty|=1<<HOST_CCREG;
10443 regs[k].wasconst&=~(1<<HOST_CCREG);
10444 regs[k].isconst&=~(1<<HOST_CCREG);
10449 //printf("Fail Extend CC, %x ->\n",start+k*4);
10453 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10454 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10455 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10456 itype[i]!=FCONV&&itype[i]!=FCOMP)
10458 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10463 // Cache memory offset or tlb map pointer if a register is available
10464 #ifndef HOST_IMM_ADDR32
10469 int earliest_available[HOST_REGS];
10470 int loop_start[HOST_REGS];
10471 int score[HOST_REGS];
10472 int end[HOST_REGS];
10473 int reg=using_tlb?MMREG:ROREG;
10476 for(hr=0;hr<HOST_REGS;hr++) {
10477 score[hr]=0;earliest_available[hr]=0;
10478 loop_start[hr]=MAXBLOCK;
10480 for(i=0;i<slen-1;i++)
10482 // Can't do anything if no registers are available
10483 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10484 for(hr=0;hr<HOST_REGS;hr++) {
10485 score[hr]=0;earliest_available[hr]=i+1;
10486 loop_start[hr]=MAXBLOCK;
10489 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10491 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10492 for(hr=0;hr<HOST_REGS;hr++) {
10493 score[hr]=0;earliest_available[hr]=i+1;
10494 loop_start[hr]=MAXBLOCK;
10498 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10499 for(hr=0;hr<HOST_REGS;hr++) {
10500 score[hr]=0;earliest_available[hr]=i+1;
10501 loop_start[hr]=MAXBLOCK;
10506 // Mark unavailable registers
10507 for(hr=0;hr<HOST_REGS;hr++) {
10508 if(regs[i].regmap[hr]>=0) {
10509 score[hr]=0;earliest_available[hr]=i+1;
10510 loop_start[hr]=MAXBLOCK;
10512 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10513 if(branch_regs[i].regmap[hr]>=0) {
10514 score[hr]=0;earliest_available[hr]=i+2;
10515 loop_start[hr]=MAXBLOCK;
10519 // No register allocations after unconditional jumps
10520 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10522 for(hr=0;hr<HOST_REGS;hr++) {
10523 score[hr]=0;earliest_available[hr]=i+2;
10524 loop_start[hr]=MAXBLOCK;
10526 i++; // Skip delay slot too
10527 //printf("skip delay slot: %x\n",start+i*4);
10531 if(itype[i]==LOAD||itype[i]==LOADLR||
10532 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10533 for(hr=0;hr<HOST_REGS;hr++) {
10534 if(hr!=EXCLUDE_REG) {
10536 for(j=i;j<slen-1;j++) {
10537 if(regs[j].regmap[hr]>=0) break;
10538 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10539 if(branch_regs[j].regmap[hr]>=0) break;
10541 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10543 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10546 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10547 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10548 int t=(ba[j]-start)>>2;
10549 if(t<j&&t>=earliest_available[hr]) {
10550 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10551 // Score a point for hoisting loop invariant
10552 if(t<loop_start[hr]) loop_start[hr]=t;
10553 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10559 if(regs[t].regmap[hr]==reg) {
10560 // Score a point if the branch target matches this register
10565 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10566 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10571 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10573 // Stop on unconditional branch
10577 if(itype[j]==LOAD||itype[j]==LOADLR||
10578 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10585 // Find highest score and allocate that register
10587 for(hr=0;hr<HOST_REGS;hr++) {
10588 if(hr!=EXCLUDE_REG) {
10589 if(score[hr]>score[maxscore]) {
10591 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10595 if(score[maxscore]>1)
10597 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10598 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10599 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10600 assert(regs[j].regmap[maxscore]<0);
10601 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10602 regs[j].regmap[maxscore]=reg;
10603 regs[j].dirty&=~(1<<maxscore);
10604 regs[j].wasconst&=~(1<<maxscore);
10605 regs[j].isconst&=~(1<<maxscore);
10606 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10607 branch_regs[j].regmap[maxscore]=reg;
10608 branch_regs[j].wasdirty&=~(1<<maxscore);
10609 branch_regs[j].dirty&=~(1<<maxscore);
10610 branch_regs[j].wasconst&=~(1<<maxscore);
10611 branch_regs[j].isconst&=~(1<<maxscore);
10612 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10613 regmap_pre[j+2][maxscore]=reg;
10614 regs[j+2].wasdirty&=~(1<<maxscore);
10616 // loop optimization (loop_preload)
10617 int t=(ba[j]-start)>>2;
10618 if(t==loop_start[maxscore]) {
10619 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10620 regs[t].regmap_entry[maxscore]=reg;
10625 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10626 regmap_pre[j+1][maxscore]=reg;
10627 regs[j+1].wasdirty&=~(1<<maxscore);
10632 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10633 for(hr=0;hr<HOST_REGS;hr++) {
10634 score[hr]=0;earliest_available[hr]=i+i;
10635 loop_start[hr]=MAXBLOCK;
10643 // This allocates registers (if possible) one instruction prior
10644 // to use, which can avoid a load-use penalty on certain CPUs.
10645 for(i=0;i<slen-1;i++)
10647 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10651 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10652 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10655 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10657 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10659 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10660 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10661 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10662 regs[i].isconst&=~(1<<hr);
10663 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10664 constmap[i][hr]=constmap[i+1][hr];
10665 regs[i+1].wasdirty&=~(1<<hr);
10666 regs[i].dirty&=~(1<<hr);
10671 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10673 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10675 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10676 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10677 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10678 regs[i].isconst&=~(1<<hr);
10679 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10680 constmap[i][hr]=constmap[i+1][hr];
10681 regs[i+1].wasdirty&=~(1<<hr);
10682 regs[i].dirty&=~(1<<hr);
10686 // Preload target address for load instruction (non-constant)
10687 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10688 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10690 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10692 regs[i].regmap[hr]=rs1[i+1];
10693 regmap_pre[i+1][hr]=rs1[i+1];
10694 regs[i+1].regmap_entry[hr]=rs1[i+1];
10695 regs[i].isconst&=~(1<<hr);
10696 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10697 constmap[i][hr]=constmap[i+1][hr];
10698 regs[i+1].wasdirty&=~(1<<hr);
10699 regs[i].dirty&=~(1<<hr);
10703 // Load source into target register
10704 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10705 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10707 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10709 regs[i].regmap[hr]=rs1[i+1];
10710 regmap_pre[i+1][hr]=rs1[i+1];
10711 regs[i+1].regmap_entry[hr]=rs1[i+1];
10712 regs[i].isconst&=~(1<<hr);
10713 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10714 constmap[i][hr]=constmap[i+1][hr];
10715 regs[i+1].wasdirty&=~(1<<hr);
10716 regs[i].dirty&=~(1<<hr);
10720 // Preload map address
10721 #ifndef HOST_IMM_ADDR32
10722 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10723 hr=get_reg(regs[i+1].regmap,TLREG);
10725 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10726 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10728 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10730 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10731 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10732 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10733 regs[i].isconst&=~(1<<hr);
10734 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10735 constmap[i][hr]=constmap[i+1][hr];
10736 regs[i+1].wasdirty&=~(1<<hr);
10737 regs[i].dirty&=~(1<<hr);
10739 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10741 // move it to another register
10742 regs[i+1].regmap[hr]=-1;
10743 regmap_pre[i+2][hr]=-1;
10744 regs[i+1].regmap[nr]=TLREG;
10745 regmap_pre[i+2][nr]=TLREG;
10746 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10747 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10748 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10749 regs[i].isconst&=~(1<<nr);
10750 regs[i+1].isconst&=~(1<<nr);
10751 regs[i].dirty&=~(1<<nr);
10752 regs[i+1].wasdirty&=~(1<<nr);
10753 regs[i+1].dirty&=~(1<<nr);
10754 regs[i+2].wasdirty&=~(1<<nr);
10760 // Address for store instruction (non-constant)
10761 if(itype[i+1]==STORE||itype[i+1]==STORELR
10762 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10763 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10764 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10765 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10766 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10768 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10770 regs[i].regmap[hr]=rs1[i+1];
10771 regmap_pre[i+1][hr]=rs1[i+1];
10772 regs[i+1].regmap_entry[hr]=rs1[i+1];
10773 regs[i].isconst&=~(1<<hr);
10774 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10775 constmap[i][hr]=constmap[i+1][hr];
10776 regs[i+1].wasdirty&=~(1<<hr);
10777 regs[i].dirty&=~(1<<hr);
10781 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10782 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10784 hr=get_reg(regs[i+1].regmap,FTEMP);
10786 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10788 regs[i].regmap[hr]=rs1[i+1];
10789 regmap_pre[i+1][hr]=rs1[i+1];
10790 regs[i+1].regmap_entry[hr]=rs1[i+1];
10791 regs[i].isconst&=~(1<<hr);
10792 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10793 constmap[i][hr]=constmap[i+1][hr];
10794 regs[i+1].wasdirty&=~(1<<hr);
10795 regs[i].dirty&=~(1<<hr);
10797 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10799 // move it to another register
10800 regs[i+1].regmap[hr]=-1;
10801 regmap_pre[i+2][hr]=-1;
10802 regs[i+1].regmap[nr]=FTEMP;
10803 regmap_pre[i+2][nr]=FTEMP;
10804 regs[i].regmap[nr]=rs1[i+1];
10805 regmap_pre[i+1][nr]=rs1[i+1];
10806 regs[i+1].regmap_entry[nr]=rs1[i+1];
10807 regs[i].isconst&=~(1<<nr);
10808 regs[i+1].isconst&=~(1<<nr);
10809 regs[i].dirty&=~(1<<nr);
10810 regs[i+1].wasdirty&=~(1<<nr);
10811 regs[i+1].dirty&=~(1<<nr);
10812 regs[i+2].wasdirty&=~(1<<nr);
10816 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10817 if(itype[i+1]==LOAD)
10818 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10819 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10820 hr=get_reg(regs[i+1].regmap,FTEMP);
10821 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10822 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10823 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10825 if(hr>=0&®s[i].regmap[hr]<0) {
10826 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10827 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10828 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10829 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10830 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10831 regs[i].isconst&=~(1<<hr);
10832 regs[i+1].wasdirty&=~(1<<hr);
10833 regs[i].dirty&=~(1<<hr);
10842 /* Pass 6 - Optimize clean/dirty state */
10843 clean_registers(0,slen-1,1);
10845 /* Pass 7 - Identify 32-bit registers */
10851 for (i=slen-1;i>=0;i--)
10854 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10856 if(ba[i]<start || ba[i]>=(start+slen*4))
10858 // Branch out of this block, don't need anything
10864 // Need whatever matches the target
10865 // (and doesn't get overwritten by the delay slot instruction)
10867 int t=(ba[i]-start)>>2;
10868 if(ba[i]>start+i*4) {
10870 if(!(requires_32bit[t]&~regs[i].was32))
10871 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10874 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10875 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10876 if(!(pr32[t]&~regs[i].was32))
10877 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10880 // Conditional branch may need registers for following instructions
10881 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10884 r32|=requires_32bit[i+2];
10885 r32&=regs[i].was32;
10886 // Mark this address as a branch target since it may be called
10887 // upon return from interrupt
10891 // Merge in delay slot
10893 // These are overwritten unless the branch is "likely"
10894 // and the delay slot is nullified if not taken
10895 r32&=~(1LL<<rt1[i+1]);
10896 r32&=~(1LL<<rt2[i+1]);
10898 // Assume these are needed (delay slot)
10901 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10905 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10907 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10909 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10911 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10913 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10916 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10918 // SYSCALL instruction (software interrupt)
10921 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10923 // ERET instruction (return from interrupt)
10927 r32&=~(1LL<<rt1[i]);
10928 r32&=~(1LL<<rt2[i]);
10931 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10935 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10937 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10939 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10941 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10943 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10945 requires_32bit[i]=r32;
10947 // Dirty registers which are 32-bit, require 32-bit input
10948 // as they will be written as 32-bit values
10949 for(hr=0;hr<HOST_REGS;hr++)
10951 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10952 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10953 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10954 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10958 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10961 for (i=slen-1;i>=0;i--)
10963 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10965 // Conditional branch
10966 if((source[i]>>16)!=0x1000&&i<slen-2) {
10967 // Mark this address as a branch target since it may be called
10968 // upon return from interrupt
10975 if(itype[slen-1]==SPAN) {
10976 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10980 /* Debug/disassembly */
10981 for(i=0;i<slen;i++)
10985 for(r=1;r<=CCREG;r++) {
10986 if((unneeded_reg[i]>>r)&1) {
10987 if(r==HIREG) printf(" HI");
10988 else if(r==LOREG) printf(" LO");
10989 else printf(" r%d",r);
10994 for(r=1;r<=CCREG;r++) {
10995 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10996 if(r==HIREG) printf(" HI");
10997 else if(r==LOREG) printf(" LO");
10998 else printf(" r%d",r);
11002 for(r=0;r<=CCREG;r++) {
11003 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11004 if((regs[i].was32>>r)&1) {
11005 if(r==CCREG) printf(" CC");
11006 else if(r==HIREG) printf(" HI");
11007 else if(r==LOREG) printf(" LO");
11008 else printf(" r%d",r);
11013 #if defined(__i386__) || defined(__x86_64__)
11014 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11017 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11020 if(needed_reg[i]&1) printf("eax ");
11021 if((needed_reg[i]>>1)&1) printf("ecx ");
11022 if((needed_reg[i]>>2)&1) printf("edx ");
11023 if((needed_reg[i]>>3)&1) printf("ebx ");
11024 if((needed_reg[i]>>5)&1) printf("ebp ");
11025 if((needed_reg[i]>>6)&1) printf("esi ");
11026 if((needed_reg[i]>>7)&1) printf("edi ");
11028 for(r=0;r<=CCREG;r++) {
11029 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11030 if((requires_32bit[i]>>r)&1) {
11031 if(r==CCREG) printf(" CC");
11032 else if(r==HIREG) printf(" HI");
11033 else if(r==LOREG) printf(" LO");
11034 else printf(" r%d",r);
11039 for(r=0;r<=CCREG;r++) {
11040 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11041 if((pr32[i]>>r)&1) {
11042 if(r==CCREG) printf(" CC");
11043 else if(r==HIREG) printf(" HI");
11044 else if(r==LOREG) printf(" LO");
11045 else printf(" r%d",r);
11048 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11050 #if defined(__i386__) || defined(__x86_64__)
11051 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11053 if(regs[i].wasdirty&1) printf("eax ");
11054 if((regs[i].wasdirty>>1)&1) printf("ecx ");
11055 if((regs[i].wasdirty>>2)&1) printf("edx ");
11056 if((regs[i].wasdirty>>3)&1) printf("ebx ");
11057 if((regs[i].wasdirty>>5)&1) printf("ebp ");
11058 if((regs[i].wasdirty>>6)&1) printf("esi ");
11059 if((regs[i].wasdirty>>7)&1) printf("edi ");
11062 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11064 if(regs[i].wasdirty&1) printf("r0 ");
11065 if((regs[i].wasdirty>>1)&1) printf("r1 ");
11066 if((regs[i].wasdirty>>2)&1) printf("r2 ");
11067 if((regs[i].wasdirty>>3)&1) printf("r3 ");
11068 if((regs[i].wasdirty>>4)&1) printf("r4 ");
11069 if((regs[i].wasdirty>>5)&1) printf("r5 ");
11070 if((regs[i].wasdirty>>6)&1) printf("r6 ");
11071 if((regs[i].wasdirty>>7)&1) printf("r7 ");
11072 if((regs[i].wasdirty>>8)&1) printf("r8 ");
11073 if((regs[i].wasdirty>>9)&1) printf("r9 ");
11074 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11075 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11078 disassemble_inst(i);
11079 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11080 #if defined(__i386__) || defined(__x86_64__)
11081 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11082 if(regs[i].dirty&1) printf("eax ");
11083 if((regs[i].dirty>>1)&1) printf("ecx ");
11084 if((regs[i].dirty>>2)&1) printf("edx ");
11085 if((regs[i].dirty>>3)&1) printf("ebx ");
11086 if((regs[i].dirty>>5)&1) printf("ebp ");
11087 if((regs[i].dirty>>6)&1) printf("esi ");
11088 if((regs[i].dirty>>7)&1) printf("edi ");
11091 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11092 if(regs[i].dirty&1) printf("r0 ");
11093 if((regs[i].dirty>>1)&1) printf("r1 ");
11094 if((regs[i].dirty>>2)&1) printf("r2 ");
11095 if((regs[i].dirty>>3)&1) printf("r3 ");
11096 if((regs[i].dirty>>4)&1) printf("r4 ");
11097 if((regs[i].dirty>>5)&1) printf("r5 ");
11098 if((regs[i].dirty>>6)&1) printf("r6 ");
11099 if((regs[i].dirty>>7)&1) printf("r7 ");
11100 if((regs[i].dirty>>8)&1) printf("r8 ");
11101 if((regs[i].dirty>>9)&1) printf("r9 ");
11102 if((regs[i].dirty>>10)&1) printf("r10 ");
11103 if((regs[i].dirty>>12)&1) printf("r12 ");
11106 if(regs[i].isconst) {
11107 printf("constants: ");
11108 #if defined(__i386__) || defined(__x86_64__)
11109 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11110 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11111 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11112 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11113 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11114 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11115 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11118 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11119 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11120 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11121 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11122 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11123 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11124 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11125 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11126 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11127 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11128 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11129 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11135 for(r=0;r<=CCREG;r++) {
11136 if((regs[i].is32>>r)&1) {
11137 if(r==CCREG) printf(" CC");
11138 else if(r==HIREG) printf(" HI");
11139 else if(r==LOREG) printf(" LO");
11140 else printf(" r%d",r);
11146 for(r=0;r<=CCREG;r++) {
11147 if((p32[i]>>r)&1) {
11148 if(r==CCREG) printf(" CC");
11149 else if(r==HIREG) printf(" HI");
11150 else if(r==LOREG) printf(" LO");
11151 else printf(" r%d",r);
11154 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11155 else printf("\n");*/
11156 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11157 #if defined(__i386__) || defined(__x86_64__)
11158 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11159 if(branch_regs[i].dirty&1) printf("eax ");
11160 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11161 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11162 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11163 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11164 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11165 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11168 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11169 if(branch_regs[i].dirty&1) printf("r0 ");
11170 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11171 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11172 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11173 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11174 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11175 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11176 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11177 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11178 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11179 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11180 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11184 for(r=0;r<=CCREG;r++) {
11185 if((branch_regs[i].is32>>r)&1) {
11186 if(r==CCREG) printf(" CC");
11187 else if(r==HIREG) printf(" HI");
11188 else if(r==LOREG) printf(" LO");
11189 else printf(" r%d",r);
11198 /* Pass 8 - Assembly */
11199 linkcount=0;stubcount=0;
11200 ds=0;is_delayslot=0;
11202 uint64_t is32_pre=0;
11204 u_int beginning=(u_int)out;
11205 if((u_int)addr&1) {
11209 u_int instr_addr0_override=0;
11212 if (start == 0x80030000) {
11213 // nasty hack for fastbios thing
11214 // override block entry to this code
11215 instr_addr0_override=(u_int)out;
11216 emit_movimm(start,0);
11217 // abuse io address var as a flag that we
11218 // have already returned here once
11219 emit_readword((int)&address,1);
11220 emit_writeword(0,(int)&pcaddr);
11221 emit_writeword(0,(int)&address);
11223 emit_jne((int)new_dyna_leave);
11226 for(i=0;i<slen;i++)
11228 //if(ds) printf("ds: ");
11229 disassemble_inst(i);
11231 ds=0; // Skip delay slot
11232 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11235 speculate_register_values(i);
11236 #ifndef DESTRUCTIVE_WRITEBACK
11237 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11239 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11240 unneeded_reg[i],unneeded_reg_upper[i]);
11241 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11242 unneeded_reg[i],unneeded_reg_upper[i]);
11244 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11245 is32_pre=branch_regs[i].is32;
11246 dirty_pre=branch_regs[i].dirty;
11248 is32_pre=regs[i].is32;
11249 dirty_pre=regs[i].dirty;
11253 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11255 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11256 unneeded_reg[i],unneeded_reg_upper[i]);
11257 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11259 // branch target entry point
11260 instr_addr[i]=(u_int)out;
11261 assem_debug("<->\n");
11263 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11264 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11265 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11266 address_generation(i,®s[i],regs[i].regmap_entry);
11267 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11268 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11270 // Load the delay slot registers if necessary
11271 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11272 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11273 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11274 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11275 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11276 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11280 // Preload registers for following instruction
11281 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11282 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11283 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11284 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11285 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11286 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11288 // TODO: if(is_ooo(i)) address_generation(i+1);
11289 if(itype[i]==CJUMP||itype[i]==FJUMP)
11290 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11291 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11292 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11293 if(bt[i]) cop1_usable=0;
11297 alu_assemble(i,®s[i]);break;
11299 imm16_assemble(i,®s[i]);break;
11301 shift_assemble(i,®s[i]);break;
11303 shiftimm_assemble(i,®s[i]);break;
11305 load_assemble(i,®s[i]);break;
11307 loadlr_assemble(i,®s[i]);break;
11309 store_assemble(i,®s[i]);break;
11311 storelr_assemble(i,®s[i]);break;
11313 cop0_assemble(i,®s[i]);break;
11315 cop1_assemble(i,®s[i]);break;
11317 c1ls_assemble(i,®s[i]);break;
11319 cop2_assemble(i,®s[i]);break;
11321 c2ls_assemble(i,®s[i]);break;
11323 c2op_assemble(i,®s[i]);break;
11325 fconv_assemble(i,®s[i]);break;
11327 float_assemble(i,®s[i]);break;
11329 fcomp_assemble(i,®s[i]);break;
11331 multdiv_assemble(i,®s[i]);break;
11333 mov_assemble(i,®s[i]);break;
11335 syscall_assemble(i,®s[i]);break;
11337 hlecall_assemble(i,®s[i]);break;
11339 intcall_assemble(i,®s[i]);break;
11341 ujump_assemble(i,®s[i]);ds=1;break;
11343 rjump_assemble(i,®s[i]);ds=1;break;
11345 cjump_assemble(i,®s[i]);ds=1;break;
11347 sjump_assemble(i,®s[i]);ds=1;break;
11349 fjump_assemble(i,®s[i]);ds=1;break;
11351 pagespan_assemble(i,®s[i]);break;
11353 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11354 literal_pool(1024);
11356 literal_pool_jumpover(256);
11359 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11360 // If the block did not end with an unconditional branch,
11361 // add a jump to the next instruction.
11363 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11364 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11366 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11367 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11368 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11369 emit_loadreg(CCREG,HOST_CCREG);
11370 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11372 else if(!likely[i-2])
11374 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11375 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11379 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11380 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11382 add_to_linker((int)out,start+i*4,0);
11389 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11390 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11391 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11392 emit_loadreg(CCREG,HOST_CCREG);
11393 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11394 add_to_linker((int)out,start+i*4,0);
11398 // TODO: delay slot stubs?
11400 for(i=0;i<stubcount;i++)
11402 switch(stubs[i][0])
11410 do_readstub(i);break;
11415 do_writestub(i);break;
11417 do_ccstub(i);break;
11419 do_invstub(i);break;
11421 do_cop1stub(i);break;
11423 do_unalignedwritestub(i);break;
11427 if (instr_addr0_override)
11428 instr_addr[0] = instr_addr0_override;
11430 /* Pass 9 - Linker */
11431 for(i=0;i<linkcount;i++)
11433 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11435 if(!link_addr[i][2])
11438 void *addr=check_addr(link_addr[i][1]);
11439 emit_extjump(link_addr[i][0],link_addr[i][1]);
11441 set_jump_target(link_addr[i][0],(int)addr);
11442 add_link(link_addr[i][1],stub);
11444 else set_jump_target(link_addr[i][0],(int)stub);
11449 int target=(link_addr[i][1]-start)>>2;
11450 assert(target>=0&&target<slen);
11451 assert(instr_addr[target]);
11452 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11453 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11455 set_jump_target(link_addr[i][0],instr_addr[target]);
11459 // External Branch Targets (jump_in)
11460 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11461 for(i=0;i<slen;i++)
11465 if(instr_addr[i]) // TODO - delay slots (=null)
11467 u_int vaddr=start+i*4;
11468 u_int page=get_page(vaddr);
11469 u_int vpage=get_vpage(vaddr);
11471 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11473 if(!requires_32bit[i])
11478 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11479 assem_debug("jump_in: %x\n",start+i*4);
11480 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11481 int entry_point=do_dirty_stub(i);
11482 ll_add(jump_in+page,vaddr,(void *)entry_point);
11483 // If there was an existing entry in the hash table,
11484 // replace it with the new address.
11485 // Don't add new entries. We'll insert the
11486 // ones that actually get used in check_addr().
11487 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11488 if(ht_bin[0]==vaddr) {
11489 ht_bin[1]=entry_point;
11491 if(ht_bin[2]==vaddr) {
11492 ht_bin[3]=entry_point;
11497 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11498 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11499 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11500 //int entry_point=(int)out;
11501 ////assem_debug("entry_point: %x\n",entry_point);
11502 //load_regs_entry(i);
11503 //if(entry_point==(int)out)
11504 // entry_point=instr_addr[i];
11506 // emit_jmp(instr_addr[i]);
11507 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11508 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11509 int entry_point=do_dirty_stub(i);
11510 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11515 // Write out the literal pool if necessary
11517 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11519 if(((u_int)out)&7) emit_addnop(13);
11521 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11522 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11523 memcpy(copy,source,slen*4);
11527 __clear_cache((void *)beginning,out);
11530 // If we're within 256K of the end of the buffer,
11531 // start over from the beginning. (Is 256K enough?)
11532 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11534 // Trap writes to any of the pages we compiled
11535 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11537 #ifndef DISABLE_TLB
11538 memory_map[i]|=0x40000000;
11539 if((signed int)start>=(signed int)0xC0000000) {
11541 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11543 memory_map[j]|=0x40000000;
11544 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11548 inv_code_start=inv_code_end=~0;
11550 // for PCSX we need to mark all mirrors too
11551 if(get_page(start)<(RAM_SIZE>>12))
11552 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11553 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11554 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11555 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11558 /* Pass 10 - Free memory by expiring oldest blocks */
11560 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11561 while(expirep!=end)
11563 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11564 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11565 inv_debug("EXP: Phase %d\n",expirep);
11566 switch((expirep>>11)&3)
11569 // Clear jump_in and jump_dirty
11570 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11571 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11572 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11573 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11577 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11578 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11581 // Clear hash table
11582 for(i=0;i<32;i++) {
11583 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11584 if((ht_bin[3]>>shift)==(base>>shift) ||
11585 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11586 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11587 ht_bin[2]=ht_bin[3]=-1;
11589 if((ht_bin[1]>>shift)==(base>>shift) ||
11590 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11591 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11592 ht_bin[0]=ht_bin[2];
11593 ht_bin[1]=ht_bin[3];
11594 ht_bin[2]=ht_bin[3]=-1;
11601 if((expirep&2047)==0)
11604 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11605 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11608 expirep=(expirep+1)&65535;
11613 // vim:shiftwidth=2:expandtab