1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
49 signed char regmap_entry[HOST_REGS];
50 signed char regmap[HOST_REGS];
59 u_int loadedconst; // host regs that have constants loaded
60 u_int waswritten; // MIPS regs that were used as store base before
68 struct ll_entry *next;
74 char insn[MAXBLOCK][10];
75 u_char itype[MAXBLOCK];
76 u_char opcode[MAXBLOCK];
77 u_char opcode2[MAXBLOCK];
85 u_char dep1[MAXBLOCK];
86 u_char dep2[MAXBLOCK];
88 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
89 static uint64_t gte_rt[MAXBLOCK];
90 static uint64_t gte_unneeded[MAXBLOCK];
91 static u_int smrv[32]; // speculated MIPS register values
92 static u_int smrv_strong; // mask or regs that are likely to have correct values
93 static u_int smrv_weak; // same, but somewhat less likely
94 static u_int smrv_strong_next; // same, but after current insn executes
95 static u_int smrv_weak_next;
98 char likely[MAXBLOCK];
101 uint64_t unneeded_reg[MAXBLOCK];
102 uint64_t unneeded_reg_upper[MAXBLOCK];
103 uint64_t branch_unneeded_reg[MAXBLOCK];
104 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
105 uint64_t p32[MAXBLOCK];
106 uint64_t pr32[MAXBLOCK];
107 signed char regmap_pre[MAXBLOCK][HOST_REGS];
108 static uint64_t current_constmap[HOST_REGS];
109 static uint64_t constmap[MAXBLOCK][HOST_REGS];
110 static struct regstat regs[MAXBLOCK];
111 static struct regstat branch_regs[MAXBLOCK];
112 signed char minimum_free_regs[MAXBLOCK];
113 u_int needed_reg[MAXBLOCK];
114 uint64_t requires_32bit[MAXBLOCK];
115 u_int wont_dirty[MAXBLOCK];
116 u_int will_dirty[MAXBLOCK];
119 u_int instr_addr[MAXBLOCK];
120 u_int link_addr[MAXBLOCK][3];
122 u_int stubs[MAXBLOCK*3][8];
124 u_int literals[1024][2];
129 struct ll_entry *jump_in[4096];
130 struct ll_entry *jump_out[4096];
131 struct ll_entry *jump_dirty[4096];
132 u_int hash_table[65536][4] __attribute__((aligned(16)));
133 char shadow[1048576] __attribute__((aligned(16)));
139 static const u_int using_tlb=0;
141 int new_dynarec_did_compile;
142 int new_dynarec_hacks;
143 u_int stop_after_jal;
144 extern u_char restore_candidate[512];
145 extern int cycle_count;
147 /* registers that may be allocated */
149 #define HIREG 32 // hi
150 #define LOREG 33 // lo
151 #define FSREG 34 // FPU status (FCSR)
152 #define CSREG 35 // Coprocessor status
153 #define CCREG 36 // Cycle count
154 #define INVCP 37 // Pointer to invalid_code
155 #define MMREG 38 // Pointer to memory_map
156 #define ROREG 39 // ram offset (if rdram!=0x80000000)
158 #define FTEMP 40 // FPU temporary register
159 #define PTEMP 41 // Prefetch temporary register
160 #define TLREG 42 // TLB mapping offset
161 #define RHASH 43 // Return address hash
162 #define RHTBL 44 // Return address hash table address
163 #define RTEMP 45 // JR/JALR address register
165 #define AGEN1 46 // Address generation temporary register
166 #define AGEN2 47 // Address generation temporary register
167 #define MGEN1 48 // Maptable address generation temporary register
168 #define MGEN2 49 // Maptable address generation temporary register
169 #define BTREG 50 // Branch target temporary register
171 /* instruction types */
172 #define NOP 0 // No operation
173 #define LOAD 1 // Load
174 #define STORE 2 // Store
175 #define LOADLR 3 // Unaligned load
176 #define STORELR 4 // Unaligned store
177 #define MOV 5 // Move
178 #define ALU 6 // Arithmetic/logic
179 #define MULTDIV 7 // Multiply/divide
180 #define SHIFT 8 // Shift by register
181 #define SHIFTIMM 9// Shift by immediate
182 #define IMM16 10 // 16-bit immediate
183 #define RJUMP 11 // Unconditional jump to register
184 #define UJUMP 12 // Unconditional jump
185 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
186 #define SJUMP 14 // Conditional branch (regimm format)
187 #define COP0 15 // Coprocessor 0
188 #define COP1 16 // Coprocessor 1
189 #define C1LS 17 // Coprocessor 1 load/store
190 #define FJUMP 18 // Conditional branch (floating point)
191 #define FLOAT 19 // Floating point unit
192 #define FCONV 20 // Convert integer to float
193 #define FCOMP 21 // Floating point compare (sets FSREG)
194 #define SYSCALL 22// SYSCALL
195 #define OTHER 23 // Other
196 #define SPAN 24 // Branch/delay slot spans 2 pages
197 #define NI 25 // Not implemented
198 #define HLECALL 26// PCSX fake opcodes for HLE
199 #define COP2 27 // Coprocessor 2 move
200 #define C2LS 28 // Coprocessor 2 load/store
201 #define C2OP 29 // Coprocessor 2 operation
202 #define INTCALL 30// Call interpreter to handle rare corner cases
211 #define LOADBU_STUB 7
212 #define LOADHU_STUB 8
213 #define STOREB_STUB 9
214 #define STOREH_STUB 10
215 #define STOREW_STUB 11
216 #define STORED_STUB 12
217 #define STORELR_STUB 13
218 #define INVCODE_STUB 14
226 int new_recompile_block(int addr);
227 void *get_addr_ht(u_int vaddr);
228 void invalidate_block(u_int block);
229 void invalidate_addr(u_int addr);
230 void remove_hash(int vaddr);
233 void dyna_linker_ds();
235 void verify_code_vm();
236 void verify_code_ds();
239 void fp_exception_ds();
241 void jump_syscall_hle();
245 void new_dyna_leave();
250 void read_nomem_new();
251 void read_nomemb_new();
252 void read_nomemh_new();
253 void read_nomemd_new();
254 void write_nomem_new();
255 void write_nomemb_new();
256 void write_nomemh_new();
257 void write_nomemd_new();
258 void write_rdram_new();
259 void write_rdramb_new();
260 void write_rdramh_new();
261 void write_rdramd_new();
262 extern u_int memory_map[1048576];
264 // Needed by assembler
265 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
266 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
267 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
268 void load_all_regs(signed char i_regmap[]);
269 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
270 void load_regs_entry(int t);
271 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
275 //#define DEBUG_CYCLE_COUNT 1
277 int cycle_multiplier; // 100 for 1.0
279 static int CLOCK_ADJUST(int x)
282 return (x * cycle_multiplier + s * 50) / 100;
285 static void tlb_hacks()
289 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
293 switch (ROM_HEADER->Country_code&0xFF)
305 // Unknown country code
309 u_int rom_addr=(u_int)rom;
311 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
312 // in the lower 4G of memory to use this hack. Copy it if necessary.
313 if((void *)rom>(void *)0xffffffff) {
314 munmap(ROM_COPY, 67108864);
315 if(mmap(ROM_COPY, 12582912,
316 PROT_READ | PROT_WRITE,
317 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
318 -1, 0) <= 0) {printf("mmap() failed\n");}
319 memcpy(ROM_COPY,rom,12582912);
320 rom_addr=(u_int)ROM_COPY;
324 for(n=0x7F000;n<0x80000;n++) {
325 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
332 static u_int get_page(u_int vaddr)
335 u_int page=(vaddr^0x80000000)>>12;
337 u_int page=vaddr&~0xe0000000;
338 if (page < 0x1000000)
339 page &= ~0x0e00000; // RAM mirrors
343 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
345 if(page>2048) page=2048+(page&2047);
350 static u_int get_vpage(u_int vaddr)
352 u_int vpage=(vaddr^0x80000000)>>12;
354 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
356 if(vpage>2048) vpage=2048+(vpage&2047);
360 // no virtual mem in PCSX
361 static u_int get_vpage(u_int vaddr)
363 return get_page(vaddr);
367 // Get address from virtual address
368 // This is called from the recompiled JR/JALR instructions
369 void *get_addr(u_int vaddr)
371 u_int page=get_page(vaddr);
372 u_int vpage=get_vpage(vaddr);
373 struct ll_entry *head;
374 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
377 if(head->vaddr==vaddr&&head->reg32==0) {
378 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
379 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
382 ht_bin[1]=(int)head->addr;
388 head=jump_dirty[vpage];
390 if(head->vaddr==vaddr&&head->reg32==0) {
391 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
392 // Don't restore blocks which are about to expire from the cache
393 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
394 if(verify_dirty(head->addr)) {
395 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
396 invalid_code[vaddr>>12]=0;
397 inv_code_start=inv_code_end=~0;
399 memory_map[vaddr>>12]|=0x40000000;
403 if(tlb_LUT_r[vaddr>>12]) {
404 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
405 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
408 restore_candidate[vpage>>3]|=1<<(vpage&7);
410 else restore_candidate[page>>3]|=1<<(page&7);
411 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
412 if(ht_bin[0]==vaddr) {
413 ht_bin[1]=(int)head->addr; // Replace existing entry
419 ht_bin[1]=(int)head->addr;
427 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
428 int r=new_recompile_block(vaddr);
429 if(r==0) return get_addr(vaddr);
430 // Execute in unmapped page, generate pagefault execption
432 Cause=(vaddr<<31)|0x8;
433 EPC=(vaddr&1)?vaddr-5:vaddr;
435 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
436 EntryHi=BadVAddr&0xFFFFE000;
437 return get_addr_ht(0x80000000);
439 // Look up address in hash table first
440 void *get_addr_ht(u_int vaddr)
442 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
443 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
444 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
445 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
446 return get_addr(vaddr);
449 void *get_addr_32(u_int vaddr,u_int flags)
452 return get_addr(vaddr);
454 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
455 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
456 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
457 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
458 u_int page=get_page(vaddr);
459 u_int vpage=get_vpage(vaddr);
460 struct ll_entry *head;
463 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
464 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
466 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
468 ht_bin[1]=(int)head->addr;
470 }else if(ht_bin[2]==-1) {
471 ht_bin[3]=(int)head->addr;
474 //ht_bin[3]=ht_bin[1];
475 //ht_bin[2]=ht_bin[0];
476 //ht_bin[1]=(int)head->addr;
483 head=jump_dirty[vpage];
485 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
486 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
487 // Don't restore blocks which are about to expire from the cache
488 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
489 if(verify_dirty(head->addr)) {
490 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
491 invalid_code[vaddr>>12]=0;
492 inv_code_start=inv_code_end=~0;
493 memory_map[vaddr>>12]|=0x40000000;
496 if(tlb_LUT_r[vaddr>>12]) {
497 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
498 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
501 restore_candidate[vpage>>3]|=1<<(vpage&7);
503 else restore_candidate[page>>3]|=1<<(page&7);
505 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
507 ht_bin[1]=(int)head->addr;
509 }else if(ht_bin[2]==-1) {
510 ht_bin[3]=(int)head->addr;
513 //ht_bin[3]=ht_bin[1];
514 //ht_bin[2]=ht_bin[0];
515 //ht_bin[1]=(int)head->addr;
523 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
524 int r=new_recompile_block(vaddr);
525 if(r==0) return get_addr(vaddr);
526 // Execute in unmapped page, generate pagefault execption
528 Cause=(vaddr<<31)|0x8;
529 EPC=(vaddr&1)?vaddr-5:vaddr;
531 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
532 EntryHi=BadVAddr&0xFFFFE000;
533 return get_addr_ht(0x80000000);
537 void clear_all_regs(signed char regmap[])
540 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
543 signed char get_reg(signed char regmap[],int r)
546 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
550 // Find a register that is available for two consecutive cycles
551 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
554 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
558 int count_free_regs(signed char regmap[])
562 for(hr=0;hr<HOST_REGS;hr++)
564 if(hr!=EXCLUDE_REG) {
565 if(regmap[hr]<0) count++;
571 void dirty_reg(struct regstat *cur,signed char reg)
575 for (hr=0;hr<HOST_REGS;hr++) {
576 if((cur->regmap[hr]&63)==reg) {
582 // If we dirty the lower half of a 64 bit register which is now being
583 // sign-extended, we need to dump the upper half.
584 // Note: Do this only after completion of the instruction, because
585 // some instructions may need to read the full 64-bit value even if
586 // overwriting it (eg SLTI, DSRA32).
587 static void flush_dirty_uppers(struct regstat *cur)
590 for (hr=0;hr<HOST_REGS;hr++) {
591 if((cur->dirty>>hr)&1) {
594 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
599 void set_const(struct regstat *cur,signed char reg,uint64_t value)
603 for (hr=0;hr<HOST_REGS;hr++) {
604 if(cur->regmap[hr]==reg) {
606 current_constmap[hr]=value;
608 else if((cur->regmap[hr]^64)==reg) {
610 current_constmap[hr]=value>>32;
615 void clear_const(struct regstat *cur,signed char reg)
619 for (hr=0;hr<HOST_REGS;hr++) {
620 if((cur->regmap[hr]&63)==reg) {
621 cur->isconst&=~(1<<hr);
626 int is_const(struct regstat *cur,signed char reg)
631 for (hr=0;hr<HOST_REGS;hr++) {
632 if((cur->regmap[hr]&63)==reg) {
633 return (cur->isconst>>hr)&1;
638 uint64_t get_const(struct regstat *cur,signed char reg)
642 for (hr=0;hr<HOST_REGS;hr++) {
643 if(cur->regmap[hr]==reg) {
644 return current_constmap[hr];
647 printf("Unknown constant in r%d\n",reg);
651 // Least soon needed registers
652 // Look at the next ten instructions and see which registers
653 // will be used. Try not to reallocate these.
654 void lsn(u_char hsn[], int i, int *preferred_reg)
664 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
666 // Don't go past an unconditonal jump
673 if(rs1[i+j]) hsn[rs1[i+j]]=j;
674 if(rs2[i+j]) hsn[rs2[i+j]]=j;
675 if(rt1[i+j]) hsn[rt1[i+j]]=j;
676 if(rt2[i+j]) hsn[rt2[i+j]]=j;
677 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
678 // Stores can allocate zero
682 // On some architectures stores need invc_ptr
683 #if defined(HOST_IMM8)
684 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
688 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
696 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
698 // Follow first branch
699 int t=(ba[i+b]-start)>>2;
700 j=7-b;if(t+j>=slen) j=slen-t-1;
703 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
704 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
705 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
706 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
709 // TODO: preferred register based on backward branch
711 // Delay slot should preferably not overwrite branch conditions or cycle count
712 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
713 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
714 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
720 // Coprocessor load/store needs FTEMP, even if not declared
721 if(itype[i]==C1LS||itype[i]==C2LS) {
724 // Load L/R also uses FTEMP as a temporary register
725 if(itype[i]==LOADLR) {
728 // Also SWL/SWR/SDL/SDR
729 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
732 // Don't remove the TLB registers either
733 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
736 // Don't remove the miniht registers
737 if(itype[i]==UJUMP||itype[i]==RJUMP)
744 // We only want to allocate registers if we're going to use them again soon
745 int needed_again(int r, int i)
751 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
753 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
754 return 0; // Don't need any registers if exiting the block
762 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
764 // Don't go past an unconditonal jump
768 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
775 if(rs1[i+j]==r) rn=j;
776 if(rs2[i+j]==r) rn=j;
777 if((unneeded_reg[i+j]>>r)&1) rn=10;
778 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
786 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
788 // Follow first branch
790 int t=(ba[i+b]-start)>>2;
791 j=7-b;if(t+j>=slen) j=slen-t-1;
794 if(!((unneeded_reg[t+j]>>r)&1)) {
795 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
796 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
806 // Try to match register allocations at the end of a loop with those
808 int loop_reg(int i, int r, int hr)
817 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
819 // Don't go past an unconditonal jump
826 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
831 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
832 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
833 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
835 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
837 int t=(ba[i+k]-start)>>2;
838 int reg=get_reg(regs[t].regmap_entry,r);
839 if(reg>=0) return reg;
840 //reg=get_reg(regs[t+1].regmap_entry,r);
841 //if(reg>=0) return reg;
849 // Allocate every register, preserving source/target regs
850 void alloc_all(struct regstat *cur,int i)
854 for(hr=0;hr<HOST_REGS;hr++) {
855 if(hr!=EXCLUDE_REG) {
856 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
857 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
860 cur->dirty&=~(1<<hr);
863 if((cur->regmap[hr]&63)==0)
866 cur->dirty&=~(1<<hr);
873 void div64(int64_t dividend,int64_t divisor)
877 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
878 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
880 void divu64(uint64_t dividend,uint64_t divisor)
884 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
885 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
888 void mult64(uint64_t m1,uint64_t m2)
890 unsigned long long int op1, op2, op3, op4;
891 unsigned long long int result1, result2, result3, result4;
892 unsigned long long int temp1, temp2, temp3, temp4;
908 op1 = op2 & 0xFFFFFFFF;
909 op2 = (op2 >> 32) & 0xFFFFFFFF;
910 op3 = op4 & 0xFFFFFFFF;
911 op4 = (op4 >> 32) & 0xFFFFFFFF;
914 temp2 = (temp1 >> 32) + op1 * op4;
916 temp4 = (temp3 >> 32) + op2 * op4;
918 result1 = temp1 & 0xFFFFFFFF;
919 result2 = temp2 + (temp3 & 0xFFFFFFFF);
920 result3 = (result2 >> 32) + temp4;
921 result4 = (result3 >> 32);
923 lo = result1 | (result2 << 32);
924 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
933 void multu64(uint64_t m1,uint64_t m2)
935 unsigned long long int op1, op2, op3, op4;
936 unsigned long long int result1, result2, result3, result4;
937 unsigned long long int temp1, temp2, temp3, temp4;
939 op1 = m1 & 0xFFFFFFFF;
940 op2 = (m1 >> 32) & 0xFFFFFFFF;
941 op3 = m2 & 0xFFFFFFFF;
942 op4 = (m2 >> 32) & 0xFFFFFFFF;
945 temp2 = (temp1 >> 32) + op1 * op4;
947 temp4 = (temp3 >> 32) + op2 * op4;
949 result1 = temp1 & 0xFFFFFFFF;
950 result2 = temp2 + (temp3 & 0xFFFFFFFF);
951 result3 = (result2 >> 32) + temp4;
952 result4 = (result3 >> 32);
954 lo = result1 | (result2 << 32);
955 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
957 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
958 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
961 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
969 else original=loaded;
972 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
975 original>>=64-(bits^56);
976 original<<=64-(bits^56);
980 else original=loaded;
986 #include "assem_x86.c"
989 #include "assem_x64.c"
992 #include "assem_arm.c"
995 // Add virtual address mapping to linked list
996 void ll_add(struct ll_entry **head,int vaddr,void *addr)
998 struct ll_entry *new_entry;
999 new_entry=malloc(sizeof(struct ll_entry));
1000 assert(new_entry!=NULL);
1001 new_entry->vaddr=vaddr;
1003 new_entry->addr=addr;
1004 new_entry->next=*head;
1008 // Add virtual address mapping for 32-bit compiled block
1009 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1011 ll_add(head,vaddr,addr);
1013 (*head)->reg32=reg32;
1017 // Check if an address is already compiled
1018 // but don't return addresses which are about to expire from the cache
1019 void *check_addr(u_int vaddr)
1021 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1022 if(ht_bin[0]==vaddr) {
1023 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1024 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1026 if(ht_bin[2]==vaddr) {
1027 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1028 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1030 u_int page=get_page(vaddr);
1031 struct ll_entry *head;
1034 if(head->vaddr==vaddr&&head->reg32==0) {
1035 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1036 // Update existing entry with current address
1037 if(ht_bin[0]==vaddr) {
1038 ht_bin[1]=(int)head->addr;
1041 if(ht_bin[2]==vaddr) {
1042 ht_bin[3]=(int)head->addr;
1045 // Insert into hash table with low priority.
1046 // Don't evict existing entries, as they are probably
1047 // addresses that are being accessed frequently.
1049 ht_bin[1]=(int)head->addr;
1051 }else if(ht_bin[2]==-1) {
1052 ht_bin[3]=(int)head->addr;
1063 void remove_hash(int vaddr)
1065 //printf("remove hash: %x\n",vaddr);
1066 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1067 if(ht_bin[2]==vaddr) {
1068 ht_bin[2]=ht_bin[3]=-1;
1070 if(ht_bin[0]==vaddr) {
1071 ht_bin[0]=ht_bin[2];
1072 ht_bin[1]=ht_bin[3];
1073 ht_bin[2]=ht_bin[3]=-1;
1077 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1079 struct ll_entry *next;
1081 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1082 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1084 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1085 remove_hash((*head)->vaddr);
1092 head=&((*head)->next);
1097 // Remove all entries from linked list
1098 void ll_clear(struct ll_entry **head)
1100 struct ll_entry *cur;
1101 struct ll_entry *next;
1112 // Dereference the pointers and remove if it matches
1113 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1116 int ptr=get_pointer(head->addr);
1117 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1118 if(((ptr>>shift)==(addr>>shift)) ||
1119 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1121 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1122 u_int host_addr=(u_int)kill_pointer(head->addr);
1124 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1131 // This is called when we write to a compiled block (see do_invstub)
1132 void invalidate_page(u_int page)
1134 struct ll_entry *head;
1135 struct ll_entry *next;
1139 inv_debug("INVALIDATE: %x\n",head->vaddr);
1140 remove_hash(head->vaddr);
1145 head=jump_out[page];
1148 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1149 u_int host_addr=(u_int)kill_pointer(head->addr);
1151 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1159 static void invalidate_block_range(u_int block, u_int first, u_int last)
1161 u_int page=get_page(block<<12);
1162 //printf("first=%d last=%d\n",first,last);
1163 invalidate_page(page);
1164 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1165 assert(last<page+5);
1166 // Invalidate the adjacent pages if a block crosses a 4K boundary
1168 invalidate_page(first);
1171 for(first=page+1;first<last;first++) {
1172 invalidate_page(first);
1178 // Don't trap writes
1179 invalid_code[block]=1;
1181 // If there is a valid TLB entry for this page, remove write protect
1182 if(tlb_LUT_w[block]) {
1183 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1184 // CHECK: Is this right?
1185 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1186 u_int real_block=tlb_LUT_w[block]>>12;
1187 invalid_code[real_block]=1;
1188 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1190 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1194 memset(mini_ht,-1,sizeof(mini_ht));
1198 void invalidate_block(u_int block)
1200 u_int page=get_page(block<<12);
1201 u_int vpage=get_vpage(block<<12);
1202 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1203 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1206 struct ll_entry *head;
1207 head=jump_dirty[vpage];
1208 //printf("page=%d vpage=%d\n",page,vpage);
1211 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1212 get_bounds((int)head->addr,&start,&end);
1213 //printf("start: %x end: %x\n",start,end);
1214 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1215 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1216 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1217 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1221 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1222 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1223 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1224 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1231 invalidate_block_range(block,first,last);
1234 void invalidate_addr(u_int addr)
1238 // this check is done by the caller
1239 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1240 u_int page=get_vpage(addr);
1241 if(page<2048) { // RAM
1242 struct ll_entry *head;
1243 u_int addr_min=~0, addr_max=0;
1244 int mask=RAM_SIZE-1;
1246 inv_code_start=addr&~0xfff;
1247 inv_code_end=addr|0xfff;
1250 // must check previous page too because of spans..
1252 inv_code_start-=0x1000;
1254 for(;pg1<=page;pg1++) {
1255 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1257 get_bounds((int)head->addr,&start,&end);
1258 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1259 if(start<addr_min) addr_min=start;
1260 if(end>addr_max) addr_max=end;
1262 else if(addr<start) {
1263 if(start<inv_code_end)
1264 inv_code_end=start-1;
1267 if(end>inv_code_start)
1273 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1274 inv_code_start=inv_code_end=~0;
1275 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1279 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1284 invalidate_block(addr>>12);
1287 // This is called when loading a save state.
1288 // Anything could have changed, so invalidate everything.
1289 void invalidate_all_pages()
1292 for(page=0;page<4096;page++)
1293 invalidate_page(page);
1294 for(page=0;page<1048576;page++)
1295 if(!invalid_code[page]) {
1296 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1297 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1300 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1303 memset(mini_ht,-1,sizeof(mini_ht));
1307 for(page=0;page<0x100000;page++) {
1308 if(tlb_LUT_r[page]) {
1309 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1310 if(!tlb_LUT_w[page]||!invalid_code[page])
1311 memory_map[page]|=0x40000000; // Write protect
1313 else memory_map[page]=-1;
1314 if(page==0x80000) page=0xC0000;
1320 // Add an entry to jump_out after making a link
1321 void add_link(u_int vaddr,void *src)
1323 u_int page=get_page(vaddr);
1324 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1325 int *ptr=(int *)(src+4);
1326 assert((*ptr&0x0fff0000)==0x059f0000);
1327 ll_add(jump_out+page,vaddr,src);
1328 //int ptr=get_pointer(src);
1329 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1332 // If a code block was found to be unmodified (bit was set in
1333 // restore_candidate) and it remains unmodified (bit is clear
1334 // in invalid_code) then move the entries for that 4K page from
1335 // the dirty list to the clean list.
1336 void clean_blocks(u_int page)
1338 struct ll_entry *head;
1339 inv_debug("INV: clean_blocks page=%d\n",page);
1340 head=jump_dirty[page];
1342 if(!invalid_code[head->vaddr>>12]) {
1343 // Don't restore blocks which are about to expire from the cache
1344 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1346 if(verify_dirty((int)head->addr)) {
1347 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1350 get_bounds((int)head->addr,&start,&end);
1351 if(start-(u_int)rdram<RAM_SIZE) {
1352 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1353 inv|=invalid_code[i];
1357 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1358 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1359 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1360 if(addr<start||addr>=end) inv=1;
1363 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1367 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1368 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1371 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1373 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1374 //printf("page=%x, addr=%x\n",page,head->vaddr);
1375 //assert(head->vaddr>>12==(page|0x80000));
1376 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1377 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1379 if(ht_bin[0]==head->vaddr) {
1380 ht_bin[1]=(int)clean_addr; // Replace existing entry
1382 if(ht_bin[2]==head->vaddr) {
1383 ht_bin[3]=(int)clean_addr; // Replace existing entry
1396 void mov_alloc(struct regstat *current,int i)
1398 // Note: Don't need to actually alloc the source registers
1399 if((~current->is32>>rs1[i])&1) {
1400 //alloc_reg64(current,i,rs1[i]);
1401 alloc_reg64(current,i,rt1[i]);
1402 current->is32&=~(1LL<<rt1[i]);
1404 //alloc_reg(current,i,rs1[i]);
1405 alloc_reg(current,i,rt1[i]);
1406 current->is32|=(1LL<<rt1[i]);
1408 clear_const(current,rs1[i]);
1409 clear_const(current,rt1[i]);
1410 dirty_reg(current,rt1[i]);
1413 void shiftimm_alloc(struct regstat *current,int i)
1415 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1418 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1420 alloc_reg(current,i,rt1[i]);
1421 current->is32|=1LL<<rt1[i];
1422 dirty_reg(current,rt1[i]);
1423 if(is_const(current,rs1[i])) {
1424 int v=get_const(current,rs1[i]);
1425 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1426 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1427 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1429 else clear_const(current,rt1[i]);
1434 clear_const(current,rs1[i]);
1435 clear_const(current,rt1[i]);
1438 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1441 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1442 alloc_reg64(current,i,rt1[i]);
1443 current->is32&=~(1LL<<rt1[i]);
1444 dirty_reg(current,rt1[i]);
1447 if(opcode2[i]==0x3c) // DSLL32
1450 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1451 alloc_reg64(current,i,rt1[i]);
1452 current->is32&=~(1LL<<rt1[i]);
1453 dirty_reg(current,rt1[i]);
1456 if(opcode2[i]==0x3e) // DSRL32
1459 alloc_reg64(current,i,rs1[i]);
1461 alloc_reg64(current,i,rt1[i]);
1462 current->is32&=~(1LL<<rt1[i]);
1464 alloc_reg(current,i,rt1[i]);
1465 current->is32|=1LL<<rt1[i];
1467 dirty_reg(current,rt1[i]);
1470 if(opcode2[i]==0x3f) // DSRA32
1473 alloc_reg64(current,i,rs1[i]);
1474 alloc_reg(current,i,rt1[i]);
1475 current->is32|=1LL<<rt1[i];
1476 dirty_reg(current,rt1[i]);
1481 void shift_alloc(struct regstat *current,int i)
1484 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1486 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1487 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1488 alloc_reg(current,i,rt1[i]);
1489 if(rt1[i]==rs2[i]) {
1490 alloc_reg_temp(current,i,-1);
1491 minimum_free_regs[i]=1;
1493 current->is32|=1LL<<rt1[i];
1494 } else { // DSLLV/DSRLV/DSRAV
1495 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1496 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1497 alloc_reg64(current,i,rt1[i]);
1498 current->is32&=~(1LL<<rt1[i]);
1499 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1501 alloc_reg_temp(current,i,-1);
1502 minimum_free_regs[i]=1;
1505 clear_const(current,rs1[i]);
1506 clear_const(current,rs2[i]);
1507 clear_const(current,rt1[i]);
1508 dirty_reg(current,rt1[i]);
1512 void alu_alloc(struct regstat *current,int i)
1514 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1516 if(rs1[i]&&rs2[i]) {
1517 alloc_reg(current,i,rs1[i]);
1518 alloc_reg(current,i,rs2[i]);
1521 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1522 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1524 alloc_reg(current,i,rt1[i]);
1526 current->is32|=1LL<<rt1[i];
1528 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1530 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1532 alloc_reg64(current,i,rs1[i]);
1533 alloc_reg64(current,i,rs2[i]);
1534 alloc_reg(current,i,rt1[i]);
1536 alloc_reg(current,i,rs1[i]);
1537 alloc_reg(current,i,rs2[i]);
1538 alloc_reg(current,i,rt1[i]);
1541 current->is32|=1LL<<rt1[i];
1543 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1545 if(rs1[i]&&rs2[i]) {
1546 alloc_reg(current,i,rs1[i]);
1547 alloc_reg(current,i,rs2[i]);
1551 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1552 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1554 alloc_reg(current,i,rt1[i]);
1555 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1557 if(!((current->uu>>rt1[i])&1)) {
1558 alloc_reg64(current,i,rt1[i]);
1560 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1561 if(rs1[i]&&rs2[i]) {
1562 alloc_reg64(current,i,rs1[i]);
1563 alloc_reg64(current,i,rs2[i]);
1567 // Is is really worth it to keep 64-bit values in registers?
1569 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1570 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1574 current->is32&=~(1LL<<rt1[i]);
1576 current->is32|=1LL<<rt1[i];
1580 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1582 if(rs1[i]&&rs2[i]) {
1583 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1584 alloc_reg64(current,i,rs1[i]);
1585 alloc_reg64(current,i,rs2[i]);
1586 alloc_reg64(current,i,rt1[i]);
1588 alloc_reg(current,i,rs1[i]);
1589 alloc_reg(current,i,rs2[i]);
1590 alloc_reg(current,i,rt1[i]);
1594 alloc_reg(current,i,rt1[i]);
1595 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1596 // DADD used as move, or zeroing
1597 // If we have a 64-bit source, then make the target 64 bits too
1598 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1599 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1600 alloc_reg64(current,i,rt1[i]);
1601 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1602 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1603 alloc_reg64(current,i,rt1[i]);
1605 if(opcode2[i]>=0x2e&&rs2[i]) {
1606 // DSUB used as negation - 64-bit result
1607 // If we have a 32-bit register, extend it to 64 bits
1608 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1609 alloc_reg64(current,i,rt1[i]);
1613 if(rs1[i]&&rs2[i]) {
1614 current->is32&=~(1LL<<rt1[i]);
1616 current->is32&=~(1LL<<rt1[i]);
1617 if((current->is32>>rs1[i])&1)
1618 current->is32|=1LL<<rt1[i];
1620 current->is32&=~(1LL<<rt1[i]);
1621 if((current->is32>>rs2[i])&1)
1622 current->is32|=1LL<<rt1[i];
1624 current->is32|=1LL<<rt1[i];
1628 clear_const(current,rs1[i]);
1629 clear_const(current,rs2[i]);
1630 clear_const(current,rt1[i]);
1631 dirty_reg(current,rt1[i]);
1634 void imm16_alloc(struct regstat *current,int i)
1636 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1638 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1639 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1640 current->is32&=~(1LL<<rt1[i]);
1641 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1642 // TODO: Could preserve the 32-bit flag if the immediate is zero
1643 alloc_reg64(current,i,rt1[i]);
1644 alloc_reg64(current,i,rs1[i]);
1646 clear_const(current,rs1[i]);
1647 clear_const(current,rt1[i]);
1649 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1650 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1651 current->is32|=1LL<<rt1[i];
1652 clear_const(current,rs1[i]);
1653 clear_const(current,rt1[i]);
1655 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1656 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1657 if(rs1[i]!=rt1[i]) {
1658 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1659 alloc_reg64(current,i,rt1[i]);
1660 current->is32&=~(1LL<<rt1[i]);
1663 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1664 if(is_const(current,rs1[i])) {
1665 int v=get_const(current,rs1[i]);
1666 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1667 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1668 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1670 else clear_const(current,rt1[i]);
1672 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1673 if(is_const(current,rs1[i])) {
1674 int v=get_const(current,rs1[i]);
1675 set_const(current,rt1[i],v+imm[i]);
1677 else clear_const(current,rt1[i]);
1678 current->is32|=1LL<<rt1[i];
1681 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1682 current->is32|=1LL<<rt1[i];
1684 dirty_reg(current,rt1[i]);
1687 void load_alloc(struct regstat *current,int i)
1689 clear_const(current,rt1[i]);
1690 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1691 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1692 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1693 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1694 alloc_reg(current,i,rt1[i]);
1695 assert(get_reg(current->regmap,rt1[i])>=0);
1696 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1698 current->is32&=~(1LL<<rt1[i]);
1699 alloc_reg64(current,i,rt1[i]);
1701 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1703 current->is32&=~(1LL<<rt1[i]);
1704 alloc_reg64(current,i,rt1[i]);
1705 alloc_all(current,i);
1706 alloc_reg64(current,i,FTEMP);
1707 minimum_free_regs[i]=HOST_REGS;
1709 else current->is32|=1LL<<rt1[i];
1710 dirty_reg(current,rt1[i]);
1711 // If using TLB, need a register for pointer to the mapping table
1712 if(using_tlb) alloc_reg(current,i,TLREG);
1713 // LWL/LWR need a temporary register for the old value
1714 if(opcode[i]==0x22||opcode[i]==0x26)
1716 alloc_reg(current,i,FTEMP);
1717 alloc_reg_temp(current,i,-1);
1718 minimum_free_regs[i]=1;
1723 // Load to r0 or unneeded register (dummy load)
1724 // but we still need a register to calculate the address
1725 if(opcode[i]==0x22||opcode[i]==0x26)
1727 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1729 // If using TLB, need a register for pointer to the mapping table
1730 if(using_tlb) alloc_reg(current,i,TLREG);
1731 alloc_reg_temp(current,i,-1);
1732 minimum_free_regs[i]=1;
1733 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1735 alloc_all(current,i);
1736 alloc_reg64(current,i,FTEMP);
1737 minimum_free_regs[i]=HOST_REGS;
1742 void store_alloc(struct regstat *current,int i)
1744 clear_const(current,rs2[i]);
1745 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1746 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1747 alloc_reg(current,i,rs2[i]);
1748 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1749 alloc_reg64(current,i,rs2[i]);
1750 if(rs2[i]) alloc_reg(current,i,FTEMP);
1752 // If using TLB, need a register for pointer to the mapping table
1753 if(using_tlb) alloc_reg(current,i,TLREG);
1754 #if defined(HOST_IMM8)
1755 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1756 else alloc_reg(current,i,INVCP);
1758 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1759 alloc_reg(current,i,FTEMP);
1761 // We need a temporary register for address generation
1762 alloc_reg_temp(current,i,-1);
1763 minimum_free_regs[i]=1;
1766 void c1ls_alloc(struct regstat *current,int i)
1768 //clear_const(current,rs1[i]); // FIXME
1769 clear_const(current,rt1[i]);
1770 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1771 alloc_reg(current,i,CSREG); // Status
1772 alloc_reg(current,i,FTEMP);
1773 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1774 alloc_reg64(current,i,FTEMP);
1776 // If using TLB, need a register for pointer to the mapping table
1777 if(using_tlb) alloc_reg(current,i,TLREG);
1778 #if defined(HOST_IMM8)
1779 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1780 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1781 alloc_reg(current,i,INVCP);
1783 // We need a temporary register for address generation
1784 alloc_reg_temp(current,i,-1);
1787 void c2ls_alloc(struct regstat *current,int i)
1789 clear_const(current,rt1[i]);
1790 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1791 alloc_reg(current,i,FTEMP);
1792 // If using TLB, need a register for pointer to the mapping table
1793 if(using_tlb) alloc_reg(current,i,TLREG);
1794 #if defined(HOST_IMM8)
1795 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1796 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1797 alloc_reg(current,i,INVCP);
1799 // We need a temporary register for address generation
1800 alloc_reg_temp(current,i,-1);
1801 minimum_free_regs[i]=1;
1804 #ifndef multdiv_alloc
1805 void multdiv_alloc(struct regstat *current,int i)
1812 // case 0x1D: DMULTU
1815 clear_const(current,rs1[i]);
1816 clear_const(current,rs2[i]);
1819 if((opcode2[i]&4)==0) // 32-bit
1821 current->u&=~(1LL<<HIREG);
1822 current->u&=~(1LL<<LOREG);
1823 alloc_reg(current,i,HIREG);
1824 alloc_reg(current,i,LOREG);
1825 alloc_reg(current,i,rs1[i]);
1826 alloc_reg(current,i,rs2[i]);
1827 current->is32|=1LL<<HIREG;
1828 current->is32|=1LL<<LOREG;
1829 dirty_reg(current,HIREG);
1830 dirty_reg(current,LOREG);
1834 current->u&=~(1LL<<HIREG);
1835 current->u&=~(1LL<<LOREG);
1836 current->uu&=~(1LL<<HIREG);
1837 current->uu&=~(1LL<<LOREG);
1838 alloc_reg64(current,i,HIREG);
1839 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1840 alloc_reg64(current,i,rs1[i]);
1841 alloc_reg64(current,i,rs2[i]);
1842 alloc_all(current,i);
1843 current->is32&=~(1LL<<HIREG);
1844 current->is32&=~(1LL<<LOREG);
1845 dirty_reg(current,HIREG);
1846 dirty_reg(current,LOREG);
1847 minimum_free_regs[i]=HOST_REGS;
1852 // Multiply by zero is zero.
1853 // MIPS does not have a divide by zero exception.
1854 // The result is undefined, we return zero.
1855 alloc_reg(current,i,HIREG);
1856 alloc_reg(current,i,LOREG);
1857 current->is32|=1LL<<HIREG;
1858 current->is32|=1LL<<LOREG;
1859 dirty_reg(current,HIREG);
1860 dirty_reg(current,LOREG);
1865 void cop0_alloc(struct regstat *current,int i)
1867 if(opcode2[i]==0) // MFC0
1870 clear_const(current,rt1[i]);
1871 alloc_all(current,i);
1872 alloc_reg(current,i,rt1[i]);
1873 current->is32|=1LL<<rt1[i];
1874 dirty_reg(current,rt1[i]);
1877 else if(opcode2[i]==4) // MTC0
1880 clear_const(current,rs1[i]);
1881 alloc_reg(current,i,rs1[i]);
1882 alloc_all(current,i);
1885 alloc_all(current,i); // FIXME: Keep r0
1887 alloc_reg(current,i,0);
1892 // TLBR/TLBWI/TLBWR/TLBP/ERET
1893 assert(opcode2[i]==0x10);
1894 alloc_all(current,i);
1896 minimum_free_regs[i]=HOST_REGS;
1899 void cop1_alloc(struct regstat *current,int i)
1901 alloc_reg(current,i,CSREG); // Load status
1902 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1905 clear_const(current,rt1[i]);
1907 alloc_reg64(current,i,rt1[i]); // DMFC1
1908 current->is32&=~(1LL<<rt1[i]);
1910 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1911 current->is32|=1LL<<rt1[i];
1913 dirty_reg(current,rt1[i]);
1915 alloc_reg_temp(current,i,-1);
1917 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1920 clear_const(current,rs1[i]);
1922 alloc_reg64(current,i,rs1[i]); // DMTC1
1924 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1925 alloc_reg_temp(current,i,-1);
1929 alloc_reg(current,i,0);
1930 alloc_reg_temp(current,i,-1);
1933 minimum_free_regs[i]=1;
1935 void fconv_alloc(struct regstat *current,int i)
1937 alloc_reg(current,i,CSREG); // Load status
1938 alloc_reg_temp(current,i,-1);
1939 minimum_free_regs[i]=1;
1941 void float_alloc(struct regstat *current,int i)
1943 alloc_reg(current,i,CSREG); // Load status
1944 alloc_reg_temp(current,i,-1);
1945 minimum_free_regs[i]=1;
1947 void c2op_alloc(struct regstat *current,int i)
1949 alloc_reg_temp(current,i,-1);
1951 void fcomp_alloc(struct regstat *current,int i)
1953 alloc_reg(current,i,CSREG); // Load status
1954 alloc_reg(current,i,FSREG); // Load flags
1955 dirty_reg(current,FSREG); // Flag will be modified
1956 alloc_reg_temp(current,i,-1);
1957 minimum_free_regs[i]=1;
1960 void syscall_alloc(struct regstat *current,int i)
1962 alloc_cc(current,i);
1963 dirty_reg(current,CCREG);
1964 alloc_all(current,i);
1965 minimum_free_regs[i]=HOST_REGS;
1969 void delayslot_alloc(struct regstat *current,int i)
1980 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1981 printf("Disabled speculative precompilation\n");
1985 imm16_alloc(current,i);
1989 load_alloc(current,i);
1993 store_alloc(current,i);
1996 alu_alloc(current,i);
1999 shift_alloc(current,i);
2002 multdiv_alloc(current,i);
2005 shiftimm_alloc(current,i);
2008 mov_alloc(current,i);
2011 cop0_alloc(current,i);
2015 cop1_alloc(current,i);
2018 c1ls_alloc(current,i);
2021 c2ls_alloc(current,i);
2024 fconv_alloc(current,i);
2027 float_alloc(current,i);
2030 fcomp_alloc(current,i);
2033 c2op_alloc(current,i);
2038 // Special case where a branch and delay slot span two pages in virtual memory
2039 static void pagespan_alloc(struct regstat *current,int i)
2042 current->wasconst=0;
2044 minimum_free_regs[i]=HOST_REGS;
2045 alloc_all(current,i);
2046 alloc_cc(current,i);
2047 dirty_reg(current,CCREG);
2048 if(opcode[i]==3) // JAL
2050 alloc_reg(current,i,31);
2051 dirty_reg(current,31);
2053 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2055 alloc_reg(current,i,rs1[i]);
2057 alloc_reg(current,i,rt1[i]);
2058 dirty_reg(current,rt1[i]);
2061 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2063 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2064 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2065 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2067 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2068 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2072 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2074 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2075 if(!((current->is32>>rs1[i])&1))
2077 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2081 if(opcode[i]==0x11) // BC1
2083 alloc_reg(current,i,FSREG);
2084 alloc_reg(current,i,CSREG);
2089 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2091 stubs[stubcount][0]=type;
2092 stubs[stubcount][1]=addr;
2093 stubs[stubcount][2]=retaddr;
2094 stubs[stubcount][3]=a;
2095 stubs[stubcount][4]=b;
2096 stubs[stubcount][5]=c;
2097 stubs[stubcount][6]=d;
2098 stubs[stubcount][7]=e;
2102 // Write out a single register
2103 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2106 for(hr=0;hr<HOST_REGS;hr++) {
2107 if(hr!=EXCLUDE_REG) {
2108 if((regmap[hr]&63)==r) {
2111 emit_storereg(r,hr);
2113 if((is32>>regmap[hr])&1) {
2114 emit_sarimm(hr,31,hr);
2115 emit_storereg(r|64,hr);
2119 emit_storereg(r|64,hr);
2129 //if(!tracedebug) return 0;
2132 for(i=0;i<2097152;i++) {
2133 unsigned int temp=sum;
2136 sum^=((u_int *)rdram)[i];
2145 sum^=((u_int *)reg)[i];
2153 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2155 #ifndef DISABLE_COP1
2158 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2168 void memdebug(int i)
2170 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2171 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2174 //if(Count>=-2084597794) {
2175 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2177 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2178 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2179 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2182 printf("TRACE: %x\n",(&i)[-1]);
2186 printf("TRACE: %x \n",(&j)[10]);
2187 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2191 //printf("TRACE: %x\n",(&i)[-1]);
2194 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2196 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2199 void alu_assemble(int i,struct regstat *i_regs)
2201 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2203 signed char s1,s2,t;
2204 t=get_reg(i_regs->regmap,rt1[i]);
2206 s1=get_reg(i_regs->regmap,rs1[i]);
2207 s2=get_reg(i_regs->regmap,rs2[i]);
2208 if(rs1[i]&&rs2[i]) {
2211 if(opcode2[i]&2) emit_sub(s1,s2,t);
2212 else emit_add(s1,s2,t);
2215 if(s1>=0) emit_mov(s1,t);
2216 else emit_loadreg(rs1[i],t);
2220 if(opcode2[i]&2) emit_neg(s2,t);
2221 else emit_mov(s2,t);
2224 emit_loadreg(rs2[i],t);
2225 if(opcode2[i]&2) emit_neg(t,t);
2228 else emit_zeroreg(t);
2232 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2234 signed char s1l,s2l,s1h,s2h,tl,th;
2235 tl=get_reg(i_regs->regmap,rt1[i]);
2236 th=get_reg(i_regs->regmap,rt1[i]|64);
2238 s1l=get_reg(i_regs->regmap,rs1[i]);
2239 s2l=get_reg(i_regs->regmap,rs2[i]);
2240 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2241 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2242 if(rs1[i]&&rs2[i]) {
2245 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2246 else emit_adds(s1l,s2l,tl);
2248 #ifdef INVERTED_CARRY
2249 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2251 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2253 else emit_add(s1h,s2h,th);
2257 if(s1l>=0) emit_mov(s1l,tl);
2258 else emit_loadreg(rs1[i],tl);
2260 if(s1h>=0) emit_mov(s1h,th);
2261 else emit_loadreg(rs1[i]|64,th);
2266 if(opcode2[i]&2) emit_negs(s2l,tl);
2267 else emit_mov(s2l,tl);
2270 emit_loadreg(rs2[i],tl);
2271 if(opcode2[i]&2) emit_negs(tl,tl);
2274 #ifdef INVERTED_CARRY
2275 if(s2h>=0) emit_mov(s2h,th);
2276 else emit_loadreg(rs2[i]|64,th);
2278 emit_adcimm(-1,th); // x86 has inverted carry flag
2283 if(s2h>=0) emit_rscimm(s2h,0,th);
2285 emit_loadreg(rs2[i]|64,th);
2286 emit_rscimm(th,0,th);
2289 if(s2h>=0) emit_mov(s2h,th);
2290 else emit_loadreg(rs2[i]|64,th);
2297 if(th>=0) emit_zeroreg(th);
2302 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2304 signed char s1l,s1h,s2l,s2h,t;
2305 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2307 t=get_reg(i_regs->regmap,rt1[i]);
2310 s1l=get_reg(i_regs->regmap,rs1[i]);
2311 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2312 s2l=get_reg(i_regs->regmap,rs2[i]);
2313 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2314 if(rs2[i]==0) // rx<r0
2317 if(opcode2[i]==0x2a) // SLT
2318 emit_shrimm(s1h,31,t);
2319 else // SLTU (unsigned can not be less than zero)
2322 else if(rs1[i]==0) // r0<rx
2325 if(opcode2[i]==0x2a) // SLT
2326 emit_set_gz64_32(s2h,s2l,t);
2327 else // SLTU (set if not zero)
2328 emit_set_nz64_32(s2h,s2l,t);
2331 assert(s1l>=0);assert(s1h>=0);
2332 assert(s2l>=0);assert(s2h>=0);
2333 if(opcode2[i]==0x2a) // SLT
2334 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2336 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2340 t=get_reg(i_regs->regmap,rt1[i]);
2343 s1l=get_reg(i_regs->regmap,rs1[i]);
2344 s2l=get_reg(i_regs->regmap,rs2[i]);
2345 if(rs2[i]==0) // rx<r0
2348 if(opcode2[i]==0x2a) // SLT
2349 emit_shrimm(s1l,31,t);
2350 else // SLTU (unsigned can not be less than zero)
2353 else if(rs1[i]==0) // r0<rx
2356 if(opcode2[i]==0x2a) // SLT
2357 emit_set_gz32(s2l,t);
2358 else // SLTU (set if not zero)
2359 emit_set_nz32(s2l,t);
2362 assert(s1l>=0);assert(s2l>=0);
2363 if(opcode2[i]==0x2a) // SLT
2364 emit_set_if_less32(s1l,s2l,t);
2366 emit_set_if_carry32(s1l,s2l,t);
2372 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2374 signed char s1l,s1h,s2l,s2h,th,tl;
2375 tl=get_reg(i_regs->regmap,rt1[i]);
2376 th=get_reg(i_regs->regmap,rt1[i]|64);
2377 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2381 s1l=get_reg(i_regs->regmap,rs1[i]);
2382 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2383 s2l=get_reg(i_regs->regmap,rs2[i]);
2384 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2385 if(rs1[i]&&rs2[i]) {
2386 assert(s1l>=0);assert(s1h>=0);
2387 assert(s2l>=0);assert(s2h>=0);
2388 if(opcode2[i]==0x24) { // AND
2389 emit_and(s1l,s2l,tl);
2390 emit_and(s1h,s2h,th);
2392 if(opcode2[i]==0x25) { // OR
2393 emit_or(s1l,s2l,tl);
2394 emit_or(s1h,s2h,th);
2396 if(opcode2[i]==0x26) { // XOR
2397 emit_xor(s1l,s2l,tl);
2398 emit_xor(s1h,s2h,th);
2400 if(opcode2[i]==0x27) { // NOR
2401 emit_or(s1l,s2l,tl);
2402 emit_or(s1h,s2h,th);
2409 if(opcode2[i]==0x24) { // AND
2413 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2415 if(s1l>=0) emit_mov(s1l,tl);
2416 else emit_loadreg(rs1[i],tl);
2417 if(s1h>=0) emit_mov(s1h,th);
2418 else emit_loadreg(rs1[i]|64,th);
2422 if(s2l>=0) emit_mov(s2l,tl);
2423 else emit_loadreg(rs2[i],tl);
2424 if(s2h>=0) emit_mov(s2h,th);
2425 else emit_loadreg(rs2[i]|64,th);
2432 if(opcode2[i]==0x27) { // NOR
2434 if(s1l>=0) emit_not(s1l,tl);
2436 emit_loadreg(rs1[i],tl);
2439 if(s1h>=0) emit_not(s1h,th);
2441 emit_loadreg(rs1[i]|64,th);
2447 if(s2l>=0) emit_not(s2l,tl);
2449 emit_loadreg(rs2[i],tl);
2452 if(s2h>=0) emit_not(s2h,th);
2454 emit_loadreg(rs2[i]|64,th);
2470 s1l=get_reg(i_regs->regmap,rs1[i]);
2471 s2l=get_reg(i_regs->regmap,rs2[i]);
2472 if(rs1[i]&&rs2[i]) {
2475 if(opcode2[i]==0x24) { // AND
2476 emit_and(s1l,s2l,tl);
2478 if(opcode2[i]==0x25) { // OR
2479 emit_or(s1l,s2l,tl);
2481 if(opcode2[i]==0x26) { // XOR
2482 emit_xor(s1l,s2l,tl);
2484 if(opcode2[i]==0x27) { // NOR
2485 emit_or(s1l,s2l,tl);
2491 if(opcode2[i]==0x24) { // AND
2494 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2496 if(s1l>=0) emit_mov(s1l,tl);
2497 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2501 if(s2l>=0) emit_mov(s2l,tl);
2502 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2504 else emit_zeroreg(tl);
2506 if(opcode2[i]==0x27) { // NOR
2508 if(s1l>=0) emit_not(s1l,tl);
2510 emit_loadreg(rs1[i],tl);
2516 if(s2l>=0) emit_not(s2l,tl);
2518 emit_loadreg(rs2[i],tl);
2522 else emit_movimm(-1,tl);
2531 void imm16_assemble(int i,struct regstat *i_regs)
2533 if (opcode[i]==0x0f) { // LUI
2536 t=get_reg(i_regs->regmap,rt1[i]);
2539 if(!((i_regs->isconst>>t)&1))
2540 emit_movimm(imm[i]<<16,t);
2544 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2547 t=get_reg(i_regs->regmap,rt1[i]);
2548 s=get_reg(i_regs->regmap,rs1[i]);
2553 if(!((i_regs->isconst>>t)&1)) {
2555 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2556 emit_addimm(t,imm[i],t);
2558 if(!((i_regs->wasconst>>s)&1))
2559 emit_addimm(s,imm[i],t);
2561 emit_movimm(constmap[i][s]+imm[i],t);
2567 if(!((i_regs->isconst>>t)&1))
2568 emit_movimm(imm[i],t);
2573 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2575 signed char sh,sl,th,tl;
2576 th=get_reg(i_regs->regmap,rt1[i]|64);
2577 tl=get_reg(i_regs->regmap,rt1[i]);
2578 sh=get_reg(i_regs->regmap,rs1[i]|64);
2579 sl=get_reg(i_regs->regmap,rs1[i]);
2585 emit_addimm64_32(sh,sl,imm[i],th,tl);
2588 emit_addimm(sl,imm[i],tl);
2591 emit_movimm(imm[i],tl);
2592 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2597 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2599 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2600 signed char sh,sl,t;
2601 t=get_reg(i_regs->regmap,rt1[i]);
2602 sh=get_reg(i_regs->regmap,rs1[i]|64);
2603 sl=get_reg(i_regs->regmap,rs1[i]);
2607 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2608 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2609 if(opcode[i]==0x0a) { // SLTI
2611 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2612 emit_slti32(t,imm[i],t);
2614 emit_slti32(sl,imm[i],t);
2619 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2620 emit_sltiu32(t,imm[i],t);
2622 emit_sltiu32(sl,imm[i],t);
2627 if(opcode[i]==0x0a) // SLTI
2628 emit_slti64_32(sh,sl,imm[i],t);
2630 emit_sltiu64_32(sh,sl,imm[i],t);
2633 // SLTI(U) with r0 is just stupid,
2634 // nonetheless examples can be found
2635 if(opcode[i]==0x0a) // SLTI
2636 if(0<imm[i]) emit_movimm(1,t);
2637 else emit_zeroreg(t);
2640 if(imm[i]) emit_movimm(1,t);
2641 else emit_zeroreg(t);
2647 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2649 signed char sh,sl,th,tl;
2650 th=get_reg(i_regs->regmap,rt1[i]|64);
2651 tl=get_reg(i_regs->regmap,rt1[i]);
2652 sh=get_reg(i_regs->regmap,rs1[i]|64);
2653 sl=get_reg(i_regs->regmap,rs1[i]);
2654 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2655 if(opcode[i]==0x0c) //ANDI
2659 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2660 emit_andimm(tl,imm[i],tl);
2662 if(!((i_regs->wasconst>>sl)&1))
2663 emit_andimm(sl,imm[i],tl);
2665 emit_movimm(constmap[i][sl]&imm[i],tl);
2670 if(th>=0) emit_zeroreg(th);
2676 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2680 emit_loadreg(rs1[i]|64,th);
2685 if(opcode[i]==0x0d) //ORI
2687 emit_orimm(tl,imm[i],tl);
2689 if(!((i_regs->wasconst>>sl)&1))
2690 emit_orimm(sl,imm[i],tl);
2692 emit_movimm(constmap[i][sl]|imm[i],tl);
2694 if(opcode[i]==0x0e) //XORI
2696 emit_xorimm(tl,imm[i],tl);
2698 if(!((i_regs->wasconst>>sl)&1))
2699 emit_xorimm(sl,imm[i],tl);
2701 emit_movimm(constmap[i][sl]^imm[i],tl);
2705 emit_movimm(imm[i],tl);
2706 if(th>=0) emit_zeroreg(th);
2714 void shiftimm_assemble(int i,struct regstat *i_regs)
2716 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2720 t=get_reg(i_regs->regmap,rt1[i]);
2721 s=get_reg(i_regs->regmap,rs1[i]);
2723 if(t>=0&&!((i_regs->isconst>>t)&1)){
2730 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2732 if(opcode2[i]==0) // SLL
2734 emit_shlimm(s<0?t:s,imm[i],t);
2736 if(opcode2[i]==2) // SRL
2738 emit_shrimm(s<0?t:s,imm[i],t);
2740 if(opcode2[i]==3) // SRA
2742 emit_sarimm(s<0?t:s,imm[i],t);
2746 if(s>=0 && s!=t) emit_mov(s,t);
2750 //emit_storereg(rt1[i],t); //DEBUG
2753 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2756 signed char sh,sl,th,tl;
2757 th=get_reg(i_regs->regmap,rt1[i]|64);
2758 tl=get_reg(i_regs->regmap,rt1[i]);
2759 sh=get_reg(i_regs->regmap,rs1[i]|64);
2760 sl=get_reg(i_regs->regmap,rs1[i]);
2765 if(th>=0) emit_zeroreg(th);
2772 if(opcode2[i]==0x38) // DSLL
2774 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2775 emit_shlimm(sl,imm[i],tl);
2777 if(opcode2[i]==0x3a) // DSRL
2779 emit_shrdimm(sl,sh,imm[i],tl);
2780 if(th>=0) emit_shrimm(sh,imm[i],th);
2782 if(opcode2[i]==0x3b) // DSRA
2784 emit_shrdimm(sl,sh,imm[i],tl);
2785 if(th>=0) emit_sarimm(sh,imm[i],th);
2789 if(sl!=tl) emit_mov(sl,tl);
2790 if(th>=0&&sh!=th) emit_mov(sh,th);
2796 if(opcode2[i]==0x3c) // DSLL32
2799 signed char sl,tl,th;
2800 tl=get_reg(i_regs->regmap,rt1[i]);
2801 th=get_reg(i_regs->regmap,rt1[i]|64);
2802 sl=get_reg(i_regs->regmap,rs1[i]);
2811 emit_shlimm(th,imm[i]&31,th);
2816 if(opcode2[i]==0x3e) // DSRL32
2819 signed char sh,tl,th;
2820 tl=get_reg(i_regs->regmap,rt1[i]);
2821 th=get_reg(i_regs->regmap,rt1[i]|64);
2822 sh=get_reg(i_regs->regmap,rs1[i]|64);
2826 if(th>=0) emit_zeroreg(th);
2829 emit_shrimm(tl,imm[i]&31,tl);
2834 if(opcode2[i]==0x3f) // DSRA32
2838 tl=get_reg(i_regs->regmap,rt1[i]);
2839 sh=get_reg(i_regs->regmap,rs1[i]|64);
2845 emit_sarimm(tl,imm[i]&31,tl);
2852 #ifndef shift_assemble
2853 void shift_assemble(int i,struct regstat *i_regs)
2855 printf("Need shift_assemble for this architecture.\n");
2860 void load_assemble(int i,struct regstat *i_regs)
2862 int s,th,tl,addr,map=-1;
2865 int memtarget=0,c=0;
2866 int fastload_reg_override=0;
2868 th=get_reg(i_regs->regmap,rt1[i]|64);
2869 tl=get_reg(i_regs->regmap,rt1[i]);
2870 s=get_reg(i_regs->regmap,rs1[i]);
2872 for(hr=0;hr<HOST_REGS;hr++) {
2873 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2875 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2877 c=(i_regs->wasconst>>s)&1;
2879 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2880 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2883 //printf("load_assemble: c=%d\n",c);
2884 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2885 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2887 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2889 // could be FIFO, must perform the read
2891 assem_debug("(forced read)\n");
2892 tl=get_reg(i_regs->regmap,-1);
2896 if(offset||s<0||c) addr=tl;
2898 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2900 //printf("load_assemble: c=%d\n",c);
2901 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2902 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2904 if(th>=0) reglist&=~(1<<th);
2908 map=get_reg(i_regs->regmap,ROREG);
2909 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2911 //#define R29_HACK 1
2913 // Strmnnrmn's speed hack
2914 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2917 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2922 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2923 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2924 map=get_reg(i_regs->regmap,TLREG);
2927 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2928 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2930 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2931 if (opcode[i]==0x20) { // LB
2934 #ifdef HOST_IMM_ADDR32
2936 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2940 //emit_xorimm(addr,3,tl);
2941 //gen_tlb_addr_r(tl,map);
2942 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2944 #ifdef BIG_ENDIAN_MIPS
2945 if(!c) emit_xorimm(addr,3,tl);
2946 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2950 if(fastload_reg_override) a=fastload_reg_override;
2952 emit_movsbl_indexed_tlb(x,a,map,tl);
2956 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2959 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2961 if (opcode[i]==0x21) { // LH
2964 #ifdef HOST_IMM_ADDR32
2966 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2971 #ifdef BIG_ENDIAN_MIPS
2972 if(!c) emit_xorimm(addr,2,tl);
2973 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2977 if(fastload_reg_override) a=fastload_reg_override;
2979 //emit_movswl_indexed_tlb(x,tl,map,tl);
2982 gen_tlb_addr_r(a,map);
2983 emit_movswl_indexed(x,a,tl);
2986 emit_movswl_indexed(x,a,tl);
2988 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2994 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2997 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2999 if (opcode[i]==0x23) { // LW
3003 if(fastload_reg_override) a=fastload_reg_override;
3004 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3005 #ifdef HOST_IMM_ADDR32
3007 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3010 emit_readword_indexed_tlb(0,a,map,tl);
3013 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3016 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3018 if (opcode[i]==0x24) { // LBU
3021 #ifdef HOST_IMM_ADDR32
3023 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3027 //emit_xorimm(addr,3,tl);
3028 //gen_tlb_addr_r(tl,map);
3029 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3031 #ifdef BIG_ENDIAN_MIPS
3032 if(!c) emit_xorimm(addr,3,tl);
3033 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3037 if(fastload_reg_override) a=fastload_reg_override;
3039 emit_movzbl_indexed_tlb(x,a,map,tl);
3043 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3046 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3048 if (opcode[i]==0x25) { // LHU
3051 #ifdef HOST_IMM_ADDR32
3053 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3058 #ifdef BIG_ENDIAN_MIPS
3059 if(!c) emit_xorimm(addr,2,tl);
3060 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3064 if(fastload_reg_override) a=fastload_reg_override;
3066 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3069 gen_tlb_addr_r(a,map);
3070 emit_movzwl_indexed(x,a,tl);
3073 emit_movzwl_indexed(x,a,tl);
3075 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3081 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3084 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3086 if (opcode[i]==0x27) { // LWU
3091 if(fastload_reg_override) a=fastload_reg_override;
3092 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3093 #ifdef HOST_IMM_ADDR32
3095 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3098 emit_readword_indexed_tlb(0,a,map,tl);
3101 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3104 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3108 if (opcode[i]==0x37) { // LD
3112 if(fastload_reg_override) a=fastload_reg_override;
3113 //gen_tlb_addr_r(tl,map);
3114 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3115 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3116 #ifdef HOST_IMM_ADDR32
3118 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3121 emit_readdword_indexed_tlb(0,a,map,th,tl);
3124 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3127 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3130 //emit_storereg(rt1[i],tl); // DEBUG
3131 //if(opcode[i]==0x23)
3132 //if(opcode[i]==0x24)
3133 //if(opcode[i]==0x23||opcode[i]==0x24)
3134 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3138 emit_readword((int)&last_count,ECX);
3140 if(get_reg(i_regs->regmap,CCREG)<0)
3141 emit_loadreg(CCREG,HOST_CCREG);
3142 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3143 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3144 emit_writeword(HOST_CCREG,(int)&Count);
3147 if(get_reg(i_regs->regmap,CCREG)<0)
3148 emit_loadreg(CCREG,0);
3150 emit_mov(HOST_CCREG,0);
3152 emit_addimm(0,2*ccadj[i],0);
3153 emit_writeword(0,(int)&Count);
3155 emit_call((int)memdebug);
3157 restore_regs(0x100f);
3161 #ifndef loadlr_assemble
3162 void loadlr_assemble(int i,struct regstat *i_regs)
3164 printf("Need loadlr_assemble for this architecture.\n");
3169 void store_assemble(int i,struct regstat *i_regs)
3174 int jaddr=0,jaddr2,type;
3175 int memtarget=0,c=0;
3176 int agr=AGEN1+(i&1);
3177 int faststore_reg_override=0;
3179 th=get_reg(i_regs->regmap,rs2[i]|64);
3180 tl=get_reg(i_regs->regmap,rs2[i]);
3181 s=get_reg(i_regs->regmap,rs1[i]);
3182 temp=get_reg(i_regs->regmap,agr);
3183 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3186 c=(i_regs->wasconst>>s)&1;
3188 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3189 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3194 for(hr=0;hr<HOST_REGS;hr++) {
3195 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3197 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3198 if(offset||s<0||c) addr=temp;
3204 // Strmnnrmn's speed hack
3205 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3207 emit_cmpimm(addr,RAM_SIZE);
3208 #ifdef DESTRUCTIVE_SHIFT
3209 if(s==addr) emit_mov(s,temp);
3213 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3217 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3218 // Hint to branch predictor that the branch is unlikely to be taken
3220 emit_jno_unlikely(0);
3226 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3231 if (opcode[i]==0x28) x=3; // SB
3232 if (opcode[i]==0x29) x=2; // SH
3233 map=get_reg(i_regs->regmap,TLREG);
3236 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3237 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3240 if (opcode[i]==0x28) { // SB
3243 #ifdef BIG_ENDIAN_MIPS
3244 if(!c) emit_xorimm(addr,3,temp);
3245 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3249 if(faststore_reg_override) a=faststore_reg_override;
3250 //gen_tlb_addr_w(temp,map);
3251 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3252 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3256 if (opcode[i]==0x29) { // SH
3259 #ifdef BIG_ENDIAN_MIPS
3260 if(!c) emit_xorimm(addr,2,temp);
3261 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3265 if(faststore_reg_override) a=faststore_reg_override;
3267 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3270 gen_tlb_addr_w(a,map);
3271 emit_writehword_indexed(tl,x,a);
3273 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3277 if (opcode[i]==0x2B) { // SW
3280 if(faststore_reg_override) a=faststore_reg_override;
3281 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3282 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3286 if (opcode[i]==0x3F) { // SD
3289 if(faststore_reg_override) a=faststore_reg_override;
3292 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3293 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3294 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3297 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3298 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3299 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3306 // PCSX store handlers don't check invcode again
3308 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3312 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3314 #ifdef DESTRUCTIVE_SHIFT
3315 // The x86 shift operation is 'destructive'; it overwrites the
3316 // source register, so we need to make a copy first and use that.
3319 #if defined(HOST_IMM8)
3320 int ir=get_reg(i_regs->regmap,INVCP);
3322 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3324 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3326 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3327 emit_callne(invalidate_addr_reg[addr]);
3331 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3335 u_int addr_val=constmap[i][s]+offset;
3337 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3338 } else if(c&&!memtarget) {
3339 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
3341 // basic current block modification detection..
3342 // not looking back as that should be in mips cache already
3343 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
3344 printf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
3345 assert(i_regs->regmap==regs[i].regmap); // not delay slot
3346 if(i_regs->regmap==regs[i].regmap) {
3347 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
3348 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
3349 emit_movimm(start+i*4+4,0);
3350 emit_writeword(0,(int)&pcaddr);
3351 emit_jmp((int)do_interrupt);
3354 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3355 //if(opcode[i]==0x2B || opcode[i]==0x28)
3356 //if(opcode[i]==0x2B || opcode[i]==0x29)
3357 //if(opcode[i]==0x2B)
3358 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3366 emit_readword((int)&last_count,ECX);
3368 if(get_reg(i_regs->regmap,CCREG)<0)
3369 emit_loadreg(CCREG,HOST_CCREG);
3370 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3371 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3372 emit_writeword(HOST_CCREG,(int)&Count);
3375 if(get_reg(i_regs->regmap,CCREG)<0)
3376 emit_loadreg(CCREG,0);
3378 emit_mov(HOST_CCREG,0);
3380 emit_addimm(0,2*ccadj[i],0);
3381 emit_writeword(0,(int)&Count);
3383 emit_call((int)memdebug);
3388 restore_regs(0x100f);
3393 void storelr_assemble(int i,struct regstat *i_regs)
3400 int case1,case2,case3;
3401 int done0,done1,done2;
3402 int memtarget=0,c=0;
3403 int agr=AGEN1+(i&1);
3405 th=get_reg(i_regs->regmap,rs2[i]|64);
3406 tl=get_reg(i_regs->regmap,rs2[i]);
3407 s=get_reg(i_regs->regmap,rs1[i]);
3408 temp=get_reg(i_regs->regmap,agr);
3409 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3412 c=(i_regs->isconst>>s)&1;
3414 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3415 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3419 for(hr=0;hr<HOST_REGS;hr++) {
3420 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3425 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3426 if(!offset&&s!=temp) emit_mov(s,temp);
3432 if(!memtarget||!rs1[i]) {
3438 int map=get_reg(i_regs->regmap,ROREG);
3439 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3440 gen_tlb_addr_w(temp,map);
3442 if((u_int)rdram!=0x80000000)
3443 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3446 int map=get_reg(i_regs->regmap,TLREG);
3449 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3450 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3451 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3452 if(!jaddr&&!memtarget) {
3456 gen_tlb_addr_w(temp,map);
3459 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3460 temp2=get_reg(i_regs->regmap,FTEMP);
3461 if(!rs2[i]) temp2=th=tl;
3464 #ifndef BIG_ENDIAN_MIPS
3465 emit_xorimm(temp,3,temp);
3467 emit_testimm(temp,2);
3470 emit_testimm(temp,1);
3474 if (opcode[i]==0x2A) { // SWL
3475 emit_writeword_indexed(tl,0,temp);
3477 if (opcode[i]==0x2E) { // SWR
3478 emit_writebyte_indexed(tl,3,temp);
3480 if (opcode[i]==0x2C) { // SDL
3481 emit_writeword_indexed(th,0,temp);
3482 if(rs2[i]) emit_mov(tl,temp2);
3484 if (opcode[i]==0x2D) { // SDR
3485 emit_writebyte_indexed(tl,3,temp);
3486 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3491 set_jump_target(case1,(int)out);
3492 if (opcode[i]==0x2A) { // SWL
3493 // Write 3 msb into three least significant bytes
3494 if(rs2[i]) emit_rorimm(tl,8,tl);
3495 emit_writehword_indexed(tl,-1,temp);
3496 if(rs2[i]) emit_rorimm(tl,16,tl);
3497 emit_writebyte_indexed(tl,1,temp);
3498 if(rs2[i]) emit_rorimm(tl,8,tl);
3500 if (opcode[i]==0x2E) { // SWR
3501 // Write two lsb into two most significant bytes
3502 emit_writehword_indexed(tl,1,temp);
3504 if (opcode[i]==0x2C) { // SDL
3505 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3506 // Write 3 msb into three least significant bytes
3507 if(rs2[i]) emit_rorimm(th,8,th);
3508 emit_writehword_indexed(th,-1,temp);
3509 if(rs2[i]) emit_rorimm(th,16,th);
3510 emit_writebyte_indexed(th,1,temp);
3511 if(rs2[i]) emit_rorimm(th,8,th);
3513 if (opcode[i]==0x2D) { // SDR
3514 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3515 // Write two lsb into two most significant bytes
3516 emit_writehword_indexed(tl,1,temp);
3521 set_jump_target(case2,(int)out);
3522 emit_testimm(temp,1);
3525 if (opcode[i]==0x2A) { // SWL
3526 // Write two msb into two least significant bytes
3527 if(rs2[i]) emit_rorimm(tl,16,tl);
3528 emit_writehword_indexed(tl,-2,temp);
3529 if(rs2[i]) emit_rorimm(tl,16,tl);
3531 if (opcode[i]==0x2E) { // SWR
3532 // Write 3 lsb into three most significant bytes
3533 emit_writebyte_indexed(tl,-1,temp);
3534 if(rs2[i]) emit_rorimm(tl,8,tl);
3535 emit_writehword_indexed(tl,0,temp);
3536 if(rs2[i]) emit_rorimm(tl,24,tl);
3538 if (opcode[i]==0x2C) { // SDL
3539 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3540 // Write two msb into two least significant bytes
3541 if(rs2[i]) emit_rorimm(th,16,th);
3542 emit_writehword_indexed(th,-2,temp);
3543 if(rs2[i]) emit_rorimm(th,16,th);
3545 if (opcode[i]==0x2D) { // SDR
3546 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3547 // Write 3 lsb into three most significant bytes
3548 emit_writebyte_indexed(tl,-1,temp);
3549 if(rs2[i]) emit_rorimm(tl,8,tl);
3550 emit_writehword_indexed(tl,0,temp);
3551 if(rs2[i]) emit_rorimm(tl,24,tl);
3556 set_jump_target(case3,(int)out);
3557 if (opcode[i]==0x2A) { // SWL
3558 // Write msb into least significant byte
3559 if(rs2[i]) emit_rorimm(tl,24,tl);
3560 emit_writebyte_indexed(tl,-3,temp);
3561 if(rs2[i]) emit_rorimm(tl,8,tl);
3563 if (opcode[i]==0x2E) { // SWR
3564 // Write entire word
3565 emit_writeword_indexed(tl,-3,temp);
3567 if (opcode[i]==0x2C) { // SDL
3568 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3569 // Write msb into least significant byte
3570 if(rs2[i]) emit_rorimm(th,24,th);
3571 emit_writebyte_indexed(th,-3,temp);
3572 if(rs2[i]) emit_rorimm(th,8,th);
3574 if (opcode[i]==0x2D) { // SDR
3575 if(rs2[i]) emit_mov(th,temp2);
3576 // Write entire word
3577 emit_writeword_indexed(tl,-3,temp);
3579 set_jump_target(done0,(int)out);
3580 set_jump_target(done1,(int)out);
3581 set_jump_target(done2,(int)out);
3582 if (opcode[i]==0x2C) { // SDL
3583 emit_testimm(temp,4);
3586 emit_andimm(temp,~3,temp);
3587 emit_writeword_indexed(temp2,4,temp);
3588 set_jump_target(done0,(int)out);
3590 if (opcode[i]==0x2D) { // SDR
3591 emit_testimm(temp,4);
3594 emit_andimm(temp,~3,temp);
3595 emit_writeword_indexed(temp2,-4,temp);
3596 set_jump_target(done0,(int)out);
3599 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3600 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3602 int map=get_reg(i_regs->regmap,ROREG);
3603 if(map<0) map=HOST_TEMPREG;
3604 gen_orig_addr_w(temp,map);
3606 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3608 #if defined(HOST_IMM8)
3609 int ir=get_reg(i_regs->regmap,INVCP);
3611 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3613 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3615 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3616 emit_callne(invalidate_addr_reg[temp]);
3620 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3625 //save_regs(0x100f);
3626 emit_readword((int)&last_count,ECX);
3627 if(get_reg(i_regs->regmap,CCREG)<0)
3628 emit_loadreg(CCREG,HOST_CCREG);
3629 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3630 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3631 emit_writeword(HOST_CCREG,(int)&Count);
3632 emit_call((int)memdebug);
3634 //restore_regs(0x100f);
3638 void c1ls_assemble(int i,struct regstat *i_regs)
3640 #ifndef DISABLE_COP1
3646 int jaddr,jaddr2=0,jaddr3,type;
3647 int agr=AGEN1+(i&1);
3649 th=get_reg(i_regs->regmap,FTEMP|64);
3650 tl=get_reg(i_regs->regmap,FTEMP);
3651 s=get_reg(i_regs->regmap,rs1[i]);
3652 temp=get_reg(i_regs->regmap,agr);
3653 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3658 for(hr=0;hr<HOST_REGS;hr++) {
3659 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3661 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3662 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3664 // Loads use a temporary register which we need to save
3667 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3671 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3672 //else c=(i_regs->wasconst>>s)&1;
3673 if(s>=0) c=(i_regs->wasconst>>s)&1;
3674 // Check cop1 unusable
3676 signed char rs=get_reg(i_regs->regmap,CSREG);
3678 emit_testimm(rs,0x20000000);
3681 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3684 if (opcode[i]==0x39) { // SWC1 (get float address)
3685 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3687 if (opcode[i]==0x3D) { // SDC1 (get double address)
3688 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3690 // Generate address + offset
3693 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3697 map=get_reg(i_regs->regmap,TLREG);
3700 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3701 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3703 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3704 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3707 if (opcode[i]==0x39) { // SWC1 (read float)
3708 emit_readword_indexed(0,tl,tl);
3710 if (opcode[i]==0x3D) { // SDC1 (read double)
3711 emit_readword_indexed(4,tl,th);
3712 emit_readword_indexed(0,tl,tl);
3714 if (opcode[i]==0x31) { // LWC1 (get target address)
3715 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3717 if (opcode[i]==0x35) { // LDC1 (get target address)
3718 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3725 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3727 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3729 #ifdef DESTRUCTIVE_SHIFT
3730 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3731 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3735 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3736 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3738 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3739 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3742 if (opcode[i]==0x31) { // LWC1
3743 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3744 //gen_tlb_addr_r(ar,map);
3745 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3746 #ifdef HOST_IMM_ADDR32
3747 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3750 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3753 if (opcode[i]==0x35) { // LDC1
3755 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3756 //gen_tlb_addr_r(ar,map);
3757 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3758 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3759 #ifdef HOST_IMM_ADDR32
3760 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3763 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3766 if (opcode[i]==0x39) { // SWC1
3767 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3768 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3771 if (opcode[i]==0x3D) { // SDC1
3773 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3774 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3775 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3778 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3779 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3780 #ifndef DESTRUCTIVE_SHIFT
3781 temp=offset||c||s<0?ar:s;
3783 #if defined(HOST_IMM8)
3784 int ir=get_reg(i_regs->regmap,INVCP);
3786 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3788 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3790 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3791 emit_callne(invalidate_addr_reg[temp]);
3795 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3799 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3800 if (opcode[i]==0x31) { // LWC1 (write float)
3801 emit_writeword_indexed(tl,0,temp);
3803 if (opcode[i]==0x35) { // LDC1 (write double)
3804 emit_writeword_indexed(th,4,temp);
3805 emit_writeword_indexed(tl,0,temp);
3807 //if(opcode[i]==0x39)
3808 /*if(opcode[i]==0x39||opcode[i]==0x31)
3811 emit_readword((int)&last_count,ECX);
3812 if(get_reg(i_regs->regmap,CCREG)<0)
3813 emit_loadreg(CCREG,HOST_CCREG);
3814 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3815 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3816 emit_writeword(HOST_CCREG,(int)&Count);
3817 emit_call((int)memdebug);
3821 cop1_unusable(i, i_regs);
3825 void c2ls_assemble(int i,struct regstat *i_regs)
3830 int memtarget=0,c=0;
3831 int jaddr2=0,jaddr3,type;
3832 int agr=AGEN1+(i&1);
3833 int fastio_reg_override=0;
3835 u_int copr=(source[i]>>16)&0x1f;
3836 s=get_reg(i_regs->regmap,rs1[i]);
3837 tl=get_reg(i_regs->regmap,FTEMP);
3843 for(hr=0;hr<HOST_REGS;hr++) {
3844 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3846 if(i_regs->regmap[HOST_CCREG]==CCREG)
3847 reglist&=~(1<<HOST_CCREG);
3850 if (opcode[i]==0x3a) { // SWC2
3851 ar=get_reg(i_regs->regmap,agr);
3852 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3857 if(s>=0) c=(i_regs->wasconst>>s)&1;
3858 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3859 if (!offset&&!c&&s>=0) ar=s;
3862 if (opcode[i]==0x3a) { // SWC2
3863 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3871 emit_jmp(0); // inline_readstub/inline_writestub?
3875 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3877 if (opcode[i]==0x32) { // LWC2
3878 #ifdef HOST_IMM_ADDR32
3879 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3883 if(fastio_reg_override) a=fastio_reg_override;
3884 emit_readword_indexed(0,a,tl);
3886 if (opcode[i]==0x3a) { // SWC2
3887 #ifdef DESTRUCTIVE_SHIFT
3888 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3891 if(fastio_reg_override) a=fastio_reg_override;
3892 emit_writeword_indexed(tl,0,a);
3896 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3897 if(opcode[i]==0x3a) // SWC2
3898 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3899 #if defined(HOST_IMM8)
3900 int ir=get_reg(i_regs->regmap,INVCP);
3902 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3904 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3906 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3907 emit_callne(invalidate_addr_reg[ar]);
3911 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3914 if (opcode[i]==0x32) { // LWC2
3915 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3919 #ifndef multdiv_assemble
3920 void multdiv_assemble(int i,struct regstat *i_regs)
3922 printf("Need multdiv_assemble for this architecture.\n");
3927 void mov_assemble(int i,struct regstat *i_regs)
3929 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3930 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3932 signed char sh,sl,th,tl;
3933 th=get_reg(i_regs->regmap,rt1[i]|64);
3934 tl=get_reg(i_regs->regmap,rt1[i]);
3937 sh=get_reg(i_regs->regmap,rs1[i]|64);
3938 sl=get_reg(i_regs->regmap,rs1[i]);
3939 if(sl>=0) emit_mov(sl,tl);
3940 else emit_loadreg(rs1[i],tl);
3942 if(sh>=0) emit_mov(sh,th);
3943 else emit_loadreg(rs1[i]|64,th);
3949 #ifndef fconv_assemble
3950 void fconv_assemble(int i,struct regstat *i_regs)
3952 printf("Need fconv_assemble for this architecture.\n");
3958 void float_assemble(int i,struct regstat *i_regs)
3960 printf("Need float_assemble for this architecture.\n");
3965 void syscall_assemble(int i,struct regstat *i_regs)
3967 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3968 assert(ccreg==HOST_CCREG);
3969 assert(!is_delayslot);
3970 emit_movimm(start+i*4,EAX); // Get PC
3971 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3972 emit_jmp((int)jump_syscall_hle); // XXX
3975 void hlecall_assemble(int i,struct regstat *i_regs)
3977 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3978 assert(ccreg==HOST_CCREG);
3979 assert(!is_delayslot);
3980 emit_movimm(start+i*4+4,0); // Get PC
3981 emit_movimm((int)psxHLEt[source[i]&7],1);
3982 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3983 emit_jmp((int)jump_hlecall);
3986 void intcall_assemble(int i,struct regstat *i_regs)
3988 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3989 assert(ccreg==HOST_CCREG);
3990 assert(!is_delayslot);
3991 emit_movimm(start+i*4,0); // Get PC
3992 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3993 emit_jmp((int)jump_intcall);
3996 void ds_assemble(int i,struct regstat *i_regs)
3998 speculate_register_values(i);
4002 alu_assemble(i,i_regs);break;
4004 imm16_assemble(i,i_regs);break;
4006 shift_assemble(i,i_regs);break;
4008 shiftimm_assemble(i,i_regs);break;
4010 load_assemble(i,i_regs);break;
4012 loadlr_assemble(i,i_regs);break;
4014 store_assemble(i,i_regs);break;
4016 storelr_assemble(i,i_regs);break;
4018 cop0_assemble(i,i_regs);break;
4020 cop1_assemble(i,i_regs);break;
4022 c1ls_assemble(i,i_regs);break;
4024 cop2_assemble(i,i_regs);break;
4026 c2ls_assemble(i,i_regs);break;
4028 c2op_assemble(i,i_regs);break;
4030 fconv_assemble(i,i_regs);break;
4032 float_assemble(i,i_regs);break;
4034 fcomp_assemble(i,i_regs);break;
4036 multdiv_assemble(i,i_regs);break;
4038 mov_assemble(i,i_regs);break;
4048 printf("Jump in the delay slot. This is probably a bug.\n");
4053 // Is the branch target a valid internal jump?
4054 int internal_branch(uint64_t i_is32,int addr)
4056 if(addr&1) return 0; // Indirect (register) jump
4057 if(addr>=start && addr<start+slen*4-4)
4059 int t=(addr-start)>>2;
4060 // Delay slots are not valid branch targets
4061 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4062 // 64 -> 32 bit transition requires a recompile
4063 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4065 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4066 else printf("optimizable: yes\n");
4068 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4070 if(requires_32bit[t]&~i_is32) return 0;
4078 #ifndef wb_invalidate
4079 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4080 uint64_t u,uint64_t uu)
4083 for(hr=0;hr<HOST_REGS;hr++) {
4084 if(hr!=EXCLUDE_REG) {
4085 if(pre[hr]!=entry[hr]) {
4088 if(get_reg(entry,pre[hr])<0) {
4090 if(!((u>>pre[hr])&1)) {
4091 emit_storereg(pre[hr],hr);
4092 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4093 emit_sarimm(hr,31,hr);
4094 emit_storereg(pre[hr]|64,hr);
4098 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4099 emit_storereg(pre[hr],hr);
4108 // Move from one register to another (no writeback)
4109 for(hr=0;hr<HOST_REGS;hr++) {
4110 if(hr!=EXCLUDE_REG) {
4111 if(pre[hr]!=entry[hr]) {
4112 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4114 if((nr=get_reg(entry,pre[hr]))>=0) {
4124 // Load the specified registers
4125 // This only loads the registers given as arguments because
4126 // we don't want to load things that will be overwritten
4127 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4131 for(hr=0;hr<HOST_REGS;hr++) {
4132 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4133 if(entry[hr]!=regmap[hr]) {
4134 if(regmap[hr]==rs1||regmap[hr]==rs2)
4141 emit_loadreg(regmap[hr],hr);
4148 for(hr=0;hr<HOST_REGS;hr++) {
4149 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4150 if(entry[hr]!=regmap[hr]) {
4151 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4153 assert(regmap[hr]!=64);
4154 if((is32>>(regmap[hr]&63))&1) {
4155 int lr=get_reg(regmap,regmap[hr]-64);
4157 emit_sarimm(lr,31,hr);
4159 emit_loadreg(regmap[hr],hr);
4163 emit_loadreg(regmap[hr],hr);
4171 // Load registers prior to the start of a loop
4172 // so that they are not loaded within the loop
4173 static void loop_preload(signed char pre[],signed char entry[])
4176 for(hr=0;hr<HOST_REGS;hr++) {
4177 if(hr!=EXCLUDE_REG) {
4178 if(pre[hr]!=entry[hr]) {
4180 if(get_reg(pre,entry[hr])<0) {
4181 assem_debug("loop preload:\n");
4182 //printf("loop preload: %d\n",hr);
4186 else if(entry[hr]<TEMPREG)
4188 emit_loadreg(entry[hr],hr);
4190 else if(entry[hr]-64<TEMPREG)
4192 emit_loadreg(entry[hr],hr);
4201 // Generate address for load/store instruction
4202 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4203 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4205 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4207 int agr=AGEN1+(i&1);
4208 int mgr=MGEN1+(i&1);
4209 if(itype[i]==LOAD) {
4210 ra=get_reg(i_regs->regmap,rt1[i]);
4211 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4214 if(itype[i]==LOADLR) {
4215 ra=get_reg(i_regs->regmap,FTEMP);
4217 if(itype[i]==STORE||itype[i]==STORELR) {
4218 ra=get_reg(i_regs->regmap,agr);
4219 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4221 if(itype[i]==C1LS||itype[i]==C2LS) {
4222 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4223 ra=get_reg(i_regs->regmap,FTEMP);
4224 else { // SWC1/SDC1/SWC2/SDC2
4225 ra=get_reg(i_regs->regmap,agr);
4226 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4229 int rs=get_reg(i_regs->regmap,rs1[i]);
4230 int rm=get_reg(i_regs->regmap,TLREG);
4233 int c=(i_regs->wasconst>>rs)&1;
4235 // Using r0 as a base address
4237 if(!entry||entry[rm]!=mgr) {
4238 generate_map_const(offset,rm);
4239 } // else did it in the previous cycle
4241 if(!entry||entry[ra]!=agr) {
4242 if (opcode[i]==0x22||opcode[i]==0x26) {
4243 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4244 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4245 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4247 emit_movimm(offset,ra);
4249 } // else did it in the previous cycle
4252 if(!entry||entry[ra]!=rs1[i])
4253 emit_loadreg(rs1[i],ra);
4254 //if(!entry||entry[ra]!=rs1[i])
4255 // printf("poor load scheduling!\n");
4260 if(!entry||entry[rm]!=mgr) {
4261 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4262 // Stores to memory go thru the mapper to detect self-modifying
4263 // code, loads don't.
4264 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4265 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4266 generate_map_const(constmap[i][rs]+offset,rm);
4268 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4269 generate_map_const(constmap[i][rs]+offset,rm);
4274 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4275 if(!entry||entry[ra]!=agr) {
4276 if (opcode[i]==0x22||opcode[i]==0x26) {
4277 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4278 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4279 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4281 #ifdef HOST_IMM_ADDR32
4282 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4283 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4285 emit_movimm(constmap[i][rs]+offset,ra);
4286 regs[i].loadedconst|=1<<ra;
4288 } // else did it in the previous cycle
4289 } // else load_consts already did it
4291 if(offset&&!c&&rs1[i]) {
4293 emit_addimm(rs,offset,ra);
4295 emit_addimm(ra,offset,ra);
4300 // Preload constants for next instruction
4301 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4303 #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4305 agr=MGEN1+((i+1)&1);
4306 ra=get_reg(i_regs->regmap,agr);
4308 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4309 int offset=imm[i+1];
4310 int c=(regs[i+1].wasconst>>rs)&1;
4312 if(itype[i+1]==STORE||itype[i+1]==STORELR
4313 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4314 // Stores to memory go thru the mapper to detect self-modifying
4315 // code, loads don't.
4316 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4317 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4318 generate_map_const(constmap[i+1][rs]+offset,ra);
4320 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4321 generate_map_const(constmap[i+1][rs]+offset,ra);
4324 /*else if(rs1[i]==0) {
4325 generate_map_const(offset,ra);
4330 agr=AGEN1+((i+1)&1);
4331 ra=get_reg(i_regs->regmap,agr);
4333 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4334 int offset=imm[i+1];
4335 int c=(regs[i+1].wasconst>>rs)&1;
4336 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4337 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4338 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4339 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4340 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4342 #ifdef HOST_IMM_ADDR32
4343 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4344 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4346 emit_movimm(constmap[i+1][rs]+offset,ra);
4347 regs[i+1].loadedconst|=1<<ra;
4350 else if(rs1[i+1]==0) {
4351 // Using r0 as a base address
4352 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4353 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4354 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4355 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4357 emit_movimm(offset,ra);
4364 int get_final_value(int hr, int i, int *value)
4366 int reg=regs[i].regmap[hr];
4368 if(regs[i+1].regmap[hr]!=reg) break;
4369 if(!((regs[i+1].isconst>>hr)&1)) break;
4374 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4375 *value=constmap[i][hr];
4379 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4380 // Load in delay slot, out-of-order execution
4381 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4383 #ifdef HOST_IMM_ADDR32
4384 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4386 // Precompute load address
4387 *value=constmap[i][hr]+imm[i+2];
4391 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4393 #ifdef HOST_IMM_ADDR32
4394 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4396 // Precompute load address
4397 *value=constmap[i][hr]+imm[i+1];
4398 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4403 *value=constmap[i][hr];
4404 //printf("c=%x\n",(int)constmap[i][hr]);
4405 if(i==slen-1) return 1;
4407 return !((unneeded_reg[i+1]>>reg)&1);
4409 return !((unneeded_reg_upper[i+1]>>reg)&1);
4413 // Load registers with known constants
4414 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4417 // propagate loaded constant flags
4419 regs[i].loadedconst=0;
4421 for(hr=0;hr<HOST_REGS;hr++) {
4422 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4423 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4425 regs[i].loadedconst|=1<<hr;
4430 for(hr=0;hr<HOST_REGS;hr++) {
4431 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4432 //if(entry[hr]!=regmap[hr]) {
4433 if(!((regs[i].loadedconst>>hr)&1)) {
4434 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4435 int value,similar=0;
4436 if(get_final_value(hr,i,&value)) {
4437 // see if some other register has similar value
4438 for(hr2=0;hr2<HOST_REGS;hr2++) {
4439 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4440 if(is_similar_value(value,constmap[i][hr2])) {
4448 if(get_final_value(hr2,i,&value2)) // is this needed?
4449 emit_movimm_from(value2,hr2,value,hr);
4451 emit_movimm(value,hr);
4457 emit_movimm(value,hr);
4460 regs[i].loadedconst|=1<<hr;
4466 for(hr=0;hr<HOST_REGS;hr++) {
4467 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4468 //if(entry[hr]!=regmap[hr]) {
4469 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4470 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4471 if((is32>>(regmap[hr]&63))&1) {
4472 int lr=get_reg(regmap,regmap[hr]-64);
4474 emit_sarimm(lr,31,hr);
4479 if(get_final_value(hr,i,&value)) {
4484 emit_movimm(value,hr);
4493 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4497 for(hr=0;hr<HOST_REGS;hr++) {
4498 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4499 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4500 int value=constmap[i][hr];
4505 emit_movimm(value,hr);
4511 for(hr=0;hr<HOST_REGS;hr++) {
4512 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4513 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4514 if((is32>>(regmap[hr]&63))&1) {
4515 int lr=get_reg(regmap,regmap[hr]-64);
4517 emit_sarimm(lr,31,hr);
4521 int value=constmap[i][hr];
4526 emit_movimm(value,hr);
4534 // Write out all dirty registers (except cycle count)
4535 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4538 for(hr=0;hr<HOST_REGS;hr++) {
4539 if(hr!=EXCLUDE_REG) {
4540 if(i_regmap[hr]>0) {
4541 if(i_regmap[hr]!=CCREG) {
4542 if((i_dirty>>hr)&1) {
4543 if(i_regmap[hr]<64) {
4544 emit_storereg(i_regmap[hr],hr);
4546 if( ((i_is32>>i_regmap[hr])&1) ) {
4547 #ifdef DESTRUCTIVE_WRITEBACK
4548 emit_sarimm(hr,31,hr);
4549 emit_storereg(i_regmap[hr]|64,hr);
4551 emit_sarimm(hr,31,HOST_TEMPREG);
4552 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4557 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4558 emit_storereg(i_regmap[hr],hr);
4567 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4568 // This writes the registers not written by store_regs_bt
4569 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4572 int t=(addr-start)>>2;
4573 for(hr=0;hr<HOST_REGS;hr++) {
4574 if(hr!=EXCLUDE_REG) {
4575 if(i_regmap[hr]>0) {
4576 if(i_regmap[hr]!=CCREG) {
4577 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4578 if((i_dirty>>hr)&1) {
4579 if(i_regmap[hr]<64) {
4580 emit_storereg(i_regmap[hr],hr);
4582 if( ((i_is32>>i_regmap[hr])&1) ) {
4583 #ifdef DESTRUCTIVE_WRITEBACK
4584 emit_sarimm(hr,31,hr);
4585 emit_storereg(i_regmap[hr]|64,hr);
4587 emit_sarimm(hr,31,HOST_TEMPREG);
4588 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4593 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4594 emit_storereg(i_regmap[hr],hr);
4605 // Load all registers (except cycle count)
4606 void load_all_regs(signed char i_regmap[])
4609 for(hr=0;hr<HOST_REGS;hr++) {
4610 if(hr!=EXCLUDE_REG) {
4611 if(i_regmap[hr]==0) {
4615 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4617 emit_loadreg(i_regmap[hr],hr);
4623 // Load all current registers also needed by next instruction
4624 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4627 for(hr=0;hr<HOST_REGS;hr++) {
4628 if(hr!=EXCLUDE_REG) {
4629 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4630 if(i_regmap[hr]==0) {
4634 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4636 emit_loadreg(i_regmap[hr],hr);
4643 // Load all regs, storing cycle count if necessary
4644 void load_regs_entry(int t)
4647 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4648 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4649 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4650 emit_storereg(CCREG,HOST_CCREG);
4653 for(hr=0;hr<HOST_REGS;hr++) {
4654 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4655 if(regs[t].regmap_entry[hr]==0) {
4658 else if(regs[t].regmap_entry[hr]!=CCREG)
4660 emit_loadreg(regs[t].regmap_entry[hr],hr);
4665 for(hr=0;hr<HOST_REGS;hr++) {
4666 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4667 assert(regs[t].regmap_entry[hr]!=64);
4668 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4669 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4671 emit_loadreg(regs[t].regmap_entry[hr],hr);
4675 emit_sarimm(lr,31,hr);
4680 emit_loadreg(regs[t].regmap_entry[hr],hr);
4686 // Store dirty registers prior to branch
4687 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4689 if(internal_branch(i_is32,addr))
4691 int t=(addr-start)>>2;
4693 for(hr=0;hr<HOST_REGS;hr++) {
4694 if(hr!=EXCLUDE_REG) {
4695 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4696 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4697 if((i_dirty>>hr)&1) {
4698 if(i_regmap[hr]<64) {
4699 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4700 emit_storereg(i_regmap[hr],hr);
4701 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4702 #ifdef DESTRUCTIVE_WRITEBACK
4703 emit_sarimm(hr,31,hr);
4704 emit_storereg(i_regmap[hr]|64,hr);
4706 emit_sarimm(hr,31,HOST_TEMPREG);
4707 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4712 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4713 emit_storereg(i_regmap[hr],hr);
4724 // Branch out of this block, write out all dirty regs
4725 wb_dirtys(i_regmap,i_is32,i_dirty);
4729 // Load all needed registers for branch target
4730 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4732 //if(addr>=start && addr<(start+slen*4))
4733 if(internal_branch(i_is32,addr))
4735 int t=(addr-start)>>2;
4737 // Store the cycle count before loading something else
4738 if(i_regmap[HOST_CCREG]!=CCREG) {
4739 assert(i_regmap[HOST_CCREG]==-1);
4741 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4742 emit_storereg(CCREG,HOST_CCREG);
4745 for(hr=0;hr<HOST_REGS;hr++) {
4746 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4747 #ifdef DESTRUCTIVE_WRITEBACK
4748 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4750 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4752 if(regs[t].regmap_entry[hr]==0) {
4755 else if(regs[t].regmap_entry[hr]!=CCREG)
4757 emit_loadreg(regs[t].regmap_entry[hr],hr);
4763 for(hr=0;hr<HOST_REGS;hr++) {
4764 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4765 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4766 assert(regs[t].regmap_entry[hr]!=64);
4767 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4768 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4770 emit_loadreg(regs[t].regmap_entry[hr],hr);
4774 emit_sarimm(lr,31,hr);
4779 emit_loadreg(regs[t].regmap_entry[hr],hr);
4782 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4783 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4785 emit_sarimm(lr,31,hr);
4792 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4794 if(addr>=start && addr<start+slen*4-4)
4796 int t=(addr-start)>>2;
4798 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4799 for(hr=0;hr<HOST_REGS;hr++)
4803 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4805 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4812 if(i_regmap[hr]<TEMPREG)
4814 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4817 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4819 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4824 else // Same register but is it 32-bit or dirty?
4827 if(!((regs[t].dirty>>hr)&1))
4831 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4833 //printf("%x: dirty no match\n",addr);
4838 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4840 //printf("%x: is32 no match\n",addr);
4846 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4848 if(requires_32bit[t]&~i_is32) return 0;
4850 // Delay slots are not valid branch targets
4851 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4852 // Delay slots require additional processing, so do not match
4853 if(is_ds[t]) return 0;
4858 for(hr=0;hr<HOST_REGS;hr++)
4864 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4878 // Used when a branch jumps into the delay slot of another branch
4879 void ds_assemble_entry(int i)
4881 int t=(ba[i]-start)>>2;
4882 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4883 assem_debug("Assemble delay slot at %x\n",ba[i]);
4884 assem_debug("<->\n");
4885 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4886 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4887 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4888 address_generation(t,®s[t],regs[t].regmap_entry);
4889 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4890 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4895 alu_assemble(t,®s[t]);break;
4897 imm16_assemble(t,®s[t]);break;
4899 shift_assemble(t,®s[t]);break;
4901 shiftimm_assemble(t,®s[t]);break;
4903 load_assemble(t,®s[t]);break;
4905 loadlr_assemble(t,®s[t]);break;
4907 store_assemble(t,®s[t]);break;
4909 storelr_assemble(t,®s[t]);break;
4911 cop0_assemble(t,®s[t]);break;
4913 cop1_assemble(t,®s[t]);break;
4915 c1ls_assemble(t,®s[t]);break;
4917 cop2_assemble(t,®s[t]);break;
4919 c2ls_assemble(t,®s[t]);break;
4921 c2op_assemble(t,®s[t]);break;
4923 fconv_assemble(t,®s[t]);break;
4925 float_assemble(t,®s[t]);break;
4927 fcomp_assemble(t,®s[t]);break;
4929 multdiv_assemble(t,®s[t]);break;
4931 mov_assemble(t,®s[t]);break;
4941 printf("Jump in the delay slot. This is probably a bug.\n");
4943 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4944 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4945 if(internal_branch(regs[t].is32,ba[i]+4))
4946 assem_debug("branch: internal\n");
4948 assem_debug("branch: external\n");
4949 assert(internal_branch(regs[t].is32,ba[i]+4));
4950 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4954 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4963 //if(ba[i]>=start && ba[i]<(start+slen*4))
4964 if(internal_branch(branch_regs[i].is32,ba[i]))
4966 int t=(ba[i]-start)>>2;
4967 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4975 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4977 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4979 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4980 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4984 else if(*adj==0||invert) {
4985 emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
4991 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4995 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4998 void do_ccstub(int n)
5001 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
5002 set_jump_target(stubs[n][1],(int)out);
5004 if(stubs[n][6]==NULLDS) {
5005 // Delay slot instruction is nullified ("likely" branch)
5006 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
5008 else if(stubs[n][6]!=TAKEN) {
5009 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
5012 if(internal_branch(branch_regs[i].is32,ba[i]))
5013 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5017 // Save PC as return address
5018 emit_movimm(stubs[n][5],EAX);
5019 emit_writeword(EAX,(int)&pcaddr);
5023 // Return address depends on which way the branch goes
5024 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5026 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5027 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5028 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5029 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5039 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5043 #ifdef DESTRUCTIVE_WRITEBACK
5045 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5046 emit_loadreg(rs1[i],s1l);
5049 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5050 emit_loadreg(rs2[i],s1l);
5053 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5054 emit_loadreg(rs2[i],s2l);
5057 int addr=-1,alt=-1,ntaddr=-1;
5060 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5061 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5062 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5070 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5071 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5072 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5078 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5082 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5083 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5084 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5090 assert(hr<HOST_REGS);
5092 if((opcode[i]&0x2f)==4) // BEQ
5094 #ifdef HAVE_CMOV_IMM
5096 if(s2l>=0) emit_cmp(s1l,s2l);
5097 else emit_test(s1l,s1l);
5098 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5103 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5105 if(s2h>=0) emit_cmp(s1h,s2h);
5106 else emit_test(s1h,s1h);
5107 emit_cmovne_reg(alt,addr);
5109 if(s2l>=0) emit_cmp(s1l,s2l);
5110 else emit_test(s1l,s1l);
5111 emit_cmovne_reg(alt,addr);
5114 if((opcode[i]&0x2f)==5) // BNE
5116 #ifdef HAVE_CMOV_IMM
5118 if(s2l>=0) emit_cmp(s1l,s2l);
5119 else emit_test(s1l,s1l);
5120 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5125 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5127 if(s2h>=0) emit_cmp(s1h,s2h);
5128 else emit_test(s1h,s1h);
5129 emit_cmovne_reg(alt,addr);
5131 if(s2l>=0) emit_cmp(s1l,s2l);
5132 else emit_test(s1l,s1l);
5133 emit_cmovne_reg(alt,addr);
5136 if((opcode[i]&0x2f)==6) // BLEZ
5138 //emit_movimm(ba[i],alt);
5139 //emit_movimm(start+i*4+8,addr);
5140 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5142 if(s1h>=0) emit_mov(addr,ntaddr);
5143 emit_cmovl_reg(alt,addr);
5146 emit_cmovne_reg(ntaddr,addr);
5147 emit_cmovs_reg(alt,addr);
5150 if((opcode[i]&0x2f)==7) // BGTZ
5152 //emit_movimm(ba[i],addr);
5153 //emit_movimm(start+i*4+8,ntaddr);
5154 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5156 if(s1h>=0) emit_mov(addr,alt);
5157 emit_cmovl_reg(ntaddr,addr);
5160 emit_cmovne_reg(alt,addr);
5161 emit_cmovs_reg(ntaddr,addr);
5164 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5166 //emit_movimm(ba[i],alt);
5167 //emit_movimm(start+i*4+8,addr);
5168 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5169 if(s1h>=0) emit_test(s1h,s1h);
5170 else emit_test(s1l,s1l);
5171 emit_cmovs_reg(alt,addr);
5173 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5175 //emit_movimm(ba[i],addr);
5176 //emit_movimm(start+i*4+8,alt);
5177 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5178 if(s1h>=0) emit_test(s1h,s1h);
5179 else emit_test(s1l,s1l);
5180 emit_cmovs_reg(alt,addr);
5182 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5183 if(source[i]&0x10000) // BC1T
5185 //emit_movimm(ba[i],alt);
5186 //emit_movimm(start+i*4+8,addr);
5187 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5188 emit_testimm(s1l,0x800000);
5189 emit_cmovne_reg(alt,addr);
5193 //emit_movimm(ba[i],addr);
5194 //emit_movimm(start+i*4+8,alt);
5195 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5196 emit_testimm(s1l,0x800000);
5197 emit_cmovne_reg(alt,addr);
5200 emit_writeword(addr,(int)&pcaddr);
5205 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5206 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5207 r=get_reg(branch_regs[i].regmap,RTEMP);
5209 emit_writeword(r,(int)&pcaddr);
5211 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5213 // Update cycle count
5214 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5215 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5216 emit_call((int)cc_interrupt);
5217 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5218 if(stubs[n][6]==TAKEN) {
5219 if(internal_branch(branch_regs[i].is32,ba[i]))
5220 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5221 else if(itype[i]==RJUMP) {
5222 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5223 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5225 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5227 }else if(stubs[n][6]==NOTTAKEN) {
5228 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5229 else load_all_regs(branch_regs[i].regmap);
5230 }else if(stubs[n][6]==NULLDS) {
5231 // Delay slot instruction is nullified ("likely" branch)
5232 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5233 else load_all_regs(regs[i].regmap);
5235 load_all_regs(branch_regs[i].regmap);
5237 emit_jmp(stubs[n][2]); // return address
5239 /* This works but uses a lot of memory...
5240 emit_readword((int)&last_count,ECX);
5241 emit_add(HOST_CCREG,ECX,EAX);
5242 emit_writeword(EAX,(int)&Count);
5243 emit_call((int)gen_interupt);
5244 emit_readword((int)&Count,HOST_CCREG);
5245 emit_readword((int)&next_interupt,EAX);
5246 emit_readword((int)&pending_exception,EBX);
5247 emit_writeword(EAX,(int)&last_count);
5248 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5250 int jne_instr=(int)out;
5252 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5253 load_all_regs(branch_regs[i].regmap);
5254 emit_jmp(stubs[n][2]); // return address
5255 set_jump_target(jne_instr,(int)out);
5256 emit_readword((int)&pcaddr,EAX);
5257 // Call get_addr_ht instead of doing the hash table here.
5258 // This code is executed infrequently and takes up a lot of space
5259 // so smaller is better.
5260 emit_storereg(CCREG,HOST_CCREG);
5262 emit_call((int)get_addr_ht);
5263 emit_loadreg(CCREG,HOST_CCREG);
5264 emit_addimm(ESP,4,ESP);
5268 add_to_linker(int addr,int target,int ext)
5270 link_addr[linkcount][0]=addr;
5271 link_addr[linkcount][1]=target;
5272 link_addr[linkcount][2]=ext;
5276 static void ujump_assemble_write_ra(int i)
5279 unsigned int return_address;
5280 rt=get_reg(branch_regs[i].regmap,31);
5281 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5283 return_address=start+i*4+8;
5286 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5287 int temp=-1; // note: must be ds-safe
5291 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5292 else emit_movimm(return_address,rt);
5300 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5303 emit_movimm(return_address,rt); // PC into link register
5305 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5311 void ujump_assemble(int i,struct regstat *i_regs)
5313 signed char *i_regmap=i_regs->regmap;
5315 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5316 address_generation(i+1,i_regs,regs[i].regmap_entry);
5318 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5319 if(rt1[i]==31&&temp>=0)
5321 int return_address=start+i*4+8;
5322 if(get_reg(branch_regs[i].regmap,31)>0)
5323 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5326 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5327 ujump_assemble_write_ra(i); // writeback ra for DS
5330 ds_assemble(i+1,i_regs);
5331 uint64_t bc_unneeded=branch_regs[i].u;
5332 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5333 bc_unneeded|=1|(1LL<<rt1[i]);
5334 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5335 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5336 bc_unneeded,bc_unneeded_upper);
5337 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5338 if(!ra_done&&rt1[i]==31)
5339 ujump_assemble_write_ra(i);
5341 cc=get_reg(branch_regs[i].regmap,CCREG);
5342 assert(cc==HOST_CCREG);
5343 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5345 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5347 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5348 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5349 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5350 if(internal_branch(branch_regs[i].is32,ba[i]))
5351 assem_debug("branch: internal\n");
5353 assem_debug("branch: external\n");
5354 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5355 ds_assemble_entry(i);
5358 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5363 static void rjump_assemble_write_ra(int i)
5365 int rt,return_address;
5366 assert(rt1[i+1]!=rt1[i]);
5367 assert(rt2[i+1]!=rt1[i]);
5368 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5369 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5371 return_address=start+i*4+8;
5375 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5378 emit_movimm(return_address,rt); // PC into link register
5380 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5384 void rjump_assemble(int i,struct regstat *i_regs)
5386 signed char *i_regmap=i_regs->regmap;
5390 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5392 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5393 // Delay slot abuse, make a copy of the branch address register
5394 temp=get_reg(branch_regs[i].regmap,RTEMP);
5396 assert(regs[i].regmap[temp]==RTEMP);
5400 address_generation(i+1,i_regs,regs[i].regmap_entry);
5404 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5405 int return_address=start+i*4+8;
5406 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5412 int rh=get_reg(regs[i].regmap,RHASH);
5413 if(rh>=0) do_preload_rhash(rh);
5416 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5417 rjump_assemble_write_ra(i);
5420 ds_assemble(i+1,i_regs);
5421 uint64_t bc_unneeded=branch_regs[i].u;
5422 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5423 bc_unneeded|=1|(1LL<<rt1[i]);
5424 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5425 bc_unneeded&=~(1LL<<rs1[i]);
5426 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5427 bc_unneeded,bc_unneeded_upper);
5428 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5429 if(!ra_done&&rt1[i]!=0)
5430 rjump_assemble_write_ra(i);
5431 cc=get_reg(branch_regs[i].regmap,CCREG);
5432 assert(cc==HOST_CCREG);
5434 int rh=get_reg(branch_regs[i].regmap,RHASH);
5435 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5437 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5438 do_preload_rhtbl(ht);
5442 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5443 #ifdef DESTRUCTIVE_WRITEBACK
5444 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5445 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5446 emit_loadreg(rs1[i],rs);
5451 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5455 do_miniht_load(ht,rh);
5458 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5459 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5461 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5462 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5464 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5465 // special case for RFE
5470 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5473 do_miniht_jump(rs,rh,ht);
5478 //if(rs!=EAX) emit_mov(rs,EAX);
5479 //emit_jmp((int)jump_vaddr_eax);
5480 emit_jmp(jump_vaddr_reg[rs]);
5485 emit_shrimm(rs,16,rs);
5486 emit_xor(temp,rs,rs);
5487 emit_movzwl_reg(rs,rs);
5488 emit_shlimm(rs,4,rs);
5489 emit_cmpmem_indexed((int)hash_table,rs,temp);
5490 emit_jne((int)out+14);
5491 emit_readword_indexed((int)hash_table+4,rs,rs);
5493 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5494 emit_addimm_no_flags(8,rs);
5495 emit_jeq((int)out-17);
5496 // No hit on hash table, call compiler
5499 #ifdef DEBUG_CYCLE_COUNT
5500 emit_readword((int)&last_count,ECX);
5501 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5502 emit_readword((int)&next_interupt,ECX);
5503 emit_writeword(HOST_CCREG,(int)&Count);
5504 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5505 emit_writeword(ECX,(int)&last_count);
5508 emit_storereg(CCREG,HOST_CCREG);
5509 emit_call((int)get_addr);
5510 emit_loadreg(CCREG,HOST_CCREG);
5511 emit_addimm(ESP,4,ESP);
5513 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5514 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5518 void cjump_assemble(int i,struct regstat *i_regs)
5520 signed char *i_regmap=i_regs->regmap;
5523 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5524 assem_debug("match=%d\n",match);
5525 int s1h,s1l,s2h,s2l;
5526 int prev_cop1_usable=cop1_usable;
5527 int unconditional=0,nop=0;
5530 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5531 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5532 if(!match) invert=1;
5533 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5534 if(i>(ba[i]-start)>>2) invert=1;
5538 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5539 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5540 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5541 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5544 s1l=get_reg(i_regmap,rs1[i]);
5545 s1h=get_reg(i_regmap,rs1[i]|64);
5546 s2l=get_reg(i_regmap,rs2[i]);
5547 s2h=get_reg(i_regmap,rs2[i]|64);
5549 if(rs1[i]==0&&rs2[i]==0)
5551 if(opcode[i]&1) nop=1;
5552 else unconditional=1;
5553 //assert(opcode[i]!=5);
5554 //assert(opcode[i]!=7);
5555 //assert(opcode[i]!=0x15);
5556 //assert(opcode[i]!=0x17);
5562 only32=(regs[i].was32>>rs2[i])&1;
5567 only32=(regs[i].was32>>rs1[i])&1;
5570 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5574 // Out of order execution (delay slot first)
5576 address_generation(i+1,i_regs,regs[i].regmap_entry);
5577 ds_assemble(i+1,i_regs);
5579 uint64_t bc_unneeded=branch_regs[i].u;
5580 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5581 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5582 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5584 bc_unneeded_upper|=1;
5585 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5586 bc_unneeded,bc_unneeded_upper);
5587 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5588 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5589 cc=get_reg(branch_regs[i].regmap,CCREG);
5590 assert(cc==HOST_CCREG);
5592 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5593 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5594 //assem_debug("cycle count (adj)\n");
5596 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5597 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5598 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5599 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5601 assem_debug("branch: internal\n");
5603 assem_debug("branch: external\n");
5604 if(internal&&is_ds[(ba[i]-start)>>2]) {
5605 ds_assemble_entry(i);
5608 add_to_linker((int)out,ba[i],internal);
5611 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5612 if(((u_int)out)&7) emit_addnop(0);
5617 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5620 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5623 int taken=0,nottaken=0,nottaken1=0;
5624 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5625 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5629 if(opcode[i]==4) // BEQ
5631 if(s2h>=0) emit_cmp(s1h,s2h);
5632 else emit_test(s1h,s1h);
5636 if(opcode[i]==5) // BNE
5638 if(s2h>=0) emit_cmp(s1h,s2h);
5639 else emit_test(s1h,s1h);
5640 if(invert) taken=(int)out;
5641 else add_to_linker((int)out,ba[i],internal);
5644 if(opcode[i]==6) // BLEZ
5647 if(invert) taken=(int)out;
5648 else add_to_linker((int)out,ba[i],internal);
5653 if(opcode[i]==7) // BGTZ
5658 if(invert) taken=(int)out;
5659 else add_to_linker((int)out,ba[i],internal);
5664 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5666 if(opcode[i]==4) // BEQ
5668 if(s2l>=0) emit_cmp(s1l,s2l);
5669 else emit_test(s1l,s1l);
5674 add_to_linker((int)out,ba[i],internal);
5678 if(opcode[i]==5) // BNE
5680 if(s2l>=0) emit_cmp(s1l,s2l);
5681 else emit_test(s1l,s1l);
5686 add_to_linker((int)out,ba[i],internal);
5690 if(opcode[i]==6) // BLEZ
5697 add_to_linker((int)out,ba[i],internal);
5701 if(opcode[i]==7) // BGTZ
5708 add_to_linker((int)out,ba[i],internal);
5713 if(taken) set_jump_target(taken,(int)out);
5714 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5715 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5717 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5718 add_to_linker((int)out,ba[i],internal);
5721 add_to_linker((int)out,ba[i],internal*2);
5727 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5728 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5729 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5731 assem_debug("branch: internal\n");
5733 assem_debug("branch: external\n");
5734 if(internal&&is_ds[(ba[i]-start)>>2]) {
5735 ds_assemble_entry(i);
5738 add_to_linker((int)out,ba[i],internal);
5742 set_jump_target(nottaken,(int)out);
5745 if(nottaken1) set_jump_target(nottaken1,(int)out);
5747 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5749 } // (!unconditional)
5753 // In-order execution (branch first)
5754 //if(likely[i]) printf("IOL\n");
5757 int taken=0,nottaken=0,nottaken1=0;
5758 if(!unconditional&&!nop) {
5762 if((opcode[i]&0x2f)==4) // BEQ
5764 if(s2h>=0) emit_cmp(s1h,s2h);
5765 else emit_test(s1h,s1h);
5769 if((opcode[i]&0x2f)==5) // BNE
5771 if(s2h>=0) emit_cmp(s1h,s2h);
5772 else emit_test(s1h,s1h);
5776 if((opcode[i]&0x2f)==6) // BLEZ
5784 if((opcode[i]&0x2f)==7) // BGTZ
5794 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5796 if((opcode[i]&0x2f)==4) // BEQ
5798 if(s2l>=0) emit_cmp(s1l,s2l);
5799 else emit_test(s1l,s1l);
5803 if((opcode[i]&0x2f)==5) // BNE
5805 if(s2l>=0) emit_cmp(s1l,s2l);
5806 else emit_test(s1l,s1l);
5810 if((opcode[i]&0x2f)==6) // BLEZ
5816 if((opcode[i]&0x2f)==7) // BGTZ
5822 } // if(!unconditional)
5824 uint64_t ds_unneeded=branch_regs[i].u;
5825 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5826 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5827 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5828 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5830 ds_unneeded_upper|=1;
5833 if(taken) set_jump_target(taken,(int)out);
5834 assem_debug("1:\n");
5835 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5836 ds_unneeded,ds_unneeded_upper);
5838 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5839 address_generation(i+1,&branch_regs[i],0);
5840 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5841 ds_assemble(i+1,&branch_regs[i]);
5842 cc=get_reg(branch_regs[i].regmap,CCREG);
5844 emit_loadreg(CCREG,cc=HOST_CCREG);
5845 // CHECK: Is the following instruction (fall thru) allocated ok?
5847 assert(cc==HOST_CCREG);
5848 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5849 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5850 assem_debug("cycle count (adj)\n");
5851 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5852 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5854 assem_debug("branch: internal\n");
5856 assem_debug("branch: external\n");
5857 if(internal&&is_ds[(ba[i]-start)>>2]) {
5858 ds_assemble_entry(i);
5861 add_to_linker((int)out,ba[i],internal);
5866 cop1_usable=prev_cop1_usable;
5867 if(!unconditional) {
5868 if(nottaken1) set_jump_target(nottaken1,(int)out);
5869 set_jump_target(nottaken,(int)out);
5870 assem_debug("2:\n");
5872 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5873 ds_unneeded,ds_unneeded_upper);
5874 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5875 address_generation(i+1,&branch_regs[i],0);
5876 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5877 ds_assemble(i+1,&branch_regs[i]);
5879 cc=get_reg(branch_regs[i].regmap,CCREG);
5880 if(cc==-1&&!likely[i]) {
5881 // Cycle count isn't in a register, temporarily load it then write it out
5882 emit_loadreg(CCREG,HOST_CCREG);
5883 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5886 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5887 emit_storereg(CCREG,HOST_CCREG);
5890 cc=get_reg(i_regmap,CCREG);
5891 assert(cc==HOST_CCREG);
5892 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5895 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5901 void sjump_assemble(int i,struct regstat *i_regs)
5903 signed char *i_regmap=i_regs->regmap;
5906 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5907 assem_debug("smatch=%d\n",match);
5909 int prev_cop1_usable=cop1_usable;
5910 int unconditional=0,nevertaken=0;
5913 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5914 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5915 if(!match) invert=1;
5916 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5917 if(i>(ba[i]-start)>>2) invert=1;
5920 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5921 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5924 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5925 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5928 s1l=get_reg(i_regmap,rs1[i]);
5929 s1h=get_reg(i_regmap,rs1[i]|64);
5933 if(opcode2[i]&1) unconditional=1;
5935 // These are never taken (r0 is never less than zero)
5936 //assert(opcode2[i]!=0);
5937 //assert(opcode2[i]!=2);
5938 //assert(opcode2[i]!=0x10);
5939 //assert(opcode2[i]!=0x12);
5942 only32=(regs[i].was32>>rs1[i])&1;
5946 // Out of order execution (delay slot first)
5948 address_generation(i+1,i_regs,regs[i].regmap_entry);
5949 ds_assemble(i+1,i_regs);
5951 uint64_t bc_unneeded=branch_regs[i].u;
5952 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5953 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5954 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5956 bc_unneeded_upper|=1;
5957 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5958 bc_unneeded,bc_unneeded_upper);
5959 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5960 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5962 int rt,return_address;
5963 rt=get_reg(branch_regs[i].regmap,31);
5964 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5966 // Save the PC even if the branch is not taken
5967 return_address=start+i*4+8;
5968 emit_movimm(return_address,rt); // PC into link register
5970 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5974 cc=get_reg(branch_regs[i].regmap,CCREG);
5975 assert(cc==HOST_CCREG);
5977 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5978 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5979 assem_debug("cycle count (adj)\n");
5981 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5982 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5983 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5984 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5986 assem_debug("branch: internal\n");
5988 assem_debug("branch: external\n");
5989 if(internal&&is_ds[(ba[i]-start)>>2]) {
5990 ds_assemble_entry(i);
5993 add_to_linker((int)out,ba[i],internal);
5996 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5997 if(((u_int)out)&7) emit_addnop(0);
6001 else if(nevertaken) {
6002 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6005 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6009 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6010 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6014 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6021 add_to_linker((int)out,ba[i],internal);
6025 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6032 add_to_linker((int)out,ba[i],internal);
6040 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6047 add_to_linker((int)out,ba[i],internal);
6051 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6058 add_to_linker((int)out,ba[i],internal);
6065 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6066 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6068 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6069 add_to_linker((int)out,ba[i],internal);
6072 add_to_linker((int)out,ba[i],internal*2);
6078 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6079 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6080 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6082 assem_debug("branch: internal\n");
6084 assem_debug("branch: external\n");
6085 if(internal&&is_ds[(ba[i]-start)>>2]) {
6086 ds_assemble_entry(i);
6089 add_to_linker((int)out,ba[i],internal);
6093 set_jump_target(nottaken,(int)out);
6097 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6099 } // (!unconditional)
6103 // In-order execution (branch first)
6107 int rt,return_address;
6108 rt=get_reg(branch_regs[i].regmap,31);
6110 // Save the PC even if the branch is not taken
6111 return_address=start+i*4+8;
6112 emit_movimm(return_address,rt); // PC into link register
6114 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6118 if(!unconditional) {
6119 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6123 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6129 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6139 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6145 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6152 } // if(!unconditional)
6154 uint64_t ds_unneeded=branch_regs[i].u;
6155 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6156 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6157 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6158 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6160 ds_unneeded_upper|=1;
6163 //assem_debug("1:\n");
6164 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6165 ds_unneeded,ds_unneeded_upper);
6167 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6168 address_generation(i+1,&branch_regs[i],0);
6169 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6170 ds_assemble(i+1,&branch_regs[i]);
6171 cc=get_reg(branch_regs[i].regmap,CCREG);
6173 emit_loadreg(CCREG,cc=HOST_CCREG);
6174 // CHECK: Is the following instruction (fall thru) allocated ok?
6176 assert(cc==HOST_CCREG);
6177 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6178 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6179 assem_debug("cycle count (adj)\n");
6180 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6181 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6183 assem_debug("branch: internal\n");
6185 assem_debug("branch: external\n");
6186 if(internal&&is_ds[(ba[i]-start)>>2]) {
6187 ds_assemble_entry(i);
6190 add_to_linker((int)out,ba[i],internal);
6195 cop1_usable=prev_cop1_usable;
6196 if(!unconditional) {
6197 set_jump_target(nottaken,(int)out);
6198 assem_debug("1:\n");
6200 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6201 ds_unneeded,ds_unneeded_upper);
6202 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6203 address_generation(i+1,&branch_regs[i],0);
6204 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6205 ds_assemble(i+1,&branch_regs[i]);
6207 cc=get_reg(branch_regs[i].regmap,CCREG);
6208 if(cc==-1&&!likely[i]) {
6209 // Cycle count isn't in a register, temporarily load it then write it out
6210 emit_loadreg(CCREG,HOST_CCREG);
6211 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6214 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6215 emit_storereg(CCREG,HOST_CCREG);
6218 cc=get_reg(i_regmap,CCREG);
6219 assert(cc==HOST_CCREG);
6220 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6223 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6229 void fjump_assemble(int i,struct regstat *i_regs)
6231 signed char *i_regmap=i_regs->regmap;
6234 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6235 assem_debug("fmatch=%d\n",match);
6239 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6240 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6241 if(!match) invert=1;
6242 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6243 if(i>(ba[i]-start)>>2) invert=1;
6247 fs=get_reg(branch_regs[i].regmap,FSREG);
6248 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6251 fs=get_reg(i_regmap,FSREG);
6254 // Check cop1 unusable
6256 cs=get_reg(i_regmap,CSREG);
6258 emit_testimm(cs,0x20000000);
6261 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6266 // Out of order execution (delay slot first)
6268 ds_assemble(i+1,i_regs);
6270 uint64_t bc_unneeded=branch_regs[i].u;
6271 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6272 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6273 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6275 bc_unneeded_upper|=1;
6276 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6277 bc_unneeded,bc_unneeded_upper);
6278 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6279 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6280 cc=get_reg(branch_regs[i].regmap,CCREG);
6281 assert(cc==HOST_CCREG);
6282 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6283 assem_debug("cycle count (adj)\n");
6286 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6289 emit_testimm(fs,0x800000);
6290 if(source[i]&0x10000) // BC1T
6296 add_to_linker((int)out,ba[i],internal);
6305 add_to_linker((int)out,ba[i],internal);
6313 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6314 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6315 else if(match) emit_addnop(13);
6317 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6318 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6320 assem_debug("branch: internal\n");
6322 assem_debug("branch: external\n");
6323 if(internal&&is_ds[(ba[i]-start)>>2]) {
6324 ds_assemble_entry(i);
6327 add_to_linker((int)out,ba[i],internal);
6330 set_jump_target(nottaken,(int)out);
6334 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6336 } // (!unconditional)
6340 // In-order execution (branch first)
6344 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6347 emit_testimm(fs,0x800000);
6348 if(source[i]&0x10000) // BC1T
6359 } // if(!unconditional)
6361 uint64_t ds_unneeded=branch_regs[i].u;
6362 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6363 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6364 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6365 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6367 ds_unneeded_upper|=1;
6369 //assem_debug("1:\n");
6370 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6371 ds_unneeded,ds_unneeded_upper);
6373 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6374 address_generation(i+1,&branch_regs[i],0);
6375 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6376 ds_assemble(i+1,&branch_regs[i]);
6377 cc=get_reg(branch_regs[i].regmap,CCREG);
6379 emit_loadreg(CCREG,cc=HOST_CCREG);
6380 // CHECK: Is the following instruction (fall thru) allocated ok?
6382 assert(cc==HOST_CCREG);
6383 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6384 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6385 assem_debug("cycle count (adj)\n");
6386 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6387 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6389 assem_debug("branch: internal\n");
6391 assem_debug("branch: external\n");
6392 if(internal&&is_ds[(ba[i]-start)>>2]) {
6393 ds_assemble_entry(i);
6396 add_to_linker((int)out,ba[i],internal);
6401 if(1) { // <- FIXME (don't need this)
6402 set_jump_target(nottaken,(int)out);
6403 assem_debug("1:\n");
6405 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6406 ds_unneeded,ds_unneeded_upper);
6407 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6408 address_generation(i+1,&branch_regs[i],0);
6409 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6410 ds_assemble(i+1,&branch_regs[i]);
6412 cc=get_reg(branch_regs[i].regmap,CCREG);
6413 if(cc==-1&&!likely[i]) {
6414 // Cycle count isn't in a register, temporarily load it then write it out
6415 emit_loadreg(CCREG,HOST_CCREG);
6416 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6419 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6420 emit_storereg(CCREG,HOST_CCREG);
6423 cc=get_reg(i_regmap,CCREG);
6424 assert(cc==HOST_CCREG);
6425 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6428 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6434 static void pagespan_assemble(int i,struct regstat *i_regs)
6436 int s1l=get_reg(i_regs->regmap,rs1[i]);
6437 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6438 int s2l=get_reg(i_regs->regmap,rs2[i]);
6439 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6440 void *nt_branch=NULL;
6443 int unconditional=0;
6453 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6457 int addr,alt,ntaddr;
6458 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6462 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6463 (i_regs->regmap[hr]&63)!=rs1[i] &&
6464 (i_regs->regmap[hr]&63)!=rs2[i] )
6473 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6474 (i_regs->regmap[hr]&63)!=rs1[i] &&
6475 (i_regs->regmap[hr]&63)!=rs2[i] )
6481 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6485 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6486 (i_regs->regmap[hr]&63)!=rs1[i] &&
6487 (i_regs->regmap[hr]&63)!=rs2[i] )
6494 assert(hr<HOST_REGS);
6495 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6496 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6498 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6499 if(opcode[i]==2) // J
6503 if(opcode[i]==3) // JAL
6506 int rt=get_reg(i_regs->regmap,31);
6507 emit_movimm(start+i*4+8,rt);
6510 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6513 if(opcode2[i]==9) // JALR
6515 int rt=get_reg(i_regs->regmap,rt1[i]);
6516 emit_movimm(start+i*4+8,rt);
6519 if((opcode[i]&0x3f)==4) // BEQ
6526 #ifdef HAVE_CMOV_IMM
6528 if(s2l>=0) emit_cmp(s1l,s2l);
6529 else emit_test(s1l,s1l);
6530 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6536 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6538 if(s2h>=0) emit_cmp(s1h,s2h);
6539 else emit_test(s1h,s1h);
6540 emit_cmovne_reg(alt,addr);
6542 if(s2l>=0) emit_cmp(s1l,s2l);
6543 else emit_test(s1l,s1l);
6544 emit_cmovne_reg(alt,addr);
6547 if((opcode[i]&0x3f)==5) // BNE
6549 #ifdef HAVE_CMOV_IMM
6551 if(s2l>=0) emit_cmp(s1l,s2l);
6552 else emit_test(s1l,s1l);
6553 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6559 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6561 if(s2h>=0) emit_cmp(s1h,s2h);
6562 else emit_test(s1h,s1h);
6563 emit_cmovne_reg(alt,addr);
6565 if(s2l>=0) emit_cmp(s1l,s2l);
6566 else emit_test(s1l,s1l);
6567 emit_cmovne_reg(alt,addr);
6570 if((opcode[i]&0x3f)==0x14) // BEQL
6573 if(s2h>=0) emit_cmp(s1h,s2h);
6574 else emit_test(s1h,s1h);
6578 if(s2l>=0) emit_cmp(s1l,s2l);
6579 else emit_test(s1l,s1l);
6580 if(nottaken) set_jump_target(nottaken,(int)out);
6584 if((opcode[i]&0x3f)==0x15) // BNEL
6587 if(s2h>=0) emit_cmp(s1h,s2h);
6588 else emit_test(s1h,s1h);
6592 if(s2l>=0) emit_cmp(s1l,s2l);
6593 else emit_test(s1l,s1l);
6596 if(taken) set_jump_target(taken,(int)out);
6598 if((opcode[i]&0x3f)==6) // BLEZ
6600 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6602 if(s1h>=0) emit_mov(addr,ntaddr);
6603 emit_cmovl_reg(alt,addr);
6606 emit_cmovne_reg(ntaddr,addr);
6607 emit_cmovs_reg(alt,addr);
6610 if((opcode[i]&0x3f)==7) // BGTZ
6612 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6614 if(s1h>=0) emit_mov(addr,alt);
6615 emit_cmovl_reg(ntaddr,addr);
6618 emit_cmovne_reg(alt,addr);
6619 emit_cmovs_reg(ntaddr,addr);
6622 if((opcode[i]&0x3f)==0x16) // BLEZL
6624 assert((opcode[i]&0x3f)!=0x16);
6626 if((opcode[i]&0x3f)==0x17) // BGTZL
6628 assert((opcode[i]&0x3f)!=0x17);
6630 assert(opcode[i]!=1); // BLTZ/BGEZ
6632 //FIXME: Check CSREG
6633 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6634 if((source[i]&0x30000)==0) // BC1F
6636 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6637 emit_testimm(s1l,0x800000);
6638 emit_cmovne_reg(alt,addr);
6640 if((source[i]&0x30000)==0x10000) // BC1T
6642 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6643 emit_testimm(s1l,0x800000);
6644 emit_cmovne_reg(alt,addr);
6646 if((source[i]&0x30000)==0x20000) // BC1FL
6648 emit_testimm(s1l,0x800000);
6652 if((source[i]&0x30000)==0x30000) // BC1TL
6654 emit_testimm(s1l,0x800000);
6660 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6661 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6662 if(likely[i]||unconditional)
6664 emit_movimm(ba[i],HOST_BTREG);
6666 else if(addr!=HOST_BTREG)
6668 emit_mov(addr,HOST_BTREG);
6670 void *branch_addr=out;
6672 int target_addr=start+i*4+5;
6674 void *compiled_target_addr=check_addr(target_addr);
6675 emit_extjump_ds((int)branch_addr,target_addr);
6676 if(compiled_target_addr) {
6677 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6678 add_link(target_addr,stub);
6680 else set_jump_target((int)branch_addr,(int)stub);
6683 set_jump_target((int)nottaken,(int)out);
6684 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6685 void *branch_addr=out;
6687 int target_addr=start+i*4+8;
6689 void *compiled_target_addr=check_addr(target_addr);
6690 emit_extjump_ds((int)branch_addr,target_addr);
6691 if(compiled_target_addr) {
6692 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6693 add_link(target_addr,stub);
6695 else set_jump_target((int)branch_addr,(int)stub);
6699 // Assemble the delay slot for the above
6700 static void pagespan_ds()
6702 assem_debug("initial delay slot:\n");
6703 u_int vaddr=start+1;
6704 u_int page=get_page(vaddr);
6705 u_int vpage=get_vpage(vaddr);
6706 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6708 ll_add(jump_in+page,vaddr,(void *)out);
6709 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6710 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6711 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6712 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6713 emit_writeword(HOST_BTREG,(int)&branch_target);
6714 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6715 address_generation(0,®s[0],regs[0].regmap_entry);
6716 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6717 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6722 alu_assemble(0,®s[0]);break;
6724 imm16_assemble(0,®s[0]);break;
6726 shift_assemble(0,®s[0]);break;
6728 shiftimm_assemble(0,®s[0]);break;
6730 load_assemble(0,®s[0]);break;
6732 loadlr_assemble(0,®s[0]);break;
6734 store_assemble(0,®s[0]);break;
6736 storelr_assemble(0,®s[0]);break;
6738 cop0_assemble(0,®s[0]);break;
6740 cop1_assemble(0,®s[0]);break;
6742 c1ls_assemble(0,®s[0]);break;
6744 cop2_assemble(0,®s[0]);break;
6746 c2ls_assemble(0,®s[0]);break;
6748 c2op_assemble(0,®s[0]);break;
6750 fconv_assemble(0,®s[0]);break;
6752 float_assemble(0,®s[0]);break;
6754 fcomp_assemble(0,®s[0]);break;
6756 multdiv_assemble(0,®s[0]);break;
6758 mov_assemble(0,®s[0]);break;
6768 printf("Jump in the delay slot. This is probably a bug.\n");
6770 int btaddr=get_reg(regs[0].regmap,BTREG);
6772 btaddr=get_reg(regs[0].regmap,-1);
6773 emit_readword((int)&branch_target,btaddr);
6775 assert(btaddr!=HOST_CCREG);
6776 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6778 emit_movimm(start+4,HOST_TEMPREG);
6779 emit_cmp(btaddr,HOST_TEMPREG);
6781 emit_cmpimm(btaddr,start+4);
6783 int branch=(int)out;
6785 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6786 emit_jmp(jump_vaddr_reg[btaddr]);
6787 set_jump_target(branch,(int)out);
6788 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6789 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6792 // Basic liveness analysis for MIPS registers
6793 void unneeded_registers(int istart,int iend,int r)
6796 uint64_t u,uu,gte_u,b,bu,gte_bu;
6797 uint64_t temp_u,temp_uu,temp_gte_u=0;
6799 uint64_t gte_u_unknown=0;
6800 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6804 gte_u=gte_u_unknown;
6806 u=unneeded_reg[iend+1];
6807 uu=unneeded_reg_upper[iend+1];
6809 gte_u=gte_unneeded[iend+1];
6812 for (i=iend;i>=istart;i--)
6814 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6815 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6817 // If subroutine call, flag return address as a possible branch target
6818 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6820 if(ba[i]<start || ba[i]>=(start+slen*4))
6822 // Branch out of this block, flush all regs
6825 gte_u=gte_u_unknown;
6827 if(itype[i]==UJUMP&&rt1[i]==31)
6829 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6831 if(itype[i]==RJUMP&&rs1[i]==31)
6833 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6835 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6836 if(itype[i]==UJUMP&&rt1[i]==31)
6838 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6839 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6841 if(itype[i]==RJUMP&&rs1[i]==31)
6843 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6844 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6847 branch_unneeded_reg[i]=u;
6848 branch_unneeded_reg_upper[i]=uu;
6849 // Merge in delay slot
6850 tdep=(~uu>>rt1[i+1])&1;
6851 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6852 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6853 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6854 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6855 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6858 gte_u&=~gte_rs[i+1];
6859 // If branch is "likely" (and conditional)
6860 // then we skip the delay slot on the fall-thru path
6863 u&=unneeded_reg[i+2];
6864 uu&=unneeded_reg_upper[i+2];
6865 gte_u&=gte_unneeded[i+2];
6871 gte_u=gte_u_unknown;
6877 // Internal branch, flag target
6878 bt[(ba[i]-start)>>2]=1;
6879 if(ba[i]<=start+i*4) {
6881 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6883 // Unconditional branch
6887 // Conditional branch (not taken case)
6888 temp_u=unneeded_reg[i+2];
6889 temp_uu=unneeded_reg_upper[i+2];
6890 temp_gte_u&=gte_unneeded[i+2];
6892 // Merge in delay slot
6893 tdep=(~temp_uu>>rt1[i+1])&1;
6894 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6895 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6896 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6897 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6898 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6899 temp_u|=1;temp_uu|=1;
6900 temp_gte_u|=gte_rt[i+1];
6901 temp_gte_u&=~gte_rs[i+1];
6902 // If branch is "likely" (and conditional)
6903 // then we skip the delay slot on the fall-thru path
6906 temp_u&=unneeded_reg[i+2];
6907 temp_uu&=unneeded_reg_upper[i+2];
6908 temp_gte_u&=gte_unneeded[i+2];
6914 temp_gte_u=gte_u_unknown;
6917 tdep=(~temp_uu>>rt1[i])&1;
6918 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6919 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6920 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6921 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6922 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6923 temp_u|=1;temp_uu|=1;
6924 temp_gte_u|=gte_rt[i];
6925 temp_gte_u&=~gte_rs[i];
6926 unneeded_reg[i]=temp_u;
6927 unneeded_reg_upper[i]=temp_uu;
6928 gte_unneeded[i]=temp_gte_u;
6929 // Only go three levels deep. This recursion can take an
6930 // excessive amount of time if there are a lot of nested loops.
6932 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6934 unneeded_reg[(ba[i]-start)>>2]=1;
6935 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6936 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6939 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6941 // Unconditional branch
6942 u=unneeded_reg[(ba[i]-start)>>2];
6943 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6944 gte_u=gte_unneeded[(ba[i]-start)>>2];
6945 branch_unneeded_reg[i]=u;
6946 branch_unneeded_reg_upper[i]=uu;
6949 //branch_unneeded_reg[i]=u;
6950 //branch_unneeded_reg_upper[i]=uu;
6951 // Merge in delay slot
6952 tdep=(~uu>>rt1[i+1])&1;
6953 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6954 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6955 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6956 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6957 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6960 gte_u&=~gte_rs[i+1];
6962 // Conditional branch
6963 b=unneeded_reg[(ba[i]-start)>>2];
6964 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6965 gte_bu=gte_unneeded[(ba[i]-start)>>2];
6966 branch_unneeded_reg[i]=b;
6967 branch_unneeded_reg_upper[i]=bu;
6970 //branch_unneeded_reg[i]=b;
6971 //branch_unneeded_reg_upper[i]=bu;
6972 // Branch delay slot
6973 tdep=(~uu>>rt1[i+1])&1;
6974 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6975 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6976 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6977 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6978 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6980 gte_bu|=gte_rt[i+1];
6981 gte_bu&=~gte_rs[i+1];
6982 // If branch is "likely" then we skip the
6983 // delay slot on the fall-thru path
6989 u&=unneeded_reg[i+2];
6990 uu&=unneeded_reg_upper[i+2];
6991 gte_u&=gte_unneeded[i+2];
7003 branch_unneeded_reg[i]&=unneeded_reg[i+2];
7004 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
7005 //branch_unneeded_reg[i]=1;
7006 //branch_unneeded_reg_upper[i]=1;
7008 branch_unneeded_reg[i]=1;
7009 branch_unneeded_reg_upper[i]=1;
7015 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7017 // SYSCALL instruction (software interrupt)
7021 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7023 // ERET instruction (return from interrupt)
7028 tdep=(~uu>>rt1[i])&1;
7029 // Written registers are unneeded
7035 // Accessed registers are needed
7041 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
7042 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
7043 // Source-target dependencies
7044 uu&=~(tdep<<dep1[i]);
7045 uu&=~(tdep<<dep2[i]);
7046 // R0 is always unneeded
7050 unneeded_reg_upper[i]=uu;
7051 gte_unneeded[i]=gte_u;
7053 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7056 for(r=1;r<=CCREG;r++) {
7057 if((unneeded_reg[i]>>r)&1) {
7058 if(r==HIREG) printf(" HI");
7059 else if(r==LOREG) printf(" LO");
7060 else printf(" r%d",r);
7064 for(r=1;r<=CCREG;r++) {
7065 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7066 if(r==HIREG) printf(" HI");
7067 else if(r==LOREG) printf(" LO");
7068 else printf(" r%d",r);
7074 for (i=iend;i>=istart;i--)
7076 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7081 // Identify registers which are likely to contain 32-bit values
7082 // This is used to predict whether any branches will jump to a
7083 // location with 64-bit values in registers.
7084 static void provisional_32bit()
7088 uint64_t lastbranch=1;
7093 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7094 if(i>1) is32=lastbranch;
7100 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7102 if(i>2) is32=lastbranch;
7106 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7108 if(rs1[i-2]==0||rs2[i-2]==0)
7111 is32|=1LL<<rs1[i-2];
7114 is32|=1LL<<rs2[i-2];
7119 // If something jumps here with 64-bit values
7120 // then promote those registers to 64 bits
7123 uint64_t temp_is32=is32;
7126 if(ba[j]==start+i*4)
7127 //temp_is32&=branch_regs[j].is32;
7132 if(ba[j]==start+i*4)
7143 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7144 // Branches don't write registers, consider the delay slot instead.
7155 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7156 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7165 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7166 if(op==0x22) is32|=1LL<<rt; // LWL
7169 if (op==0x08||op==0x09|| // ADDI/ADDIU
7170 op==0x0a||op==0x0b|| // SLTI/SLTIU
7176 if(op==0x18||op==0x19) { // DADDI/DADDIU
7179 // is32|=((is32>>s1)&1LL)<<rt;
7181 if(op==0x0d||op==0x0e) { // ORI/XORI
7182 uint64_t sr=((is32>>s1)&1LL);
7198 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7201 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7204 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7205 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7209 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7214 uint64_t sr=((is32>>s1)&1LL);
7219 uint64_t sr=((is32>>s2)&1LL);
7227 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7232 uint64_t sr=((is32>>s1)&1LL);
7242 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7243 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7246 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7251 uint64_t sr=((is32>>s1)&1LL);
7257 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7258 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7262 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7263 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7266 if(op2==0) is32|=1LL<<rt; // MFC0
7270 if(op2==0) is32|=1LL<<rt; // MFC1
7271 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7272 if(op2==2) is32|=1LL<<rt; // CFC1
7294 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7296 if(rt1[i-1]==31) // JAL/JALR
7298 // Subroutine call will return here, don't alloc any registers
7303 // Internal branch will jump here, match registers to caller
7311 // Identify registers which may be assumed to contain 32-bit values
7312 // and where optimizations will rely on this.
7313 // This is used to determine whether backward branches can safely
7314 // jump to a location with 64-bit values in registers.
7315 static void provisional_r32()
7320 for (i=slen-1;i>=0;i--)
7323 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7325 if(ba[i]<start || ba[i]>=(start+slen*4))
7327 // Branch out of this block, don't need anything
7333 // Need whatever matches the target
7334 // (and doesn't get overwritten by the delay slot instruction)
7336 int t=(ba[i]-start)>>2;
7337 if(ba[i]>start+i*4) {
7339 //if(!(requires_32bit[t]&~regs[i].was32))
7340 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7341 if(!(pr32[t]&~regs[i].was32))
7342 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7345 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7346 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7349 // Conditional branch may need registers for following instructions
7350 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7353 //r32|=requires_32bit[i+2];
7356 // Mark this address as a branch target since it may be called
7357 // upon return from interrupt
7361 // Merge in delay slot
7363 // These are overwritten unless the branch is "likely"
7364 // and the delay slot is nullified if not taken
7365 r32&=~(1LL<<rt1[i+1]);
7366 r32&=~(1LL<<rt2[i+1]);
7368 // Assume these are needed (delay slot)
7371 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7375 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7377 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7379 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7381 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7383 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7386 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7388 // SYSCALL instruction (software interrupt)
7391 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7393 // ERET instruction (return from interrupt)
7397 r32&=~(1LL<<rt1[i]);
7398 r32&=~(1LL<<rt2[i]);
7401 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7405 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7407 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7409 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7411 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7413 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7415 //requires_32bit[i]=r32;
7418 // Dirty registers which are 32-bit, require 32-bit input
7419 // as they will be written as 32-bit values
7420 for(hr=0;hr<HOST_REGS;hr++)
7422 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7423 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7424 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7425 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7426 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7433 // Write back dirty registers as soon as we will no longer modify them,
7434 // so that we don't end up with lots of writes at the branches.
7435 void clean_registers(int istart,int iend,int wr)
7439 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7440 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7442 will_dirty_i=will_dirty_next=0;
7443 wont_dirty_i=wont_dirty_next=0;
7445 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7446 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7448 for (i=iend;i>=istart;i--)
7450 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7452 if(ba[i]<start || ba[i]>=(start+slen*4))
7454 // Branch out of this block, flush all regs
7455 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7457 // Unconditional branch
7460 // Merge in delay slot (will dirty)
7461 for(r=0;r<HOST_REGS;r++) {
7462 if(r!=EXCLUDE_REG) {
7463 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7464 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7465 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7466 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7467 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7468 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7469 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7470 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7471 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7472 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7473 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7474 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7475 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7476 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7482 // Conditional branch
7484 wont_dirty_i=wont_dirty_next;
7485 // Merge in delay slot (will dirty)
7486 for(r=0;r<HOST_REGS;r++) {
7487 if(r!=EXCLUDE_REG) {
7489 // Might not dirty if likely branch is not taken
7490 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7491 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7492 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7493 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7494 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7495 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7496 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7497 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7498 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7499 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7500 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7501 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7502 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7503 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7508 // Merge in delay slot (wont dirty)
7509 for(r=0;r<HOST_REGS;r++) {
7510 if(r!=EXCLUDE_REG) {
7511 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7512 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7513 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7514 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7515 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7516 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7517 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7518 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7519 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7520 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7524 #ifndef DESTRUCTIVE_WRITEBACK
7525 branch_regs[i].dirty&=wont_dirty_i;
7527 branch_regs[i].dirty|=will_dirty_i;
7533 if(ba[i]<=start+i*4) {
7535 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7537 // Unconditional branch
7540 // Merge in delay slot (will dirty)
7541 for(r=0;r<HOST_REGS;r++) {
7542 if(r!=EXCLUDE_REG) {
7543 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7544 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7545 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7546 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7547 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7548 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7549 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7550 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7551 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7552 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7553 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7554 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7555 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7556 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7560 // Conditional branch (not taken case)
7561 temp_will_dirty=will_dirty_next;
7562 temp_wont_dirty=wont_dirty_next;
7563 // Merge in delay slot (will dirty)
7564 for(r=0;r<HOST_REGS;r++) {
7565 if(r!=EXCLUDE_REG) {
7567 // Will not dirty if likely branch is not taken
7568 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7569 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7570 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7571 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7572 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7573 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7574 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7575 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7576 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7577 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7578 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7579 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7580 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7581 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7586 // Merge in delay slot (wont dirty)
7587 for(r=0;r<HOST_REGS;r++) {
7588 if(r!=EXCLUDE_REG) {
7589 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7590 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7591 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7592 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7593 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7594 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7595 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7596 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7597 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7598 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7601 // Deal with changed mappings
7603 for(r=0;r<HOST_REGS;r++) {
7604 if(r!=EXCLUDE_REG) {
7605 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7606 temp_will_dirty&=~(1<<r);
7607 temp_wont_dirty&=~(1<<r);
7608 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7609 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7610 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7612 temp_will_dirty|=1<<r;
7613 temp_wont_dirty|=1<<r;
7620 will_dirty[i]=temp_will_dirty;
7621 wont_dirty[i]=temp_wont_dirty;
7622 clean_registers((ba[i]-start)>>2,i-1,0);
7624 // Limit recursion. It can take an excessive amount
7625 // of time if there are a lot of nested loops.
7626 will_dirty[(ba[i]-start)>>2]=0;
7627 wont_dirty[(ba[i]-start)>>2]=-1;
7632 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7634 // Unconditional branch
7637 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7638 for(r=0;r<HOST_REGS;r++) {
7639 if(r!=EXCLUDE_REG) {
7640 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7641 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7642 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7644 if(branch_regs[i].regmap[r]>=0) {
7645 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7646 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7651 // Merge in delay slot
7652 for(r=0;r<HOST_REGS;r++) {
7653 if(r!=EXCLUDE_REG) {
7654 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7655 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7656 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7657 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7658 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7659 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7660 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7661 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7662 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7663 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7664 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7665 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7666 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7667 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7671 // Conditional branch
7672 will_dirty_i=will_dirty_next;
7673 wont_dirty_i=wont_dirty_next;
7674 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7675 for(r=0;r<HOST_REGS;r++) {
7676 if(r!=EXCLUDE_REG) {
7677 signed char target_reg=branch_regs[i].regmap[r];
7678 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7679 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7680 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7682 else if(target_reg>=0) {
7683 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7684 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7686 // Treat delay slot as part of branch too
7687 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7688 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7689 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7693 will_dirty[i+1]&=~(1<<r);
7698 // Merge in delay slot
7699 for(r=0;r<HOST_REGS;r++) {
7700 if(r!=EXCLUDE_REG) {
7702 // Might not dirty if likely branch is not taken
7703 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7704 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7705 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7706 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7707 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7708 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7709 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7710 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7711 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7712 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7713 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7714 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7715 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7716 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7721 // Merge in delay slot (won't dirty)
7722 for(r=0;r<HOST_REGS;r++) {
7723 if(r!=EXCLUDE_REG) {
7724 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7725 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7726 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7727 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7728 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7729 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7730 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7731 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7732 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7733 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7737 #ifndef DESTRUCTIVE_WRITEBACK
7738 branch_regs[i].dirty&=wont_dirty_i;
7740 branch_regs[i].dirty|=will_dirty_i;
7745 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7747 // SYSCALL instruction (software interrupt)
7751 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7753 // ERET instruction (return from interrupt)
7757 will_dirty_next=will_dirty_i;
7758 wont_dirty_next=wont_dirty_i;
7759 for(r=0;r<HOST_REGS;r++) {
7760 if(r!=EXCLUDE_REG) {
7761 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7762 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7763 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7764 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7765 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7766 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7767 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7768 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7770 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7772 // Don't store a register immediately after writing it,
7773 // may prevent dual-issue.
7774 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7775 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7781 will_dirty[i]=will_dirty_i;
7782 wont_dirty[i]=wont_dirty_i;
7783 // Mark registers that won't be dirtied as not dirty
7785 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7786 for(r=0;r<HOST_REGS;r++) {
7787 if((will_dirty_i>>r)&1) {
7793 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7794 regs[i].dirty|=will_dirty_i;
7795 #ifndef DESTRUCTIVE_WRITEBACK
7796 regs[i].dirty&=wont_dirty_i;
7797 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7799 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7800 for(r=0;r<HOST_REGS;r++) {
7801 if(r!=EXCLUDE_REG) {
7802 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7803 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7804 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7812 for(r=0;r<HOST_REGS;r++) {
7813 if(r!=EXCLUDE_REG) {
7814 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7815 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7816 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7824 // Deal with changed mappings
7825 temp_will_dirty=will_dirty_i;
7826 temp_wont_dirty=wont_dirty_i;
7827 for(r=0;r<HOST_REGS;r++) {
7828 if(r!=EXCLUDE_REG) {
7830 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7832 #ifndef DESTRUCTIVE_WRITEBACK
7833 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7835 regs[i].wasdirty|=will_dirty_i&(1<<r);
7838 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7839 // Register moved to a different register
7840 will_dirty_i&=~(1<<r);
7841 wont_dirty_i&=~(1<<r);
7842 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7843 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7845 #ifndef DESTRUCTIVE_WRITEBACK
7846 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7848 regs[i].wasdirty|=will_dirty_i&(1<<r);
7852 will_dirty_i&=~(1<<r);
7853 wont_dirty_i&=~(1<<r);
7854 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7855 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7856 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7859 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7869 void disassemble_inst(int i)
7871 if (bt[i]) printf("*"); else printf(" ");
7874 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7876 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7878 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7880 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7882 if (opcode[i]==0x9&&rt1[i]!=31)
7883 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7885 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7888 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7890 if(opcode[i]==0xf) //LUI
7891 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7893 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7897 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7901 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7905 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7908 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7911 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7914 if((opcode2[i]&0x1d)==0x10)
7915 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7916 else if((opcode2[i]&0x1d)==0x11)
7917 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7919 printf (" %x: %s\n",start+i*4,insn[i]);
7923 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7924 else if(opcode2[i]==4)
7925 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7926 else printf (" %x: %s\n",start+i*4,insn[i]);
7930 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7931 else if(opcode2[i]>3)
7932 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7933 else printf (" %x: %s\n",start+i*4,insn[i]);
7937 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7938 else if(opcode2[i]>3)
7939 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7940 else printf (" %x: %s\n",start+i*4,insn[i]);
7943 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7946 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7949 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7952 //printf (" %s %8x\n",insn[i],source[i]);
7953 printf (" %x: %s\n",start+i*4,insn[i]);
7957 static void disassemble_inst(int i) {}
7960 // clear the state completely, instead of just marking
7961 // things invalid like invalidate_all_pages() does
7962 void new_dynarec_clear_full()
7965 out=(u_char *)BASE_ADDR;
7966 memset(invalid_code,1,sizeof(invalid_code));
7967 memset(hash_table,0xff,sizeof(hash_table));
7968 memset(mini_ht,-1,sizeof(mini_ht));
7969 memset(restore_candidate,0,sizeof(restore_candidate));
7970 memset(shadow,0,sizeof(shadow));
7972 expirep=16384; // Expiry pointer, +2 blocks
7973 pending_exception=0;
7976 inv_code_start=inv_code_end=~0;
7980 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7982 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7983 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7984 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7987 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7988 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7989 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7992 void new_dynarec_init()
7994 printf("Init new dynarec\n");
7995 out=(u_char *)BASE_ADDR;
7996 #ifdef BASE_ADDR_FIXED
7997 if (mmap (out, 1<<TARGET_SIZE_2,
7998 PROT_READ | PROT_WRITE | PROT_EXEC,
7999 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
8000 -1, 0) <= 0) {printf("mmap() failed\n");}
8002 // not all systems allow execute in data segment by default
8003 if (mprotect(out, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
8004 printf("mprotect() failed\n");
8007 rdword=&readmem_dword;
8008 fake_pc.f.r.rs=&readmem_dword;
8009 fake_pc.f.r.rt=&readmem_dword;
8010 fake_pc.f.r.rd=&readmem_dword;
8013 cycle_multiplier=200;
8014 new_dynarec_clear_full();
8016 // Copy this into local area so we don't have to put it in every literal pool
8017 invc_ptr=invalid_code;
8020 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8021 writemem[n] = write_nomem_new;
8022 writememb[n] = write_nomemb_new;
8023 writememh[n] = write_nomemh_new;
8025 writememd[n] = write_nomemd_new;
8027 readmem[n] = read_nomem_new;
8028 readmemb[n] = read_nomemb_new;
8029 readmemh[n] = read_nomemh_new;
8031 readmemd[n] = read_nomemd_new;
8034 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8035 writemem[n] = write_rdram_new;
8036 writememb[n] = write_rdramb_new;
8037 writememh[n] = write_rdramh_new;
8039 writememd[n] = write_rdramd_new;
8042 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8043 writemem[n] = write_nomem_new;
8044 writememb[n] = write_nomemb_new;
8045 writememh[n] = write_nomemh_new;
8047 writememd[n] = write_nomemd_new;
8049 readmem[n] = read_nomem_new;
8050 readmemb[n] = read_nomemb_new;
8051 readmemh[n] = read_nomemh_new;
8053 readmemd[n] = read_nomemd_new;
8061 void new_dynarec_cleanup()
8064 #ifdef BASE_ADDR_FIXED
8065 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
8067 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8068 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8069 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8071 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8075 int new_recompile_block(int addr)
8078 if(addr==0x800cd050) {
8080 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8082 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8085 //if(Count==365117028) tracedebug=1;
8086 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8087 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8088 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8090 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8091 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8092 /*if(Count>=312978186) {
8096 start = (u_int)addr&~3;
8097 //assert(((u_int)addr&1)==0);
8098 new_dynarec_did_compile=1;
8100 if (Config.HLE && start == 0x80001000) // hlecall
8102 // XXX: is this enough? Maybe check hleSoftCall?
8103 u_int beginning=(u_int)out;
8104 u_int page=get_page(start);
8105 invalid_code[start>>12]=0;
8106 emit_movimm(start,0);
8107 emit_writeword(0,(int)&pcaddr);
8108 emit_jmp((int)new_dyna_leave);
8111 __clear_cache((void *)beginning,out);
8113 ll_add(jump_in+page,start,(void *)beginning);
8116 else if ((u_int)addr < 0x00200000 ||
8117 (0xa0000000 <= addr && addr < 0xa0200000)) {
8118 // used for BIOS calls mostly?
8119 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8120 pagelimit = (addr&0xa0000000)|0x00200000;
8122 else if (!Config.HLE && (
8123 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8124 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8126 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8127 pagelimit = (addr&0xfff00000)|0x80000;
8132 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8133 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8134 pagelimit = 0xa4001000;
8138 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8139 source = (u_int *)((u_int)rdram+start-0x80000000);
8140 pagelimit = 0x80000000+RAM_SIZE;
8143 else if ((signed int)addr >= (signed int)0xC0000000) {
8144 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8145 //if(tlb_LUT_r[start>>12])
8146 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8147 if((signed int)memory_map[start>>12]>=0) {
8148 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8149 pagelimit=(start+4096)&0xFFFFF000;
8150 int map=memory_map[start>>12];
8153 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8154 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8156 assem_debug("pagelimit=%x\n",pagelimit);
8157 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8160 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8161 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8162 return -1; // Caller will invoke exception handler
8164 //printf("source= %x\n",(int)source);
8168 printf("Compile at bogus memory address: %x \n", (int)addr);
8172 /* Pass 1: disassemble */
8173 /* Pass 2: register dependencies, branch targets */
8174 /* Pass 3: register allocation */
8175 /* Pass 4: branch dependencies */
8176 /* Pass 5: pre-alloc */
8177 /* Pass 6: optimize clean/dirty state */
8178 /* Pass 7: flag 32-bit registers */
8179 /* Pass 8: assembly */
8180 /* Pass 9: linker */
8181 /* Pass 10: garbage collection / free memory */
8185 unsigned int type,op,op2;
8187 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8189 /* Pass 1 disassembly */
8191 for(i=0;!done;i++) {
8192 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8193 minimum_free_regs[i]=0;
8194 opcode[i]=op=source[i]>>26;
8197 case 0x00: strcpy(insn[i],"special"); type=NI;
8201 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8202 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8203 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8204 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8205 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8206 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8207 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8208 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8209 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8210 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8211 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8212 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8213 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8214 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8215 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8216 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8217 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8218 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8219 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8220 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8221 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8222 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8223 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8224 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8225 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8226 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8227 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8228 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8229 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8230 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8231 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8232 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8233 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8234 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8235 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8237 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8238 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8239 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8240 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8241 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8242 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8243 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8244 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8245 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8246 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8247 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8248 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8249 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8250 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8251 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8252 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8253 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8257 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8258 op2=(source[i]>>16)&0x1f;
8261 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8262 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8263 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8264 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8265 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8266 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8267 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8268 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8269 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8270 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8271 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8272 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8273 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8274 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8277 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8278 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8279 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8280 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8281 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8282 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8283 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8284 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8285 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8286 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8287 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8288 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8289 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8290 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8291 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8292 op2=(source[i]>>21)&0x1f;
8295 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8296 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8297 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8298 switch(source[i]&0x3f)
8300 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8301 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8302 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8303 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8305 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8307 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8312 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8313 op2=(source[i]>>21)&0x1f;
8316 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8317 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8318 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8319 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8320 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8321 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8322 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8323 switch((source[i]>>16)&0x3)
8325 case 0x00: strcpy(insn[i],"BC1F"); break;
8326 case 0x01: strcpy(insn[i],"BC1T"); break;
8327 case 0x02: strcpy(insn[i],"BC1FL"); break;
8328 case 0x03: strcpy(insn[i],"BC1TL"); break;
8331 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8332 switch(source[i]&0x3f)
8334 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8335 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8336 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8337 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8338 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8339 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8340 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8341 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8342 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8343 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8344 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8345 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8346 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8347 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8348 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8349 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8350 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8351 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8352 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8353 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8354 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8355 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8356 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8357 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8358 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8359 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8360 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8361 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8362 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8363 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8364 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8365 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8366 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8367 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8368 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8371 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8372 switch(source[i]&0x3f)
8374 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8375 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8376 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8377 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8378 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8379 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8380 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8381 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8382 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8383 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8384 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8385 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8386 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8387 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8388 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8389 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8390 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8391 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8392 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8393 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8394 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8395 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8396 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8397 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8398 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8399 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8400 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8401 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8402 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8403 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8404 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8405 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8406 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8407 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8408 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8411 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8412 switch(source[i]&0x3f)
8414 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8415 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8418 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8419 switch(source[i]&0x3f)
8421 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8422 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8428 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8429 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8430 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8431 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8432 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8433 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8434 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8435 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8437 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8438 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8439 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8440 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8441 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8442 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8443 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8445 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8447 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8448 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8449 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8450 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8452 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8453 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8455 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8456 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8457 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8458 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8460 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8461 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8462 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8464 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8465 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8467 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8468 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8469 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8472 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8473 op2=(source[i]>>21)&0x1f;
8475 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8476 if (gte_handlers[source[i]&0x3f]!=NULL) {
8477 if (gte_regnames[source[i]&0x3f]!=NULL)
8478 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8480 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8486 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8487 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8488 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8489 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8492 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8493 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8494 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8496 default: strcpy(insn[i],"???"); type=NI;
8497 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8502 /* Get registers/immediates */
8508 gte_rs[i]=gte_rt[i]=0;
8511 rs1[i]=(source[i]>>21)&0x1f;
8513 rt1[i]=(source[i]>>16)&0x1f;
8515 imm[i]=(short)source[i];
8519 rs1[i]=(source[i]>>21)&0x1f;
8520 rs2[i]=(source[i]>>16)&0x1f;
8523 imm[i]=(short)source[i];
8524 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8527 // LWL/LWR only load part of the register,
8528 // therefore the target register must be treated as a source too
8529 rs1[i]=(source[i]>>21)&0x1f;
8530 rs2[i]=(source[i]>>16)&0x1f;
8531 rt1[i]=(source[i]>>16)&0x1f;
8533 imm[i]=(short)source[i];
8534 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8535 if(op==0x26) dep1[i]=rt1[i]; // LWR
8538 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8539 else rs1[i]=(source[i]>>21)&0x1f;
8541 rt1[i]=(source[i]>>16)&0x1f;
8543 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8544 imm[i]=(unsigned short)source[i];
8546 imm[i]=(short)source[i];
8548 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8549 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8550 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8557 // The JAL instruction writes to r31.
8564 rs1[i]=(source[i]>>21)&0x1f;
8568 // The JALR instruction writes to rd.
8570 rt1[i]=(source[i]>>11)&0x1f;
8575 rs1[i]=(source[i]>>21)&0x1f;
8576 rs2[i]=(source[i]>>16)&0x1f;
8579 if(op&2) { // BGTZ/BLEZ
8587 rs1[i]=(source[i]>>21)&0x1f;
8592 if(op2&0x10) { // BxxAL
8594 // NOTE: If the branch is not taken, r31 is still overwritten
8596 likely[i]=(op2&2)>>1;
8603 likely[i]=((source[i])>>17)&1;
8606 rs1[i]=(source[i]>>21)&0x1f; // source
8607 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8608 rt1[i]=(source[i]>>11)&0x1f; // destination
8610 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8611 us1[i]=rs1[i];us2[i]=rs2[i];
8613 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8614 dep1[i]=rs1[i];dep2[i]=rs2[i];
8616 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8617 dep1[i]=rs1[i];dep2[i]=rs2[i];
8621 rs1[i]=(source[i]>>21)&0x1f; // source
8622 rs2[i]=(source[i]>>16)&0x1f; // divisor
8625 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8626 us1[i]=rs1[i];us2[i]=rs2[i];
8634 if(op2==0x10) rs1[i]=HIREG; // MFHI
8635 if(op2==0x11) rt1[i]=HIREG; // MTHI
8636 if(op2==0x12) rs1[i]=LOREG; // MFLO
8637 if(op2==0x13) rt1[i]=LOREG; // MTLO
8638 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8639 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8643 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8644 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8645 rt1[i]=(source[i]>>11)&0x1f; // destination
8647 // DSLLV/DSRLV/DSRAV are 64-bit
8648 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8651 rs1[i]=(source[i]>>16)&0x1f;
8653 rt1[i]=(source[i]>>11)&0x1f;
8655 imm[i]=(source[i]>>6)&0x1f;
8656 // DSxx32 instructions
8657 if(op2>=0x3c) imm[i]|=0x20;
8658 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8659 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8666 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8667 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8668 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8669 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8676 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8677 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8678 if(op2==5) us1[i]=rs1[i]; // DMTC1
8686 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8687 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8689 int gr=(source[i]>>11)&0x1F;
8692 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8693 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8694 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8695 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8699 rs1[i]=(source[i]>>21)&0x1F;
8703 imm[i]=(short)source[i];
8706 rs1[i]=(source[i]>>21)&0x1F;
8710 imm[i]=(short)source[i];
8711 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8712 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8719 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8720 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8721 gte_rt[i]|=1ll<<63; // every op changes flags
8722 if((source[i]&0x3f)==GTE_MVMVA) {
8723 int v = (source[i] >> 15) & 3;
8724 gte_rs[i]&=~0xe3fll;
8725 if(v==3) gte_rs[i]|=0xe00ll;
8726 else gte_rs[i]|=3ll<<(v*2);
8756 /* Calculate branch target addresses */
8758 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8759 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8760 ba[i]=start+i*4+8; // Ignore never taken branch
8761 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8762 ba[i]=start+i*4+8; // Ignore never taken branch
8763 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8764 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8767 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8769 // branch in delay slot?
8770 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8771 // don't handle first branch and call interpreter if it's hit
8772 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8775 // basic load delay detection
8776 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8777 int t=(ba[i-1]-start)/4;
8778 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8779 // jump target wants DS result - potential load delay effect
8780 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8782 bt[t+1]=1; // expected return from interpreter
8784 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8785 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8786 // v0 overwrite like this is a sign of trouble, bail out
8787 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8793 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8797 i--; // don't compile the DS
8801 /* Is this the end of the block? */
8802 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8803 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8807 if(stop_after_jal) done=1;
8809 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8811 // Don't recompile stuff that's already compiled
8812 if(check_addr(start+i*4+4)) done=1;
8813 // Don't get too close to the limit
8814 if(i>MAXBLOCK/2) done=1;
8816 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8817 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8819 // Does the block continue due to a branch?
8822 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8823 if(ba[j]==start+i*4+4) done=j=0;
8824 if(ba[j]==start+i*4+8) done=j=0;
8827 //assert(i<MAXBLOCK-1);
8828 if(start+i*4==pagelimit-4) done=1;
8829 assert(start+i*4<pagelimit);
8830 if (i==MAXBLOCK-1) done=1;
8831 // Stop if we're compiling junk
8832 if(itype[i]==NI&&opcode[i]==0x11) {
8833 done=stop_after_jal=1;
8834 printf("Disabled speculative precompilation\n");
8838 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8839 if(start+i*4==pagelimit) {
8845 /* Pass 2 - Register dependencies and branch targets */
8847 unneeded_registers(0,slen-1,0);
8849 /* Pass 3 - Register allocation */
8851 struct regstat current; // Current register allocations/status
8854 current.u=unneeded_reg[0];
8855 current.uu=unneeded_reg_upper[0];
8856 clear_all_regs(current.regmap);
8857 alloc_reg(¤t,0,CCREG);
8858 dirty_reg(¤t,CCREG);
8861 current.waswritten=0;
8867 provisional_32bit();
8870 // First instruction is delay slot
8875 unneeded_reg_upper[0]=1;
8876 current.regmap[HOST_BTREG]=BTREG;
8884 for(hr=0;hr<HOST_REGS;hr++)
8886 // Is this really necessary?
8887 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8890 current.waswritten=0;
8894 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8896 if(rs1[i-2]==0||rs2[i-2]==0)
8899 current.is32|=1LL<<rs1[i-2];
8900 int hr=get_reg(current.regmap,rs1[i-2]|64);
8901 if(hr>=0) current.regmap[hr]=-1;
8904 current.is32|=1LL<<rs2[i-2];
8905 int hr=get_reg(current.regmap,rs2[i-2]|64);
8906 if(hr>=0) current.regmap[hr]=-1;
8912 // If something jumps here with 64-bit values
8913 // then promote those registers to 64 bits
8916 uint64_t temp_is32=current.is32;
8919 if(ba[j]==start+i*4)
8920 temp_is32&=branch_regs[j].is32;
8924 if(ba[j]==start+i*4)
8928 if(temp_is32!=current.is32) {
8929 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8930 #ifndef DESTRUCTIVE_WRITEBACK
8933 for(hr=0;hr<HOST_REGS;hr++)
8935 int r=current.regmap[hr];
8938 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8940 //printf("restore %d\n",r);
8944 current.is32=temp_is32;
8951 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8952 regs[i].wasconst=current.isconst;
8953 regs[i].was32=current.is32;
8954 regs[i].wasdirty=current.dirty;
8955 regs[i].loadedconst=0;
8956 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8957 // To change a dirty register from 32 to 64 bits, we must write
8958 // it out during the previous cycle (for branches, 2 cycles)
8959 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8961 uint64_t temp_is32=current.is32;
8964 if(ba[j]==start+i*4+4)
8965 temp_is32&=branch_regs[j].is32;
8969 if(ba[j]==start+i*4+4)
8973 if(temp_is32!=current.is32) {
8974 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8975 for(hr=0;hr<HOST_REGS;hr++)
8977 int r=current.regmap[hr];
8980 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8981 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8983 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8985 //printf("dump %d/r%d\n",hr,r);
8986 current.regmap[hr]=-1;
8987 if(get_reg(current.regmap,r|64)>=0)
8988 current.regmap[get_reg(current.regmap,r|64)]=-1;
8996 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8998 uint64_t temp_is32=current.is32;
9001 if(ba[j]==start+i*4+8)
9002 temp_is32&=branch_regs[j].is32;
9006 if(ba[j]==start+i*4+8)
9010 if(temp_is32!=current.is32) {
9011 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
9012 for(hr=0;hr<HOST_REGS;hr++)
9014 int r=current.regmap[hr];
9017 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
9018 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
9020 //printf("dump %d/r%d\n",hr,r);
9021 current.regmap[hr]=-1;
9022 if(get_reg(current.regmap,r|64)>=0)
9023 current.regmap[get_reg(current.regmap,r|64)]=-1;
9031 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9033 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9034 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9035 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9044 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9045 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9046 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9047 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9048 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9051 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9055 ds=0; // Skip delay slot, already allocated as part of branch
9056 // ...but we need to alloc it in case something jumps here
9058 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9059 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9061 current.u=branch_unneeded_reg[i-1];
9062 current.uu=branch_unneeded_reg_upper[i-1];
9064 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9065 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9066 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9069 struct regstat temp;
9070 memcpy(&temp,¤t,sizeof(current));
9071 temp.wasdirty=temp.dirty;
9072 temp.was32=temp.is32;
9073 // TODO: Take into account unconditional branches, as below
9074 delayslot_alloc(&temp,i);
9075 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9076 regs[i].wasdirty=temp.wasdirty;
9077 regs[i].was32=temp.was32;
9078 regs[i].dirty=temp.dirty;
9079 regs[i].is32=temp.is32;
9083 // Create entry (branch target) regmap
9084 for(hr=0;hr<HOST_REGS;hr++)
9086 int r=temp.regmap[hr];
9088 if(r!=regmap_pre[i][hr]) {
9089 regs[i].regmap_entry[hr]=-1;
9094 if((current.u>>r)&1) {
9095 regs[i].regmap_entry[hr]=-1;
9096 regs[i].regmap[hr]=-1;
9097 //Don't clear regs in the delay slot as the branch might need them
9098 //current.regmap[hr]=-1;
9100 regs[i].regmap_entry[hr]=r;
9103 if((current.uu>>(r&63))&1) {
9104 regs[i].regmap_entry[hr]=-1;
9105 regs[i].regmap[hr]=-1;
9106 //Don't clear regs in the delay slot as the branch might need them
9107 //current.regmap[hr]=-1;
9109 regs[i].regmap_entry[hr]=r;
9113 // First instruction expects CCREG to be allocated
9114 if(i==0&&hr==HOST_CCREG)
9115 regs[i].regmap_entry[hr]=CCREG;
9117 regs[i].regmap_entry[hr]=-1;
9121 else { // Not delay slot
9124 //current.isconst=0; // DEBUG
9125 //current.wasconst=0; // DEBUG
9126 //regs[i].wasconst=0; // DEBUG
9127 clear_const(¤t,rt1[i]);
9128 alloc_cc(¤t,i);
9129 dirty_reg(¤t,CCREG);
9131 alloc_reg(¤t,i,31);
9132 dirty_reg(¤t,31);
9133 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9134 //assert(rt1[i+1]!=rt1[i]);
9136 alloc_reg(¤t,i,PTEMP);
9138 //current.is32|=1LL<<rt1[i];
9141 delayslot_alloc(¤t,i+1);
9142 //current.isconst=0; // DEBUG
9144 //printf("i=%d, isconst=%x\n",i,current.isconst);
9147 //current.isconst=0;
9148 //current.wasconst=0;
9149 //regs[i].wasconst=0;
9150 clear_const(¤t,rs1[i]);
9151 clear_const(¤t,rt1[i]);
9152 alloc_cc(¤t,i);
9153 dirty_reg(¤t,CCREG);
9154 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9155 alloc_reg(¤t,i,rs1[i]);
9157 alloc_reg(¤t,i,rt1[i]);
9158 dirty_reg(¤t,rt1[i]);
9159 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9160 assert(rt1[i+1]!=rt1[i]);
9162 alloc_reg(¤t,i,PTEMP);
9166 if(rs1[i]==31) { // JALR
9167 alloc_reg(¤t,i,RHASH);
9168 #ifndef HOST_IMM_ADDR32
9169 alloc_reg(¤t,i,RHTBL);
9173 delayslot_alloc(¤t,i+1);
9175 // The delay slot overwrites our source register,
9176 // allocate a temporary register to hold the old value.
9180 delayslot_alloc(¤t,i+1);
9182 alloc_reg(¤t,i,RTEMP);
9184 //current.isconst=0; // DEBUG
9189 //current.isconst=0;
9190 //current.wasconst=0;
9191 //regs[i].wasconst=0;
9192 clear_const(¤t,rs1[i]);
9193 clear_const(¤t,rs2[i]);
9194 if((opcode[i]&0x3E)==4) // BEQ/BNE
9196 alloc_cc(¤t,i);
9197 dirty_reg(¤t,CCREG);
9198 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9199 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9200 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9202 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9203 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9205 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9206 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9207 // The delay slot overwrites one of our conditions.
9208 // Allocate the branch condition registers instead.
9212 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9213 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9214 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9216 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9217 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9223 delayslot_alloc(¤t,i+1);
9227 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9229 alloc_cc(¤t,i);
9230 dirty_reg(¤t,CCREG);
9231 alloc_reg(¤t,i,rs1[i]);
9232 if(!(current.is32>>rs1[i]&1))
9234 alloc_reg64(¤t,i,rs1[i]);
9236 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9237 // The delay slot overwrites one of our conditions.
9238 // Allocate the branch condition registers instead.
9242 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9243 if(!((current.is32>>rs1[i])&1))
9245 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9251 delayslot_alloc(¤t,i+1);
9255 // Don't alloc the delay slot yet because we might not execute it
9256 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9261 alloc_cc(¤t,i);
9262 dirty_reg(¤t,CCREG);
9263 alloc_reg(¤t,i,rs1[i]);
9264 alloc_reg(¤t,i,rs2[i]);
9265 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9267 alloc_reg64(¤t,i,rs1[i]);
9268 alloc_reg64(¤t,i,rs2[i]);
9272 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9277 alloc_cc(¤t,i);
9278 dirty_reg(¤t,CCREG);
9279 alloc_reg(¤t,i,rs1[i]);
9280 if(!(current.is32>>rs1[i]&1))
9282 alloc_reg64(¤t,i,rs1[i]);
9286 //current.isconst=0;
9289 //current.isconst=0;
9290 //current.wasconst=0;
9291 //regs[i].wasconst=0;
9292 clear_const(¤t,rs1[i]);
9293 clear_const(¤t,rt1[i]);
9294 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9295 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9297 alloc_cc(¤t,i);
9298 dirty_reg(¤t,CCREG);
9299 alloc_reg(¤t,i,rs1[i]);
9300 if(!(current.is32>>rs1[i]&1))
9302 alloc_reg64(¤t,i,rs1[i]);
9304 if (rt1[i]==31) { // BLTZAL/BGEZAL
9305 alloc_reg(¤t,i,31);
9306 dirty_reg(¤t,31);
9307 //#ifdef REG_PREFETCH
9308 //alloc_reg(¤t,i,PTEMP);
9310 //current.is32|=1LL<<rt1[i];
9312 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9313 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9314 // Allocate the branch condition registers instead.
9318 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9319 if(!((current.is32>>rs1[i])&1))
9321 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9327 delayslot_alloc(¤t,i+1);
9331 // Don't alloc the delay slot yet because we might not execute it
9332 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9337 alloc_cc(¤t,i);
9338 dirty_reg(¤t,CCREG);
9339 alloc_reg(¤t,i,rs1[i]);
9340 if(!(current.is32>>rs1[i]&1))
9342 alloc_reg64(¤t,i,rs1[i]);
9346 //current.isconst=0;
9352 if(likely[i]==0) // BC1F/BC1T
9354 // TODO: Theoretically we can run out of registers here on x86.
9355 // The delay slot can allocate up to six, and we need to check
9356 // CSREG before executing the delay slot. Possibly we can drop
9357 // the cycle count and then reload it after checking that the
9358 // FPU is in a usable state, or don't do out-of-order execution.
9359 alloc_cc(¤t,i);
9360 dirty_reg(¤t,CCREG);
9361 alloc_reg(¤t,i,FSREG);
9362 alloc_reg(¤t,i,CSREG);
9363 if(itype[i+1]==FCOMP) {
9364 // The delay slot overwrites the branch condition.
9365 // Allocate the branch condition registers instead.
9366 alloc_cc(¤t,i);
9367 dirty_reg(¤t,CCREG);
9368 alloc_reg(¤t,i,CSREG);
9369 alloc_reg(¤t,i,FSREG);
9373 delayslot_alloc(¤t,i+1);
9374 alloc_reg(¤t,i+1,CSREG);
9378 // Don't alloc the delay slot yet because we might not execute it
9379 if(likely[i]) // BC1FL/BC1TL
9381 alloc_cc(¤t,i);
9382 dirty_reg(¤t,CCREG);
9383 alloc_reg(¤t,i,CSREG);
9384 alloc_reg(¤t,i,FSREG);
9390 imm16_alloc(¤t,i);
9394 load_alloc(¤t,i);
9398 store_alloc(¤t,i);
9401 alu_alloc(¤t,i);
9404 shift_alloc(¤t,i);
9407 multdiv_alloc(¤t,i);
9410 shiftimm_alloc(¤t,i);
9413 mov_alloc(¤t,i);
9416 cop0_alloc(¤t,i);
9420 cop1_alloc(¤t,i);
9423 c1ls_alloc(¤t,i);
9426 c2ls_alloc(¤t,i);
9429 c2op_alloc(¤t,i);
9432 fconv_alloc(¤t,i);
9435 float_alloc(¤t,i);
9438 fcomp_alloc(¤t,i);
9443 syscall_alloc(¤t,i);
9446 pagespan_alloc(¤t,i);
9450 // Drop the upper half of registers that have become 32-bit
9451 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9452 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9453 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9454 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9457 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9458 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9459 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9460 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9464 // Create entry (branch target) regmap
9465 for(hr=0;hr<HOST_REGS;hr++)
9468 r=current.regmap[hr];
9470 if(r!=regmap_pre[i][hr]) {
9471 // TODO: delay slot (?)
9472 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9473 if(or<0||(r&63)>=TEMPREG){
9474 regs[i].regmap_entry[hr]=-1;
9478 // Just move it to a different register
9479 regs[i].regmap_entry[hr]=r;
9480 // If it was dirty before, it's still dirty
9481 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9488 regs[i].regmap_entry[hr]=0;
9492 if((current.u>>r)&1) {
9493 regs[i].regmap_entry[hr]=-1;
9494 //regs[i].regmap[hr]=-1;
9495 current.regmap[hr]=-1;
9497 regs[i].regmap_entry[hr]=r;
9500 if((current.uu>>(r&63))&1) {
9501 regs[i].regmap_entry[hr]=-1;
9502 //regs[i].regmap[hr]=-1;
9503 current.regmap[hr]=-1;
9505 regs[i].regmap_entry[hr]=r;
9509 // Branches expect CCREG to be allocated at the target
9510 if(regmap_pre[i][hr]==CCREG)
9511 regs[i].regmap_entry[hr]=CCREG;
9513 regs[i].regmap_entry[hr]=-1;
9516 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9519 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9520 current.waswritten|=1<<rs1[i-1];
9521 current.waswritten&=~(1<<rt1[i]);
9522 current.waswritten&=~(1<<rt2[i]);
9523 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9524 current.waswritten&=~(1<<rs1[i]);
9526 /* Branch post-alloc */
9529 current.was32=current.is32;
9530 current.wasdirty=current.dirty;
9531 switch(itype[i-1]) {
9533 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9534 branch_regs[i-1].isconst=0;
9535 branch_regs[i-1].wasconst=0;
9536 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9537 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9538 alloc_cc(&branch_regs[i-1],i-1);
9539 dirty_reg(&branch_regs[i-1],CCREG);
9540 if(rt1[i-1]==31) { // JAL
9541 alloc_reg(&branch_regs[i-1],i-1,31);
9542 dirty_reg(&branch_regs[i-1],31);
9543 branch_regs[i-1].is32|=1LL<<31;
9545 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9546 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9549 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9550 branch_regs[i-1].isconst=0;
9551 branch_regs[i-1].wasconst=0;
9552 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9553 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9554 alloc_cc(&branch_regs[i-1],i-1);
9555 dirty_reg(&branch_regs[i-1],CCREG);
9556 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9557 if(rt1[i-1]!=0) { // JALR
9558 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9559 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9560 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9563 if(rs1[i-1]==31) { // JALR
9564 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9565 #ifndef HOST_IMM_ADDR32
9566 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9570 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9571 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9574 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9576 alloc_cc(¤t,i-1);
9577 dirty_reg(¤t,CCREG);
9578 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9579 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9580 // The delay slot overwrote one of our conditions
9581 // Delay slot goes after the test (in order)
9582 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9583 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9584 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9587 delayslot_alloc(¤t,i);
9592 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9593 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9594 // Alloc the branch condition registers
9595 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9596 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9597 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9599 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9600 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9603 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9604 branch_regs[i-1].isconst=0;
9605 branch_regs[i-1].wasconst=0;
9606 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9607 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9610 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9612 alloc_cc(¤t,i-1);
9613 dirty_reg(¤t,CCREG);
9614 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9615 // The delay slot overwrote the branch condition
9616 // Delay slot goes after the test (in order)
9617 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9618 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9619 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9622 delayslot_alloc(¤t,i);
9627 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9628 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9629 // Alloc the branch condition register
9630 alloc_reg(¤t,i-1,rs1[i-1]);
9631 if(!(current.is32>>rs1[i-1]&1))
9633 alloc_reg64(¤t,i-1,rs1[i-1]);
9636 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9637 branch_regs[i-1].isconst=0;
9638 branch_regs[i-1].wasconst=0;
9639 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9640 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9643 // Alloc the delay slot in case the branch is taken
9644 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9646 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9647 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9648 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9649 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9650 alloc_cc(&branch_regs[i-1],i);
9651 dirty_reg(&branch_regs[i-1],CCREG);
9652 delayslot_alloc(&branch_regs[i-1],i);
9653 branch_regs[i-1].isconst=0;
9654 alloc_reg(¤t,i,CCREG); // Not taken path
9655 dirty_reg(¤t,CCREG);
9656 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9659 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9661 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9662 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9663 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9664 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9665 alloc_cc(&branch_regs[i-1],i);
9666 dirty_reg(&branch_regs[i-1],CCREG);
9667 delayslot_alloc(&branch_regs[i-1],i);
9668 branch_regs[i-1].isconst=0;
9669 alloc_reg(¤t,i,CCREG); // Not taken path
9670 dirty_reg(¤t,CCREG);
9671 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9675 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9676 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9678 alloc_cc(¤t,i-1);
9679 dirty_reg(¤t,CCREG);
9680 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9681 // The delay slot overwrote the branch condition
9682 // Delay slot goes after the test (in order)
9683 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9684 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9685 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9688 delayslot_alloc(¤t,i);
9693 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9694 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9695 // Alloc the branch condition register
9696 alloc_reg(¤t,i-1,rs1[i-1]);
9697 if(!(current.is32>>rs1[i-1]&1))
9699 alloc_reg64(¤t,i-1,rs1[i-1]);
9702 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9703 branch_regs[i-1].isconst=0;
9704 branch_regs[i-1].wasconst=0;
9705 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9706 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
9709 // Alloc the delay slot in case the branch is taken
9710 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9712 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9713 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9714 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9715 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9716 alloc_cc(&branch_regs[i-1],i);
9717 dirty_reg(&branch_regs[i-1],CCREG);
9718 delayslot_alloc(&branch_regs[i-1],i);
9719 branch_regs[i-1].isconst=0;
9720 alloc_reg(¤t,i,CCREG); // Not taken path
9721 dirty_reg(¤t,CCREG);
9722 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9724 // FIXME: BLTZAL/BGEZAL
9725 if(opcode2[i-1]&0x10) { // BxxZAL
9726 alloc_reg(&branch_regs[i-1],i-1,31);
9727 dirty_reg(&branch_regs[i-1],31);
9728 branch_regs[i-1].is32|=1LL<<31;
9732 if(likely[i-1]==0) // BC1F/BC1T
9734 alloc_cc(¤t,i-1);
9735 dirty_reg(¤t,CCREG);
9736 if(itype[i]==FCOMP) {
9737 // The delay slot overwrote the branch condition
9738 // Delay slot goes after the test (in order)
9739 delayslot_alloc(¤t,i);
9744 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9745 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9746 // Alloc the branch condition register
9747 alloc_reg(¤t,i-1,FSREG);
9749 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9750 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9754 // Alloc the delay slot in case the branch is taken
9755 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9756 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9757 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9758 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9759 alloc_cc(&branch_regs[i-1],i);
9760 dirty_reg(&branch_regs[i-1],CCREG);
9761 delayslot_alloc(&branch_regs[i-1],i);
9762 branch_regs[i-1].isconst=0;
9763 alloc_reg(¤t,i,CCREG); // Not taken path
9764 dirty_reg(¤t,CCREG);
9765 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9770 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9772 if(rt1[i-1]==31) // JAL/JALR
9774 // Subroutine call will return here, don't alloc any registers
9777 clear_all_regs(current.regmap);
9778 alloc_reg(¤t,i,CCREG);
9779 dirty_reg(¤t,CCREG);
9783 // Internal branch will jump here, match registers to caller
9784 current.is32=0x3FFFFFFFFLL;
9786 clear_all_regs(current.regmap);
9787 alloc_reg(¤t,i,CCREG);
9788 dirty_reg(¤t,CCREG);
9791 if(ba[j]==start+i*4+4) {
9792 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9793 current.is32=branch_regs[j].is32;
9794 current.dirty=branch_regs[j].dirty;
9799 if(ba[j]==start+i*4+4) {
9800 for(hr=0;hr<HOST_REGS;hr++) {
9801 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9802 current.regmap[hr]=-1;
9804 current.is32&=branch_regs[j].is32;
9805 current.dirty&=branch_regs[j].dirty;
9814 // Count cycles in between branches
9816 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9820 #if defined(PCSX) && !defined(DRC_DBG)
9821 else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
9823 // GTE runs in parallel until accessed, divide by 2 for a rough guess
9824 cc+=gte_cycletab[source[i]&0x3f]/2;
9826 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9828 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9830 else if(itype[i]==C2LS)
9840 flush_dirty_uppers(¤t);
9842 regs[i].is32=current.is32;
9843 regs[i].dirty=current.dirty;
9844 regs[i].isconst=current.isconst;
9845 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
9847 for(hr=0;hr<HOST_REGS;hr++) {
9848 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9849 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9850 regs[i].wasconst&=~(1<<hr);
9854 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9855 regs[i].waswritten=current.waswritten;
9858 /* Pass 4 - Cull unused host registers */
9862 for (i=slen-1;i>=0;i--)
9865 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9867 if(ba[i]<start || ba[i]>=(start+slen*4))
9869 // Branch out of this block, don't need anything
9875 // Need whatever matches the target
9877 int t=(ba[i]-start)>>2;
9878 for(hr=0;hr<HOST_REGS;hr++)
9880 if(regs[i].regmap_entry[hr]>=0) {
9881 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9885 // Conditional branch may need registers for following instructions
9886 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9889 nr|=needed_reg[i+2];
9890 for(hr=0;hr<HOST_REGS;hr++)
9892 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9893 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9897 // Don't need stuff which is overwritten
9898 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9899 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9900 // Merge in delay slot
9901 for(hr=0;hr<HOST_REGS;hr++)
9904 // These are overwritten unless the branch is "likely"
9905 // and the delay slot is nullified if not taken
9906 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9907 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9909 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9910 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9911 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9912 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9913 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9914 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9915 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9916 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9917 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9918 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9919 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9921 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9922 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9923 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9925 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9926 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9927 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9931 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9933 // SYSCALL instruction (software interrupt)
9936 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9938 // ERET instruction (return from interrupt)
9944 for(hr=0;hr<HOST_REGS;hr++) {
9945 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9946 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9947 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9948 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9952 for(hr=0;hr<HOST_REGS;hr++)
9954 // Overwritten registers are not needed
9955 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9956 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9957 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9958 // Source registers are needed
9959 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9960 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9961 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9962 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9963 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9964 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9965 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9966 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9967 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9968 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9969 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9971 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9972 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9973 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9975 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9976 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9977 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9979 // Don't store a register immediately after writing it,
9980 // may prevent dual-issue.
9981 // But do so if this is a branch target, otherwise we
9982 // might have to load the register before the branch.
9983 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9984 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9985 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9986 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9987 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9989 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9990 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9991 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9992 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9996 // Cycle count is needed at branches. Assume it is needed at the target too.
9997 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9998 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9999 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
10004 // Deallocate unneeded registers
10005 for(hr=0;hr<HOST_REGS;hr++)
10007 if(!((nr>>hr)&1)) {
10008 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
10009 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10010 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10011 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
10013 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10016 regs[i].regmap[hr]=-1;
10017 regs[i].isconst&=~(1<<hr);
10019 regmap_pre[i+2][hr]=-1;
10020 regs[i+2].wasconst&=~(1<<hr);
10025 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10027 int d1=0,d2=0,map=0,temp=0;
10028 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10034 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10035 itype[i+1]==STORE || itype[i+1]==STORELR ||
10036 itype[i+1]==C1LS || itype[i+1]==C2LS)
10039 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10040 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10043 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10044 itype[i+1]==C1LS || itype[i+1]==C2LS)
10046 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10047 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10048 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10049 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10050 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10051 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10052 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10053 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10054 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10055 regs[i].regmap[hr]!=map )
10057 regs[i].regmap[hr]=-1;
10058 regs[i].isconst&=~(1<<hr);
10059 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10060 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10061 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10062 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10063 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10064 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10065 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10066 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10067 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10068 branch_regs[i].regmap[hr]!=map)
10070 branch_regs[i].regmap[hr]=-1;
10071 branch_regs[i].regmap_entry[hr]=-1;
10072 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10074 if(!likely[i]&&i<slen-2) {
10075 regmap_pre[i+2][hr]=-1;
10076 regs[i+2].wasconst&=~(1<<hr);
10087 int d1=0,d2=0,map=-1,temp=-1;
10088 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10094 if(itype[i]==LOAD || itype[i]==LOADLR ||
10095 itype[i]==STORE || itype[i]==STORELR ||
10096 itype[i]==C1LS || itype[i]==C2LS)
10098 } else if(itype[i]==STORE || itype[i]==STORELR ||
10099 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10102 if(itype[i]==LOADLR || itype[i]==STORELR ||
10103 itype[i]==C1LS || itype[i]==C2LS)
10105 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10106 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10107 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10108 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10109 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10110 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10112 if(i<slen-1&&!is_ds[i]) {
10113 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10114 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10115 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10117 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10118 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10120 regmap_pre[i+1][hr]=-1;
10121 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10122 regs[i+1].wasconst&=~(1<<hr);
10124 regs[i].regmap[hr]=-1;
10125 regs[i].isconst&=~(1<<hr);
10133 /* Pass 5 - Pre-allocate registers */
10135 // If a register is allocated during a loop, try to allocate it for the
10136 // entire loop, if possible. This avoids loading/storing registers
10137 // inside of the loop.
10139 signed char f_regmap[HOST_REGS];
10140 clear_all_regs(f_regmap);
10141 for(i=0;i<slen-1;i++)
10143 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10145 if(ba[i]>=start && ba[i]<(start+i*4))
10146 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10147 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10148 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10149 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10150 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10151 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10153 int t=(ba[i]-start)>>2;
10154 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10155 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10156 for(hr=0;hr<HOST_REGS;hr++)
10158 if(regs[i].regmap[hr]>64) {
10159 if(!((regs[i].dirty>>hr)&1))
10160 f_regmap[hr]=regs[i].regmap[hr];
10161 else f_regmap[hr]=-1;
10163 else if(regs[i].regmap[hr]>=0) {
10164 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10165 // dealloc old register
10167 for(n=0;n<HOST_REGS;n++)
10169 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10171 // and alloc new one
10172 f_regmap[hr]=regs[i].regmap[hr];
10175 if(branch_regs[i].regmap[hr]>64) {
10176 if(!((branch_regs[i].dirty>>hr)&1))
10177 f_regmap[hr]=branch_regs[i].regmap[hr];
10178 else f_regmap[hr]=-1;
10180 else if(branch_regs[i].regmap[hr]>=0) {
10181 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10182 // dealloc old register
10184 for(n=0;n<HOST_REGS;n++)
10186 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10188 // and alloc new one
10189 f_regmap[hr]=branch_regs[i].regmap[hr];
10193 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10194 f_regmap[hr]=branch_regs[i].regmap[hr];
10196 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10197 f_regmap[hr]=branch_regs[i].regmap[hr];
10199 // Avoid dirty->clean transition
10200 #ifdef DESTRUCTIVE_WRITEBACK
10201 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10203 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10204 // case above, however it's always a good idea. We can't hoist the
10205 // load if the register was already allocated, so there's no point
10206 // wasting time analyzing most of these cases. It only "succeeds"
10207 // when the mapping was different and the load can be replaced with
10208 // a mov, which is of negligible benefit. So such cases are
10210 if(f_regmap[hr]>0) {
10211 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10212 int r=f_regmap[hr];
10215 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10216 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10217 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10219 // NB This can exclude the case where the upper-half
10220 // register is lower numbered than the lower-half
10221 // register. Not sure if it's worth fixing...
10222 if(get_reg(regs[j].regmap,r&63)<0) break;
10223 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10224 if(regs[j].is32&(1LL<<(r&63))) break;
10226 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10227 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10229 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10230 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10232 if(get_reg(regs[i].regmap,r&63)<0) break;
10233 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10236 while(k>1&®s[k-1].regmap[hr]==-1) {
10237 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10238 //printf("no free regs for store %x\n",start+(k-1)*4);
10241 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10242 //printf("no-match due to different register\n");
10245 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10246 //printf("no-match due to branch\n");
10249 // call/ret fast path assumes no registers allocated
10250 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10254 // NB This can exclude the case where the upper-half
10255 // register is lower numbered than the lower-half
10256 // register. Not sure if it's worth fixing...
10257 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10258 if(regs[k-1].is32&(1LL<<(r&63))) break;
10263 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10264 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10265 //printf("bad match after branch\n");
10269 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10270 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10272 regs[k].regmap_entry[hr]=f_regmap[hr];
10273 regs[k].regmap[hr]=f_regmap[hr];
10274 regmap_pre[k+1][hr]=f_regmap[hr];
10275 regs[k].wasdirty&=~(1<<hr);
10276 regs[k].dirty&=~(1<<hr);
10277 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10278 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10279 regs[k].wasconst&=~(1<<hr);
10280 regs[k].isconst&=~(1<<hr);
10285 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10288 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10289 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10290 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10291 regs[i].regmap_entry[hr]=f_regmap[hr];
10292 regs[i].regmap[hr]=f_regmap[hr];
10293 regs[i].wasdirty&=~(1<<hr);
10294 regs[i].dirty&=~(1<<hr);
10295 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10296 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10297 regs[i].wasconst&=~(1<<hr);
10298 regs[i].isconst&=~(1<<hr);
10299 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10300 branch_regs[i].wasdirty&=~(1<<hr);
10301 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10302 branch_regs[i].regmap[hr]=f_regmap[hr];
10303 branch_regs[i].dirty&=~(1<<hr);
10304 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10305 branch_regs[i].wasconst&=~(1<<hr);
10306 branch_regs[i].isconst&=~(1<<hr);
10307 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10308 regmap_pre[i+2][hr]=f_regmap[hr];
10309 regs[i+2].wasdirty&=~(1<<hr);
10310 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10311 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10312 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10317 // Alloc register clean at beginning of loop,
10318 // but may dirty it in pass 6
10319 regs[k].regmap_entry[hr]=f_regmap[hr];
10320 regs[k].regmap[hr]=f_regmap[hr];
10321 regs[k].dirty&=~(1<<hr);
10322 regs[k].wasconst&=~(1<<hr);
10323 regs[k].isconst&=~(1<<hr);
10324 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10325 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10326 branch_regs[k].regmap[hr]=f_regmap[hr];
10327 branch_regs[k].dirty&=~(1<<hr);
10328 branch_regs[k].wasconst&=~(1<<hr);
10329 branch_regs[k].isconst&=~(1<<hr);
10330 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10331 regmap_pre[k+2][hr]=f_regmap[hr];
10332 regs[k+2].wasdirty&=~(1<<hr);
10333 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10334 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10339 regmap_pre[k+1][hr]=f_regmap[hr];
10340 regs[k+1].wasdirty&=~(1<<hr);
10343 if(regs[j].regmap[hr]==f_regmap[hr])
10344 regs[j].regmap_entry[hr]=f_regmap[hr];
10348 if(regs[j].regmap[hr]>=0)
10350 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10351 //printf("no-match due to different register\n");
10354 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10355 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10358 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10360 // Stop on unconditional branch
10363 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10366 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10369 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10372 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10373 //printf("no-match due to different register (branch)\n");
10377 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10378 //printf("No free regs for store %x\n",start+j*4);
10381 if(f_regmap[hr]>=64) {
10382 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10387 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10398 // Non branch or undetermined branch target
10399 for(hr=0;hr<HOST_REGS;hr++)
10401 if(hr!=EXCLUDE_REG) {
10402 if(regs[i].regmap[hr]>64) {
10403 if(!((regs[i].dirty>>hr)&1))
10404 f_regmap[hr]=regs[i].regmap[hr];
10406 else if(regs[i].regmap[hr]>=0) {
10407 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10408 // dealloc old register
10410 for(n=0;n<HOST_REGS;n++)
10412 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10414 // and alloc new one
10415 f_regmap[hr]=regs[i].regmap[hr];
10420 // Try to restore cycle count at branch targets
10422 for(j=i;j<slen-1;j++) {
10423 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10424 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10425 //printf("no free regs for store %x\n",start+j*4);
10429 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10431 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10433 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10434 regs[k].regmap[HOST_CCREG]=CCREG;
10435 regmap_pre[k+1][HOST_CCREG]=CCREG;
10436 regs[k+1].wasdirty|=1<<HOST_CCREG;
10437 regs[k].dirty|=1<<HOST_CCREG;
10438 regs[k].wasconst&=~(1<<HOST_CCREG);
10439 regs[k].isconst&=~(1<<HOST_CCREG);
10442 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10444 // Work backwards from the branch target
10445 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10447 //printf("Extend backwards\n");
10450 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10451 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10452 //printf("no free regs for store %x\n",start+(k-1)*4);
10457 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10458 //printf("Extend CC, %x ->\n",start+k*4);
10460 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10461 regs[k].regmap[HOST_CCREG]=CCREG;
10462 regmap_pre[k+1][HOST_CCREG]=CCREG;
10463 regs[k+1].wasdirty|=1<<HOST_CCREG;
10464 regs[k].dirty|=1<<HOST_CCREG;
10465 regs[k].wasconst&=~(1<<HOST_CCREG);
10466 regs[k].isconst&=~(1<<HOST_CCREG);
10471 //printf("Fail Extend CC, %x ->\n",start+k*4);
10475 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10476 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10477 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10478 itype[i]!=FCONV&&itype[i]!=FCOMP)
10480 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10485 // Cache memory offset or tlb map pointer if a register is available
10486 #ifndef HOST_IMM_ADDR32
10491 int earliest_available[HOST_REGS];
10492 int loop_start[HOST_REGS];
10493 int score[HOST_REGS];
10494 int end[HOST_REGS];
10495 int reg=using_tlb?MMREG:ROREG;
10498 for(hr=0;hr<HOST_REGS;hr++) {
10499 score[hr]=0;earliest_available[hr]=0;
10500 loop_start[hr]=MAXBLOCK;
10502 for(i=0;i<slen-1;i++)
10504 // Can't do anything if no registers are available
10505 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10506 for(hr=0;hr<HOST_REGS;hr++) {
10507 score[hr]=0;earliest_available[hr]=i+1;
10508 loop_start[hr]=MAXBLOCK;
10511 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10513 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10514 for(hr=0;hr<HOST_REGS;hr++) {
10515 score[hr]=0;earliest_available[hr]=i+1;
10516 loop_start[hr]=MAXBLOCK;
10520 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10521 for(hr=0;hr<HOST_REGS;hr++) {
10522 score[hr]=0;earliest_available[hr]=i+1;
10523 loop_start[hr]=MAXBLOCK;
10528 // Mark unavailable registers
10529 for(hr=0;hr<HOST_REGS;hr++) {
10530 if(regs[i].regmap[hr]>=0) {
10531 score[hr]=0;earliest_available[hr]=i+1;
10532 loop_start[hr]=MAXBLOCK;
10534 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10535 if(branch_regs[i].regmap[hr]>=0) {
10536 score[hr]=0;earliest_available[hr]=i+2;
10537 loop_start[hr]=MAXBLOCK;
10541 // No register allocations after unconditional jumps
10542 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10544 for(hr=0;hr<HOST_REGS;hr++) {
10545 score[hr]=0;earliest_available[hr]=i+2;
10546 loop_start[hr]=MAXBLOCK;
10548 i++; // Skip delay slot too
10549 //printf("skip delay slot: %x\n",start+i*4);
10553 if(itype[i]==LOAD||itype[i]==LOADLR||
10554 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10555 for(hr=0;hr<HOST_REGS;hr++) {
10556 if(hr!=EXCLUDE_REG) {
10558 for(j=i;j<slen-1;j++) {
10559 if(regs[j].regmap[hr]>=0) break;
10560 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10561 if(branch_regs[j].regmap[hr]>=0) break;
10563 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10565 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10568 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10569 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10570 int t=(ba[j]-start)>>2;
10571 if(t<j&&t>=earliest_available[hr]) {
10572 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10573 // Score a point for hoisting loop invariant
10574 if(t<loop_start[hr]) loop_start[hr]=t;
10575 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10581 if(regs[t].regmap[hr]==reg) {
10582 // Score a point if the branch target matches this register
10587 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10588 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10593 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10595 // Stop on unconditional branch
10599 if(itype[j]==LOAD||itype[j]==LOADLR||
10600 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10607 // Find highest score and allocate that register
10609 for(hr=0;hr<HOST_REGS;hr++) {
10610 if(hr!=EXCLUDE_REG) {
10611 if(score[hr]>score[maxscore]) {
10613 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10617 if(score[maxscore]>1)
10619 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10620 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10621 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10622 assert(regs[j].regmap[maxscore]<0);
10623 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10624 regs[j].regmap[maxscore]=reg;
10625 regs[j].dirty&=~(1<<maxscore);
10626 regs[j].wasconst&=~(1<<maxscore);
10627 regs[j].isconst&=~(1<<maxscore);
10628 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10629 branch_regs[j].regmap[maxscore]=reg;
10630 branch_regs[j].wasdirty&=~(1<<maxscore);
10631 branch_regs[j].dirty&=~(1<<maxscore);
10632 branch_regs[j].wasconst&=~(1<<maxscore);
10633 branch_regs[j].isconst&=~(1<<maxscore);
10634 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10635 regmap_pre[j+2][maxscore]=reg;
10636 regs[j+2].wasdirty&=~(1<<maxscore);
10638 // loop optimization (loop_preload)
10639 int t=(ba[j]-start)>>2;
10640 if(t==loop_start[maxscore]) {
10641 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10642 regs[t].regmap_entry[maxscore]=reg;
10647 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10648 regmap_pre[j+1][maxscore]=reg;
10649 regs[j+1].wasdirty&=~(1<<maxscore);
10654 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10655 for(hr=0;hr<HOST_REGS;hr++) {
10656 score[hr]=0;earliest_available[hr]=i+i;
10657 loop_start[hr]=MAXBLOCK;
10665 // This allocates registers (if possible) one instruction prior
10666 // to use, which can avoid a load-use penalty on certain CPUs.
10667 for(i=0;i<slen-1;i++)
10669 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10673 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10674 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10677 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10679 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10681 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10682 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10683 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10684 regs[i].isconst&=~(1<<hr);
10685 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10686 constmap[i][hr]=constmap[i+1][hr];
10687 regs[i+1].wasdirty&=~(1<<hr);
10688 regs[i].dirty&=~(1<<hr);
10693 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10695 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10697 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10698 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10699 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10700 regs[i].isconst&=~(1<<hr);
10701 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10702 constmap[i][hr]=constmap[i+1][hr];
10703 regs[i+1].wasdirty&=~(1<<hr);
10704 regs[i].dirty&=~(1<<hr);
10708 // Preload target address for load instruction (non-constant)
10709 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10710 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10712 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10714 regs[i].regmap[hr]=rs1[i+1];
10715 regmap_pre[i+1][hr]=rs1[i+1];
10716 regs[i+1].regmap_entry[hr]=rs1[i+1];
10717 regs[i].isconst&=~(1<<hr);
10718 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10719 constmap[i][hr]=constmap[i+1][hr];
10720 regs[i+1].wasdirty&=~(1<<hr);
10721 regs[i].dirty&=~(1<<hr);
10725 // Load source into target register
10726 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10727 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10729 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10731 regs[i].regmap[hr]=rs1[i+1];
10732 regmap_pre[i+1][hr]=rs1[i+1];
10733 regs[i+1].regmap_entry[hr]=rs1[i+1];
10734 regs[i].isconst&=~(1<<hr);
10735 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10736 constmap[i][hr]=constmap[i+1][hr];
10737 regs[i+1].wasdirty&=~(1<<hr);
10738 regs[i].dirty&=~(1<<hr);
10742 // Preload map address
10743 #ifndef HOST_IMM_ADDR32
10744 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10745 hr=get_reg(regs[i+1].regmap,TLREG);
10747 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10748 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10750 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10752 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10753 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10754 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10755 regs[i].isconst&=~(1<<hr);
10756 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10757 constmap[i][hr]=constmap[i+1][hr];
10758 regs[i+1].wasdirty&=~(1<<hr);
10759 regs[i].dirty&=~(1<<hr);
10761 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10763 // move it to another register
10764 regs[i+1].regmap[hr]=-1;
10765 regmap_pre[i+2][hr]=-1;
10766 regs[i+1].regmap[nr]=TLREG;
10767 regmap_pre[i+2][nr]=TLREG;
10768 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10769 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10770 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10771 regs[i].isconst&=~(1<<nr);
10772 regs[i+1].isconst&=~(1<<nr);
10773 regs[i].dirty&=~(1<<nr);
10774 regs[i+1].wasdirty&=~(1<<nr);
10775 regs[i+1].dirty&=~(1<<nr);
10776 regs[i+2].wasdirty&=~(1<<nr);
10782 // Address for store instruction (non-constant)
10783 if(itype[i+1]==STORE||itype[i+1]==STORELR
10784 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10785 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10786 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10787 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10788 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10790 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10792 regs[i].regmap[hr]=rs1[i+1];
10793 regmap_pre[i+1][hr]=rs1[i+1];
10794 regs[i+1].regmap_entry[hr]=rs1[i+1];
10795 regs[i].isconst&=~(1<<hr);
10796 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10797 constmap[i][hr]=constmap[i+1][hr];
10798 regs[i+1].wasdirty&=~(1<<hr);
10799 regs[i].dirty&=~(1<<hr);
10803 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10804 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10806 hr=get_reg(regs[i+1].regmap,FTEMP);
10808 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10810 regs[i].regmap[hr]=rs1[i+1];
10811 regmap_pre[i+1][hr]=rs1[i+1];
10812 regs[i+1].regmap_entry[hr]=rs1[i+1];
10813 regs[i].isconst&=~(1<<hr);
10814 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10815 constmap[i][hr]=constmap[i+1][hr];
10816 regs[i+1].wasdirty&=~(1<<hr);
10817 regs[i].dirty&=~(1<<hr);
10819 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10821 // move it to another register
10822 regs[i+1].regmap[hr]=-1;
10823 regmap_pre[i+2][hr]=-1;
10824 regs[i+1].regmap[nr]=FTEMP;
10825 regmap_pre[i+2][nr]=FTEMP;
10826 regs[i].regmap[nr]=rs1[i+1];
10827 regmap_pre[i+1][nr]=rs1[i+1];
10828 regs[i+1].regmap_entry[nr]=rs1[i+1];
10829 regs[i].isconst&=~(1<<nr);
10830 regs[i+1].isconst&=~(1<<nr);
10831 regs[i].dirty&=~(1<<nr);
10832 regs[i+1].wasdirty&=~(1<<nr);
10833 regs[i+1].dirty&=~(1<<nr);
10834 regs[i+2].wasdirty&=~(1<<nr);
10838 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10839 if(itype[i+1]==LOAD)
10840 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10841 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10842 hr=get_reg(regs[i+1].regmap,FTEMP);
10843 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10844 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10845 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10847 if(hr>=0&®s[i].regmap[hr]<0) {
10848 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10849 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10850 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10851 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10852 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10853 regs[i].isconst&=~(1<<hr);
10854 regs[i+1].wasdirty&=~(1<<hr);
10855 regs[i].dirty&=~(1<<hr);
10864 /* Pass 6 - Optimize clean/dirty state */
10865 clean_registers(0,slen-1,1);
10867 /* Pass 7 - Identify 32-bit registers */
10873 for (i=slen-1;i>=0;i--)
10876 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10878 if(ba[i]<start || ba[i]>=(start+slen*4))
10880 // Branch out of this block, don't need anything
10886 // Need whatever matches the target
10887 // (and doesn't get overwritten by the delay slot instruction)
10889 int t=(ba[i]-start)>>2;
10890 if(ba[i]>start+i*4) {
10892 if(!(requires_32bit[t]&~regs[i].was32))
10893 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10896 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10897 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10898 if(!(pr32[t]&~regs[i].was32))
10899 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10902 // Conditional branch may need registers for following instructions
10903 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10906 r32|=requires_32bit[i+2];
10907 r32&=regs[i].was32;
10908 // Mark this address as a branch target since it may be called
10909 // upon return from interrupt
10913 // Merge in delay slot
10915 // These are overwritten unless the branch is "likely"
10916 // and the delay slot is nullified if not taken
10917 r32&=~(1LL<<rt1[i+1]);
10918 r32&=~(1LL<<rt2[i+1]);
10920 // Assume these are needed (delay slot)
10923 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10927 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10929 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10931 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10933 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10935 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10938 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10940 // SYSCALL instruction (software interrupt)
10943 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10945 // ERET instruction (return from interrupt)
10949 r32&=~(1LL<<rt1[i]);
10950 r32&=~(1LL<<rt2[i]);
10953 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10957 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10959 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10961 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10963 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10965 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10967 requires_32bit[i]=r32;
10969 // Dirty registers which are 32-bit, require 32-bit input
10970 // as they will be written as 32-bit values
10971 for(hr=0;hr<HOST_REGS;hr++)
10973 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10974 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10975 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10976 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10980 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10983 for (i=slen-1;i>=0;i--)
10985 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10987 // Conditional branch
10988 if((source[i]>>16)!=0x1000&&i<slen-2) {
10989 // Mark this address as a branch target since it may be called
10990 // upon return from interrupt
10997 if(itype[slen-1]==SPAN) {
10998 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
11002 /* Debug/disassembly */
11003 for(i=0;i<slen;i++)
11007 for(r=1;r<=CCREG;r++) {
11008 if((unneeded_reg[i]>>r)&1) {
11009 if(r==HIREG) printf(" HI");
11010 else if(r==LOREG) printf(" LO");
11011 else printf(" r%d",r);
11016 for(r=1;r<=CCREG;r++) {
11017 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
11018 if(r==HIREG) printf(" HI");
11019 else if(r==LOREG) printf(" LO");
11020 else printf(" r%d",r);
11024 for(r=0;r<=CCREG;r++) {
11025 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11026 if((regs[i].was32>>r)&1) {
11027 if(r==CCREG) printf(" CC");
11028 else if(r==HIREG) printf(" HI");
11029 else if(r==LOREG) printf(" LO");
11030 else printf(" r%d",r);
11035 #if defined(__i386__) || defined(__x86_64__)
11036 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11039 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11042 if(needed_reg[i]&1) printf("eax ");
11043 if((needed_reg[i]>>1)&1) printf("ecx ");
11044 if((needed_reg[i]>>2)&1) printf("edx ");
11045 if((needed_reg[i]>>3)&1) printf("ebx ");
11046 if((needed_reg[i]>>5)&1) printf("ebp ");
11047 if((needed_reg[i]>>6)&1) printf("esi ");
11048 if((needed_reg[i]>>7)&1) printf("edi ");
11050 for(r=0;r<=CCREG;r++) {
11051 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11052 if((requires_32bit[i]>>r)&1) {
11053 if(r==CCREG) printf(" CC");
11054 else if(r==HIREG) printf(" HI");
11055 else if(r==LOREG) printf(" LO");
11056 else printf(" r%d",r);
11061 for(r=0;r<=CCREG;r++) {
11062 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11063 if((pr32[i]>>r)&1) {
11064 if(r==CCREG) printf(" CC");
11065 else if(r==HIREG) printf(" HI");
11066 else if(r==LOREG) printf(" LO");
11067 else printf(" r%d",r);
11070 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11072 #if defined(__i386__) || defined(__x86_64__)
11073 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11075 if(regs[i].wasdirty&1) printf("eax ");
11076 if((regs[i].wasdirty>>1)&1) printf("ecx ");
11077 if((regs[i].wasdirty>>2)&1) printf("edx ");
11078 if((regs[i].wasdirty>>3)&1) printf("ebx ");
11079 if((regs[i].wasdirty>>5)&1) printf("ebp ");
11080 if((regs[i].wasdirty>>6)&1) printf("esi ");
11081 if((regs[i].wasdirty>>7)&1) printf("edi ");
11084 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11086 if(regs[i].wasdirty&1) printf("r0 ");
11087 if((regs[i].wasdirty>>1)&1) printf("r1 ");
11088 if((regs[i].wasdirty>>2)&1) printf("r2 ");
11089 if((regs[i].wasdirty>>3)&1) printf("r3 ");
11090 if((regs[i].wasdirty>>4)&1) printf("r4 ");
11091 if((regs[i].wasdirty>>5)&1) printf("r5 ");
11092 if((regs[i].wasdirty>>6)&1) printf("r6 ");
11093 if((regs[i].wasdirty>>7)&1) printf("r7 ");
11094 if((regs[i].wasdirty>>8)&1) printf("r8 ");
11095 if((regs[i].wasdirty>>9)&1) printf("r9 ");
11096 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11097 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11100 disassemble_inst(i);
11101 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11102 #if defined(__i386__) || defined(__x86_64__)
11103 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11104 if(regs[i].dirty&1) printf("eax ");
11105 if((regs[i].dirty>>1)&1) printf("ecx ");
11106 if((regs[i].dirty>>2)&1) printf("edx ");
11107 if((regs[i].dirty>>3)&1) printf("ebx ");
11108 if((regs[i].dirty>>5)&1) printf("ebp ");
11109 if((regs[i].dirty>>6)&1) printf("esi ");
11110 if((regs[i].dirty>>7)&1) printf("edi ");
11113 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11114 if(regs[i].dirty&1) printf("r0 ");
11115 if((regs[i].dirty>>1)&1) printf("r1 ");
11116 if((regs[i].dirty>>2)&1) printf("r2 ");
11117 if((regs[i].dirty>>3)&1) printf("r3 ");
11118 if((regs[i].dirty>>4)&1) printf("r4 ");
11119 if((regs[i].dirty>>5)&1) printf("r5 ");
11120 if((regs[i].dirty>>6)&1) printf("r6 ");
11121 if((regs[i].dirty>>7)&1) printf("r7 ");
11122 if((regs[i].dirty>>8)&1) printf("r8 ");
11123 if((regs[i].dirty>>9)&1) printf("r9 ");
11124 if((regs[i].dirty>>10)&1) printf("r10 ");
11125 if((regs[i].dirty>>12)&1) printf("r12 ");
11128 if(regs[i].isconst) {
11129 printf("constants: ");
11130 #if defined(__i386__) || defined(__x86_64__)
11131 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11132 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11133 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11134 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11135 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11136 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11137 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11140 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11141 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11142 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11143 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11144 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11145 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11146 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11147 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11148 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11149 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11150 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11151 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11157 for(r=0;r<=CCREG;r++) {
11158 if((regs[i].is32>>r)&1) {
11159 if(r==CCREG) printf(" CC");
11160 else if(r==HIREG) printf(" HI");
11161 else if(r==LOREG) printf(" LO");
11162 else printf(" r%d",r);
11168 for(r=0;r<=CCREG;r++) {
11169 if((p32[i]>>r)&1) {
11170 if(r==CCREG) printf(" CC");
11171 else if(r==HIREG) printf(" HI");
11172 else if(r==LOREG) printf(" LO");
11173 else printf(" r%d",r);
11176 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11177 else printf("\n");*/
11178 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11179 #if defined(__i386__) || defined(__x86_64__)
11180 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11181 if(branch_regs[i].dirty&1) printf("eax ");
11182 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11183 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11184 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11185 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11186 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11187 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11190 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11191 if(branch_regs[i].dirty&1) printf("r0 ");
11192 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11193 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11194 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11195 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11196 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11197 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11198 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11199 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11200 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11201 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11202 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11206 for(r=0;r<=CCREG;r++) {
11207 if((branch_regs[i].is32>>r)&1) {
11208 if(r==CCREG) printf(" CC");
11209 else if(r==HIREG) printf(" HI");
11210 else if(r==LOREG) printf(" LO");
11211 else printf(" r%d",r);
11220 /* Pass 8 - Assembly */
11221 linkcount=0;stubcount=0;
11222 ds=0;is_delayslot=0;
11224 uint64_t is32_pre=0;
11226 u_int beginning=(u_int)out;
11227 if((u_int)addr&1) {
11231 u_int instr_addr0_override=0;
11234 if (start == 0x80030000) {
11235 // nasty hack for fastbios thing
11236 // override block entry to this code
11237 instr_addr0_override=(u_int)out;
11238 emit_movimm(start,0);
11239 // abuse io address var as a flag that we
11240 // have already returned here once
11241 emit_readword((int)&address,1);
11242 emit_writeword(0,(int)&pcaddr);
11243 emit_writeword(0,(int)&address);
11245 emit_jne((int)new_dyna_leave);
11248 for(i=0;i<slen;i++)
11250 //if(ds) printf("ds: ");
11251 disassemble_inst(i);
11253 ds=0; // Skip delay slot
11254 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11257 speculate_register_values(i);
11258 #ifndef DESTRUCTIVE_WRITEBACK
11259 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11261 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11262 unneeded_reg[i],unneeded_reg_upper[i]);
11263 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11264 unneeded_reg[i],unneeded_reg_upper[i]);
11266 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11267 is32_pre=branch_regs[i].is32;
11268 dirty_pre=branch_regs[i].dirty;
11270 is32_pre=regs[i].is32;
11271 dirty_pre=regs[i].dirty;
11275 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11277 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11278 unneeded_reg[i],unneeded_reg_upper[i]);
11279 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11281 // branch target entry point
11282 instr_addr[i]=(u_int)out;
11283 assem_debug("<->\n");
11285 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11286 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11287 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11288 address_generation(i,®s[i],regs[i].regmap_entry);
11289 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11290 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11292 // Load the delay slot registers if necessary
11293 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11294 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11295 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11296 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11297 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11298 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11302 // Preload registers for following instruction
11303 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11304 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11305 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11306 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11307 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11308 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11310 // TODO: if(is_ooo(i)) address_generation(i+1);
11311 if(itype[i]==CJUMP||itype[i]==FJUMP)
11312 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11313 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11314 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11315 if(bt[i]) cop1_usable=0;
11319 alu_assemble(i,®s[i]);break;
11321 imm16_assemble(i,®s[i]);break;
11323 shift_assemble(i,®s[i]);break;
11325 shiftimm_assemble(i,®s[i]);break;
11327 load_assemble(i,®s[i]);break;
11329 loadlr_assemble(i,®s[i]);break;
11331 store_assemble(i,®s[i]);break;
11333 storelr_assemble(i,®s[i]);break;
11335 cop0_assemble(i,®s[i]);break;
11337 cop1_assemble(i,®s[i]);break;
11339 c1ls_assemble(i,®s[i]);break;
11341 cop2_assemble(i,®s[i]);break;
11343 c2ls_assemble(i,®s[i]);break;
11345 c2op_assemble(i,®s[i]);break;
11347 fconv_assemble(i,®s[i]);break;
11349 float_assemble(i,®s[i]);break;
11351 fcomp_assemble(i,®s[i]);break;
11353 multdiv_assemble(i,®s[i]);break;
11355 mov_assemble(i,®s[i]);break;
11357 syscall_assemble(i,®s[i]);break;
11359 hlecall_assemble(i,®s[i]);break;
11361 intcall_assemble(i,®s[i]);break;
11363 ujump_assemble(i,®s[i]);ds=1;break;
11365 rjump_assemble(i,®s[i]);ds=1;break;
11367 cjump_assemble(i,®s[i]);ds=1;break;
11369 sjump_assemble(i,®s[i]);ds=1;break;
11371 fjump_assemble(i,®s[i]);ds=1;break;
11373 pagespan_assemble(i,®s[i]);break;
11375 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11376 literal_pool(1024);
11378 literal_pool_jumpover(256);
11381 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11382 // If the block did not end with an unconditional branch,
11383 // add a jump to the next instruction.
11385 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11386 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11388 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11389 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11390 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11391 emit_loadreg(CCREG,HOST_CCREG);
11392 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11394 else if(!likely[i-2])
11396 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11397 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11401 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11402 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11404 add_to_linker((int)out,start+i*4,0);
11411 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11412 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11413 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11414 emit_loadreg(CCREG,HOST_CCREG);
11415 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11416 add_to_linker((int)out,start+i*4,0);
11420 // TODO: delay slot stubs?
11422 for(i=0;i<stubcount;i++)
11424 switch(stubs[i][0])
11432 do_readstub(i);break;
11437 do_writestub(i);break;
11439 do_ccstub(i);break;
11441 do_invstub(i);break;
11443 do_cop1stub(i);break;
11445 do_unalignedwritestub(i);break;
11449 if (instr_addr0_override)
11450 instr_addr[0] = instr_addr0_override;
11452 /* Pass 9 - Linker */
11453 for(i=0;i<linkcount;i++)
11455 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11457 if(!link_addr[i][2])
11460 void *addr=check_addr(link_addr[i][1]);
11461 emit_extjump(link_addr[i][0],link_addr[i][1]);
11463 set_jump_target(link_addr[i][0],(int)addr);
11464 add_link(link_addr[i][1],stub);
11466 else set_jump_target(link_addr[i][0],(int)stub);
11471 int target=(link_addr[i][1]-start)>>2;
11472 assert(target>=0&&target<slen);
11473 assert(instr_addr[target]);
11474 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11475 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11477 set_jump_target(link_addr[i][0],instr_addr[target]);
11481 // External Branch Targets (jump_in)
11482 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11483 for(i=0;i<slen;i++)
11487 if(instr_addr[i]) // TODO - delay slots (=null)
11489 u_int vaddr=start+i*4;
11490 u_int page=get_page(vaddr);
11491 u_int vpage=get_vpage(vaddr);
11493 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11495 if(!requires_32bit[i])
11500 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11501 assem_debug("jump_in: %x\n",start+i*4);
11502 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11503 int entry_point=do_dirty_stub(i);
11504 ll_add(jump_in+page,vaddr,(void *)entry_point);
11505 // If there was an existing entry in the hash table,
11506 // replace it with the new address.
11507 // Don't add new entries. We'll insert the
11508 // ones that actually get used in check_addr().
11509 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11510 if(ht_bin[0]==vaddr) {
11511 ht_bin[1]=entry_point;
11513 if(ht_bin[2]==vaddr) {
11514 ht_bin[3]=entry_point;
11519 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11520 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11521 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11522 //int entry_point=(int)out;
11523 ////assem_debug("entry_point: %x\n",entry_point);
11524 //load_regs_entry(i);
11525 //if(entry_point==(int)out)
11526 // entry_point=instr_addr[i];
11528 // emit_jmp(instr_addr[i]);
11529 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11530 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11531 int entry_point=do_dirty_stub(i);
11532 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11537 // Write out the literal pool if necessary
11539 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11541 if(((u_int)out)&7) emit_addnop(13);
11543 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11544 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11545 memcpy(copy,source,slen*4);
11549 __clear_cache((void *)beginning,out);
11552 // If we're within 256K of the end of the buffer,
11553 // start over from the beginning. (Is 256K enough?)
11554 if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11556 // Trap writes to any of the pages we compiled
11557 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11559 #ifndef DISABLE_TLB
11560 memory_map[i]|=0x40000000;
11561 if((signed int)start>=(signed int)0xC0000000) {
11563 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11565 memory_map[j]|=0x40000000;
11566 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11570 inv_code_start=inv_code_end=~0;
11572 // for PCSX we need to mark all mirrors too
11573 if(get_page(start)<(RAM_SIZE>>12))
11574 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11575 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11576 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11577 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11580 /* Pass 10 - Free memory by expiring oldest blocks */
11582 int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11583 while(expirep!=end)
11585 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11586 int base=(int)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11587 inv_debug("EXP: Phase %d\n",expirep);
11588 switch((expirep>>11)&3)
11591 // Clear jump_in and jump_dirty
11592 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11593 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11594 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11595 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11599 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11600 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11603 // Clear hash table
11604 for(i=0;i<32;i++) {
11605 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11606 if((ht_bin[3]>>shift)==(base>>shift) ||
11607 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11608 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11609 ht_bin[2]=ht_bin[3]=-1;
11611 if((ht_bin[1]>>shift)==(base>>shift) ||
11612 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11613 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11614 ht_bin[0]=ht_bin[2];
11615 ht_bin[1]=ht_bin[3];
11616 ht_bin[2]=ht_bin[3]=-1;
11623 if((expirep&2047)==0)
11626 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11627 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11630 expirep=(expirep+1)&65535;
11635 // vim:shiftwidth=2:expandtab