1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
26 #include "emu_if.h" //emulator interface
29 //#define assem_debug printf
30 //#define inv_debug printf
31 #define assem_debug(...)
32 #define inv_debug(...)
35 #include "assem_x86.h"
38 #include "assem_x64.h"
41 #include "assem_arm.h"
45 #define MAX_OUTPUT_BLOCK_SIZE 262144
49 signed char regmap_entry[HOST_REGS];
50 signed char regmap[HOST_REGS];
59 u_int loadedconst; // host regs that have constants loaded
60 u_int waswritten; // MIPS regs that were used as store base before
61 uint64_t constmap[HOST_REGS];
69 struct ll_entry *next;
75 char insn[MAXBLOCK][10];
76 u_char itype[MAXBLOCK];
77 u_char opcode[MAXBLOCK];
78 u_char opcode2[MAXBLOCK];
86 u_char dep1[MAXBLOCK];
87 u_char dep2[MAXBLOCK];
89 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
90 static uint64_t gte_rt[MAXBLOCK];
91 static uint64_t gte_unneeded[MAXBLOCK];
92 static u_int smrv[32]; // speculated MIPS register values
93 static u_int smrv_strong; // mask or regs that are likely to have correct values
94 static u_int smrv_weak; // same, but somewhat less likely
95 static u_int smrv_strong_next; // same, but after current insn executes
96 static u_int smrv_weak_next;
99 char likely[MAXBLOCK];
100 char is_ds[MAXBLOCK];
102 uint64_t unneeded_reg[MAXBLOCK];
103 uint64_t unneeded_reg_upper[MAXBLOCK];
104 uint64_t branch_unneeded_reg[MAXBLOCK];
105 uint64_t branch_unneeded_reg_upper[MAXBLOCK];
106 uint64_t p32[MAXBLOCK];
107 uint64_t pr32[MAXBLOCK];
108 signed char regmap_pre[MAXBLOCK][HOST_REGS];
109 signed char regmap[MAXBLOCK][HOST_REGS];
110 signed char regmap_entry[MAXBLOCK][HOST_REGS];
111 uint64_t constmap[MAXBLOCK][HOST_REGS];
112 struct regstat regs[MAXBLOCK];
113 struct regstat branch_regs[MAXBLOCK];
114 signed char minimum_free_regs[MAXBLOCK];
115 u_int needed_reg[MAXBLOCK];
116 uint64_t requires_32bit[MAXBLOCK];
117 u_int wont_dirty[MAXBLOCK];
118 u_int will_dirty[MAXBLOCK];
121 u_int instr_addr[MAXBLOCK];
122 u_int link_addr[MAXBLOCK][3];
124 u_int stubs[MAXBLOCK*3][8];
126 u_int literals[1024][2];
131 struct ll_entry *jump_in[4096];
132 struct ll_entry *jump_out[4096];
133 struct ll_entry *jump_dirty[4096];
134 u_int hash_table[65536][4] __attribute__((aligned(16)));
135 char shadow[1048576] __attribute__((aligned(16)));
141 static const u_int using_tlb=0;
143 int new_dynarec_did_compile;
144 int new_dynarec_hacks;
145 u_int stop_after_jal;
146 extern u_char restore_candidate[512];
147 extern int cycle_count;
149 /* registers that may be allocated */
151 #define HIREG 32 // hi
152 #define LOREG 33 // lo
153 #define FSREG 34 // FPU status (FCSR)
154 #define CSREG 35 // Coprocessor status
155 #define CCREG 36 // Cycle count
156 #define INVCP 37 // Pointer to invalid_code
157 #define MMREG 38 // Pointer to memory_map
158 #define ROREG 39 // ram offset (if rdram!=0x80000000)
160 #define FTEMP 40 // FPU temporary register
161 #define PTEMP 41 // Prefetch temporary register
162 #define TLREG 42 // TLB mapping offset
163 #define RHASH 43 // Return address hash
164 #define RHTBL 44 // Return address hash table address
165 #define RTEMP 45 // JR/JALR address register
167 #define AGEN1 46 // Address generation temporary register
168 #define AGEN2 47 // Address generation temporary register
169 #define MGEN1 48 // Maptable address generation temporary register
170 #define MGEN2 49 // Maptable address generation temporary register
171 #define BTREG 50 // Branch target temporary register
173 /* instruction types */
174 #define NOP 0 // No operation
175 #define LOAD 1 // Load
176 #define STORE 2 // Store
177 #define LOADLR 3 // Unaligned load
178 #define STORELR 4 // Unaligned store
179 #define MOV 5 // Move
180 #define ALU 6 // Arithmetic/logic
181 #define MULTDIV 7 // Multiply/divide
182 #define SHIFT 8 // Shift by register
183 #define SHIFTIMM 9// Shift by immediate
184 #define IMM16 10 // 16-bit immediate
185 #define RJUMP 11 // Unconditional jump to register
186 #define UJUMP 12 // Unconditional jump
187 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
188 #define SJUMP 14 // Conditional branch (regimm format)
189 #define COP0 15 // Coprocessor 0
190 #define COP1 16 // Coprocessor 1
191 #define C1LS 17 // Coprocessor 1 load/store
192 #define FJUMP 18 // Conditional branch (floating point)
193 #define FLOAT 19 // Floating point unit
194 #define FCONV 20 // Convert integer to float
195 #define FCOMP 21 // Floating point compare (sets FSREG)
196 #define SYSCALL 22// SYSCALL
197 #define OTHER 23 // Other
198 #define SPAN 24 // Branch/delay slot spans 2 pages
199 #define NI 25 // Not implemented
200 #define HLECALL 26// PCSX fake opcodes for HLE
201 #define COP2 27 // Coprocessor 2 move
202 #define C2LS 28 // Coprocessor 2 load/store
203 #define C2OP 29 // Coprocessor 2 operation
204 #define INTCALL 30// Call interpreter to handle rare corner cases
213 #define LOADBU_STUB 7
214 #define LOADHU_STUB 8
215 #define STOREB_STUB 9
216 #define STOREH_STUB 10
217 #define STOREW_STUB 11
218 #define STORED_STUB 12
219 #define STORELR_STUB 13
220 #define INVCODE_STUB 14
228 int new_recompile_block(int addr);
229 void *get_addr_ht(u_int vaddr);
230 void invalidate_block(u_int block);
231 void invalidate_addr(u_int addr);
232 void remove_hash(int vaddr);
235 void dyna_linker_ds();
237 void verify_code_vm();
238 void verify_code_ds();
241 void fp_exception_ds();
243 void jump_syscall_hle();
247 void new_dyna_leave();
252 void read_nomem_new();
253 void read_nomemb_new();
254 void read_nomemh_new();
255 void read_nomemd_new();
256 void write_nomem_new();
257 void write_nomemb_new();
258 void write_nomemh_new();
259 void write_nomemd_new();
260 void write_rdram_new();
261 void write_rdramb_new();
262 void write_rdramh_new();
263 void write_rdramd_new();
264 extern u_int memory_map[1048576];
266 // Needed by assembler
267 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
268 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
269 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
270 void load_all_regs(signed char i_regmap[]);
271 void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
272 void load_regs_entry(int t);
273 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
277 //#define DEBUG_CYCLE_COUNT 1
279 int cycle_multiplier; // 100 for 1.0
281 static int CLOCK_ADJUST(int x)
284 return (x * cycle_multiplier + s * 50) / 100;
287 static void tlb_hacks()
291 if (strncmp((char *) ROM_HEADER->nom, "GOLDENEYE",9) == 0)
295 switch (ROM_HEADER->Country_code&0xFF)
307 // Unknown country code
311 u_int rom_addr=(u_int)rom;
313 // Since memory_map is 32-bit, on 64-bit systems the rom needs to be
314 // in the lower 4G of memory to use this hack. Copy it if necessary.
315 if((void *)rom>(void *)0xffffffff) {
316 munmap(ROM_COPY, 67108864);
317 if(mmap(ROM_COPY, 12582912,
318 PROT_READ | PROT_WRITE,
319 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
320 -1, 0) <= 0) {printf("mmap() failed\n");}
321 memcpy(ROM_COPY,rom,12582912);
322 rom_addr=(u_int)ROM_COPY;
326 for(n=0x7F000;n<0x80000;n++) {
327 memory_map[n]=(((u_int)(rom_addr+addr-0x7F000000))>>2)|0x40000000;
334 static u_int get_page(u_int vaddr)
337 u_int page=(vaddr^0x80000000)>>12;
339 u_int page=vaddr&~0xe0000000;
340 if (page < 0x1000000)
341 page &= ~0x0e00000; // RAM mirrors
345 if(page>262143&&tlb_LUT_r[vaddr>>12]) page=(tlb_LUT_r[vaddr>>12]^0x80000000)>>12;
347 if(page>2048) page=2048+(page&2047);
352 static u_int get_vpage(u_int vaddr)
354 u_int vpage=(vaddr^0x80000000)>>12;
356 if(vpage>262143&&tlb_LUT_r[vaddr>>12]) vpage&=2047; // jump_dirty uses a hash of the virtual address instead
358 if(vpage>2048) vpage=2048+(vpage&2047);
362 // no virtual mem in PCSX
363 static u_int get_vpage(u_int vaddr)
365 return get_page(vaddr);
369 // Get address from virtual address
370 // This is called from the recompiled JR/JALR instructions
371 void *get_addr(u_int vaddr)
373 u_int page=get_page(vaddr);
374 u_int vpage=get_vpage(vaddr);
375 struct ll_entry *head;
376 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
379 if(head->vaddr==vaddr&&head->reg32==0) {
380 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
381 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
384 ht_bin[1]=(int)head->addr;
390 head=jump_dirty[vpage];
392 if(head->vaddr==vaddr&&head->reg32==0) {
393 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
394 // Don't restore blocks which are about to expire from the cache
395 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
396 if(verify_dirty(head->addr)) {
397 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
398 invalid_code[vaddr>>12]=0;
399 inv_code_start=inv_code_end=~0;
401 memory_map[vaddr>>12]|=0x40000000;
405 if(tlb_LUT_r[vaddr>>12]) {
406 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
407 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
410 restore_candidate[vpage>>3]|=1<<(vpage&7);
412 else restore_candidate[page>>3]|=1<<(page&7);
413 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
414 if(ht_bin[0]==vaddr) {
415 ht_bin[1]=(int)head->addr; // Replace existing entry
421 ht_bin[1]=(int)head->addr;
429 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
430 int r=new_recompile_block(vaddr);
431 if(r==0) return get_addr(vaddr);
432 // Execute in unmapped page, generate pagefault execption
434 Cause=(vaddr<<31)|0x8;
435 EPC=(vaddr&1)?vaddr-5:vaddr;
437 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
438 EntryHi=BadVAddr&0xFFFFE000;
439 return get_addr_ht(0x80000000);
441 // Look up address in hash table first
442 void *get_addr_ht(u_int vaddr)
444 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
445 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
446 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
447 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
448 return get_addr(vaddr);
451 void *get_addr_32(u_int vaddr,u_int flags)
454 return get_addr(vaddr);
456 //printf("TRACE: count=%d next=%d (get_addr_32 %x,flags %x)\n",Count,next_interupt,vaddr,flags);
457 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
458 if(ht_bin[0]==vaddr) return (void *)ht_bin[1];
459 if(ht_bin[2]==vaddr) return (void *)ht_bin[3];
460 u_int page=get_page(vaddr);
461 u_int vpage=get_vpage(vaddr);
462 struct ll_entry *head;
465 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
466 //printf("TRACE: count=%d next=%d (get_addr_32 match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
468 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
470 ht_bin[1]=(int)head->addr;
472 }else if(ht_bin[2]==-1) {
473 ht_bin[3]=(int)head->addr;
476 //ht_bin[3]=ht_bin[1];
477 //ht_bin[2]=ht_bin[0];
478 //ht_bin[1]=(int)head->addr;
485 head=jump_dirty[vpage];
487 if(head->vaddr==vaddr&&(head->reg32&flags)==0) {
488 //printf("TRACE: count=%d next=%d (get_addr_32 match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
489 // Don't restore blocks which are about to expire from the cache
490 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
491 if(verify_dirty(head->addr)) {
492 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
493 invalid_code[vaddr>>12]=0;
494 inv_code_start=inv_code_end=~0;
495 memory_map[vaddr>>12]|=0x40000000;
498 if(tlb_LUT_r[vaddr>>12]) {
499 invalid_code[tlb_LUT_r[vaddr>>12]>>12]=0;
500 memory_map[tlb_LUT_r[vaddr>>12]>>12]|=0x40000000;
503 restore_candidate[vpage>>3]|=1<<(vpage&7);
505 else restore_candidate[page>>3]|=1<<(page&7);
507 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
509 ht_bin[1]=(int)head->addr;
511 }else if(ht_bin[2]==-1) {
512 ht_bin[3]=(int)head->addr;
515 //ht_bin[3]=ht_bin[1];
516 //ht_bin[2]=ht_bin[0];
517 //ht_bin[1]=(int)head->addr;
525 //printf("TRACE: count=%d next=%d (get_addr_32 no-match %x,flags %x)\n",Count,next_interupt,vaddr,flags);
526 int r=new_recompile_block(vaddr);
527 if(r==0) return get_addr(vaddr);
528 // Execute in unmapped page, generate pagefault execption
530 Cause=(vaddr<<31)|0x8;
531 EPC=(vaddr&1)?vaddr-5:vaddr;
533 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
534 EntryHi=BadVAddr&0xFFFFE000;
535 return get_addr_ht(0x80000000);
539 void clear_all_regs(signed char regmap[])
542 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
545 signed char get_reg(signed char regmap[],int r)
548 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
552 // Find a register that is available for two consecutive cycles
553 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
556 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
560 int count_free_regs(signed char regmap[])
564 for(hr=0;hr<HOST_REGS;hr++)
566 if(hr!=EXCLUDE_REG) {
567 if(regmap[hr]<0) count++;
573 void dirty_reg(struct regstat *cur,signed char reg)
577 for (hr=0;hr<HOST_REGS;hr++) {
578 if((cur->regmap[hr]&63)==reg) {
584 // If we dirty the lower half of a 64 bit register which is now being
585 // sign-extended, we need to dump the upper half.
586 // Note: Do this only after completion of the instruction, because
587 // some instructions may need to read the full 64-bit value even if
588 // overwriting it (eg SLTI, DSRA32).
589 static void flush_dirty_uppers(struct regstat *cur)
592 for (hr=0;hr<HOST_REGS;hr++) {
593 if((cur->dirty>>hr)&1) {
596 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
601 void set_const(struct regstat *cur,signed char reg,uint64_t value)
605 for (hr=0;hr<HOST_REGS;hr++) {
606 if(cur->regmap[hr]==reg) {
608 cur->constmap[hr]=value;
610 else if((cur->regmap[hr]^64)==reg) {
612 cur->constmap[hr]=value>>32;
617 void clear_const(struct regstat *cur,signed char reg)
621 for (hr=0;hr<HOST_REGS;hr++) {
622 if((cur->regmap[hr]&63)==reg) {
623 cur->isconst&=~(1<<hr);
628 int is_const(struct regstat *cur,signed char reg)
633 for (hr=0;hr<HOST_REGS;hr++) {
634 if((cur->regmap[hr]&63)==reg) {
635 return (cur->isconst>>hr)&1;
640 uint64_t get_const(struct regstat *cur,signed char reg)
644 for (hr=0;hr<HOST_REGS;hr++) {
645 if(cur->regmap[hr]==reg) {
646 return cur->constmap[hr];
649 printf("Unknown constant in r%d\n",reg);
653 // Least soon needed registers
654 // Look at the next ten instructions and see which registers
655 // will be used. Try not to reallocate these.
656 void lsn(u_char hsn[], int i, int *preferred_reg)
666 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
668 // Don't go past an unconditonal jump
675 if(rs1[i+j]) hsn[rs1[i+j]]=j;
676 if(rs2[i+j]) hsn[rs2[i+j]]=j;
677 if(rt1[i+j]) hsn[rt1[i+j]]=j;
678 if(rt2[i+j]) hsn[rt2[i+j]]=j;
679 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
680 // Stores can allocate zero
684 // On some architectures stores need invc_ptr
685 #if defined(HOST_IMM8)
686 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
690 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
698 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
700 // Follow first branch
701 int t=(ba[i+b]-start)>>2;
702 j=7-b;if(t+j>=slen) j=slen-t-1;
705 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
706 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
707 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
708 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
711 // TODO: preferred register based on backward branch
713 // Delay slot should preferably not overwrite branch conditions or cycle count
714 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
715 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
716 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
722 // Coprocessor load/store needs FTEMP, even if not declared
723 if(itype[i]==C1LS||itype[i]==C2LS) {
726 // Load L/R also uses FTEMP as a temporary register
727 if(itype[i]==LOADLR) {
730 // Also SWL/SWR/SDL/SDR
731 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
734 // Don't remove the TLB registers either
735 if(itype[i]==LOAD || itype[i]==LOADLR || itype[i]==STORE || itype[i]==STORELR || itype[i]==C1LS || itype[i]==C2LS) {
738 // Don't remove the miniht registers
739 if(itype[i]==UJUMP||itype[i]==RJUMP)
746 // We only want to allocate registers if we're going to use them again soon
747 int needed_again(int r, int i)
753 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
755 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
756 return 0; // Don't need any registers if exiting the block
764 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
766 // Don't go past an unconditonal jump
770 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
777 if(rs1[i+j]==r) rn=j;
778 if(rs2[i+j]==r) rn=j;
779 if((unneeded_reg[i+j]>>r)&1) rn=10;
780 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
788 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
790 // Follow first branch
792 int t=(ba[i+b]-start)>>2;
793 j=7-b;if(t+j>=slen) j=slen-t-1;
796 if(!((unneeded_reg[t+j]>>r)&1)) {
797 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
798 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
808 // Try to match register allocations at the end of a loop with those
810 int loop_reg(int i, int r, int hr)
819 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
821 // Don't go past an unconditonal jump
828 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
833 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
834 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
835 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
837 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
839 int t=(ba[i+k]-start)>>2;
840 int reg=get_reg(regs[t].regmap_entry,r);
841 if(reg>=0) return reg;
842 //reg=get_reg(regs[t+1].regmap_entry,r);
843 //if(reg>=0) return reg;
851 // Allocate every register, preserving source/target regs
852 void alloc_all(struct regstat *cur,int i)
856 for(hr=0;hr<HOST_REGS;hr++) {
857 if(hr!=EXCLUDE_REG) {
858 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
859 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
862 cur->dirty&=~(1<<hr);
865 if((cur->regmap[hr]&63)==0)
868 cur->dirty&=~(1<<hr);
875 void div64(int64_t dividend,int64_t divisor)
879 //printf("TRACE: ddiv %8x%8x %8x%8x\n" ,(int)reg[HIREG],(int)(reg[HIREG]>>32)
880 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
882 void divu64(uint64_t dividend,uint64_t divisor)
886 //printf("TRACE: ddivu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
887 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
890 void mult64(uint64_t m1,uint64_t m2)
892 unsigned long long int op1, op2, op3, op4;
893 unsigned long long int result1, result2, result3, result4;
894 unsigned long long int temp1, temp2, temp3, temp4;
910 op1 = op2 & 0xFFFFFFFF;
911 op2 = (op2 >> 32) & 0xFFFFFFFF;
912 op3 = op4 & 0xFFFFFFFF;
913 op4 = (op4 >> 32) & 0xFFFFFFFF;
916 temp2 = (temp1 >> 32) + op1 * op4;
918 temp4 = (temp3 >> 32) + op2 * op4;
920 result1 = temp1 & 0xFFFFFFFF;
921 result2 = temp2 + (temp3 & 0xFFFFFFFF);
922 result3 = (result2 >> 32) + temp4;
923 result4 = (result3 >> 32);
925 lo = result1 | (result2 << 32);
926 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
935 void multu64(uint64_t m1,uint64_t m2)
937 unsigned long long int op1, op2, op3, op4;
938 unsigned long long int result1, result2, result3, result4;
939 unsigned long long int temp1, temp2, temp3, temp4;
941 op1 = m1 & 0xFFFFFFFF;
942 op2 = (m1 >> 32) & 0xFFFFFFFF;
943 op3 = m2 & 0xFFFFFFFF;
944 op4 = (m2 >> 32) & 0xFFFFFFFF;
947 temp2 = (temp1 >> 32) + op1 * op4;
949 temp4 = (temp3 >> 32) + op2 * op4;
951 result1 = temp1 & 0xFFFFFFFF;
952 result2 = temp2 + (temp3 & 0xFFFFFFFF);
953 result3 = (result2 >> 32) + temp4;
954 result4 = (result3 >> 32);
956 lo = result1 | (result2 << 32);
957 hi = (result3 & 0xFFFFFFFF) | (result4 << 32);
959 //printf("TRACE: dmultu %8x%8x %8x%8x\n",(int)reg[HIREG],(int)(reg[HIREG]>>32)
960 // ,(int)reg[LOREG],(int)(reg[LOREG]>>32));
963 uint64_t ldl_merge(uint64_t original,uint64_t loaded,u_int bits)
971 else original=loaded;
974 uint64_t ldr_merge(uint64_t original,uint64_t loaded,u_int bits)
977 original>>=64-(bits^56);
978 original<<=64-(bits^56);
982 else original=loaded;
988 #include "assem_x86.c"
991 #include "assem_x64.c"
994 #include "assem_arm.c"
997 // Add virtual address mapping to linked list
998 void ll_add(struct ll_entry **head,int vaddr,void *addr)
1000 struct ll_entry *new_entry;
1001 new_entry=malloc(sizeof(struct ll_entry));
1002 assert(new_entry!=NULL);
1003 new_entry->vaddr=vaddr;
1005 new_entry->addr=addr;
1006 new_entry->next=*head;
1010 // Add virtual address mapping for 32-bit compiled block
1011 void ll_add_32(struct ll_entry **head,int vaddr,u_int reg32,void *addr)
1013 ll_add(head,vaddr,addr);
1015 (*head)->reg32=reg32;
1019 // Check if an address is already compiled
1020 // but don't return addresses which are about to expire from the cache
1021 void *check_addr(u_int vaddr)
1023 u_int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
1024 if(ht_bin[0]==vaddr) {
1025 if(((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1026 if(isclean(ht_bin[1])) return (void *)ht_bin[1];
1028 if(ht_bin[2]==vaddr) {
1029 if(((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2)))
1030 if(isclean(ht_bin[3])) return (void *)ht_bin[3];
1032 u_int page=get_page(vaddr);
1033 struct ll_entry *head;
1036 if(head->vaddr==vaddr&&head->reg32==0) {
1037 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1038 // Update existing entry with current address
1039 if(ht_bin[0]==vaddr) {
1040 ht_bin[1]=(int)head->addr;
1043 if(ht_bin[2]==vaddr) {
1044 ht_bin[3]=(int)head->addr;
1047 // Insert into hash table with low priority.
1048 // Don't evict existing entries, as they are probably
1049 // addresses that are being accessed frequently.
1051 ht_bin[1]=(int)head->addr;
1053 }else if(ht_bin[2]==-1) {
1054 ht_bin[3]=(int)head->addr;
1065 void remove_hash(int vaddr)
1067 //printf("remove hash: %x\n",vaddr);
1068 int *ht_bin=hash_table[(((vaddr)>>16)^vaddr)&0xFFFF];
1069 if(ht_bin[2]==vaddr) {
1070 ht_bin[2]=ht_bin[3]=-1;
1072 if(ht_bin[0]==vaddr) {
1073 ht_bin[0]=ht_bin[2];
1074 ht_bin[1]=ht_bin[3];
1075 ht_bin[2]=ht_bin[3]=-1;
1079 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
1081 struct ll_entry *next;
1083 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
1084 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
1086 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
1087 remove_hash((*head)->vaddr);
1094 head=&((*head)->next);
1099 // Remove all entries from linked list
1100 void ll_clear(struct ll_entry **head)
1102 struct ll_entry *cur;
1103 struct ll_entry *next;
1114 // Dereference the pointers and remove if it matches
1115 void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
1118 int ptr=get_pointer(head->addr);
1119 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
1120 if(((ptr>>shift)==(addr>>shift)) ||
1121 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
1123 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
1124 u_int host_addr=(u_int)kill_pointer(head->addr);
1126 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1133 // This is called when we write to a compiled block (see do_invstub)
1134 void invalidate_page(u_int page)
1136 struct ll_entry *head;
1137 struct ll_entry *next;
1141 inv_debug("INVALIDATE: %x\n",head->vaddr);
1142 remove_hash(head->vaddr);
1147 head=jump_out[page];
1150 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
1151 u_int host_addr=(u_int)kill_pointer(head->addr);
1153 needs_clear_cache[(host_addr-(u_int)BASE_ADDR)>>17]|=1<<(((host_addr-(u_int)BASE_ADDR)>>12)&31);
1161 static void invalidate_block_range(u_int block, u_int first, u_int last)
1163 u_int page=get_page(block<<12);
1164 //printf("first=%d last=%d\n",first,last);
1165 invalidate_page(page);
1166 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
1167 assert(last<page+5);
1168 // Invalidate the adjacent pages if a block crosses a 4K boundary
1170 invalidate_page(first);
1173 for(first=page+1;first<last;first++) {
1174 invalidate_page(first);
1180 // Don't trap writes
1181 invalid_code[block]=1;
1183 // If there is a valid TLB entry for this page, remove write protect
1184 if(tlb_LUT_w[block]) {
1185 assert(tlb_LUT_r[block]==tlb_LUT_w[block]);
1186 // CHECK: Is this right?
1187 memory_map[block]=((tlb_LUT_w[block]&0xFFFFF000)-(block<<12)+(unsigned int)rdram-0x80000000)>>2;
1188 u_int real_block=tlb_LUT_w[block]>>12;
1189 invalid_code[real_block]=1;
1190 if(real_block>=0x80000&&real_block<0x80800) memory_map[real_block]=((u_int)rdram-0x80000000)>>2;
1192 else if(block>=0x80000&&block<0x80800) memory_map[block]=((u_int)rdram-0x80000000)>>2;
1196 memset(mini_ht,-1,sizeof(mini_ht));
1200 void invalidate_block(u_int block)
1202 u_int page=get_page(block<<12);
1203 u_int vpage=get_vpage(block<<12);
1204 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1205 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1208 struct ll_entry *head;
1209 head=jump_dirty[vpage];
1210 //printf("page=%d vpage=%d\n",page,vpage);
1213 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1214 get_bounds((int)head->addr,&start,&end);
1215 //printf("start: %x end: %x\n",start,end);
1216 if(page<2048&&start>=0x80000000&&end<0x80000000+RAM_SIZE) {
1217 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1218 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1219 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1223 if(page<2048&&(signed int)start>=(signed int)0xC0000000&&(signed int)end>=(signed int)0xC0000000) {
1224 if(((start+memory_map[start>>12]-(u_int)rdram)>>12)<=page&&((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)>=page) {
1225 if((((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047)<first) first=((start+memory_map[start>>12]-(u_int)rdram)>>12)&2047;
1226 if((((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047)>last) last=((end-1+memory_map[(end-1)>>12]-(u_int)rdram)>>12)&2047;
1233 invalidate_block_range(block,first,last);
1236 void invalidate_addr(u_int addr)
1240 // this check is done by the caller
1241 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1242 u_int page=get_vpage(addr);
1243 if(page<2048) { // RAM
1244 struct ll_entry *head;
1245 u_int addr_min=~0, addr_max=0;
1246 int mask=RAM_SIZE-1;
1248 inv_code_start=addr&~0xfff;
1249 inv_code_end=addr|0xfff;
1252 // must check previous page too because of spans..
1254 inv_code_start-=0x1000;
1256 for(;pg1<=page;pg1++) {
1257 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1259 get_bounds((int)head->addr,&start,&end);
1260 if((start&mask)<=(addr&mask)&&(addr&mask)<(end&mask)) {
1261 if(start<addr_min) addr_min=start;
1262 if(end>addr_max) addr_max=end;
1264 else if(addr<start) {
1265 if(start<inv_code_end)
1266 inv_code_end=start-1;
1269 if(end>inv_code_start)
1275 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1276 inv_code_start=inv_code_end=~0;
1277 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1281 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1286 invalidate_block(addr>>12);
1289 // This is called when loading a save state.
1290 // Anything could have changed, so invalidate everything.
1291 void invalidate_all_pages()
1294 for(page=0;page<4096;page++)
1295 invalidate_page(page);
1296 for(page=0;page<1048576;page++)
1297 if(!invalid_code[page]) {
1298 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1299 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1302 __clear_cache((void *)BASE_ADDR,(void *)BASE_ADDR+(1<<TARGET_SIZE_2));
1305 memset(mini_ht,-1,sizeof(mini_ht));
1309 for(page=0;page<0x100000;page++) {
1310 if(tlb_LUT_r[page]) {
1311 memory_map[page]=((tlb_LUT_r[page]&0xFFFFF000)-(page<<12)+(unsigned int)rdram-0x80000000)>>2;
1312 if(!tlb_LUT_w[page]||!invalid_code[page])
1313 memory_map[page]|=0x40000000; // Write protect
1315 else memory_map[page]=-1;
1316 if(page==0x80000) page=0xC0000;
1322 // Add an entry to jump_out after making a link
1323 void add_link(u_int vaddr,void *src)
1325 u_int page=get_page(vaddr);
1326 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1327 int *ptr=(int *)(src+4);
1328 assert((*ptr&0x0fff0000)==0x059f0000);
1329 ll_add(jump_out+page,vaddr,src);
1330 //int ptr=get_pointer(src);
1331 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1334 // If a code block was found to be unmodified (bit was set in
1335 // restore_candidate) and it remains unmodified (bit is clear
1336 // in invalid_code) then move the entries for that 4K page from
1337 // the dirty list to the clean list.
1338 void clean_blocks(u_int page)
1340 struct ll_entry *head;
1341 inv_debug("INV: clean_blocks page=%d\n",page);
1342 head=jump_dirty[page];
1344 if(!invalid_code[head->vaddr>>12]) {
1345 // Don't restore blocks which are about to expire from the cache
1346 if((((u_int)head->addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1348 if(verify_dirty((int)head->addr)) {
1349 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1352 get_bounds((int)head->addr,&start,&end);
1353 if(start-(u_int)rdram<RAM_SIZE) {
1354 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1355 inv|=invalid_code[i];
1359 if((signed int)head->vaddr>=(signed int)0xC0000000) {
1360 u_int addr = (head->vaddr+(memory_map[head->vaddr>>12]<<2));
1361 //printf("addr=%x start=%x end=%x\n",addr,start,end);
1362 if(addr<start||addr>=end) inv=1;
1365 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1369 void * clean_addr=(void *)get_clean_addr((int)head->addr);
1370 if((((u_int)clean_addr-(u_int)out)<<(32-TARGET_SIZE_2))>0x60000000+(MAX_OUTPUT_BLOCK_SIZE<<(32-TARGET_SIZE_2))) {
1373 if(page<2048&&tlb_LUT_r[head->vaddr>>12]) ppage=(tlb_LUT_r[head->vaddr>>12]^0x80000000)>>12;
1375 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1376 //printf("page=%x, addr=%x\n",page,head->vaddr);
1377 //assert(head->vaddr>>12==(page|0x80000));
1378 ll_add_32(jump_in+ppage,head->vaddr,head->reg32,clean_addr);
1379 int *ht_bin=hash_table[((head->vaddr>>16)^head->vaddr)&0xFFFF];
1381 if(ht_bin[0]==head->vaddr) {
1382 ht_bin[1]=(int)clean_addr; // Replace existing entry
1384 if(ht_bin[2]==head->vaddr) {
1385 ht_bin[3]=(int)clean_addr; // Replace existing entry
1398 void mov_alloc(struct regstat *current,int i)
1400 // Note: Don't need to actually alloc the source registers
1401 if((~current->is32>>rs1[i])&1) {
1402 //alloc_reg64(current,i,rs1[i]);
1403 alloc_reg64(current,i,rt1[i]);
1404 current->is32&=~(1LL<<rt1[i]);
1406 //alloc_reg(current,i,rs1[i]);
1407 alloc_reg(current,i,rt1[i]);
1408 current->is32|=(1LL<<rt1[i]);
1410 clear_const(current,rs1[i]);
1411 clear_const(current,rt1[i]);
1412 dirty_reg(current,rt1[i]);
1415 void shiftimm_alloc(struct regstat *current,int i)
1417 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1420 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1422 alloc_reg(current,i,rt1[i]);
1423 current->is32|=1LL<<rt1[i];
1424 dirty_reg(current,rt1[i]);
1425 if(is_const(current,rs1[i])) {
1426 int v=get_const(current,rs1[i]);
1427 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1428 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1429 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1431 else clear_const(current,rt1[i]);
1436 clear_const(current,rs1[i]);
1437 clear_const(current,rt1[i]);
1440 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1443 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1444 alloc_reg64(current,i,rt1[i]);
1445 current->is32&=~(1LL<<rt1[i]);
1446 dirty_reg(current,rt1[i]);
1449 if(opcode2[i]==0x3c) // DSLL32
1452 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1453 alloc_reg64(current,i,rt1[i]);
1454 current->is32&=~(1LL<<rt1[i]);
1455 dirty_reg(current,rt1[i]);
1458 if(opcode2[i]==0x3e) // DSRL32
1461 alloc_reg64(current,i,rs1[i]);
1463 alloc_reg64(current,i,rt1[i]);
1464 current->is32&=~(1LL<<rt1[i]);
1466 alloc_reg(current,i,rt1[i]);
1467 current->is32|=1LL<<rt1[i];
1469 dirty_reg(current,rt1[i]);
1472 if(opcode2[i]==0x3f) // DSRA32
1475 alloc_reg64(current,i,rs1[i]);
1476 alloc_reg(current,i,rt1[i]);
1477 current->is32|=1LL<<rt1[i];
1478 dirty_reg(current,rt1[i]);
1483 void shift_alloc(struct regstat *current,int i)
1486 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1488 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1489 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1490 alloc_reg(current,i,rt1[i]);
1491 if(rt1[i]==rs2[i]) {
1492 alloc_reg_temp(current,i,-1);
1493 minimum_free_regs[i]=1;
1495 current->is32|=1LL<<rt1[i];
1496 } else { // DSLLV/DSRLV/DSRAV
1497 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1498 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1499 alloc_reg64(current,i,rt1[i]);
1500 current->is32&=~(1LL<<rt1[i]);
1501 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1503 alloc_reg_temp(current,i,-1);
1504 minimum_free_regs[i]=1;
1507 clear_const(current,rs1[i]);
1508 clear_const(current,rs2[i]);
1509 clear_const(current,rt1[i]);
1510 dirty_reg(current,rt1[i]);
1514 void alu_alloc(struct regstat *current,int i)
1516 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1518 if(rs1[i]&&rs2[i]) {
1519 alloc_reg(current,i,rs1[i]);
1520 alloc_reg(current,i,rs2[i]);
1523 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1524 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1526 alloc_reg(current,i,rt1[i]);
1528 current->is32|=1LL<<rt1[i];
1530 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1532 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1534 alloc_reg64(current,i,rs1[i]);
1535 alloc_reg64(current,i,rs2[i]);
1536 alloc_reg(current,i,rt1[i]);
1538 alloc_reg(current,i,rs1[i]);
1539 alloc_reg(current,i,rs2[i]);
1540 alloc_reg(current,i,rt1[i]);
1543 current->is32|=1LL<<rt1[i];
1545 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1547 if(rs1[i]&&rs2[i]) {
1548 alloc_reg(current,i,rs1[i]);
1549 alloc_reg(current,i,rs2[i]);
1553 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1554 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1556 alloc_reg(current,i,rt1[i]);
1557 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1559 if(!((current->uu>>rt1[i])&1)) {
1560 alloc_reg64(current,i,rt1[i]);
1562 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1563 if(rs1[i]&&rs2[i]) {
1564 alloc_reg64(current,i,rs1[i]);
1565 alloc_reg64(current,i,rs2[i]);
1569 // Is is really worth it to keep 64-bit values in registers?
1571 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1572 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1576 current->is32&=~(1LL<<rt1[i]);
1578 current->is32|=1LL<<rt1[i];
1582 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1584 if(rs1[i]&&rs2[i]) {
1585 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1586 alloc_reg64(current,i,rs1[i]);
1587 alloc_reg64(current,i,rs2[i]);
1588 alloc_reg64(current,i,rt1[i]);
1590 alloc_reg(current,i,rs1[i]);
1591 alloc_reg(current,i,rs2[i]);
1592 alloc_reg(current,i,rt1[i]);
1596 alloc_reg(current,i,rt1[i]);
1597 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1598 // DADD used as move, or zeroing
1599 // If we have a 64-bit source, then make the target 64 bits too
1600 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1601 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1602 alloc_reg64(current,i,rt1[i]);
1603 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1604 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1605 alloc_reg64(current,i,rt1[i]);
1607 if(opcode2[i]>=0x2e&&rs2[i]) {
1608 // DSUB used as negation - 64-bit result
1609 // If we have a 32-bit register, extend it to 64 bits
1610 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1611 alloc_reg64(current,i,rt1[i]);
1615 if(rs1[i]&&rs2[i]) {
1616 current->is32&=~(1LL<<rt1[i]);
1618 current->is32&=~(1LL<<rt1[i]);
1619 if((current->is32>>rs1[i])&1)
1620 current->is32|=1LL<<rt1[i];
1622 current->is32&=~(1LL<<rt1[i]);
1623 if((current->is32>>rs2[i])&1)
1624 current->is32|=1LL<<rt1[i];
1626 current->is32|=1LL<<rt1[i];
1630 clear_const(current,rs1[i]);
1631 clear_const(current,rs2[i]);
1632 clear_const(current,rt1[i]);
1633 dirty_reg(current,rt1[i]);
1636 void imm16_alloc(struct regstat *current,int i)
1638 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1640 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1641 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1642 current->is32&=~(1LL<<rt1[i]);
1643 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1644 // TODO: Could preserve the 32-bit flag if the immediate is zero
1645 alloc_reg64(current,i,rt1[i]);
1646 alloc_reg64(current,i,rs1[i]);
1648 clear_const(current,rs1[i]);
1649 clear_const(current,rt1[i]);
1651 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1652 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1653 current->is32|=1LL<<rt1[i];
1654 clear_const(current,rs1[i]);
1655 clear_const(current,rt1[i]);
1657 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1658 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1659 if(rs1[i]!=rt1[i]) {
1660 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1661 alloc_reg64(current,i,rt1[i]);
1662 current->is32&=~(1LL<<rt1[i]);
1665 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1666 if(is_const(current,rs1[i])) {
1667 int v=get_const(current,rs1[i]);
1668 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1669 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1670 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1672 else clear_const(current,rt1[i]);
1674 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1675 if(is_const(current,rs1[i])) {
1676 int v=get_const(current,rs1[i]);
1677 set_const(current,rt1[i],v+imm[i]);
1679 else clear_const(current,rt1[i]);
1680 current->is32|=1LL<<rt1[i];
1683 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1684 current->is32|=1LL<<rt1[i];
1686 dirty_reg(current,rt1[i]);
1689 void load_alloc(struct regstat *current,int i)
1691 clear_const(current,rt1[i]);
1692 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1693 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1694 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1695 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1696 alloc_reg(current,i,rt1[i]);
1697 assert(get_reg(current->regmap,rt1[i])>=0);
1698 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1700 current->is32&=~(1LL<<rt1[i]);
1701 alloc_reg64(current,i,rt1[i]);
1703 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1705 current->is32&=~(1LL<<rt1[i]);
1706 alloc_reg64(current,i,rt1[i]);
1707 alloc_all(current,i);
1708 alloc_reg64(current,i,FTEMP);
1709 minimum_free_regs[i]=HOST_REGS;
1711 else current->is32|=1LL<<rt1[i];
1712 dirty_reg(current,rt1[i]);
1713 // If using TLB, need a register for pointer to the mapping table
1714 if(using_tlb) alloc_reg(current,i,TLREG);
1715 // LWL/LWR need a temporary register for the old value
1716 if(opcode[i]==0x22||opcode[i]==0x26)
1718 alloc_reg(current,i,FTEMP);
1719 alloc_reg_temp(current,i,-1);
1720 minimum_free_regs[i]=1;
1725 // Load to r0 or unneeded register (dummy load)
1726 // but we still need a register to calculate the address
1727 if(opcode[i]==0x22||opcode[i]==0x26)
1729 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1731 // If using TLB, need a register for pointer to the mapping table
1732 if(using_tlb) alloc_reg(current,i,TLREG);
1733 alloc_reg_temp(current,i,-1);
1734 minimum_free_regs[i]=1;
1735 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1737 alloc_all(current,i);
1738 alloc_reg64(current,i,FTEMP);
1739 minimum_free_regs[i]=HOST_REGS;
1744 void store_alloc(struct regstat *current,int i)
1746 clear_const(current,rs2[i]);
1747 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1748 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1749 alloc_reg(current,i,rs2[i]);
1750 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1751 alloc_reg64(current,i,rs2[i]);
1752 if(rs2[i]) alloc_reg(current,i,FTEMP);
1754 // If using TLB, need a register for pointer to the mapping table
1755 if(using_tlb) alloc_reg(current,i,TLREG);
1756 #if defined(HOST_IMM8)
1757 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1758 else alloc_reg(current,i,INVCP);
1760 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1761 alloc_reg(current,i,FTEMP);
1763 // We need a temporary register for address generation
1764 alloc_reg_temp(current,i,-1);
1765 minimum_free_regs[i]=1;
1768 void c1ls_alloc(struct regstat *current,int i)
1770 //clear_const(current,rs1[i]); // FIXME
1771 clear_const(current,rt1[i]);
1772 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1773 alloc_reg(current,i,CSREG); // Status
1774 alloc_reg(current,i,FTEMP);
1775 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1776 alloc_reg64(current,i,FTEMP);
1778 // If using TLB, need a register for pointer to the mapping table
1779 if(using_tlb) alloc_reg(current,i,TLREG);
1780 #if defined(HOST_IMM8)
1781 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1782 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1783 alloc_reg(current,i,INVCP);
1785 // We need a temporary register for address generation
1786 alloc_reg_temp(current,i,-1);
1789 void c2ls_alloc(struct regstat *current,int i)
1791 clear_const(current,rt1[i]);
1792 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1793 alloc_reg(current,i,FTEMP);
1794 // If using TLB, need a register for pointer to the mapping table
1795 if(using_tlb) alloc_reg(current,i,TLREG);
1796 #if defined(HOST_IMM8)
1797 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1798 else if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1799 alloc_reg(current,i,INVCP);
1801 // We need a temporary register for address generation
1802 alloc_reg_temp(current,i,-1);
1803 minimum_free_regs[i]=1;
1806 #ifndef multdiv_alloc
1807 void multdiv_alloc(struct regstat *current,int i)
1814 // case 0x1D: DMULTU
1817 clear_const(current,rs1[i]);
1818 clear_const(current,rs2[i]);
1821 if((opcode2[i]&4)==0) // 32-bit
1823 current->u&=~(1LL<<HIREG);
1824 current->u&=~(1LL<<LOREG);
1825 alloc_reg(current,i,HIREG);
1826 alloc_reg(current,i,LOREG);
1827 alloc_reg(current,i,rs1[i]);
1828 alloc_reg(current,i,rs2[i]);
1829 current->is32|=1LL<<HIREG;
1830 current->is32|=1LL<<LOREG;
1831 dirty_reg(current,HIREG);
1832 dirty_reg(current,LOREG);
1836 current->u&=~(1LL<<HIREG);
1837 current->u&=~(1LL<<LOREG);
1838 current->uu&=~(1LL<<HIREG);
1839 current->uu&=~(1LL<<LOREG);
1840 alloc_reg64(current,i,HIREG);
1841 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1842 alloc_reg64(current,i,rs1[i]);
1843 alloc_reg64(current,i,rs2[i]);
1844 alloc_all(current,i);
1845 current->is32&=~(1LL<<HIREG);
1846 current->is32&=~(1LL<<LOREG);
1847 dirty_reg(current,HIREG);
1848 dirty_reg(current,LOREG);
1849 minimum_free_regs[i]=HOST_REGS;
1854 // Multiply by zero is zero.
1855 // MIPS does not have a divide by zero exception.
1856 // The result is undefined, we return zero.
1857 alloc_reg(current,i,HIREG);
1858 alloc_reg(current,i,LOREG);
1859 current->is32|=1LL<<HIREG;
1860 current->is32|=1LL<<LOREG;
1861 dirty_reg(current,HIREG);
1862 dirty_reg(current,LOREG);
1867 void cop0_alloc(struct regstat *current,int i)
1869 if(opcode2[i]==0) // MFC0
1872 clear_const(current,rt1[i]);
1873 alloc_all(current,i);
1874 alloc_reg(current,i,rt1[i]);
1875 current->is32|=1LL<<rt1[i];
1876 dirty_reg(current,rt1[i]);
1879 else if(opcode2[i]==4) // MTC0
1882 clear_const(current,rs1[i]);
1883 alloc_reg(current,i,rs1[i]);
1884 alloc_all(current,i);
1887 alloc_all(current,i); // FIXME: Keep r0
1889 alloc_reg(current,i,0);
1894 // TLBR/TLBWI/TLBWR/TLBP/ERET
1895 assert(opcode2[i]==0x10);
1896 alloc_all(current,i);
1898 minimum_free_regs[i]=HOST_REGS;
1901 void cop1_alloc(struct regstat *current,int i)
1903 alloc_reg(current,i,CSREG); // Load status
1904 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1907 clear_const(current,rt1[i]);
1909 alloc_reg64(current,i,rt1[i]); // DMFC1
1910 current->is32&=~(1LL<<rt1[i]);
1912 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1913 current->is32|=1LL<<rt1[i];
1915 dirty_reg(current,rt1[i]);
1917 alloc_reg_temp(current,i,-1);
1919 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1922 clear_const(current,rs1[i]);
1924 alloc_reg64(current,i,rs1[i]); // DMTC1
1926 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1927 alloc_reg_temp(current,i,-1);
1931 alloc_reg(current,i,0);
1932 alloc_reg_temp(current,i,-1);
1935 minimum_free_regs[i]=1;
1937 void fconv_alloc(struct regstat *current,int i)
1939 alloc_reg(current,i,CSREG); // Load status
1940 alloc_reg_temp(current,i,-1);
1941 minimum_free_regs[i]=1;
1943 void float_alloc(struct regstat *current,int i)
1945 alloc_reg(current,i,CSREG); // Load status
1946 alloc_reg_temp(current,i,-1);
1947 minimum_free_regs[i]=1;
1949 void c2op_alloc(struct regstat *current,int i)
1951 alloc_reg_temp(current,i,-1);
1953 void fcomp_alloc(struct regstat *current,int i)
1955 alloc_reg(current,i,CSREG); // Load status
1956 alloc_reg(current,i,FSREG); // Load flags
1957 dirty_reg(current,FSREG); // Flag will be modified
1958 alloc_reg_temp(current,i,-1);
1959 minimum_free_regs[i]=1;
1962 void syscall_alloc(struct regstat *current,int i)
1964 alloc_cc(current,i);
1965 dirty_reg(current,CCREG);
1966 alloc_all(current,i);
1967 minimum_free_regs[i]=HOST_REGS;
1971 void delayslot_alloc(struct regstat *current,int i)
1982 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1983 printf("Disabled speculative precompilation\n");
1987 imm16_alloc(current,i);
1991 load_alloc(current,i);
1995 store_alloc(current,i);
1998 alu_alloc(current,i);
2001 shift_alloc(current,i);
2004 multdiv_alloc(current,i);
2007 shiftimm_alloc(current,i);
2010 mov_alloc(current,i);
2013 cop0_alloc(current,i);
2017 cop1_alloc(current,i);
2020 c1ls_alloc(current,i);
2023 c2ls_alloc(current,i);
2026 fconv_alloc(current,i);
2029 float_alloc(current,i);
2032 fcomp_alloc(current,i);
2035 c2op_alloc(current,i);
2040 // Special case where a branch and delay slot span two pages in virtual memory
2041 static void pagespan_alloc(struct regstat *current,int i)
2044 current->wasconst=0;
2046 minimum_free_regs[i]=HOST_REGS;
2047 alloc_all(current,i);
2048 alloc_cc(current,i);
2049 dirty_reg(current,CCREG);
2050 if(opcode[i]==3) // JAL
2052 alloc_reg(current,i,31);
2053 dirty_reg(current,31);
2055 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
2057 alloc_reg(current,i,rs1[i]);
2059 alloc_reg(current,i,rt1[i]);
2060 dirty_reg(current,rt1[i]);
2063 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
2065 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2066 if(rs2[i]) alloc_reg(current,i,rs2[i]);
2067 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
2069 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2070 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
2074 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
2076 if(rs1[i]) alloc_reg(current,i,rs1[i]);
2077 if(!((current->is32>>rs1[i])&1))
2079 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
2083 if(opcode[i]==0x11) // BC1
2085 alloc_reg(current,i,FSREG);
2086 alloc_reg(current,i,CSREG);
2091 add_stub(int type,int addr,int retaddr,int a,int b,int c,int d,int e)
2093 stubs[stubcount][0]=type;
2094 stubs[stubcount][1]=addr;
2095 stubs[stubcount][2]=retaddr;
2096 stubs[stubcount][3]=a;
2097 stubs[stubcount][4]=b;
2098 stubs[stubcount][5]=c;
2099 stubs[stubcount][6]=d;
2100 stubs[stubcount][7]=e;
2104 // Write out a single register
2105 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
2108 for(hr=0;hr<HOST_REGS;hr++) {
2109 if(hr!=EXCLUDE_REG) {
2110 if((regmap[hr]&63)==r) {
2113 emit_storereg(r,hr);
2115 if((is32>>regmap[hr])&1) {
2116 emit_sarimm(hr,31,hr);
2117 emit_storereg(r|64,hr);
2121 emit_storereg(r|64,hr);
2131 //if(!tracedebug) return 0;
2134 for(i=0;i<2097152;i++) {
2135 unsigned int temp=sum;
2138 sum^=((u_int *)rdram)[i];
2147 sum^=((u_int *)reg)[i];
2155 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
2157 #ifndef DISABLE_COP1
2160 printf("f%d:%8x%8x ",i,((int*)reg_cop1_simple[i])[1],*((int*)reg_cop1_simple[i]));
2170 void memdebug(int i)
2172 //printf("TRACE: count=%d next=%d (checksum %x) lo=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[LOREG]>>32),(int)reg[LOREG]);
2173 //printf("TRACE: count=%d next=%d (rchecksum %x)\n",Count,next_interupt,rchecksum());
2176 //if(Count>=-2084597794) {
2177 if((signed int)Count>=-2084597794&&(signed int)Count<0) {
2179 printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
2180 //printf("TRACE: count=%d next=%d (checksum %x) Status=%x\n",Count,next_interupt,mchecksum(),Status);
2181 //printf("TRACE: count=%d next=%d (checksum %x) hi=%8x%8x\n",Count,next_interupt,mchecksum(),(int)(reg[HIREG]>>32),(int)reg[HIREG]);
2184 printf("TRACE: %x\n",(&i)[-1]);
2188 printf("TRACE: %x \n",(&j)[10]);
2189 printf("TRACE: %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x\n",(&j)[1],(&j)[2],(&j)[3],(&j)[4],(&j)[5],(&j)[6],(&j)[7],(&j)[8],(&j)[9],(&j)[10],(&j)[11],(&j)[12],(&j)[13],(&j)[14],(&j)[15],(&j)[16],(&j)[17],(&j)[18],(&j)[19],(&j)[20]);
2193 //printf("TRACE: %x\n",(&i)[-1]);
2196 void tlb_debug(u_int cause, u_int addr, u_int iaddr)
2198 printf("TLB Exception: instruction=%x addr=%x cause=%x\n",iaddr, addr, cause);
2201 void alu_assemble(int i,struct regstat *i_regs)
2203 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
2205 signed char s1,s2,t;
2206 t=get_reg(i_regs->regmap,rt1[i]);
2208 s1=get_reg(i_regs->regmap,rs1[i]);
2209 s2=get_reg(i_regs->regmap,rs2[i]);
2210 if(rs1[i]&&rs2[i]) {
2213 if(opcode2[i]&2) emit_sub(s1,s2,t);
2214 else emit_add(s1,s2,t);
2217 if(s1>=0) emit_mov(s1,t);
2218 else emit_loadreg(rs1[i],t);
2222 if(opcode2[i]&2) emit_neg(s2,t);
2223 else emit_mov(s2,t);
2226 emit_loadreg(rs2[i],t);
2227 if(opcode2[i]&2) emit_neg(t,t);
2230 else emit_zeroreg(t);
2234 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
2236 signed char s1l,s2l,s1h,s2h,tl,th;
2237 tl=get_reg(i_regs->regmap,rt1[i]);
2238 th=get_reg(i_regs->regmap,rt1[i]|64);
2240 s1l=get_reg(i_regs->regmap,rs1[i]);
2241 s2l=get_reg(i_regs->regmap,rs2[i]);
2242 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2243 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2244 if(rs1[i]&&rs2[i]) {
2247 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
2248 else emit_adds(s1l,s2l,tl);
2250 #ifdef INVERTED_CARRY
2251 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
2253 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
2255 else emit_add(s1h,s2h,th);
2259 if(s1l>=0) emit_mov(s1l,tl);
2260 else emit_loadreg(rs1[i],tl);
2262 if(s1h>=0) emit_mov(s1h,th);
2263 else emit_loadreg(rs1[i]|64,th);
2268 if(opcode2[i]&2) emit_negs(s2l,tl);
2269 else emit_mov(s2l,tl);
2272 emit_loadreg(rs2[i],tl);
2273 if(opcode2[i]&2) emit_negs(tl,tl);
2276 #ifdef INVERTED_CARRY
2277 if(s2h>=0) emit_mov(s2h,th);
2278 else emit_loadreg(rs2[i]|64,th);
2280 emit_adcimm(-1,th); // x86 has inverted carry flag
2285 if(s2h>=0) emit_rscimm(s2h,0,th);
2287 emit_loadreg(rs2[i]|64,th);
2288 emit_rscimm(th,0,th);
2291 if(s2h>=0) emit_mov(s2h,th);
2292 else emit_loadreg(rs2[i]|64,th);
2299 if(th>=0) emit_zeroreg(th);
2304 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2306 signed char s1l,s1h,s2l,s2h,t;
2307 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2309 t=get_reg(i_regs->regmap,rt1[i]);
2312 s1l=get_reg(i_regs->regmap,rs1[i]);
2313 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2314 s2l=get_reg(i_regs->regmap,rs2[i]);
2315 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2316 if(rs2[i]==0) // rx<r0
2319 if(opcode2[i]==0x2a) // SLT
2320 emit_shrimm(s1h,31,t);
2321 else // SLTU (unsigned can not be less than zero)
2324 else if(rs1[i]==0) // r0<rx
2327 if(opcode2[i]==0x2a) // SLT
2328 emit_set_gz64_32(s2h,s2l,t);
2329 else // SLTU (set if not zero)
2330 emit_set_nz64_32(s2h,s2l,t);
2333 assert(s1l>=0);assert(s1h>=0);
2334 assert(s2l>=0);assert(s2h>=0);
2335 if(opcode2[i]==0x2a) // SLT
2336 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2338 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2342 t=get_reg(i_regs->regmap,rt1[i]);
2345 s1l=get_reg(i_regs->regmap,rs1[i]);
2346 s2l=get_reg(i_regs->regmap,rs2[i]);
2347 if(rs2[i]==0) // rx<r0
2350 if(opcode2[i]==0x2a) // SLT
2351 emit_shrimm(s1l,31,t);
2352 else // SLTU (unsigned can not be less than zero)
2355 else if(rs1[i]==0) // r0<rx
2358 if(opcode2[i]==0x2a) // SLT
2359 emit_set_gz32(s2l,t);
2360 else // SLTU (set if not zero)
2361 emit_set_nz32(s2l,t);
2364 assert(s1l>=0);assert(s2l>=0);
2365 if(opcode2[i]==0x2a) // SLT
2366 emit_set_if_less32(s1l,s2l,t);
2368 emit_set_if_carry32(s1l,s2l,t);
2374 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2376 signed char s1l,s1h,s2l,s2h,th,tl;
2377 tl=get_reg(i_regs->regmap,rt1[i]);
2378 th=get_reg(i_regs->regmap,rt1[i]|64);
2379 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2383 s1l=get_reg(i_regs->regmap,rs1[i]);
2384 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2385 s2l=get_reg(i_regs->regmap,rs2[i]);
2386 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2387 if(rs1[i]&&rs2[i]) {
2388 assert(s1l>=0);assert(s1h>=0);
2389 assert(s2l>=0);assert(s2h>=0);
2390 if(opcode2[i]==0x24) { // AND
2391 emit_and(s1l,s2l,tl);
2392 emit_and(s1h,s2h,th);
2394 if(opcode2[i]==0x25) { // OR
2395 emit_or(s1l,s2l,tl);
2396 emit_or(s1h,s2h,th);
2398 if(opcode2[i]==0x26) { // XOR
2399 emit_xor(s1l,s2l,tl);
2400 emit_xor(s1h,s2h,th);
2402 if(opcode2[i]==0x27) { // NOR
2403 emit_or(s1l,s2l,tl);
2404 emit_or(s1h,s2h,th);
2411 if(opcode2[i]==0x24) { // AND
2415 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2417 if(s1l>=0) emit_mov(s1l,tl);
2418 else emit_loadreg(rs1[i],tl);
2419 if(s1h>=0) emit_mov(s1h,th);
2420 else emit_loadreg(rs1[i]|64,th);
2424 if(s2l>=0) emit_mov(s2l,tl);
2425 else emit_loadreg(rs2[i],tl);
2426 if(s2h>=0) emit_mov(s2h,th);
2427 else emit_loadreg(rs2[i]|64,th);
2434 if(opcode2[i]==0x27) { // NOR
2436 if(s1l>=0) emit_not(s1l,tl);
2438 emit_loadreg(rs1[i],tl);
2441 if(s1h>=0) emit_not(s1h,th);
2443 emit_loadreg(rs1[i]|64,th);
2449 if(s2l>=0) emit_not(s2l,tl);
2451 emit_loadreg(rs2[i],tl);
2454 if(s2h>=0) emit_not(s2h,th);
2456 emit_loadreg(rs2[i]|64,th);
2472 s1l=get_reg(i_regs->regmap,rs1[i]);
2473 s2l=get_reg(i_regs->regmap,rs2[i]);
2474 if(rs1[i]&&rs2[i]) {
2477 if(opcode2[i]==0x24) { // AND
2478 emit_and(s1l,s2l,tl);
2480 if(opcode2[i]==0x25) { // OR
2481 emit_or(s1l,s2l,tl);
2483 if(opcode2[i]==0x26) { // XOR
2484 emit_xor(s1l,s2l,tl);
2486 if(opcode2[i]==0x27) { // NOR
2487 emit_or(s1l,s2l,tl);
2493 if(opcode2[i]==0x24) { // AND
2496 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2498 if(s1l>=0) emit_mov(s1l,tl);
2499 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2503 if(s2l>=0) emit_mov(s2l,tl);
2504 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2506 else emit_zeroreg(tl);
2508 if(opcode2[i]==0x27) { // NOR
2510 if(s1l>=0) emit_not(s1l,tl);
2512 emit_loadreg(rs1[i],tl);
2518 if(s2l>=0) emit_not(s2l,tl);
2520 emit_loadreg(rs2[i],tl);
2524 else emit_movimm(-1,tl);
2533 void imm16_assemble(int i,struct regstat *i_regs)
2535 if (opcode[i]==0x0f) { // LUI
2538 t=get_reg(i_regs->regmap,rt1[i]);
2541 if(!((i_regs->isconst>>t)&1))
2542 emit_movimm(imm[i]<<16,t);
2546 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2549 t=get_reg(i_regs->regmap,rt1[i]);
2550 s=get_reg(i_regs->regmap,rs1[i]);
2555 if(!((i_regs->isconst>>t)&1)) {
2557 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2558 emit_addimm(t,imm[i],t);
2560 if(!((i_regs->wasconst>>s)&1))
2561 emit_addimm(s,imm[i],t);
2563 emit_movimm(constmap[i][s]+imm[i],t);
2569 if(!((i_regs->isconst>>t)&1))
2570 emit_movimm(imm[i],t);
2575 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2577 signed char sh,sl,th,tl;
2578 th=get_reg(i_regs->regmap,rt1[i]|64);
2579 tl=get_reg(i_regs->regmap,rt1[i]);
2580 sh=get_reg(i_regs->regmap,rs1[i]|64);
2581 sl=get_reg(i_regs->regmap,rs1[i]);
2587 emit_addimm64_32(sh,sl,imm[i],th,tl);
2590 emit_addimm(sl,imm[i],tl);
2593 emit_movimm(imm[i],tl);
2594 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2599 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2601 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2602 signed char sh,sl,t;
2603 t=get_reg(i_regs->regmap,rt1[i]);
2604 sh=get_reg(i_regs->regmap,rs1[i]|64);
2605 sl=get_reg(i_regs->regmap,rs1[i]);
2609 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2610 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2611 if(opcode[i]==0x0a) { // SLTI
2613 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2614 emit_slti32(t,imm[i],t);
2616 emit_slti32(sl,imm[i],t);
2621 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2622 emit_sltiu32(t,imm[i],t);
2624 emit_sltiu32(sl,imm[i],t);
2629 if(opcode[i]==0x0a) // SLTI
2630 emit_slti64_32(sh,sl,imm[i],t);
2632 emit_sltiu64_32(sh,sl,imm[i],t);
2635 // SLTI(U) with r0 is just stupid,
2636 // nonetheless examples can be found
2637 if(opcode[i]==0x0a) // SLTI
2638 if(0<imm[i]) emit_movimm(1,t);
2639 else emit_zeroreg(t);
2642 if(imm[i]) emit_movimm(1,t);
2643 else emit_zeroreg(t);
2649 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2651 signed char sh,sl,th,tl;
2652 th=get_reg(i_regs->regmap,rt1[i]|64);
2653 tl=get_reg(i_regs->regmap,rt1[i]);
2654 sh=get_reg(i_regs->regmap,rs1[i]|64);
2655 sl=get_reg(i_regs->regmap,rs1[i]);
2656 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2657 if(opcode[i]==0x0c) //ANDI
2661 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2662 emit_andimm(tl,imm[i],tl);
2664 if(!((i_regs->wasconst>>sl)&1))
2665 emit_andimm(sl,imm[i],tl);
2667 emit_movimm(constmap[i][sl]&imm[i],tl);
2672 if(th>=0) emit_zeroreg(th);
2678 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2682 emit_loadreg(rs1[i]|64,th);
2687 if(opcode[i]==0x0d) //ORI
2689 emit_orimm(tl,imm[i],tl);
2691 if(!((i_regs->wasconst>>sl)&1))
2692 emit_orimm(sl,imm[i],tl);
2694 emit_movimm(constmap[i][sl]|imm[i],tl);
2696 if(opcode[i]==0x0e) //XORI
2698 emit_xorimm(tl,imm[i],tl);
2700 if(!((i_regs->wasconst>>sl)&1))
2701 emit_xorimm(sl,imm[i],tl);
2703 emit_movimm(constmap[i][sl]^imm[i],tl);
2707 emit_movimm(imm[i],tl);
2708 if(th>=0) emit_zeroreg(th);
2716 void shiftimm_assemble(int i,struct regstat *i_regs)
2718 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2722 t=get_reg(i_regs->regmap,rt1[i]);
2723 s=get_reg(i_regs->regmap,rs1[i]);
2725 if(t>=0&&!((i_regs->isconst>>t)&1)){
2732 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2734 if(opcode2[i]==0) // SLL
2736 emit_shlimm(s<0?t:s,imm[i],t);
2738 if(opcode2[i]==2) // SRL
2740 emit_shrimm(s<0?t:s,imm[i],t);
2742 if(opcode2[i]==3) // SRA
2744 emit_sarimm(s<0?t:s,imm[i],t);
2748 if(s>=0 && s!=t) emit_mov(s,t);
2752 //emit_storereg(rt1[i],t); //DEBUG
2755 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2758 signed char sh,sl,th,tl;
2759 th=get_reg(i_regs->regmap,rt1[i]|64);
2760 tl=get_reg(i_regs->regmap,rt1[i]);
2761 sh=get_reg(i_regs->regmap,rs1[i]|64);
2762 sl=get_reg(i_regs->regmap,rs1[i]);
2767 if(th>=0) emit_zeroreg(th);
2774 if(opcode2[i]==0x38) // DSLL
2776 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2777 emit_shlimm(sl,imm[i],tl);
2779 if(opcode2[i]==0x3a) // DSRL
2781 emit_shrdimm(sl,sh,imm[i],tl);
2782 if(th>=0) emit_shrimm(sh,imm[i],th);
2784 if(opcode2[i]==0x3b) // DSRA
2786 emit_shrdimm(sl,sh,imm[i],tl);
2787 if(th>=0) emit_sarimm(sh,imm[i],th);
2791 if(sl!=tl) emit_mov(sl,tl);
2792 if(th>=0&&sh!=th) emit_mov(sh,th);
2798 if(opcode2[i]==0x3c) // DSLL32
2801 signed char sl,tl,th;
2802 tl=get_reg(i_regs->regmap,rt1[i]);
2803 th=get_reg(i_regs->regmap,rt1[i]|64);
2804 sl=get_reg(i_regs->regmap,rs1[i]);
2813 emit_shlimm(th,imm[i]&31,th);
2818 if(opcode2[i]==0x3e) // DSRL32
2821 signed char sh,tl,th;
2822 tl=get_reg(i_regs->regmap,rt1[i]);
2823 th=get_reg(i_regs->regmap,rt1[i]|64);
2824 sh=get_reg(i_regs->regmap,rs1[i]|64);
2828 if(th>=0) emit_zeroreg(th);
2831 emit_shrimm(tl,imm[i]&31,tl);
2836 if(opcode2[i]==0x3f) // DSRA32
2840 tl=get_reg(i_regs->regmap,rt1[i]);
2841 sh=get_reg(i_regs->regmap,rs1[i]|64);
2847 emit_sarimm(tl,imm[i]&31,tl);
2854 #ifndef shift_assemble
2855 void shift_assemble(int i,struct regstat *i_regs)
2857 printf("Need shift_assemble for this architecture.\n");
2862 void load_assemble(int i,struct regstat *i_regs)
2864 int s,th,tl,addr,map=-1;
2867 int memtarget=0,c=0;
2868 int fastload_reg_override=0;
2870 th=get_reg(i_regs->regmap,rt1[i]|64);
2871 tl=get_reg(i_regs->regmap,rt1[i]);
2872 s=get_reg(i_regs->regmap,rs1[i]);
2874 for(hr=0;hr<HOST_REGS;hr++) {
2875 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2877 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2879 c=(i_regs->wasconst>>s)&1;
2881 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2882 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
2885 //printf("load_assemble: c=%d\n",c);
2886 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2887 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2889 if(tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80)
2891 // could be FIFO, must perform the read
2893 assem_debug("(forced read)\n");
2894 tl=get_reg(i_regs->regmap,-1);
2898 if(offset||s<0||c) addr=tl;
2900 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2902 //printf("load_assemble: c=%d\n",c);
2903 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2904 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2906 if(th>=0) reglist&=~(1<<th);
2910 map=get_reg(i_regs->regmap,ROREG);
2911 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2913 //#define R29_HACK 1
2915 // Strmnnrmn's speed hack
2916 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2919 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2924 if (opcode[i]==0x20||opcode[i]==0x24) x=3; // LB/LBU
2925 if (opcode[i]==0x21||opcode[i]==0x25) x=2; // LH/LHU
2926 map=get_reg(i_regs->regmap,TLREG);
2929 map=do_tlb_r(addr,tl,map,x,-1,-1,c,constmap[i][s]+offset);
2930 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr);
2932 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2933 if (opcode[i]==0x20) { // LB
2936 #ifdef HOST_IMM_ADDR32
2938 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2942 //emit_xorimm(addr,3,tl);
2943 //gen_tlb_addr_r(tl,map);
2944 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2946 #ifdef BIG_ENDIAN_MIPS
2947 if(!c) emit_xorimm(addr,3,tl);
2948 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2952 if(fastload_reg_override) a=fastload_reg_override;
2954 emit_movsbl_indexed_tlb(x,a,map,tl);
2958 add_stub(LOADB_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2961 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2963 if (opcode[i]==0x21) { // LH
2966 #ifdef HOST_IMM_ADDR32
2968 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2973 #ifdef BIG_ENDIAN_MIPS
2974 if(!c) emit_xorimm(addr,2,tl);
2975 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2979 if(fastload_reg_override) a=fastload_reg_override;
2981 //emit_movswl_indexed_tlb(x,tl,map,tl);
2984 gen_tlb_addr_r(a,map);
2985 emit_movswl_indexed(x,a,tl);
2988 emit_movswl_indexed(x,a,tl);
2990 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2996 add_stub(LOADH_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
2999 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3001 if (opcode[i]==0x23) { // LW
3005 if(fastload_reg_override) a=fastload_reg_override;
3006 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3007 #ifdef HOST_IMM_ADDR32
3009 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3012 emit_readword_indexed_tlb(0,a,map,tl);
3015 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3018 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3020 if (opcode[i]==0x24) { // LBU
3023 #ifdef HOST_IMM_ADDR32
3025 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
3029 //emit_xorimm(addr,3,tl);
3030 //gen_tlb_addr_r(tl,map);
3031 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
3033 #ifdef BIG_ENDIAN_MIPS
3034 if(!c) emit_xorimm(addr,3,tl);
3035 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3039 if(fastload_reg_override) a=fastload_reg_override;
3041 emit_movzbl_indexed_tlb(x,a,map,tl);
3045 add_stub(LOADBU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3048 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3050 if (opcode[i]==0x25) { // LHU
3053 #ifdef HOST_IMM_ADDR32
3055 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
3060 #ifdef BIG_ENDIAN_MIPS
3061 if(!c) emit_xorimm(addr,2,tl);
3062 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3066 if(fastload_reg_override) a=fastload_reg_override;
3068 //emit_movzwl_indexed_tlb(x,tl,map,tl);
3071 gen_tlb_addr_r(a,map);
3072 emit_movzwl_indexed(x,a,tl);
3075 emit_movzwl_indexed(x,a,tl);
3077 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
3083 add_stub(LOADHU_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3086 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3088 if (opcode[i]==0x27) { // LWU
3093 if(fastload_reg_override) a=fastload_reg_override;
3094 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
3095 #ifdef HOST_IMM_ADDR32
3097 emit_readword_tlb(constmap[i][s]+offset,map,tl);
3100 emit_readword_indexed_tlb(0,a,map,tl);
3103 add_stub(LOADW_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3106 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3110 if (opcode[i]==0x37) { // LD
3114 if(fastload_reg_override) a=fastload_reg_override;
3115 //gen_tlb_addr_r(tl,map);
3116 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
3117 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
3118 #ifdef HOST_IMM_ADDR32
3120 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3123 emit_readdword_indexed_tlb(0,a,map,th,tl);
3126 add_stub(LOADD_STUB,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3129 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
3132 //emit_storereg(rt1[i],tl); // DEBUG
3133 //if(opcode[i]==0x23)
3134 //if(opcode[i]==0x24)
3135 //if(opcode[i]==0x23||opcode[i]==0x24)
3136 /*if(opcode[i]==0x21||opcode[i]==0x23||opcode[i]==0x24)
3140 emit_readword((int)&last_count,ECX);
3142 if(get_reg(i_regs->regmap,CCREG)<0)
3143 emit_loadreg(CCREG,HOST_CCREG);
3144 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3145 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3146 emit_writeword(HOST_CCREG,(int)&Count);
3149 if(get_reg(i_regs->regmap,CCREG)<0)
3150 emit_loadreg(CCREG,0);
3152 emit_mov(HOST_CCREG,0);
3154 emit_addimm(0,2*ccadj[i],0);
3155 emit_writeword(0,(int)&Count);
3157 emit_call((int)memdebug);
3159 restore_regs(0x100f);
3163 #ifndef loadlr_assemble
3164 void loadlr_assemble(int i,struct regstat *i_regs)
3166 printf("Need loadlr_assemble for this architecture.\n");
3171 void store_assemble(int i,struct regstat *i_regs)
3176 int jaddr=0,jaddr2,type;
3177 int memtarget=0,c=0;
3178 int agr=AGEN1+(i&1);
3179 int faststore_reg_override=0;
3181 th=get_reg(i_regs->regmap,rs2[i]|64);
3182 tl=get_reg(i_regs->regmap,rs2[i]);
3183 s=get_reg(i_regs->regmap,rs1[i]);
3184 temp=get_reg(i_regs->regmap,agr);
3185 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3188 c=(i_regs->wasconst>>s)&1;
3190 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3191 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3196 for(hr=0;hr<HOST_REGS;hr++) {
3197 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3199 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3200 if(offset||s<0||c) addr=temp;
3206 // Strmnnrmn's speed hack
3207 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3209 emit_cmpimm(addr,RAM_SIZE);
3210 #ifdef DESTRUCTIVE_SHIFT
3211 if(s==addr) emit_mov(s,temp);
3215 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
3219 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
3220 // Hint to branch predictor that the branch is unlikely to be taken
3222 emit_jno_unlikely(0);
3228 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
3233 if (opcode[i]==0x28) x=3; // SB
3234 if (opcode[i]==0x29) x=2; // SH
3235 map=get_reg(i_regs->regmap,TLREG);
3238 map=do_tlb_w(addr,temp,map,x,c,constmap[i][s]+offset);
3239 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3242 if (opcode[i]==0x28) { // SB
3245 #ifdef BIG_ENDIAN_MIPS
3246 if(!c) emit_xorimm(addr,3,temp);
3247 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
3251 if(faststore_reg_override) a=faststore_reg_override;
3252 //gen_tlb_addr_w(temp,map);
3253 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
3254 emit_writebyte_indexed_tlb(tl,x,a,map,a);
3258 if (opcode[i]==0x29) { // SH
3261 #ifdef BIG_ENDIAN_MIPS
3262 if(!c) emit_xorimm(addr,2,temp);
3263 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
3267 if(faststore_reg_override) a=faststore_reg_override;
3269 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
3272 gen_tlb_addr_w(a,map);
3273 emit_writehword_indexed(tl,x,a);
3275 emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
3279 if (opcode[i]==0x2B) { // SW
3282 if(faststore_reg_override) a=faststore_reg_override;
3283 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
3284 emit_writeword_indexed_tlb(tl,0,a,map,temp);
3288 if (opcode[i]==0x3F) { // SD
3291 if(faststore_reg_override) a=faststore_reg_override;
3294 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
3295 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
3296 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
3299 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3300 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3301 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
3308 // PCSX store handlers don't check invcode again
3310 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3314 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3316 #ifdef DESTRUCTIVE_SHIFT
3317 // The x86 shift operation is 'destructive'; it overwrites the
3318 // source register, so we need to make a copy first and use that.
3321 #if defined(HOST_IMM8)
3322 int ir=get_reg(i_regs->regmap,INVCP);
3324 emit_cmpmem_indexedsr12_reg(ir,addr,1);
3326 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
3328 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3329 emit_callne(invalidate_addr_reg[addr]);
3333 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),addr,0,0,0);
3338 add_stub(type,jaddr,(int)out,i,addr,(int)i_regs,ccadj[i],reglist);
3339 } else if(c&&!memtarget) {
3340 inline_writestub(type,i,constmap[i][s]+offset,i_regs->regmap,rs2[i],ccadj[i],reglist);
3342 //if(opcode[i]==0x2B || opcode[i]==0x3F)
3343 //if(opcode[i]==0x2B || opcode[i]==0x28)
3344 //if(opcode[i]==0x2B || opcode[i]==0x29)
3345 //if(opcode[i]==0x2B)
3346 /*if(opcode[i]==0x2B || opcode[i]==0x28 || opcode[i]==0x29 || opcode[i]==0x3F)
3354 emit_readword((int)&last_count,ECX);
3356 if(get_reg(i_regs->regmap,CCREG)<0)
3357 emit_loadreg(CCREG,HOST_CCREG);
3358 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3359 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3360 emit_writeword(HOST_CCREG,(int)&Count);
3363 if(get_reg(i_regs->regmap,CCREG)<0)
3364 emit_loadreg(CCREG,0);
3366 emit_mov(HOST_CCREG,0);
3368 emit_addimm(0,2*ccadj[i],0);
3369 emit_writeword(0,(int)&Count);
3371 emit_call((int)memdebug);
3376 restore_regs(0x100f);
3381 void storelr_assemble(int i,struct regstat *i_regs)
3388 int case1,case2,case3;
3389 int done0,done1,done2;
3390 int memtarget=0,c=0;
3391 int agr=AGEN1+(i&1);
3393 th=get_reg(i_regs->regmap,rs2[i]|64);
3394 tl=get_reg(i_regs->regmap,rs2[i]);
3395 s=get_reg(i_regs->regmap,rs1[i]);
3396 temp=get_reg(i_regs->regmap,agr);
3397 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3400 c=(i_regs->isconst>>s)&1;
3402 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3403 if(using_tlb&&((signed int)(constmap[i][s]+offset))>=(signed int)0xC0000000) memtarget=1;
3407 for(hr=0;hr<HOST_REGS;hr++) {
3408 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3413 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3414 if(!offset&&s!=temp) emit_mov(s,temp);
3420 if(!memtarget||!rs1[i]) {
3426 int map=get_reg(i_regs->regmap,ROREG);
3427 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3428 gen_tlb_addr_w(temp,map);
3430 if((u_int)rdram!=0x80000000)
3431 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3434 int map=get_reg(i_regs->regmap,TLREG);
3437 map=do_tlb_w(c||s<0||offset?temp:s,temp,map,0,c,constmap[i][s]+offset);
3438 if(!c&&!offset&&s>=0) emit_mov(s,temp);
3439 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr);
3440 if(!jaddr&&!memtarget) {
3444 gen_tlb_addr_w(temp,map);
3447 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3448 temp2=get_reg(i_regs->regmap,FTEMP);
3449 if(!rs2[i]) temp2=th=tl;
3452 #ifndef BIG_ENDIAN_MIPS
3453 emit_xorimm(temp,3,temp);
3455 emit_testimm(temp,2);
3458 emit_testimm(temp,1);
3462 if (opcode[i]==0x2A) { // SWL
3463 emit_writeword_indexed(tl,0,temp);
3465 if (opcode[i]==0x2E) { // SWR
3466 emit_writebyte_indexed(tl,3,temp);
3468 if (opcode[i]==0x2C) { // SDL
3469 emit_writeword_indexed(th,0,temp);
3470 if(rs2[i]) emit_mov(tl,temp2);
3472 if (opcode[i]==0x2D) { // SDR
3473 emit_writebyte_indexed(tl,3,temp);
3474 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3479 set_jump_target(case1,(int)out);
3480 if (opcode[i]==0x2A) { // SWL
3481 // Write 3 msb into three least significant bytes
3482 if(rs2[i]) emit_rorimm(tl,8,tl);
3483 emit_writehword_indexed(tl,-1,temp);
3484 if(rs2[i]) emit_rorimm(tl,16,tl);
3485 emit_writebyte_indexed(tl,1,temp);
3486 if(rs2[i]) emit_rorimm(tl,8,tl);
3488 if (opcode[i]==0x2E) { // SWR
3489 // Write two lsb into two most significant bytes
3490 emit_writehword_indexed(tl,1,temp);
3492 if (opcode[i]==0x2C) { // SDL
3493 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3494 // Write 3 msb into three least significant bytes
3495 if(rs2[i]) emit_rorimm(th,8,th);
3496 emit_writehword_indexed(th,-1,temp);
3497 if(rs2[i]) emit_rorimm(th,16,th);
3498 emit_writebyte_indexed(th,1,temp);
3499 if(rs2[i]) emit_rorimm(th,8,th);
3501 if (opcode[i]==0x2D) { // SDR
3502 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3503 // Write two lsb into two most significant bytes
3504 emit_writehword_indexed(tl,1,temp);
3509 set_jump_target(case2,(int)out);
3510 emit_testimm(temp,1);
3513 if (opcode[i]==0x2A) { // SWL
3514 // Write two msb into two least significant bytes
3515 if(rs2[i]) emit_rorimm(tl,16,tl);
3516 emit_writehword_indexed(tl,-2,temp);
3517 if(rs2[i]) emit_rorimm(tl,16,tl);
3519 if (opcode[i]==0x2E) { // SWR
3520 // Write 3 lsb into three most significant bytes
3521 emit_writebyte_indexed(tl,-1,temp);
3522 if(rs2[i]) emit_rorimm(tl,8,tl);
3523 emit_writehword_indexed(tl,0,temp);
3524 if(rs2[i]) emit_rorimm(tl,24,tl);
3526 if (opcode[i]==0x2C) { // SDL
3527 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3528 // Write two msb into two least significant bytes
3529 if(rs2[i]) emit_rorimm(th,16,th);
3530 emit_writehword_indexed(th,-2,temp);
3531 if(rs2[i]) emit_rorimm(th,16,th);
3533 if (opcode[i]==0x2D) { // SDR
3534 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3535 // Write 3 lsb into three most significant bytes
3536 emit_writebyte_indexed(tl,-1,temp);
3537 if(rs2[i]) emit_rorimm(tl,8,tl);
3538 emit_writehword_indexed(tl,0,temp);
3539 if(rs2[i]) emit_rorimm(tl,24,tl);
3544 set_jump_target(case3,(int)out);
3545 if (opcode[i]==0x2A) { // SWL
3546 // Write msb into least significant byte
3547 if(rs2[i]) emit_rorimm(tl,24,tl);
3548 emit_writebyte_indexed(tl,-3,temp);
3549 if(rs2[i]) emit_rorimm(tl,8,tl);
3551 if (opcode[i]==0x2E) { // SWR
3552 // Write entire word
3553 emit_writeword_indexed(tl,-3,temp);
3555 if (opcode[i]==0x2C) { // SDL
3556 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3557 // Write msb into least significant byte
3558 if(rs2[i]) emit_rorimm(th,24,th);
3559 emit_writebyte_indexed(th,-3,temp);
3560 if(rs2[i]) emit_rorimm(th,8,th);
3562 if (opcode[i]==0x2D) { // SDR
3563 if(rs2[i]) emit_mov(th,temp2);
3564 // Write entire word
3565 emit_writeword_indexed(tl,-3,temp);
3567 set_jump_target(done0,(int)out);
3568 set_jump_target(done1,(int)out);
3569 set_jump_target(done2,(int)out);
3570 if (opcode[i]==0x2C) { // SDL
3571 emit_testimm(temp,4);
3574 emit_andimm(temp,~3,temp);
3575 emit_writeword_indexed(temp2,4,temp);
3576 set_jump_target(done0,(int)out);
3578 if (opcode[i]==0x2D) { // SDR
3579 emit_testimm(temp,4);
3582 emit_andimm(temp,~3,temp);
3583 emit_writeword_indexed(temp2,-4,temp);
3584 set_jump_target(done0,(int)out);
3587 add_stub(STORELR_STUB,jaddr,(int)out,i,(int)i_regs,temp,ccadj[i],reglist);
3588 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3590 int map=get_reg(i_regs->regmap,ROREG);
3591 if(map<0) map=HOST_TEMPREG;
3592 gen_orig_addr_w(temp,map);
3594 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3596 #if defined(HOST_IMM8)
3597 int ir=get_reg(i_regs->regmap,INVCP);
3599 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3601 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3603 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3604 emit_callne(invalidate_addr_reg[temp]);
3608 add_stub(INVCODE_STUB,jaddr2,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3613 //save_regs(0x100f);
3614 emit_readword((int)&last_count,ECX);
3615 if(get_reg(i_regs->regmap,CCREG)<0)
3616 emit_loadreg(CCREG,HOST_CCREG);
3617 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3618 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3619 emit_writeword(HOST_CCREG,(int)&Count);
3620 emit_call((int)memdebug);
3622 //restore_regs(0x100f);
3626 void c1ls_assemble(int i,struct regstat *i_regs)
3628 #ifndef DISABLE_COP1
3634 int jaddr,jaddr2=0,jaddr3,type;
3635 int agr=AGEN1+(i&1);
3637 th=get_reg(i_regs->regmap,FTEMP|64);
3638 tl=get_reg(i_regs->regmap,FTEMP);
3639 s=get_reg(i_regs->regmap,rs1[i]);
3640 temp=get_reg(i_regs->regmap,agr);
3641 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3646 for(hr=0;hr<HOST_REGS;hr++) {
3647 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3649 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
3650 if (opcode[i]==0x31||opcode[i]==0x35) // LWC1/LDC1
3652 // Loads use a temporary register which we need to save
3655 if (opcode[i]==0x39||opcode[i]==0x3D) // SWC1/SDC1
3659 //if(s<0) emit_loadreg(rs1[i],ar); //address_generation does this now
3660 //else c=(i_regs->wasconst>>s)&1;
3661 if(s>=0) c=(i_regs->wasconst>>s)&1;
3662 // Check cop1 unusable
3664 signed char rs=get_reg(i_regs->regmap,CSREG);
3666 emit_testimm(rs,0x20000000);
3669 add_stub(FP_STUB,jaddr,(int)out,i,rs,(int)i_regs,is_delayslot,0);
3672 if (opcode[i]==0x39) { // SWC1 (get float address)
3673 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],tl);
3675 if (opcode[i]==0x3D) { // SDC1 (get double address)
3676 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],tl);
3678 // Generate address + offset
3681 emit_cmpimm(offset||c||s<0?ar:s,RAM_SIZE);
3685 map=get_reg(i_regs->regmap,TLREG);
3688 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3689 map=do_tlb_r(offset||c||s<0?ar:s,ar,map,0,-1,-1,c,constmap[i][s]+offset);
3691 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3692 map=do_tlb_w(offset||c||s<0?ar:s,ar,map,0,c,constmap[i][s]+offset);
3695 if (opcode[i]==0x39) { // SWC1 (read float)
3696 emit_readword_indexed(0,tl,tl);
3698 if (opcode[i]==0x3D) { // SDC1 (read double)
3699 emit_readword_indexed(4,tl,th);
3700 emit_readword_indexed(0,tl,tl);
3702 if (opcode[i]==0x31) { // LWC1 (get target address)
3703 emit_readword((int)®_cop1_simple[(source[i]>>16)&0x1f],temp);
3705 if (opcode[i]==0x35) { // LDC1 (get target address)
3706 emit_readword((int)®_cop1_double[(source[i]>>16)&0x1f],temp);
3713 else if(((signed int)(constmap[i][s]+offset))>=(signed int)0x80000000+RAM_SIZE) {
3715 emit_jmp(0); // inline_readstub/inline_writestub? Very rare case
3717 #ifdef DESTRUCTIVE_SHIFT
3718 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3719 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3723 if (opcode[i]==0x31||opcode[i]==0x35) { // LWC1/LDC1
3724 do_tlb_r_branch(map,c,constmap[i][s]+offset,&jaddr2);
3726 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3727 do_tlb_w_branch(map,c,constmap[i][s]+offset,&jaddr2);
3730 if (opcode[i]==0x31) { // LWC1
3731 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3732 //gen_tlb_addr_r(ar,map);
3733 //emit_readword_indexed((int)rdram-0x80000000,tl,tl);
3734 #ifdef HOST_IMM_ADDR32
3735 if(c) emit_readword_tlb(constmap[i][s]+offset,map,tl);
3738 emit_readword_indexed_tlb(0,offset||c||s<0?tl:s,map,tl);
3741 if (opcode[i]==0x35) { // LDC1
3743 //if(s>=0&&!c&&!offset) emit_mov(s,tl);
3744 //gen_tlb_addr_r(ar,map);
3745 //emit_readword_indexed((int)rdram-0x80000000,tl,th);
3746 //emit_readword_indexed((int)rdram-0x7FFFFFFC,tl,tl);
3747 #ifdef HOST_IMM_ADDR32
3748 if(c) emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
3751 emit_readdword_indexed_tlb(0,offset||c||s<0?tl:s,map,th,tl);
3754 if (opcode[i]==0x39) { // SWC1
3755 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
3756 emit_writeword_indexed_tlb(tl,0,offset||c||s<0?temp:s,map,temp);
3759 if (opcode[i]==0x3D) { // SDC1
3761 //emit_writeword_indexed(th,(int)rdram-0x80000000,temp);
3762 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
3763 emit_writedword_indexed_tlb(th,tl,0,offset||c||s<0?temp:s,map,temp);
3766 if(!using_tlb&&!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3767 if (opcode[i]==0x39||opcode[i]==0x3D) { // SWC1/SDC1
3768 #ifndef DESTRUCTIVE_SHIFT
3769 temp=offset||c||s<0?ar:s;
3771 #if defined(HOST_IMM8)
3772 int ir=get_reg(i_regs->regmap,INVCP);
3774 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3776 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3778 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3779 emit_callne(invalidate_addr_reg[temp]);
3783 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3787 if(jaddr2) add_stub(type,jaddr2,(int)out,i,offset||c||s<0?ar:s,(int)i_regs,ccadj[i],reglist);
3788 if (opcode[i]==0x31) { // LWC1 (write float)
3789 emit_writeword_indexed(tl,0,temp);
3791 if (opcode[i]==0x35) { // LDC1 (write double)
3792 emit_writeword_indexed(th,4,temp);
3793 emit_writeword_indexed(tl,0,temp);
3795 //if(opcode[i]==0x39)
3796 /*if(opcode[i]==0x39||opcode[i]==0x31)
3799 emit_readword((int)&last_count,ECX);
3800 if(get_reg(i_regs->regmap,CCREG)<0)
3801 emit_loadreg(CCREG,HOST_CCREG);
3802 emit_add(HOST_CCREG,ECX,HOST_CCREG);
3803 emit_addimm(HOST_CCREG,2*ccadj[i],HOST_CCREG);
3804 emit_writeword(HOST_CCREG,(int)&Count);
3805 emit_call((int)memdebug);
3809 cop1_unusable(i, i_regs);
3813 void c2ls_assemble(int i,struct regstat *i_regs)
3818 int memtarget=0,c=0;
3819 int jaddr2=0,jaddr3,type;
3820 int agr=AGEN1+(i&1);
3821 int fastio_reg_override=0;
3823 u_int copr=(source[i]>>16)&0x1f;
3824 s=get_reg(i_regs->regmap,rs1[i]);
3825 tl=get_reg(i_regs->regmap,FTEMP);
3831 for(hr=0;hr<HOST_REGS;hr++) {
3832 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3834 if(i_regs->regmap[HOST_CCREG]==CCREG)
3835 reglist&=~(1<<HOST_CCREG);
3838 if (opcode[i]==0x3a) { // SWC2
3839 ar=get_reg(i_regs->regmap,agr);
3840 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3845 if(s>=0) c=(i_regs->wasconst>>s)&1;
3846 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3847 if (!offset&&!c&&s>=0) ar=s;
3850 if (opcode[i]==0x3a) { // SWC2
3851 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3859 emit_jmp(0); // inline_readstub/inline_writestub?
3863 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3865 if (opcode[i]==0x32) { // LWC2
3866 #ifdef HOST_IMM_ADDR32
3867 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3871 if(fastio_reg_override) a=fastio_reg_override;
3872 emit_readword_indexed(0,a,tl);
3874 if (opcode[i]==0x3a) { // SWC2
3875 #ifdef DESTRUCTIVE_SHIFT
3876 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3879 if(fastio_reg_override) a=fastio_reg_override;
3880 emit_writeword_indexed(tl,0,a);
3884 add_stub(type,jaddr2,(int)out,i,ar,(int)i_regs,ccadj[i],reglist);
3885 if(opcode[i]==0x3a) // SWC2
3886 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3887 #if defined(HOST_IMM8)
3888 int ir=get_reg(i_regs->regmap,INVCP);
3890 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3892 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3894 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3895 emit_callne(invalidate_addr_reg[ar]);
3899 add_stub(INVCODE_STUB,jaddr3,(int)out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3902 if (opcode[i]==0x32) { // LWC2
3903 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3907 #ifndef multdiv_assemble
3908 void multdiv_assemble(int i,struct regstat *i_regs)
3910 printf("Need multdiv_assemble for this architecture.\n");
3915 void mov_assemble(int i,struct regstat *i_regs)
3917 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3918 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3920 signed char sh,sl,th,tl;
3921 th=get_reg(i_regs->regmap,rt1[i]|64);
3922 tl=get_reg(i_regs->regmap,rt1[i]);
3925 sh=get_reg(i_regs->regmap,rs1[i]|64);
3926 sl=get_reg(i_regs->regmap,rs1[i]);
3927 if(sl>=0) emit_mov(sl,tl);
3928 else emit_loadreg(rs1[i],tl);
3930 if(sh>=0) emit_mov(sh,th);
3931 else emit_loadreg(rs1[i]|64,th);
3937 #ifndef fconv_assemble
3938 void fconv_assemble(int i,struct regstat *i_regs)
3940 printf("Need fconv_assemble for this architecture.\n");
3946 void float_assemble(int i,struct regstat *i_regs)
3948 printf("Need float_assemble for this architecture.\n");
3953 void syscall_assemble(int i,struct regstat *i_regs)
3955 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3956 assert(ccreg==HOST_CCREG);
3957 assert(!is_delayslot);
3958 emit_movimm(start+i*4,EAX); // Get PC
3959 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3960 emit_jmp((int)jump_syscall_hle); // XXX
3963 void hlecall_assemble(int i,struct regstat *i_regs)
3965 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3966 assert(ccreg==HOST_CCREG);
3967 assert(!is_delayslot);
3968 emit_movimm(start+i*4+4,0); // Get PC
3969 emit_movimm((int)psxHLEt[source[i]&7],1);
3970 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3971 emit_jmp((int)jump_hlecall);
3974 void intcall_assemble(int i,struct regstat *i_regs)
3976 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3977 assert(ccreg==HOST_CCREG);
3978 assert(!is_delayslot);
3979 emit_movimm(start+i*4,0); // Get PC
3980 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3981 emit_jmp((int)jump_intcall);
3984 void ds_assemble(int i,struct regstat *i_regs)
3986 speculate_register_values(i);
3990 alu_assemble(i,i_regs);break;
3992 imm16_assemble(i,i_regs);break;
3994 shift_assemble(i,i_regs);break;
3996 shiftimm_assemble(i,i_regs);break;
3998 load_assemble(i,i_regs);break;
4000 loadlr_assemble(i,i_regs);break;
4002 store_assemble(i,i_regs);break;
4004 storelr_assemble(i,i_regs);break;
4006 cop0_assemble(i,i_regs);break;
4008 cop1_assemble(i,i_regs);break;
4010 c1ls_assemble(i,i_regs);break;
4012 cop2_assemble(i,i_regs);break;
4014 c2ls_assemble(i,i_regs);break;
4016 c2op_assemble(i,i_regs);break;
4018 fconv_assemble(i,i_regs);break;
4020 float_assemble(i,i_regs);break;
4022 fcomp_assemble(i,i_regs);break;
4024 multdiv_assemble(i,i_regs);break;
4026 mov_assemble(i,i_regs);break;
4036 printf("Jump in the delay slot. This is probably a bug.\n");
4041 // Is the branch target a valid internal jump?
4042 int internal_branch(uint64_t i_is32,int addr)
4044 if(addr&1) return 0; // Indirect (register) jump
4045 if(addr>=start && addr<start+slen*4-4)
4047 int t=(addr-start)>>2;
4048 // Delay slots are not valid branch targets
4049 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4050 // 64 -> 32 bit transition requires a recompile
4051 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
4053 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
4054 else printf("optimizable: yes\n");
4056 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4058 if(requires_32bit[t]&~i_is32) return 0;
4066 #ifndef wb_invalidate
4067 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
4068 uint64_t u,uint64_t uu)
4071 for(hr=0;hr<HOST_REGS;hr++) {
4072 if(hr!=EXCLUDE_REG) {
4073 if(pre[hr]!=entry[hr]) {
4076 if(get_reg(entry,pre[hr])<0) {
4078 if(!((u>>pre[hr])&1)) {
4079 emit_storereg(pre[hr],hr);
4080 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
4081 emit_sarimm(hr,31,hr);
4082 emit_storereg(pre[hr]|64,hr);
4086 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
4087 emit_storereg(pre[hr],hr);
4096 // Move from one register to another (no writeback)
4097 for(hr=0;hr<HOST_REGS;hr++) {
4098 if(hr!=EXCLUDE_REG) {
4099 if(pre[hr]!=entry[hr]) {
4100 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
4102 if((nr=get_reg(entry,pre[hr]))>=0) {
4112 // Load the specified registers
4113 // This only loads the registers given as arguments because
4114 // we don't want to load things that will be overwritten
4115 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
4119 for(hr=0;hr<HOST_REGS;hr++) {
4120 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4121 if(entry[hr]!=regmap[hr]) {
4122 if(regmap[hr]==rs1||regmap[hr]==rs2)
4129 emit_loadreg(regmap[hr],hr);
4136 for(hr=0;hr<HOST_REGS;hr++) {
4137 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4138 if(entry[hr]!=regmap[hr]) {
4139 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
4141 assert(regmap[hr]!=64);
4142 if((is32>>(regmap[hr]&63))&1) {
4143 int lr=get_reg(regmap,regmap[hr]-64);
4145 emit_sarimm(lr,31,hr);
4147 emit_loadreg(regmap[hr],hr);
4151 emit_loadreg(regmap[hr],hr);
4159 // Load registers prior to the start of a loop
4160 // so that they are not loaded within the loop
4161 static void loop_preload(signed char pre[],signed char entry[])
4164 for(hr=0;hr<HOST_REGS;hr++) {
4165 if(hr!=EXCLUDE_REG) {
4166 if(pre[hr]!=entry[hr]) {
4168 if(get_reg(pre,entry[hr])<0) {
4169 assem_debug("loop preload:\n");
4170 //printf("loop preload: %d\n",hr);
4174 else if(entry[hr]<TEMPREG)
4176 emit_loadreg(entry[hr],hr);
4178 else if(entry[hr]-64<TEMPREG)
4180 emit_loadreg(entry[hr],hr);
4189 // Generate address for load/store instruction
4190 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
4191 void address_generation(int i,struct regstat *i_regs,signed char entry[])
4193 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
4195 int agr=AGEN1+(i&1);
4196 int mgr=MGEN1+(i&1);
4197 if(itype[i]==LOAD) {
4198 ra=get_reg(i_regs->regmap,rt1[i]);
4199 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4202 if(itype[i]==LOADLR) {
4203 ra=get_reg(i_regs->regmap,FTEMP);
4205 if(itype[i]==STORE||itype[i]==STORELR) {
4206 ra=get_reg(i_regs->regmap,agr);
4207 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4209 if(itype[i]==C1LS||itype[i]==C2LS) {
4210 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
4211 ra=get_reg(i_regs->regmap,FTEMP);
4212 else { // SWC1/SDC1/SWC2/SDC2
4213 ra=get_reg(i_regs->regmap,agr);
4214 if(ra<0) ra=get_reg(i_regs->regmap,-1);
4217 int rs=get_reg(i_regs->regmap,rs1[i]);
4218 int rm=get_reg(i_regs->regmap,TLREG);
4221 int c=(i_regs->wasconst>>rs)&1;
4223 // Using r0 as a base address
4225 if(!entry||entry[rm]!=mgr) {
4226 generate_map_const(offset,rm);
4227 } // else did it in the previous cycle
4229 if(!entry||entry[ra]!=agr) {
4230 if (opcode[i]==0x22||opcode[i]==0x26) {
4231 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4232 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4233 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4235 emit_movimm(offset,ra);
4237 } // else did it in the previous cycle
4240 if(!entry||entry[ra]!=rs1[i])
4241 emit_loadreg(rs1[i],ra);
4242 //if(!entry||entry[ra]!=rs1[i])
4243 // printf("poor load scheduling!\n");
4248 if(!entry||entry[rm]!=mgr) {
4249 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a) {
4250 // Stores to memory go thru the mapper to detect self-modifying
4251 // code, loads don't.
4252 if((unsigned int)(constmap[i][rs]+offset)>=0xC0000000 ||
4253 (unsigned int)(constmap[i][rs]+offset)<0x80000000+RAM_SIZE )
4254 generate_map_const(constmap[i][rs]+offset,rm);
4256 if((signed int)(constmap[i][rs]+offset)>=(signed int)0xC0000000)
4257 generate_map_const(constmap[i][rs]+offset,rm);
4262 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
4263 if(!entry||entry[ra]!=agr) {
4264 if (opcode[i]==0x22||opcode[i]==0x26) {
4265 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4266 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
4267 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4269 #ifdef HOST_IMM_ADDR32
4270 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4271 (using_tlb&&((signed int)constmap[i][rs]+offset)>=(signed int)0xC0000000))
4273 emit_movimm(constmap[i][rs]+offset,ra);
4274 regs[i].loadedconst|=1<<ra;
4276 } // else did it in the previous cycle
4277 } // else load_consts already did it
4279 if(offset&&!c&&rs1[i]) {
4281 emit_addimm(rs,offset,ra);
4283 emit_addimm(ra,offset,ra);
4288 // Preload constants for next instruction
4289 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
4291 #if !defined(HOST_IMM_ADDR32) && !defined(DISABLE_TLB)
4293 agr=MGEN1+((i+1)&1);
4294 ra=get_reg(i_regs->regmap,agr);
4296 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4297 int offset=imm[i+1];
4298 int c=(regs[i+1].wasconst>>rs)&1;
4300 if(itype[i+1]==STORE||itype[i+1]==STORELR
4301 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1, SWC2/SDC2
4302 // Stores to memory go thru the mapper to detect self-modifying
4303 // code, loads don't.
4304 if((unsigned int)(constmap[i+1][rs]+offset)>=0xC0000000 ||
4305 (unsigned int)(constmap[i+1][rs]+offset)<0x80000000+RAM_SIZE )
4306 generate_map_const(constmap[i+1][rs]+offset,ra);
4308 if((signed int)(constmap[i+1][rs]+offset)>=(signed int)0xC0000000)
4309 generate_map_const(constmap[i+1][rs]+offset,ra);
4312 /*else if(rs1[i]==0) {
4313 generate_map_const(offset,ra);
4318 agr=AGEN1+((i+1)&1);
4319 ra=get_reg(i_regs->regmap,agr);
4321 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
4322 int offset=imm[i+1];
4323 int c=(regs[i+1].wasconst>>rs)&1;
4324 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
4325 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4326 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
4327 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4328 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
4330 #ifdef HOST_IMM_ADDR32
4331 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32) || // LWC1/LDC1/LWC2/LDC2
4332 (using_tlb&&((signed int)constmap[i+1][rs]+offset)>=(signed int)0xC0000000))
4334 emit_movimm(constmap[i+1][rs]+offset,ra);
4335 regs[i+1].loadedconst|=1<<ra;
4338 else if(rs1[i+1]==0) {
4339 // Using r0 as a base address
4340 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
4341 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
4342 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
4343 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
4345 emit_movimm(offset,ra);
4352 int get_final_value(int hr, int i, int *value)
4354 int reg=regs[i].regmap[hr];
4356 if(regs[i+1].regmap[hr]!=reg) break;
4357 if(!((regs[i+1].isconst>>hr)&1)) break;
4362 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
4363 *value=constmap[i][hr];
4367 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
4368 // Load in delay slot, out-of-order execution
4369 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
4371 #ifdef HOST_IMM_ADDR32
4372 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+2])<(signed int)0xC0000000) return 0;
4374 // Precompute load address
4375 *value=constmap[i][hr]+imm[i+2];
4379 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
4381 #ifdef HOST_IMM_ADDR32
4382 if(!using_tlb||((signed int)constmap[i][hr]+imm[i+1])<(signed int)0xC0000000) return 0;
4384 // Precompute load address
4385 *value=constmap[i][hr]+imm[i+1];
4386 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
4391 *value=constmap[i][hr];
4392 //printf("c=%x\n",(int)constmap[i][hr]);
4393 if(i==slen-1) return 1;
4395 return !((unneeded_reg[i+1]>>reg)&1);
4397 return !((unneeded_reg_upper[i+1]>>reg)&1);
4401 // Load registers with known constants
4402 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
4405 // propagate loaded constant flags
4407 regs[i].loadedconst=0;
4409 for(hr=0;hr<HOST_REGS;hr++) {
4410 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
4411 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
4413 regs[i].loadedconst|=1<<hr;
4418 for(hr=0;hr<HOST_REGS;hr++) {
4419 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4420 //if(entry[hr]!=regmap[hr]) {
4421 if(!((regs[i].loadedconst>>hr)&1)) {
4422 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4423 int value,similar=0;
4424 if(get_final_value(hr,i,&value)) {
4425 // see if some other register has similar value
4426 for(hr2=0;hr2<HOST_REGS;hr2++) {
4427 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
4428 if(is_similar_value(value,constmap[i][hr2])) {
4436 if(get_final_value(hr2,i,&value2)) // is this needed?
4437 emit_movimm_from(value2,hr2,value,hr);
4439 emit_movimm(value,hr);
4445 emit_movimm(value,hr);
4448 regs[i].loadedconst|=1<<hr;
4454 for(hr=0;hr<HOST_REGS;hr++) {
4455 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
4456 //if(entry[hr]!=regmap[hr]) {
4457 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
4458 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4459 if((is32>>(regmap[hr]&63))&1) {
4460 int lr=get_reg(regmap,regmap[hr]-64);
4462 emit_sarimm(lr,31,hr);
4467 if(get_final_value(hr,i,&value)) {
4472 emit_movimm(value,hr);
4481 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
4485 for(hr=0;hr<HOST_REGS;hr++) {
4486 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4487 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
4488 int value=constmap[i][hr];
4493 emit_movimm(value,hr);
4499 for(hr=0;hr<HOST_REGS;hr++) {
4500 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
4501 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
4502 if((is32>>(regmap[hr]&63))&1) {
4503 int lr=get_reg(regmap,regmap[hr]-64);
4505 emit_sarimm(lr,31,hr);
4509 int value=constmap[i][hr];
4514 emit_movimm(value,hr);
4522 // Write out all dirty registers (except cycle count)
4523 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
4526 for(hr=0;hr<HOST_REGS;hr++) {
4527 if(hr!=EXCLUDE_REG) {
4528 if(i_regmap[hr]>0) {
4529 if(i_regmap[hr]!=CCREG) {
4530 if((i_dirty>>hr)&1) {
4531 if(i_regmap[hr]<64) {
4532 emit_storereg(i_regmap[hr],hr);
4534 if( ((i_is32>>i_regmap[hr])&1) ) {
4535 #ifdef DESTRUCTIVE_WRITEBACK
4536 emit_sarimm(hr,31,hr);
4537 emit_storereg(i_regmap[hr]|64,hr);
4539 emit_sarimm(hr,31,HOST_TEMPREG);
4540 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4545 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4546 emit_storereg(i_regmap[hr],hr);
4555 // Write out dirty registers that we need to reload (pair with load_needed_regs)
4556 // This writes the registers not written by store_regs_bt
4557 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4560 int t=(addr-start)>>2;
4561 for(hr=0;hr<HOST_REGS;hr++) {
4562 if(hr!=EXCLUDE_REG) {
4563 if(i_regmap[hr]>0) {
4564 if(i_regmap[hr]!=CCREG) {
4565 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4566 if((i_dirty>>hr)&1) {
4567 if(i_regmap[hr]<64) {
4568 emit_storereg(i_regmap[hr],hr);
4570 if( ((i_is32>>i_regmap[hr])&1) ) {
4571 #ifdef DESTRUCTIVE_WRITEBACK
4572 emit_sarimm(hr,31,hr);
4573 emit_storereg(i_regmap[hr]|64,hr);
4575 emit_sarimm(hr,31,HOST_TEMPREG);
4576 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4581 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
4582 emit_storereg(i_regmap[hr],hr);
4593 // Load all registers (except cycle count)
4594 void load_all_regs(signed char i_regmap[])
4597 for(hr=0;hr<HOST_REGS;hr++) {
4598 if(hr!=EXCLUDE_REG) {
4599 if(i_regmap[hr]==0) {
4603 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4605 emit_loadreg(i_regmap[hr],hr);
4611 // Load all current registers also needed by next instruction
4612 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
4615 for(hr=0;hr<HOST_REGS;hr++) {
4616 if(hr!=EXCLUDE_REG) {
4617 if(get_reg(next_regmap,i_regmap[hr])>=0) {
4618 if(i_regmap[hr]==0) {
4622 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
4624 emit_loadreg(i_regmap[hr],hr);
4631 // Load all regs, storing cycle count if necessary
4632 void load_regs_entry(int t)
4635 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
4636 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
4637 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4638 emit_storereg(CCREG,HOST_CCREG);
4641 for(hr=0;hr<HOST_REGS;hr++) {
4642 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4643 if(regs[t].regmap_entry[hr]==0) {
4646 else if(regs[t].regmap_entry[hr]!=CCREG)
4648 emit_loadreg(regs[t].regmap_entry[hr],hr);
4653 for(hr=0;hr<HOST_REGS;hr++) {
4654 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4655 assert(regs[t].regmap_entry[hr]!=64);
4656 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
4657 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4659 emit_loadreg(regs[t].regmap_entry[hr],hr);
4663 emit_sarimm(lr,31,hr);
4668 emit_loadreg(regs[t].regmap_entry[hr],hr);
4674 // Store dirty registers prior to branch
4675 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4677 if(internal_branch(i_is32,addr))
4679 int t=(addr-start)>>2;
4681 for(hr=0;hr<HOST_REGS;hr++) {
4682 if(hr!=EXCLUDE_REG) {
4683 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4684 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4685 if((i_dirty>>hr)&1) {
4686 if(i_regmap[hr]<64) {
4687 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4688 emit_storereg(i_regmap[hr],hr);
4689 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4690 #ifdef DESTRUCTIVE_WRITEBACK
4691 emit_sarimm(hr,31,hr);
4692 emit_storereg(i_regmap[hr]|64,hr);
4694 emit_sarimm(hr,31,HOST_TEMPREG);
4695 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4700 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4701 emit_storereg(i_regmap[hr],hr);
4712 // Branch out of this block, write out all dirty regs
4713 wb_dirtys(i_regmap,i_is32,i_dirty);
4717 // Load all needed registers for branch target
4718 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4720 //if(addr>=start && addr<(start+slen*4))
4721 if(internal_branch(i_is32,addr))
4723 int t=(addr-start)>>2;
4725 // Store the cycle count before loading something else
4726 if(i_regmap[HOST_CCREG]!=CCREG) {
4727 assert(i_regmap[HOST_CCREG]==-1);
4729 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4730 emit_storereg(CCREG,HOST_CCREG);
4733 for(hr=0;hr<HOST_REGS;hr++) {
4734 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4735 #ifdef DESTRUCTIVE_WRITEBACK
4736 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4738 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4740 if(regs[t].regmap_entry[hr]==0) {
4743 else if(regs[t].regmap_entry[hr]!=CCREG)
4745 emit_loadreg(regs[t].regmap_entry[hr],hr);
4751 for(hr=0;hr<HOST_REGS;hr++) {
4752 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4753 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4754 assert(regs[t].regmap_entry[hr]!=64);
4755 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4756 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4758 emit_loadreg(regs[t].regmap_entry[hr],hr);
4762 emit_sarimm(lr,31,hr);
4767 emit_loadreg(regs[t].regmap_entry[hr],hr);
4770 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4771 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4773 emit_sarimm(lr,31,hr);
4780 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4782 if(addr>=start && addr<start+slen*4-4)
4784 int t=(addr-start)>>2;
4786 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4787 for(hr=0;hr<HOST_REGS;hr++)
4791 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4793 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4800 if(i_regmap[hr]<TEMPREG)
4802 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4805 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4807 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4812 else // Same register but is it 32-bit or dirty?
4815 if(!((regs[t].dirty>>hr)&1))
4819 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4821 //printf("%x: dirty no match\n",addr);
4826 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4828 //printf("%x: is32 no match\n",addr);
4834 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4836 if(requires_32bit[t]&~i_is32) return 0;
4838 // Delay slots are not valid branch targets
4839 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4840 // Delay slots require additional processing, so do not match
4841 if(is_ds[t]) return 0;
4846 for(hr=0;hr<HOST_REGS;hr++)
4852 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4866 // Used when a branch jumps into the delay slot of another branch
4867 void ds_assemble_entry(int i)
4869 int t=(ba[i]-start)>>2;
4870 if(!instr_addr[t]) instr_addr[t]=(u_int)out;
4871 assem_debug("Assemble delay slot at %x\n",ba[i]);
4872 assem_debug("<->\n");
4873 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4874 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4875 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4876 address_generation(t,®s[t],regs[t].regmap_entry);
4877 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4878 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4883 alu_assemble(t,®s[t]);break;
4885 imm16_assemble(t,®s[t]);break;
4887 shift_assemble(t,®s[t]);break;
4889 shiftimm_assemble(t,®s[t]);break;
4891 load_assemble(t,®s[t]);break;
4893 loadlr_assemble(t,®s[t]);break;
4895 store_assemble(t,®s[t]);break;
4897 storelr_assemble(t,®s[t]);break;
4899 cop0_assemble(t,®s[t]);break;
4901 cop1_assemble(t,®s[t]);break;
4903 c1ls_assemble(t,®s[t]);break;
4905 cop2_assemble(t,®s[t]);break;
4907 c2ls_assemble(t,®s[t]);break;
4909 c2op_assemble(t,®s[t]);break;
4911 fconv_assemble(t,®s[t]);break;
4913 float_assemble(t,®s[t]);break;
4915 fcomp_assemble(t,®s[t]);break;
4917 multdiv_assemble(t,®s[t]);break;
4919 mov_assemble(t,®s[t]);break;
4929 printf("Jump in the delay slot. This is probably a bug.\n");
4931 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4932 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4933 if(internal_branch(regs[t].is32,ba[i]+4))
4934 assem_debug("branch: internal\n");
4936 assem_debug("branch: external\n");
4937 assert(internal_branch(regs[t].is32,ba[i]+4));
4938 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4942 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4951 //if(ba[i]>=start && ba[i]<(start+slen*4))
4952 if(internal_branch(branch_regs[i].is32,ba[i]))
4954 int t=(ba[i]-start)>>2;
4955 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4963 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4965 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4967 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4968 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4972 else if(*adj==0||invert) {
4973 emit_addimm_and_set_flags(CLOCK_ADJUST(count+2),HOST_CCREG);
4979 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4983 add_stub(CC_STUB,jaddr,idle?idle:(int)out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4986 void do_ccstub(int n)
4989 assem_debug("do_ccstub %x\n",start+stubs[n][4]*4);
4990 set_jump_target(stubs[n][1],(int)out);
4992 if(stubs[n][6]==NULLDS) {
4993 // Delay slot instruction is nullified ("likely" branch)
4994 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4996 else if(stubs[n][6]!=TAKEN) {
4997 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
5000 if(internal_branch(branch_regs[i].is32,ba[i]))
5001 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5005 // Save PC as return address
5006 emit_movimm(stubs[n][5],EAX);
5007 emit_writeword(EAX,(int)&pcaddr);
5011 // Return address depends on which way the branch goes
5012 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
5014 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5015 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5016 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5017 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5027 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
5031 #ifdef DESTRUCTIVE_WRITEBACK
5033 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
5034 emit_loadreg(rs1[i],s1l);
5037 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
5038 emit_loadreg(rs2[i],s1l);
5041 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
5042 emit_loadreg(rs2[i],s2l);
5045 int addr=-1,alt=-1,ntaddr=-1;
5048 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5049 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5050 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5058 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5059 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5060 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5066 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5070 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5071 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
5072 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
5078 assert(hr<HOST_REGS);
5080 if((opcode[i]&0x2f)==4) // BEQ
5082 #ifdef HAVE_CMOV_IMM
5084 if(s2l>=0) emit_cmp(s1l,s2l);
5085 else emit_test(s1l,s1l);
5086 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5091 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5093 if(s2h>=0) emit_cmp(s1h,s2h);
5094 else emit_test(s1h,s1h);
5095 emit_cmovne_reg(alt,addr);
5097 if(s2l>=0) emit_cmp(s1l,s2l);
5098 else emit_test(s1l,s1l);
5099 emit_cmovne_reg(alt,addr);
5102 if((opcode[i]&0x2f)==5) // BNE
5104 #ifdef HAVE_CMOV_IMM
5106 if(s2l>=0) emit_cmp(s1l,s2l);
5107 else emit_test(s1l,s1l);
5108 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5113 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5115 if(s2h>=0) emit_cmp(s1h,s2h);
5116 else emit_test(s1h,s1h);
5117 emit_cmovne_reg(alt,addr);
5119 if(s2l>=0) emit_cmp(s1l,s2l);
5120 else emit_test(s1l,s1l);
5121 emit_cmovne_reg(alt,addr);
5124 if((opcode[i]&0x2f)==6) // BLEZ
5126 //emit_movimm(ba[i],alt);
5127 //emit_movimm(start+i*4+8,addr);
5128 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5130 if(s1h>=0) emit_mov(addr,ntaddr);
5131 emit_cmovl_reg(alt,addr);
5134 emit_cmovne_reg(ntaddr,addr);
5135 emit_cmovs_reg(alt,addr);
5138 if((opcode[i]&0x2f)==7) // BGTZ
5140 //emit_movimm(ba[i],addr);
5141 //emit_movimm(start+i*4+8,ntaddr);
5142 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5144 if(s1h>=0) emit_mov(addr,alt);
5145 emit_cmovl_reg(ntaddr,addr);
5148 emit_cmovne_reg(alt,addr);
5149 emit_cmovs_reg(ntaddr,addr);
5152 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
5154 //emit_movimm(ba[i],alt);
5155 //emit_movimm(start+i*4+8,addr);
5156 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5157 if(s1h>=0) emit_test(s1h,s1h);
5158 else emit_test(s1l,s1l);
5159 emit_cmovs_reg(alt,addr);
5161 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
5163 //emit_movimm(ba[i],addr);
5164 //emit_movimm(start+i*4+8,alt);
5165 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5166 if(s1h>=0) emit_test(s1h,s1h);
5167 else emit_test(s1l,s1l);
5168 emit_cmovs_reg(alt,addr);
5170 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5171 if(source[i]&0x10000) // BC1T
5173 //emit_movimm(ba[i],alt);
5174 //emit_movimm(start+i*4+8,addr);
5175 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5176 emit_testimm(s1l,0x800000);
5177 emit_cmovne_reg(alt,addr);
5181 //emit_movimm(ba[i],addr);
5182 //emit_movimm(start+i*4+8,alt);
5183 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5184 emit_testimm(s1l,0x800000);
5185 emit_cmovne_reg(alt,addr);
5188 emit_writeword(addr,(int)&pcaddr);
5193 int r=get_reg(branch_regs[i].regmap,rs1[i]);
5194 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5195 r=get_reg(branch_regs[i].regmap,RTEMP);
5197 emit_writeword(r,(int)&pcaddr);
5199 else {printf("Unknown branch type in do_ccstub\n");exit(1);}
5201 // Update cycle count
5202 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
5203 if(stubs[n][3]) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5204 emit_call((int)cc_interrupt);
5205 if(stubs[n][3]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n][3]),HOST_CCREG);
5206 if(stubs[n][6]==TAKEN) {
5207 if(internal_branch(branch_regs[i].is32,ba[i]))
5208 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
5209 else if(itype[i]==RJUMP) {
5210 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
5211 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
5213 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
5215 }else if(stubs[n][6]==NOTTAKEN) {
5216 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
5217 else load_all_regs(branch_regs[i].regmap);
5218 }else if(stubs[n][6]==NULLDS) {
5219 // Delay slot instruction is nullified ("likely" branch)
5220 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
5221 else load_all_regs(regs[i].regmap);
5223 load_all_regs(branch_regs[i].regmap);
5225 emit_jmp(stubs[n][2]); // return address
5227 /* This works but uses a lot of memory...
5228 emit_readword((int)&last_count,ECX);
5229 emit_add(HOST_CCREG,ECX,EAX);
5230 emit_writeword(EAX,(int)&Count);
5231 emit_call((int)gen_interupt);
5232 emit_readword((int)&Count,HOST_CCREG);
5233 emit_readword((int)&next_interupt,EAX);
5234 emit_readword((int)&pending_exception,EBX);
5235 emit_writeword(EAX,(int)&last_count);
5236 emit_sub(HOST_CCREG,EAX,HOST_CCREG);
5238 int jne_instr=(int)out;
5240 if(stubs[n][3]) emit_addimm(HOST_CCREG,-2*stubs[n][3],HOST_CCREG);
5241 load_all_regs(branch_regs[i].regmap);
5242 emit_jmp(stubs[n][2]); // return address
5243 set_jump_target(jne_instr,(int)out);
5244 emit_readword((int)&pcaddr,EAX);
5245 // Call get_addr_ht instead of doing the hash table here.
5246 // This code is executed infrequently and takes up a lot of space
5247 // so smaller is better.
5248 emit_storereg(CCREG,HOST_CCREG);
5250 emit_call((int)get_addr_ht);
5251 emit_loadreg(CCREG,HOST_CCREG);
5252 emit_addimm(ESP,4,ESP);
5256 add_to_linker(int addr,int target,int ext)
5258 link_addr[linkcount][0]=addr;
5259 link_addr[linkcount][1]=target;
5260 link_addr[linkcount][2]=ext;
5264 static void ujump_assemble_write_ra(int i)
5267 unsigned int return_address;
5268 rt=get_reg(branch_regs[i].regmap,31);
5269 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5271 return_address=start+i*4+8;
5274 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
5275 int temp=-1; // note: must be ds-safe
5279 if(temp>=0) do_miniht_insert(return_address,rt,temp);
5280 else emit_movimm(return_address,rt);
5288 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5291 emit_movimm(return_address,rt); // PC into link register
5293 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5299 void ujump_assemble(int i,struct regstat *i_regs)
5301 signed char *i_regmap=i_regs->regmap;
5303 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5304 address_generation(i+1,i_regs,regs[i].regmap_entry);
5306 int temp=get_reg(branch_regs[i].regmap,PTEMP);
5307 if(rt1[i]==31&&temp>=0)
5309 int return_address=start+i*4+8;
5310 if(get_reg(branch_regs[i].regmap,31)>0)
5311 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5314 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5315 ujump_assemble_write_ra(i); // writeback ra for DS
5318 ds_assemble(i+1,i_regs);
5319 uint64_t bc_unneeded=branch_regs[i].u;
5320 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5321 bc_unneeded|=1|(1LL<<rt1[i]);
5322 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5323 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5324 bc_unneeded,bc_unneeded_upper);
5325 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5326 if(!ra_done&&rt1[i]==31)
5327 ujump_assemble_write_ra(i);
5329 cc=get_reg(branch_regs[i].regmap,CCREG);
5330 assert(cc==HOST_CCREG);
5331 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5333 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5335 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5336 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5337 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5338 if(internal_branch(branch_regs[i].is32,ba[i]))
5339 assem_debug("branch: internal\n");
5341 assem_debug("branch: external\n");
5342 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
5343 ds_assemble_entry(i);
5346 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
5351 static void rjump_assemble_write_ra(int i)
5353 int rt,return_address;
5354 assert(rt1[i+1]!=rt1[i]);
5355 assert(rt2[i+1]!=rt1[i]);
5356 rt=get_reg(branch_regs[i].regmap,rt1[i]);
5357 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5359 return_address=start+i*4+8;
5363 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5366 emit_movimm(return_address,rt); // PC into link register
5368 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5372 void rjump_assemble(int i,struct regstat *i_regs)
5374 signed char *i_regmap=i_regs->regmap;
5378 rs=get_reg(branch_regs[i].regmap,rs1[i]);
5380 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
5381 // Delay slot abuse, make a copy of the branch address register
5382 temp=get_reg(branch_regs[i].regmap,RTEMP);
5384 assert(regs[i].regmap[temp]==RTEMP);
5388 address_generation(i+1,i_regs,regs[i].regmap_entry);
5392 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
5393 int return_address=start+i*4+8;
5394 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table[((return_address>>16)^return_address)&0xFFFF],temp);
5400 int rh=get_reg(regs[i].regmap,RHASH);
5401 if(rh>=0) do_preload_rhash(rh);
5404 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
5405 rjump_assemble_write_ra(i);
5408 ds_assemble(i+1,i_regs);
5409 uint64_t bc_unneeded=branch_regs[i].u;
5410 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5411 bc_unneeded|=1|(1LL<<rt1[i]);
5412 bc_unneeded_upper|=1|(1LL<<rt1[i]);
5413 bc_unneeded&=~(1LL<<rs1[i]);
5414 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5415 bc_unneeded,bc_unneeded_upper);
5416 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
5417 if(!ra_done&&rt1[i]!=0)
5418 rjump_assemble_write_ra(i);
5419 cc=get_reg(branch_regs[i].regmap,CCREG);
5420 assert(cc==HOST_CCREG);
5422 int rh=get_reg(branch_regs[i].regmap,RHASH);
5423 int ht=get_reg(branch_regs[i].regmap,RHTBL);
5425 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
5426 do_preload_rhtbl(ht);
5430 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5431 #ifdef DESTRUCTIVE_WRITEBACK
5432 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
5433 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
5434 emit_loadreg(rs1[i],rs);
5439 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
5443 do_miniht_load(ht,rh);
5446 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
5447 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
5449 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5450 add_stub(CC_STUB,(int)out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
5452 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
5453 // special case for RFE
5458 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
5461 do_miniht_jump(rs,rh,ht);
5466 //if(rs!=EAX) emit_mov(rs,EAX);
5467 //emit_jmp((int)jump_vaddr_eax);
5468 emit_jmp(jump_vaddr_reg[rs]);
5473 emit_shrimm(rs,16,rs);
5474 emit_xor(temp,rs,rs);
5475 emit_movzwl_reg(rs,rs);
5476 emit_shlimm(rs,4,rs);
5477 emit_cmpmem_indexed((int)hash_table,rs,temp);
5478 emit_jne((int)out+14);
5479 emit_readword_indexed((int)hash_table+4,rs,rs);
5481 emit_cmpmem_indexed((int)hash_table+8,rs,temp);
5482 emit_addimm_no_flags(8,rs);
5483 emit_jeq((int)out-17);
5484 // No hit on hash table, call compiler
5487 #ifdef DEBUG_CYCLE_COUNT
5488 emit_readword((int)&last_count,ECX);
5489 emit_add(HOST_CCREG,ECX,HOST_CCREG);
5490 emit_readword((int)&next_interupt,ECX);
5491 emit_writeword(HOST_CCREG,(int)&Count);
5492 emit_sub(HOST_CCREG,ECX,HOST_CCREG);
5493 emit_writeword(ECX,(int)&last_count);
5496 emit_storereg(CCREG,HOST_CCREG);
5497 emit_call((int)get_addr);
5498 emit_loadreg(CCREG,HOST_CCREG);
5499 emit_addimm(ESP,4,ESP);
5501 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5502 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
5506 void cjump_assemble(int i,struct regstat *i_regs)
5508 signed char *i_regmap=i_regs->regmap;
5511 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5512 assem_debug("match=%d\n",match);
5513 int s1h,s1l,s2h,s2l;
5514 int prev_cop1_usable=cop1_usable;
5515 int unconditional=0,nop=0;
5518 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5519 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5520 if(!match) invert=1;
5521 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5522 if(i>(ba[i]-start)>>2) invert=1;
5526 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5527 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5528 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
5529 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
5532 s1l=get_reg(i_regmap,rs1[i]);
5533 s1h=get_reg(i_regmap,rs1[i]|64);
5534 s2l=get_reg(i_regmap,rs2[i]);
5535 s2h=get_reg(i_regmap,rs2[i]|64);
5537 if(rs1[i]==0&&rs2[i]==0)
5539 if(opcode[i]&1) nop=1;
5540 else unconditional=1;
5541 //assert(opcode[i]!=5);
5542 //assert(opcode[i]!=7);
5543 //assert(opcode[i]!=0x15);
5544 //assert(opcode[i]!=0x17);
5550 only32=(regs[i].was32>>rs2[i])&1;
5555 only32=(regs[i].was32>>rs1[i])&1;
5558 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
5562 // Out of order execution (delay slot first)
5564 address_generation(i+1,i_regs,regs[i].regmap_entry);
5565 ds_assemble(i+1,i_regs);
5567 uint64_t bc_unneeded=branch_regs[i].u;
5568 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5569 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5570 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5572 bc_unneeded_upper|=1;
5573 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5574 bc_unneeded,bc_unneeded_upper);
5575 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
5576 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5577 cc=get_reg(branch_regs[i].regmap,CCREG);
5578 assert(cc==HOST_CCREG);
5580 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5581 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5582 //assem_debug("cycle count (adj)\n");
5584 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5585 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5586 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5587 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5589 assem_debug("branch: internal\n");
5591 assem_debug("branch: external\n");
5592 if(internal&&is_ds[(ba[i]-start)>>2]) {
5593 ds_assemble_entry(i);
5596 add_to_linker((int)out,ba[i],internal);
5599 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5600 if(((u_int)out)&7) emit_addnop(0);
5605 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5608 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5611 int taken=0,nottaken=0,nottaken1=0;
5612 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5613 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5617 if(opcode[i]==4) // BEQ
5619 if(s2h>=0) emit_cmp(s1h,s2h);
5620 else emit_test(s1h,s1h);
5624 if(opcode[i]==5) // BNE
5626 if(s2h>=0) emit_cmp(s1h,s2h);
5627 else emit_test(s1h,s1h);
5628 if(invert) taken=(int)out;
5629 else add_to_linker((int)out,ba[i],internal);
5632 if(opcode[i]==6) // BLEZ
5635 if(invert) taken=(int)out;
5636 else add_to_linker((int)out,ba[i],internal);
5641 if(opcode[i]==7) // BGTZ
5646 if(invert) taken=(int)out;
5647 else add_to_linker((int)out,ba[i],internal);
5652 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5654 if(opcode[i]==4) // BEQ
5656 if(s2l>=0) emit_cmp(s1l,s2l);
5657 else emit_test(s1l,s1l);
5662 add_to_linker((int)out,ba[i],internal);
5666 if(opcode[i]==5) // BNE
5668 if(s2l>=0) emit_cmp(s1l,s2l);
5669 else emit_test(s1l,s1l);
5674 add_to_linker((int)out,ba[i],internal);
5678 if(opcode[i]==6) // BLEZ
5685 add_to_linker((int)out,ba[i],internal);
5689 if(opcode[i]==7) // BGTZ
5696 add_to_linker((int)out,ba[i],internal);
5701 if(taken) set_jump_target(taken,(int)out);
5702 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5703 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5705 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5706 add_to_linker((int)out,ba[i],internal);
5709 add_to_linker((int)out,ba[i],internal*2);
5715 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5716 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5717 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5719 assem_debug("branch: internal\n");
5721 assem_debug("branch: external\n");
5722 if(internal&&is_ds[(ba[i]-start)>>2]) {
5723 ds_assemble_entry(i);
5726 add_to_linker((int)out,ba[i],internal);
5730 set_jump_target(nottaken,(int)out);
5733 if(nottaken1) set_jump_target(nottaken1,(int)out);
5735 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5737 } // (!unconditional)
5741 // In-order execution (branch first)
5742 //if(likely[i]) printf("IOL\n");
5745 int taken=0,nottaken=0,nottaken1=0;
5746 if(!unconditional&&!nop) {
5750 if((opcode[i]&0x2f)==4) // BEQ
5752 if(s2h>=0) emit_cmp(s1h,s2h);
5753 else emit_test(s1h,s1h);
5757 if((opcode[i]&0x2f)==5) // BNE
5759 if(s2h>=0) emit_cmp(s1h,s2h);
5760 else emit_test(s1h,s1h);
5764 if((opcode[i]&0x2f)==6) // BLEZ
5772 if((opcode[i]&0x2f)==7) // BGTZ
5782 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5784 if((opcode[i]&0x2f)==4) // BEQ
5786 if(s2l>=0) emit_cmp(s1l,s2l);
5787 else emit_test(s1l,s1l);
5791 if((opcode[i]&0x2f)==5) // BNE
5793 if(s2l>=0) emit_cmp(s1l,s2l);
5794 else emit_test(s1l,s1l);
5798 if((opcode[i]&0x2f)==6) // BLEZ
5804 if((opcode[i]&0x2f)==7) // BGTZ
5810 } // if(!unconditional)
5812 uint64_t ds_unneeded=branch_regs[i].u;
5813 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5814 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5815 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5816 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5818 ds_unneeded_upper|=1;
5821 if(taken) set_jump_target(taken,(int)out);
5822 assem_debug("1:\n");
5823 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5824 ds_unneeded,ds_unneeded_upper);
5826 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5827 address_generation(i+1,&branch_regs[i],0);
5828 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5829 ds_assemble(i+1,&branch_regs[i]);
5830 cc=get_reg(branch_regs[i].regmap,CCREG);
5832 emit_loadreg(CCREG,cc=HOST_CCREG);
5833 // CHECK: Is the following instruction (fall thru) allocated ok?
5835 assert(cc==HOST_CCREG);
5836 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5837 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5838 assem_debug("cycle count (adj)\n");
5839 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5840 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5842 assem_debug("branch: internal\n");
5844 assem_debug("branch: external\n");
5845 if(internal&&is_ds[(ba[i]-start)>>2]) {
5846 ds_assemble_entry(i);
5849 add_to_linker((int)out,ba[i],internal);
5854 cop1_usable=prev_cop1_usable;
5855 if(!unconditional) {
5856 if(nottaken1) set_jump_target(nottaken1,(int)out);
5857 set_jump_target(nottaken,(int)out);
5858 assem_debug("2:\n");
5860 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5861 ds_unneeded,ds_unneeded_upper);
5862 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5863 address_generation(i+1,&branch_regs[i],0);
5864 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5865 ds_assemble(i+1,&branch_regs[i]);
5867 cc=get_reg(branch_regs[i].regmap,CCREG);
5868 if(cc==-1&&!likely[i]) {
5869 // Cycle count isn't in a register, temporarily load it then write it out
5870 emit_loadreg(CCREG,HOST_CCREG);
5871 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5874 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5875 emit_storereg(CCREG,HOST_CCREG);
5878 cc=get_reg(i_regmap,CCREG);
5879 assert(cc==HOST_CCREG);
5880 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5883 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5889 void sjump_assemble(int i,struct regstat *i_regs)
5891 signed char *i_regmap=i_regs->regmap;
5894 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5895 assem_debug("smatch=%d\n",match);
5897 int prev_cop1_usable=cop1_usable;
5898 int unconditional=0,nevertaken=0;
5901 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5902 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5903 if(!match) invert=1;
5904 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5905 if(i>(ba[i]-start)>>2) invert=1;
5908 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5909 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5912 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5913 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5916 s1l=get_reg(i_regmap,rs1[i]);
5917 s1h=get_reg(i_regmap,rs1[i]|64);
5921 if(opcode2[i]&1) unconditional=1;
5923 // These are never taken (r0 is never less than zero)
5924 //assert(opcode2[i]!=0);
5925 //assert(opcode2[i]!=2);
5926 //assert(opcode2[i]!=0x10);
5927 //assert(opcode2[i]!=0x12);
5930 only32=(regs[i].was32>>rs1[i])&1;
5934 // Out of order execution (delay slot first)
5936 address_generation(i+1,i_regs,regs[i].regmap_entry);
5937 ds_assemble(i+1,i_regs);
5939 uint64_t bc_unneeded=branch_regs[i].u;
5940 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5941 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5942 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5944 bc_unneeded_upper|=1;
5945 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5946 bc_unneeded,bc_unneeded_upper);
5947 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5948 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5950 int rt,return_address;
5951 rt=get_reg(branch_regs[i].regmap,31);
5952 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5954 // Save the PC even if the branch is not taken
5955 return_address=start+i*4+8;
5956 emit_movimm(return_address,rt); // PC into link register
5958 if(!nevertaken) emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
5962 cc=get_reg(branch_regs[i].regmap,CCREG);
5963 assert(cc==HOST_CCREG);
5965 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5966 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5967 assem_debug("cycle count (adj)\n");
5969 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5970 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5971 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5972 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5974 assem_debug("branch: internal\n");
5976 assem_debug("branch: external\n");
5977 if(internal&&is_ds[(ba[i]-start)>>2]) {
5978 ds_assemble_entry(i);
5981 add_to_linker((int)out,ba[i],internal);
5984 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5985 if(((u_int)out)&7) emit_addnop(0);
5989 else if(nevertaken) {
5990 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5993 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
5997 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5998 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6002 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6009 add_to_linker((int)out,ba[i],internal);
6013 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6020 add_to_linker((int)out,ba[i],internal);
6028 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
6035 add_to_linker((int)out,ba[i],internal);
6039 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
6046 add_to_linker((int)out,ba[i],internal);
6053 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6054 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
6056 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6057 add_to_linker((int)out,ba[i],internal);
6060 add_to_linker((int)out,ba[i],internal*2);
6066 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6067 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6068 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6070 assem_debug("branch: internal\n");
6072 assem_debug("branch: external\n");
6073 if(internal&&is_ds[(ba[i]-start)>>2]) {
6074 ds_assemble_entry(i);
6077 add_to_linker((int)out,ba[i],internal);
6081 set_jump_target(nottaken,(int)out);
6085 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6087 } // (!unconditional)
6091 // In-order execution (branch first)
6095 int rt,return_address;
6096 rt=get_reg(branch_regs[i].regmap,31);
6098 // Save the PC even if the branch is not taken
6099 return_address=start+i*4+8;
6100 emit_movimm(return_address,rt); // PC into link register
6102 emit_prefetch(hash_table[((return_address>>16)^return_address)&0xFFFF]);
6106 if(!unconditional) {
6107 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6111 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6117 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6127 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
6133 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
6140 } // if(!unconditional)
6142 uint64_t ds_unneeded=branch_regs[i].u;
6143 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6144 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6145 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6146 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6148 ds_unneeded_upper|=1;
6151 //assem_debug("1:\n");
6152 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6153 ds_unneeded,ds_unneeded_upper);
6155 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6156 address_generation(i+1,&branch_regs[i],0);
6157 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6158 ds_assemble(i+1,&branch_regs[i]);
6159 cc=get_reg(branch_regs[i].regmap,CCREG);
6161 emit_loadreg(CCREG,cc=HOST_CCREG);
6162 // CHECK: Is the following instruction (fall thru) allocated ok?
6164 assert(cc==HOST_CCREG);
6165 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6166 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6167 assem_debug("cycle count (adj)\n");
6168 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6169 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6171 assem_debug("branch: internal\n");
6173 assem_debug("branch: external\n");
6174 if(internal&&is_ds[(ba[i]-start)>>2]) {
6175 ds_assemble_entry(i);
6178 add_to_linker((int)out,ba[i],internal);
6183 cop1_usable=prev_cop1_usable;
6184 if(!unconditional) {
6185 set_jump_target(nottaken,(int)out);
6186 assem_debug("1:\n");
6188 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6189 ds_unneeded,ds_unneeded_upper);
6190 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6191 address_generation(i+1,&branch_regs[i],0);
6192 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6193 ds_assemble(i+1,&branch_regs[i]);
6195 cc=get_reg(branch_regs[i].regmap,CCREG);
6196 if(cc==-1&&!likely[i]) {
6197 // Cycle count isn't in a register, temporarily load it then write it out
6198 emit_loadreg(CCREG,HOST_CCREG);
6199 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6202 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6203 emit_storereg(CCREG,HOST_CCREG);
6206 cc=get_reg(i_regmap,CCREG);
6207 assert(cc==HOST_CCREG);
6208 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6211 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6217 void fjump_assemble(int i,struct regstat *i_regs)
6219 signed char *i_regmap=i_regs->regmap;
6222 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6223 assem_debug("fmatch=%d\n",match);
6227 int internal=internal_branch(branch_regs[i].is32,ba[i]);
6228 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
6229 if(!match) invert=1;
6230 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6231 if(i>(ba[i]-start)>>2) invert=1;
6235 fs=get_reg(branch_regs[i].regmap,FSREG);
6236 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
6239 fs=get_reg(i_regmap,FSREG);
6242 // Check cop1 unusable
6244 cs=get_reg(i_regmap,CSREG);
6246 emit_testimm(cs,0x20000000);
6249 add_stub(FP_STUB,eaddr,(int)out,i,cs,(int)i_regs,0,0);
6254 // Out of order execution (delay slot first)
6256 ds_assemble(i+1,i_regs);
6258 uint64_t bc_unneeded=branch_regs[i].u;
6259 uint64_t bc_unneeded_upper=branch_regs[i].uu;
6260 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6261 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
6263 bc_unneeded_upper|=1;
6264 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6265 bc_unneeded,bc_unneeded_upper);
6266 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
6267 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6268 cc=get_reg(branch_regs[i].regmap,CCREG);
6269 assert(cc==HOST_CCREG);
6270 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
6271 assem_debug("cycle count (adj)\n");
6274 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6277 emit_testimm(fs,0x800000);
6278 if(source[i]&0x10000) // BC1T
6284 add_to_linker((int)out,ba[i],internal);
6293 add_to_linker((int)out,ba[i],internal);
6301 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
6302 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
6303 else if(match) emit_addnop(13);
6305 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6306 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6308 assem_debug("branch: internal\n");
6310 assem_debug("branch: external\n");
6311 if(internal&&is_ds[(ba[i]-start)>>2]) {
6312 ds_assemble_entry(i);
6315 add_to_linker((int)out,ba[i],internal);
6318 set_jump_target(nottaken,(int)out);
6322 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
6324 } // (!unconditional)
6328 // In-order execution (branch first)
6332 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
6335 emit_testimm(fs,0x800000);
6336 if(source[i]&0x10000) // BC1T
6347 } // if(!unconditional)
6349 uint64_t ds_unneeded=branch_regs[i].u;
6350 uint64_t ds_unneeded_upper=branch_regs[i].uu;
6351 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6352 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6353 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
6355 ds_unneeded_upper|=1;
6357 //assem_debug("1:\n");
6358 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6359 ds_unneeded,ds_unneeded_upper);
6361 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6362 address_generation(i+1,&branch_regs[i],0);
6363 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
6364 ds_assemble(i+1,&branch_regs[i]);
6365 cc=get_reg(branch_regs[i].regmap,CCREG);
6367 emit_loadreg(CCREG,cc=HOST_CCREG);
6368 // CHECK: Is the following instruction (fall thru) allocated ok?
6370 assert(cc==HOST_CCREG);
6371 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6372 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
6373 assem_debug("cycle count (adj)\n");
6374 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
6375 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
6377 assem_debug("branch: internal\n");
6379 assem_debug("branch: external\n");
6380 if(internal&&is_ds[(ba[i]-start)>>2]) {
6381 ds_assemble_entry(i);
6384 add_to_linker((int)out,ba[i],internal);
6389 if(1) { // <- FIXME (don't need this)
6390 set_jump_target(nottaken,(int)out);
6391 assem_debug("1:\n");
6393 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
6394 ds_unneeded,ds_unneeded_upper);
6395 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
6396 address_generation(i+1,&branch_regs[i],0);
6397 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
6398 ds_assemble(i+1,&branch_regs[i]);
6400 cc=get_reg(branch_regs[i].regmap,CCREG);
6401 if(cc==-1&&!likely[i]) {
6402 // Cycle count isn't in a register, temporarily load it then write it out
6403 emit_loadreg(CCREG,HOST_CCREG);
6404 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6407 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,NOTTAKEN,0);
6408 emit_storereg(CCREG,HOST_CCREG);
6411 cc=get_reg(i_regmap,CCREG);
6412 assert(cc==HOST_CCREG);
6413 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
6416 add_stub(CC_STUB,jaddr,(int)out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
6422 static void pagespan_assemble(int i,struct regstat *i_regs)
6424 int s1l=get_reg(i_regs->regmap,rs1[i]);
6425 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
6426 int s2l=get_reg(i_regs->regmap,rs2[i]);
6427 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
6428 void *nt_branch=NULL;
6431 int unconditional=0;
6441 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
6445 int addr,alt,ntaddr;
6446 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
6450 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
6451 (i_regs->regmap[hr]&63)!=rs1[i] &&
6452 (i_regs->regmap[hr]&63)!=rs2[i] )
6461 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6462 (i_regs->regmap[hr]&63)!=rs1[i] &&
6463 (i_regs->regmap[hr]&63)!=rs2[i] )
6469 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
6473 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
6474 (i_regs->regmap[hr]&63)!=rs1[i] &&
6475 (i_regs->regmap[hr]&63)!=rs2[i] )
6482 assert(hr<HOST_REGS);
6483 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
6484 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
6486 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
6487 if(opcode[i]==2) // J
6491 if(opcode[i]==3) // JAL
6494 int rt=get_reg(i_regs->regmap,31);
6495 emit_movimm(start+i*4+8,rt);
6498 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
6501 if(opcode2[i]==9) // JALR
6503 int rt=get_reg(i_regs->regmap,rt1[i]);
6504 emit_movimm(start+i*4+8,rt);
6507 if((opcode[i]&0x3f)==4) // BEQ
6514 #ifdef HAVE_CMOV_IMM
6516 if(s2l>=0) emit_cmp(s1l,s2l);
6517 else emit_test(s1l,s1l);
6518 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
6524 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6526 if(s2h>=0) emit_cmp(s1h,s2h);
6527 else emit_test(s1h,s1h);
6528 emit_cmovne_reg(alt,addr);
6530 if(s2l>=0) emit_cmp(s1l,s2l);
6531 else emit_test(s1l,s1l);
6532 emit_cmovne_reg(alt,addr);
6535 if((opcode[i]&0x3f)==5) // BNE
6537 #ifdef HAVE_CMOV_IMM
6539 if(s2l>=0) emit_cmp(s1l,s2l);
6540 else emit_test(s1l,s1l);
6541 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
6547 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
6549 if(s2h>=0) emit_cmp(s1h,s2h);
6550 else emit_test(s1h,s1h);
6551 emit_cmovne_reg(alt,addr);
6553 if(s2l>=0) emit_cmp(s1l,s2l);
6554 else emit_test(s1l,s1l);
6555 emit_cmovne_reg(alt,addr);
6558 if((opcode[i]&0x3f)==0x14) // BEQL
6561 if(s2h>=0) emit_cmp(s1h,s2h);
6562 else emit_test(s1h,s1h);
6566 if(s2l>=0) emit_cmp(s1l,s2l);
6567 else emit_test(s1l,s1l);
6568 if(nottaken) set_jump_target(nottaken,(int)out);
6572 if((opcode[i]&0x3f)==0x15) // BNEL
6575 if(s2h>=0) emit_cmp(s1h,s2h);
6576 else emit_test(s1h,s1h);
6580 if(s2l>=0) emit_cmp(s1l,s2l);
6581 else emit_test(s1l,s1l);
6584 if(taken) set_jump_target(taken,(int)out);
6586 if((opcode[i]&0x3f)==6) // BLEZ
6588 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6590 if(s1h>=0) emit_mov(addr,ntaddr);
6591 emit_cmovl_reg(alt,addr);
6594 emit_cmovne_reg(ntaddr,addr);
6595 emit_cmovs_reg(alt,addr);
6598 if((opcode[i]&0x3f)==7) // BGTZ
6600 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
6602 if(s1h>=0) emit_mov(addr,alt);
6603 emit_cmovl_reg(ntaddr,addr);
6606 emit_cmovne_reg(alt,addr);
6607 emit_cmovs_reg(ntaddr,addr);
6610 if((opcode[i]&0x3f)==0x16) // BLEZL
6612 assert((opcode[i]&0x3f)!=0x16);
6614 if((opcode[i]&0x3f)==0x17) // BGTZL
6616 assert((opcode[i]&0x3f)!=0x17);
6618 assert(opcode[i]!=1); // BLTZ/BGEZ
6620 //FIXME: Check CSREG
6621 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
6622 if((source[i]&0x30000)==0) // BC1F
6624 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
6625 emit_testimm(s1l,0x800000);
6626 emit_cmovne_reg(alt,addr);
6628 if((source[i]&0x30000)==0x10000) // BC1T
6630 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
6631 emit_testimm(s1l,0x800000);
6632 emit_cmovne_reg(alt,addr);
6634 if((source[i]&0x30000)==0x20000) // BC1FL
6636 emit_testimm(s1l,0x800000);
6640 if((source[i]&0x30000)==0x30000) // BC1TL
6642 emit_testimm(s1l,0x800000);
6648 assert(i_regs->regmap[HOST_CCREG]==CCREG);
6649 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6650 if(likely[i]||unconditional)
6652 emit_movimm(ba[i],HOST_BTREG);
6654 else if(addr!=HOST_BTREG)
6656 emit_mov(addr,HOST_BTREG);
6658 void *branch_addr=out;
6660 int target_addr=start+i*4+5;
6662 void *compiled_target_addr=check_addr(target_addr);
6663 emit_extjump_ds((int)branch_addr,target_addr);
6664 if(compiled_target_addr) {
6665 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6666 add_link(target_addr,stub);
6668 else set_jump_target((int)branch_addr,(int)stub);
6671 set_jump_target((int)nottaken,(int)out);
6672 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
6673 void *branch_addr=out;
6675 int target_addr=start+i*4+8;
6677 void *compiled_target_addr=check_addr(target_addr);
6678 emit_extjump_ds((int)branch_addr,target_addr);
6679 if(compiled_target_addr) {
6680 set_jump_target((int)branch_addr,(int)compiled_target_addr);
6681 add_link(target_addr,stub);
6683 else set_jump_target((int)branch_addr,(int)stub);
6687 // Assemble the delay slot for the above
6688 static void pagespan_ds()
6690 assem_debug("initial delay slot:\n");
6691 u_int vaddr=start+1;
6692 u_int page=get_page(vaddr);
6693 u_int vpage=get_vpage(vaddr);
6694 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6696 ll_add(jump_in+page,vaddr,(void *)out);
6697 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6698 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6699 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6700 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6701 emit_writeword(HOST_BTREG,(int)&branch_target);
6702 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6703 address_generation(0,®s[0],regs[0].regmap_entry);
6704 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6705 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6710 alu_assemble(0,®s[0]);break;
6712 imm16_assemble(0,®s[0]);break;
6714 shift_assemble(0,®s[0]);break;
6716 shiftimm_assemble(0,®s[0]);break;
6718 load_assemble(0,®s[0]);break;
6720 loadlr_assemble(0,®s[0]);break;
6722 store_assemble(0,®s[0]);break;
6724 storelr_assemble(0,®s[0]);break;
6726 cop0_assemble(0,®s[0]);break;
6728 cop1_assemble(0,®s[0]);break;
6730 c1ls_assemble(0,®s[0]);break;
6732 cop2_assemble(0,®s[0]);break;
6734 c2ls_assemble(0,®s[0]);break;
6736 c2op_assemble(0,®s[0]);break;
6738 fconv_assemble(0,®s[0]);break;
6740 float_assemble(0,®s[0]);break;
6742 fcomp_assemble(0,®s[0]);break;
6744 multdiv_assemble(0,®s[0]);break;
6746 mov_assemble(0,®s[0]);break;
6756 printf("Jump in the delay slot. This is probably a bug.\n");
6758 int btaddr=get_reg(regs[0].regmap,BTREG);
6760 btaddr=get_reg(regs[0].regmap,-1);
6761 emit_readword((int)&branch_target,btaddr);
6763 assert(btaddr!=HOST_CCREG);
6764 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6766 emit_movimm(start+4,HOST_TEMPREG);
6767 emit_cmp(btaddr,HOST_TEMPREG);
6769 emit_cmpimm(btaddr,start+4);
6771 int branch=(int)out;
6773 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6774 emit_jmp(jump_vaddr_reg[btaddr]);
6775 set_jump_target(branch,(int)out);
6776 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6777 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6780 // Basic liveness analysis for MIPS registers
6781 void unneeded_registers(int istart,int iend,int r)
6784 uint64_t u,uu,gte_u,b,bu,gte_bu;
6785 uint64_t temp_u,temp_uu,temp_gte_u=0;
6787 uint64_t gte_u_unknown=0;
6788 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6792 gte_u=gte_u_unknown;
6794 u=unneeded_reg[iend+1];
6795 uu=unneeded_reg_upper[iend+1];
6797 gte_u=gte_unneeded[iend+1];
6800 for (i=iend;i>=istart;i--)
6802 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6803 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6805 // If subroutine call, flag return address as a possible branch target
6806 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6808 if(ba[i]<start || ba[i]>=(start+slen*4))
6810 // Branch out of this block, flush all regs
6813 gte_u=gte_u_unknown;
6815 if(itype[i]==UJUMP&&rt1[i]==31)
6817 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6819 if(itype[i]==RJUMP&&rs1[i]==31)
6821 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6823 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6824 if(itype[i]==UJUMP&&rt1[i]==31)
6826 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6827 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6829 if(itype[i]==RJUMP&&rs1[i]==31)
6831 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6832 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6835 branch_unneeded_reg[i]=u;
6836 branch_unneeded_reg_upper[i]=uu;
6837 // Merge in delay slot
6838 tdep=(~uu>>rt1[i+1])&1;
6839 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6840 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6841 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6842 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6843 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6846 gte_u&=~gte_rs[i+1];
6847 // If branch is "likely" (and conditional)
6848 // then we skip the delay slot on the fall-thru path
6851 u&=unneeded_reg[i+2];
6852 uu&=unneeded_reg_upper[i+2];
6853 gte_u&=gte_unneeded[i+2];
6859 gte_u=gte_u_unknown;
6865 // Internal branch, flag target
6866 bt[(ba[i]-start)>>2]=1;
6867 if(ba[i]<=start+i*4) {
6869 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6871 // Unconditional branch
6875 // Conditional branch (not taken case)
6876 temp_u=unneeded_reg[i+2];
6877 temp_uu=unneeded_reg_upper[i+2];
6878 temp_gte_u&=gte_unneeded[i+2];
6880 // Merge in delay slot
6881 tdep=(~temp_uu>>rt1[i+1])&1;
6882 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6883 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6884 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6885 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6886 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6887 temp_u|=1;temp_uu|=1;
6888 temp_gte_u|=gte_rt[i+1];
6889 temp_gte_u&=~gte_rs[i+1];
6890 // If branch is "likely" (and conditional)
6891 // then we skip the delay slot on the fall-thru path
6894 temp_u&=unneeded_reg[i+2];
6895 temp_uu&=unneeded_reg_upper[i+2];
6896 temp_gte_u&=gte_unneeded[i+2];
6902 temp_gte_u=gte_u_unknown;
6905 tdep=(~temp_uu>>rt1[i])&1;
6906 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6907 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6908 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6909 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6910 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6911 temp_u|=1;temp_uu|=1;
6912 temp_gte_u|=gte_rt[i];
6913 temp_gte_u&=~gte_rs[i];
6914 unneeded_reg[i]=temp_u;
6915 unneeded_reg_upper[i]=temp_uu;
6916 gte_unneeded[i]=temp_gte_u;
6917 // Only go three levels deep. This recursion can take an
6918 // excessive amount of time if there are a lot of nested loops.
6920 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6922 unneeded_reg[(ba[i]-start)>>2]=1;
6923 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6924 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6927 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6929 // Unconditional branch
6930 u=unneeded_reg[(ba[i]-start)>>2];
6931 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6932 gte_u=gte_unneeded[(ba[i]-start)>>2];
6933 branch_unneeded_reg[i]=u;
6934 branch_unneeded_reg_upper[i]=uu;
6937 //branch_unneeded_reg[i]=u;
6938 //branch_unneeded_reg_upper[i]=uu;
6939 // Merge in delay slot
6940 tdep=(~uu>>rt1[i+1])&1;
6941 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6942 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6943 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6944 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6945 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6948 gte_u&=~gte_rs[i+1];
6950 // Conditional branch
6951 b=unneeded_reg[(ba[i]-start)>>2];
6952 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6953 gte_bu=gte_unneeded[(ba[i]-start)>>2];
6954 branch_unneeded_reg[i]=b;
6955 branch_unneeded_reg_upper[i]=bu;
6958 //branch_unneeded_reg[i]=b;
6959 //branch_unneeded_reg_upper[i]=bu;
6960 // Branch delay slot
6961 tdep=(~uu>>rt1[i+1])&1;
6962 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6963 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6964 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6965 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6966 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6968 gte_bu|=gte_rt[i+1];
6969 gte_bu&=~gte_rs[i+1];
6970 // If branch is "likely" then we skip the
6971 // delay slot on the fall-thru path
6977 u&=unneeded_reg[i+2];
6978 uu&=unneeded_reg_upper[i+2];
6979 gte_u&=gte_unneeded[i+2];
6991 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6992 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6993 //branch_unneeded_reg[i]=1;
6994 //branch_unneeded_reg_upper[i]=1;
6996 branch_unneeded_reg[i]=1;
6997 branch_unneeded_reg_upper[i]=1;
7003 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7005 // SYSCALL instruction (software interrupt)
7009 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7011 // ERET instruction (return from interrupt)
7016 tdep=(~uu>>rt1[i])&1;
7017 // Written registers are unneeded
7023 // Accessed registers are needed
7029 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
7030 gte_u|=gte_rs[i]; // MFC2/CFC2 to dead register, unneeded
7031 // Source-target dependencies
7032 uu&=~(tdep<<dep1[i]);
7033 uu&=~(tdep<<dep2[i]);
7034 // R0 is always unneeded
7038 unneeded_reg_upper[i]=uu;
7039 gte_unneeded[i]=gte_u;
7041 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
7044 for(r=1;r<=CCREG;r++) {
7045 if((unneeded_reg[i]>>r)&1) {
7046 if(r==HIREG) printf(" HI");
7047 else if(r==LOREG) printf(" LO");
7048 else printf(" r%d",r);
7052 for(r=1;r<=CCREG;r++) {
7053 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
7054 if(r==HIREG) printf(" HI");
7055 else if(r==LOREG) printf(" LO");
7056 else printf(" r%d",r);
7062 for (i=iend;i>=istart;i--)
7064 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
7069 // Identify registers which are likely to contain 32-bit values
7070 // This is used to predict whether any branches will jump to a
7071 // location with 64-bit values in registers.
7072 static void provisional_32bit()
7076 uint64_t lastbranch=1;
7081 if(itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP) {
7082 if(i>1) is32=lastbranch;
7088 if(itype[i-2]==CJUMP||itype[i-2]==SJUMP||itype[i-2]==FJUMP) {
7090 if(i>2) is32=lastbranch;
7094 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7096 if(rs1[i-2]==0||rs2[i-2]==0)
7099 is32|=1LL<<rs1[i-2];
7102 is32|=1LL<<rs2[i-2];
7107 // If something jumps here with 64-bit values
7108 // then promote those registers to 64 bits
7111 uint64_t temp_is32=is32;
7114 if(ba[j]==start+i*4)
7115 //temp_is32&=branch_regs[j].is32;
7120 if(ba[j]==start+i*4)
7131 if(type==UJUMP||type==RJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7132 // Branches don't write registers, consider the delay slot instead.
7143 if(opcode[i]==0x27||opcode[i]==0x37|| // LWU/LD
7144 opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
7153 if(op==0x1a||op==0x1b) is32&=~(1LL<<rt); // LDR/LDL
7154 if(op==0x22) is32|=1LL<<rt; // LWL
7157 if (op==0x08||op==0x09|| // ADDI/ADDIU
7158 op==0x0a||op==0x0b|| // SLTI/SLTIU
7164 if(op==0x18||op==0x19) { // DADDI/DADDIU
7167 // is32|=((is32>>s1)&1LL)<<rt;
7169 if(op==0x0d||op==0x0e) { // ORI/XORI
7170 uint64_t sr=((is32>>s1)&1LL);
7186 if(op2>=0x20&&op2<=0x23) { // ADD/ADDU/SUB/SUBU
7189 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7192 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7193 uint64_t sr=((is32>>s1)&(is32>>s2)&1LL);
7197 else if(op2>=0x2c&&op2<=0x2d) { // DADD/DADDU
7202 uint64_t sr=((is32>>s1)&1LL);
7207 uint64_t sr=((is32>>s2)&1LL);
7215 else if(op2>=0x2e&&op2<=0x2f) { // DSUB/DSUBU
7220 uint64_t sr=((is32>>s1)&1LL);
7230 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7231 is32&=~((1LL<<HIREG)|(1LL<<LOREG));
7234 is32|=(1LL<<HIREG)|(1LL<<LOREG);
7239 uint64_t sr=((is32>>s1)&1LL);
7245 if(op2>=0x14&&op2<=0x17) is32&=~(1LL<<rt); // DSLLV/DSRLV/DSRAV
7246 else is32|=1LL<<rt; // SLLV/SRLV/SRAV
7250 // DSLL/DSRL/DSRA/DSLL32/DSRL32 but not DSRA32 have 64-bit result
7251 if(op2>=0x38&&op2<0x3f) is32&=~(1LL<<rt);
7254 if(op2==0) is32|=1LL<<rt; // MFC0
7258 if(op2==0) is32|=1LL<<rt; // MFC1
7259 if(op2==1) is32&=~(1LL<<rt); // DMFC1
7260 if(op2==2) is32|=1LL<<rt; // CFC1
7282 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
7284 if(rt1[i-1]==31) // JAL/JALR
7286 // Subroutine call will return here, don't alloc any registers
7291 // Internal branch will jump here, match registers to caller
7299 // Identify registers which may be assumed to contain 32-bit values
7300 // and where optimizations will rely on this.
7301 // This is used to determine whether backward branches can safely
7302 // jump to a location with 64-bit values in registers.
7303 static void provisional_r32()
7308 for (i=slen-1;i>=0;i--)
7311 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7313 if(ba[i]<start || ba[i]>=(start+slen*4))
7315 // Branch out of this block, don't need anything
7321 // Need whatever matches the target
7322 // (and doesn't get overwritten by the delay slot instruction)
7324 int t=(ba[i]-start)>>2;
7325 if(ba[i]>start+i*4) {
7327 //if(!(requires_32bit[t]&~regs[i].was32))
7328 // r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7329 if(!(pr32[t]&~regs[i].was32))
7330 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7333 if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
7334 r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
7337 // Conditional branch may need registers for following instructions
7338 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
7341 //r32|=requires_32bit[i+2];
7344 // Mark this address as a branch target since it may be called
7345 // upon return from interrupt
7349 // Merge in delay slot
7351 // These are overwritten unless the branch is "likely"
7352 // and the delay slot is nullified if not taken
7353 r32&=~(1LL<<rt1[i+1]);
7354 r32&=~(1LL<<rt2[i+1]);
7356 // Assume these are needed (delay slot)
7359 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
7363 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
7365 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
7367 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
7369 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
7371 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
7374 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7376 // SYSCALL instruction (software interrupt)
7379 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7381 // ERET instruction (return from interrupt)
7385 r32&=~(1LL<<rt1[i]);
7386 r32&=~(1LL<<rt2[i]);
7389 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
7393 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
7395 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
7397 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
7399 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
7401 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
7403 //requires_32bit[i]=r32;
7406 // Dirty registers which are 32-bit, require 32-bit input
7407 // as they will be written as 32-bit values
7408 for(hr=0;hr<HOST_REGS;hr++)
7410 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
7411 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
7412 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
7413 pr32[i]|=1LL<<regs[i].regmap_entry[hr];
7414 //requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
7421 // Write back dirty registers as soon as we will no longer modify them,
7422 // so that we don't end up with lots of writes at the branches.
7423 void clean_registers(int istart,int iend,int wr)
7427 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
7428 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
7430 will_dirty_i=will_dirty_next=0;
7431 wont_dirty_i=wont_dirty_next=0;
7433 will_dirty_i=will_dirty_next=will_dirty[iend+1];
7434 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
7436 for (i=iend;i>=istart;i--)
7438 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7440 if(ba[i]<start || ba[i]>=(start+slen*4))
7442 // Branch out of this block, flush all regs
7443 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7445 // Unconditional branch
7448 // Merge in delay slot (will dirty)
7449 for(r=0;r<HOST_REGS;r++) {
7450 if(r!=EXCLUDE_REG) {
7451 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7452 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7453 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7454 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7455 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7456 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7457 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7458 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7459 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7460 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7461 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7462 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7463 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7464 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7470 // Conditional branch
7472 wont_dirty_i=wont_dirty_next;
7473 // Merge in delay slot (will dirty)
7474 for(r=0;r<HOST_REGS;r++) {
7475 if(r!=EXCLUDE_REG) {
7477 // Might not dirty if likely branch is not taken
7478 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7479 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7480 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7481 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7482 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7483 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
7484 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7485 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7486 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7487 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7488 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7489 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7490 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7491 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7496 // Merge in delay slot (wont dirty)
7497 for(r=0;r<HOST_REGS;r++) {
7498 if(r!=EXCLUDE_REG) {
7499 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7500 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7501 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7502 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7503 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7504 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7505 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7506 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7507 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7508 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7512 #ifndef DESTRUCTIVE_WRITEBACK
7513 branch_regs[i].dirty&=wont_dirty_i;
7515 branch_regs[i].dirty|=will_dirty_i;
7521 if(ba[i]<=start+i*4) {
7523 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7525 // Unconditional branch
7528 // Merge in delay slot (will dirty)
7529 for(r=0;r<HOST_REGS;r++) {
7530 if(r!=EXCLUDE_REG) {
7531 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7532 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7533 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7534 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7535 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7536 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7537 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7538 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7539 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7540 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7541 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7542 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7543 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7544 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7548 // Conditional branch (not taken case)
7549 temp_will_dirty=will_dirty_next;
7550 temp_wont_dirty=wont_dirty_next;
7551 // Merge in delay slot (will dirty)
7552 for(r=0;r<HOST_REGS;r++) {
7553 if(r!=EXCLUDE_REG) {
7555 // Will not dirty if likely branch is not taken
7556 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7557 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7558 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7559 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7560 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7561 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
7562 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7563 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
7564 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
7565 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
7566 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
7567 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
7568 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
7569 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
7574 // Merge in delay slot (wont dirty)
7575 for(r=0;r<HOST_REGS;r++) {
7576 if(r!=EXCLUDE_REG) {
7577 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7578 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7579 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7580 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7581 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7582 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
7583 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
7584 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
7585 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
7586 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
7589 // Deal with changed mappings
7591 for(r=0;r<HOST_REGS;r++) {
7592 if(r!=EXCLUDE_REG) {
7593 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
7594 temp_will_dirty&=~(1<<r);
7595 temp_wont_dirty&=~(1<<r);
7596 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7597 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7598 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7600 temp_will_dirty|=1<<r;
7601 temp_wont_dirty|=1<<r;
7608 will_dirty[i]=temp_will_dirty;
7609 wont_dirty[i]=temp_wont_dirty;
7610 clean_registers((ba[i]-start)>>2,i-1,0);
7612 // Limit recursion. It can take an excessive amount
7613 // of time if there are a lot of nested loops.
7614 will_dirty[(ba[i]-start)>>2]=0;
7615 wont_dirty[(ba[i]-start)>>2]=-1;
7620 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
7622 // Unconditional branch
7625 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7626 for(r=0;r<HOST_REGS;r++) {
7627 if(r!=EXCLUDE_REG) {
7628 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7629 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
7630 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7632 if(branch_regs[i].regmap[r]>=0) {
7633 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7634 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
7639 // Merge in delay slot
7640 for(r=0;r<HOST_REGS;r++) {
7641 if(r!=EXCLUDE_REG) {
7642 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7643 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7644 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7645 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7646 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7647 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7648 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7649 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7650 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7651 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7652 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7653 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7654 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7655 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7659 // Conditional branch
7660 will_dirty_i=will_dirty_next;
7661 wont_dirty_i=wont_dirty_next;
7662 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
7663 for(r=0;r<HOST_REGS;r++) {
7664 if(r!=EXCLUDE_REG) {
7665 signed char target_reg=branch_regs[i].regmap[r];
7666 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7667 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7668 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7670 else if(target_reg>=0) {
7671 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7672 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
7674 // Treat delay slot as part of branch too
7675 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
7676 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
7677 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
7681 will_dirty[i+1]&=~(1<<r);
7686 // Merge in delay slot
7687 for(r=0;r<HOST_REGS;r++) {
7688 if(r!=EXCLUDE_REG) {
7690 // Might not dirty if likely branch is not taken
7691 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7692 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7693 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7694 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7695 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7696 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7697 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7698 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7699 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7700 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
7701 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
7702 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7703 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7704 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7709 // Merge in delay slot (won't dirty)
7710 for(r=0;r<HOST_REGS;r++) {
7711 if(r!=EXCLUDE_REG) {
7712 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7713 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7714 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7715 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7716 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7717 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7718 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7719 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
7720 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
7721 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7725 #ifndef DESTRUCTIVE_WRITEBACK
7726 branch_regs[i].dirty&=wont_dirty_i;
7728 branch_regs[i].dirty|=will_dirty_i;
7733 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
7735 // SYSCALL instruction (software interrupt)
7739 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
7741 // ERET instruction (return from interrupt)
7745 will_dirty_next=will_dirty_i;
7746 wont_dirty_next=wont_dirty_i;
7747 for(r=0;r<HOST_REGS;r++) {
7748 if(r!=EXCLUDE_REG) {
7749 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
7750 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
7751 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
7752 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
7753 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
7754 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
7755 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
7756 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
7758 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
7760 // Don't store a register immediately after writing it,
7761 // may prevent dual-issue.
7762 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
7763 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
7769 will_dirty[i]=will_dirty_i;
7770 wont_dirty[i]=wont_dirty_i;
7771 // Mark registers that won't be dirtied as not dirty
7773 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
7774 for(r=0;r<HOST_REGS;r++) {
7775 if((will_dirty_i>>r)&1) {
7781 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
7782 regs[i].dirty|=will_dirty_i;
7783 #ifndef DESTRUCTIVE_WRITEBACK
7784 regs[i].dirty&=wont_dirty_i;
7785 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
7787 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
7788 for(r=0;r<HOST_REGS;r++) {
7789 if(r!=EXCLUDE_REG) {
7790 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
7791 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
7792 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7800 for(r=0;r<HOST_REGS;r++) {
7801 if(r!=EXCLUDE_REG) {
7802 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
7803 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
7804 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);/*assert(!((wont_dirty_i>>r)&1));*/}
7812 // Deal with changed mappings
7813 temp_will_dirty=will_dirty_i;
7814 temp_wont_dirty=wont_dirty_i;
7815 for(r=0;r<HOST_REGS;r++) {
7816 if(r!=EXCLUDE_REG) {
7818 if(regs[i].regmap[r]==regmap_pre[i][r]) {
7820 #ifndef DESTRUCTIVE_WRITEBACK
7821 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7823 regs[i].wasdirty|=will_dirty_i&(1<<r);
7826 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
7827 // Register moved to a different register
7828 will_dirty_i&=~(1<<r);
7829 wont_dirty_i&=~(1<<r);
7830 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
7831 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
7833 #ifndef DESTRUCTIVE_WRITEBACK
7834 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
7836 regs[i].wasdirty|=will_dirty_i&(1<<r);
7840 will_dirty_i&=~(1<<r);
7841 wont_dirty_i&=~(1<<r);
7842 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
7843 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7844 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
7847 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);/*assert(!((will_dirty>>r)&1));*/
7857 void disassemble_inst(int i)
7859 if (bt[i]) printf("*"); else printf(" ");
7862 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7864 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
7866 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
7868 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
7870 if (opcode[i]==0x9&&rt1[i]!=31)
7871 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
7873 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7876 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
7878 if(opcode[i]==0xf) //LUI
7879 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
7881 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7885 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7889 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
7893 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
7896 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
7899 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
7902 if((opcode2[i]&0x1d)==0x10)
7903 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
7904 else if((opcode2[i]&0x1d)==0x11)
7905 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
7907 printf (" %x: %s\n",start+i*4,insn[i]);
7911 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
7912 else if(opcode2[i]==4)
7913 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
7914 else printf (" %x: %s\n",start+i*4,insn[i]);
7918 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
7919 else if(opcode2[i]>3)
7920 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
7921 else printf (" %x: %s\n",start+i*4,insn[i]);
7925 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
7926 else if(opcode2[i]>3)
7927 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
7928 else printf (" %x: %s\n",start+i*4,insn[i]);
7931 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7934 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
7937 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
7940 //printf (" %s %8x\n",insn[i],source[i]);
7941 printf (" %x: %s\n",start+i*4,insn[i]);
7945 static void disassemble_inst(int i) {}
7948 // clear the state completely, instead of just marking
7949 // things invalid like invalidate_all_pages() does
7950 void new_dynarec_clear_full()
7953 out=(u_char *)BASE_ADDR;
7954 memset(invalid_code,1,sizeof(invalid_code));
7955 memset(hash_table,0xff,sizeof(hash_table));
7956 memset(mini_ht,-1,sizeof(mini_ht));
7957 memset(restore_candidate,0,sizeof(restore_candidate));
7958 memset(shadow,0,sizeof(shadow));
7960 expirep=16384; // Expiry pointer, +2 blocks
7961 pending_exception=0;
7964 inv_code_start=inv_code_end=~0;
7968 for(n=0;n<524288;n++) // 0 .. 0x7FFFFFFF
7970 for(n=524288;n<526336;n++) // 0x80000000 .. 0x807FFFFF
7971 memory_map[n]=((u_int)rdram-0x80000000)>>2;
7972 for(n=526336;n<1048576;n++) // 0x80800000 .. 0xFFFFFFFF
7975 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7976 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7977 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7980 void new_dynarec_init()
7982 printf("Init new dynarec\n");
7983 out=(u_char *)BASE_ADDR;
7984 if (mmap (out, 1<<TARGET_SIZE_2,
7985 PROT_READ | PROT_WRITE | PROT_EXEC,
7986 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS,
7987 -1, 0) <= 0) {printf("mmap() failed\n");}
7989 rdword=&readmem_dword;
7990 fake_pc.f.r.rs=&readmem_dword;
7991 fake_pc.f.r.rt=&readmem_dword;
7992 fake_pc.f.r.rd=&readmem_dword;
7995 cycle_multiplier=200;
7996 new_dynarec_clear_full();
7998 // Copy this into local area so we don't have to put it in every literal pool
7999 invc_ptr=invalid_code;
8002 for(n=0;n<0x8000;n++) { // 0 .. 0x7FFFFFFF
8003 writemem[n] = write_nomem_new;
8004 writememb[n] = write_nomemb_new;
8005 writememh[n] = write_nomemh_new;
8007 writememd[n] = write_nomemd_new;
8009 readmem[n] = read_nomem_new;
8010 readmemb[n] = read_nomemb_new;
8011 readmemh[n] = read_nomemh_new;
8013 readmemd[n] = read_nomemd_new;
8016 for(n=0x8000;n<0x8080;n++) { // 0x80000000 .. 0x807FFFFF
8017 writemem[n] = write_rdram_new;
8018 writememb[n] = write_rdramb_new;
8019 writememh[n] = write_rdramh_new;
8021 writememd[n] = write_rdramd_new;
8024 for(n=0xC000;n<0x10000;n++) { // 0xC0000000 .. 0xFFFFFFFF
8025 writemem[n] = write_nomem_new;
8026 writememb[n] = write_nomemb_new;
8027 writememh[n] = write_nomemh_new;
8029 writememd[n] = write_nomemd_new;
8031 readmem[n] = read_nomem_new;
8032 readmemb[n] = read_nomemb_new;
8033 readmemh[n] = read_nomemh_new;
8035 readmemd[n] = read_nomemd_new;
8043 void new_dynarec_cleanup()
8046 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0) {printf("munmap() failed\n");}
8047 for(n=0;n<4096;n++) ll_clear(jump_in+n);
8048 for(n=0;n<4096;n++) ll_clear(jump_out+n);
8049 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
8051 if (munmap (ROM_COPY, 67108864) < 0) {printf("munmap() failed\n");}
8055 int new_recompile_block(int addr)
8058 if(addr==0x800cd050) {
8060 for(block=0x80000;block<0x80800;block++) invalidate_block(block);
8062 for(n=0;n<=2048;n++) ll_clear(jump_dirty+n);
8065 //if(Count==365117028) tracedebug=1;
8066 assem_debug("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8067 //printf("NOTCOMPILED: addr = %x -> %x\n", (int)addr, (int)out);
8068 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
8070 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
8071 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
8072 /*if(Count>=312978186) {
8076 start = (u_int)addr&~3;
8077 //assert(((u_int)addr&1)==0);
8078 new_dynarec_did_compile=1;
8080 if (Config.HLE && start == 0x80001000) // hlecall
8082 // XXX: is this enough? Maybe check hleSoftCall?
8083 u_int beginning=(u_int)out;
8084 u_int page=get_page(start);
8085 invalid_code[start>>12]=0;
8086 emit_movimm(start,0);
8087 emit_writeword(0,(int)&pcaddr);
8088 emit_jmp((int)new_dyna_leave);
8091 __clear_cache((void *)beginning,out);
8093 ll_add(jump_in+page,start,(void *)beginning);
8096 else if ((u_int)addr < 0x00200000 ||
8097 (0xa0000000 <= addr && addr < 0xa0200000)) {
8098 // used for BIOS calls mostly?
8099 source = (u_int *)((u_int)rdram+(start&0x1fffff));
8100 pagelimit = (addr&0xa0000000)|0x00200000;
8102 else if (!Config.HLE && (
8103 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
8104 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
8106 source = (u_int *)((u_int)psxR+(start&0x7ffff));
8107 pagelimit = (addr&0xfff00000)|0x80000;
8112 if ((int)addr >= 0xa4000000 && (int)addr < 0xa4001000) {
8113 source = (u_int *)((u_int)SP_DMEM+start-0xa4000000);
8114 pagelimit = 0xa4001000;
8118 if ((int)addr >= 0x80000000 && (int)addr < 0x80000000+RAM_SIZE) {
8119 source = (u_int *)((u_int)rdram+start-0x80000000);
8120 pagelimit = 0x80000000+RAM_SIZE;
8123 else if ((signed int)addr >= (signed int)0xC0000000) {
8124 //printf("addr=%x mm=%x\n",(u_int)addr,(memory_map[start>>12]<<2));
8125 //if(tlb_LUT_r[start>>12])
8126 //source = (u_int *)(((int)rdram)+(tlb_LUT_r[start>>12]&0xFFFFF000)+(((int)addr)&0xFFF)-0x80000000);
8127 if((signed int)memory_map[start>>12]>=0) {
8128 source = (u_int *)((u_int)(start+(memory_map[start>>12]<<2)));
8129 pagelimit=(start+4096)&0xFFFFF000;
8130 int map=memory_map[start>>12];
8133 //printf("start: %x next: %x\n",map,memory_map[pagelimit>>12]);
8134 if((map&0xBFFFFFFF)==(memory_map[pagelimit>>12]&0xBFFFFFFF)) pagelimit+=4096;
8136 assem_debug("pagelimit=%x\n",pagelimit);
8137 assem_debug("mapping=%x (%x)\n",memory_map[start>>12],(memory_map[start>>12]<<2)+start);
8140 assem_debug("Compile at unmapped memory address: %x \n", (int)addr);
8141 //assem_debug("start: %x next: %x\n",memory_map[start>>12],memory_map[(start+4096)>>12]);
8142 return -1; // Caller will invoke exception handler
8144 //printf("source= %x\n",(int)source);
8148 printf("Compile at bogus memory address: %x \n", (int)addr);
8152 /* Pass 1: disassemble */
8153 /* Pass 2: register dependencies, branch targets */
8154 /* Pass 3: register allocation */
8155 /* Pass 4: branch dependencies */
8156 /* Pass 5: pre-alloc */
8157 /* Pass 6: optimize clean/dirty state */
8158 /* Pass 7: flag 32-bit registers */
8159 /* Pass 8: assembly */
8160 /* Pass 9: linker */
8161 /* Pass 10: garbage collection / free memory */
8165 unsigned int type,op,op2;
8167 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
8169 /* Pass 1 disassembly */
8171 for(i=0;!done;i++) {
8172 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
8173 minimum_free_regs[i]=0;
8174 opcode[i]=op=source[i]>>26;
8177 case 0x00: strcpy(insn[i],"special"); type=NI;
8181 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
8182 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
8183 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
8184 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
8185 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
8186 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
8187 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
8188 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
8189 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
8190 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
8191 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
8192 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
8193 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
8194 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
8195 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
8196 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
8197 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
8198 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
8199 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
8200 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
8201 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
8202 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
8203 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
8204 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
8205 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
8206 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
8207 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
8208 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
8209 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
8210 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
8211 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
8212 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
8213 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
8214 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
8215 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
8217 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
8218 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
8219 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
8220 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
8221 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
8222 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
8223 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
8224 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
8225 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
8226 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
8227 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
8228 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
8229 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
8230 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
8231 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
8232 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
8233 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
8237 case 0x01: strcpy(insn[i],"regimm"); type=NI;
8238 op2=(source[i]>>16)&0x1f;
8241 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
8242 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
8243 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
8244 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
8245 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
8246 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
8247 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
8248 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
8249 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
8250 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
8251 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
8252 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
8253 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
8254 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
8257 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
8258 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
8259 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
8260 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
8261 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
8262 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
8263 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
8264 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
8265 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
8266 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
8267 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
8268 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
8269 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
8270 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
8271 case 0x10: strcpy(insn[i],"cop0"); type=NI;
8272 op2=(source[i]>>21)&0x1f;
8275 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
8276 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
8277 case 0x10: strcpy(insn[i],"tlb"); type=NI;
8278 switch(source[i]&0x3f)
8280 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
8281 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
8282 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
8283 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
8285 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
8287 case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
8292 case 0x11: strcpy(insn[i],"cop1"); type=NI;
8293 op2=(source[i]>>21)&0x1f;
8296 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
8297 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
8298 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
8299 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
8300 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
8301 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
8302 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
8303 switch((source[i]>>16)&0x3)
8305 case 0x00: strcpy(insn[i],"BC1F"); break;
8306 case 0x01: strcpy(insn[i],"BC1T"); break;
8307 case 0x02: strcpy(insn[i],"BC1FL"); break;
8308 case 0x03: strcpy(insn[i],"BC1TL"); break;
8311 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
8312 switch(source[i]&0x3f)
8314 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
8315 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
8316 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
8317 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
8318 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
8319 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
8320 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
8321 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
8322 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
8323 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
8324 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
8325 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
8326 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
8327 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
8328 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
8329 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
8330 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
8331 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
8332 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
8333 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
8334 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
8335 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
8336 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
8337 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
8338 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
8339 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
8340 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
8341 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
8342 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
8343 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
8344 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
8345 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
8346 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
8347 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
8348 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
8351 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
8352 switch(source[i]&0x3f)
8354 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
8355 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
8356 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
8357 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
8358 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
8359 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
8360 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
8361 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
8362 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
8363 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
8364 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
8365 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
8366 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
8367 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
8368 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
8369 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
8370 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
8371 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
8372 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
8373 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
8374 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
8375 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
8376 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
8377 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
8378 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
8379 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
8380 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
8381 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
8382 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
8383 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
8384 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
8385 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
8386 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
8387 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
8388 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
8391 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
8392 switch(source[i]&0x3f)
8394 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
8395 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
8398 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
8399 switch(source[i]&0x3f)
8401 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
8402 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
8408 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
8409 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
8410 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
8411 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
8412 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
8413 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
8414 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
8415 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
8417 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
8418 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
8419 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
8420 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
8421 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
8422 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
8423 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
8425 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
8427 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
8428 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
8429 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
8430 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
8432 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
8433 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
8435 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
8436 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
8437 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
8438 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
8440 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
8441 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
8442 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
8444 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
8445 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
8447 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
8448 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
8449 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
8452 case 0x12: strcpy(insn[i],"COP2"); type=NI;
8453 op2=(source[i]>>21)&0x1f;
8455 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
8456 if (gte_handlers[source[i]&0x3f]!=NULL) {
8457 if (gte_regnames[source[i]&0x3f]!=NULL)
8458 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
8460 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
8466 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
8467 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
8468 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
8469 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
8472 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
8473 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
8474 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
8476 default: strcpy(insn[i],"???"); type=NI;
8477 printf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
8482 /* Get registers/immediates */
8488 gte_rs[i]=gte_rt[i]=0;
8491 rs1[i]=(source[i]>>21)&0x1f;
8493 rt1[i]=(source[i]>>16)&0x1f;
8495 imm[i]=(short)source[i];
8499 rs1[i]=(source[i]>>21)&0x1f;
8500 rs2[i]=(source[i]>>16)&0x1f;
8503 imm[i]=(short)source[i];
8504 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
8507 // LWL/LWR only load part of the register,
8508 // therefore the target register must be treated as a source too
8509 rs1[i]=(source[i]>>21)&0x1f;
8510 rs2[i]=(source[i]>>16)&0x1f;
8511 rt1[i]=(source[i]>>16)&0x1f;
8513 imm[i]=(short)source[i];
8514 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
8515 if(op==0x26) dep1[i]=rt1[i]; // LWR
8518 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
8519 else rs1[i]=(source[i]>>21)&0x1f;
8521 rt1[i]=(source[i]>>16)&0x1f;
8523 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
8524 imm[i]=(unsigned short)source[i];
8526 imm[i]=(short)source[i];
8528 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
8529 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
8530 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
8537 // The JAL instruction writes to r31.
8544 rs1[i]=(source[i]>>21)&0x1f;
8548 // The JALR instruction writes to rd.
8550 rt1[i]=(source[i]>>11)&0x1f;
8555 rs1[i]=(source[i]>>21)&0x1f;
8556 rs2[i]=(source[i]>>16)&0x1f;
8559 if(op&2) { // BGTZ/BLEZ
8567 rs1[i]=(source[i]>>21)&0x1f;
8572 if(op2&0x10) { // BxxAL
8574 // NOTE: If the branch is not taken, r31 is still overwritten
8576 likely[i]=(op2&2)>>1;
8583 likely[i]=((source[i])>>17)&1;
8586 rs1[i]=(source[i]>>21)&0x1f; // source
8587 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
8588 rt1[i]=(source[i]>>11)&0x1f; // destination
8590 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
8591 us1[i]=rs1[i];us2[i]=rs2[i];
8593 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
8594 dep1[i]=rs1[i];dep2[i]=rs2[i];
8596 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
8597 dep1[i]=rs1[i];dep2[i]=rs2[i];
8601 rs1[i]=(source[i]>>21)&0x1f; // source
8602 rs2[i]=(source[i]>>16)&0x1f; // divisor
8605 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
8606 us1[i]=rs1[i];us2[i]=rs2[i];
8614 if(op2==0x10) rs1[i]=HIREG; // MFHI
8615 if(op2==0x11) rt1[i]=HIREG; // MTHI
8616 if(op2==0x12) rs1[i]=LOREG; // MFLO
8617 if(op2==0x13) rt1[i]=LOREG; // MTLO
8618 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
8619 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
8623 rs1[i]=(source[i]>>16)&0x1f; // target of shift
8624 rs2[i]=(source[i]>>21)&0x1f; // shift amount
8625 rt1[i]=(source[i]>>11)&0x1f; // destination
8627 // DSLLV/DSRLV/DSRAV are 64-bit
8628 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
8631 rs1[i]=(source[i]>>16)&0x1f;
8633 rt1[i]=(source[i]>>11)&0x1f;
8635 imm[i]=(source[i]>>6)&0x1f;
8636 // DSxx32 instructions
8637 if(op2>=0x3c) imm[i]|=0x20;
8638 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
8639 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
8646 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
8647 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
8648 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
8649 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
8656 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
8657 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
8658 if(op2==5) us1[i]=rs1[i]; // DMTC1
8666 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
8667 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
8669 int gr=(source[i]>>11)&0x1F;
8672 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
8673 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
8674 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
8675 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
8679 rs1[i]=(source[i]>>21)&0x1F;
8683 imm[i]=(short)source[i];
8686 rs1[i]=(source[i]>>21)&0x1F;
8690 imm[i]=(short)source[i];
8691 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
8692 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
8699 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
8700 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
8701 gte_rt[i]|=1ll<<63; // every op changes flags
8730 /* Calculate branch target addresses */
8732 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
8733 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
8734 ba[i]=start+i*4+8; // Ignore never taken branch
8735 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
8736 ba[i]=start+i*4+8; // Ignore never taken branch
8737 else if(type==CJUMP||type==SJUMP||type==FJUMP)
8738 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
8741 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
8743 // branch in delay slot?
8744 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
8745 // don't handle first branch and call interpreter if it's hit
8746 printf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
8749 // basic load delay detection
8750 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
8751 int t=(ba[i-1]-start)/4;
8752 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
8753 // jump target wants DS result - potential load delay effect
8754 printf("load delay @%08x (%08x)\n", addr + i*4, addr);
8756 bt[t+1]=1; // expected return from interpreter
8758 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
8759 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
8760 // v0 overwrite like this is a sign of trouble, bail out
8761 printf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
8767 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
8771 i--; // don't compile the DS
8775 /* Is this the end of the block? */
8776 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
8777 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
8781 if(stop_after_jal) done=1;
8783 if((source[i+1]&0xfc00003f)==0x0d) done=1;
8785 // Don't recompile stuff that's already compiled
8786 if(check_addr(start+i*4+4)) done=1;
8787 // Don't get too close to the limit
8788 if(i>MAXBLOCK/2) done=1;
8790 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
8791 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
8793 // Does the block continue due to a branch?
8796 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
8797 if(ba[j]==start+i*4+4) done=j=0;
8798 if(ba[j]==start+i*4+8) done=j=0;
8801 //assert(i<MAXBLOCK-1);
8802 if(start+i*4==pagelimit-4) done=1;
8803 assert(start+i*4<pagelimit);
8804 if (i==MAXBLOCK-1) done=1;
8805 // Stop if we're compiling junk
8806 if(itype[i]==NI&&opcode[i]==0x11) {
8807 done=stop_after_jal=1;
8808 printf("Disabled speculative precompilation\n");
8812 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
8813 if(start+i*4==pagelimit) {
8819 /* Pass 2 - Register dependencies and branch targets */
8821 unneeded_registers(0,slen-1,0);
8823 /* Pass 3 - Register allocation */
8825 struct regstat current; // Current register allocations/status
8828 current.u=unneeded_reg[0];
8829 current.uu=unneeded_reg_upper[0];
8830 clear_all_regs(current.regmap);
8831 alloc_reg(¤t,0,CCREG);
8832 dirty_reg(¤t,CCREG);
8835 current.waswritten=0;
8841 provisional_32bit();
8844 // First instruction is delay slot
8849 unneeded_reg_upper[0]=1;
8850 current.regmap[HOST_BTREG]=BTREG;
8858 for(hr=0;hr<HOST_REGS;hr++)
8860 // Is this really necessary?
8861 if(current.regmap[hr]==0) current.regmap[hr]=-1;
8864 current.waswritten=0;
8868 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
8870 if(rs1[i-2]==0||rs2[i-2]==0)
8873 current.is32|=1LL<<rs1[i-2];
8874 int hr=get_reg(current.regmap,rs1[i-2]|64);
8875 if(hr>=0) current.regmap[hr]=-1;
8878 current.is32|=1LL<<rs2[i-2];
8879 int hr=get_reg(current.regmap,rs2[i-2]|64);
8880 if(hr>=0) current.regmap[hr]=-1;
8886 // If something jumps here with 64-bit values
8887 // then promote those registers to 64 bits
8890 uint64_t temp_is32=current.is32;
8893 if(ba[j]==start+i*4)
8894 temp_is32&=branch_regs[j].is32;
8898 if(ba[j]==start+i*4)
8902 if(temp_is32!=current.is32) {
8903 //printf("dumping 32-bit regs (%x)\n",start+i*4);
8904 #ifndef DESTRUCTIVE_WRITEBACK
8907 for(hr=0;hr<HOST_REGS;hr++)
8909 int r=current.regmap[hr];
8912 if((current.dirty>>hr)&((current.is32&~temp_is32)>>r)&1) {
8914 //printf("restore %d\n",r);
8918 current.is32=temp_is32;
8925 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
8926 regs[i].wasconst=current.isconst;
8927 regs[i].was32=current.is32;
8928 regs[i].wasdirty=current.dirty;
8929 regs[i].loadedconst=0;
8930 #if defined(DESTRUCTIVE_WRITEBACK) && !defined(FORCE32)
8931 // To change a dirty register from 32 to 64 bits, we must write
8932 // it out during the previous cycle (for branches, 2 cycles)
8933 if(i<slen-1&&bt[i+1]&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP)
8935 uint64_t temp_is32=current.is32;
8938 if(ba[j]==start+i*4+4)
8939 temp_is32&=branch_regs[j].is32;
8943 if(ba[j]==start+i*4+4)
8947 if(temp_is32!=current.is32) {
8948 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8949 for(hr=0;hr<HOST_REGS;hr++)
8951 int r=current.regmap[hr];
8954 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8955 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP)
8957 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63))
8959 //printf("dump %d/r%d\n",hr,r);
8960 current.regmap[hr]=-1;
8961 if(get_reg(current.regmap,r|64)>=0)
8962 current.regmap[get_reg(current.regmap,r|64)]=-1;
8970 else if(i<slen-2&&bt[i+2]&&(source[i-1]>>16)!=0x1000&&(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP))
8972 uint64_t temp_is32=current.is32;
8975 if(ba[j]==start+i*4+8)
8976 temp_is32&=branch_regs[j].is32;
8980 if(ba[j]==start+i*4+8)
8984 if(temp_is32!=current.is32) {
8985 //printf("pre-dumping 32-bit regs (%x)\n",start+i*4);
8986 for(hr=0;hr<HOST_REGS;hr++)
8988 int r=current.regmap[hr];
8991 if((current.dirty>>hr)&((current.is32&~temp_is32)>>(r&63))&1) {
8992 if(rs1[i]!=(r&63)&&rs2[i]!=(r&63)&&rs1[i+1]!=(r&63)&&rs2[i+1]!=(r&63))
8994 //printf("dump %d/r%d\n",hr,r);
8995 current.regmap[hr]=-1;
8996 if(get_reg(current.regmap,r|64)>=0)
8997 current.regmap[get_reg(current.regmap,r|64)]=-1;
9005 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9007 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9008 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9009 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9018 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
9019 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9020 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9021 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9022 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9025 } else { printf("oops, branch at end of block with no delay slot\n");exit(1); }
9029 ds=0; // Skip delay slot, already allocated as part of branch
9030 // ...but we need to alloc it in case something jumps here
9032 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
9033 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
9035 current.u=branch_unneeded_reg[i-1];
9036 current.uu=branch_unneeded_reg_upper[i-1];
9038 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
9039 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9040 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9043 struct regstat temp;
9044 memcpy(&temp,¤t,sizeof(current));
9045 temp.wasdirty=temp.dirty;
9046 temp.was32=temp.is32;
9047 // TODO: Take into account unconditional branches, as below
9048 delayslot_alloc(&temp,i);
9049 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
9050 regs[i].wasdirty=temp.wasdirty;
9051 regs[i].was32=temp.was32;
9052 regs[i].dirty=temp.dirty;
9053 regs[i].is32=temp.is32;
9057 // Create entry (branch target) regmap
9058 for(hr=0;hr<HOST_REGS;hr++)
9060 int r=temp.regmap[hr];
9062 if(r!=regmap_pre[i][hr]) {
9063 regs[i].regmap_entry[hr]=-1;
9068 if((current.u>>r)&1) {
9069 regs[i].regmap_entry[hr]=-1;
9070 regs[i].regmap[hr]=-1;
9071 //Don't clear regs in the delay slot as the branch might need them
9072 //current.regmap[hr]=-1;
9074 regs[i].regmap_entry[hr]=r;
9077 if((current.uu>>(r&63))&1) {
9078 regs[i].regmap_entry[hr]=-1;
9079 regs[i].regmap[hr]=-1;
9080 //Don't clear regs in the delay slot as the branch might need them
9081 //current.regmap[hr]=-1;
9083 regs[i].regmap_entry[hr]=r;
9087 // First instruction expects CCREG to be allocated
9088 if(i==0&&hr==HOST_CCREG)
9089 regs[i].regmap_entry[hr]=CCREG;
9091 regs[i].regmap_entry[hr]=-1;
9095 else { // Not delay slot
9098 //current.isconst=0; // DEBUG
9099 //current.wasconst=0; // DEBUG
9100 //regs[i].wasconst=0; // DEBUG
9101 clear_const(¤t,rt1[i]);
9102 alloc_cc(¤t,i);
9103 dirty_reg(¤t,CCREG);
9105 alloc_reg(¤t,i,31);
9106 dirty_reg(¤t,31);
9107 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
9108 //assert(rt1[i+1]!=rt1[i]);
9110 alloc_reg(¤t,i,PTEMP);
9112 //current.is32|=1LL<<rt1[i];
9115 delayslot_alloc(¤t,i+1);
9116 //current.isconst=0; // DEBUG
9118 //printf("i=%d, isconst=%x\n",i,current.isconst);
9121 //current.isconst=0;
9122 //current.wasconst=0;
9123 //regs[i].wasconst=0;
9124 clear_const(¤t,rs1[i]);
9125 clear_const(¤t,rt1[i]);
9126 alloc_cc(¤t,i);
9127 dirty_reg(¤t,CCREG);
9128 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
9129 alloc_reg(¤t,i,rs1[i]);
9131 alloc_reg(¤t,i,rt1[i]);
9132 dirty_reg(¤t,rt1[i]);
9133 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
9134 assert(rt1[i+1]!=rt1[i]);
9136 alloc_reg(¤t,i,PTEMP);
9140 if(rs1[i]==31) { // JALR
9141 alloc_reg(¤t,i,RHASH);
9142 #ifndef HOST_IMM_ADDR32
9143 alloc_reg(¤t,i,RHTBL);
9147 delayslot_alloc(¤t,i+1);
9149 // The delay slot overwrites our source register,
9150 // allocate a temporary register to hold the old value.
9154 delayslot_alloc(¤t,i+1);
9156 alloc_reg(¤t,i,RTEMP);
9158 //current.isconst=0; // DEBUG
9163 //current.isconst=0;
9164 //current.wasconst=0;
9165 //regs[i].wasconst=0;
9166 clear_const(¤t,rs1[i]);
9167 clear_const(¤t,rs2[i]);
9168 if((opcode[i]&0x3E)==4) // BEQ/BNE
9170 alloc_cc(¤t,i);
9171 dirty_reg(¤t,CCREG);
9172 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9173 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9174 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9176 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9177 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9179 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
9180 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
9181 // The delay slot overwrites one of our conditions.
9182 // Allocate the branch condition registers instead.
9186 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9187 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
9188 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9190 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9191 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
9197 delayslot_alloc(¤t,i+1);
9201 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
9203 alloc_cc(¤t,i);
9204 dirty_reg(¤t,CCREG);
9205 alloc_reg(¤t,i,rs1[i]);
9206 if(!(current.is32>>rs1[i]&1))
9208 alloc_reg64(¤t,i,rs1[i]);
9210 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
9211 // The delay slot overwrites one of our conditions.
9212 // Allocate the branch condition registers instead.
9216 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9217 if(!((current.is32>>rs1[i])&1))
9219 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9225 delayslot_alloc(¤t,i+1);
9229 // Don't alloc the delay slot yet because we might not execute it
9230 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
9235 alloc_cc(¤t,i);
9236 dirty_reg(¤t,CCREG);
9237 alloc_reg(¤t,i,rs1[i]);
9238 alloc_reg(¤t,i,rs2[i]);
9239 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
9241 alloc_reg64(¤t,i,rs1[i]);
9242 alloc_reg64(¤t,i,rs2[i]);
9246 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
9251 alloc_cc(¤t,i);
9252 dirty_reg(¤t,CCREG);
9253 alloc_reg(¤t,i,rs1[i]);
9254 if(!(current.is32>>rs1[i]&1))
9256 alloc_reg64(¤t,i,rs1[i]);
9260 //current.isconst=0;
9263 //current.isconst=0;
9264 //current.wasconst=0;
9265 //regs[i].wasconst=0;
9266 clear_const(¤t,rs1[i]);
9267 clear_const(¤t,rt1[i]);
9268 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
9269 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
9271 alloc_cc(¤t,i);
9272 dirty_reg(¤t,CCREG);
9273 alloc_reg(¤t,i,rs1[i]);
9274 if(!(current.is32>>rs1[i]&1))
9276 alloc_reg64(¤t,i,rs1[i]);
9278 if (rt1[i]==31) { // BLTZAL/BGEZAL
9279 alloc_reg(¤t,i,31);
9280 dirty_reg(¤t,31);
9281 //#ifdef REG_PREFETCH
9282 //alloc_reg(¤t,i,PTEMP);
9284 //current.is32|=1LL<<rt1[i];
9286 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
9287 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
9288 // Allocate the branch condition registers instead.
9292 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
9293 if(!((current.is32>>rs1[i])&1))
9295 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
9301 delayslot_alloc(¤t,i+1);
9305 // Don't alloc the delay slot yet because we might not execute it
9306 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
9311 alloc_cc(¤t,i);
9312 dirty_reg(¤t,CCREG);
9313 alloc_reg(¤t,i,rs1[i]);
9314 if(!(current.is32>>rs1[i]&1))
9316 alloc_reg64(¤t,i,rs1[i]);
9320 //current.isconst=0;
9326 if(likely[i]==0) // BC1F/BC1T
9328 // TODO: Theoretically we can run out of registers here on x86.
9329 // The delay slot can allocate up to six, and we need to check
9330 // CSREG before executing the delay slot. Possibly we can drop
9331 // the cycle count and then reload it after checking that the
9332 // FPU is in a usable state, or don't do out-of-order execution.
9333 alloc_cc(¤t,i);
9334 dirty_reg(¤t,CCREG);
9335 alloc_reg(¤t,i,FSREG);
9336 alloc_reg(¤t,i,CSREG);
9337 if(itype[i+1]==FCOMP) {
9338 // The delay slot overwrites the branch condition.
9339 // Allocate the branch condition registers instead.
9340 alloc_cc(¤t,i);
9341 dirty_reg(¤t,CCREG);
9342 alloc_reg(¤t,i,CSREG);
9343 alloc_reg(¤t,i,FSREG);
9347 delayslot_alloc(¤t,i+1);
9348 alloc_reg(¤t,i+1,CSREG);
9352 // Don't alloc the delay slot yet because we might not execute it
9353 if(likely[i]) // BC1FL/BC1TL
9355 alloc_cc(¤t,i);
9356 dirty_reg(¤t,CCREG);
9357 alloc_reg(¤t,i,CSREG);
9358 alloc_reg(¤t,i,FSREG);
9364 imm16_alloc(¤t,i);
9368 load_alloc(¤t,i);
9372 store_alloc(¤t,i);
9375 alu_alloc(¤t,i);
9378 shift_alloc(¤t,i);
9381 multdiv_alloc(¤t,i);
9384 shiftimm_alloc(¤t,i);
9387 mov_alloc(¤t,i);
9390 cop0_alloc(¤t,i);
9394 cop1_alloc(¤t,i);
9397 c1ls_alloc(¤t,i);
9400 c2ls_alloc(¤t,i);
9403 c2op_alloc(¤t,i);
9406 fconv_alloc(¤t,i);
9409 float_alloc(¤t,i);
9412 fcomp_alloc(¤t,i);
9417 syscall_alloc(¤t,i);
9420 pagespan_alloc(¤t,i);
9424 // Drop the upper half of registers that have become 32-bit
9425 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
9426 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
9427 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9428 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9431 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
9432 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
9433 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
9434 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
9438 // Create entry (branch target) regmap
9439 for(hr=0;hr<HOST_REGS;hr++)
9442 r=current.regmap[hr];
9444 if(r!=regmap_pre[i][hr]) {
9445 // TODO: delay slot (?)
9446 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
9447 if(or<0||(r&63)>=TEMPREG){
9448 regs[i].regmap_entry[hr]=-1;
9452 // Just move it to a different register
9453 regs[i].regmap_entry[hr]=r;
9454 // If it was dirty before, it's still dirty
9455 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
9462 regs[i].regmap_entry[hr]=0;
9466 if((current.u>>r)&1) {
9467 regs[i].regmap_entry[hr]=-1;
9468 //regs[i].regmap[hr]=-1;
9469 current.regmap[hr]=-1;
9471 regs[i].regmap_entry[hr]=r;
9474 if((current.uu>>(r&63))&1) {
9475 regs[i].regmap_entry[hr]=-1;
9476 //regs[i].regmap[hr]=-1;
9477 current.regmap[hr]=-1;
9479 regs[i].regmap_entry[hr]=r;
9483 // Branches expect CCREG to be allocated at the target
9484 if(regmap_pre[i][hr]==CCREG)
9485 regs[i].regmap_entry[hr]=CCREG;
9487 regs[i].regmap_entry[hr]=-1;
9490 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
9493 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
9494 current.waswritten|=1<<rs1[i-1];
9495 current.waswritten&=~(1<<rt1[i]);
9496 current.waswritten&=~(1<<rt2[i]);
9497 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
9498 current.waswritten&=~(1<<rs1[i]);
9500 /* Branch post-alloc */
9503 current.was32=current.is32;
9504 current.wasdirty=current.dirty;
9505 switch(itype[i-1]) {
9507 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9508 branch_regs[i-1].isconst=0;
9509 branch_regs[i-1].wasconst=0;
9510 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9511 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9512 alloc_cc(&branch_regs[i-1],i-1);
9513 dirty_reg(&branch_regs[i-1],CCREG);
9514 if(rt1[i-1]==31) { // JAL
9515 alloc_reg(&branch_regs[i-1],i-1,31);
9516 dirty_reg(&branch_regs[i-1],31);
9517 branch_regs[i-1].is32|=1LL<<31;
9519 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9520 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9523 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9524 branch_regs[i-1].isconst=0;
9525 branch_regs[i-1].wasconst=0;
9526 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9527 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9528 alloc_cc(&branch_regs[i-1],i-1);
9529 dirty_reg(&branch_regs[i-1],CCREG);
9530 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
9531 if(rt1[i-1]!=0) { // JALR
9532 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
9533 dirty_reg(&branch_regs[i-1],rt1[i-1]);
9534 branch_regs[i-1].is32|=1LL<<rt1[i-1];
9537 if(rs1[i-1]==31) { // JALR
9538 alloc_reg(&branch_regs[i-1],i-1,RHASH);
9539 #ifndef HOST_IMM_ADDR32
9540 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
9544 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9545 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9548 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
9550 alloc_cc(¤t,i-1);
9551 dirty_reg(¤t,CCREG);
9552 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
9553 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
9554 // The delay slot overwrote one of our conditions
9555 // Delay slot goes after the test (in order)
9556 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9557 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9558 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9561 delayslot_alloc(¤t,i);
9566 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
9567 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
9568 // Alloc the branch condition registers
9569 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
9570 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
9571 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
9573 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
9574 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
9577 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9578 branch_regs[i-1].isconst=0;
9579 branch_regs[i-1].wasconst=0;
9580 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9581 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9584 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
9586 alloc_cc(¤t,i-1);
9587 dirty_reg(¤t,CCREG);
9588 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9589 // The delay slot overwrote the branch condition
9590 // Delay slot goes after the test (in order)
9591 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9592 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9593 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9596 delayslot_alloc(¤t,i);
9601 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9602 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9603 // Alloc the branch condition register
9604 alloc_reg(¤t,i-1,rs1[i-1]);
9605 if(!(current.is32>>rs1[i-1]&1))
9607 alloc_reg64(¤t,i-1,rs1[i-1]);
9610 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9611 branch_regs[i-1].isconst=0;
9612 branch_regs[i-1].wasconst=0;
9613 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9614 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9617 // Alloc the delay slot in case the branch is taken
9618 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
9620 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9621 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9622 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9623 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9624 alloc_cc(&branch_regs[i-1],i);
9625 dirty_reg(&branch_regs[i-1],CCREG);
9626 delayslot_alloc(&branch_regs[i-1],i);
9627 branch_regs[i-1].isconst=0;
9628 alloc_reg(¤t,i,CCREG); // Not taken path
9629 dirty_reg(¤t,CCREG);
9630 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9633 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
9635 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9636 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9637 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9638 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9639 alloc_cc(&branch_regs[i-1],i);
9640 dirty_reg(&branch_regs[i-1],CCREG);
9641 delayslot_alloc(&branch_regs[i-1],i);
9642 branch_regs[i-1].isconst=0;
9643 alloc_reg(¤t,i,CCREG); // Not taken path
9644 dirty_reg(¤t,CCREG);
9645 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9649 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
9650 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
9652 alloc_cc(¤t,i-1);
9653 dirty_reg(¤t,CCREG);
9654 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
9655 // The delay slot overwrote the branch condition
9656 // Delay slot goes after the test (in order)
9657 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
9658 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
9659 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
9662 delayslot_alloc(¤t,i);
9667 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9668 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9669 // Alloc the branch condition register
9670 alloc_reg(¤t,i-1,rs1[i-1]);
9671 if(!(current.is32>>rs1[i-1]&1))
9673 alloc_reg64(¤t,i-1,rs1[i-1]);
9676 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9677 branch_regs[i-1].isconst=0;
9678 branch_regs[i-1].wasconst=0;
9679 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9680 memcpy(constmap[i],constmap[i-1],sizeof(current.constmap));
9683 // Alloc the delay slot in case the branch is taken
9684 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
9686 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9687 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9688 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9689 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9690 alloc_cc(&branch_regs[i-1],i);
9691 dirty_reg(&branch_regs[i-1],CCREG);
9692 delayslot_alloc(&branch_regs[i-1],i);
9693 branch_regs[i-1].isconst=0;
9694 alloc_reg(¤t,i,CCREG); // Not taken path
9695 dirty_reg(¤t,CCREG);
9696 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9698 // FIXME: BLTZAL/BGEZAL
9699 if(opcode2[i-1]&0x10) { // BxxZAL
9700 alloc_reg(&branch_regs[i-1],i-1,31);
9701 dirty_reg(&branch_regs[i-1],31);
9702 branch_regs[i-1].is32|=1LL<<31;
9706 if(likely[i-1]==0) // BC1F/BC1T
9708 alloc_cc(¤t,i-1);
9709 dirty_reg(¤t,CCREG);
9710 if(itype[i]==FCOMP) {
9711 // The delay slot overwrote the branch condition
9712 // Delay slot goes after the test (in order)
9713 delayslot_alloc(¤t,i);
9718 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
9719 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
9720 // Alloc the branch condition register
9721 alloc_reg(¤t,i-1,FSREG);
9723 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9724 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
9728 // Alloc the delay slot in case the branch is taken
9729 memcpy(&branch_regs[i-1],¤t,sizeof(current));
9730 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9731 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
9732 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
9733 alloc_cc(&branch_regs[i-1],i);
9734 dirty_reg(&branch_regs[i-1],CCREG);
9735 delayslot_alloc(&branch_regs[i-1],i);
9736 branch_regs[i-1].isconst=0;
9737 alloc_reg(¤t,i,CCREG); // Not taken path
9738 dirty_reg(¤t,CCREG);
9739 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
9744 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
9746 if(rt1[i-1]==31) // JAL/JALR
9748 // Subroutine call will return here, don't alloc any registers
9751 clear_all_regs(current.regmap);
9752 alloc_reg(¤t,i,CCREG);
9753 dirty_reg(¤t,CCREG);
9757 // Internal branch will jump here, match registers to caller
9758 current.is32=0x3FFFFFFFFLL;
9760 clear_all_regs(current.regmap);
9761 alloc_reg(¤t,i,CCREG);
9762 dirty_reg(¤t,CCREG);
9765 if(ba[j]==start+i*4+4) {
9766 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
9767 current.is32=branch_regs[j].is32;
9768 current.dirty=branch_regs[j].dirty;
9773 if(ba[j]==start+i*4+4) {
9774 for(hr=0;hr<HOST_REGS;hr++) {
9775 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
9776 current.regmap[hr]=-1;
9778 current.is32&=branch_regs[j].is32;
9779 current.dirty&=branch_regs[j].dirty;
9788 // Count cycles in between branches
9790 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
9794 #if defined(PCSX) && !defined(DRC_DBG)
9795 else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
9797 // GTE runs in parallel until accessed, divide by 2 for a rough guess
9798 cc+=gte_cycletab[source[i]&0x3f]/2;
9800 else if(/*itype[i]==LOAD||*/itype[i]==STORE||itype[i]==C1LS) // load causes weird timing issues
9802 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
9804 else if(itype[i]==C2LS)
9814 flush_dirty_uppers(¤t);
9816 regs[i].is32=current.is32;
9817 regs[i].dirty=current.dirty;
9818 regs[i].isconst=current.isconst;
9819 memcpy(constmap[i],current.constmap,sizeof(current.constmap));
9821 for(hr=0;hr<HOST_REGS;hr++) {
9822 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
9823 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
9824 regs[i].wasconst&=~(1<<hr);
9828 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
9829 regs[i].waswritten=current.waswritten;
9832 /* Pass 4 - Cull unused host registers */
9836 for (i=slen-1;i>=0;i--)
9839 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9841 if(ba[i]<start || ba[i]>=(start+slen*4))
9843 // Branch out of this block, don't need anything
9849 // Need whatever matches the target
9851 int t=(ba[i]-start)>>2;
9852 for(hr=0;hr<HOST_REGS;hr++)
9854 if(regs[i].regmap_entry[hr]>=0) {
9855 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
9859 // Conditional branch may need registers for following instructions
9860 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9863 nr|=needed_reg[i+2];
9864 for(hr=0;hr<HOST_REGS;hr++)
9866 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
9867 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
9871 // Don't need stuff which is overwritten
9872 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9873 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9874 // Merge in delay slot
9875 for(hr=0;hr<HOST_REGS;hr++)
9878 // These are overwritten unless the branch is "likely"
9879 // and the delay slot is nullified if not taken
9880 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9881 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9883 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9884 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9885 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9886 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
9887 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9888 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9889 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9890 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9891 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
9892 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9893 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9895 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
9896 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9897 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9899 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
9900 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9901 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9905 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
9907 // SYSCALL instruction (software interrupt)
9910 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
9912 // ERET instruction (return from interrupt)
9918 for(hr=0;hr<HOST_REGS;hr++) {
9919 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
9920 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
9921 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
9922 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
9926 for(hr=0;hr<HOST_REGS;hr++)
9928 // Overwritten registers are not needed
9929 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9930 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9931 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
9932 // Source registers are needed
9933 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9934 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9935 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
9936 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
9937 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9938 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9939 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9940 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
9941 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
9942 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9943 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9945 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
9946 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9947 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9949 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
9950 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
9951 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
9953 // Don't store a register immediately after writing it,
9954 // may prevent dual-issue.
9955 // But do so if this is a branch target, otherwise we
9956 // might have to load the register before the branch.
9957 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
9958 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
9959 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
9960 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9961 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
9963 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
9964 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
9965 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9966 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
9970 // Cycle count is needed at branches. Assume it is needed at the target too.
9971 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
9972 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9973 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
9978 // Deallocate unneeded registers
9979 for(hr=0;hr<HOST_REGS;hr++)
9982 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
9983 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
9984 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
9985 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
9987 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
9990 regs[i].regmap[hr]=-1;
9991 regs[i].isconst&=~(1<<hr);
9993 regmap_pre[i+2][hr]=-1;
9994 regs[i+2].wasconst&=~(1<<hr);
9999 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10001 int d1=0,d2=0,map=0,temp=0;
10002 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
10008 if(itype[i+1]==LOAD || itype[i+1]==LOADLR ||
10009 itype[i+1]==STORE || itype[i+1]==STORELR ||
10010 itype[i+1]==C1LS || itype[i+1]==C2LS)
10013 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
10014 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10017 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
10018 itype[i+1]==C1LS || itype[i+1]==C2LS)
10020 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
10021 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10022 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
10023 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
10024 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10025 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
10026 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
10027 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
10028 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
10029 regs[i].regmap[hr]!=map )
10031 regs[i].regmap[hr]=-1;
10032 regs[i].isconst&=~(1<<hr);
10033 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
10034 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
10035 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
10036 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
10037 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
10038 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
10039 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
10040 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
10041 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
10042 branch_regs[i].regmap[hr]!=map)
10044 branch_regs[i].regmap[hr]=-1;
10045 branch_regs[i].regmap_entry[hr]=-1;
10046 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10048 if(!likely[i]&&i<slen-2) {
10049 regmap_pre[i+2][hr]=-1;
10050 regs[i+2].wasconst&=~(1<<hr);
10061 int d1=0,d2=0,map=-1,temp=-1;
10062 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
10068 if(itype[i]==LOAD || itype[i]==LOADLR ||
10069 itype[i]==STORE || itype[i]==STORELR ||
10070 itype[i]==C1LS || itype[i]==C2LS)
10072 } else if(itype[i]==STORE || itype[i]==STORELR ||
10073 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
10076 if(itype[i]==LOADLR || itype[i]==STORELR ||
10077 itype[i]==C1LS || itype[i]==C2LS)
10079 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
10080 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
10081 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
10082 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
10083 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
10084 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
10086 if(i<slen-1&&!is_ds[i]) {
10087 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
10088 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
10089 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
10091 printf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
10092 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
10094 regmap_pre[i+1][hr]=-1;
10095 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
10096 regs[i+1].wasconst&=~(1<<hr);
10098 regs[i].regmap[hr]=-1;
10099 regs[i].isconst&=~(1<<hr);
10107 /* Pass 5 - Pre-allocate registers */
10109 // If a register is allocated during a loop, try to allocate it for the
10110 // entire loop, if possible. This avoids loading/storing registers
10111 // inside of the loop.
10113 signed char f_regmap[HOST_REGS];
10114 clear_all_regs(f_regmap);
10115 for(i=0;i<slen-1;i++)
10117 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10119 if(ba[i]>=start && ba[i]<(start+i*4))
10120 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
10121 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
10122 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
10123 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
10124 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
10125 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
10127 int t=(ba[i]-start)>>2;
10128 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
10129 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
10130 for(hr=0;hr<HOST_REGS;hr++)
10132 if(regs[i].regmap[hr]>64) {
10133 if(!((regs[i].dirty>>hr)&1))
10134 f_regmap[hr]=regs[i].regmap[hr];
10135 else f_regmap[hr]=-1;
10137 else if(regs[i].regmap[hr]>=0) {
10138 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10139 // dealloc old register
10141 for(n=0;n<HOST_REGS;n++)
10143 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10145 // and alloc new one
10146 f_regmap[hr]=regs[i].regmap[hr];
10149 if(branch_regs[i].regmap[hr]>64) {
10150 if(!((branch_regs[i].dirty>>hr)&1))
10151 f_regmap[hr]=branch_regs[i].regmap[hr];
10152 else f_regmap[hr]=-1;
10154 else if(branch_regs[i].regmap[hr]>=0) {
10155 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
10156 // dealloc old register
10158 for(n=0;n<HOST_REGS;n++)
10160 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
10162 // and alloc new one
10163 f_regmap[hr]=branch_regs[i].regmap[hr];
10167 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
10168 f_regmap[hr]=branch_regs[i].regmap[hr];
10170 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
10171 f_regmap[hr]=branch_regs[i].regmap[hr];
10173 // Avoid dirty->clean transition
10174 #ifdef DESTRUCTIVE_WRITEBACK
10175 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
10177 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
10178 // case above, however it's always a good idea. We can't hoist the
10179 // load if the register was already allocated, so there's no point
10180 // wasting time analyzing most of these cases. It only "succeeds"
10181 // when the mapping was different and the load can be replaced with
10182 // a mov, which is of negligible benefit. So such cases are
10184 if(f_regmap[hr]>0) {
10185 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
10186 int r=f_regmap[hr];
10189 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10190 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
10191 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
10193 // NB This can exclude the case where the upper-half
10194 // register is lower numbered than the lower-half
10195 // register. Not sure if it's worth fixing...
10196 if(get_reg(regs[j].regmap,r&63)<0) break;
10197 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
10198 if(regs[j].is32&(1LL<<(r&63))) break;
10200 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
10201 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
10203 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
10204 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
10206 if(get_reg(regs[i].regmap,r&63)<0) break;
10207 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
10210 while(k>1&®s[k-1].regmap[hr]==-1) {
10211 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10212 //printf("no free regs for store %x\n",start+(k-1)*4);
10215 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
10216 //printf("no-match due to different register\n");
10219 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
10220 //printf("no-match due to branch\n");
10223 // call/ret fast path assumes no registers allocated
10224 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
10228 // NB This can exclude the case where the upper-half
10229 // register is lower numbered than the lower-half
10230 // register. Not sure if it's worth fixing...
10231 if(get_reg(regs[k-1].regmap,r&63)<0) break;
10232 if(regs[k-1].is32&(1LL<<(r&63))) break;
10237 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
10238 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
10239 //printf("bad match after branch\n");
10243 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
10244 //printf("Extend r%d, %x ->\n",hr,start+k*4);
10246 regs[k].regmap_entry[hr]=f_regmap[hr];
10247 regs[k].regmap[hr]=f_regmap[hr];
10248 regmap_pre[k+1][hr]=f_regmap[hr];
10249 regs[k].wasdirty&=~(1<<hr);
10250 regs[k].dirty&=~(1<<hr);
10251 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
10252 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
10253 regs[k].wasconst&=~(1<<hr);
10254 regs[k].isconst&=~(1<<hr);
10259 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
10262 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
10263 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
10264 //printf("OK fill %x (r%d)\n",start+i*4,hr);
10265 regs[i].regmap_entry[hr]=f_regmap[hr];
10266 regs[i].regmap[hr]=f_regmap[hr];
10267 regs[i].wasdirty&=~(1<<hr);
10268 regs[i].dirty&=~(1<<hr);
10269 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
10270 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
10271 regs[i].wasconst&=~(1<<hr);
10272 regs[i].isconst&=~(1<<hr);
10273 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
10274 branch_regs[i].wasdirty&=~(1<<hr);
10275 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
10276 branch_regs[i].regmap[hr]=f_regmap[hr];
10277 branch_regs[i].dirty&=~(1<<hr);
10278 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
10279 branch_regs[i].wasconst&=~(1<<hr);
10280 branch_regs[i].isconst&=~(1<<hr);
10281 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
10282 regmap_pre[i+2][hr]=f_regmap[hr];
10283 regs[i+2].wasdirty&=~(1<<hr);
10284 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
10285 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
10286 (regs[i+2].was32&(1LL<<f_regmap[hr])));
10291 // Alloc register clean at beginning of loop,
10292 // but may dirty it in pass 6
10293 regs[k].regmap_entry[hr]=f_regmap[hr];
10294 regs[k].regmap[hr]=f_regmap[hr];
10295 regs[k].dirty&=~(1<<hr);
10296 regs[k].wasconst&=~(1<<hr);
10297 regs[k].isconst&=~(1<<hr);
10298 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
10299 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
10300 branch_regs[k].regmap[hr]=f_regmap[hr];
10301 branch_regs[k].dirty&=~(1<<hr);
10302 branch_regs[k].wasconst&=~(1<<hr);
10303 branch_regs[k].isconst&=~(1<<hr);
10304 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
10305 regmap_pre[k+2][hr]=f_regmap[hr];
10306 regs[k+2].wasdirty&=~(1<<hr);
10307 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
10308 (regs[k+2].was32&(1LL<<f_regmap[hr])));
10313 regmap_pre[k+1][hr]=f_regmap[hr];
10314 regs[k+1].wasdirty&=~(1<<hr);
10317 if(regs[j].regmap[hr]==f_regmap[hr])
10318 regs[j].regmap_entry[hr]=f_regmap[hr];
10322 if(regs[j].regmap[hr]>=0)
10324 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
10325 //printf("no-match due to different register\n");
10328 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
10329 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
10332 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10334 // Stop on unconditional branch
10337 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
10340 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
10343 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
10346 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
10347 //printf("no-match due to different register (branch)\n");
10351 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10352 //printf("No free regs for store %x\n",start+j*4);
10355 if(f_regmap[hr]>=64) {
10356 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
10361 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
10372 // Non branch or undetermined branch target
10373 for(hr=0;hr<HOST_REGS;hr++)
10375 if(hr!=EXCLUDE_REG) {
10376 if(regs[i].regmap[hr]>64) {
10377 if(!((regs[i].dirty>>hr)&1))
10378 f_regmap[hr]=regs[i].regmap[hr];
10380 else if(regs[i].regmap[hr]>=0) {
10381 if(f_regmap[hr]!=regs[i].regmap[hr]) {
10382 // dealloc old register
10384 for(n=0;n<HOST_REGS;n++)
10386 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
10388 // and alloc new one
10389 f_regmap[hr]=regs[i].regmap[hr];
10394 // Try to restore cycle count at branch targets
10396 for(j=i;j<slen-1;j++) {
10397 if(regs[j].regmap[HOST_CCREG]!=-1) break;
10398 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
10399 //printf("no free regs for store %x\n",start+j*4);
10403 if(regs[j].regmap[HOST_CCREG]==CCREG) {
10405 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
10407 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10408 regs[k].regmap[HOST_CCREG]=CCREG;
10409 regmap_pre[k+1][HOST_CCREG]=CCREG;
10410 regs[k+1].wasdirty|=1<<HOST_CCREG;
10411 regs[k].dirty|=1<<HOST_CCREG;
10412 regs[k].wasconst&=~(1<<HOST_CCREG);
10413 regs[k].isconst&=~(1<<HOST_CCREG);
10416 regs[j].regmap_entry[HOST_CCREG]=CCREG;
10418 // Work backwards from the branch target
10419 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
10421 //printf("Extend backwards\n");
10424 while(regs[k-1].regmap[HOST_CCREG]==-1) {
10425 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
10426 //printf("no free regs for store %x\n",start+(k-1)*4);
10431 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
10432 //printf("Extend CC, %x ->\n",start+k*4);
10434 regs[k].regmap_entry[HOST_CCREG]=CCREG;
10435 regs[k].regmap[HOST_CCREG]=CCREG;
10436 regmap_pre[k+1][HOST_CCREG]=CCREG;
10437 regs[k+1].wasdirty|=1<<HOST_CCREG;
10438 regs[k].dirty|=1<<HOST_CCREG;
10439 regs[k].wasconst&=~(1<<HOST_CCREG);
10440 regs[k].isconst&=~(1<<HOST_CCREG);
10445 //printf("Fail Extend CC, %x ->\n",start+k*4);
10449 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
10450 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
10451 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
10452 itype[i]!=FCONV&&itype[i]!=FCOMP)
10454 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
10459 // Cache memory offset or tlb map pointer if a register is available
10460 #ifndef HOST_IMM_ADDR32
10465 int earliest_available[HOST_REGS];
10466 int loop_start[HOST_REGS];
10467 int score[HOST_REGS];
10468 int end[HOST_REGS];
10469 int reg=using_tlb?MMREG:ROREG;
10472 for(hr=0;hr<HOST_REGS;hr++) {
10473 score[hr]=0;earliest_available[hr]=0;
10474 loop_start[hr]=MAXBLOCK;
10476 for(i=0;i<slen-1;i++)
10478 // Can't do anything if no registers are available
10479 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
10480 for(hr=0;hr<HOST_REGS;hr++) {
10481 score[hr]=0;earliest_available[hr]=i+1;
10482 loop_start[hr]=MAXBLOCK;
10485 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10487 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
10488 for(hr=0;hr<HOST_REGS;hr++) {
10489 score[hr]=0;earliest_available[hr]=i+1;
10490 loop_start[hr]=MAXBLOCK;
10494 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
10495 for(hr=0;hr<HOST_REGS;hr++) {
10496 score[hr]=0;earliest_available[hr]=i+1;
10497 loop_start[hr]=MAXBLOCK;
10502 // Mark unavailable registers
10503 for(hr=0;hr<HOST_REGS;hr++) {
10504 if(regs[i].regmap[hr]>=0) {
10505 score[hr]=0;earliest_available[hr]=i+1;
10506 loop_start[hr]=MAXBLOCK;
10508 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
10509 if(branch_regs[i].regmap[hr]>=0) {
10510 score[hr]=0;earliest_available[hr]=i+2;
10511 loop_start[hr]=MAXBLOCK;
10515 // No register allocations after unconditional jumps
10516 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10518 for(hr=0;hr<HOST_REGS;hr++) {
10519 score[hr]=0;earliest_available[hr]=i+2;
10520 loop_start[hr]=MAXBLOCK;
10522 i++; // Skip delay slot too
10523 //printf("skip delay slot: %x\n",start+i*4);
10527 if(itype[i]==LOAD||itype[i]==LOADLR||
10528 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
10529 for(hr=0;hr<HOST_REGS;hr++) {
10530 if(hr!=EXCLUDE_REG) {
10532 for(j=i;j<slen-1;j++) {
10533 if(regs[j].regmap[hr]>=0) break;
10534 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10535 if(branch_regs[j].regmap[hr]>=0) break;
10537 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
10539 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
10542 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
10543 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10544 int t=(ba[j]-start)>>2;
10545 if(t<j&&t>=earliest_available[hr]) {
10546 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
10547 // Score a point for hoisting loop invariant
10548 if(t<loop_start[hr]) loop_start[hr]=t;
10549 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
10555 if(regs[t].regmap[hr]==reg) {
10556 // Score a point if the branch target matches this register
10561 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
10562 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
10567 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
10569 // Stop on unconditional branch
10573 if(itype[j]==LOAD||itype[j]==LOADLR||
10574 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
10581 // Find highest score and allocate that register
10583 for(hr=0;hr<HOST_REGS;hr++) {
10584 if(hr!=EXCLUDE_REG) {
10585 if(score[hr]>score[maxscore]) {
10587 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
10591 if(score[maxscore]>1)
10593 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
10594 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
10595 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
10596 assert(regs[j].regmap[maxscore]<0);
10597 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
10598 regs[j].regmap[maxscore]=reg;
10599 regs[j].dirty&=~(1<<maxscore);
10600 regs[j].wasconst&=~(1<<maxscore);
10601 regs[j].isconst&=~(1<<maxscore);
10602 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
10603 branch_regs[j].regmap[maxscore]=reg;
10604 branch_regs[j].wasdirty&=~(1<<maxscore);
10605 branch_regs[j].dirty&=~(1<<maxscore);
10606 branch_regs[j].wasconst&=~(1<<maxscore);
10607 branch_regs[j].isconst&=~(1<<maxscore);
10608 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
10609 regmap_pre[j+2][maxscore]=reg;
10610 regs[j+2].wasdirty&=~(1<<maxscore);
10612 // loop optimization (loop_preload)
10613 int t=(ba[j]-start)>>2;
10614 if(t==loop_start[maxscore]) {
10615 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
10616 regs[t].regmap_entry[maxscore]=reg;
10621 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
10622 regmap_pre[j+1][maxscore]=reg;
10623 regs[j+1].wasdirty&=~(1<<maxscore);
10628 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
10629 for(hr=0;hr<HOST_REGS;hr++) {
10630 score[hr]=0;earliest_available[hr]=i+i;
10631 loop_start[hr]=MAXBLOCK;
10639 // This allocates registers (if possible) one instruction prior
10640 // to use, which can avoid a load-use penalty on certain CPUs.
10641 for(i=0;i<slen-1;i++)
10643 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
10647 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
10648 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
10651 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
10653 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10655 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10656 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10657 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10658 regs[i].isconst&=~(1<<hr);
10659 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10660 constmap[i][hr]=constmap[i+1][hr];
10661 regs[i+1].wasdirty&=~(1<<hr);
10662 regs[i].dirty&=~(1<<hr);
10667 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
10669 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10671 regs[i].regmap[hr]=regs[i+1].regmap[hr];
10672 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
10673 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
10674 regs[i].isconst&=~(1<<hr);
10675 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10676 constmap[i][hr]=constmap[i+1][hr];
10677 regs[i+1].wasdirty&=~(1<<hr);
10678 regs[i].dirty&=~(1<<hr);
10682 // Preload target address for load instruction (non-constant)
10683 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10684 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10686 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10688 regs[i].regmap[hr]=rs1[i+1];
10689 regmap_pre[i+1][hr]=rs1[i+1];
10690 regs[i+1].regmap_entry[hr]=rs1[i+1];
10691 regs[i].isconst&=~(1<<hr);
10692 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10693 constmap[i][hr]=constmap[i+1][hr];
10694 regs[i+1].wasdirty&=~(1<<hr);
10695 regs[i].dirty&=~(1<<hr);
10699 // Load source into target register
10700 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10701 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
10703 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10705 regs[i].regmap[hr]=rs1[i+1];
10706 regmap_pre[i+1][hr]=rs1[i+1];
10707 regs[i+1].regmap_entry[hr]=rs1[i+1];
10708 regs[i].isconst&=~(1<<hr);
10709 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10710 constmap[i][hr]=constmap[i+1][hr];
10711 regs[i+1].wasdirty&=~(1<<hr);
10712 regs[i].dirty&=~(1<<hr);
10716 // Preload map address
10717 #ifndef HOST_IMM_ADDR32
10718 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
10719 hr=get_reg(regs[i+1].regmap,TLREG);
10721 int sr=get_reg(regs[i+1].regmap,rs1[i+1]);
10722 if(sr>=0&&((regs[i+1].wasconst>>sr)&1)) {
10724 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10726 regs[i].regmap[hr]=MGEN1+((i+1)&1);
10727 regmap_pre[i+1][hr]=MGEN1+((i+1)&1);
10728 regs[i+1].regmap_entry[hr]=MGEN1+((i+1)&1);
10729 regs[i].isconst&=~(1<<hr);
10730 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10731 constmap[i][hr]=constmap[i+1][hr];
10732 regs[i+1].wasdirty&=~(1<<hr);
10733 regs[i].dirty&=~(1<<hr);
10735 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10737 // move it to another register
10738 regs[i+1].regmap[hr]=-1;
10739 regmap_pre[i+2][hr]=-1;
10740 regs[i+1].regmap[nr]=TLREG;
10741 regmap_pre[i+2][nr]=TLREG;
10742 regs[i].regmap[nr]=MGEN1+((i+1)&1);
10743 regmap_pre[i+1][nr]=MGEN1+((i+1)&1);
10744 regs[i+1].regmap_entry[nr]=MGEN1+((i+1)&1);
10745 regs[i].isconst&=~(1<<nr);
10746 regs[i+1].isconst&=~(1<<nr);
10747 regs[i].dirty&=~(1<<nr);
10748 regs[i+1].wasdirty&=~(1<<nr);
10749 regs[i+1].dirty&=~(1<<nr);
10750 regs[i+2].wasdirty&=~(1<<nr);
10756 // Address for store instruction (non-constant)
10757 if(itype[i+1]==STORE||itype[i+1]==STORELR
10758 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
10759 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10760 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
10761 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10762 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
10764 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10766 regs[i].regmap[hr]=rs1[i+1];
10767 regmap_pre[i+1][hr]=rs1[i+1];
10768 regs[i+1].regmap_entry[hr]=rs1[i+1];
10769 regs[i].isconst&=~(1<<hr);
10770 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10771 constmap[i][hr]=constmap[i+1][hr];
10772 regs[i+1].wasdirty&=~(1<<hr);
10773 regs[i].dirty&=~(1<<hr);
10777 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
10778 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
10780 hr=get_reg(regs[i+1].regmap,FTEMP);
10782 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
10784 regs[i].regmap[hr]=rs1[i+1];
10785 regmap_pre[i+1][hr]=rs1[i+1];
10786 regs[i+1].regmap_entry[hr]=rs1[i+1];
10787 regs[i].isconst&=~(1<<hr);
10788 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
10789 constmap[i][hr]=constmap[i+1][hr];
10790 regs[i+1].wasdirty&=~(1<<hr);
10791 regs[i].dirty&=~(1<<hr);
10793 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
10795 // move it to another register
10796 regs[i+1].regmap[hr]=-1;
10797 regmap_pre[i+2][hr]=-1;
10798 regs[i+1].regmap[nr]=FTEMP;
10799 regmap_pre[i+2][nr]=FTEMP;
10800 regs[i].regmap[nr]=rs1[i+1];
10801 regmap_pre[i+1][nr]=rs1[i+1];
10802 regs[i+1].regmap_entry[nr]=rs1[i+1];
10803 regs[i].isconst&=~(1<<nr);
10804 regs[i+1].isconst&=~(1<<nr);
10805 regs[i].dirty&=~(1<<nr);
10806 regs[i+1].wasdirty&=~(1<<nr);
10807 regs[i+1].dirty&=~(1<<nr);
10808 regs[i+2].wasdirty&=~(1<<nr);
10812 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
10813 if(itype[i+1]==LOAD)
10814 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
10815 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
10816 hr=get_reg(regs[i+1].regmap,FTEMP);
10817 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
10818 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
10819 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
10821 if(hr>=0&®s[i].regmap[hr]<0) {
10822 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
10823 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
10824 regs[i].regmap[hr]=AGEN1+((i+1)&1);
10825 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
10826 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
10827 regs[i].isconst&=~(1<<hr);
10828 regs[i+1].wasdirty&=~(1<<hr);
10829 regs[i].dirty&=~(1<<hr);
10838 /* Pass 6 - Optimize clean/dirty state */
10839 clean_registers(0,slen-1,1);
10841 /* Pass 7 - Identify 32-bit registers */
10847 for (i=slen-1;i>=0;i--)
10850 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10852 if(ba[i]<start || ba[i]>=(start+slen*4))
10854 // Branch out of this block, don't need anything
10860 // Need whatever matches the target
10861 // (and doesn't get overwritten by the delay slot instruction)
10863 int t=(ba[i]-start)>>2;
10864 if(ba[i]>start+i*4) {
10866 if(!(requires_32bit[t]&~regs[i].was32))
10867 r32|=requires_32bit[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10870 //if(!(regs[t].was32&~unneeded_reg_upper[t]&~regs[i].was32))
10871 // r32|=regs[t].was32&~unneeded_reg_upper[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10872 if(!(pr32[t]&~regs[i].was32))
10873 r32|=pr32[t]&(~(1LL<<rt1[i+1]))&(~(1LL<<rt2[i+1]));
10876 // Conditional branch may need registers for following instructions
10877 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
10880 r32|=requires_32bit[i+2];
10881 r32&=regs[i].was32;
10882 // Mark this address as a branch target since it may be called
10883 // upon return from interrupt
10887 // Merge in delay slot
10889 // These are overwritten unless the branch is "likely"
10890 // and the delay slot is nullified if not taken
10891 r32&=~(1LL<<rt1[i+1]);
10892 r32&=~(1LL<<rt2[i+1]);
10894 // Assume these are needed (delay slot)
10897 if((regs[i].was32>>us1[i+1])&1) r32|=1LL<<us1[i+1];
10901 if((regs[i].was32>>us2[i+1])&1) r32|=1LL<<us2[i+1];
10903 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1))
10905 if((regs[i].was32>>dep1[i+1])&1) r32|=1LL<<dep1[i+1];
10907 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1))
10909 if((regs[i].was32>>dep2[i+1])&1) r32|=1LL<<dep2[i+1];
10912 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
10914 // SYSCALL instruction (software interrupt)
10917 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
10919 // ERET instruction (return from interrupt)
10923 r32&=~(1LL<<rt1[i]);
10924 r32&=~(1LL<<rt2[i]);
10927 if((regs[i].was32>>us1[i])&1) r32|=1LL<<us1[i];
10931 if((regs[i].was32>>us2[i])&1) r32|=1LL<<us2[i];
10933 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1))
10935 if((regs[i].was32>>dep1[i])&1) r32|=1LL<<dep1[i];
10937 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1))
10939 if((regs[i].was32>>dep2[i])&1) r32|=1LL<<dep2[i];
10941 requires_32bit[i]=r32;
10943 // Dirty registers which are 32-bit, require 32-bit input
10944 // as they will be written as 32-bit values
10945 for(hr=0;hr<HOST_REGS;hr++)
10947 if(regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64) {
10948 if((regs[i].was32>>regs[i].regmap_entry[hr])&(regs[i].wasdirty>>hr)&1) {
10949 if(!((unneeded_reg_upper[i]>>regs[i].regmap_entry[hr])&1))
10950 requires_32bit[i]|=1LL<<regs[i].regmap_entry[hr];
10954 //requires_32bit[i]=is32[i]&~unneeded_reg_upper[i]; // DEBUG
10957 for (i=slen-1;i>=0;i--)
10959 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
10961 // Conditional branch
10962 if((source[i]>>16)!=0x1000&&i<slen-2) {
10963 // Mark this address as a branch target since it may be called
10964 // upon return from interrupt
10971 if(itype[slen-1]==SPAN) {
10972 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
10976 /* Debug/disassembly */
10977 for(i=0;i<slen;i++)
10981 for(r=1;r<=CCREG;r++) {
10982 if((unneeded_reg[i]>>r)&1) {
10983 if(r==HIREG) printf(" HI");
10984 else if(r==LOREG) printf(" LO");
10985 else printf(" r%d",r);
10990 for(r=1;r<=CCREG;r++) {
10991 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
10992 if(r==HIREG) printf(" HI");
10993 else if(r==LOREG) printf(" LO");
10994 else printf(" r%d",r);
10998 for(r=0;r<=CCREG;r++) {
10999 //if(((is32[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11000 if((regs[i].was32>>r)&1) {
11001 if(r==CCREG) printf(" CC");
11002 else if(r==HIREG) printf(" HI");
11003 else if(r==LOREG) printf(" LO");
11004 else printf(" r%d",r);
11009 #if defined(__i386__) || defined(__x86_64__)
11010 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
11013 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
11016 if(needed_reg[i]&1) printf("eax ");
11017 if((needed_reg[i]>>1)&1) printf("ecx ");
11018 if((needed_reg[i]>>2)&1) printf("edx ");
11019 if((needed_reg[i]>>3)&1) printf("ebx ");
11020 if((needed_reg[i]>>5)&1) printf("ebp ");
11021 if((needed_reg[i]>>6)&1) printf("esi ");
11022 if((needed_reg[i]>>7)&1) printf("edi ");
11024 for(r=0;r<=CCREG;r++) {
11025 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11026 if((requires_32bit[i]>>r)&1) {
11027 if(r==CCREG) printf(" CC");
11028 else if(r==HIREG) printf(" HI");
11029 else if(r==LOREG) printf(" LO");
11030 else printf(" r%d",r);
11035 for(r=0;r<=CCREG;r++) {
11036 //if(((requires_32bit[i]>>r)&(~unneeded_reg[i]>>r))&1) {
11037 if((pr32[i]>>r)&1) {
11038 if(r==CCREG) printf(" CC");
11039 else if(r==HIREG) printf(" HI");
11040 else if(r==LOREG) printf(" LO");
11041 else printf(" r%d",r);
11044 if(pr32[i]!=requires_32bit[i]) printf(" OOPS");
11046 #if defined(__i386__) || defined(__x86_64__)
11047 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
11049 if(regs[i].wasdirty&1) printf("eax ");
11050 if((regs[i].wasdirty>>1)&1) printf("ecx ");
11051 if((regs[i].wasdirty>>2)&1) printf("edx ");
11052 if((regs[i].wasdirty>>3)&1) printf("ebx ");
11053 if((regs[i].wasdirty>>5)&1) printf("ebp ");
11054 if((regs[i].wasdirty>>6)&1) printf("esi ");
11055 if((regs[i].wasdirty>>7)&1) printf("edi ");
11058 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
11060 if(regs[i].wasdirty&1) printf("r0 ");
11061 if((regs[i].wasdirty>>1)&1) printf("r1 ");
11062 if((regs[i].wasdirty>>2)&1) printf("r2 ");
11063 if((regs[i].wasdirty>>3)&1) printf("r3 ");
11064 if((regs[i].wasdirty>>4)&1) printf("r4 ");
11065 if((regs[i].wasdirty>>5)&1) printf("r5 ");
11066 if((regs[i].wasdirty>>6)&1) printf("r6 ");
11067 if((regs[i].wasdirty>>7)&1) printf("r7 ");
11068 if((regs[i].wasdirty>>8)&1) printf("r8 ");
11069 if((regs[i].wasdirty>>9)&1) printf("r9 ");
11070 if((regs[i].wasdirty>>10)&1) printf("r10 ");
11071 if((regs[i].wasdirty>>12)&1) printf("r12 ");
11074 disassemble_inst(i);
11075 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
11076 #if defined(__i386__) || defined(__x86_64__)
11077 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
11078 if(regs[i].dirty&1) printf("eax ");
11079 if((regs[i].dirty>>1)&1) printf("ecx ");
11080 if((regs[i].dirty>>2)&1) printf("edx ");
11081 if((regs[i].dirty>>3)&1) printf("ebx ");
11082 if((regs[i].dirty>>5)&1) printf("ebp ");
11083 if((regs[i].dirty>>6)&1) printf("esi ");
11084 if((regs[i].dirty>>7)&1) printf("edi ");
11087 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
11088 if(regs[i].dirty&1) printf("r0 ");
11089 if((regs[i].dirty>>1)&1) printf("r1 ");
11090 if((regs[i].dirty>>2)&1) printf("r2 ");
11091 if((regs[i].dirty>>3)&1) printf("r3 ");
11092 if((regs[i].dirty>>4)&1) printf("r4 ");
11093 if((regs[i].dirty>>5)&1) printf("r5 ");
11094 if((regs[i].dirty>>6)&1) printf("r6 ");
11095 if((regs[i].dirty>>7)&1) printf("r7 ");
11096 if((regs[i].dirty>>8)&1) printf("r8 ");
11097 if((regs[i].dirty>>9)&1) printf("r9 ");
11098 if((regs[i].dirty>>10)&1) printf("r10 ");
11099 if((regs[i].dirty>>12)&1) printf("r12 ");
11102 if(regs[i].isconst) {
11103 printf("constants: ");
11104 #if defined(__i386__) || defined(__x86_64__)
11105 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
11106 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
11107 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
11108 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
11109 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
11110 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
11111 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
11114 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
11115 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
11116 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
11117 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
11118 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
11119 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
11120 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
11121 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
11122 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
11123 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
11124 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
11125 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
11131 for(r=0;r<=CCREG;r++) {
11132 if((regs[i].is32>>r)&1) {
11133 if(r==CCREG) printf(" CC");
11134 else if(r==HIREG) printf(" HI");
11135 else if(r==LOREG) printf(" LO");
11136 else printf(" r%d",r);
11142 for(r=0;r<=CCREG;r++) {
11143 if((p32[i]>>r)&1) {
11144 if(r==CCREG) printf(" CC");
11145 else if(r==HIREG) printf(" HI");
11146 else if(r==LOREG) printf(" LO");
11147 else printf(" r%d",r);
11150 if(p32[i]!=regs[i].is32) printf(" NO MATCH\n");
11151 else printf("\n");*/
11152 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
11153 #if defined(__i386__) || defined(__x86_64__)
11154 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
11155 if(branch_regs[i].dirty&1) printf("eax ");
11156 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
11157 if((branch_regs[i].dirty>>2)&1) printf("edx ");
11158 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
11159 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
11160 if((branch_regs[i].dirty>>6)&1) printf("esi ");
11161 if((branch_regs[i].dirty>>7)&1) printf("edi ");
11164 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
11165 if(branch_regs[i].dirty&1) printf("r0 ");
11166 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
11167 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
11168 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
11169 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
11170 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
11171 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
11172 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
11173 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
11174 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
11175 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
11176 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
11180 for(r=0;r<=CCREG;r++) {
11181 if((branch_regs[i].is32>>r)&1) {
11182 if(r==CCREG) printf(" CC");
11183 else if(r==HIREG) printf(" HI");
11184 else if(r==LOREG) printf(" LO");
11185 else printf(" r%d",r);
11194 /* Pass 8 - Assembly */
11195 linkcount=0;stubcount=0;
11196 ds=0;is_delayslot=0;
11198 uint64_t is32_pre=0;
11200 u_int beginning=(u_int)out;
11201 if((u_int)addr&1) {
11205 u_int instr_addr0_override=0;
11208 if (start == 0x80030000) {
11209 // nasty hack for fastbios thing
11210 // override block entry to this code
11211 instr_addr0_override=(u_int)out;
11212 emit_movimm(start,0);
11213 // abuse io address var as a flag that we
11214 // have already returned here once
11215 emit_readword((int)&address,1);
11216 emit_writeword(0,(int)&pcaddr);
11217 emit_writeword(0,(int)&address);
11219 emit_jne((int)new_dyna_leave);
11222 for(i=0;i<slen;i++)
11224 //if(ds) printf("ds: ");
11225 disassemble_inst(i);
11227 ds=0; // Skip delay slot
11228 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
11231 speculate_register_values(i);
11232 #ifndef DESTRUCTIVE_WRITEBACK
11233 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11235 wb_sx(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,is32_pre,regs[i].was32,
11236 unneeded_reg[i],unneeded_reg_upper[i]);
11237 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
11238 unneeded_reg[i],unneeded_reg_upper[i]);
11240 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
11241 is32_pre=branch_regs[i].is32;
11242 dirty_pre=branch_regs[i].dirty;
11244 is32_pre=regs[i].is32;
11245 dirty_pre=regs[i].dirty;
11249 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
11251 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
11252 unneeded_reg[i],unneeded_reg_upper[i]);
11253 loop_preload(regmap_pre[i],regs[i].regmap_entry);
11255 // branch target entry point
11256 instr_addr[i]=(u_int)out;
11257 assem_debug("<->\n");
11259 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
11260 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
11261 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
11262 address_generation(i,®s[i],regs[i].regmap_entry);
11263 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
11264 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
11266 // Load the delay slot registers if necessary
11267 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
11268 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11269 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
11270 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11271 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
11272 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11276 // Preload registers for following instruction
11277 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
11278 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
11279 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
11280 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
11281 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
11282 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
11284 // TODO: if(is_ooo(i)) address_generation(i+1);
11285 if(itype[i]==CJUMP||itype[i]==FJUMP)
11286 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
11287 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
11288 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
11289 if(bt[i]) cop1_usable=0;
11293 alu_assemble(i,®s[i]);break;
11295 imm16_assemble(i,®s[i]);break;
11297 shift_assemble(i,®s[i]);break;
11299 shiftimm_assemble(i,®s[i]);break;
11301 load_assemble(i,®s[i]);break;
11303 loadlr_assemble(i,®s[i]);break;
11305 store_assemble(i,®s[i]);break;
11307 storelr_assemble(i,®s[i]);break;
11309 cop0_assemble(i,®s[i]);break;
11311 cop1_assemble(i,®s[i]);break;
11313 c1ls_assemble(i,®s[i]);break;
11315 cop2_assemble(i,®s[i]);break;
11317 c2ls_assemble(i,®s[i]);break;
11319 c2op_assemble(i,®s[i]);break;
11321 fconv_assemble(i,®s[i]);break;
11323 float_assemble(i,®s[i]);break;
11325 fcomp_assemble(i,®s[i]);break;
11327 multdiv_assemble(i,®s[i]);break;
11329 mov_assemble(i,®s[i]);break;
11331 syscall_assemble(i,®s[i]);break;
11333 hlecall_assemble(i,®s[i]);break;
11335 intcall_assemble(i,®s[i]);break;
11337 ujump_assemble(i,®s[i]);ds=1;break;
11339 rjump_assemble(i,®s[i]);ds=1;break;
11341 cjump_assemble(i,®s[i]);ds=1;break;
11343 sjump_assemble(i,®s[i]);ds=1;break;
11345 fjump_assemble(i,®s[i]);ds=1;break;
11347 pagespan_assemble(i,®s[i]);break;
11349 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
11350 literal_pool(1024);
11352 literal_pool_jumpover(256);
11355 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
11356 // If the block did not end with an unconditional branch,
11357 // add a jump to the next instruction.
11359 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
11360 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11362 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
11363 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11364 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11365 emit_loadreg(CCREG,HOST_CCREG);
11366 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11368 else if(!likely[i-2])
11370 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
11371 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
11375 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
11376 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
11378 add_to_linker((int)out,start+i*4,0);
11385 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
11386 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
11387 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
11388 emit_loadreg(CCREG,HOST_CCREG);
11389 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
11390 add_to_linker((int)out,start+i*4,0);
11394 // TODO: delay slot stubs?
11396 for(i=0;i<stubcount;i++)
11398 switch(stubs[i][0])
11406 do_readstub(i);break;
11411 do_writestub(i);break;
11413 do_ccstub(i);break;
11415 do_invstub(i);break;
11417 do_cop1stub(i);break;
11419 do_unalignedwritestub(i);break;
11423 if (instr_addr0_override)
11424 instr_addr[0] = instr_addr0_override;
11426 /* Pass 9 - Linker */
11427 for(i=0;i<linkcount;i++)
11429 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
11431 if(!link_addr[i][2])
11434 void *addr=check_addr(link_addr[i][1]);
11435 emit_extjump(link_addr[i][0],link_addr[i][1]);
11437 set_jump_target(link_addr[i][0],(int)addr);
11438 add_link(link_addr[i][1],stub);
11440 else set_jump_target(link_addr[i][0],(int)stub);
11445 int target=(link_addr[i][1]-start)>>2;
11446 assert(target>=0&&target<slen);
11447 assert(instr_addr[target]);
11448 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11449 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
11451 set_jump_target(link_addr[i][0],instr_addr[target]);
11455 // External Branch Targets (jump_in)
11456 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
11457 for(i=0;i<slen;i++)
11461 if(instr_addr[i]) // TODO - delay slots (=null)
11463 u_int vaddr=start+i*4;
11464 u_int page=get_page(vaddr);
11465 u_int vpage=get_vpage(vaddr);
11467 //if(!(is32[i]&(~unneeded_reg_upper[i])&~(1LL<<CCREG)))
11469 if(!requires_32bit[i])
11474 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11475 assem_debug("jump_in: %x\n",start+i*4);
11476 ll_add(jump_dirty+vpage,vaddr,(void *)out);
11477 int entry_point=do_dirty_stub(i);
11478 ll_add(jump_in+page,vaddr,(void *)entry_point);
11479 // If there was an existing entry in the hash table,
11480 // replace it with the new address.
11481 // Don't add new entries. We'll insert the
11482 // ones that actually get used in check_addr().
11483 int *ht_bin=hash_table[((vaddr>>16)^vaddr)&0xFFFF];
11484 if(ht_bin[0]==vaddr) {
11485 ht_bin[1]=entry_point;
11487 if(ht_bin[2]==vaddr) {
11488 ht_bin[3]=entry_point;
11493 u_int r=requires_32bit[i]|!!(requires_32bit[i]>>32);
11494 assem_debug("%8x (%d) <- %8x\n",instr_addr[i],i,start+i*4);
11495 assem_debug("jump_in: %x (restricted - %x)\n",start+i*4,r);
11496 //int entry_point=(int)out;
11497 ////assem_debug("entry_point: %x\n",entry_point);
11498 //load_regs_entry(i);
11499 //if(entry_point==(int)out)
11500 // entry_point=instr_addr[i];
11502 // emit_jmp(instr_addr[i]);
11503 //ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11504 ll_add_32(jump_dirty+vpage,vaddr,r,(void *)out);
11505 int entry_point=do_dirty_stub(i);
11506 ll_add_32(jump_in+page,vaddr,r,(void *)entry_point);
11511 // Write out the literal pool if necessary
11513 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
11515 if(((u_int)out)&7) emit_addnop(13);
11517 assert((u_int)out-beginning<MAX_OUTPUT_BLOCK_SIZE);
11518 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
11519 memcpy(copy,source,slen*4);
11523 __clear_cache((void *)beginning,out);
11526 // If we're within 256K of the end of the buffer,
11527 // start over from the beginning. (Is 256K enough?)
11528 if((int)out>BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
11530 // Trap writes to any of the pages we compiled
11531 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
11533 #ifndef DISABLE_TLB
11534 memory_map[i]|=0x40000000;
11535 if((signed int)start>=(signed int)0xC0000000) {
11537 j=(((u_int)i<<12)+(memory_map[i]<<2)-(u_int)rdram+(u_int)0x80000000)>>12;
11539 memory_map[j]|=0x40000000;
11540 //printf("write protect physical page: %x (virtual %x)\n",j<<12,start);
11544 inv_code_start=inv_code_end=~0;
11546 // for PCSX we need to mark all mirrors too
11547 if(get_page(start)<(RAM_SIZE>>12))
11548 for(i=start>>12;i<=(start+slen*4)>>12;i++)
11549 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
11550 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
11551 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
11554 /* Pass 10 - Free memory by expiring oldest blocks */
11556 int end=((((int)out-BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
11557 while(expirep!=end)
11559 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
11560 int base=BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
11561 inv_debug("EXP: Phase %d\n",expirep);
11562 switch((expirep>>11)&3)
11565 // Clear jump_in and jump_dirty
11566 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
11567 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
11568 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
11569 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
11573 ll_kill_pointers(jump_out[expirep&2047],base,shift);
11574 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
11577 // Clear hash table
11578 for(i=0;i<32;i++) {
11579 int *ht_bin=hash_table[((expirep&2047)<<5)+i];
11580 if((ht_bin[3]>>shift)==(base>>shift) ||
11581 ((ht_bin[3]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11582 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[2],ht_bin[3]);
11583 ht_bin[2]=ht_bin[3]=-1;
11585 if((ht_bin[1]>>shift)==(base>>shift) ||
11586 ((ht_bin[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
11587 inv_debug("EXP: Remove hash %x -> %x\n",ht_bin[0],ht_bin[1]);
11588 ht_bin[0]=ht_bin[2];
11589 ht_bin[1]=ht_bin[3];
11590 ht_bin[2]=ht_bin[3]=-1;
11597 if((expirep&2047)==0)
11600 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
11601 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
11604 expirep=(expirep+1)&65535;
11609 // vim:shiftwidth=2:expandtab