1 /* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
2 * Mupen64plus - new_dynarec.c *
3 * Copyright (C) 2009-2011 Ari64 *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. *
19 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
22 #include <stdint.h> //include for uint64_t
27 #include <libkern/OSCacheControl.h>
30 #include <3ds_utils.h>
33 #include <psp2/kernel/sysmem.h>
37 #include "new_dynarec_config.h"
38 #include "../psxhle.h" //emulator interface
39 #include "emu_if.h" //emulator interface
42 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(x[0]))
46 //#define assem_debug printf
47 //#define inv_debug printf
48 #define assem_debug(...)
49 #define inv_debug(...)
52 #include "assem_x86.h"
55 #include "assem_x64.h"
58 #include "assem_arm.h"
62 #define MAX_OUTPUT_BLOCK_SIZE 262144
84 signed char regmap_entry[HOST_REGS];
85 signed char regmap[HOST_REGS];
94 u_int loadedconst; // host regs that have constants loaded
95 u_int waswritten; // MIPS regs that were used as store base before
98 // note: asm depends on this layout
104 struct ll_entry *next;
127 struct ht_entry hash_table[65536] __attribute__((aligned(16)));
128 struct ll_entry *jump_in[4096] __attribute__((aligned(16)));
129 struct ll_entry *jump_dirty[4096];
131 static struct ll_entry *jump_out[4096];
133 static u_int *source;
134 static char insn[MAXBLOCK][10];
135 static u_char itype[MAXBLOCK];
136 static u_char opcode[MAXBLOCK];
137 static u_char opcode2[MAXBLOCK];
138 static u_char bt[MAXBLOCK];
139 static u_char rs1[MAXBLOCK];
140 static u_char rs2[MAXBLOCK];
141 static u_char rt1[MAXBLOCK];
142 static u_char rt2[MAXBLOCK];
143 static u_char us1[MAXBLOCK];
144 static u_char us2[MAXBLOCK];
145 static u_char dep1[MAXBLOCK];
146 static u_char dep2[MAXBLOCK];
147 static u_char lt1[MAXBLOCK];
148 static uint64_t gte_rs[MAXBLOCK]; // gte: 32 data and 32 ctl regs
149 static uint64_t gte_rt[MAXBLOCK];
150 static uint64_t gte_unneeded[MAXBLOCK];
151 static u_int smrv[32]; // speculated MIPS register values
152 static u_int smrv_strong; // mask or regs that are likely to have correct values
153 static u_int smrv_weak; // same, but somewhat less likely
154 static u_int smrv_strong_next; // same, but after current insn executes
155 static u_int smrv_weak_next;
156 static int imm[MAXBLOCK];
157 static u_int ba[MAXBLOCK];
158 static char likely[MAXBLOCK];
159 static char is_ds[MAXBLOCK];
160 static char ooo[MAXBLOCK];
161 static uint64_t unneeded_reg[MAXBLOCK];
162 static uint64_t unneeded_reg_upper[MAXBLOCK];
163 static uint64_t branch_unneeded_reg[MAXBLOCK];
164 static uint64_t branch_unneeded_reg_upper[MAXBLOCK];
165 static signed char regmap_pre[MAXBLOCK][HOST_REGS];
166 static uint64_t current_constmap[HOST_REGS];
167 static uint64_t constmap[MAXBLOCK][HOST_REGS];
168 static struct regstat regs[MAXBLOCK];
169 static struct regstat branch_regs[MAXBLOCK];
170 static signed char minimum_free_regs[MAXBLOCK];
171 static u_int needed_reg[MAXBLOCK];
172 static u_int wont_dirty[MAXBLOCK];
173 static u_int will_dirty[MAXBLOCK];
174 static int ccadj[MAXBLOCK];
176 static void *instr_addr[MAXBLOCK];
177 static u_int link_addr[MAXBLOCK][3];
178 static int linkcount;
179 static struct code_stub stubs[MAXBLOCK*3];
180 static int stubcount;
181 static u_int literals[1024][2];
182 static int literalcount;
183 static int is_delayslot;
184 static int cop1_usable;
185 static char shadow[1048576] __attribute__((aligned(16)));
188 static u_int stop_after_jal;
190 static u_int ram_offset;
192 static const u_int ram_offset=0;
195 int new_dynarec_hacks;
196 int new_dynarec_did_compile;
197 extern u_char restore_candidate[512];
198 extern int cycle_count;
200 /* registers that may be allocated */
202 #define HIREG 32 // hi
203 #define LOREG 33 // lo
204 #define FSREG 34 // FPU status (FCSR)
205 #define CSREG 35 // Coprocessor status
206 #define CCREG 36 // Cycle count
207 #define INVCP 37 // Pointer to invalid_code
208 //#define MMREG 38 // Pointer to memory_map
209 #define ROREG 39 // ram offset (if rdram!=0x80000000)
211 #define FTEMP 40 // FPU temporary register
212 #define PTEMP 41 // Prefetch temporary register
213 //#define TLREG 42 // TLB mapping offset
214 #define RHASH 43 // Return address hash
215 #define RHTBL 44 // Return address hash table address
216 #define RTEMP 45 // JR/JALR address register
218 #define AGEN1 46 // Address generation temporary register
219 //#define AGEN2 47 // Address generation temporary register
220 //#define MGEN1 48 // Maptable address generation temporary register
221 //#define MGEN2 49 // Maptable address generation temporary register
222 #define BTREG 50 // Branch target temporary register
224 /* instruction types */
225 #define NOP 0 // No operation
226 #define LOAD 1 // Load
227 #define STORE 2 // Store
228 #define LOADLR 3 // Unaligned load
229 #define STORELR 4 // Unaligned store
230 #define MOV 5 // Move
231 #define ALU 6 // Arithmetic/logic
232 #define MULTDIV 7 // Multiply/divide
233 #define SHIFT 8 // Shift by register
234 #define SHIFTIMM 9// Shift by immediate
235 #define IMM16 10 // 16-bit immediate
236 #define RJUMP 11 // Unconditional jump to register
237 #define UJUMP 12 // Unconditional jump
238 #define CJUMP 13 // Conditional branch (BEQ/BNE/BGTZ/BLEZ)
239 #define SJUMP 14 // Conditional branch (regimm format)
240 #define COP0 15 // Coprocessor 0
241 #define COP1 16 // Coprocessor 1
242 #define C1LS 17 // Coprocessor 1 load/store
243 #define FJUMP 18 // Conditional branch (floating point)
244 #define FLOAT 19 // Floating point unit
245 #define FCONV 20 // Convert integer to float
246 #define FCOMP 21 // Floating point compare (sets FSREG)
247 #define SYSCALL 22// SYSCALL
248 #define OTHER 23 // Other
249 #define SPAN 24 // Branch/delay slot spans 2 pages
250 #define NI 25 // Not implemented
251 #define HLECALL 26// PCSX fake opcodes for HLE
252 #define COP2 27 // Coprocessor 2 move
253 #define C2LS 28 // Coprocessor 2 load/store
254 #define C2OP 29 // Coprocessor 2 operation
255 #define INTCALL 30// Call interpreter to handle rare corner cases
263 int new_recompile_block(int addr);
264 void *get_addr_ht(u_int vaddr);
265 void invalidate_block(u_int block);
266 void invalidate_addr(u_int addr);
267 void remove_hash(int vaddr);
269 void dyna_linker_ds();
271 void verify_code_vm();
272 void verify_code_ds();
275 void fp_exception_ds();
276 void jump_syscall_hle();
279 void new_dyna_leave();
281 // Needed by assembler
282 static void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32);
283 static void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty);
284 static void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr);
285 static void load_all_regs(signed char i_regmap[]);
286 static void load_needed_regs(signed char i_regmap[],signed char next_regmap[]);
287 static void load_regs_entry(int t);
288 static void load_all_consts(signed char regmap[],int is32,u_int dirty,int i);
290 static int verify_dirty(u_int *ptr);
291 static int get_final_value(int hr, int i, int *value);
292 static void add_stub(enum stub_type type, void *addr, void *retaddr,
293 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e);
294 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
295 int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist);
296 static void add_to_linker(int addr,int target,int ext);
298 static int tracedebug=0;
300 static void mprotect_w_x(void *start, void *end, int is_x)
304 // *Open* enables write on all memory that was
305 // allocated by sceKernelAllocMemBlockForVM()?
307 sceKernelCloseVMDomain();
309 sceKernelOpenVMDomain();
311 u_long mstart = (u_long)start & ~4095ul;
312 u_long mend = (u_long)end;
313 if (mprotect((void *)mstart, mend - mstart,
314 PROT_READ | (is_x ? PROT_EXEC : PROT_WRITE)) != 0)
315 SysPrintf("mprotect(%c) failed: %s\n", is_x ? 'x' : 'w', strerror(errno));
320 static void start_tcache_write(void *start, void *end)
322 mprotect_w_x(start, end, 0);
325 static void end_tcache_write(void *start, void *end)
328 size_t len = (char *)end - (char *)start;
329 #if defined(__BLACKBERRY_QNX__)
330 msync(start, len, MS_SYNC | MS_CACHE_ONLY | MS_INVALIDATE_ICACHE);
331 #elif defined(__MACH__)
332 sys_cache_control(kCacheFunctionPrepareForExecution, start, len);
334 sceKernelSyncVMDomain(sceBlock, start, len);
336 ctr_flush_invalidate_cache();
338 __clear_cache(start, end);
343 mprotect_w_x(start, end, 1);
346 static void *start_block(void)
348 u_char *end = out + MAX_OUTPUT_BLOCK_SIZE;
349 if (end > (u_char *)BASE_ADDR + (1<<TARGET_SIZE_2))
350 end = (u_char *)BASE_ADDR + (1<<TARGET_SIZE_2);
351 start_tcache_write(out, end);
355 static void end_block(void *start)
357 end_tcache_write(start, out);
360 //#define DEBUG_CYCLE_COUNT 1
362 #define NO_CYCLE_PENALTY_THR 12
364 int cycle_multiplier; // 100 for 1.0
366 static int CLOCK_ADJUST(int x)
369 return (x * cycle_multiplier + s * 50) / 100;
372 static u_int get_page(u_int vaddr)
374 u_int page=vaddr&~0xe0000000;
375 if (page < 0x1000000)
376 page &= ~0x0e00000; // RAM mirrors
378 if(page>2048) page=2048+(page&2047);
382 // no virtual mem in PCSX
383 static u_int get_vpage(u_int vaddr)
385 return get_page(vaddr);
388 static struct ht_entry *hash_table_get(u_int vaddr)
390 return &hash_table[((vaddr>>16)^vaddr)&0xFFFF];
393 static void hash_table_add(struct ht_entry *ht_bin, u_int vaddr, void *tcaddr)
395 ht_bin->vaddr[1] = ht_bin->vaddr[0];
396 ht_bin->tcaddr[1] = ht_bin->tcaddr[0];
397 ht_bin->vaddr[0] = vaddr;
398 ht_bin->tcaddr[0] = tcaddr;
401 // some messy ari64's code, seems to rely on unsigned 32bit overflow
402 static int doesnt_expire_soon(void *tcaddr)
404 u_int diff = (u_int)((u_char *)tcaddr - out) << (32-TARGET_SIZE_2);
405 return diff > (u_int)(0x60000000 + (MAX_OUTPUT_BLOCK_SIZE << (32-TARGET_SIZE_2)));
408 // Get address from virtual address
409 // This is called from the recompiled JR/JALR instructions
410 void *get_addr(u_int vaddr)
412 u_int page=get_page(vaddr);
413 u_int vpage=get_vpage(vaddr);
414 struct ll_entry *head;
415 //printf("TRACE: count=%d next=%d (get_addr %x,page %d)\n",Count,next_interupt,vaddr,page);
418 if(head->vaddr==vaddr) {
419 //printf("TRACE: count=%d next=%d (get_addr match %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
420 hash_table_add(hash_table_get(vaddr), vaddr, head->addr);
425 head=jump_dirty[vpage];
427 if(head->vaddr==vaddr) {
428 //printf("TRACE: count=%d next=%d (get_addr match dirty %x: %x)\n",Count,next_interupt,vaddr,(int)head->addr);
429 // Don't restore blocks which are about to expire from the cache
430 if (doesnt_expire_soon(head->addr))
431 if (verify_dirty(head->addr)) {
432 //printf("restore candidate: %x (%d) d=%d\n",vaddr,page,invalid_code[vaddr>>12]);
433 invalid_code[vaddr>>12]=0;
434 inv_code_start=inv_code_end=~0;
436 restore_candidate[vpage>>3]|=1<<(vpage&7);
438 else restore_candidate[page>>3]|=1<<(page&7);
439 struct ht_entry *ht_bin = hash_table_get(vaddr);
440 if (ht_bin->vaddr[0] == vaddr)
441 ht_bin->tcaddr[0] = head->addr; // Replace existing entry
443 hash_table_add(ht_bin, vaddr, head->addr);
450 //printf("TRACE: count=%d next=%d (get_addr no-match %x)\n",Count,next_interupt,vaddr);
451 int r=new_recompile_block(vaddr);
452 if(r==0) return get_addr(vaddr);
453 // Execute in unmapped page, generate pagefault execption
455 Cause=(vaddr<<31)|0x8;
456 EPC=(vaddr&1)?vaddr-5:vaddr;
458 Context=(Context&0xFF80000F)|((BadVAddr>>9)&0x007FFFF0);
459 EntryHi=BadVAddr&0xFFFFE000;
460 return get_addr_ht(0x80000000);
462 // Look up address in hash table first
463 void *get_addr_ht(u_int vaddr)
465 //printf("TRACE: count=%d next=%d (get_addr_ht %x)\n",Count,next_interupt,vaddr);
466 const struct ht_entry *ht_bin = hash_table_get(vaddr);
467 if (ht_bin->vaddr[0] == vaddr) return ht_bin->tcaddr[0];
468 if (ht_bin->vaddr[1] == vaddr) return ht_bin->tcaddr[1];
469 return get_addr(vaddr);
472 void clear_all_regs(signed char regmap[])
475 for (hr=0;hr<HOST_REGS;hr++) regmap[hr]=-1;
478 signed char get_reg(signed char regmap[],int r)
481 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map[hr]==r) return hr;
485 // Find a register that is available for two consecutive cycles
486 signed char get_reg2(signed char regmap1[],signed char regmap2[],int r)
489 for (hr=0;hr<HOST_REGS;hr++) if(hr!=EXCLUDE_REG&®map1[hr]==r&®map2[hr]==r) return hr;
493 int count_free_regs(signed char regmap[])
497 for(hr=0;hr<HOST_REGS;hr++)
499 if(hr!=EXCLUDE_REG) {
500 if(regmap[hr]<0) count++;
506 void dirty_reg(struct regstat *cur,signed char reg)
510 for (hr=0;hr<HOST_REGS;hr++) {
511 if((cur->regmap[hr]&63)==reg) {
517 // If we dirty the lower half of a 64 bit register which is now being
518 // sign-extended, we need to dump the upper half.
519 // Note: Do this only after completion of the instruction, because
520 // some instructions may need to read the full 64-bit value even if
521 // overwriting it (eg SLTI, DSRA32).
522 static void flush_dirty_uppers(struct regstat *cur)
525 for (hr=0;hr<HOST_REGS;hr++) {
526 if((cur->dirty>>hr)&1) {
529 if((cur->is32>>(reg&63))&1) cur->regmap[hr]=-1;
534 void set_const(struct regstat *cur,signed char reg,uint64_t value)
538 for (hr=0;hr<HOST_REGS;hr++) {
539 if(cur->regmap[hr]==reg) {
541 current_constmap[hr]=value;
543 else if((cur->regmap[hr]^64)==reg) {
545 current_constmap[hr]=value>>32;
550 void clear_const(struct regstat *cur,signed char reg)
554 for (hr=0;hr<HOST_REGS;hr++) {
555 if((cur->regmap[hr]&63)==reg) {
556 cur->isconst&=~(1<<hr);
561 int is_const(struct regstat *cur,signed char reg)
566 for (hr=0;hr<HOST_REGS;hr++) {
567 if((cur->regmap[hr]&63)==reg) {
568 return (cur->isconst>>hr)&1;
573 uint64_t get_const(struct regstat *cur,signed char reg)
577 for (hr=0;hr<HOST_REGS;hr++) {
578 if(cur->regmap[hr]==reg) {
579 return current_constmap[hr];
582 SysPrintf("Unknown constant in r%d\n",reg);
586 // Least soon needed registers
587 // Look at the next ten instructions and see which registers
588 // will be used. Try not to reallocate these.
589 void lsn(u_char hsn[], int i, int *preferred_reg)
599 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
601 // Don't go past an unconditonal jump
608 if(rs1[i+j]) hsn[rs1[i+j]]=j;
609 if(rs2[i+j]) hsn[rs2[i+j]]=j;
610 if(rt1[i+j]) hsn[rt1[i+j]]=j;
611 if(rt2[i+j]) hsn[rt2[i+j]]=j;
612 if(itype[i+j]==STORE || itype[i+j]==STORELR) {
613 // Stores can allocate zero
617 // On some architectures stores need invc_ptr
618 #if defined(HOST_IMM8)
619 if(itype[i+j]==STORE || itype[i+j]==STORELR || (opcode[i+j]&0x3b)==0x39 || (opcode[i+j]&0x3b)==0x3a) {
623 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
631 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
633 // Follow first branch
634 int t=(ba[i+b]-start)>>2;
635 j=7-b;if(t+j>=slen) j=slen-t-1;
638 if(rs1[t+j]) if(hsn[rs1[t+j]]>j+b+2) hsn[rs1[t+j]]=j+b+2;
639 if(rs2[t+j]) if(hsn[rs2[t+j]]>j+b+2) hsn[rs2[t+j]]=j+b+2;
640 //if(rt1[t+j]) if(hsn[rt1[t+j]]>j+b+2) hsn[rt1[t+j]]=j+b+2;
641 //if(rt2[t+j]) if(hsn[rt2[t+j]]>j+b+2) hsn[rt2[t+j]]=j+b+2;
644 // TODO: preferred register based on backward branch
646 // Delay slot should preferably not overwrite branch conditions or cycle count
647 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
648 if(rs1[i-1]) if(hsn[rs1[i-1]]>1) hsn[rs1[i-1]]=1;
649 if(rs2[i-1]) if(hsn[rs2[i-1]]>1) hsn[rs2[i-1]]=1;
655 // Coprocessor load/store needs FTEMP, even if not declared
656 if(itype[i]==C1LS||itype[i]==C2LS) {
659 // Load L/R also uses FTEMP as a temporary register
660 if(itype[i]==LOADLR) {
663 // Also SWL/SWR/SDL/SDR
664 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) {
667 // Don't remove the miniht registers
668 if(itype[i]==UJUMP||itype[i]==RJUMP)
675 // We only want to allocate registers if we're going to use them again soon
676 int needed_again(int r, int i)
682 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000))
684 if(ba[i-1]<start || ba[i-1]>start+slen*4-4)
685 return 0; // Don't need any registers if exiting the block
693 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
695 // Don't go past an unconditonal jump
699 if(itype[i+j]==SYSCALL||itype[i+j]==HLECALL||itype[i+j]==INTCALL||((source[i+j]&0xfc00003f)==0x0d))
706 if(rs1[i+j]==r) rn=j;
707 if(rs2[i+j]==r) rn=j;
708 if((unneeded_reg[i+j]>>r)&1) rn=10;
709 if(i+j>=0&&(itype[i+j]==UJUMP||itype[i+j]==CJUMP||itype[i+j]==SJUMP||itype[i+j]==FJUMP))
717 if(ba[i+b]>=start && ba[i+b]<(start+slen*4))
719 // Follow first branch
721 int t=(ba[i+b]-start)>>2;
722 j=7-b;if(t+j>=slen) j=slen-t-1;
725 if(!((unneeded_reg[t+j]>>r)&1)) {
726 if(rs1[t+j]==r) if(rn>j+b+2) rn=j+b+2;
727 if(rs2[t+j]==r) if(rn>j+b+2) rn=j+b+2;
738 // Try to match register allocations at the end of a loop with those
740 int loop_reg(int i, int r, int hr)
749 if(itype[i+j]==UJUMP||itype[i+j]==RJUMP||(source[i+j]>>16)==0x1000)
751 // Don't go past an unconditonal jump
758 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)
763 if(r<64&&((unneeded_reg[i+k]>>r)&1)) return hr;
764 if(r>64&&((unneeded_reg_upper[i+k]>>r)&1)) return hr;
765 if(i+k>=0&&(itype[i+k]==UJUMP||itype[i+k]==CJUMP||itype[i+k]==SJUMP||itype[i+k]==FJUMP))
767 if(ba[i+k]>=start && ba[i+k]<(start+i*4))
769 int t=(ba[i+k]-start)>>2;
770 int reg=get_reg(regs[t].regmap_entry,r);
771 if(reg>=0) return reg;
772 //reg=get_reg(regs[t+1].regmap_entry,r);
773 //if(reg>=0) return reg;
781 // Allocate every register, preserving source/target regs
782 void alloc_all(struct regstat *cur,int i)
786 for(hr=0;hr<HOST_REGS;hr++) {
787 if(hr!=EXCLUDE_REG) {
788 if(((cur->regmap[hr]&63)!=rs1[i])&&((cur->regmap[hr]&63)!=rs2[i])&&
789 ((cur->regmap[hr]&63)!=rt1[i])&&((cur->regmap[hr]&63)!=rt2[i]))
792 cur->dirty&=~(1<<hr);
795 if((cur->regmap[hr]&63)==0)
798 cur->dirty&=~(1<<hr);
805 #include "assem_x86.c"
808 #include "assem_x64.c"
811 #include "assem_arm.c"
814 // Add virtual address mapping to linked list
815 void ll_add(struct ll_entry **head,int vaddr,void *addr)
817 struct ll_entry *new_entry;
818 new_entry=malloc(sizeof(struct ll_entry));
819 assert(new_entry!=NULL);
820 new_entry->vaddr=vaddr;
821 new_entry->reg_sv_flags=0;
822 new_entry->addr=addr;
823 new_entry->next=*head;
827 void ll_add_flags(struct ll_entry **head,int vaddr,u_int reg_sv_flags,void *addr)
829 ll_add(head,vaddr,addr);
830 (*head)->reg_sv_flags=reg_sv_flags;
833 // Check if an address is already compiled
834 // but don't return addresses which are about to expire from the cache
835 void *check_addr(u_int vaddr)
837 struct ht_entry *ht_bin = hash_table_get(vaddr);
839 for (i = 0; i < ARRAY_SIZE(ht_bin->vaddr); i++) {
840 if (ht_bin->vaddr[i] == vaddr)
841 if (doesnt_expire_soon((u_char *)ht_bin->tcaddr[i] - MAX_OUTPUT_BLOCK_SIZE))
842 if (isclean(ht_bin->tcaddr[i]))
843 return ht_bin->tcaddr[i];
845 u_int page=get_page(vaddr);
846 struct ll_entry *head;
848 while (head != NULL) {
849 if (head->vaddr == vaddr) {
850 if (doesnt_expire_soon(head->addr)) {
851 // Update existing entry with current address
852 if (ht_bin->vaddr[0] == vaddr) {
853 ht_bin->tcaddr[0] = head->addr;
856 if (ht_bin->vaddr[1] == vaddr) {
857 ht_bin->tcaddr[1] = head->addr;
860 // Insert into hash table with low priority.
861 // Don't evict existing entries, as they are probably
862 // addresses that are being accessed frequently.
863 if (ht_bin->vaddr[0] == -1) {
864 ht_bin->vaddr[0] = vaddr;
865 ht_bin->tcaddr[0] = head->addr;
867 else if (ht_bin->vaddr[1] == -1) {
868 ht_bin->vaddr[1] = vaddr;
869 ht_bin->tcaddr[1] = head->addr;
879 void remove_hash(int vaddr)
881 //printf("remove hash: %x\n",vaddr);
882 struct ht_entry *ht_bin = hash_table_get(vaddr);
883 if (ht_bin->vaddr[1] == vaddr) {
884 ht_bin->vaddr[1] = -1;
885 ht_bin->tcaddr[1] = NULL;
887 if (ht_bin->vaddr[0] == vaddr) {
888 ht_bin->vaddr[0] = ht_bin->vaddr[1];
889 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
890 ht_bin->vaddr[1] = -1;
891 ht_bin->tcaddr[1] = NULL;
895 void ll_remove_matching_addrs(struct ll_entry **head,int addr,int shift)
897 struct ll_entry *next;
899 if(((u_int)((*head)->addr)>>shift)==(addr>>shift) ||
900 ((u_int)((*head)->addr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift))
902 inv_debug("EXP: Remove pointer to %x (%x)\n",(int)(*head)->addr,(*head)->vaddr);
903 remove_hash((*head)->vaddr);
910 head=&((*head)->next);
915 // Remove all entries from linked list
916 void ll_clear(struct ll_entry **head)
918 struct ll_entry *cur;
919 struct ll_entry *next;
930 // Dereference the pointers and remove if it matches
931 static void ll_kill_pointers(struct ll_entry *head,int addr,int shift)
934 int ptr=get_pointer(head->addr);
935 inv_debug("EXP: Lookup pointer to %x at %x (%x)\n",(int)ptr,(int)head->addr,head->vaddr);
936 if(((ptr>>shift)==(addr>>shift)) ||
937 (((ptr-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(addr>>shift)))
939 inv_debug("EXP: Kill pointer at %x (%x)\n",(int)head->addr,head->vaddr);
940 void *host_addr=find_extjump_insn(head->addr);
942 mark_clear_cache(host_addr);
944 set_jump_target(host_addr, head->addr);
950 // This is called when we write to a compiled block (see do_invstub)
951 void invalidate_page(u_int page)
953 struct ll_entry *head;
954 struct ll_entry *next;
958 inv_debug("INVALIDATE: %x\n",head->vaddr);
959 remove_hash(head->vaddr);
967 inv_debug("INVALIDATE: kill pointer to %x (%x)\n",head->vaddr,(int)head->addr);
968 void *host_addr=find_extjump_insn(head->addr);
970 mark_clear_cache(host_addr);
972 set_jump_target(host_addr, head->addr);
979 static void invalidate_block_range(u_int block, u_int first, u_int last)
981 u_int page=get_page(block<<12);
982 //printf("first=%d last=%d\n",first,last);
983 invalidate_page(page);
984 assert(first+5>page); // NB: this assumes MAXBLOCK<=4096 (4 pages)
986 // Invalidate the adjacent pages if a block crosses a 4K boundary
988 invalidate_page(first);
991 for(first=page+1;first<last;first++) {
992 invalidate_page(first);
999 invalid_code[block]=1;
1002 memset(mini_ht,-1,sizeof(mini_ht));
1006 void invalidate_block(u_int block)
1008 u_int page=get_page(block<<12);
1009 u_int vpage=get_vpage(block<<12);
1010 inv_debug("INVALIDATE: %x (%d)\n",block<<12,page);
1011 //inv_debug("invalid_code[block]=%d\n",invalid_code[block]);
1014 struct ll_entry *head;
1015 head=jump_dirty[vpage];
1016 //printf("page=%d vpage=%d\n",page,vpage);
1019 if(vpage>2047||(head->vaddr>>12)==block) { // Ignore vaddr hash collision
1020 get_bounds((int)head->addr,&start,&end);
1021 //printf("start: %x end: %x\n",start,end);
1022 if(page<2048&&start>=(u_int)rdram&&end<(u_int)rdram+RAM_SIZE) {
1023 if(((start-(u_int)rdram)>>12)<=page&&((end-1-(u_int)rdram)>>12)>=page) {
1024 if((((start-(u_int)rdram)>>12)&2047)<first) first=((start-(u_int)rdram)>>12)&2047;
1025 if((((end-1-(u_int)rdram)>>12)&2047)>last) last=((end-1-(u_int)rdram)>>12)&2047;
1031 invalidate_block_range(block,first,last);
1034 void invalidate_addr(u_int addr)
1037 // this check is done by the caller
1038 //if (inv_code_start<=addr&&addr<=inv_code_end) { rhits++; return; }
1039 u_int page=get_vpage(addr);
1040 if(page<2048) { // RAM
1041 struct ll_entry *head;
1042 u_int addr_min=~0, addr_max=0;
1043 u_int mask=RAM_SIZE-1;
1044 u_int addr_main=0x80000000|(addr&mask);
1046 inv_code_start=addr_main&~0xfff;
1047 inv_code_end=addr_main|0xfff;
1050 // must check previous page too because of spans..
1052 inv_code_start-=0x1000;
1054 for(;pg1<=page;pg1++) {
1055 for(head=jump_dirty[pg1];head!=NULL;head=head->next) {
1057 get_bounds((int)head->addr,&start,&end);
1062 if(start<=addr_main&&addr_main<end) {
1063 if(start<addr_min) addr_min=start;
1064 if(end>addr_max) addr_max=end;
1066 else if(addr_main<start) {
1067 if(start<inv_code_end)
1068 inv_code_end=start-1;
1071 if(end>inv_code_start)
1077 inv_debug("INV ADDR: %08x hit %08x-%08x\n", addr, addr_min, addr_max);
1078 inv_code_start=inv_code_end=~0;
1079 invalidate_block_range(addr>>12,(addr_min&mask)>>12,(addr_max&mask)>>12);
1083 inv_code_start=(addr&~mask)|(inv_code_start&mask);
1084 inv_code_end=(addr&~mask)|(inv_code_end&mask);
1085 inv_debug("INV ADDR: %08x miss, inv %08x-%08x, sk %d\n", addr, inv_code_start, inv_code_end, 0);
1089 invalidate_block(addr>>12);
1092 // This is called when loading a save state.
1093 // Anything could have changed, so invalidate everything.
1094 void invalidate_all_pages()
1097 for(page=0;page<4096;page++)
1098 invalidate_page(page);
1099 for(page=0;page<1048576;page++)
1100 if(!invalid_code[page]) {
1101 restore_candidate[(page&2047)>>3]|=1<<(page&7);
1102 restore_candidate[((page&2047)>>3)+256]|=1<<(page&7);
1105 memset(mini_ht,-1,sizeof(mini_ht));
1109 // Add an entry to jump_out after making a link
1110 void add_link(u_int vaddr,void *src)
1112 u_int page=get_page(vaddr);
1113 inv_debug("add_link: %x -> %x (%d)\n",(int)src,vaddr,page);
1114 int *ptr=(int *)(src+4);
1115 assert((*ptr&0x0fff0000)==0x059f0000);
1117 ll_add(jump_out+page,vaddr,src);
1118 //int ptr=get_pointer(src);
1119 //inv_debug("add_link: Pointer is to %x\n",(int)ptr);
1122 // If a code block was found to be unmodified (bit was set in
1123 // restore_candidate) and it remains unmodified (bit is clear
1124 // in invalid_code) then move the entries for that 4K page from
1125 // the dirty list to the clean list.
1126 void clean_blocks(u_int page)
1128 struct ll_entry *head;
1129 inv_debug("INV: clean_blocks page=%d\n",page);
1130 head=jump_dirty[page];
1132 if(!invalid_code[head->vaddr>>12]) {
1133 // Don't restore blocks which are about to expire from the cache
1134 if (doesnt_expire_soon(head->addr)) {
1136 if(verify_dirty(head->addr)) {
1137 //printf("Possibly Restore %x (%x)\n",head->vaddr, (int)head->addr);
1140 get_bounds((int)head->addr,&start,&end);
1141 if(start-(u_int)rdram<RAM_SIZE) {
1142 for(i=(start-(u_int)rdram+0x80000000)>>12;i<=(end-1-(u_int)rdram+0x80000000)>>12;i++) {
1143 inv|=invalid_code[i];
1146 else if((signed int)head->vaddr>=(signed int)0x80000000+RAM_SIZE) {
1150 void *clean_addr = get_clean_addr(head->addr);
1151 if (doesnt_expire_soon(clean_addr)) {
1153 inv_debug("INV: Restored %x (%x/%x)\n",head->vaddr, (int)head->addr, (int)clean_addr);
1154 //printf("page=%x, addr=%x\n",page,head->vaddr);
1155 //assert(head->vaddr>>12==(page|0x80000));
1156 ll_add_flags(jump_in+ppage,head->vaddr,head->reg_sv_flags,clean_addr);
1157 struct ht_entry *ht_bin = hash_table_get(head->vaddr);
1158 if (ht_bin->vaddr[0] == head->vaddr)
1159 ht_bin->tcaddr[0] = clean_addr; // Replace existing entry
1160 if (ht_bin->vaddr[1] == head->vaddr)
1161 ht_bin->tcaddr[1] = clean_addr; // Replace existing entry
1172 void mov_alloc(struct regstat *current,int i)
1174 // Note: Don't need to actually alloc the source registers
1175 if((~current->is32>>rs1[i])&1) {
1176 //alloc_reg64(current,i,rs1[i]);
1177 alloc_reg64(current,i,rt1[i]);
1178 current->is32&=~(1LL<<rt1[i]);
1180 //alloc_reg(current,i,rs1[i]);
1181 alloc_reg(current,i,rt1[i]);
1182 current->is32|=(1LL<<rt1[i]);
1184 clear_const(current,rs1[i]);
1185 clear_const(current,rt1[i]);
1186 dirty_reg(current,rt1[i]);
1189 void shiftimm_alloc(struct regstat *current,int i)
1191 if(opcode2[i]<=0x3) // SLL/SRL/SRA
1194 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1196 alloc_reg(current,i,rt1[i]);
1197 current->is32|=1LL<<rt1[i];
1198 dirty_reg(current,rt1[i]);
1199 if(is_const(current,rs1[i])) {
1200 int v=get_const(current,rs1[i]);
1201 if(opcode2[i]==0x00) set_const(current,rt1[i],v<<imm[i]);
1202 if(opcode2[i]==0x02) set_const(current,rt1[i],(u_int)v>>imm[i]);
1203 if(opcode2[i]==0x03) set_const(current,rt1[i],v>>imm[i]);
1205 else clear_const(current,rt1[i]);
1210 clear_const(current,rs1[i]);
1211 clear_const(current,rt1[i]);
1214 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
1217 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1218 alloc_reg64(current,i,rt1[i]);
1219 current->is32&=~(1LL<<rt1[i]);
1220 dirty_reg(current,rt1[i]);
1223 if(opcode2[i]==0x3c) // DSLL32
1226 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1227 alloc_reg64(current,i,rt1[i]);
1228 current->is32&=~(1LL<<rt1[i]);
1229 dirty_reg(current,rt1[i]);
1232 if(opcode2[i]==0x3e) // DSRL32
1235 alloc_reg64(current,i,rs1[i]);
1237 alloc_reg64(current,i,rt1[i]);
1238 current->is32&=~(1LL<<rt1[i]);
1240 alloc_reg(current,i,rt1[i]);
1241 current->is32|=1LL<<rt1[i];
1243 dirty_reg(current,rt1[i]);
1246 if(opcode2[i]==0x3f) // DSRA32
1249 alloc_reg64(current,i,rs1[i]);
1250 alloc_reg(current,i,rt1[i]);
1251 current->is32|=1LL<<rt1[i];
1252 dirty_reg(current,rt1[i]);
1257 void shift_alloc(struct regstat *current,int i)
1260 if(opcode2[i]<=0x07) // SLLV/SRLV/SRAV
1262 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1263 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1264 alloc_reg(current,i,rt1[i]);
1265 if(rt1[i]==rs2[i]) {
1266 alloc_reg_temp(current,i,-1);
1267 minimum_free_regs[i]=1;
1269 current->is32|=1LL<<rt1[i];
1270 } else { // DSLLV/DSRLV/DSRAV
1271 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1272 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1273 alloc_reg64(current,i,rt1[i]);
1274 current->is32&=~(1LL<<rt1[i]);
1275 if(opcode2[i]==0x16||opcode2[i]==0x17) // DSRLV and DSRAV need a temporary register
1277 alloc_reg_temp(current,i,-1);
1278 minimum_free_regs[i]=1;
1281 clear_const(current,rs1[i]);
1282 clear_const(current,rs2[i]);
1283 clear_const(current,rt1[i]);
1284 dirty_reg(current,rt1[i]);
1288 void alu_alloc(struct regstat *current,int i)
1290 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1292 if(rs1[i]&&rs2[i]) {
1293 alloc_reg(current,i,rs1[i]);
1294 alloc_reg(current,i,rs2[i]);
1297 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1298 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1300 alloc_reg(current,i,rt1[i]);
1302 current->is32|=1LL<<rt1[i];
1304 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
1306 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1308 alloc_reg64(current,i,rs1[i]);
1309 alloc_reg64(current,i,rs2[i]);
1310 alloc_reg(current,i,rt1[i]);
1312 alloc_reg(current,i,rs1[i]);
1313 alloc_reg(current,i,rs2[i]);
1314 alloc_reg(current,i,rt1[i]);
1317 current->is32|=1LL<<rt1[i];
1319 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
1321 if(rs1[i]&&rs2[i]) {
1322 alloc_reg(current,i,rs1[i]);
1323 alloc_reg(current,i,rs2[i]);
1327 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1328 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg(current,i,rs2[i]);
1330 alloc_reg(current,i,rt1[i]);
1331 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1333 if(!((current->uu>>rt1[i])&1)) {
1334 alloc_reg64(current,i,rt1[i]);
1336 if(get_reg(current->regmap,rt1[i]|64)>=0) {
1337 if(rs1[i]&&rs2[i]) {
1338 alloc_reg64(current,i,rs1[i]);
1339 alloc_reg64(current,i,rs2[i]);
1343 // Is is really worth it to keep 64-bit values in registers?
1345 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1346 if(rs2[i]&&needed_again(rs2[i],i)) alloc_reg64(current,i,rs2[i]);
1350 current->is32&=~(1LL<<rt1[i]);
1352 current->is32|=1LL<<rt1[i];
1356 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1358 if(rs1[i]&&rs2[i]) {
1359 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1360 alloc_reg64(current,i,rs1[i]);
1361 alloc_reg64(current,i,rs2[i]);
1362 alloc_reg64(current,i,rt1[i]);
1364 alloc_reg(current,i,rs1[i]);
1365 alloc_reg(current,i,rs2[i]);
1366 alloc_reg(current,i,rt1[i]);
1370 alloc_reg(current,i,rt1[i]);
1371 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1372 // DADD used as move, or zeroing
1373 // If we have a 64-bit source, then make the target 64 bits too
1374 if(rs1[i]&&!((current->is32>>rs1[i])&1)) {
1375 if(get_reg(current->regmap,rs1[i])>=0) alloc_reg64(current,i,rs1[i]);
1376 alloc_reg64(current,i,rt1[i]);
1377 } else if(rs2[i]&&!((current->is32>>rs2[i])&1)) {
1378 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1379 alloc_reg64(current,i,rt1[i]);
1381 if(opcode2[i]>=0x2e&&rs2[i]) {
1382 // DSUB used as negation - 64-bit result
1383 // If we have a 32-bit register, extend it to 64 bits
1384 if(get_reg(current->regmap,rs2[i])>=0) alloc_reg64(current,i,rs2[i]);
1385 alloc_reg64(current,i,rt1[i]);
1389 if(rs1[i]&&rs2[i]) {
1390 current->is32&=~(1LL<<rt1[i]);
1392 current->is32&=~(1LL<<rt1[i]);
1393 if((current->is32>>rs1[i])&1)
1394 current->is32|=1LL<<rt1[i];
1396 current->is32&=~(1LL<<rt1[i]);
1397 if((current->is32>>rs2[i])&1)
1398 current->is32|=1LL<<rt1[i];
1400 current->is32|=1LL<<rt1[i];
1404 clear_const(current,rs1[i]);
1405 clear_const(current,rs2[i]);
1406 clear_const(current,rt1[i]);
1407 dirty_reg(current,rt1[i]);
1410 void imm16_alloc(struct regstat *current,int i)
1412 if(rs1[i]&&needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1414 if(rt1[i]) alloc_reg(current,i,rt1[i]);
1415 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
1416 current->is32&=~(1LL<<rt1[i]);
1417 if(!((current->uu>>rt1[i])&1)||get_reg(current->regmap,rt1[i]|64)>=0) {
1418 // TODO: Could preserve the 32-bit flag if the immediate is zero
1419 alloc_reg64(current,i,rt1[i]);
1420 alloc_reg64(current,i,rs1[i]);
1422 clear_const(current,rs1[i]);
1423 clear_const(current,rt1[i]);
1425 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
1426 if((~current->is32>>rs1[i])&1) alloc_reg64(current,i,rs1[i]);
1427 current->is32|=1LL<<rt1[i];
1428 clear_const(current,rs1[i]);
1429 clear_const(current,rt1[i]);
1431 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
1432 if(((~current->is32>>rs1[i])&1)&&opcode[i]>0x0c) {
1433 if(rs1[i]!=rt1[i]) {
1434 if(needed_again(rs1[i],i)) alloc_reg64(current,i,rs1[i]);
1435 alloc_reg64(current,i,rt1[i]);
1436 current->is32&=~(1LL<<rt1[i]);
1439 else current->is32|=1LL<<rt1[i]; // ANDI clears upper bits
1440 if(is_const(current,rs1[i])) {
1441 int v=get_const(current,rs1[i]);
1442 if(opcode[i]==0x0c) set_const(current,rt1[i],v&imm[i]);
1443 if(opcode[i]==0x0d) set_const(current,rt1[i],v|imm[i]);
1444 if(opcode[i]==0x0e) set_const(current,rt1[i],v^imm[i]);
1446 else clear_const(current,rt1[i]);
1448 else if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
1449 if(is_const(current,rs1[i])) {
1450 int v=get_const(current,rs1[i]);
1451 set_const(current,rt1[i],v+imm[i]);
1453 else clear_const(current,rt1[i]);
1454 current->is32|=1LL<<rt1[i];
1457 set_const(current,rt1[i],((long long)((short)imm[i]))<<16); // LUI
1458 current->is32|=1LL<<rt1[i];
1460 dirty_reg(current,rt1[i]);
1463 void load_alloc(struct regstat *current,int i)
1465 clear_const(current,rt1[i]);
1466 //if(rs1[i]!=rt1[i]&&needed_again(rs1[i],i)) clear_const(current,rs1[i]); // Does this help or hurt?
1467 if(!rs1[i]) current->u&=~1LL; // Allow allocating r0 if it's the source register
1468 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1469 if(rt1[i]&&!((current->u>>rt1[i])&1)) {
1470 alloc_reg(current,i,rt1[i]);
1471 assert(get_reg(current->regmap,rt1[i])>=0);
1472 if(opcode[i]==0x27||opcode[i]==0x37) // LWU/LD
1474 current->is32&=~(1LL<<rt1[i]);
1475 alloc_reg64(current,i,rt1[i]);
1477 else if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1479 current->is32&=~(1LL<<rt1[i]);
1480 alloc_reg64(current,i,rt1[i]);
1481 alloc_all(current,i);
1482 alloc_reg64(current,i,FTEMP);
1483 minimum_free_regs[i]=HOST_REGS;
1485 else current->is32|=1LL<<rt1[i];
1486 dirty_reg(current,rt1[i]);
1487 // LWL/LWR need a temporary register for the old value
1488 if(opcode[i]==0x22||opcode[i]==0x26)
1490 alloc_reg(current,i,FTEMP);
1491 alloc_reg_temp(current,i,-1);
1492 minimum_free_regs[i]=1;
1497 // Load to r0 or unneeded register (dummy load)
1498 // but we still need a register to calculate the address
1499 if(opcode[i]==0x22||opcode[i]==0x26)
1501 alloc_reg(current,i,FTEMP); // LWL/LWR need another temporary
1503 alloc_reg_temp(current,i,-1);
1504 minimum_free_regs[i]=1;
1505 if(opcode[i]==0x1A||opcode[i]==0x1B) // LDL/LDR
1507 alloc_all(current,i);
1508 alloc_reg64(current,i,FTEMP);
1509 minimum_free_regs[i]=HOST_REGS;
1514 void store_alloc(struct regstat *current,int i)
1516 clear_const(current,rs2[i]);
1517 if(!(rs2[i])) current->u&=~1LL; // Allow allocating r0 if necessary
1518 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1519 alloc_reg(current,i,rs2[i]);
1520 if(opcode[i]==0x2c||opcode[i]==0x2d||opcode[i]==0x3f) { // 64-bit SDL/SDR/SD
1521 alloc_reg64(current,i,rs2[i]);
1522 if(rs2[i]) alloc_reg(current,i,FTEMP);
1524 #if defined(HOST_IMM8)
1525 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1526 else alloc_reg(current,i,INVCP);
1528 if(opcode[i]==0x2a||opcode[i]==0x2e||opcode[i]==0x2c||opcode[i]==0x2d) { // SWL/SWL/SDL/SDR
1529 alloc_reg(current,i,FTEMP);
1531 // We need a temporary register for address generation
1532 alloc_reg_temp(current,i,-1);
1533 minimum_free_regs[i]=1;
1536 void c1ls_alloc(struct regstat *current,int i)
1538 //clear_const(current,rs1[i]); // FIXME
1539 clear_const(current,rt1[i]);
1540 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1541 alloc_reg(current,i,CSREG); // Status
1542 alloc_reg(current,i,FTEMP);
1543 if(opcode[i]==0x35||opcode[i]==0x3d) { // 64-bit LDC1/SDC1
1544 alloc_reg64(current,i,FTEMP);
1546 #if defined(HOST_IMM8)
1547 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1548 else if((opcode[i]&0x3b)==0x39) // SWC1/SDC1
1549 alloc_reg(current,i,INVCP);
1551 // We need a temporary register for address generation
1552 alloc_reg_temp(current,i,-1);
1555 void c2ls_alloc(struct regstat *current,int i)
1557 clear_const(current,rt1[i]);
1558 if(needed_again(rs1[i],i)) alloc_reg(current,i,rs1[i]);
1559 alloc_reg(current,i,FTEMP);
1560 #if defined(HOST_IMM8)
1561 // On CPUs without 32-bit immediates we need a pointer to invalid_code
1562 if((opcode[i]&0x3b)==0x3a) // SWC2/SDC2
1563 alloc_reg(current,i,INVCP);
1565 // We need a temporary register for address generation
1566 alloc_reg_temp(current,i,-1);
1567 minimum_free_regs[i]=1;
1570 #ifndef multdiv_alloc
1571 void multdiv_alloc(struct regstat *current,int i)
1578 // case 0x1D: DMULTU
1581 clear_const(current,rs1[i]);
1582 clear_const(current,rs2[i]);
1585 if((opcode2[i]&4)==0) // 32-bit
1587 current->u&=~(1LL<<HIREG);
1588 current->u&=~(1LL<<LOREG);
1589 alloc_reg(current,i,HIREG);
1590 alloc_reg(current,i,LOREG);
1591 alloc_reg(current,i,rs1[i]);
1592 alloc_reg(current,i,rs2[i]);
1593 current->is32|=1LL<<HIREG;
1594 current->is32|=1LL<<LOREG;
1595 dirty_reg(current,HIREG);
1596 dirty_reg(current,LOREG);
1600 current->u&=~(1LL<<HIREG);
1601 current->u&=~(1LL<<LOREG);
1602 current->uu&=~(1LL<<HIREG);
1603 current->uu&=~(1LL<<LOREG);
1604 alloc_reg64(current,i,HIREG);
1605 //if(HOST_REGS>10) alloc_reg64(current,i,LOREG);
1606 alloc_reg64(current,i,rs1[i]);
1607 alloc_reg64(current,i,rs2[i]);
1608 alloc_all(current,i);
1609 current->is32&=~(1LL<<HIREG);
1610 current->is32&=~(1LL<<LOREG);
1611 dirty_reg(current,HIREG);
1612 dirty_reg(current,LOREG);
1613 minimum_free_regs[i]=HOST_REGS;
1618 // Multiply by zero is zero.
1619 // MIPS does not have a divide by zero exception.
1620 // The result is undefined, we return zero.
1621 alloc_reg(current,i,HIREG);
1622 alloc_reg(current,i,LOREG);
1623 current->is32|=1LL<<HIREG;
1624 current->is32|=1LL<<LOREG;
1625 dirty_reg(current,HIREG);
1626 dirty_reg(current,LOREG);
1631 void cop0_alloc(struct regstat *current,int i)
1633 if(opcode2[i]==0) // MFC0
1636 clear_const(current,rt1[i]);
1637 alloc_all(current,i);
1638 alloc_reg(current,i,rt1[i]);
1639 current->is32|=1LL<<rt1[i];
1640 dirty_reg(current,rt1[i]);
1643 else if(opcode2[i]==4) // MTC0
1646 clear_const(current,rs1[i]);
1647 alloc_reg(current,i,rs1[i]);
1648 alloc_all(current,i);
1651 alloc_all(current,i); // FIXME: Keep r0
1653 alloc_reg(current,i,0);
1658 // TLBR/TLBWI/TLBWR/TLBP/ERET
1659 assert(opcode2[i]==0x10);
1660 alloc_all(current,i);
1662 minimum_free_regs[i]=HOST_REGS;
1665 void cop1_alloc(struct regstat *current,int i)
1667 alloc_reg(current,i,CSREG); // Load status
1668 if(opcode2[i]<3) // MFC1/DMFC1/CFC1
1671 clear_const(current,rt1[i]);
1673 alloc_reg64(current,i,rt1[i]); // DMFC1
1674 current->is32&=~(1LL<<rt1[i]);
1676 alloc_reg(current,i,rt1[i]); // MFC1/CFC1
1677 current->is32|=1LL<<rt1[i];
1679 dirty_reg(current,rt1[i]);
1681 alloc_reg_temp(current,i,-1);
1683 else if(opcode2[i]>3) // MTC1/DMTC1/CTC1
1686 clear_const(current,rs1[i]);
1688 alloc_reg64(current,i,rs1[i]); // DMTC1
1690 alloc_reg(current,i,rs1[i]); // MTC1/CTC1
1691 alloc_reg_temp(current,i,-1);
1695 alloc_reg(current,i,0);
1696 alloc_reg_temp(current,i,-1);
1699 minimum_free_regs[i]=1;
1701 void fconv_alloc(struct regstat *current,int i)
1703 alloc_reg(current,i,CSREG); // Load status
1704 alloc_reg_temp(current,i,-1);
1705 minimum_free_regs[i]=1;
1707 void float_alloc(struct regstat *current,int i)
1709 alloc_reg(current,i,CSREG); // Load status
1710 alloc_reg_temp(current,i,-1);
1711 minimum_free_regs[i]=1;
1713 void c2op_alloc(struct regstat *current,int i)
1715 alloc_reg_temp(current,i,-1);
1717 void fcomp_alloc(struct regstat *current,int i)
1719 alloc_reg(current,i,CSREG); // Load status
1720 alloc_reg(current,i,FSREG); // Load flags
1721 dirty_reg(current,FSREG); // Flag will be modified
1722 alloc_reg_temp(current,i,-1);
1723 minimum_free_regs[i]=1;
1726 void syscall_alloc(struct regstat *current,int i)
1728 alloc_cc(current,i);
1729 dirty_reg(current,CCREG);
1730 alloc_all(current,i);
1731 minimum_free_regs[i]=HOST_REGS;
1735 void delayslot_alloc(struct regstat *current,int i)
1746 assem_debug("jump in the delay slot. this shouldn't happen.\n");//exit(1);
1747 SysPrintf("Disabled speculative precompilation\n");
1751 imm16_alloc(current,i);
1755 load_alloc(current,i);
1759 store_alloc(current,i);
1762 alu_alloc(current,i);
1765 shift_alloc(current,i);
1768 multdiv_alloc(current,i);
1771 shiftimm_alloc(current,i);
1774 mov_alloc(current,i);
1777 cop0_alloc(current,i);
1781 cop1_alloc(current,i);
1784 c1ls_alloc(current,i);
1787 c2ls_alloc(current,i);
1790 fconv_alloc(current,i);
1793 float_alloc(current,i);
1796 fcomp_alloc(current,i);
1799 c2op_alloc(current,i);
1804 // Special case where a branch and delay slot span two pages in virtual memory
1805 static void pagespan_alloc(struct regstat *current,int i)
1808 current->wasconst=0;
1810 minimum_free_regs[i]=HOST_REGS;
1811 alloc_all(current,i);
1812 alloc_cc(current,i);
1813 dirty_reg(current,CCREG);
1814 if(opcode[i]==3) // JAL
1816 alloc_reg(current,i,31);
1817 dirty_reg(current,31);
1819 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
1821 alloc_reg(current,i,rs1[i]);
1823 alloc_reg(current,i,rt1[i]);
1824 dirty_reg(current,rt1[i]);
1827 if((opcode[i]&0x2E)==4) // BEQ/BNE/BEQL/BNEL
1829 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1830 if(rs2[i]) alloc_reg(current,i,rs2[i]);
1831 if(!((current->is32>>rs1[i])&(current->is32>>rs2[i])&1))
1833 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1834 if(rs2[i]) alloc_reg64(current,i,rs2[i]);
1838 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ/BLEZL/BGTZL
1840 if(rs1[i]) alloc_reg(current,i,rs1[i]);
1841 if(!((current->is32>>rs1[i])&1))
1843 if(rs1[i]) alloc_reg64(current,i,rs1[i]);
1847 if(opcode[i]==0x11) // BC1
1849 alloc_reg(current,i,FSREG);
1850 alloc_reg(current,i,CSREG);
1855 static void add_stub(enum stub_type type, void *addr, void *retaddr,
1856 u_int a, uintptr_t b, uintptr_t c, u_int d, u_int e)
1858 assert(a < ARRAY_SIZE(stubs));
1859 stubs[stubcount].type = type;
1860 stubs[stubcount].addr = addr;
1861 stubs[stubcount].retaddr = retaddr;
1862 stubs[stubcount].a = a;
1863 stubs[stubcount].b = b;
1864 stubs[stubcount].c = c;
1865 stubs[stubcount].d = d;
1866 stubs[stubcount].e = e;
1870 static void add_stub_r(enum stub_type type, void *addr, void *retaddr,
1871 int i, int addr_reg, struct regstat *i_regs, int ccadj, u_int reglist)
1873 add_stub(type, addr, retaddr, i, addr_reg, (uintptr_t)i_regs, ccadj, reglist);
1876 // Write out a single register
1877 void wb_register(signed char r,signed char regmap[],uint64_t dirty,uint64_t is32)
1880 for(hr=0;hr<HOST_REGS;hr++) {
1881 if(hr!=EXCLUDE_REG) {
1882 if((regmap[hr]&63)==r) {
1885 emit_storereg(r,hr);
1887 emit_storereg(r|64,hr);
1899 for(i=0;i<2097152;i++) {
1900 unsigned int temp=sum;
1903 sum^=((u_int *)rdram)[i];
1912 sum^=((u_int *)reg)[i];
1920 printf("r%d:%8x%8x ",i,((int *)(reg+i))[1],((int *)(reg+i))[0]);
1924 void alu_assemble(int i,struct regstat *i_regs)
1926 if(opcode2[i]>=0x20&&opcode2[i]<=0x23) { // ADD/ADDU/SUB/SUBU
1928 signed char s1,s2,t;
1929 t=get_reg(i_regs->regmap,rt1[i]);
1931 s1=get_reg(i_regs->regmap,rs1[i]);
1932 s2=get_reg(i_regs->regmap,rs2[i]);
1933 if(rs1[i]&&rs2[i]) {
1936 if(opcode2[i]&2) emit_sub(s1,s2,t);
1937 else emit_add(s1,s2,t);
1940 if(s1>=0) emit_mov(s1,t);
1941 else emit_loadreg(rs1[i],t);
1945 if(opcode2[i]&2) emit_neg(s2,t);
1946 else emit_mov(s2,t);
1949 emit_loadreg(rs2[i],t);
1950 if(opcode2[i]&2) emit_neg(t,t);
1953 else emit_zeroreg(t);
1957 if(opcode2[i]>=0x2c&&opcode2[i]<=0x2f) { // DADD/DADDU/DSUB/DSUBU
1959 signed char s1l,s2l,s1h,s2h,tl,th;
1960 tl=get_reg(i_regs->regmap,rt1[i]);
1961 th=get_reg(i_regs->regmap,rt1[i]|64);
1963 s1l=get_reg(i_regs->regmap,rs1[i]);
1964 s2l=get_reg(i_regs->regmap,rs2[i]);
1965 s1h=get_reg(i_regs->regmap,rs1[i]|64);
1966 s2h=get_reg(i_regs->regmap,rs2[i]|64);
1967 if(rs1[i]&&rs2[i]) {
1970 if(opcode2[i]&2) emit_subs(s1l,s2l,tl);
1971 else emit_adds(s1l,s2l,tl);
1973 #ifdef INVERTED_CARRY
1974 if(opcode2[i]&2) {if(s1h!=th) emit_mov(s1h,th);emit_sbb(th,s2h);}
1976 if(opcode2[i]&2) emit_sbc(s1h,s2h,th);
1978 else emit_add(s1h,s2h,th);
1982 if(s1l>=0) emit_mov(s1l,tl);
1983 else emit_loadreg(rs1[i],tl);
1985 if(s1h>=0) emit_mov(s1h,th);
1986 else emit_loadreg(rs1[i]|64,th);
1991 if(opcode2[i]&2) emit_negs(s2l,tl);
1992 else emit_mov(s2l,tl);
1995 emit_loadreg(rs2[i],tl);
1996 if(opcode2[i]&2) emit_negs(tl,tl);
1999 #ifdef INVERTED_CARRY
2000 if(s2h>=0) emit_mov(s2h,th);
2001 else emit_loadreg(rs2[i]|64,th);
2003 emit_adcimm(-1,th); // x86 has inverted carry flag
2008 if(s2h>=0) emit_rscimm(s2h,0,th);
2010 emit_loadreg(rs2[i]|64,th);
2011 emit_rscimm(th,0,th);
2014 if(s2h>=0) emit_mov(s2h,th);
2015 else emit_loadreg(rs2[i]|64,th);
2022 if(th>=0) emit_zeroreg(th);
2027 if(opcode2[i]==0x2a||opcode2[i]==0x2b) { // SLT/SLTU
2029 signed char s1l,s1h,s2l,s2h,t;
2030 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1))
2032 t=get_reg(i_regs->regmap,rt1[i]);
2035 s1l=get_reg(i_regs->regmap,rs1[i]);
2036 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2037 s2l=get_reg(i_regs->regmap,rs2[i]);
2038 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2039 if(rs2[i]==0) // rx<r0
2042 if(opcode2[i]==0x2a) // SLT
2043 emit_shrimm(s1h,31,t);
2044 else // SLTU (unsigned can not be less than zero)
2047 else if(rs1[i]==0) // r0<rx
2050 if(opcode2[i]==0x2a) // SLT
2051 emit_set_gz64_32(s2h,s2l,t);
2052 else // SLTU (set if not zero)
2053 emit_set_nz64_32(s2h,s2l,t);
2056 assert(s1l>=0);assert(s1h>=0);
2057 assert(s2l>=0);assert(s2h>=0);
2058 if(opcode2[i]==0x2a) // SLT
2059 emit_set_if_less64_32(s1h,s1l,s2h,s2l,t);
2061 emit_set_if_carry64_32(s1h,s1l,s2h,s2l,t);
2065 t=get_reg(i_regs->regmap,rt1[i]);
2068 s1l=get_reg(i_regs->regmap,rs1[i]);
2069 s2l=get_reg(i_regs->regmap,rs2[i]);
2070 if(rs2[i]==0) // rx<r0
2073 if(opcode2[i]==0x2a) // SLT
2074 emit_shrimm(s1l,31,t);
2075 else // SLTU (unsigned can not be less than zero)
2078 else if(rs1[i]==0) // r0<rx
2081 if(opcode2[i]==0x2a) // SLT
2082 emit_set_gz32(s2l,t);
2083 else // SLTU (set if not zero)
2084 emit_set_nz32(s2l,t);
2087 assert(s1l>=0);assert(s2l>=0);
2088 if(opcode2[i]==0x2a) // SLT
2089 emit_set_if_less32(s1l,s2l,t);
2091 emit_set_if_carry32(s1l,s2l,t);
2097 if(opcode2[i]>=0x24&&opcode2[i]<=0x27) { // AND/OR/XOR/NOR
2099 signed char s1l,s1h,s2l,s2h,th,tl;
2100 tl=get_reg(i_regs->regmap,rt1[i]);
2101 th=get_reg(i_regs->regmap,rt1[i]|64);
2102 if(!((i_regs->was32>>rs1[i])&(i_regs->was32>>rs2[i])&1)&&th>=0)
2106 s1l=get_reg(i_regs->regmap,rs1[i]);
2107 s1h=get_reg(i_regs->regmap,rs1[i]|64);
2108 s2l=get_reg(i_regs->regmap,rs2[i]);
2109 s2h=get_reg(i_regs->regmap,rs2[i]|64);
2110 if(rs1[i]&&rs2[i]) {
2111 assert(s1l>=0);assert(s1h>=0);
2112 assert(s2l>=0);assert(s2h>=0);
2113 if(opcode2[i]==0x24) { // AND
2114 emit_and(s1l,s2l,tl);
2115 emit_and(s1h,s2h,th);
2117 if(opcode2[i]==0x25) { // OR
2118 emit_or(s1l,s2l,tl);
2119 emit_or(s1h,s2h,th);
2121 if(opcode2[i]==0x26) { // XOR
2122 emit_xor(s1l,s2l,tl);
2123 emit_xor(s1h,s2h,th);
2125 if(opcode2[i]==0x27) { // NOR
2126 emit_or(s1l,s2l,tl);
2127 emit_or(s1h,s2h,th);
2134 if(opcode2[i]==0x24) { // AND
2138 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2140 if(s1l>=0) emit_mov(s1l,tl);
2141 else emit_loadreg(rs1[i],tl);
2142 if(s1h>=0) emit_mov(s1h,th);
2143 else emit_loadreg(rs1[i]|64,th);
2147 if(s2l>=0) emit_mov(s2l,tl);
2148 else emit_loadreg(rs2[i],tl);
2149 if(s2h>=0) emit_mov(s2h,th);
2150 else emit_loadreg(rs2[i]|64,th);
2157 if(opcode2[i]==0x27) { // NOR
2159 if(s1l>=0) emit_not(s1l,tl);
2161 emit_loadreg(rs1[i],tl);
2164 if(s1h>=0) emit_not(s1h,th);
2166 emit_loadreg(rs1[i]|64,th);
2172 if(s2l>=0) emit_not(s2l,tl);
2174 emit_loadreg(rs2[i],tl);
2177 if(s2h>=0) emit_not(s2h,th);
2179 emit_loadreg(rs2[i]|64,th);
2195 s1l=get_reg(i_regs->regmap,rs1[i]);
2196 s2l=get_reg(i_regs->regmap,rs2[i]);
2197 if(rs1[i]&&rs2[i]) {
2200 if(opcode2[i]==0x24) { // AND
2201 emit_and(s1l,s2l,tl);
2203 if(opcode2[i]==0x25) { // OR
2204 emit_or(s1l,s2l,tl);
2206 if(opcode2[i]==0x26) { // XOR
2207 emit_xor(s1l,s2l,tl);
2209 if(opcode2[i]==0x27) { // NOR
2210 emit_or(s1l,s2l,tl);
2216 if(opcode2[i]==0x24) { // AND
2219 if(opcode2[i]==0x25||opcode2[i]==0x26) { // OR/XOR
2221 if(s1l>=0) emit_mov(s1l,tl);
2222 else emit_loadreg(rs1[i],tl); // CHECK: regmap_entry?
2226 if(s2l>=0) emit_mov(s2l,tl);
2227 else emit_loadreg(rs2[i],tl); // CHECK: regmap_entry?
2229 else emit_zeroreg(tl);
2231 if(opcode2[i]==0x27) { // NOR
2233 if(s1l>=0) emit_not(s1l,tl);
2235 emit_loadreg(rs1[i],tl);
2241 if(s2l>=0) emit_not(s2l,tl);
2243 emit_loadreg(rs2[i],tl);
2247 else emit_movimm(-1,tl);
2256 void imm16_assemble(int i,struct regstat *i_regs)
2258 if (opcode[i]==0x0f) { // LUI
2261 t=get_reg(i_regs->regmap,rt1[i]);
2264 if(!((i_regs->isconst>>t)&1))
2265 emit_movimm(imm[i]<<16,t);
2269 if(opcode[i]==0x08||opcode[i]==0x09) { // ADDI/ADDIU
2272 t=get_reg(i_regs->regmap,rt1[i]);
2273 s=get_reg(i_regs->regmap,rs1[i]);
2278 if(!((i_regs->isconst>>t)&1)) {
2280 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2281 emit_addimm(t,imm[i],t);
2283 if(!((i_regs->wasconst>>s)&1))
2284 emit_addimm(s,imm[i],t);
2286 emit_movimm(constmap[i][s]+imm[i],t);
2292 if(!((i_regs->isconst>>t)&1))
2293 emit_movimm(imm[i],t);
2298 if(opcode[i]==0x18||opcode[i]==0x19) { // DADDI/DADDIU
2300 signed char sh,sl,th,tl;
2301 th=get_reg(i_regs->regmap,rt1[i]|64);
2302 tl=get_reg(i_regs->regmap,rt1[i]);
2303 sh=get_reg(i_regs->regmap,rs1[i]|64);
2304 sl=get_reg(i_regs->regmap,rs1[i]);
2310 emit_addimm64_32(sh,sl,imm[i],th,tl);
2313 emit_addimm(sl,imm[i],tl);
2316 emit_movimm(imm[i],tl);
2317 if(th>=0) emit_movimm(((signed int)imm[i])>>31,th);
2322 else if(opcode[i]==0x0a||opcode[i]==0x0b) { // SLTI/SLTIU
2324 //assert(rs1[i]!=0); // r0 might be valid, but it's probably a bug
2325 signed char sh,sl,t;
2326 t=get_reg(i_regs->regmap,rt1[i]);
2327 sh=get_reg(i_regs->regmap,rs1[i]|64);
2328 sl=get_reg(i_regs->regmap,rs1[i]);
2332 if(sh<0) assert((i_regs->was32>>rs1[i])&1);
2333 if(sh<0||((i_regs->was32>>rs1[i])&1)) {
2334 if(opcode[i]==0x0a) { // SLTI
2336 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2337 emit_slti32(t,imm[i],t);
2339 emit_slti32(sl,imm[i],t);
2344 if(i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2345 emit_sltiu32(t,imm[i],t);
2347 emit_sltiu32(sl,imm[i],t);
2352 if(opcode[i]==0x0a) // SLTI
2353 emit_slti64_32(sh,sl,imm[i],t);
2355 emit_sltiu64_32(sh,sl,imm[i],t);
2358 // SLTI(U) with r0 is just stupid,
2359 // nonetheless examples can be found
2360 if(opcode[i]==0x0a) // SLTI
2361 if(0<imm[i]) emit_movimm(1,t);
2362 else emit_zeroreg(t);
2365 if(imm[i]) emit_movimm(1,t);
2366 else emit_zeroreg(t);
2372 else if(opcode[i]>=0x0c&&opcode[i]<=0x0e) { // ANDI/ORI/XORI
2374 signed char sh,sl,th,tl;
2375 th=get_reg(i_regs->regmap,rt1[i]|64);
2376 tl=get_reg(i_regs->regmap,rt1[i]);
2377 sh=get_reg(i_regs->regmap,rs1[i]|64);
2378 sl=get_reg(i_regs->regmap,rs1[i]);
2379 if(tl>=0 && !((i_regs->isconst>>tl)&1)) {
2380 if(opcode[i]==0x0c) //ANDI
2384 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2385 emit_andimm(tl,imm[i],tl);
2387 if(!((i_regs->wasconst>>sl)&1))
2388 emit_andimm(sl,imm[i],tl);
2390 emit_movimm(constmap[i][sl]&imm[i],tl);
2395 if(th>=0) emit_zeroreg(th);
2401 if(i_regs->regmap_entry[tl]!=rs1[i]) emit_loadreg(rs1[i],tl);
2405 emit_loadreg(rs1[i]|64,th);
2410 if(opcode[i]==0x0d) { // ORI
2412 emit_orimm(tl,imm[i],tl);
2414 if(!((i_regs->wasconst>>sl)&1))
2415 emit_orimm(sl,imm[i],tl);
2417 emit_movimm(constmap[i][sl]|imm[i],tl);
2420 if(opcode[i]==0x0e) { // XORI
2422 emit_xorimm(tl,imm[i],tl);
2424 if(!((i_regs->wasconst>>sl)&1))
2425 emit_xorimm(sl,imm[i],tl);
2427 emit_movimm(constmap[i][sl]^imm[i],tl);
2432 emit_movimm(imm[i],tl);
2433 if(th>=0) emit_zeroreg(th);
2441 void shiftimm_assemble(int i,struct regstat *i_regs)
2443 if(opcode2[i]<=0x3) // SLL/SRL/SRA
2447 t=get_reg(i_regs->regmap,rt1[i]);
2448 s=get_reg(i_regs->regmap,rs1[i]);
2450 if(t>=0&&!((i_regs->isconst>>t)&1)){
2457 if(s<0&&i_regs->regmap_entry[t]!=rs1[i]) emit_loadreg(rs1[i],t);
2459 if(opcode2[i]==0) // SLL
2461 emit_shlimm(s<0?t:s,imm[i],t);
2463 if(opcode2[i]==2) // SRL
2465 emit_shrimm(s<0?t:s,imm[i],t);
2467 if(opcode2[i]==3) // SRA
2469 emit_sarimm(s<0?t:s,imm[i],t);
2473 if(s>=0 && s!=t) emit_mov(s,t);
2477 //emit_storereg(rt1[i],t); //DEBUG
2480 if(opcode2[i]>=0x38&&opcode2[i]<=0x3b) // DSLL/DSRL/DSRA
2483 signed char sh,sl,th,tl;
2484 th=get_reg(i_regs->regmap,rt1[i]|64);
2485 tl=get_reg(i_regs->regmap,rt1[i]);
2486 sh=get_reg(i_regs->regmap,rs1[i]|64);
2487 sl=get_reg(i_regs->regmap,rs1[i]);
2492 if(th>=0) emit_zeroreg(th);
2499 if(opcode2[i]==0x38) // DSLL
2501 if(th>=0) emit_shldimm(sh,sl,imm[i],th);
2502 emit_shlimm(sl,imm[i],tl);
2504 if(opcode2[i]==0x3a) // DSRL
2506 emit_shrdimm(sl,sh,imm[i],tl);
2507 if(th>=0) emit_shrimm(sh,imm[i],th);
2509 if(opcode2[i]==0x3b) // DSRA
2511 emit_shrdimm(sl,sh,imm[i],tl);
2512 if(th>=0) emit_sarimm(sh,imm[i],th);
2516 if(sl!=tl) emit_mov(sl,tl);
2517 if(th>=0&&sh!=th) emit_mov(sh,th);
2523 if(opcode2[i]==0x3c) // DSLL32
2526 signed char sl,tl,th;
2527 tl=get_reg(i_regs->regmap,rt1[i]);
2528 th=get_reg(i_regs->regmap,rt1[i]|64);
2529 sl=get_reg(i_regs->regmap,rs1[i]);
2538 emit_shlimm(th,imm[i]&31,th);
2543 if(opcode2[i]==0x3e) // DSRL32
2546 signed char sh,tl,th;
2547 tl=get_reg(i_regs->regmap,rt1[i]);
2548 th=get_reg(i_regs->regmap,rt1[i]|64);
2549 sh=get_reg(i_regs->regmap,rs1[i]|64);
2553 if(th>=0) emit_zeroreg(th);
2556 emit_shrimm(tl,imm[i]&31,tl);
2561 if(opcode2[i]==0x3f) // DSRA32
2565 tl=get_reg(i_regs->regmap,rt1[i]);
2566 sh=get_reg(i_regs->regmap,rs1[i]|64);
2572 emit_sarimm(tl,imm[i]&31,tl);
2579 #ifndef shift_assemble
2580 void shift_assemble(int i,struct regstat *i_regs)
2582 printf("Need shift_assemble for this architecture.\n");
2587 void load_assemble(int i,struct regstat *i_regs)
2589 int s,th,tl,addr,map=-1;
2592 int memtarget=0,c=0;
2593 int fastload_reg_override=0;
2595 th=get_reg(i_regs->regmap,rt1[i]|64);
2596 tl=get_reg(i_regs->regmap,rt1[i]);
2597 s=get_reg(i_regs->regmap,rs1[i]);
2599 for(hr=0;hr<HOST_REGS;hr++) {
2600 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2602 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2604 c=(i_regs->wasconst>>s)&1;
2606 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2609 //printf("load_assemble: c=%d\n",c);
2610 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2611 // FIXME: Even if the load is a NOP, we should check for pagefaults...
2612 if((tl<0&&(!c||(((u_int)constmap[i][s]+offset)>>16)==0x1f80))
2614 // could be FIFO, must perform the read
2616 assem_debug("(forced read)\n");
2617 tl=get_reg(i_regs->regmap,-1);
2620 if(offset||s<0||c) addr=tl;
2622 //if(tl<0) tl=get_reg(i_regs->regmap,-1);
2624 //printf("load_assemble: c=%d\n",c);
2625 //if(c) printf("load_assemble: const=%x\n",(int)constmap[i][s]+offset);
2626 assert(tl>=0); // Even if the load is a NOP, we must check for pagefaults and I/O
2628 if(th>=0) reglist&=~(1<<th);
2631 map=get_reg(i_regs->regmap,ROREG);
2632 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
2635 // Strmnnrmn's speed hack
2636 if(rs1[i]!=29||start<0x80001000||start>=0x80000000+RAM_SIZE)
2639 jaddr=emit_fastpath_cmp_jump(i,addr,&fastload_reg_override);
2642 else if(ram_offset&&memtarget) {
2643 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2644 fastload_reg_override=HOST_TEMPREG;
2646 int dummy=(rt1[i]==0)||(tl!=get_reg(i_regs->regmap,rt1[i])); // ignore loads to r0 and unneeded reg
2647 if (opcode[i]==0x20) { // LB
2650 #ifdef HOST_IMM_ADDR32
2652 emit_movsbl_tlb((constmap[i][s]+offset)^3,map,tl);
2656 //emit_xorimm(addr,3,tl);
2657 //emit_movsbl_indexed((int)rdram-0x80000000,tl,tl);
2659 #ifdef BIG_ENDIAN_MIPS
2660 if(!c) emit_xorimm(addr,3,tl);
2661 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2665 if(fastload_reg_override) a=fastload_reg_override;
2667 emit_movsbl_indexed_tlb(x,a,map,tl);
2671 add_stub_r(LOADB_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2674 inline_readstub(LOADB_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2676 if (opcode[i]==0x21) { // LH
2679 #ifdef HOST_IMM_ADDR32
2681 emit_movswl_tlb((constmap[i][s]+offset)^2,map,tl);
2686 #ifdef BIG_ENDIAN_MIPS
2687 if(!c) emit_xorimm(addr,2,tl);
2688 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2692 if(fastload_reg_override) a=fastload_reg_override;
2694 //emit_movswl_indexed_tlb(x,tl,map,tl);
2697 emit_movswl_indexed(x,a,tl);
2699 #if 1 //def RAM_OFFSET
2700 emit_movswl_indexed(x,a,tl);
2702 emit_movswl_indexed((int)rdram-0x80000000+x,a,tl);
2708 add_stub_r(LOADH_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2711 inline_readstub(LOADH_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2713 if (opcode[i]==0x23) { // LW
2717 if(fastload_reg_override) a=fastload_reg_override;
2718 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2719 #ifdef HOST_IMM_ADDR32
2721 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2724 emit_readword_indexed_tlb(0,a,map,tl);
2727 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2730 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2732 if (opcode[i]==0x24) { // LBU
2735 #ifdef HOST_IMM_ADDR32
2737 emit_movzbl_tlb((constmap[i][s]+offset)^3,map,tl);
2741 //emit_xorimm(addr,3,tl);
2742 //emit_movzbl_indexed((int)rdram-0x80000000,tl,tl);
2744 #ifdef BIG_ENDIAN_MIPS
2745 if(!c) emit_xorimm(addr,3,tl);
2746 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2750 if(fastload_reg_override) a=fastload_reg_override;
2752 emit_movzbl_indexed_tlb(x,a,map,tl);
2756 add_stub_r(LOADBU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2759 inline_readstub(LOADBU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2761 if (opcode[i]==0x25) { // LHU
2764 #ifdef HOST_IMM_ADDR32
2766 emit_movzwl_tlb((constmap[i][s]+offset)^2,map,tl);
2771 #ifdef BIG_ENDIAN_MIPS
2772 if(!c) emit_xorimm(addr,2,tl);
2773 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2777 if(fastload_reg_override) a=fastload_reg_override;
2779 //emit_movzwl_indexed_tlb(x,tl,map,tl);
2782 emit_movzwl_indexed(x,a,tl);
2784 #if 1 //def RAM_OFFSET
2785 emit_movzwl_indexed(x,a,tl);
2787 emit_movzwl_indexed((int)rdram-0x80000000+x,a,tl);
2793 add_stub_r(LOADHU_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2796 inline_readstub(LOADHU_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2798 if (opcode[i]==0x27) { // LWU
2803 if(fastload_reg_override) a=fastload_reg_override;
2804 //emit_readword_indexed((int)rdram-0x80000000,addr,tl);
2805 #ifdef HOST_IMM_ADDR32
2807 emit_readword_tlb(constmap[i][s]+offset,map,tl);
2810 emit_readword_indexed_tlb(0,a,map,tl);
2813 add_stub_r(LOADW_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2816 inline_readstub(LOADW_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2820 if (opcode[i]==0x37) { // LD
2824 if(fastload_reg_override) a=fastload_reg_override;
2825 //if(th>=0) emit_readword_indexed((int)rdram-0x80000000,addr,th);
2826 //emit_readword_indexed((int)rdram-0x7FFFFFFC,addr,tl);
2827 #ifdef HOST_IMM_ADDR32
2829 emit_readdword_tlb(constmap[i][s]+offset,map,th,tl);
2832 emit_readdword_indexed_tlb(0,a,map,th,tl);
2835 add_stub_r(LOADD_STUB,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2838 inline_readstub(LOADD_STUB,i,constmap[i][s]+offset,i_regs->regmap,rt1[i],ccadj[i],reglist);
2843 #ifndef loadlr_assemble
2844 void loadlr_assemble(int i,struct regstat *i_regs)
2846 printf("Need loadlr_assemble for this architecture.\n");
2851 void store_assemble(int i,struct regstat *i_regs)
2857 enum stub_type type;
2858 int memtarget=0,c=0;
2859 int agr=AGEN1+(i&1);
2860 int faststore_reg_override=0;
2862 th=get_reg(i_regs->regmap,rs2[i]|64);
2863 tl=get_reg(i_regs->regmap,rs2[i]);
2864 s=get_reg(i_regs->regmap,rs1[i]);
2865 temp=get_reg(i_regs->regmap,agr);
2866 if(temp<0) temp=get_reg(i_regs->regmap,-1);
2869 c=(i_regs->wasconst>>s)&1;
2871 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
2876 for(hr=0;hr<HOST_REGS;hr++) {
2877 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
2879 if(i_regs->regmap[HOST_CCREG]==CCREG) reglist&=~(1<<HOST_CCREG);
2880 if(offset||s<0||c) addr=temp;
2883 jaddr=emit_fastpath_cmp_jump(i,addr,&faststore_reg_override);
2885 else if(ram_offset&&memtarget) {
2886 emit_addimm(addr,ram_offset,HOST_TEMPREG);
2887 faststore_reg_override=HOST_TEMPREG;
2890 if (opcode[i]==0x28) { // SB
2893 #ifdef BIG_ENDIAN_MIPS
2894 if(!c) emit_xorimm(addr,3,temp);
2895 else x=((constmap[i][s]+offset)^3)-(constmap[i][s]+offset);
2899 if(faststore_reg_override) a=faststore_reg_override;
2900 //emit_writebyte_indexed(tl,(int)rdram-0x80000000,temp);
2901 emit_writebyte_indexed_tlb(tl,x,a,map,a);
2905 if (opcode[i]==0x29) { // SH
2908 #ifdef BIG_ENDIAN_MIPS
2909 if(!c) emit_xorimm(addr,2,temp);
2910 else x=((constmap[i][s]+offset)^2)-(constmap[i][s]+offset);
2914 if(faststore_reg_override) a=faststore_reg_override;
2916 //emit_writehword_indexed_tlb(tl,x,temp,map,temp);
2919 emit_writehword_indexed(tl,x,a);
2921 //emit_writehword_indexed(tl,(int)rdram-0x80000000+x,a);
2922 emit_writehword_indexed(tl,x,a);
2926 if (opcode[i]==0x2B) { // SW
2929 if(faststore_reg_override) a=faststore_reg_override;
2930 //emit_writeword_indexed(tl,(int)rdram-0x80000000,addr);
2931 emit_writeword_indexed_tlb(tl,0,a,map,temp);
2935 if (opcode[i]==0x3F) { // SD
2938 if(faststore_reg_override) a=faststore_reg_override;
2941 //emit_writeword_indexed(th,(int)rdram-0x80000000,addr);
2942 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,addr);
2943 emit_writedword_indexed_tlb(th,tl,0,a,map,temp);
2946 //emit_writeword_indexed(tl,(int)rdram-0x80000000,temp);
2947 //emit_writeword_indexed(tl,(int)rdram-0x7FFFFFFC,temp);
2948 emit_writedword_indexed_tlb(tl,tl,0,a,map,temp);
2954 // PCSX store handlers don't check invcode again
2956 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2959 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
2961 #ifdef DESTRUCTIVE_SHIFT
2962 // The x86 shift operation is 'destructive'; it overwrites the
2963 // source register, so we need to make a copy first and use that.
2966 #if defined(HOST_IMM8)
2967 int ir=get_reg(i_regs->regmap,INVCP);
2969 emit_cmpmem_indexedsr12_reg(ir,addr,1);
2971 emit_cmpmem_indexedsr12_imm((int)invalid_code,addr,1);
2973 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
2974 emit_callne(invalidate_addr_reg[addr]);
2978 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),addr,0,0,0);
2982 u_int addr_val=constmap[i][s]+offset;
2984 add_stub_r(type,jaddr,out,i,addr,i_regs,ccadj[i],reglist);
2985 } else if(c&&!memtarget) {
2986 inline_writestub(type,i,addr_val,i_regs->regmap,rs2[i],ccadj[i],reglist);
2988 // basic current block modification detection..
2989 // not looking back as that should be in mips cache already
2990 if(c&&start+i*4<addr_val&&addr_val<start+slen*4) {
2991 SysPrintf("write to %08x hits block %08x, pc=%08x\n",addr_val,start,start+i*4);
2992 assert(i_regs->regmap==regs[i].regmap); // not delay slot
2993 if(i_regs->regmap==regs[i].regmap) {
2994 load_all_consts(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty,i);
2995 wb_dirtys(regs[i].regmap_entry,regs[i].was32,regs[i].wasdirty);
2996 emit_movimm(start+i*4+4,0);
2997 emit_writeword(0,(int)&pcaddr);
2998 emit_jmp(do_interrupt);
3003 void storelr_assemble(int i,struct regstat *i_regs)
3010 void *case1, *case2, *case3;
3011 void *done0, *done1, *done2;
3012 int memtarget=0,c=0;
3013 int agr=AGEN1+(i&1);
3015 th=get_reg(i_regs->regmap,rs2[i]|64);
3016 tl=get_reg(i_regs->regmap,rs2[i]);
3017 s=get_reg(i_regs->regmap,rs1[i]);
3018 temp=get_reg(i_regs->regmap,agr);
3019 if(temp<0) temp=get_reg(i_regs->regmap,-1);
3022 c=(i_regs->isconst>>s)&1;
3024 memtarget=((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE;
3028 for(hr=0;hr<HOST_REGS;hr++) {
3029 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3033 emit_cmpimm(s<0||offset?temp:s,RAM_SIZE);
3034 if(!offset&&s!=temp) emit_mov(s,temp);
3040 if(!memtarget||!rs1[i]) {
3046 int map=get_reg(i_regs->regmap,ROREG);
3047 if(map<0) emit_loadreg(ROREG,map=HOST_TEMPREG);
3049 if((u_int)rdram!=0x80000000)
3050 emit_addimm_no_flags((u_int)rdram-(u_int)0x80000000,temp);
3053 if (opcode[i]==0x2C||opcode[i]==0x2D) { // SDL/SDR
3054 temp2=get_reg(i_regs->regmap,FTEMP);
3055 if(!rs2[i]) temp2=th=tl;
3058 #ifndef BIG_ENDIAN_MIPS
3059 emit_xorimm(temp,3,temp);
3061 emit_testimm(temp,2);
3064 emit_testimm(temp,1);
3068 if (opcode[i]==0x2A) { // SWL
3069 emit_writeword_indexed(tl,0,temp);
3071 if (opcode[i]==0x2E) { // SWR
3072 emit_writebyte_indexed(tl,3,temp);
3074 if (opcode[i]==0x2C) { // SDL
3075 emit_writeword_indexed(th,0,temp);
3076 if(rs2[i]) emit_mov(tl,temp2);
3078 if (opcode[i]==0x2D) { // SDR
3079 emit_writebyte_indexed(tl,3,temp);
3080 if(rs2[i]) emit_shldimm(th,tl,24,temp2);
3085 set_jump_target(case1, out);
3086 if (opcode[i]==0x2A) { // SWL
3087 // Write 3 msb into three least significant bytes
3088 if(rs2[i]) emit_rorimm(tl,8,tl);
3089 emit_writehword_indexed(tl,-1,temp);
3090 if(rs2[i]) emit_rorimm(tl,16,tl);
3091 emit_writebyte_indexed(tl,1,temp);
3092 if(rs2[i]) emit_rorimm(tl,8,tl);
3094 if (opcode[i]==0x2E) { // SWR
3095 // Write two lsb into two most significant bytes
3096 emit_writehword_indexed(tl,1,temp);
3098 if (opcode[i]==0x2C) { // SDL
3099 if(rs2[i]) emit_shrdimm(tl,th,8,temp2);
3100 // Write 3 msb into three least significant bytes
3101 if(rs2[i]) emit_rorimm(th,8,th);
3102 emit_writehword_indexed(th,-1,temp);
3103 if(rs2[i]) emit_rorimm(th,16,th);
3104 emit_writebyte_indexed(th,1,temp);
3105 if(rs2[i]) emit_rorimm(th,8,th);
3107 if (opcode[i]==0x2D) { // SDR
3108 if(rs2[i]) emit_shldimm(th,tl,16,temp2);
3109 // Write two lsb into two most significant bytes
3110 emit_writehword_indexed(tl,1,temp);
3115 set_jump_target(case2, out);
3116 emit_testimm(temp,1);
3119 if (opcode[i]==0x2A) { // SWL
3120 // Write two msb into two least significant bytes
3121 if(rs2[i]) emit_rorimm(tl,16,tl);
3122 emit_writehword_indexed(tl,-2,temp);
3123 if(rs2[i]) emit_rorimm(tl,16,tl);
3125 if (opcode[i]==0x2E) { // SWR
3126 // Write 3 lsb into three most significant bytes
3127 emit_writebyte_indexed(tl,-1,temp);
3128 if(rs2[i]) emit_rorimm(tl,8,tl);
3129 emit_writehword_indexed(tl,0,temp);
3130 if(rs2[i]) emit_rorimm(tl,24,tl);
3132 if (opcode[i]==0x2C) { // SDL
3133 if(rs2[i]) emit_shrdimm(tl,th,16,temp2);
3134 // Write two msb into two least significant bytes
3135 if(rs2[i]) emit_rorimm(th,16,th);
3136 emit_writehword_indexed(th,-2,temp);
3137 if(rs2[i]) emit_rorimm(th,16,th);
3139 if (opcode[i]==0x2D) { // SDR
3140 if(rs2[i]) emit_shldimm(th,tl,8,temp2);
3141 // Write 3 lsb into three most significant bytes
3142 emit_writebyte_indexed(tl,-1,temp);
3143 if(rs2[i]) emit_rorimm(tl,8,tl);
3144 emit_writehword_indexed(tl,0,temp);
3145 if(rs2[i]) emit_rorimm(tl,24,tl);
3150 set_jump_target(case3, out);
3151 if (opcode[i]==0x2A) { // SWL
3152 // Write msb into least significant byte
3153 if(rs2[i]) emit_rorimm(tl,24,tl);
3154 emit_writebyte_indexed(tl,-3,temp);
3155 if(rs2[i]) emit_rorimm(tl,8,tl);
3157 if (opcode[i]==0x2E) { // SWR
3158 // Write entire word
3159 emit_writeword_indexed(tl,-3,temp);
3161 if (opcode[i]==0x2C) { // SDL
3162 if(rs2[i]) emit_shrdimm(tl,th,24,temp2);
3163 // Write msb into least significant byte
3164 if(rs2[i]) emit_rorimm(th,24,th);
3165 emit_writebyte_indexed(th,-3,temp);
3166 if(rs2[i]) emit_rorimm(th,8,th);
3168 if (opcode[i]==0x2D) { // SDR
3169 if(rs2[i]) emit_mov(th,temp2);
3170 // Write entire word
3171 emit_writeword_indexed(tl,-3,temp);
3173 set_jump_target(done0, out);
3174 set_jump_target(done1, out);
3175 set_jump_target(done2, out);
3176 if (opcode[i]==0x2C) { // SDL
3177 emit_testimm(temp,4);
3180 emit_andimm(temp,~3,temp);
3181 emit_writeword_indexed(temp2,4,temp);
3182 set_jump_target(done0, out);
3184 if (opcode[i]==0x2D) { // SDR
3185 emit_testimm(temp,4);
3188 emit_andimm(temp,~3,temp);
3189 emit_writeword_indexed(temp2,-4,temp);
3190 set_jump_target(done0, out);
3193 add_stub_r(STORELR_STUB,jaddr,out,i,temp,i_regs,ccadj[i],reglist);
3194 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3196 int map=get_reg(i_regs->regmap,ROREG);
3197 if(map<0) map=HOST_TEMPREG;
3198 gen_orig_addr_w(temp,map);
3200 emit_addimm_no_flags((u_int)0x80000000-(u_int)rdram,temp);
3202 #if defined(HOST_IMM8)
3203 int ir=get_reg(i_regs->regmap,INVCP);
3205 emit_cmpmem_indexedsr12_reg(ir,temp,1);
3207 emit_cmpmem_indexedsr12_imm((int)invalid_code,temp,1);
3209 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3210 emit_callne(invalidate_addr_reg[temp]);
3214 add_stub(INVCODE_STUB,jaddr2,out,reglist|(1<<HOST_CCREG),temp,0,0,0);
3219 void c1ls_assemble(int i,struct regstat *i_regs)
3221 cop1_unusable(i, i_regs);
3224 void c2ls_assemble(int i,struct regstat *i_regs)
3229 int memtarget=0,c=0;
3231 enum stub_type type;
3232 int agr=AGEN1+(i&1);
3233 int fastio_reg_override=0;
3235 u_int copr=(source[i]>>16)&0x1f;
3236 s=get_reg(i_regs->regmap,rs1[i]);
3237 tl=get_reg(i_regs->regmap,FTEMP);
3242 for(hr=0;hr<HOST_REGS;hr++) {
3243 if(i_regs->regmap[hr]>=0) reglist|=1<<hr;
3245 if(i_regs->regmap[HOST_CCREG]==CCREG)
3246 reglist&=~(1<<HOST_CCREG);
3249 if (opcode[i]==0x3a) { // SWC2
3250 ar=get_reg(i_regs->regmap,agr);
3251 if(ar<0) ar=get_reg(i_regs->regmap,-1);
3256 if(s>=0) c=(i_regs->wasconst>>s)&1;
3257 memtarget=c&&(((signed int)(constmap[i][s]+offset))<(signed int)0x80000000+RAM_SIZE);
3258 if (!offset&&!c&&s>=0) ar=s;
3261 if (opcode[i]==0x3a) { // SWC2
3262 cop2_get_dreg(copr,tl,HOST_TEMPREG);
3270 emit_jmp(0); // inline_readstub/inline_writestub?
3274 jaddr2=emit_fastpath_cmp_jump(i,ar,&fastio_reg_override);
3276 else if(ram_offset&&memtarget) {
3277 emit_addimm(ar,ram_offset,HOST_TEMPREG);
3278 fastio_reg_override=HOST_TEMPREG;
3280 if (opcode[i]==0x32) { // LWC2
3281 #ifdef HOST_IMM_ADDR32
3282 if(c) emit_readword_tlb(constmap[i][s]+offset,-1,tl);
3286 if(fastio_reg_override) a=fastio_reg_override;
3287 emit_readword_indexed(0,a,tl);
3289 if (opcode[i]==0x3a) { // SWC2
3290 #ifdef DESTRUCTIVE_SHIFT
3291 if(!offset&&!c&&s>=0) emit_mov(s,ar);
3294 if(fastio_reg_override) a=fastio_reg_override;
3295 emit_writeword_indexed(tl,0,a);
3299 add_stub_r(type,jaddr2,out,i,ar,i_regs,ccadj[i],reglist);
3300 if(opcode[i]==0x3a) // SWC2
3301 if(!(i_regs->waswritten&(1<<rs1[i]))&&!(new_dynarec_hacks&NDHACK_NO_SMC_CHECK)) {
3302 #if defined(HOST_IMM8)
3303 int ir=get_reg(i_regs->regmap,INVCP);
3305 emit_cmpmem_indexedsr12_reg(ir,ar,1);
3307 emit_cmpmem_indexedsr12_imm((int)invalid_code,ar,1);
3309 #if defined(HAVE_CONDITIONAL_CALL) && !defined(DESTRUCTIVE_SHIFT)
3310 emit_callne(invalidate_addr_reg[ar]);
3314 add_stub(INVCODE_STUB,jaddr3,out,reglist|(1<<HOST_CCREG),ar,0,0,0);
3317 if (opcode[i]==0x32) { // LWC2
3318 cop2_put_dreg(copr,tl,HOST_TEMPREG);
3322 #ifndef multdiv_assemble
3323 void multdiv_assemble(int i,struct regstat *i_regs)
3325 printf("Need multdiv_assemble for this architecture.\n");
3330 void mov_assemble(int i,struct regstat *i_regs)
3332 //if(opcode2[i]==0x10||opcode2[i]==0x12) { // MFHI/MFLO
3333 //if(opcode2[i]==0x11||opcode2[i]==0x13) { // MTHI/MTLO
3335 signed char sh,sl,th,tl;
3336 th=get_reg(i_regs->regmap,rt1[i]|64);
3337 tl=get_reg(i_regs->regmap,rt1[i]);
3340 sh=get_reg(i_regs->regmap,rs1[i]|64);
3341 sl=get_reg(i_regs->regmap,rs1[i]);
3342 if(sl>=0) emit_mov(sl,tl);
3343 else emit_loadreg(rs1[i],tl);
3345 if(sh>=0) emit_mov(sh,th);
3346 else emit_loadreg(rs1[i]|64,th);
3352 #ifndef fconv_assemble
3353 void fconv_assemble(int i,struct regstat *i_regs)
3355 printf("Need fconv_assemble for this architecture.\n");
3361 void float_assemble(int i,struct regstat *i_regs)
3363 printf("Need float_assemble for this architecture.\n");
3368 void syscall_assemble(int i,struct regstat *i_regs)
3370 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3371 assert(ccreg==HOST_CCREG);
3372 assert(!is_delayslot);
3374 emit_movimm(start+i*4,EAX); // Get PC
3375 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // CHECK: is this right? There should probably be an extra cycle...
3376 emit_jmp(jump_syscall_hle); // XXX
3379 void hlecall_assemble(int i,struct regstat *i_regs)
3381 extern void psxNULL();
3382 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3383 assert(ccreg==HOST_CCREG);
3384 assert(!is_delayslot);
3386 emit_movimm(start+i*4+4,0); // Get PC
3387 uint32_t hleCode = source[i] & 0x03ffffff;
3388 if (hleCode >= ARRAY_SIZE(psxHLEt))
3389 emit_movimm((int)psxNULL,1);
3391 emit_movimm((int)psxHLEt[hleCode],1);
3392 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG); // XXX
3393 emit_jmp(jump_hlecall);
3396 void intcall_assemble(int i,struct regstat *i_regs)
3398 signed char ccreg=get_reg(i_regs->regmap,CCREG);
3399 assert(ccreg==HOST_CCREG);
3400 assert(!is_delayslot);
3402 emit_movimm(start+i*4,0); // Get PC
3403 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]),HOST_CCREG);
3404 emit_jmp(jump_intcall);
3407 void ds_assemble(int i,struct regstat *i_regs)
3409 speculate_register_values(i);
3413 alu_assemble(i,i_regs);break;
3415 imm16_assemble(i,i_regs);break;
3417 shift_assemble(i,i_regs);break;
3419 shiftimm_assemble(i,i_regs);break;
3421 load_assemble(i,i_regs);break;
3423 loadlr_assemble(i,i_regs);break;
3425 store_assemble(i,i_regs);break;
3427 storelr_assemble(i,i_regs);break;
3429 cop0_assemble(i,i_regs);break;
3431 cop1_assemble(i,i_regs);break;
3433 c1ls_assemble(i,i_regs);break;
3435 cop2_assemble(i,i_regs);break;
3437 c2ls_assemble(i,i_regs);break;
3439 c2op_assemble(i,i_regs);break;
3441 fconv_assemble(i,i_regs);break;
3443 float_assemble(i,i_regs);break;
3445 fcomp_assemble(i,i_regs);break;
3447 multdiv_assemble(i,i_regs);break;
3449 mov_assemble(i,i_regs);break;
3459 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
3464 // Is the branch target a valid internal jump?
3465 int internal_branch(uint64_t i_is32,int addr)
3467 if(addr&1) return 0; // Indirect (register) jump
3468 if(addr>=start && addr<start+slen*4-4)
3470 //int t=(addr-start)>>2;
3471 // Delay slots are not valid branch targets
3472 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
3473 // 64 -> 32 bit transition requires a recompile
3474 /*if(is32[t]&~unneeded_reg_upper[t]&~i_is32)
3476 if(requires_32bit[t]&~i_is32) printf("optimizable: no\n");
3477 else printf("optimizable: yes\n");
3479 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
3485 #ifndef wb_invalidate
3486 void wb_invalidate(signed char pre[],signed char entry[],uint64_t dirty,uint64_t is32,
3487 uint64_t u,uint64_t uu)
3490 for(hr=0;hr<HOST_REGS;hr++) {
3491 if(hr!=EXCLUDE_REG) {
3492 if(pre[hr]!=entry[hr]) {
3495 if(get_reg(entry,pre[hr])<0) {
3497 if(!((u>>pre[hr])&1)) {
3498 emit_storereg(pre[hr],hr);
3499 if( ((is32>>pre[hr])&1) && !((uu>>pre[hr])&1) ) {
3500 emit_sarimm(hr,31,hr);
3501 emit_storereg(pre[hr]|64,hr);
3505 if(!((uu>>(pre[hr]&63))&1) && !((is32>>(pre[hr]&63))&1)) {
3506 emit_storereg(pre[hr],hr);
3515 // Move from one register to another (no writeback)
3516 for(hr=0;hr<HOST_REGS;hr++) {
3517 if(hr!=EXCLUDE_REG) {
3518 if(pre[hr]!=entry[hr]) {
3519 if(pre[hr]>=0&&(pre[hr]&63)<TEMPREG) {
3521 if((nr=get_reg(entry,pre[hr]))>=0) {
3531 // Load the specified registers
3532 // This only loads the registers given as arguments because
3533 // we don't want to load things that will be overwritten
3534 void load_regs(signed char entry[],signed char regmap[],int is32,int rs1,int rs2)
3538 for(hr=0;hr<HOST_REGS;hr++) {
3539 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3540 if(entry[hr]!=regmap[hr]) {
3541 if(regmap[hr]==rs1||regmap[hr]==rs2)
3548 emit_loadreg(regmap[hr],hr);
3555 for(hr=0;hr<HOST_REGS;hr++) {
3556 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3557 if(entry[hr]!=regmap[hr]) {
3558 if(regmap[hr]-64==rs1||regmap[hr]-64==rs2)
3560 assert(regmap[hr]!=64);
3561 if((is32>>(regmap[hr]&63))&1) {
3562 int lr=get_reg(regmap,regmap[hr]-64);
3564 emit_sarimm(lr,31,hr);
3566 emit_loadreg(regmap[hr],hr);
3570 emit_loadreg(regmap[hr],hr);
3578 // Load registers prior to the start of a loop
3579 // so that they are not loaded within the loop
3580 static void loop_preload(signed char pre[],signed char entry[])
3583 for(hr=0;hr<HOST_REGS;hr++) {
3584 if(hr!=EXCLUDE_REG) {
3585 if(pre[hr]!=entry[hr]) {
3587 if(get_reg(pre,entry[hr])<0) {
3588 assem_debug("loop preload:\n");
3589 //printf("loop preload: %d\n",hr);
3593 else if(entry[hr]<TEMPREG)
3595 emit_loadreg(entry[hr],hr);
3597 else if(entry[hr]-64<TEMPREG)
3599 emit_loadreg(entry[hr],hr);
3608 // Generate address for load/store instruction
3609 // goes to AGEN for writes, FTEMP for LOADLR and cop1/2 loads
3610 void address_generation(int i,struct regstat *i_regs,signed char entry[])
3612 if(itype[i]==LOAD||itype[i]==LOADLR||itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS||itype[i]==C2LS) {
3614 int agr=AGEN1+(i&1);
3615 if(itype[i]==LOAD) {
3616 ra=get_reg(i_regs->regmap,rt1[i]);
3617 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3620 if(itype[i]==LOADLR) {
3621 ra=get_reg(i_regs->regmap,FTEMP);
3623 if(itype[i]==STORE||itype[i]==STORELR) {
3624 ra=get_reg(i_regs->regmap,agr);
3625 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3627 if(itype[i]==C1LS||itype[i]==C2LS) {
3628 if ((opcode[i]&0x3b)==0x31||(opcode[i]&0x3b)==0x32) // LWC1/LDC1/LWC2/LDC2
3629 ra=get_reg(i_regs->regmap,FTEMP);
3630 else { // SWC1/SDC1/SWC2/SDC2
3631 ra=get_reg(i_regs->regmap,agr);
3632 if(ra<0) ra=get_reg(i_regs->regmap,-1);
3635 int rs=get_reg(i_regs->regmap,rs1[i]);
3638 int c=(i_regs->wasconst>>rs)&1;
3640 // Using r0 as a base address
3641 if(!entry||entry[ra]!=agr) {
3642 if (opcode[i]==0x22||opcode[i]==0x26) {
3643 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3644 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3645 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3647 emit_movimm(offset,ra);
3649 } // else did it in the previous cycle
3652 if(!entry||entry[ra]!=rs1[i])
3653 emit_loadreg(rs1[i],ra);
3654 //if(!entry||entry[ra]!=rs1[i])
3655 // printf("poor load scheduling!\n");
3658 if(rs1[i]!=rt1[i]||itype[i]!=LOAD) {
3659 if(!entry||entry[ra]!=agr) {
3660 if (opcode[i]==0x22||opcode[i]==0x26) {
3661 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3662 }else if (opcode[i]==0x1a||opcode[i]==0x1b) {
3663 emit_movimm((constmap[i][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3665 #ifdef HOST_IMM_ADDR32
3666 if((itype[i]!=LOAD&&(opcode[i]&0x3b)!=0x31&&(opcode[i]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
3668 emit_movimm(constmap[i][rs]+offset,ra);
3669 regs[i].loadedconst|=1<<ra;
3671 } // else did it in the previous cycle
3672 } // else load_consts already did it
3674 if(offset&&!c&&rs1[i]) {
3676 emit_addimm(rs,offset,ra);
3678 emit_addimm(ra,offset,ra);
3683 // Preload constants for next instruction
3684 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS||itype[i+1]==C2LS) {
3687 agr=AGEN1+((i+1)&1);
3688 ra=get_reg(i_regs->regmap,agr);
3690 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
3691 int offset=imm[i+1];
3692 int c=(regs[i+1].wasconst>>rs)&1;
3693 if(c&&(rs1[i+1]!=rt1[i+1]||itype[i+1]!=LOAD)) {
3694 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3695 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFFC,ra); // LWL/LWR
3696 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3697 emit_movimm((constmap[i+1][rs]+offset)&0xFFFFFFF8,ra); // LDL/LDR
3699 #ifdef HOST_IMM_ADDR32
3700 if((itype[i+1]!=LOAD&&(opcode[i+1]&0x3b)!=0x31&&(opcode[i+1]&0x3b)!=0x32)) // LWC1/LDC1/LWC2/LDC2
3702 emit_movimm(constmap[i+1][rs]+offset,ra);
3703 regs[i+1].loadedconst|=1<<ra;
3706 else if(rs1[i+1]==0) {
3707 // Using r0 as a base address
3708 if (opcode[i+1]==0x22||opcode[i+1]==0x26) {
3709 emit_movimm(offset&0xFFFFFFFC,ra); // LWL/LWR
3710 }else if (opcode[i+1]==0x1a||opcode[i+1]==0x1b) {
3711 emit_movimm(offset&0xFFFFFFF8,ra); // LDL/LDR
3713 emit_movimm(offset,ra);
3720 static int get_final_value(int hr, int i, int *value)
3722 int reg=regs[i].regmap[hr];
3724 if(regs[i+1].regmap[hr]!=reg) break;
3725 if(!((regs[i+1].isconst>>hr)&1)) break;
3730 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP) {
3731 *value=constmap[i][hr];
3735 if(itype[i+1]==UJUMP||itype[i+1]==RJUMP||itype[i+1]==CJUMP||itype[i+1]==SJUMP) {
3736 // Load in delay slot, out-of-order execution
3737 if(itype[i+2]==LOAD&&rs1[i+2]==reg&&rt1[i+2]==reg&&((regs[i+1].wasconst>>hr)&1))
3739 // Precompute load address
3740 *value=constmap[i][hr]+imm[i+2];
3744 if(itype[i+1]==LOAD&&rs1[i+1]==reg&&rt1[i+1]==reg)
3746 // Precompute load address
3747 *value=constmap[i][hr]+imm[i+1];
3748 //printf("c=%x imm=%x\n",(int)constmap[i][hr],imm[i+1]);
3753 *value=constmap[i][hr];
3754 //printf("c=%x\n",(int)constmap[i][hr]);
3755 if(i==slen-1) return 1;
3757 return !((unneeded_reg[i+1]>>reg)&1);
3759 return !((unneeded_reg_upper[i+1]>>reg)&1);
3763 // Load registers with known constants
3764 void load_consts(signed char pre[],signed char regmap[],int is32,int i)
3767 // propagate loaded constant flags
3769 regs[i].loadedconst=0;
3771 for(hr=0;hr<HOST_REGS;hr++) {
3772 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((regs[i-1].isconst>>hr)&1)&&pre[hr]==regmap[hr]
3773 &®map[hr]==regs[i-1].regmap[hr]&&((regs[i-1].loadedconst>>hr)&1))
3775 regs[i].loadedconst|=1<<hr;
3780 for(hr=0;hr<HOST_REGS;hr++) {
3781 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3782 //if(entry[hr]!=regmap[hr]) {
3783 if(!((regs[i].loadedconst>>hr)&1)) {
3784 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
3785 int value,similar=0;
3786 if(get_final_value(hr,i,&value)) {
3787 // see if some other register has similar value
3788 for(hr2=0;hr2<HOST_REGS;hr2++) {
3789 if(hr2!=EXCLUDE_REG&&((regs[i].loadedconst>>hr2)&1)) {
3790 if(is_similar_value(value,constmap[i][hr2])) {
3798 if(get_final_value(hr2,i,&value2)) // is this needed?
3799 emit_movimm_from(value2,hr2,value,hr);
3801 emit_movimm(value,hr);
3807 emit_movimm(value,hr);
3810 regs[i].loadedconst|=1<<hr;
3816 for(hr=0;hr<HOST_REGS;hr++) {
3817 if(hr!=EXCLUDE_REG&®map[hr]>=0) {
3818 //if(entry[hr]!=regmap[hr]) {
3819 if(i==0||!((regs[i-1].isconst>>hr)&1)||pre[hr]!=regmap[hr]||bt[i]) {
3820 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
3821 if((is32>>(regmap[hr]&63))&1) {
3822 int lr=get_reg(regmap,regmap[hr]-64);
3824 emit_sarimm(lr,31,hr);
3829 if(get_final_value(hr,i,&value)) {
3834 emit_movimm(value,hr);
3843 void load_all_consts(signed char regmap[],int is32,u_int dirty,int i)
3847 for(hr=0;hr<HOST_REGS;hr++) {
3848 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
3849 if(((regs[i].isconst>>hr)&1)&®map[hr]<64&®map[hr]>0) {
3850 int value=constmap[i][hr];
3855 emit_movimm(value,hr);
3861 for(hr=0;hr<HOST_REGS;hr++) {
3862 if(hr!=EXCLUDE_REG&®map[hr]>=0&&((dirty>>hr)&1)) {
3863 if(((regs[i].isconst>>hr)&1)&®map[hr]>64) {
3864 if((is32>>(regmap[hr]&63))&1) {
3865 int lr=get_reg(regmap,regmap[hr]-64);
3867 emit_sarimm(lr,31,hr);
3871 int value=constmap[i][hr];
3876 emit_movimm(value,hr);
3884 // Write out all dirty registers (except cycle count)
3885 void wb_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty)
3888 for(hr=0;hr<HOST_REGS;hr++) {
3889 if(hr!=EXCLUDE_REG) {
3890 if(i_regmap[hr]>0) {
3891 if(i_regmap[hr]!=CCREG) {
3892 if((i_dirty>>hr)&1) {
3893 if(i_regmap[hr]<64) {
3894 emit_storereg(i_regmap[hr],hr);
3896 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
3897 emit_storereg(i_regmap[hr],hr);
3906 // Write out dirty registers that we need to reload (pair with load_needed_regs)
3907 // This writes the registers not written by store_regs_bt
3908 void wb_needed_dirtys(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
3911 int t=(addr-start)>>2;
3912 for(hr=0;hr<HOST_REGS;hr++) {
3913 if(hr!=EXCLUDE_REG) {
3914 if(i_regmap[hr]>0) {
3915 if(i_regmap[hr]!=CCREG) {
3916 if(i_regmap[hr]==regs[t].regmap_entry[hr] && ((regs[t].dirty>>hr)&1) && !(((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
3917 if((i_dirty>>hr)&1) {
3918 if(i_regmap[hr]<64) {
3919 emit_storereg(i_regmap[hr],hr);
3921 if( !((i_is32>>(i_regmap[hr]&63))&1) ) {
3922 emit_storereg(i_regmap[hr],hr);
3933 // Load all registers (except cycle count)
3934 void load_all_regs(signed char i_regmap[])
3937 for(hr=0;hr<HOST_REGS;hr++) {
3938 if(hr!=EXCLUDE_REG) {
3939 if(i_regmap[hr]==0) {
3943 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
3945 emit_loadreg(i_regmap[hr],hr);
3951 // Load all current registers also needed by next instruction
3952 void load_needed_regs(signed char i_regmap[],signed char next_regmap[])
3955 for(hr=0;hr<HOST_REGS;hr++) {
3956 if(hr!=EXCLUDE_REG) {
3957 if(get_reg(next_regmap,i_regmap[hr])>=0) {
3958 if(i_regmap[hr]==0) {
3962 if(i_regmap[hr]>0 && (i_regmap[hr]&63)<TEMPREG && i_regmap[hr]!=CCREG)
3964 emit_loadreg(i_regmap[hr],hr);
3971 // Load all regs, storing cycle count if necessary
3972 void load_regs_entry(int t)
3975 if(is_ds[t]) emit_addimm(HOST_CCREG,CLOCK_ADJUST(1),HOST_CCREG);
3976 else if(ccadj[t]) emit_addimm(HOST_CCREG,-CLOCK_ADJUST(ccadj[t]),HOST_CCREG);
3977 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
3978 emit_storereg(CCREG,HOST_CCREG);
3981 for(hr=0;hr<HOST_REGS;hr++) {
3982 if(regs[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
3983 if(regs[t].regmap_entry[hr]==0) {
3986 else if(regs[t].regmap_entry[hr]!=CCREG)
3988 emit_loadreg(regs[t].regmap_entry[hr],hr);
3993 for(hr=0;hr<HOST_REGS;hr++) {
3994 if(regs[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
3995 assert(regs[t].regmap_entry[hr]!=64);
3996 if((regs[t].was32>>(regs[t].regmap_entry[hr]&63))&1) {
3997 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
3999 emit_loadreg(regs[t].regmap_entry[hr],hr);
4003 emit_sarimm(lr,31,hr);
4008 emit_loadreg(regs[t].regmap_entry[hr],hr);
4014 // Store dirty registers prior to branch
4015 void store_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4017 if(internal_branch(i_is32,addr))
4019 int t=(addr-start)>>2;
4021 for(hr=0;hr<HOST_REGS;hr++) {
4022 if(hr!=EXCLUDE_REG) {
4023 if(i_regmap[hr]>0 && i_regmap[hr]!=CCREG) {
4024 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || !((regs[t].dirty>>hr)&1) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4025 if((i_dirty>>hr)&1) {
4026 if(i_regmap[hr]<64) {
4027 if(!((unneeded_reg[t]>>i_regmap[hr])&1)) {
4028 emit_storereg(i_regmap[hr],hr);
4029 if( ((i_is32>>i_regmap[hr])&1) && !((unneeded_reg_upper[t]>>i_regmap[hr])&1) ) {
4030 #ifdef DESTRUCTIVE_WRITEBACK
4031 emit_sarimm(hr,31,hr);
4032 emit_storereg(i_regmap[hr]|64,hr);
4034 emit_sarimm(hr,31,HOST_TEMPREG);
4035 emit_storereg(i_regmap[hr]|64,HOST_TEMPREG);
4040 if( !((i_is32>>(i_regmap[hr]&63))&1) && !((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1) ) {
4041 emit_storereg(i_regmap[hr],hr);
4052 // Branch out of this block, write out all dirty regs
4053 wb_dirtys(i_regmap,i_is32,i_dirty);
4057 // Load all needed registers for branch target
4058 void load_regs_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4060 //if(addr>=start && addr<(start+slen*4))
4061 if(internal_branch(i_is32,addr))
4063 int t=(addr-start)>>2;
4065 // Store the cycle count before loading something else
4066 if(i_regmap[HOST_CCREG]!=CCREG) {
4067 assert(i_regmap[HOST_CCREG]==-1);
4069 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) {
4070 emit_storereg(CCREG,HOST_CCREG);
4073 for(hr=0;hr<HOST_REGS;hr++) {
4074 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=0&®s[t].regmap_entry[hr]<TEMPREG) {
4075 #ifdef DESTRUCTIVE_WRITEBACK
4076 if(i_regmap[hr]!=regs[t].regmap_entry[hr] || ( !((regs[t].dirty>>hr)&1) && ((i_dirty>>hr)&1) && (((i_is32&~unneeded_reg_upper[t])>>i_regmap[hr])&1) ) || (((i_is32&~regs[t].was32&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)) {
4078 if(i_regmap[hr]!=regs[t].regmap_entry[hr] ) {
4080 if(regs[t].regmap_entry[hr]==0) {
4083 else if(regs[t].regmap_entry[hr]!=CCREG)
4085 emit_loadreg(regs[t].regmap_entry[hr],hr);
4091 for(hr=0;hr<HOST_REGS;hr++) {
4092 if(hr!=EXCLUDE_REG&®s[t].regmap_entry[hr]>=64&®s[t].regmap_entry[hr]<TEMPREG+64) {
4093 if(i_regmap[hr]!=regs[t].regmap_entry[hr]) {
4094 assert(regs[t].regmap_entry[hr]!=64);
4095 if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4096 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4098 emit_loadreg(regs[t].regmap_entry[hr],hr);
4102 emit_sarimm(lr,31,hr);
4107 emit_loadreg(regs[t].regmap_entry[hr],hr);
4110 else if((i_is32>>(regs[t].regmap_entry[hr]&63))&1) {
4111 int lr=get_reg(regs[t].regmap_entry,regs[t].regmap_entry[hr]-64);
4113 emit_sarimm(lr,31,hr);
4120 int match_bt(signed char i_regmap[],uint64_t i_is32,uint64_t i_dirty,int addr)
4122 if(addr>=start && addr<start+slen*4-4)
4124 int t=(addr-start)>>2;
4126 if(regs[t].regmap_entry[HOST_CCREG]!=CCREG) return 0;
4127 for(hr=0;hr<HOST_REGS;hr++)
4131 if(i_regmap[hr]!=regs[t].regmap_entry[hr])
4133 if(regs[t].regmap_entry[hr]>=0&&(regs[t].regmap_entry[hr]|64)<TEMPREG+64)
4140 if(i_regmap[hr]<TEMPREG)
4142 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4145 else if(i_regmap[hr]>=64&&i_regmap[hr]<TEMPREG+64)
4147 if(!((unneeded_reg_upper[t]>>(i_regmap[hr]&63))&1))
4152 else // Same register but is it 32-bit or dirty?
4155 if(!((regs[t].dirty>>hr)&1))
4159 if(!((unneeded_reg[t]>>i_regmap[hr])&1))
4161 //printf("%x: dirty no match\n",addr);
4166 if((((regs[t].was32^i_is32)&~unneeded_reg_upper[t])>>(i_regmap[hr]&63))&1)
4168 //printf("%x: is32 no match\n",addr);
4174 //if(is32[t]&~unneeded_reg_upper[t]&~i_is32) return 0;
4175 // Delay slots are not valid branch targets
4176 //if(t>0&&(itype[t-1]==RJUMP||itype[t-1]==UJUMP||itype[t-1]==CJUMP||itype[t-1]==SJUMP||itype[t-1]==FJUMP)) return 0;
4177 // Delay slots require additional processing, so do not match
4178 if(is_ds[t]) return 0;
4183 for(hr=0;hr<HOST_REGS;hr++)
4189 if(hr!=HOST_CCREG||i_regmap[hr]!=CCREG)
4204 static void drc_dbg_emit_do_cmp(int i)
4206 extern void do_insn_cmp();
4210 for(hr=0;hr<HOST_REGS;hr++)
4211 if(regs[i].regmap[hr]>=0) reglist|=1<<hr;
4213 emit_movimm(start+i*4,0);
4214 emit_writeword(0,(int)&pcaddr);
4215 emit_call((int)do_insn_cmp);
4216 //emit_readword((int)&cycle,0);
4217 //emit_addimm(0,2,0);
4218 //emit_writeword(0,(int)&cycle);
4219 restore_regs(reglist);
4222 #define drc_dbg_emit_do_cmp(x)
4225 // Used when a branch jumps into the delay slot of another branch
4226 void ds_assemble_entry(int i)
4228 int t=(ba[i]-start)>>2;
4230 instr_addr[t] = out;
4231 assem_debug("Assemble delay slot at %x\n",ba[i]);
4232 assem_debug("<->\n");
4233 drc_dbg_emit_do_cmp(t);
4234 if(regs[t].regmap_entry[HOST_CCREG]==CCREG&®s[t].regmap[HOST_CCREG]!=CCREG)
4235 wb_register(CCREG,regs[t].regmap_entry,regs[t].wasdirty,regs[t].was32);
4236 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,rs1[t],rs2[t]);
4237 address_generation(t,®s[t],regs[t].regmap_entry);
4238 if(itype[t]==STORE||itype[t]==STORELR||(opcode[t]&0x3b)==0x39||(opcode[t]&0x3b)==0x3a)
4239 load_regs(regs[t].regmap_entry,regs[t].regmap,regs[t].was32,INVCP,INVCP);
4244 alu_assemble(t,®s[t]);break;
4246 imm16_assemble(t,®s[t]);break;
4248 shift_assemble(t,®s[t]);break;
4250 shiftimm_assemble(t,®s[t]);break;
4252 load_assemble(t,®s[t]);break;
4254 loadlr_assemble(t,®s[t]);break;
4256 store_assemble(t,®s[t]);break;
4258 storelr_assemble(t,®s[t]);break;
4260 cop0_assemble(t,®s[t]);break;
4262 cop1_assemble(t,®s[t]);break;
4264 c1ls_assemble(t,®s[t]);break;
4266 cop2_assemble(t,®s[t]);break;
4268 c2ls_assemble(t,®s[t]);break;
4270 c2op_assemble(t,®s[t]);break;
4272 fconv_assemble(t,®s[t]);break;
4274 float_assemble(t,®s[t]);break;
4276 fcomp_assemble(t,®s[t]);break;
4278 multdiv_assemble(t,®s[t]);break;
4280 mov_assemble(t,®s[t]);break;
4290 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
4292 store_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4293 load_regs_bt(regs[t].regmap,regs[t].is32,regs[t].dirty,ba[i]+4);
4294 if(internal_branch(regs[t].is32,ba[i]+4))
4295 assem_debug("branch: internal\n");
4297 assem_debug("branch: external\n");
4298 assert(internal_branch(regs[t].is32,ba[i]+4));
4299 add_to_linker((int)out,ba[i]+4,internal_branch(regs[t].is32,ba[i]+4));
4303 void do_cc(int i,signed char i_regmap[],int *adj,int addr,int taken,int invert)
4313 //if(ba[i]>=start && ba[i]<(start+slen*4))
4314 if(internal_branch(branch_regs[i].is32,ba[i]))
4317 if(is_ds[t]) *adj=-1; // Branch into delay slot adds an extra cycle
4325 if(taken==TAKEN && i==(ba[i]-start)>>2 && source[i+1]==0) {
4327 if(count&1) emit_addimm_and_set_flags(2*(count+2),HOST_CCREG);
4329 //emit_subfrommem(&idlecount,HOST_CCREG); // Count idle cycles
4330 emit_andimm(HOST_CCREG,3,HOST_CCREG);
4334 else if(*adj==0||invert) {
4335 int cycles=CLOCK_ADJUST(count+2);
4339 if(-NO_CYCLE_PENALTY_THR<rel&&rel<0)
4340 cycles=CLOCK_ADJUST(*adj)+count+2-*adj;
4342 emit_addimm_and_set_flags(cycles,HOST_CCREG);
4348 emit_cmpimm(HOST_CCREG,-CLOCK_ADJUST(count+2));
4352 add_stub(CC_STUB,jaddr,idle?idle:out,(*adj==0||invert||idle)?0:(count+2),i,addr,taken,0);
4355 static void do_ccstub(int n)
4358 assem_debug("do_ccstub %x\n",start+stubs[n].b*4);
4359 set_jump_target(stubs[n].addr, out);
4361 if(stubs[n].d==NULLDS) {
4362 // Delay slot instruction is nullified ("likely" branch)
4363 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
4365 else if(stubs[n].d!=TAKEN) {
4366 wb_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty);
4369 if(internal_branch(branch_regs[i].is32,ba[i]))
4370 wb_needed_dirtys(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4374 // Save PC as return address
4375 emit_movimm(stubs[n].c,EAX);
4376 emit_writeword(EAX,(int)&pcaddr);
4380 // Return address depends on which way the branch goes
4381 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
4383 int s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4384 int s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4385 int s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4386 int s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4396 if((branch_regs[i].is32>>rs1[i])&(branch_regs[i].is32>>rs2[i])&1) {
4400 #ifdef DESTRUCTIVE_WRITEBACK
4402 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs1[i])&1)
4403 emit_loadreg(rs1[i],s1l);
4406 if((branch_regs[i].dirty>>s1l)&(branch_regs[i].is32>>rs2[i])&1)
4407 emit_loadreg(rs2[i],s1l);
4410 if((branch_regs[i].dirty>>s2l)&(branch_regs[i].is32>>rs2[i])&1)
4411 emit_loadreg(rs2[i],s2l);
4414 int addr=-1,alt=-1,ntaddr=-1;
4417 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4418 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4419 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4427 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4428 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4429 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4435 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
4439 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
4440 (branch_regs[i].regmap[hr]&63)!=rs1[i] &&
4441 (branch_regs[i].regmap[hr]&63)!=rs2[i] )
4447 assert(hr<HOST_REGS);
4449 if((opcode[i]&0x2f)==4) // BEQ
4451 #ifdef HAVE_CMOV_IMM
4453 if(s2l>=0) emit_cmp(s1l,s2l);
4454 else emit_test(s1l,s1l);
4455 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
4460 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4462 if(s2h>=0) emit_cmp(s1h,s2h);
4463 else emit_test(s1h,s1h);
4464 emit_cmovne_reg(alt,addr);
4466 if(s2l>=0) emit_cmp(s1l,s2l);
4467 else emit_test(s1l,s1l);
4468 emit_cmovne_reg(alt,addr);
4471 if((opcode[i]&0x2f)==5) // BNE
4473 #ifdef HAVE_CMOV_IMM
4475 if(s2l>=0) emit_cmp(s1l,s2l);
4476 else emit_test(s1l,s1l);
4477 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
4482 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
4484 if(s2h>=0) emit_cmp(s1h,s2h);
4485 else emit_test(s1h,s1h);
4486 emit_cmovne_reg(alt,addr);
4488 if(s2l>=0) emit_cmp(s1l,s2l);
4489 else emit_test(s1l,s1l);
4490 emit_cmovne_reg(alt,addr);
4493 if((opcode[i]&0x2f)==6) // BLEZ
4495 //emit_movimm(ba[i],alt);
4496 //emit_movimm(start+i*4+8,addr);
4497 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4499 if(s1h>=0) emit_mov(addr,ntaddr);
4500 emit_cmovl_reg(alt,addr);
4503 emit_cmovne_reg(ntaddr,addr);
4504 emit_cmovs_reg(alt,addr);
4507 if((opcode[i]&0x2f)==7) // BGTZ
4509 //emit_movimm(ba[i],addr);
4510 //emit_movimm(start+i*4+8,ntaddr);
4511 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
4513 if(s1h>=0) emit_mov(addr,alt);
4514 emit_cmovl_reg(ntaddr,addr);
4517 emit_cmovne_reg(alt,addr);
4518 emit_cmovs_reg(ntaddr,addr);
4521 if((opcode[i]==1)&&(opcode2[i]&0x2D)==0) // BLTZ
4523 //emit_movimm(ba[i],alt);
4524 //emit_movimm(start+i*4+8,addr);
4525 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4526 if(s1h>=0) emit_test(s1h,s1h);
4527 else emit_test(s1l,s1l);
4528 emit_cmovs_reg(alt,addr);
4530 if((opcode[i]==1)&&(opcode2[i]&0x2D)==1) // BGEZ
4532 //emit_movimm(ba[i],addr);
4533 //emit_movimm(start+i*4+8,alt);
4534 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4535 if(s1h>=0) emit_test(s1h,s1h);
4536 else emit_test(s1l,s1l);
4537 emit_cmovs_reg(alt,addr);
4539 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
4540 if(source[i]&0x10000) // BC1T
4542 //emit_movimm(ba[i],alt);
4543 //emit_movimm(start+i*4+8,addr);
4544 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
4545 emit_testimm(s1l,0x800000);
4546 emit_cmovne_reg(alt,addr);
4550 //emit_movimm(ba[i],addr);
4551 //emit_movimm(start+i*4+8,alt);
4552 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
4553 emit_testimm(s1l,0x800000);
4554 emit_cmovne_reg(alt,addr);
4557 emit_writeword(addr,(int)&pcaddr);
4562 int r=get_reg(branch_regs[i].regmap,rs1[i]);
4563 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4564 r=get_reg(branch_regs[i].regmap,RTEMP);
4566 emit_writeword(r,(int)&pcaddr);
4568 else {SysPrintf("Unknown branch type in do_ccstub\n");exit(1);}
4570 // Update cycle count
4571 assert(branch_regs[i].regmap[HOST_CCREG]==CCREG||branch_regs[i].regmap[HOST_CCREG]==-1);
4572 if(stubs[n].a) emit_addimm(HOST_CCREG,CLOCK_ADJUST((int)stubs[n].a),HOST_CCREG);
4573 emit_call((int)cc_interrupt);
4574 if(stubs[n].a) emit_addimm(HOST_CCREG,-CLOCK_ADJUST((int)stubs[n].a),HOST_CCREG);
4575 if(stubs[n].d==TAKEN) {
4576 if(internal_branch(branch_regs[i].is32,ba[i]))
4577 load_needed_regs(branch_regs[i].regmap,regs[(ba[i]-start)>>2].regmap_entry);
4578 else if(itype[i]==RJUMP) {
4579 if(get_reg(branch_regs[i].regmap,RTEMP)>=0)
4580 emit_readword((int)&pcaddr,get_reg(branch_regs[i].regmap,RTEMP));
4582 emit_loadreg(rs1[i],get_reg(branch_regs[i].regmap,rs1[i]));
4584 }else if(stubs[n].d==NOTTAKEN) {
4585 if(i<slen-2) load_needed_regs(branch_regs[i].regmap,regmap_pre[i+2]);
4586 else load_all_regs(branch_regs[i].regmap);
4587 }else if(stubs[n].d==NULLDS) {
4588 // Delay slot instruction is nullified ("likely" branch)
4589 if(i<slen-2) load_needed_regs(regs[i].regmap,regmap_pre[i+2]);
4590 else load_all_regs(regs[i].regmap);
4592 load_all_regs(branch_regs[i].regmap);
4594 emit_jmp(stubs[n].retaddr);
4597 static void add_to_linker(int addr,int target,int ext)
4599 link_addr[linkcount][0]=addr;
4600 link_addr[linkcount][1]=target;
4601 link_addr[linkcount][2]=ext;
4605 static void ujump_assemble_write_ra(int i)
4608 unsigned int return_address;
4609 rt=get_reg(branch_regs[i].regmap,31);
4610 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4612 return_address=start+i*4+8;
4615 if(internal_branch(branch_regs[i].is32,return_address)&&rt1[i+1]!=31) {
4616 int temp=-1; // note: must be ds-safe
4620 if(temp>=0) do_miniht_insert(return_address,rt,temp);
4621 else emit_movimm(return_address,rt);
4629 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table_get(return_address),temp);
4632 emit_movimm(return_address,rt); // PC into link register
4634 emit_prefetch(hash_table_get(return_address));
4640 void ujump_assemble(int i,struct regstat *i_regs)
4643 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4644 address_generation(i+1,i_regs,regs[i].regmap_entry);
4646 int temp=get_reg(branch_regs[i].regmap,PTEMP);
4647 if(rt1[i]==31&&temp>=0)
4649 signed char *i_regmap=i_regs->regmap;
4650 int return_address=start+i*4+8;
4651 if(get_reg(branch_regs[i].regmap,31)>0)
4652 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table_get(return_address),temp);
4655 if(rt1[i]==31&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4656 ujump_assemble_write_ra(i); // writeback ra for DS
4659 ds_assemble(i+1,i_regs);
4660 uint64_t bc_unneeded=branch_regs[i].u;
4661 uint64_t bc_unneeded_upper=branch_regs[i].uu;
4662 bc_unneeded|=1|(1LL<<rt1[i]);
4663 bc_unneeded_upper|=1|(1LL<<rt1[i]);
4664 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4665 bc_unneeded,bc_unneeded_upper);
4666 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
4667 if(!ra_done&&rt1[i]==31)
4668 ujump_assemble_write_ra(i);
4670 cc=get_reg(branch_regs[i].regmap,CCREG);
4671 assert(cc==HOST_CCREG);
4672 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4674 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4676 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
4677 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4678 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4679 if(internal_branch(branch_regs[i].is32,ba[i]))
4680 assem_debug("branch: internal\n");
4682 assem_debug("branch: external\n");
4683 if(internal_branch(branch_regs[i].is32,ba[i])&&is_ds[(ba[i]-start)>>2]) {
4684 ds_assemble_entry(i);
4687 add_to_linker((int)out,ba[i],internal_branch(branch_regs[i].is32,ba[i]));
4692 static void rjump_assemble_write_ra(int i)
4694 int rt,return_address;
4695 assert(rt1[i+1]!=rt1[i]);
4696 assert(rt2[i+1]!=rt1[i]);
4697 rt=get_reg(branch_regs[i].regmap,rt1[i]);
4698 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4700 return_address=start+i*4+8;
4704 if(i_regmap[temp]!=PTEMP) emit_movimm((int)hash_table_get(return_address),temp);
4707 emit_movimm(return_address,rt); // PC into link register
4709 emit_prefetch(hash_table_get(return_address));
4713 void rjump_assemble(int i,struct regstat *i_regs)
4718 rs=get_reg(branch_regs[i].regmap,rs1[i]);
4720 if(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]) {
4721 // Delay slot abuse, make a copy of the branch address register
4722 temp=get_reg(branch_regs[i].regmap,RTEMP);
4724 assert(regs[i].regmap[temp]==RTEMP);
4728 address_generation(i+1,i_regs,regs[i].regmap_entry);
4732 if((temp=get_reg(branch_regs[i].regmap,PTEMP))>=0) {
4733 signed char *i_regmap=i_regs->regmap;
4734 int return_address=start+i*4+8;
4735 if(i_regmap[temp]==PTEMP) emit_movimm((int)hash_table_get(return_address),temp);
4741 int rh=get_reg(regs[i].regmap,RHASH);
4742 if(rh>=0) do_preload_rhash(rh);
4745 if(rt1[i]!=0&&(rt1[i]==rs1[i+1]||rt1[i]==rs2[i+1])) {
4746 rjump_assemble_write_ra(i);
4749 ds_assemble(i+1,i_regs);
4750 uint64_t bc_unneeded=branch_regs[i].u;
4751 uint64_t bc_unneeded_upper=branch_regs[i].uu;
4752 bc_unneeded|=1|(1LL<<rt1[i]);
4753 bc_unneeded_upper|=1|(1LL<<rt1[i]);
4754 bc_unneeded&=~(1LL<<rs1[i]);
4755 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4756 bc_unneeded,bc_unneeded_upper);
4757 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],CCREG);
4758 if(!ra_done&&rt1[i]!=0)
4759 rjump_assemble_write_ra(i);
4760 cc=get_reg(branch_regs[i].regmap,CCREG);
4761 assert(cc==HOST_CCREG);
4764 int rh=get_reg(branch_regs[i].regmap,RHASH);
4765 int ht=get_reg(branch_regs[i].regmap,RHTBL);
4767 if(regs[i].regmap[rh]!=RHASH) do_preload_rhash(rh);
4768 do_preload_rhtbl(ht);
4772 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
4773 #ifdef DESTRUCTIVE_WRITEBACK
4774 if((branch_regs[i].dirty>>rs)&(branch_regs[i].is32>>rs1[i])&1) {
4775 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
4776 emit_loadreg(rs1[i],rs);
4781 if(rt1[i]==31&&temp>=0) emit_prefetchreg(temp);
4785 do_miniht_load(ht,rh);
4788 //do_cc(i,branch_regs[i].regmap,&adj,-1,TAKEN);
4789 //if(adj) emit_addimm(cc,2*(ccadj[i]+2-adj),cc); // ??? - Shouldn't happen
4791 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
4792 add_stub(CC_STUB,out,jump_vaddr_reg[rs],0,i,-1,TAKEN,0);
4793 if(itype[i+1]==COP0&&(source[i+1]&0x3f)==0x10)
4794 // special case for RFE
4798 //load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,-1);
4801 do_miniht_jump(rs,rh,ht);
4806 emit_jmp(jump_vaddr_reg[rs]);
4808 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4809 if(rt1[i]!=31&&i<slen-2&&(((u_int)out)&7)) emit_mov(13,13);
4813 void cjump_assemble(int i,struct regstat *i_regs)
4815 signed char *i_regmap=i_regs->regmap;
4818 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4819 assem_debug("match=%d\n",match);
4820 int s1h,s1l,s2h,s2l;
4821 int prev_cop1_usable=cop1_usable;
4822 int unconditional=0,nop=0;
4825 int internal=internal_branch(branch_regs[i].is32,ba[i]);
4826 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
4827 if(!match) invert=1;
4828 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4829 if(i>(ba[i]-start)>>2) invert=1;
4833 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
4834 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
4835 s2l=get_reg(branch_regs[i].regmap,rs2[i]);
4836 s2h=get_reg(branch_regs[i].regmap,rs2[i]|64);
4839 s1l=get_reg(i_regmap,rs1[i]);
4840 s1h=get_reg(i_regmap,rs1[i]|64);
4841 s2l=get_reg(i_regmap,rs2[i]);
4842 s2h=get_reg(i_regmap,rs2[i]|64);
4844 if(rs1[i]==0&&rs2[i]==0)
4846 if(opcode[i]&1) nop=1;
4847 else unconditional=1;
4848 //assert(opcode[i]!=5);
4849 //assert(opcode[i]!=7);
4850 //assert(opcode[i]!=0x15);
4851 //assert(opcode[i]!=0x17);
4857 only32=(regs[i].was32>>rs2[i])&1;
4862 only32=(regs[i].was32>>rs1[i])&1;
4865 only32=(regs[i].was32>>rs1[i])&(regs[i].was32>>rs2[i])&1;
4869 // Out of order execution (delay slot first)
4871 address_generation(i+1,i_regs,regs[i].regmap_entry);
4872 ds_assemble(i+1,i_regs);
4874 uint64_t bc_unneeded=branch_regs[i].u;
4875 uint64_t bc_unneeded_upper=branch_regs[i].uu;
4876 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
4877 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
4879 bc_unneeded_upper|=1;
4880 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
4881 bc_unneeded,bc_unneeded_upper);
4882 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
4883 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
4884 cc=get_reg(branch_regs[i].regmap,CCREG);
4885 assert(cc==HOST_CCREG);
4887 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4888 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
4889 //assem_debug("cycle count (adj)\n");
4891 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
4892 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
4893 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4894 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
4896 assem_debug("branch: internal\n");
4898 assem_debug("branch: external\n");
4899 if(internal&&is_ds[(ba[i]-start)>>2]) {
4900 ds_assemble_entry(i);
4903 add_to_linker((int)out,ba[i],internal);
4906 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
4907 if(((u_int)out)&7) emit_addnop(0);
4912 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
4915 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
4918 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
4919 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
4920 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
4924 if(opcode[i]==4) // BEQ
4926 if(s2h>=0) emit_cmp(s1h,s2h);
4927 else emit_test(s1h,s1h);
4931 if(opcode[i]==5) // BNE
4933 if(s2h>=0) emit_cmp(s1h,s2h);
4934 else emit_test(s1h,s1h);
4935 if(invert) taken=out;
4936 else add_to_linker((int)out,ba[i],internal);
4939 if(opcode[i]==6) // BLEZ
4942 if(invert) taken=out;
4943 else add_to_linker((int)out,ba[i],internal);
4948 if(opcode[i]==7) // BGTZ
4953 if(invert) taken=out;
4954 else add_to_linker((int)out,ba[i],internal);
4959 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
4961 if(opcode[i]==4) // BEQ
4963 if(s2l>=0) emit_cmp(s1l,s2l);
4964 else emit_test(s1l,s1l);
4969 add_to_linker((int)out,ba[i],internal);
4973 if(opcode[i]==5) // BNE
4975 if(s2l>=0) emit_cmp(s1l,s2l);
4976 else emit_test(s1l,s1l);
4981 add_to_linker((int)out,ba[i],internal);
4985 if(opcode[i]==6) // BLEZ
4992 add_to_linker((int)out,ba[i],internal);
4996 if(opcode[i]==7) // BGTZ
5003 add_to_linker((int)out,ba[i],internal);
5008 if(taken) set_jump_target(taken, out);
5009 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5010 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5012 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5013 add_to_linker((int)out,ba[i],internal);
5016 add_to_linker((int)out,ba[i],internal*2);
5022 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5023 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5024 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5026 assem_debug("branch: internal\n");
5028 assem_debug("branch: external\n");
5029 if(internal&&is_ds[(ba[i]-start)>>2]) {
5030 ds_assemble_entry(i);
5033 add_to_linker((int)out,ba[i],internal);
5037 set_jump_target(nottaken, out);
5040 if(nottaken1) set_jump_target(nottaken1, out);
5042 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5044 } // (!unconditional)
5048 // In-order execution (branch first)
5049 //if(likely[i]) printf("IOL\n");
5052 void *taken = NULL, *nottaken = NULL, *nottaken1 = NULL;
5053 if(!unconditional&&!nop) {
5057 if((opcode[i]&0x2f)==4) // BEQ
5059 if(s2h>=0) emit_cmp(s1h,s2h);
5060 else emit_test(s1h,s1h);
5064 if((opcode[i]&0x2f)==5) // BNE
5066 if(s2h>=0) emit_cmp(s1h,s2h);
5067 else emit_test(s1h,s1h);
5071 if((opcode[i]&0x2f)==6) // BLEZ
5079 if((opcode[i]&0x2f)==7) // BGTZ
5089 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5091 if((opcode[i]&0x2f)==4) // BEQ
5093 if(s2l>=0) emit_cmp(s1l,s2l);
5094 else emit_test(s1l,s1l);
5098 if((opcode[i]&0x2f)==5) // BNE
5100 if(s2l>=0) emit_cmp(s1l,s2l);
5101 else emit_test(s1l,s1l);
5105 if((opcode[i]&0x2f)==6) // BLEZ
5111 if((opcode[i]&0x2f)==7) // BGTZ
5117 } // if(!unconditional)
5119 uint64_t ds_unneeded=branch_regs[i].u;
5120 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5121 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5122 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5123 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5125 ds_unneeded_upper|=1;
5128 if(taken) set_jump_target(taken, out);
5129 assem_debug("1:\n");
5130 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5131 ds_unneeded,ds_unneeded_upper);
5133 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5134 address_generation(i+1,&branch_regs[i],0);
5135 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5136 ds_assemble(i+1,&branch_regs[i]);
5137 cc=get_reg(branch_regs[i].regmap,CCREG);
5139 emit_loadreg(CCREG,cc=HOST_CCREG);
5140 // CHECK: Is the following instruction (fall thru) allocated ok?
5142 assert(cc==HOST_CCREG);
5143 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5144 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5145 assem_debug("cycle count (adj)\n");
5146 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5147 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5149 assem_debug("branch: internal\n");
5151 assem_debug("branch: external\n");
5152 if(internal&&is_ds[(ba[i]-start)>>2]) {
5153 ds_assemble_entry(i);
5156 add_to_linker((int)out,ba[i],internal);
5161 cop1_usable=prev_cop1_usable;
5162 if(!unconditional) {
5163 if(nottaken1) set_jump_target(nottaken1, out);
5164 set_jump_target(nottaken, out);
5165 assem_debug("2:\n");
5167 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5168 ds_unneeded,ds_unneeded_upper);
5169 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5170 address_generation(i+1,&branch_regs[i],0);
5171 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5172 ds_assemble(i+1,&branch_regs[i]);
5174 cc=get_reg(branch_regs[i].regmap,CCREG);
5175 if(cc==-1&&!likely[i]) {
5176 // Cycle count isn't in a register, temporarily load it then write it out
5177 emit_loadreg(CCREG,HOST_CCREG);
5178 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5181 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5182 emit_storereg(CCREG,HOST_CCREG);
5185 cc=get_reg(i_regmap,CCREG);
5186 assert(cc==HOST_CCREG);
5187 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5190 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5196 void sjump_assemble(int i,struct regstat *i_regs)
5198 signed char *i_regmap=i_regs->regmap;
5201 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5202 assem_debug("smatch=%d\n",match);
5204 int prev_cop1_usable=cop1_usable;
5205 int unconditional=0,nevertaken=0;
5208 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5209 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5210 if(!match) invert=1;
5211 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5212 if(i>(ba[i]-start)>>2) invert=1;
5215 //if(opcode2[i]>=0x10) return; // FIXME (BxxZAL)
5216 //assert(opcode2[i]<0x10||rs1[i]==0); // FIXME (BxxZAL)
5219 s1l=get_reg(branch_regs[i].regmap,rs1[i]);
5220 s1h=get_reg(branch_regs[i].regmap,rs1[i]|64);
5223 s1l=get_reg(i_regmap,rs1[i]);
5224 s1h=get_reg(i_regmap,rs1[i]|64);
5228 if(opcode2[i]&1) unconditional=1;
5230 // These are never taken (r0 is never less than zero)
5231 //assert(opcode2[i]!=0);
5232 //assert(opcode2[i]!=2);
5233 //assert(opcode2[i]!=0x10);
5234 //assert(opcode2[i]!=0x12);
5237 only32=(regs[i].was32>>rs1[i])&1;
5241 // Out of order execution (delay slot first)
5243 address_generation(i+1,i_regs,regs[i].regmap_entry);
5244 ds_assemble(i+1,i_regs);
5246 uint64_t bc_unneeded=branch_regs[i].u;
5247 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5248 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5249 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5251 bc_unneeded_upper|=1;
5252 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5253 bc_unneeded,bc_unneeded_upper);
5254 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5255 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5257 int rt,return_address;
5258 rt=get_reg(branch_regs[i].regmap,31);
5259 assem_debug("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5261 // Save the PC even if the branch is not taken
5262 return_address=start+i*4+8;
5263 emit_movimm(return_address,rt); // PC into link register
5265 if(!nevertaken) emit_prefetch(hash_table_get(return_address));
5269 cc=get_reg(branch_regs[i].regmap,CCREG);
5270 assert(cc==HOST_CCREG);
5272 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5273 //do_cc(i,branch_regs[i].regmap,&adj,unconditional?ba[i]:-1,unconditional);
5274 assem_debug("cycle count (adj)\n");
5276 do_cc(i,branch_regs[i].regmap,&adj,ba[i],TAKEN,0);
5277 if(i!=(ba[i]-start)>>2 || source[i+1]!=0) {
5278 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5279 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5281 assem_debug("branch: internal\n");
5283 assem_debug("branch: external\n");
5284 if(internal&&is_ds[(ba[i]-start)>>2]) {
5285 ds_assemble_entry(i);
5288 add_to_linker((int)out,ba[i],internal);
5291 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5292 if(((u_int)out)&7) emit_addnop(0);
5296 else if(nevertaken) {
5297 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5300 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5303 void *nottaken = NULL;
5304 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5305 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5309 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5316 add_to_linker((int)out,ba[i],internal);
5320 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5327 add_to_linker((int)out,ba[i],internal);
5335 if((opcode2[i]&0xf)==0) // BLTZ/BLTZAL
5342 add_to_linker((int)out,ba[i],internal);
5346 if((opcode2[i]&0xf)==1) // BGEZ/BLTZAL
5353 add_to_linker((int)out,ba[i],internal);
5360 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5361 if(match&&(!internal||!is_ds[(ba[i]-start)>>2])) {
5363 emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5364 add_to_linker((int)out,ba[i],internal);
5367 add_to_linker((int)out,ba[i],internal*2);
5373 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5374 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5375 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5377 assem_debug("branch: internal\n");
5379 assem_debug("branch: external\n");
5380 if(internal&&is_ds[(ba[i]-start)>>2]) {
5381 ds_assemble_entry(i);
5384 add_to_linker((int)out,ba[i],internal);
5388 set_jump_target(nottaken, out);
5392 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5394 } // (!unconditional)
5398 // In-order execution (branch first)
5400 void *nottaken = NULL;
5402 int rt,return_address;
5403 rt=get_reg(branch_regs[i].regmap,31);
5405 // Save the PC even if the branch is not taken
5406 return_address=start+i*4+8;
5407 emit_movimm(return_address,rt); // PC into link register
5409 emit_prefetch(hash_table_get(return_address));
5413 if(!unconditional) {
5414 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5418 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5424 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5434 if((opcode2[i]&0x0d)==0) // BLTZ/BLTZL/BLTZAL/BLTZALL
5440 if((opcode2[i]&0x0d)==1) // BGEZ/BGEZL/BGEZAL/BGEZALL
5447 } // if(!unconditional)
5449 uint64_t ds_unneeded=branch_regs[i].u;
5450 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5451 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5452 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5453 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5455 ds_unneeded_upper|=1;
5458 //assem_debug("1:\n");
5459 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5460 ds_unneeded,ds_unneeded_upper);
5462 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5463 address_generation(i+1,&branch_regs[i],0);
5464 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5465 ds_assemble(i+1,&branch_regs[i]);
5466 cc=get_reg(branch_regs[i].regmap,CCREG);
5468 emit_loadreg(CCREG,cc=HOST_CCREG);
5469 // CHECK: Is the following instruction (fall thru) allocated ok?
5471 assert(cc==HOST_CCREG);
5472 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5473 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5474 assem_debug("cycle count (adj)\n");
5475 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5476 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5478 assem_debug("branch: internal\n");
5480 assem_debug("branch: external\n");
5481 if(internal&&is_ds[(ba[i]-start)>>2]) {
5482 ds_assemble_entry(i);
5485 add_to_linker((int)out,ba[i],internal);
5490 cop1_usable=prev_cop1_usable;
5491 if(!unconditional) {
5492 set_jump_target(nottaken, out);
5493 assem_debug("1:\n");
5495 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5496 ds_unneeded,ds_unneeded_upper);
5497 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5498 address_generation(i+1,&branch_regs[i],0);
5499 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5500 ds_assemble(i+1,&branch_regs[i]);
5502 cc=get_reg(branch_regs[i].regmap,CCREG);
5503 if(cc==-1&&!likely[i]) {
5504 // Cycle count isn't in a register, temporarily load it then write it out
5505 emit_loadreg(CCREG,HOST_CCREG);
5506 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5509 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5510 emit_storereg(CCREG,HOST_CCREG);
5513 cc=get_reg(i_regmap,CCREG);
5514 assert(cc==HOST_CCREG);
5515 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5518 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5524 void fjump_assemble(int i,struct regstat *i_regs)
5526 signed char *i_regmap=i_regs->regmap;
5529 match=match_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5530 assem_debug("fmatch=%d\n",match);
5534 int internal=internal_branch(branch_regs[i].is32,ba[i]);
5535 if(i==(ba[i]-start)>>2) assem_debug("idle loop\n");
5536 if(!match) invert=1;
5537 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5538 if(i>(ba[i]-start)>>2) invert=1;
5542 fs=get_reg(branch_regs[i].regmap,FSREG);
5543 address_generation(i+1,i_regs,regs[i].regmap_entry); // Is this okay?
5546 fs=get_reg(i_regmap,FSREG);
5549 // Check cop1 unusable
5551 cs=get_reg(i_regmap,CSREG);
5553 emit_testimm(cs,0x20000000);
5556 add_stub_r(FP_STUB,eaddr,out,i,cs,i_regs,0,0);
5561 // Out of order execution (delay slot first)
5563 ds_assemble(i+1,i_regs);
5565 uint64_t bc_unneeded=branch_regs[i].u;
5566 uint64_t bc_unneeded_upper=branch_regs[i].uu;
5567 bc_unneeded&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
5568 bc_unneeded_upper&=~((1LL<<us1[i])|(1LL<<us2[i]));
5570 bc_unneeded_upper|=1;
5571 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5572 bc_unneeded,bc_unneeded_upper);
5573 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i],rs1[i]);
5574 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5575 cc=get_reg(branch_regs[i].regmap,CCREG);
5576 assert(cc==HOST_CCREG);
5577 do_cc(i,branch_regs[i].regmap,&adj,-1,0,invert);
5578 assem_debug("cycle count (adj)\n");
5580 void *nottaken = NULL;
5581 if(adj&&!invert) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5584 emit_testimm(fs,0x800000);
5585 if(source[i]&0x10000) // BC1T
5591 add_to_linker((int)out,ba[i],internal);
5600 add_to_linker((int)out,ba[i],internal);
5608 if(adj) emit_addimm(cc,-CLOCK_ADJUST(adj),cc);
5609 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
5610 else if(match) emit_addnop(13);
5612 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5613 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5615 assem_debug("branch: internal\n");
5617 assem_debug("branch: external\n");
5618 if(internal&&is_ds[(ba[i]-start)>>2]) {
5619 ds_assemble_entry(i);
5622 add_to_linker((int)out,ba[i],internal);
5625 set_jump_target(nottaken, out);
5629 if(!invert) emit_addimm(cc,CLOCK_ADJUST(adj),cc);
5631 } // (!unconditional)
5635 // In-order execution (branch first)
5637 void *nottaken = NULL;
5639 //printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
5642 emit_testimm(fs,0x800000);
5643 if(source[i]&0x10000) // BC1T
5654 } // if(!unconditional)
5656 uint64_t ds_unneeded=branch_regs[i].u;
5657 uint64_t ds_unneeded_upper=branch_regs[i].uu;
5658 ds_unneeded&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
5659 ds_unneeded_upper&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
5660 if((~ds_unneeded_upper>>rt1[i+1])&1) ds_unneeded_upper&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
5662 ds_unneeded_upper|=1;
5664 //assem_debug("1:\n");
5665 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5666 ds_unneeded,ds_unneeded_upper);
5668 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5669 address_generation(i+1,&branch_regs[i],0);
5670 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,INVCP);
5671 ds_assemble(i+1,&branch_regs[i]);
5672 cc=get_reg(branch_regs[i].regmap,CCREG);
5674 emit_loadreg(CCREG,cc=HOST_CCREG);
5675 // CHECK: Is the following instruction (fall thru) allocated ok?
5677 assert(cc==HOST_CCREG);
5678 store_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5679 do_cc(i,i_regmap,&adj,ba[i],TAKEN,0);
5680 assem_debug("cycle count (adj)\n");
5681 if(adj) emit_addimm(cc,CLOCK_ADJUST(ccadj[i]+2-adj),cc);
5682 load_regs_bt(branch_regs[i].regmap,branch_regs[i].is32,branch_regs[i].dirty,ba[i]);
5684 assem_debug("branch: internal\n");
5686 assem_debug("branch: external\n");
5687 if(internal&&is_ds[(ba[i]-start)>>2]) {
5688 ds_assemble_entry(i);
5691 add_to_linker((int)out,ba[i],internal);
5696 if(1) { // <- FIXME (don't need this)
5697 set_jump_target(nottaken, out);
5698 assem_debug("1:\n");
5700 wb_invalidate(regs[i].regmap,branch_regs[i].regmap,regs[i].dirty,regs[i].is32,
5701 ds_unneeded,ds_unneeded_upper);
5702 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,rs1[i+1],rs2[i+1]);
5703 address_generation(i+1,&branch_regs[i],0);
5704 load_regs(regs[i].regmap,branch_regs[i].regmap,regs[i].was32,CCREG,CCREG);
5705 ds_assemble(i+1,&branch_regs[i]);
5707 cc=get_reg(branch_regs[i].regmap,CCREG);
5708 if(cc==-1&&!likely[i]) {
5709 // Cycle count isn't in a register, temporarily load it then write it out
5710 emit_loadreg(CCREG,HOST_CCREG);
5711 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5714 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,NOTTAKEN,0);
5715 emit_storereg(CCREG,HOST_CCREG);
5718 cc=get_reg(i_regmap,CCREG);
5719 assert(cc==HOST_CCREG);
5720 emit_addimm_and_set_flags(CLOCK_ADJUST(ccadj[i]+2),cc);
5723 add_stub(CC_STUB,jaddr,out,0,i,start+i*4+8,likely[i]?NULLDS:NOTTAKEN,0);
5729 static void pagespan_assemble(int i,struct regstat *i_regs)
5731 int s1l=get_reg(i_regs->regmap,rs1[i]);
5732 int s1h=get_reg(i_regs->regmap,rs1[i]|64);
5733 int s2l=get_reg(i_regs->regmap,rs2[i]);
5734 int s2h=get_reg(i_regs->regmap,rs2[i]|64);
5736 void *nottaken = NULL;
5737 int unconditional=0;
5747 if((i_regs->is32>>rs1[i])&(i_regs->is32>>rs2[i])&1) {
5751 int addr=-1,alt=-1,ntaddr=-1;
5752 if(i_regs->regmap[HOST_BTREG]<0) {addr=HOST_BTREG;}
5756 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG &&
5757 (i_regs->regmap[hr]&63)!=rs1[i] &&
5758 (i_regs->regmap[hr]&63)!=rs2[i] )
5767 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5768 (i_regs->regmap[hr]&63)!=rs1[i] &&
5769 (i_regs->regmap[hr]&63)!=rs2[i] )
5775 if((opcode[i]&0x2E)==6) // BLEZ/BGTZ needs another register
5779 if(hr!=EXCLUDE_REG && hr!=HOST_CCREG && hr!=HOST_BTREG &&
5780 (i_regs->regmap[hr]&63)!=rs1[i] &&
5781 (i_regs->regmap[hr]&63)!=rs2[i] )
5788 assert(hr<HOST_REGS);
5789 if((opcode[i]&0x2e)==4||opcode[i]==0x11) { // BEQ/BNE/BEQL/BNEL/BC1
5790 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
5792 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i]+2),HOST_CCREG);
5793 if(opcode[i]==2) // J
5797 if(opcode[i]==3) // JAL
5800 int rt=get_reg(i_regs->regmap,31);
5801 emit_movimm(start+i*4+8,rt);
5804 if(opcode[i]==0&&(opcode2[i]&0x3E)==8) // JR/JALR
5807 if(opcode2[i]==9) // JALR
5809 int rt=get_reg(i_regs->regmap,rt1[i]);
5810 emit_movimm(start+i*4+8,rt);
5813 if((opcode[i]&0x3f)==4) // BEQ
5820 #ifdef HAVE_CMOV_IMM
5822 if(s2l>=0) emit_cmp(s1l,s2l);
5823 else emit_test(s1l,s1l);
5824 emit_cmov2imm_e_ne_compact(ba[i],start+i*4+8,addr);
5830 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5832 if(s2h>=0) emit_cmp(s1h,s2h);
5833 else emit_test(s1h,s1h);
5834 emit_cmovne_reg(alt,addr);
5836 if(s2l>=0) emit_cmp(s1l,s2l);
5837 else emit_test(s1l,s1l);
5838 emit_cmovne_reg(alt,addr);
5841 if((opcode[i]&0x3f)==5) // BNE
5843 #ifdef HAVE_CMOV_IMM
5845 if(s2l>=0) emit_cmp(s1l,s2l);
5846 else emit_test(s1l,s1l);
5847 emit_cmov2imm_e_ne_compact(start+i*4+8,ba[i],addr);
5853 emit_mov2imm_compact(start+i*4+8,addr,ba[i],alt);
5855 if(s2h>=0) emit_cmp(s1h,s2h);
5856 else emit_test(s1h,s1h);
5857 emit_cmovne_reg(alt,addr);
5859 if(s2l>=0) emit_cmp(s1l,s2l);
5860 else emit_test(s1l,s1l);
5861 emit_cmovne_reg(alt,addr);
5864 if((opcode[i]&0x3f)==0x14) // BEQL
5867 if(s2h>=0) emit_cmp(s1h,s2h);
5868 else emit_test(s1h,s1h);
5872 if(s2l>=0) emit_cmp(s1l,s2l);
5873 else emit_test(s1l,s1l);
5874 if(nottaken) set_jump_target(nottaken, out);
5878 if((opcode[i]&0x3f)==0x15) // BNEL
5881 if(s2h>=0) emit_cmp(s1h,s2h);
5882 else emit_test(s1h,s1h);
5886 if(s2l>=0) emit_cmp(s1l,s2l);
5887 else emit_test(s1l,s1l);
5890 if(taken) set_jump_target(taken, out);
5892 if((opcode[i]&0x3f)==6) // BLEZ
5894 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5896 if(s1h>=0) emit_mov(addr,ntaddr);
5897 emit_cmovl_reg(alt,addr);
5900 emit_cmovne_reg(ntaddr,addr);
5901 emit_cmovs_reg(alt,addr);
5904 if((opcode[i]&0x3f)==7) // BGTZ
5906 emit_mov2imm_compact(ba[i],addr,start+i*4+8,ntaddr);
5908 if(s1h>=0) emit_mov(addr,alt);
5909 emit_cmovl_reg(ntaddr,addr);
5912 emit_cmovne_reg(alt,addr);
5913 emit_cmovs_reg(ntaddr,addr);
5916 if((opcode[i]&0x3f)==0x16) // BLEZL
5918 assert((opcode[i]&0x3f)!=0x16);
5920 if((opcode[i]&0x3f)==0x17) // BGTZL
5922 assert((opcode[i]&0x3f)!=0x17);
5924 assert(opcode[i]!=1); // BLTZ/BGEZ
5926 //FIXME: Check CSREG
5927 if(opcode[i]==0x11 && opcode2[i]==0x08 ) {
5928 if((source[i]&0x30000)==0) // BC1F
5930 emit_mov2imm_compact(ba[i],addr,start+i*4+8,alt);
5931 emit_testimm(s1l,0x800000);
5932 emit_cmovne_reg(alt,addr);
5934 if((source[i]&0x30000)==0x10000) // BC1T
5936 emit_mov2imm_compact(ba[i],alt,start+i*4+8,addr);
5937 emit_testimm(s1l,0x800000);
5938 emit_cmovne_reg(alt,addr);
5940 if((source[i]&0x30000)==0x20000) // BC1FL
5942 emit_testimm(s1l,0x800000);
5946 if((source[i]&0x30000)==0x30000) // BC1TL
5948 emit_testimm(s1l,0x800000);
5954 assert(i_regs->regmap[HOST_CCREG]==CCREG);
5955 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
5956 if(likely[i]||unconditional)
5958 emit_movimm(ba[i],HOST_BTREG);
5960 else if(addr!=HOST_BTREG)
5962 emit_mov(addr,HOST_BTREG);
5964 void *branch_addr=out;
5966 int target_addr=start+i*4+5;
5968 void *compiled_target_addr=check_addr(target_addr);
5969 emit_extjump_ds((int)branch_addr,target_addr);
5970 if(compiled_target_addr) {
5971 set_jump_target(branch_addr, compiled_target_addr);
5972 add_link(target_addr,stub);
5974 else set_jump_target(branch_addr, stub);
5977 set_jump_target(nottaken, out);
5978 wb_dirtys(regs[i].regmap,regs[i].is32,regs[i].dirty);
5979 void *branch_addr=out;
5981 int target_addr=start+i*4+8;
5983 void *compiled_target_addr=check_addr(target_addr);
5984 emit_extjump_ds((int)branch_addr,target_addr);
5985 if(compiled_target_addr) {
5986 set_jump_target(branch_addr, compiled_target_addr);
5987 add_link(target_addr,stub);
5989 else set_jump_target(branch_addr, stub);
5993 // Assemble the delay slot for the above
5994 static void pagespan_ds()
5996 assem_debug("initial delay slot:\n");
5997 u_int vaddr=start+1;
5998 u_int page=get_page(vaddr);
5999 u_int vpage=get_vpage(vaddr);
6000 ll_add(jump_dirty+vpage,vaddr,(void *)out);
6002 ll_add(jump_in+page,vaddr,(void *)out);
6003 assert(regs[0].regmap_entry[HOST_CCREG]==CCREG);
6004 if(regs[0].regmap[HOST_CCREG]!=CCREG)
6005 wb_register(CCREG,regs[0].regmap_entry,regs[0].wasdirty,regs[0].was32);
6006 if(regs[0].regmap[HOST_BTREG]!=BTREG)
6007 emit_writeword(HOST_BTREG,(int)&branch_target);
6008 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,rs1[0],rs2[0]);
6009 address_generation(0,®s[0],regs[0].regmap_entry);
6010 if(itype[0]==STORE||itype[0]==STORELR||(opcode[0]&0x3b)==0x39||(opcode[0]&0x3b)==0x3a)
6011 load_regs(regs[0].regmap_entry,regs[0].regmap,regs[0].was32,INVCP,INVCP);
6016 alu_assemble(0,®s[0]);break;
6018 imm16_assemble(0,®s[0]);break;
6020 shift_assemble(0,®s[0]);break;
6022 shiftimm_assemble(0,®s[0]);break;
6024 load_assemble(0,®s[0]);break;
6026 loadlr_assemble(0,®s[0]);break;
6028 store_assemble(0,®s[0]);break;
6030 storelr_assemble(0,®s[0]);break;
6032 cop0_assemble(0,®s[0]);break;
6034 cop1_assemble(0,®s[0]);break;
6036 c1ls_assemble(0,®s[0]);break;
6038 cop2_assemble(0,®s[0]);break;
6040 c2ls_assemble(0,®s[0]);break;
6042 c2op_assemble(0,®s[0]);break;
6044 fconv_assemble(0,®s[0]);break;
6046 float_assemble(0,®s[0]);break;
6048 fcomp_assemble(0,®s[0]);break;
6050 multdiv_assemble(0,®s[0]);break;
6052 mov_assemble(0,®s[0]);break;
6062 SysPrintf("Jump in the delay slot. This is probably a bug.\n");
6064 int btaddr=get_reg(regs[0].regmap,BTREG);
6066 btaddr=get_reg(regs[0].regmap,-1);
6067 emit_readword((int)&branch_target,btaddr);
6069 assert(btaddr!=HOST_CCREG);
6070 if(regs[0].regmap[HOST_CCREG]!=CCREG) emit_loadreg(CCREG,HOST_CCREG);
6072 emit_movimm(start+4,HOST_TEMPREG);
6073 emit_cmp(btaddr,HOST_TEMPREG);
6075 emit_cmpimm(btaddr,start+4);
6079 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,-1);
6080 emit_jmp(jump_vaddr_reg[btaddr]);
6081 set_jump_target(branch, out);
6082 store_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6083 load_regs_bt(regs[0].regmap,regs[0].is32,regs[0].dirty,start+4);
6086 // Basic liveness analysis for MIPS registers
6087 void unneeded_registers(int istart,int iend,int r)
6090 uint64_t u,uu,gte_u,b,bu,gte_bu;
6091 uint64_t temp_u,temp_uu,temp_gte_u=0;
6093 uint64_t gte_u_unknown=0;
6094 if(new_dynarec_hacks&NDHACK_GTE_UNNEEDED)
6098 gte_u=gte_u_unknown;
6100 u=unneeded_reg[iend+1];
6101 uu=unneeded_reg_upper[iend+1];
6103 gte_u=gte_unneeded[iend+1];
6106 for (i=iend;i>=istart;i--)
6108 //printf("unneeded registers i=%d (%d,%d) r=%d\n",i,istart,iend,r);
6109 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6111 // If subroutine call, flag return address as a possible branch target
6112 if(rt1[i]==31 && i<slen-2) bt[i+2]=1;
6114 if(ba[i]<start || ba[i]>=(start+slen*4))
6116 // Branch out of this block, flush all regs
6119 gte_u=gte_u_unknown;
6121 if(itype[i]==UJUMP&&rt1[i]==31)
6123 uu=u=0x300C00F; // Discard at, v0-v1, t6-t9
6125 if(itype[i]==RJUMP&&rs1[i]==31)
6127 uu=u=0x300C0F3; // Discard at, a0-a3, t6-t9
6129 if(start>0x80000400&&start<0x80000000+RAM_SIZE) {
6130 if(itype[i]==UJUMP&&rt1[i]==31)
6132 //uu=u=0x30300FF0FLL; // Discard at, v0-v1, t0-t9, lo, hi
6133 uu=u=0x300FF0F; // Discard at, v0-v1, t0-t9
6135 if(itype[i]==RJUMP&&rs1[i]==31)
6137 //uu=u=0x30300FFF3LL; // Discard at, a0-a3, t0-t9, lo, hi
6138 uu=u=0x300FFF3; // Discard at, a0-a3, t0-t9
6141 branch_unneeded_reg[i]=u;
6142 branch_unneeded_reg_upper[i]=uu;
6143 // Merge in delay slot
6144 tdep=(~uu>>rt1[i+1])&1;
6145 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6146 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6147 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6148 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6149 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6152 gte_u&=~gte_rs[i+1];
6153 // If branch is "likely" (and conditional)
6154 // then we skip the delay slot on the fall-thru path
6157 u&=unneeded_reg[i+2];
6158 uu&=unneeded_reg_upper[i+2];
6159 gte_u&=gte_unneeded[i+2];
6165 gte_u=gte_u_unknown;
6171 // Internal branch, flag target
6172 bt[(ba[i]-start)>>2]=1;
6173 if(ba[i]<=start+i*4) {
6175 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6177 // Unconditional branch
6181 // Conditional branch (not taken case)
6182 temp_u=unneeded_reg[i+2];
6183 temp_uu=unneeded_reg_upper[i+2];
6184 temp_gte_u&=gte_unneeded[i+2];
6186 // Merge in delay slot
6187 tdep=(~temp_uu>>rt1[i+1])&1;
6188 temp_u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6189 temp_uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6190 temp_u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6191 temp_uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6192 temp_uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6193 temp_u|=1;temp_uu|=1;
6194 temp_gte_u|=gte_rt[i+1];
6195 temp_gte_u&=~gte_rs[i+1];
6196 // If branch is "likely" (and conditional)
6197 // then we skip the delay slot on the fall-thru path
6200 temp_u&=unneeded_reg[i+2];
6201 temp_uu&=unneeded_reg_upper[i+2];
6202 temp_gte_u&=gte_unneeded[i+2];
6208 temp_gte_u=gte_u_unknown;
6211 tdep=(~temp_uu>>rt1[i])&1;
6212 temp_u|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6213 temp_uu|=(1LL<<rt1[i])|(1LL<<rt2[i]);
6214 temp_u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
6215 temp_uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
6216 temp_uu&=~((tdep<<dep1[i])|(tdep<<dep2[i]));
6217 temp_u|=1;temp_uu|=1;
6218 temp_gte_u|=gte_rt[i];
6219 temp_gte_u&=~gte_rs[i];
6220 unneeded_reg[i]=temp_u;
6221 unneeded_reg_upper[i]=temp_uu;
6222 gte_unneeded[i]=temp_gte_u;
6223 // Only go three levels deep. This recursion can take an
6224 // excessive amount of time if there are a lot of nested loops.
6226 unneeded_registers((ba[i]-start)>>2,i-1,r+1);
6228 unneeded_reg[(ba[i]-start)>>2]=1;
6229 unneeded_reg_upper[(ba[i]-start)>>2]=1;
6230 gte_unneeded[(ba[i]-start)>>2]=gte_u_unknown;
6233 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6235 // Unconditional branch
6236 u=unneeded_reg[(ba[i]-start)>>2];
6237 uu=unneeded_reg_upper[(ba[i]-start)>>2];
6238 gte_u=gte_unneeded[(ba[i]-start)>>2];
6239 branch_unneeded_reg[i]=u;
6240 branch_unneeded_reg_upper[i]=uu;
6243 //branch_unneeded_reg[i]=u;
6244 //branch_unneeded_reg_upper[i]=uu;
6245 // Merge in delay slot
6246 tdep=(~uu>>rt1[i+1])&1;
6247 u|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6248 uu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6249 u&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6250 uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6251 uu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6254 gte_u&=~gte_rs[i+1];
6256 // Conditional branch
6257 b=unneeded_reg[(ba[i]-start)>>2];
6258 bu=unneeded_reg_upper[(ba[i]-start)>>2];
6259 gte_bu=gte_unneeded[(ba[i]-start)>>2];
6260 branch_unneeded_reg[i]=b;
6261 branch_unneeded_reg_upper[i]=bu;
6264 //branch_unneeded_reg[i]=b;
6265 //branch_unneeded_reg_upper[i]=bu;
6266 // Branch delay slot
6267 tdep=(~uu>>rt1[i+1])&1;
6268 b|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6269 bu|=(1LL<<rt1[i+1])|(1LL<<rt2[i+1]);
6270 b&=~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
6271 bu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
6272 bu&=~((tdep<<dep1[i+1])|(tdep<<dep2[i+1]));
6274 gte_bu|=gte_rt[i+1];
6275 gte_bu&=~gte_rs[i+1];
6276 // If branch is "likely" then we skip the
6277 // delay slot on the fall-thru path
6283 u&=unneeded_reg[i+2];
6284 uu&=unneeded_reg_upper[i+2];
6285 gte_u&=gte_unneeded[i+2];
6297 branch_unneeded_reg[i]&=unneeded_reg[i+2];
6298 branch_unneeded_reg_upper[i]&=unneeded_reg_upper[i+2];
6299 //branch_unneeded_reg[i]=1;
6300 //branch_unneeded_reg_upper[i]=1;
6302 branch_unneeded_reg[i]=1;
6303 branch_unneeded_reg_upper[i]=1;
6309 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6311 // SYSCALL instruction (software interrupt)
6315 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6317 // ERET instruction (return from interrupt)
6322 tdep=(~uu>>rt1[i])&1;
6323 // Written registers are unneeded
6329 // Accessed registers are needed
6335 if(gte_rs[i]&&rt1[i]&&(unneeded_reg[i+1]&(1ll<<rt1[i])))
6336 gte_u|=gte_rs[i]>e_unneeded[i+1]; // MFC2/CFC2 to dead register, unneeded
6337 // Source-target dependencies
6338 uu&=~(tdep<<dep1[i]);
6339 uu&=~(tdep<<dep2[i]);
6340 // R0 is always unneeded
6344 unneeded_reg_upper[i]=uu;
6345 gte_unneeded[i]=gte_u;
6347 printf("ur (%d,%d) %x: ",istart,iend,start+i*4);
6350 for(r=1;r<=CCREG;r++) {
6351 if((unneeded_reg[i]>>r)&1) {
6352 if(r==HIREG) printf(" HI");
6353 else if(r==LOREG) printf(" LO");
6354 else printf(" r%d",r);
6358 for(r=1;r<=CCREG;r++) {
6359 if(((unneeded_reg_upper[i]&~unneeded_reg[i])>>r)&1) {
6360 if(r==HIREG) printf(" HI");
6361 else if(r==LOREG) printf(" LO");
6362 else printf(" r%d",r);
6367 for (i=iend;i>=istart;i--)
6369 unneeded_reg_upper[i]=branch_unneeded_reg_upper[i]=-1LL;
6373 // Write back dirty registers as soon as we will no longer modify them,
6374 // so that we don't end up with lots of writes at the branches.
6375 void clean_registers(int istart,int iend,int wr)
6379 u_int will_dirty_i,will_dirty_next,temp_will_dirty;
6380 u_int wont_dirty_i,wont_dirty_next,temp_wont_dirty;
6382 will_dirty_i=will_dirty_next=0;
6383 wont_dirty_i=wont_dirty_next=0;
6385 will_dirty_i=will_dirty_next=will_dirty[iend+1];
6386 wont_dirty_i=wont_dirty_next=wont_dirty[iend+1];
6388 for (i=iend;i>=istart;i--)
6390 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6392 if(ba[i]<start || ba[i]>=(start+slen*4))
6394 // Branch out of this block, flush all regs
6395 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6397 // Unconditional branch
6400 // Merge in delay slot (will dirty)
6401 for(r=0;r<HOST_REGS;r++) {
6402 if(r!=EXCLUDE_REG) {
6403 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6404 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6405 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6406 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6407 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6408 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6409 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6410 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6411 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6412 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6413 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6414 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6415 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6416 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6422 // Conditional branch
6424 wont_dirty_i=wont_dirty_next;
6425 // Merge in delay slot (will dirty)
6426 for(r=0;r<HOST_REGS;r++) {
6427 if(r!=EXCLUDE_REG) {
6429 // Might not dirty if likely branch is not taken
6430 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6431 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6432 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6433 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6434 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6435 if(branch_regs[i].regmap[r]==0) will_dirty_i&=~(1<<r);
6436 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6437 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6438 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6439 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6440 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6441 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6442 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6443 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6448 // Merge in delay slot (wont dirty)
6449 for(r=0;r<HOST_REGS;r++) {
6450 if(r!=EXCLUDE_REG) {
6451 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6452 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6453 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6454 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6455 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6456 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6457 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6458 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6459 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6460 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6464 #ifndef DESTRUCTIVE_WRITEBACK
6465 branch_regs[i].dirty&=wont_dirty_i;
6467 branch_regs[i].dirty|=will_dirty_i;
6473 if(ba[i]<=start+i*4) {
6475 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6477 // Unconditional branch
6480 // Merge in delay slot (will dirty)
6481 for(r=0;r<HOST_REGS;r++) {
6482 if(r!=EXCLUDE_REG) {
6483 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6484 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6485 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6486 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6487 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6488 if(branch_regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6489 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6490 if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6491 if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6492 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6493 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6494 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6495 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6496 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6500 // Conditional branch (not taken case)
6501 temp_will_dirty=will_dirty_next;
6502 temp_wont_dirty=wont_dirty_next;
6503 // Merge in delay slot (will dirty)
6504 for(r=0;r<HOST_REGS;r++) {
6505 if(r!=EXCLUDE_REG) {
6507 // Will not dirty if likely branch is not taken
6508 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6509 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6510 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6511 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6512 if((branch_regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6513 if(branch_regs[i].regmap[r]==0) temp_will_dirty&=~(1<<r);
6514 if(branch_regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6515 //if((regs[i].regmap[r]&63)==rt1[i]) temp_will_dirty|=1<<r;
6516 //if((regs[i].regmap[r]&63)==rt2[i]) temp_will_dirty|=1<<r;
6517 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_will_dirty|=1<<r;
6518 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_will_dirty|=1<<r;
6519 if((regs[i].regmap[r]&63)>33) temp_will_dirty&=~(1<<r);
6520 if(regs[i].regmap[r]<=0) temp_will_dirty&=~(1<<r);
6521 if(regs[i].regmap[r]==CCREG) temp_will_dirty|=1<<r;
6526 // Merge in delay slot (wont dirty)
6527 for(r=0;r<HOST_REGS;r++) {
6528 if(r!=EXCLUDE_REG) {
6529 if((regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6530 if((regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6531 if((regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6532 if((regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6533 if(regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6534 if((branch_regs[i].regmap[r]&63)==rt1[i]) temp_wont_dirty|=1<<r;
6535 if((branch_regs[i].regmap[r]&63)==rt2[i]) temp_wont_dirty|=1<<r;
6536 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) temp_wont_dirty|=1<<r;
6537 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) temp_wont_dirty|=1<<r;
6538 if(branch_regs[i].regmap[r]==CCREG) temp_wont_dirty|=1<<r;
6541 // Deal with changed mappings
6543 for(r=0;r<HOST_REGS;r++) {
6544 if(r!=EXCLUDE_REG) {
6545 if(regs[i].regmap[r]!=regmap_pre[i][r]) {
6546 temp_will_dirty&=~(1<<r);
6547 temp_wont_dirty&=~(1<<r);
6548 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6549 temp_will_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6550 temp_wont_dirty|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6552 temp_will_dirty|=1<<r;
6553 temp_wont_dirty|=1<<r;
6560 will_dirty[i]=temp_will_dirty;
6561 wont_dirty[i]=temp_wont_dirty;
6562 clean_registers((ba[i]-start)>>2,i-1,0);
6564 // Limit recursion. It can take an excessive amount
6565 // of time if there are a lot of nested loops.
6566 will_dirty[(ba[i]-start)>>2]=0;
6567 wont_dirty[(ba[i]-start)>>2]=-1;
6572 if(itype[i]==RJUMP||itype[i]==UJUMP||(source[i]>>16)==0x1000)
6574 // Unconditional branch
6577 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6578 for(r=0;r<HOST_REGS;r++) {
6579 if(r!=EXCLUDE_REG) {
6580 if(branch_regs[i].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6581 will_dirty_i|=will_dirty[(ba[i]-start)>>2]&(1<<r);
6582 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6584 if(branch_regs[i].regmap[r]>=0) {
6585 will_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6586 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(branch_regs[i].regmap[r]&63))&1)<<r;
6591 // Merge in delay slot
6592 for(r=0;r<HOST_REGS;r++) {
6593 if(r!=EXCLUDE_REG) {
6594 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6595 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6596 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6597 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6598 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6599 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6600 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6601 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6602 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6603 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6604 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6605 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6606 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6607 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6611 // Conditional branch
6612 will_dirty_i=will_dirty_next;
6613 wont_dirty_i=wont_dirty_next;
6614 //if(ba[i]>start+i*4) { // Disable recursion (for debugging)
6615 for(r=0;r<HOST_REGS;r++) {
6616 if(r!=EXCLUDE_REG) {
6617 signed char target_reg=branch_regs[i].regmap[r];
6618 if(target_reg==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6619 will_dirty_i&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6620 wont_dirty_i|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6622 else if(target_reg>=0) {
6623 will_dirty_i&=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6624 wont_dirty_i|=((unneeded_reg[(ba[i]-start)>>2]>>(target_reg&63))&1)<<r;
6626 // Treat delay slot as part of branch too
6627 /*if(regs[i+1].regmap[r]==regs[(ba[i]-start)>>2].regmap_entry[r]) {
6628 will_dirty[i+1]&=will_dirty[(ba[i]-start)>>2]&(1<<r);
6629 wont_dirty[i+1]|=wont_dirty[(ba[i]-start)>>2]&(1<<r);
6633 will_dirty[i+1]&=~(1<<r);
6638 // Merge in delay slot
6639 for(r=0;r<HOST_REGS;r++) {
6640 if(r!=EXCLUDE_REG) {
6642 // Might not dirty if likely branch is not taken
6643 if((branch_regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6644 if((branch_regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6645 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6646 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6647 if((branch_regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6648 if(branch_regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6649 if(branch_regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6650 //if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6651 //if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6652 if((regs[i].regmap[r]&63)==rt1[i+1]) will_dirty_i|=1<<r;
6653 if((regs[i].regmap[r]&63)==rt2[i+1]) will_dirty_i|=1<<r;
6654 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6655 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6656 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6661 // Merge in delay slot (won't dirty)
6662 for(r=0;r<HOST_REGS;r++) {
6663 if(r!=EXCLUDE_REG) {
6664 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6665 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6666 if((regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6667 if((regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6668 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6669 if((branch_regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6670 if((branch_regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6671 if((branch_regs[i].regmap[r]&63)==rt1[i+1]) wont_dirty_i|=1<<r;
6672 if((branch_regs[i].regmap[r]&63)==rt2[i+1]) wont_dirty_i|=1<<r;
6673 if(branch_regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6677 #ifndef DESTRUCTIVE_WRITEBACK
6678 branch_regs[i].dirty&=wont_dirty_i;
6680 branch_regs[i].dirty|=will_dirty_i;
6685 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
6687 // SYSCALL instruction (software interrupt)
6691 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
6693 // ERET instruction (return from interrupt)
6697 will_dirty_next=will_dirty_i;
6698 wont_dirty_next=wont_dirty_i;
6699 for(r=0;r<HOST_REGS;r++) {
6700 if(r!=EXCLUDE_REG) {
6701 if((regs[i].regmap[r]&63)==rt1[i]) will_dirty_i|=1<<r;
6702 if((regs[i].regmap[r]&63)==rt2[i]) will_dirty_i|=1<<r;
6703 if((regs[i].regmap[r]&63)>33) will_dirty_i&=~(1<<r);
6704 if(regs[i].regmap[r]<=0) will_dirty_i&=~(1<<r);
6705 if(regs[i].regmap[r]==CCREG) will_dirty_i|=1<<r;
6706 if((regs[i].regmap[r]&63)==rt1[i]) wont_dirty_i|=1<<r;
6707 if((regs[i].regmap[r]&63)==rt2[i]) wont_dirty_i|=1<<r;
6708 if(regs[i].regmap[r]==CCREG) wont_dirty_i|=1<<r;
6710 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=FJUMP)
6712 // Don't store a register immediately after writing it,
6713 // may prevent dual-issue.
6714 if((regs[i].regmap[r]&63)==rt1[i-1]) wont_dirty_i|=1<<r;
6715 if((regs[i].regmap[r]&63)==rt2[i-1]) wont_dirty_i|=1<<r;
6721 will_dirty[i]=will_dirty_i;
6722 wont_dirty[i]=wont_dirty_i;
6723 // Mark registers that won't be dirtied as not dirty
6725 /*printf("wr (%d,%d) %x will:",istart,iend,start+i*4);
6726 for(r=0;r<HOST_REGS;r++) {
6727 if((will_dirty_i>>r)&1) {
6733 //if(i==istart||(itype[i-1]!=RJUMP&&itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=FJUMP)) {
6734 regs[i].dirty|=will_dirty_i;
6735 #ifndef DESTRUCTIVE_WRITEBACK
6736 regs[i].dirty&=wont_dirty_i;
6737 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
6739 if(i<iend-1&&itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
6740 for(r=0;r<HOST_REGS;r++) {
6741 if(r!=EXCLUDE_REG) {
6742 if(regs[i].regmap[r]==regmap_pre[i+2][r]) {
6743 regs[i+2].wasdirty&=wont_dirty_i|~(1<<r);
6744 }else {/*printf("i: %x (%d) mismatch(+2): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6752 for(r=0;r<HOST_REGS;r++) {
6753 if(r!=EXCLUDE_REG) {
6754 if(regs[i].regmap[r]==regmap_pre[i+1][r]) {
6755 regs[i+1].wasdirty&=wont_dirty_i|~(1<<r);
6756 }else {/*printf("i: %x (%d) mismatch(+1): %d\n",start+i*4,i,r);assert(!((wont_dirty_i>>r)&1));*/}
6764 // Deal with changed mappings
6765 temp_will_dirty=will_dirty_i;
6766 temp_wont_dirty=wont_dirty_i;
6767 for(r=0;r<HOST_REGS;r++) {
6768 if(r!=EXCLUDE_REG) {
6770 if(regs[i].regmap[r]==regmap_pre[i][r]) {
6772 #ifndef DESTRUCTIVE_WRITEBACK
6773 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6775 regs[i].wasdirty|=will_dirty_i&(1<<r);
6778 else if(regmap_pre[i][r]>=0&&(nr=get_reg(regs[i].regmap,regmap_pre[i][r]))>=0) {
6779 // Register moved to a different register
6780 will_dirty_i&=~(1<<r);
6781 wont_dirty_i&=~(1<<r);
6782 will_dirty_i|=((temp_will_dirty>>nr)&1)<<r;
6783 wont_dirty_i|=((temp_wont_dirty>>nr)&1)<<r;
6785 #ifndef DESTRUCTIVE_WRITEBACK
6786 regs[i].wasdirty&=wont_dirty_i|~(1<<r);
6788 regs[i].wasdirty|=will_dirty_i&(1<<r);
6792 will_dirty_i&=~(1<<r);
6793 wont_dirty_i&=~(1<<r);
6794 if((regmap_pre[i][r]&63)>0 && (regmap_pre[i][r]&63)<34) {
6795 will_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6796 wont_dirty_i|=((unneeded_reg[i]>>(regmap_pre[i][r]&63))&1)<<r;
6799 /*printf("i: %x (%d) mismatch: %d\n",start+i*4,i,r);assert(!((will_dirty>>r)&1));*/
6809 void disassemble_inst(int i)
6811 if (bt[i]) printf("*"); else printf(" ");
6814 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6816 printf (" %x: %s r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],i?start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14):*ba);break;
6818 printf (" %x: %s r%d,%8x\n",start+i*4,insn[i],rs1[i],start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14));break;
6820 printf (" %x: %s %8x\n",start+i*4,insn[i],ba[i]);break;
6822 if (opcode[i]==0x9&&rt1[i]!=31)
6823 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i]);
6825 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6828 printf (" %x: %s (pagespan) r%d,r%d,%8x\n",start+i*4,insn[i],rs1[i],rs2[i],ba[i]);break;
6830 if(opcode[i]==0xf) //LUI
6831 printf (" %x: %s r%d,%4x0000\n",start+i*4,insn[i],rt1[i],imm[i]&0xffff);
6833 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6837 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6841 printf (" %x: %s r%d,r%d+%x\n",start+i*4,insn[i],rs2[i],rs1[i],imm[i]);
6845 printf (" %x: %s r%d,r%d,r%d\n",start+i*4,insn[i],rt1[i],rs1[i],rs2[i]);
6848 printf (" %x: %s r%d,r%d\n",start+i*4,insn[i],rs1[i],rs2[i]);
6851 printf (" %x: %s r%d,r%d,%d\n",start+i*4,insn[i],rt1[i],rs1[i],imm[i]);
6854 if((opcode2[i]&0x1d)==0x10)
6855 printf (" %x: %s r%d\n",start+i*4,insn[i],rt1[i]);
6856 else if((opcode2[i]&0x1d)==0x11)
6857 printf (" %x: %s r%d\n",start+i*4,insn[i],rs1[i]);
6859 printf (" %x: %s\n",start+i*4,insn[i]);
6863 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC0
6864 else if(opcode2[i]==4)
6865 printf (" %x: %s r%d,cpr0[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC0
6866 else printf (" %x: %s\n",start+i*4,insn[i]);
6870 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC1
6871 else if(opcode2[i]>3)
6872 printf (" %x: %s r%d,cpr1[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC1
6873 else printf (" %x: %s\n",start+i*4,insn[i]);
6877 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rt1[i],(source[i]>>11)&0x1f); // MFC2
6878 else if(opcode2[i]>3)
6879 printf (" %x: %s r%d,cpr2[%d]\n",start+i*4,insn[i],rs1[i],(source[i]>>11)&0x1f); // MTC2
6880 else printf (" %x: %s\n",start+i*4,insn[i]);
6883 printf (" %x: %s cpr1[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
6886 printf (" %x: %s cpr2[%d],r%d+%x\n",start+i*4,insn[i],(source[i]>>16)&0x1f,rs1[i],imm[i]);
6889 printf (" %x: %s (INTCALL)\n",start+i*4,insn[i]);
6892 //printf (" %s %8x\n",insn[i],source[i]);
6893 printf (" %x: %s\n",start+i*4,insn[i]);
6897 static void disassemble_inst(int i) {}
6900 #define DRC_TEST_VAL 0x74657374
6902 static int new_dynarec_test(void)
6904 int (*testfunc)(void) = (void *)out;
6908 beginning = start_block();
6909 emit_movimm(DRC_TEST_VAL,0); // test
6912 end_block(beginning);
6913 SysPrintf("testing if we can run recompiled code..\n");
6915 if (ret == DRC_TEST_VAL)
6916 SysPrintf("test passed.\n");
6918 SysPrintf("test failed: %08x\n", ret);
6919 out=(u_char *)BASE_ADDR;
6920 return ret == DRC_TEST_VAL;
6923 // clear the state completely, instead of just marking
6924 // things invalid like invalidate_all_pages() does
6925 void new_dynarec_clear_full()
6928 out=(u_char *)BASE_ADDR;
6929 memset(invalid_code,1,sizeof(invalid_code));
6930 memset(hash_table,0xff,sizeof(hash_table));
6931 memset(mini_ht,-1,sizeof(mini_ht));
6932 memset(restore_candidate,0,sizeof(restore_candidate));
6933 memset(shadow,0,sizeof(shadow));
6935 expirep=16384; // Expiry pointer, +2 blocks
6936 pending_exception=0;
6939 inv_code_start=inv_code_end=~0;
6941 for(n=0;n<4096;n++) ll_clear(jump_in+n);
6942 for(n=0;n<4096;n++) ll_clear(jump_out+n);
6943 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
6946 void new_dynarec_init()
6948 SysPrintf("Init new dynarec\n");
6950 // allocate/prepare a buffer for translation cache
6951 // see assem_arm.h for some explanation
6952 #if defined(BASE_ADDR_FIXED)
6953 if (mmap (translation_cache, 1 << TARGET_SIZE_2,
6954 PROT_READ | PROT_WRITE | PROT_EXEC,
6955 MAP_PRIVATE | MAP_ANONYMOUS,
6956 -1, 0) != translation_cache) {
6957 SysPrintf("mmap() failed: %s\n", strerror(errno));
6958 SysPrintf("disable BASE_ADDR_FIXED and recompile\n");
6961 #elif defined(BASE_ADDR_DYNAMIC)
6963 sceBlock = sceKernelAllocMemBlockForVM("code", 1 << TARGET_SIZE_2);
6965 SysPrintf("sceKernelAllocMemBlockForVM failed\n");
6966 int ret = sceKernelGetMemBlockBase(sceBlock, (void **)&translation_cache);
6968 SysPrintf("sceKernelGetMemBlockBase failed\n");
6970 translation_cache = mmap (NULL, 1 << TARGET_SIZE_2,
6971 PROT_READ | PROT_WRITE | PROT_EXEC,
6972 MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
6973 if (translation_cache == MAP_FAILED) {
6974 SysPrintf("mmap() failed: %s\n", strerror(errno));
6979 #ifndef NO_WRITE_EXEC
6980 // not all systems allow execute in data segment by default
6981 if (mprotect((void *)BASE_ADDR, 1<<TARGET_SIZE_2, PROT_READ | PROT_WRITE | PROT_EXEC) != 0)
6982 SysPrintf("mprotect() failed: %s\n", strerror(errno));
6985 out=(u_char *)BASE_ADDR;
6986 cycle_multiplier=200;
6987 new_dynarec_clear_full();
6989 // Copy this into local area so we don't have to put it in every literal pool
6990 invc_ptr=invalid_code;
6995 ram_offset=(u_int)rdram-0x80000000;
6998 SysPrintf("warning: RAM is not directly mapped, performance will suffer\n");
7001 void new_dynarec_cleanup()
7004 #if defined(BASE_ADDR_FIXED) || defined(BASE_ADDR_DYNAMIC)
7006 sceKernelFreeMemBlock(sceBlock);
7009 if (munmap ((void *)BASE_ADDR, 1<<TARGET_SIZE_2) < 0)
7010 SysPrintf("munmap() failed\n");
7013 for(n=0;n<4096;n++) ll_clear(jump_in+n);
7014 for(n=0;n<4096;n++) ll_clear(jump_out+n);
7015 for(n=0;n<4096;n++) ll_clear(jump_dirty+n);
7017 if (munmap (ROM_COPY, 67108864) < 0) {SysPrintf("munmap() failed\n");}
7021 static u_int *get_source_start(u_int addr, u_int *limit)
7023 if (addr < 0x00200000 ||
7024 (0xa0000000 <= addr && addr < 0xa0200000)) {
7025 // used for BIOS calls mostly?
7026 *limit = (addr&0xa0000000)|0x00200000;
7027 return (u_int *)((u_int)rdram + (addr&0x1fffff));
7029 else if (!Config.HLE && (
7030 /* (0x9fc00000 <= addr && addr < 0x9fc80000) ||*/
7031 (0xbfc00000 <= addr && addr < 0xbfc80000))) {
7033 *limit = (addr & 0xfff00000) | 0x80000;
7034 return (u_int *)((u_int)psxR + (addr&0x7ffff));
7036 else if (addr >= 0x80000000 && addr < 0x80000000+RAM_SIZE) {
7037 *limit = (addr & 0x80600000) + 0x00200000;
7038 return (u_int *)((u_int)rdram + (addr&0x1fffff));
7043 static u_int scan_for_ret(u_int addr)
7048 mem = get_source_start(addr, &limit);
7052 if (limit > addr + 0x1000)
7053 limit = addr + 0x1000;
7054 for (; addr < limit; addr += 4, mem++) {
7055 if (*mem == 0x03e00008) // jr $ra
7061 struct savestate_block {
7066 static int addr_cmp(const void *p1_, const void *p2_)
7068 const struct savestate_block *p1 = p1_, *p2 = p2_;
7069 return p1->addr - p2->addr;
7072 int new_dynarec_save_blocks(void *save, int size)
7074 struct savestate_block *blocks = save;
7075 int maxcount = size / sizeof(blocks[0]);
7076 struct savestate_block tmp_blocks[1024];
7077 struct ll_entry *head;
7078 int p, s, d, o, bcnt;
7082 for (p = 0; p < ARRAY_SIZE(jump_in); p++) {
7084 for (head = jump_in[p]; head != NULL; head = head->next) {
7085 tmp_blocks[bcnt].addr = head->vaddr;
7086 tmp_blocks[bcnt].regflags = head->reg_sv_flags;
7091 qsort(tmp_blocks, bcnt, sizeof(tmp_blocks[0]), addr_cmp);
7093 addr = tmp_blocks[0].addr;
7094 for (s = d = 0; s < bcnt; s++) {
7095 if (tmp_blocks[s].addr < addr)
7097 if (d == 0 || tmp_blocks[d-1].addr != tmp_blocks[s].addr)
7098 tmp_blocks[d++] = tmp_blocks[s];
7099 addr = scan_for_ret(tmp_blocks[s].addr);
7102 if (o + d > maxcount)
7104 memcpy(&blocks[o], tmp_blocks, d * sizeof(blocks[0]));
7108 return o * sizeof(blocks[0]);
7111 void new_dynarec_load_blocks(const void *save, int size)
7113 const struct savestate_block *blocks = save;
7114 int count = size / sizeof(blocks[0]);
7115 u_int regs_save[32];
7119 get_addr(psxRegs.pc);
7121 // change GPRs for speculation to at least partially work..
7122 memcpy(regs_save, &psxRegs.GPR, sizeof(regs_save));
7123 for (i = 1; i < 32; i++)
7124 psxRegs.GPR.r[i] = 0x80000000;
7126 for (b = 0; b < count; b++) {
7127 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7129 psxRegs.GPR.r[i] = 0x1f800000;
7132 get_addr(blocks[b].addr);
7134 for (f = blocks[b].regflags, i = 0; f; f >>= 1, i++) {
7136 psxRegs.GPR.r[i] = 0x80000000;
7140 memcpy(&psxRegs.GPR, regs_save, sizeof(regs_save));
7143 int new_recompile_block(int addr)
7145 u_int pagelimit = 0;
7146 u_int state_rflags = 0;
7149 assem_debug("NOTCOMPILED: addr = %x -> %p\n", addr, out);
7150 //printf("TRACE: count=%d next=%d (compile %x)\n",Count,next_interupt,addr);
7152 //printf("TRACE: count=%d next=%d (checksum %x)\n",Count,next_interupt,mchecksum());
7153 //printf("fpu mapping=%x enabled=%x\n",(Status & 0x04000000)>>26,(Status & 0x20000000)>>29);
7155 // this is just for speculation
7156 for (i = 1; i < 32; i++) {
7157 if ((psxRegs.GPR.r[i] & 0xffff0000) == 0x1f800000)
7158 state_rflags |= 1 << i;
7161 start = (u_int)addr&~3;
7162 //assert(((u_int)addr&1)==0);
7163 new_dynarec_did_compile=1;
7164 if (Config.HLE && start == 0x80001000) // hlecall
7166 // XXX: is this enough? Maybe check hleSoftCall?
7167 void *beginning=start_block();
7168 u_int page=get_page(start);
7170 invalid_code[start>>12]=0;
7171 emit_movimm(start,0);
7172 emit_writeword(0,(int)&pcaddr);
7173 emit_jmp(new_dyna_leave);
7175 end_block(beginning);
7176 ll_add_flags(jump_in+page,start,state_rflags,(void *)beginning);
7180 source = get_source_start(start, &pagelimit);
7181 if (source == NULL) {
7182 SysPrintf("Compile at bogus memory address: %08x\n", addr);
7186 /* Pass 1: disassemble */
7187 /* Pass 2: register dependencies, branch targets */
7188 /* Pass 3: register allocation */
7189 /* Pass 4: branch dependencies */
7190 /* Pass 5: pre-alloc */
7191 /* Pass 6: optimize clean/dirty state */
7192 /* Pass 7: flag 32-bit registers */
7193 /* Pass 8: assembly */
7194 /* Pass 9: linker */
7195 /* Pass 10: garbage collection / free memory */
7199 unsigned int type,op,op2;
7201 //printf("addr = %x source = %x %x\n", addr,source,source[0]);
7203 /* Pass 1 disassembly */
7205 for(i=0;!done;i++) {
7206 bt[i]=0;likely[i]=0;ooo[i]=0;op2=0;
7207 minimum_free_regs[i]=0;
7208 opcode[i]=op=source[i]>>26;
7211 case 0x00: strcpy(insn[i],"special"); type=NI;
7215 case 0x00: strcpy(insn[i],"SLL"); type=SHIFTIMM; break;
7216 case 0x02: strcpy(insn[i],"SRL"); type=SHIFTIMM; break;
7217 case 0x03: strcpy(insn[i],"SRA"); type=SHIFTIMM; break;
7218 case 0x04: strcpy(insn[i],"SLLV"); type=SHIFT; break;
7219 case 0x06: strcpy(insn[i],"SRLV"); type=SHIFT; break;
7220 case 0x07: strcpy(insn[i],"SRAV"); type=SHIFT; break;
7221 case 0x08: strcpy(insn[i],"JR"); type=RJUMP; break;
7222 case 0x09: strcpy(insn[i],"JALR"); type=RJUMP; break;
7223 case 0x0C: strcpy(insn[i],"SYSCALL"); type=SYSCALL; break;
7224 case 0x0D: strcpy(insn[i],"BREAK"); type=OTHER; break;
7225 case 0x0F: strcpy(insn[i],"SYNC"); type=OTHER; break;
7226 case 0x10: strcpy(insn[i],"MFHI"); type=MOV; break;
7227 case 0x11: strcpy(insn[i],"MTHI"); type=MOV; break;
7228 case 0x12: strcpy(insn[i],"MFLO"); type=MOV; break;
7229 case 0x13: strcpy(insn[i],"MTLO"); type=MOV; break;
7230 case 0x18: strcpy(insn[i],"MULT"); type=MULTDIV; break;
7231 case 0x19: strcpy(insn[i],"MULTU"); type=MULTDIV; break;
7232 case 0x1A: strcpy(insn[i],"DIV"); type=MULTDIV; break;
7233 case 0x1B: strcpy(insn[i],"DIVU"); type=MULTDIV; break;
7234 case 0x20: strcpy(insn[i],"ADD"); type=ALU; break;
7235 case 0x21: strcpy(insn[i],"ADDU"); type=ALU; break;
7236 case 0x22: strcpy(insn[i],"SUB"); type=ALU; break;
7237 case 0x23: strcpy(insn[i],"SUBU"); type=ALU; break;
7238 case 0x24: strcpy(insn[i],"AND"); type=ALU; break;
7239 case 0x25: strcpy(insn[i],"OR"); type=ALU; break;
7240 case 0x26: strcpy(insn[i],"XOR"); type=ALU; break;
7241 case 0x27: strcpy(insn[i],"NOR"); type=ALU; break;
7242 case 0x2A: strcpy(insn[i],"SLT"); type=ALU; break;
7243 case 0x2B: strcpy(insn[i],"SLTU"); type=ALU; break;
7244 case 0x30: strcpy(insn[i],"TGE"); type=NI; break;
7245 case 0x31: strcpy(insn[i],"TGEU"); type=NI; break;
7246 case 0x32: strcpy(insn[i],"TLT"); type=NI; break;
7247 case 0x33: strcpy(insn[i],"TLTU"); type=NI; break;
7248 case 0x34: strcpy(insn[i],"TEQ"); type=NI; break;
7249 case 0x36: strcpy(insn[i],"TNE"); type=NI; break;
7251 case 0x14: strcpy(insn[i],"DSLLV"); type=SHIFT; break;
7252 case 0x16: strcpy(insn[i],"DSRLV"); type=SHIFT; break;
7253 case 0x17: strcpy(insn[i],"DSRAV"); type=SHIFT; break;
7254 case 0x1C: strcpy(insn[i],"DMULT"); type=MULTDIV; break;
7255 case 0x1D: strcpy(insn[i],"DMULTU"); type=MULTDIV; break;
7256 case 0x1E: strcpy(insn[i],"DDIV"); type=MULTDIV; break;
7257 case 0x1F: strcpy(insn[i],"DDIVU"); type=MULTDIV; break;
7258 case 0x2C: strcpy(insn[i],"DADD"); type=ALU; break;
7259 case 0x2D: strcpy(insn[i],"DADDU"); type=ALU; break;
7260 case 0x2E: strcpy(insn[i],"DSUB"); type=ALU; break;
7261 case 0x2F: strcpy(insn[i],"DSUBU"); type=ALU; break;
7262 case 0x38: strcpy(insn[i],"DSLL"); type=SHIFTIMM; break;
7263 case 0x3A: strcpy(insn[i],"DSRL"); type=SHIFTIMM; break;
7264 case 0x3B: strcpy(insn[i],"DSRA"); type=SHIFTIMM; break;
7265 case 0x3C: strcpy(insn[i],"DSLL32"); type=SHIFTIMM; break;
7266 case 0x3E: strcpy(insn[i],"DSRL32"); type=SHIFTIMM; break;
7267 case 0x3F: strcpy(insn[i],"DSRA32"); type=SHIFTIMM; break;
7271 case 0x01: strcpy(insn[i],"regimm"); type=NI;
7272 op2=(source[i]>>16)&0x1f;
7275 case 0x00: strcpy(insn[i],"BLTZ"); type=SJUMP; break;
7276 case 0x01: strcpy(insn[i],"BGEZ"); type=SJUMP; break;
7277 case 0x02: strcpy(insn[i],"BLTZL"); type=SJUMP; break;
7278 case 0x03: strcpy(insn[i],"BGEZL"); type=SJUMP; break;
7279 case 0x08: strcpy(insn[i],"TGEI"); type=NI; break;
7280 case 0x09: strcpy(insn[i],"TGEIU"); type=NI; break;
7281 case 0x0A: strcpy(insn[i],"TLTI"); type=NI; break;
7282 case 0x0B: strcpy(insn[i],"TLTIU"); type=NI; break;
7283 case 0x0C: strcpy(insn[i],"TEQI"); type=NI; break;
7284 case 0x0E: strcpy(insn[i],"TNEI"); type=NI; break;
7285 case 0x10: strcpy(insn[i],"BLTZAL"); type=SJUMP; break;
7286 case 0x11: strcpy(insn[i],"BGEZAL"); type=SJUMP; break;
7287 case 0x12: strcpy(insn[i],"BLTZALL"); type=SJUMP; break;
7288 case 0x13: strcpy(insn[i],"BGEZALL"); type=SJUMP; break;
7291 case 0x02: strcpy(insn[i],"J"); type=UJUMP; break;
7292 case 0x03: strcpy(insn[i],"JAL"); type=UJUMP; break;
7293 case 0x04: strcpy(insn[i],"BEQ"); type=CJUMP; break;
7294 case 0x05: strcpy(insn[i],"BNE"); type=CJUMP; break;
7295 case 0x06: strcpy(insn[i],"BLEZ"); type=CJUMP; break;
7296 case 0x07: strcpy(insn[i],"BGTZ"); type=CJUMP; break;
7297 case 0x08: strcpy(insn[i],"ADDI"); type=IMM16; break;
7298 case 0x09: strcpy(insn[i],"ADDIU"); type=IMM16; break;
7299 case 0x0A: strcpy(insn[i],"SLTI"); type=IMM16; break;
7300 case 0x0B: strcpy(insn[i],"SLTIU"); type=IMM16; break;
7301 case 0x0C: strcpy(insn[i],"ANDI"); type=IMM16; break;
7302 case 0x0D: strcpy(insn[i],"ORI"); type=IMM16; break;
7303 case 0x0E: strcpy(insn[i],"XORI"); type=IMM16; break;
7304 case 0x0F: strcpy(insn[i],"LUI"); type=IMM16; break;
7305 case 0x10: strcpy(insn[i],"cop0"); type=NI;
7306 op2=(source[i]>>21)&0x1f;
7309 case 0x00: strcpy(insn[i],"MFC0"); type=COP0; break;
7310 case 0x04: strcpy(insn[i],"MTC0"); type=COP0; break;
7311 case 0x10: strcpy(insn[i],"tlb"); type=NI;
7312 switch(source[i]&0x3f)
7314 case 0x01: strcpy(insn[i],"TLBR"); type=COP0; break;
7315 case 0x02: strcpy(insn[i],"TLBWI"); type=COP0; break;
7316 case 0x06: strcpy(insn[i],"TLBWR"); type=COP0; break;
7317 case 0x08: strcpy(insn[i],"TLBP"); type=COP0; break;
7318 case 0x10: strcpy(insn[i],"RFE"); type=COP0; break;
7319 //case 0x18: strcpy(insn[i],"ERET"); type=COP0; break;
7323 case 0x11: strcpy(insn[i],"cop1"); type=NI;
7324 op2=(source[i]>>21)&0x1f;
7327 case 0x00: strcpy(insn[i],"MFC1"); type=COP1; break;
7328 case 0x01: strcpy(insn[i],"DMFC1"); type=COP1; break;
7329 case 0x02: strcpy(insn[i],"CFC1"); type=COP1; break;
7330 case 0x04: strcpy(insn[i],"MTC1"); type=COP1; break;
7331 case 0x05: strcpy(insn[i],"DMTC1"); type=COP1; break;
7332 case 0x06: strcpy(insn[i],"CTC1"); type=COP1; break;
7333 case 0x08: strcpy(insn[i],"BC1"); type=FJUMP;
7334 switch((source[i]>>16)&0x3)
7336 case 0x00: strcpy(insn[i],"BC1F"); break;
7337 case 0x01: strcpy(insn[i],"BC1T"); break;
7338 case 0x02: strcpy(insn[i],"BC1FL"); break;
7339 case 0x03: strcpy(insn[i],"BC1TL"); break;
7342 case 0x10: strcpy(insn[i],"C1.S"); type=NI;
7343 switch(source[i]&0x3f)
7345 case 0x00: strcpy(insn[i],"ADD.S"); type=FLOAT; break;
7346 case 0x01: strcpy(insn[i],"SUB.S"); type=FLOAT; break;
7347 case 0x02: strcpy(insn[i],"MUL.S"); type=FLOAT; break;
7348 case 0x03: strcpy(insn[i],"DIV.S"); type=FLOAT; break;
7349 case 0x04: strcpy(insn[i],"SQRT.S"); type=FLOAT; break;
7350 case 0x05: strcpy(insn[i],"ABS.S"); type=FLOAT; break;
7351 case 0x06: strcpy(insn[i],"MOV.S"); type=FLOAT; break;
7352 case 0x07: strcpy(insn[i],"NEG.S"); type=FLOAT; break;
7353 case 0x08: strcpy(insn[i],"ROUND.L.S"); type=FCONV; break;
7354 case 0x09: strcpy(insn[i],"TRUNC.L.S"); type=FCONV; break;
7355 case 0x0A: strcpy(insn[i],"CEIL.L.S"); type=FCONV; break;
7356 case 0x0B: strcpy(insn[i],"FLOOR.L.S"); type=FCONV; break;
7357 case 0x0C: strcpy(insn[i],"ROUND.W.S"); type=FCONV; break;
7358 case 0x0D: strcpy(insn[i],"TRUNC.W.S"); type=FCONV; break;
7359 case 0x0E: strcpy(insn[i],"CEIL.W.S"); type=FCONV; break;
7360 case 0x0F: strcpy(insn[i],"FLOOR.W.S"); type=FCONV; break;
7361 case 0x21: strcpy(insn[i],"CVT.D.S"); type=FCONV; break;
7362 case 0x24: strcpy(insn[i],"CVT.W.S"); type=FCONV; break;
7363 case 0x25: strcpy(insn[i],"CVT.L.S"); type=FCONV; break;
7364 case 0x30: strcpy(insn[i],"C.F.S"); type=FCOMP; break;
7365 case 0x31: strcpy(insn[i],"C.UN.S"); type=FCOMP; break;
7366 case 0x32: strcpy(insn[i],"C.EQ.S"); type=FCOMP; break;
7367 case 0x33: strcpy(insn[i],"C.UEQ.S"); type=FCOMP; break;
7368 case 0x34: strcpy(insn[i],"C.OLT.S"); type=FCOMP; break;
7369 case 0x35: strcpy(insn[i],"C.ULT.S"); type=FCOMP; break;
7370 case 0x36: strcpy(insn[i],"C.OLE.S"); type=FCOMP; break;
7371 case 0x37: strcpy(insn[i],"C.ULE.S"); type=FCOMP; break;
7372 case 0x38: strcpy(insn[i],"C.SF.S"); type=FCOMP; break;
7373 case 0x39: strcpy(insn[i],"C.NGLE.S"); type=FCOMP; break;
7374 case 0x3A: strcpy(insn[i],"C.SEQ.S"); type=FCOMP; break;
7375 case 0x3B: strcpy(insn[i],"C.NGL.S"); type=FCOMP; break;
7376 case 0x3C: strcpy(insn[i],"C.LT.S"); type=FCOMP; break;
7377 case 0x3D: strcpy(insn[i],"C.NGE.S"); type=FCOMP; break;
7378 case 0x3E: strcpy(insn[i],"C.LE.S"); type=FCOMP; break;
7379 case 0x3F: strcpy(insn[i],"C.NGT.S"); type=FCOMP; break;
7382 case 0x11: strcpy(insn[i],"C1.D"); type=NI;
7383 switch(source[i]&0x3f)
7385 case 0x00: strcpy(insn[i],"ADD.D"); type=FLOAT; break;
7386 case 0x01: strcpy(insn[i],"SUB.D"); type=FLOAT; break;
7387 case 0x02: strcpy(insn[i],"MUL.D"); type=FLOAT; break;
7388 case 0x03: strcpy(insn[i],"DIV.D"); type=FLOAT; break;
7389 case 0x04: strcpy(insn[i],"SQRT.D"); type=FLOAT; break;
7390 case 0x05: strcpy(insn[i],"ABS.D"); type=FLOAT; break;
7391 case 0x06: strcpy(insn[i],"MOV.D"); type=FLOAT; break;
7392 case 0x07: strcpy(insn[i],"NEG.D"); type=FLOAT; break;
7393 case 0x08: strcpy(insn[i],"ROUND.L.D"); type=FCONV; break;
7394 case 0x09: strcpy(insn[i],"TRUNC.L.D"); type=FCONV; break;
7395 case 0x0A: strcpy(insn[i],"CEIL.L.D"); type=FCONV; break;
7396 case 0x0B: strcpy(insn[i],"FLOOR.L.D"); type=FCONV; break;
7397 case 0x0C: strcpy(insn[i],"ROUND.W.D"); type=FCONV; break;
7398 case 0x0D: strcpy(insn[i],"TRUNC.W.D"); type=FCONV; break;
7399 case 0x0E: strcpy(insn[i],"CEIL.W.D"); type=FCONV; break;
7400 case 0x0F: strcpy(insn[i],"FLOOR.W.D"); type=FCONV; break;
7401 case 0x20: strcpy(insn[i],"CVT.S.D"); type=FCONV; break;
7402 case 0x24: strcpy(insn[i],"CVT.W.D"); type=FCONV; break;
7403 case 0x25: strcpy(insn[i],"CVT.L.D"); type=FCONV; break;
7404 case 0x30: strcpy(insn[i],"C.F.D"); type=FCOMP; break;
7405 case 0x31: strcpy(insn[i],"C.UN.D"); type=FCOMP; break;
7406 case 0x32: strcpy(insn[i],"C.EQ.D"); type=FCOMP; break;
7407 case 0x33: strcpy(insn[i],"C.UEQ.D"); type=FCOMP; break;
7408 case 0x34: strcpy(insn[i],"C.OLT.D"); type=FCOMP; break;
7409 case 0x35: strcpy(insn[i],"C.ULT.D"); type=FCOMP; break;
7410 case 0x36: strcpy(insn[i],"C.OLE.D"); type=FCOMP; break;
7411 case 0x37: strcpy(insn[i],"C.ULE.D"); type=FCOMP; break;
7412 case 0x38: strcpy(insn[i],"C.SF.D"); type=FCOMP; break;
7413 case 0x39: strcpy(insn[i],"C.NGLE.D"); type=FCOMP; break;
7414 case 0x3A: strcpy(insn[i],"C.SEQ.D"); type=FCOMP; break;
7415 case 0x3B: strcpy(insn[i],"C.NGL.D"); type=FCOMP; break;
7416 case 0x3C: strcpy(insn[i],"C.LT.D"); type=FCOMP; break;
7417 case 0x3D: strcpy(insn[i],"C.NGE.D"); type=FCOMP; break;
7418 case 0x3E: strcpy(insn[i],"C.LE.D"); type=FCOMP; break;
7419 case 0x3F: strcpy(insn[i],"C.NGT.D"); type=FCOMP; break;
7422 case 0x14: strcpy(insn[i],"C1.W"); type=NI;
7423 switch(source[i]&0x3f)
7425 case 0x20: strcpy(insn[i],"CVT.S.W"); type=FCONV; break;
7426 case 0x21: strcpy(insn[i],"CVT.D.W"); type=FCONV; break;
7429 case 0x15: strcpy(insn[i],"C1.L"); type=NI;
7430 switch(source[i]&0x3f)
7432 case 0x20: strcpy(insn[i],"CVT.S.L"); type=FCONV; break;
7433 case 0x21: strcpy(insn[i],"CVT.D.L"); type=FCONV; break;
7439 case 0x14: strcpy(insn[i],"BEQL"); type=CJUMP; break;
7440 case 0x15: strcpy(insn[i],"BNEL"); type=CJUMP; break;
7441 case 0x16: strcpy(insn[i],"BLEZL"); type=CJUMP; break;
7442 case 0x17: strcpy(insn[i],"BGTZL"); type=CJUMP; break;
7443 case 0x18: strcpy(insn[i],"DADDI"); type=IMM16; break;
7444 case 0x19: strcpy(insn[i],"DADDIU"); type=IMM16; break;
7445 case 0x1A: strcpy(insn[i],"LDL"); type=LOADLR; break;
7446 case 0x1B: strcpy(insn[i],"LDR"); type=LOADLR; break;
7448 case 0x20: strcpy(insn[i],"LB"); type=LOAD; break;
7449 case 0x21: strcpy(insn[i],"LH"); type=LOAD; break;
7450 case 0x22: strcpy(insn[i],"LWL"); type=LOADLR; break;
7451 case 0x23: strcpy(insn[i],"LW"); type=LOAD; break;
7452 case 0x24: strcpy(insn[i],"LBU"); type=LOAD; break;
7453 case 0x25: strcpy(insn[i],"LHU"); type=LOAD; break;
7454 case 0x26: strcpy(insn[i],"LWR"); type=LOADLR; break;
7456 case 0x27: strcpy(insn[i],"LWU"); type=LOAD; break;
7458 case 0x28: strcpy(insn[i],"SB"); type=STORE; break;
7459 case 0x29: strcpy(insn[i],"SH"); type=STORE; break;
7460 case 0x2A: strcpy(insn[i],"SWL"); type=STORELR; break;
7461 case 0x2B: strcpy(insn[i],"SW"); type=STORE; break;
7463 case 0x2C: strcpy(insn[i],"SDL"); type=STORELR; break;
7464 case 0x2D: strcpy(insn[i],"SDR"); type=STORELR; break;
7466 case 0x2E: strcpy(insn[i],"SWR"); type=STORELR; break;
7467 case 0x2F: strcpy(insn[i],"CACHE"); type=NOP; break;
7468 case 0x30: strcpy(insn[i],"LL"); type=NI; break;
7469 case 0x31: strcpy(insn[i],"LWC1"); type=C1LS; break;
7471 case 0x34: strcpy(insn[i],"LLD"); type=NI; break;
7472 case 0x35: strcpy(insn[i],"LDC1"); type=C1LS; break;
7473 case 0x37: strcpy(insn[i],"LD"); type=LOAD; break;
7475 case 0x38: strcpy(insn[i],"SC"); type=NI; break;
7476 case 0x39: strcpy(insn[i],"SWC1"); type=C1LS; break;
7478 case 0x3C: strcpy(insn[i],"SCD"); type=NI; break;
7479 case 0x3D: strcpy(insn[i],"SDC1"); type=C1LS; break;
7480 case 0x3F: strcpy(insn[i],"SD"); type=STORE; break;
7482 case 0x12: strcpy(insn[i],"COP2"); type=NI;
7483 op2=(source[i]>>21)&0x1f;
7485 if (source[i]&0x3f) { // use this hack to support old savestates with patched gte insns
7486 if (gte_handlers[source[i]&0x3f]!=NULL) {
7487 if (gte_regnames[source[i]&0x3f]!=NULL)
7488 strcpy(insn[i],gte_regnames[source[i]&0x3f]);
7490 snprintf(insn[i], sizeof(insn[i]), "COP2 %x", source[i]&0x3f);
7496 case 0x00: strcpy(insn[i],"MFC2"); type=COP2; break;
7497 case 0x02: strcpy(insn[i],"CFC2"); type=COP2; break;
7498 case 0x04: strcpy(insn[i],"MTC2"); type=COP2; break;
7499 case 0x06: strcpy(insn[i],"CTC2"); type=COP2; break;
7502 case 0x32: strcpy(insn[i],"LWC2"); type=C2LS; break;
7503 case 0x3A: strcpy(insn[i],"SWC2"); type=C2LS; break;
7504 case 0x3B: strcpy(insn[i],"HLECALL"); type=HLECALL; break;
7505 default: strcpy(insn[i],"???"); type=NI;
7506 SysPrintf("NI %08x @%08x (%08x)\n", source[i], addr + i*4, addr);
7511 /* Get registers/immediates */
7517 gte_rs[i]=gte_rt[i]=0;
7520 rs1[i]=(source[i]>>21)&0x1f;
7522 rt1[i]=(source[i]>>16)&0x1f;
7524 imm[i]=(short)source[i];
7528 rs1[i]=(source[i]>>21)&0x1f;
7529 rs2[i]=(source[i]>>16)&0x1f;
7532 imm[i]=(short)source[i];
7533 if(op==0x2c||op==0x2d||op==0x3f) us1[i]=rs2[i]; // 64-bit SDL/SDR/SD
7536 // LWL/LWR only load part of the register,
7537 // therefore the target register must be treated as a source too
7538 rs1[i]=(source[i]>>21)&0x1f;
7539 rs2[i]=(source[i]>>16)&0x1f;
7540 rt1[i]=(source[i]>>16)&0x1f;
7542 imm[i]=(short)source[i];
7543 if(op==0x1a||op==0x1b) us1[i]=rs2[i]; // LDR/LDL
7544 if(op==0x26) dep1[i]=rt1[i]; // LWR
7547 if (op==0x0f) rs1[i]=0; // LUI instruction has no source register
7548 else rs1[i]=(source[i]>>21)&0x1f;
7550 rt1[i]=(source[i]>>16)&0x1f;
7552 if(op>=0x0c&&op<=0x0e) { // ANDI/ORI/XORI
7553 imm[i]=(unsigned short)source[i];
7555 imm[i]=(short)source[i];
7557 if(op==0x18||op==0x19) us1[i]=rs1[i]; // DADDI/DADDIU
7558 if(op==0x0a||op==0x0b) us1[i]=rs1[i]; // SLTI/SLTIU
7559 if(op==0x0d||op==0x0e) dep1[i]=rs1[i]; // ORI/XORI
7566 // The JAL instruction writes to r31.
7573 rs1[i]=(source[i]>>21)&0x1f;
7577 // The JALR instruction writes to rd.
7579 rt1[i]=(source[i]>>11)&0x1f;
7584 rs1[i]=(source[i]>>21)&0x1f;
7585 rs2[i]=(source[i]>>16)&0x1f;
7588 if(op&2) { // BGTZ/BLEZ
7596 rs1[i]=(source[i]>>21)&0x1f;
7601 if(op2&0x10) { // BxxAL
7603 // NOTE: If the branch is not taken, r31 is still overwritten
7605 likely[i]=(op2&2)>>1;
7612 likely[i]=((source[i])>>17)&1;
7615 rs1[i]=(source[i]>>21)&0x1f; // source
7616 rs2[i]=(source[i]>>16)&0x1f; // subtract amount
7617 rt1[i]=(source[i]>>11)&0x1f; // destination
7619 if(op2==0x2a||op2==0x2b) { // SLT/SLTU
7620 us1[i]=rs1[i];us2[i]=rs2[i];
7622 else if(op2>=0x24&&op2<=0x27) { // AND/OR/XOR/NOR
7623 dep1[i]=rs1[i];dep2[i]=rs2[i];
7625 else if(op2>=0x2c&&op2<=0x2f) { // DADD/DSUB
7626 dep1[i]=rs1[i];dep2[i]=rs2[i];
7630 rs1[i]=(source[i]>>21)&0x1f; // source
7631 rs2[i]=(source[i]>>16)&0x1f; // divisor
7634 if (op2>=0x1c&&op2<=0x1f) { // DMULT/DMULTU/DDIV/DDIVU
7635 us1[i]=rs1[i];us2[i]=rs2[i];
7643 if(op2==0x10) rs1[i]=HIREG; // MFHI
7644 if(op2==0x11) rt1[i]=HIREG; // MTHI
7645 if(op2==0x12) rs1[i]=LOREG; // MFLO
7646 if(op2==0x13) rt1[i]=LOREG; // MTLO
7647 if((op2&0x1d)==0x10) rt1[i]=(source[i]>>11)&0x1f; // MFxx
7648 if((op2&0x1d)==0x11) rs1[i]=(source[i]>>21)&0x1f; // MTxx
7652 rs1[i]=(source[i]>>16)&0x1f; // target of shift
7653 rs2[i]=(source[i]>>21)&0x1f; // shift amount
7654 rt1[i]=(source[i]>>11)&0x1f; // destination
7656 // DSLLV/DSRLV/DSRAV are 64-bit
7657 if(op2>=0x14&&op2<=0x17) us1[i]=rs1[i];
7660 rs1[i]=(source[i]>>16)&0x1f;
7662 rt1[i]=(source[i]>>11)&0x1f;
7664 imm[i]=(source[i]>>6)&0x1f;
7665 // DSxx32 instructions
7666 if(op2>=0x3c) imm[i]|=0x20;
7667 // DSLL/DSRL/DSRA/DSRA32/DSRL32 but not DSLL32 require 64-bit source
7668 if(op2>=0x38&&op2!=0x3c) us1[i]=rs1[i];
7675 if(op2==0) rt1[i]=(source[i]>>16)&0x1F; // MFC0
7676 if(op2==4) rs1[i]=(source[i]>>16)&0x1F; // MTC0
7677 if(op2==4&&((source[i]>>11)&0x1f)==12) rt2[i]=CSREG; // Status
7678 if(op2==16) if((source[i]&0x3f)==0x18) rs2[i]=CCREG; // ERET
7685 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC1/DMFC1/CFC1
7686 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC1/DMTC1/CTC1
7687 if(op2==5) us1[i]=rs1[i]; // DMTC1
7695 if(op2<3) rt1[i]=(source[i]>>16)&0x1F; // MFC2/CFC2
7696 if(op2>3) rs1[i]=(source[i]>>16)&0x1F; // MTC2/CTC2
7698 int gr=(source[i]>>11)&0x1F;
7701 case 0x00: gte_rs[i]=1ll<<gr; break; // MFC2
7702 case 0x04: gte_rt[i]=1ll<<gr; break; // MTC2
7703 case 0x02: gte_rs[i]=1ll<<(gr+32); break; // CFC2
7704 case 0x06: gte_rt[i]=1ll<<(gr+32); break; // CTC2
7708 rs1[i]=(source[i]>>21)&0x1F;
7712 imm[i]=(short)source[i];
7715 rs1[i]=(source[i]>>21)&0x1F;
7719 imm[i]=(short)source[i];
7720 if(op==0x32) gte_rt[i]=1ll<<((source[i]>>16)&0x1F); // LWC2
7721 else gte_rs[i]=1ll<<((source[i]>>16)&0x1F); // SWC2
7728 gte_rs[i]=gte_reg_reads[source[i]&0x3f];
7729 gte_rt[i]=gte_reg_writes[source[i]&0x3f];
7730 gte_rt[i]|=1ll<<63; // every op changes flags
7731 if((source[i]&0x3f)==GTE_MVMVA) {
7732 int v = (source[i] >> 15) & 3;
7733 gte_rs[i]&=~0xe3fll;
7734 if(v==3) gte_rs[i]|=0xe00ll;
7735 else gte_rs[i]|=3ll<<(v*2);
7765 /* Calculate branch target addresses */
7767 ba[i]=((start+i*4+4)&0xF0000000)|(((unsigned int)source[i]<<6)>>4);
7768 else if(type==CJUMP&&rs1[i]==rs2[i]&&(op&1))
7769 ba[i]=start+i*4+8; // Ignore never taken branch
7770 else if(type==SJUMP&&rs1[i]==0&&!(op2&1))
7771 ba[i]=start+i*4+8; // Ignore never taken branch
7772 else if(type==CJUMP||type==SJUMP||type==FJUMP)
7773 ba[i]=start+i*4+4+((signed int)((unsigned int)source[i]<<16)>>14);
7775 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP)) {
7777 // branch in delay slot?
7778 if(type==RJUMP||type==UJUMP||type==CJUMP||type==SJUMP||type==FJUMP) {
7779 // don't handle first branch and call interpreter if it's hit
7780 SysPrintf("branch in delay slot @%08x (%08x)\n", addr + i*4, addr);
7783 // basic load delay detection
7784 else if((type==LOAD||type==LOADLR||type==COP0||type==COP2||type==C2LS)&&rt1[i]!=0) {
7785 int t=(ba[i-1]-start)/4;
7786 if(0 <= t && t < i &&(rt1[i]==rs1[t]||rt1[i]==rs2[t])&&itype[t]!=CJUMP&&itype[t]!=SJUMP) {
7787 // jump target wants DS result - potential load delay effect
7788 SysPrintf("load delay @%08x (%08x)\n", addr + i*4, addr);
7790 bt[t+1]=1; // expected return from interpreter
7792 else if(i>=2&&rt1[i-2]==2&&rt1[i]==2&&rs1[i]!=2&&rs2[i]!=2&&rs1[i-1]!=2&&rs2[i-1]!=2&&
7793 !(i>=3&&(itype[i-3]==RJUMP||itype[i-3]==UJUMP||itype[i-3]==CJUMP||itype[i-3]==SJUMP))) {
7794 // v0 overwrite like this is a sign of trouble, bail out
7795 SysPrintf("v0 overwrite @%08x (%08x)\n", addr + i*4, addr);
7801 rs2[i-1]=rt1[i-1]=rt2[i-1]=0;
7805 i--; // don't compile the DS
7808 /* Is this the end of the block? */
7809 if(i>0&&(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)) {
7810 if(rt1[i-1]==0) { // Continue past subroutine call (JAL)
7814 if(stop_after_jal) done=1;
7816 if((source[i+1]&0xfc00003f)==0x0d) done=1;
7818 // Don't recompile stuff that's already compiled
7819 if(check_addr(start+i*4+4)) done=1;
7820 // Don't get too close to the limit
7821 if(i>MAXBLOCK/2) done=1;
7823 if(itype[i]==SYSCALL&&stop_after_jal) done=1;
7824 if(itype[i]==HLECALL||itype[i]==INTCALL) done=2;
7826 // Does the block continue due to a branch?
7829 if(ba[j]==start+i*4) done=j=0; // Branch into delay slot
7830 if(ba[j]==start+i*4+4) done=j=0;
7831 if(ba[j]==start+i*4+8) done=j=0;
7834 //assert(i<MAXBLOCK-1);
7835 if(start+i*4==pagelimit-4) done=1;
7836 assert(start+i*4<pagelimit);
7837 if (i==MAXBLOCK-1) done=1;
7838 // Stop if we're compiling junk
7839 if(itype[i]==NI&&opcode[i]==0x11) {
7840 done=stop_after_jal=1;
7841 SysPrintf("Disabled speculative precompilation\n");
7845 if(itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==RJUMP||itype[i-1]==FJUMP) {
7846 if(start+i*4==pagelimit) {
7852 /* Pass 2 - Register dependencies and branch targets */
7854 unneeded_registers(0,slen-1,0);
7856 /* Pass 3 - Register allocation */
7858 struct regstat current; // Current register allocations/status
7861 current.u=unneeded_reg[0];
7862 current.uu=unneeded_reg_upper[0];
7863 clear_all_regs(current.regmap);
7864 alloc_reg(¤t,0,CCREG);
7865 dirty_reg(¤t,CCREG);
7868 current.waswritten=0;
7874 // First instruction is delay slot
7879 unneeded_reg_upper[0]=1;
7880 current.regmap[HOST_BTREG]=BTREG;
7888 for(hr=0;hr<HOST_REGS;hr++)
7890 // Is this really necessary?
7891 if(current.regmap[hr]==0) current.regmap[hr]=-1;
7894 current.waswritten=0;
7898 if((opcode[i-2]&0x2f)==0x05) // BNE/BNEL
7900 if(rs1[i-2]==0||rs2[i-2]==0)
7903 current.is32|=1LL<<rs1[i-2];
7904 int hr=get_reg(current.regmap,rs1[i-2]|64);
7905 if(hr>=0) current.regmap[hr]=-1;
7908 current.is32|=1LL<<rs2[i-2];
7909 int hr=get_reg(current.regmap,rs2[i-2]|64);
7910 if(hr>=0) current.regmap[hr]=-1;
7917 memcpy(regmap_pre[i],current.regmap,sizeof(current.regmap));
7918 regs[i].wasconst=current.isconst;
7919 regs[i].was32=current.is32;
7920 regs[i].wasdirty=current.dirty;
7921 regs[i].loadedconst=0;
7922 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
7924 current.u=unneeded_reg[i+1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
7925 current.uu=unneeded_reg_upper[i+1]&~((1LL<<us1[i])|(1LL<<us2[i]));
7926 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
7935 current.u=branch_unneeded_reg[i]&~((1LL<<rs1[i+1])|(1LL<<rs2[i+1]));
7936 current.uu=branch_unneeded_reg_upper[i]&~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
7937 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
7938 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
7939 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
7942 } else { SysPrintf("oops, branch at end of block with no delay slot\n");exit(1); }
7946 ds=0; // Skip delay slot, already allocated as part of branch
7947 // ...but we need to alloc it in case something jumps here
7949 current.u=branch_unneeded_reg[i-1]&unneeded_reg[i+1];
7950 current.uu=branch_unneeded_reg_upper[i-1]&unneeded_reg_upper[i+1];
7952 current.u=branch_unneeded_reg[i-1];
7953 current.uu=branch_unneeded_reg_upper[i-1];
7955 current.u&=~((1LL<<rs1[i])|(1LL<<rs2[i]));
7956 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
7957 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
7960 struct regstat temp;
7961 memcpy(&temp,¤t,sizeof(current));
7962 temp.wasdirty=temp.dirty;
7963 temp.was32=temp.is32;
7964 // TODO: Take into account unconditional branches, as below
7965 delayslot_alloc(&temp,i);
7966 memcpy(regs[i].regmap,temp.regmap,sizeof(temp.regmap));
7967 regs[i].wasdirty=temp.wasdirty;
7968 regs[i].was32=temp.was32;
7969 regs[i].dirty=temp.dirty;
7970 regs[i].is32=temp.is32;
7974 // Create entry (branch target) regmap
7975 for(hr=0;hr<HOST_REGS;hr++)
7977 int r=temp.regmap[hr];
7979 if(r!=regmap_pre[i][hr]) {
7980 regs[i].regmap_entry[hr]=-1;
7985 if((current.u>>r)&1) {
7986 regs[i].regmap_entry[hr]=-1;
7987 regs[i].regmap[hr]=-1;
7988 //Don't clear regs in the delay slot as the branch might need them
7989 //current.regmap[hr]=-1;
7991 regs[i].regmap_entry[hr]=r;
7994 if((current.uu>>(r&63))&1) {
7995 regs[i].regmap_entry[hr]=-1;
7996 regs[i].regmap[hr]=-1;
7997 //Don't clear regs in the delay slot as the branch might need them
7998 //current.regmap[hr]=-1;
8000 regs[i].regmap_entry[hr]=r;
8004 // First instruction expects CCREG to be allocated
8005 if(i==0&&hr==HOST_CCREG)
8006 regs[i].regmap_entry[hr]=CCREG;
8008 regs[i].regmap_entry[hr]=-1;
8012 else { // Not delay slot
8015 //current.isconst=0; // DEBUG
8016 //current.wasconst=0; // DEBUG
8017 //regs[i].wasconst=0; // DEBUG
8018 clear_const(¤t,rt1[i]);
8019 alloc_cc(¤t,i);
8020 dirty_reg(¤t,CCREG);
8022 alloc_reg(¤t,i,31);
8023 dirty_reg(¤t,31);
8024 //assert(rs1[i+1]!=31&&rs2[i+1]!=31);
8025 //assert(rt1[i+1]!=rt1[i]);
8027 alloc_reg(¤t,i,PTEMP);
8029 //current.is32|=1LL<<rt1[i];
8032 delayslot_alloc(¤t,i+1);
8033 //current.isconst=0; // DEBUG
8035 //printf("i=%d, isconst=%x\n",i,current.isconst);
8038 //current.isconst=0;
8039 //current.wasconst=0;
8040 //regs[i].wasconst=0;
8041 clear_const(¤t,rs1[i]);
8042 clear_const(¤t,rt1[i]);
8043 alloc_cc(¤t,i);
8044 dirty_reg(¤t,CCREG);
8045 if(rs1[i]!=rt1[i+1]&&rs1[i]!=rt2[i+1]) {
8046 alloc_reg(¤t,i,rs1[i]);
8048 alloc_reg(¤t,i,rt1[i]);
8049 dirty_reg(¤t,rt1[i]);
8050 assert(rs1[i+1]!=rt1[i]&&rs2[i+1]!=rt1[i]);
8051 assert(rt1[i+1]!=rt1[i]);
8053 alloc_reg(¤t,i,PTEMP);
8057 if(rs1[i]==31) { // JALR
8058 alloc_reg(¤t,i,RHASH);
8059 #ifndef HOST_IMM_ADDR32
8060 alloc_reg(¤t,i,RHTBL);
8064 delayslot_alloc(¤t,i+1);
8066 // The delay slot overwrites our source register,
8067 // allocate a temporary register to hold the old value.
8071 delayslot_alloc(¤t,i+1);
8073 alloc_reg(¤t,i,RTEMP);
8075 //current.isconst=0; // DEBUG
8080 //current.isconst=0;
8081 //current.wasconst=0;
8082 //regs[i].wasconst=0;
8083 clear_const(¤t,rs1[i]);
8084 clear_const(¤t,rs2[i]);
8085 if((opcode[i]&0x3E)==4) // BEQ/BNE
8087 alloc_cc(¤t,i);
8088 dirty_reg(¤t,CCREG);
8089 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8090 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8091 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8093 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8094 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8096 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1]))||
8097 (rs2[i]&&(rs2[i]==rt1[i+1]||rs2[i]==rt2[i+1]))) {
8098 // The delay slot overwrites one of our conditions.
8099 // Allocate the branch condition registers instead.
8103 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8104 if(rs2[i]) alloc_reg(¤t,i,rs2[i]);
8105 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8107 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8108 if(rs2[i]) alloc_reg64(¤t,i,rs2[i]);
8114 delayslot_alloc(¤t,i+1);
8118 if((opcode[i]&0x3E)==6) // BLEZ/BGTZ
8120 alloc_cc(¤t,i);
8121 dirty_reg(¤t,CCREG);
8122 alloc_reg(¤t,i,rs1[i]);
8123 if(!(current.is32>>rs1[i]&1))
8125 alloc_reg64(¤t,i,rs1[i]);
8127 if(rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) {
8128 // The delay slot overwrites one of our conditions.
8129 // Allocate the branch condition registers instead.
8133 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8134 if(!((current.is32>>rs1[i])&1))
8136 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8142 delayslot_alloc(¤t,i+1);
8146 // Don't alloc the delay slot yet because we might not execute it
8147 if((opcode[i]&0x3E)==0x14) // BEQL/BNEL
8152 alloc_cc(¤t,i);
8153 dirty_reg(¤t,CCREG);
8154 alloc_reg(¤t,i,rs1[i]);
8155 alloc_reg(¤t,i,rs2[i]);
8156 if(!((current.is32>>rs1[i])&(current.is32>>rs2[i])&1))
8158 alloc_reg64(¤t,i,rs1[i]);
8159 alloc_reg64(¤t,i,rs2[i]);
8163 if((opcode[i]&0x3E)==0x16) // BLEZL/BGTZL
8168 alloc_cc(¤t,i);
8169 dirty_reg(¤t,CCREG);
8170 alloc_reg(¤t,i,rs1[i]);
8171 if(!(current.is32>>rs1[i]&1))
8173 alloc_reg64(¤t,i,rs1[i]);
8177 //current.isconst=0;
8180 //current.isconst=0;
8181 //current.wasconst=0;
8182 //regs[i].wasconst=0;
8183 clear_const(¤t,rs1[i]);
8184 clear_const(¤t,rt1[i]);
8185 //if((opcode2[i]&0x1E)==0x0) // BLTZ/BGEZ
8186 if((opcode2[i]&0x0E)==0x0) // BLTZ/BGEZ
8188 alloc_cc(¤t,i);
8189 dirty_reg(¤t,CCREG);
8190 alloc_reg(¤t,i,rs1[i]);
8191 if(!(current.is32>>rs1[i]&1))
8193 alloc_reg64(¤t,i,rs1[i]);
8195 if (rt1[i]==31) { // BLTZAL/BGEZAL
8196 alloc_reg(¤t,i,31);
8197 dirty_reg(¤t,31);
8198 //#ifdef REG_PREFETCH
8199 //alloc_reg(¤t,i,PTEMP);
8201 //current.is32|=1LL<<rt1[i];
8203 if((rs1[i]&&(rs1[i]==rt1[i+1]||rs1[i]==rt2[i+1])) // The delay slot overwrites the branch condition.
8204 ||(rt1[i]==31&&(rs1[i+1]==31||rs2[i+1]==31||rt1[i+1]==31||rt2[i+1]==31))) { // DS touches $ra
8205 // Allocate the branch condition registers instead.
8209 if(rs1[i]) alloc_reg(¤t,i,rs1[i]);
8210 if(!((current.is32>>rs1[i])&1))
8212 if(rs1[i]) alloc_reg64(¤t,i,rs1[i]);
8218 delayslot_alloc(¤t,i+1);
8222 // Don't alloc the delay slot yet because we might not execute it
8223 if((opcode2[i]&0x1E)==0x2) // BLTZL/BGEZL
8228 alloc_cc(¤t,i);
8229 dirty_reg(¤t,CCREG);
8230 alloc_reg(¤t,i,rs1[i]);
8231 if(!(current.is32>>rs1[i]&1))
8233 alloc_reg64(¤t,i,rs1[i]);
8237 //current.isconst=0;
8243 if(likely[i]==0) // BC1F/BC1T
8245 // TODO: Theoretically we can run out of registers here on x86.
8246 // The delay slot can allocate up to six, and we need to check
8247 // CSREG before executing the delay slot. Possibly we can drop
8248 // the cycle count and then reload it after checking that the
8249 // FPU is in a usable state, or don't do out-of-order execution.
8250 alloc_cc(¤t,i);
8251 dirty_reg(¤t,CCREG);
8252 alloc_reg(¤t,i,FSREG);
8253 alloc_reg(¤t,i,CSREG);
8254 if(itype[i+1]==FCOMP) {
8255 // The delay slot overwrites the branch condition.
8256 // Allocate the branch condition registers instead.
8257 alloc_cc(¤t,i);
8258 dirty_reg(¤t,CCREG);
8259 alloc_reg(¤t,i,CSREG);
8260 alloc_reg(¤t,i,FSREG);
8264 delayslot_alloc(¤t,i+1);
8265 alloc_reg(¤t,i+1,CSREG);
8269 // Don't alloc the delay slot yet because we might not execute it
8270 if(likely[i]) // BC1FL/BC1TL
8272 alloc_cc(¤t,i);
8273 dirty_reg(¤t,CCREG);
8274 alloc_reg(¤t,i,CSREG);
8275 alloc_reg(¤t,i,FSREG);
8281 imm16_alloc(¤t,i);
8285 load_alloc(¤t,i);
8289 store_alloc(¤t,i);
8292 alu_alloc(¤t,i);
8295 shift_alloc(¤t,i);
8298 multdiv_alloc(¤t,i);
8301 shiftimm_alloc(¤t,i);
8304 mov_alloc(¤t,i);
8307 cop0_alloc(¤t,i);
8311 cop1_alloc(¤t,i);
8314 c1ls_alloc(¤t,i);
8317 c2ls_alloc(¤t,i);
8320 c2op_alloc(¤t,i);
8323 fconv_alloc(¤t,i);
8326 float_alloc(¤t,i);
8329 fcomp_alloc(¤t,i);
8334 syscall_alloc(¤t,i);
8337 pagespan_alloc(¤t,i);
8341 // Drop the upper half of registers that have become 32-bit
8342 current.uu|=current.is32&((1LL<<rt1[i])|(1LL<<rt2[i]));
8343 if(itype[i]!=UJUMP&&itype[i]!=CJUMP&&itype[i]!=SJUMP&&itype[i]!=RJUMP&&itype[i]!=FJUMP) {
8344 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8345 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8348 current.uu|=current.is32&((1LL<<rt1[i+1])|(1LL<<rt2[i+1]));
8349 current.uu&=~((1LL<<us1[i+1])|(1LL<<us2[i+1]));
8350 if((~current.uu>>rt1[i+1])&1) current.uu&=~((1LL<<dep1[i+1])|(1LL<<dep2[i+1]));
8351 current.uu&=~((1LL<<us1[i])|(1LL<<us2[i]));
8355 // Create entry (branch target) regmap
8356 for(hr=0;hr<HOST_REGS;hr++)
8359 r=current.regmap[hr];
8361 if(r!=regmap_pre[i][hr]) {
8362 // TODO: delay slot (?)
8363 or=get_reg(regmap_pre[i],r); // Get old mapping for this register
8364 if(or<0||(r&63)>=TEMPREG){
8365 regs[i].regmap_entry[hr]=-1;
8369 // Just move it to a different register
8370 regs[i].regmap_entry[hr]=r;
8371 // If it was dirty before, it's still dirty
8372 if((regs[i].wasdirty>>or)&1) dirty_reg(¤t,r&63);
8379 regs[i].regmap_entry[hr]=0;
8383 if((current.u>>r)&1) {
8384 regs[i].regmap_entry[hr]=-1;
8385 //regs[i].regmap[hr]=-1;
8386 current.regmap[hr]=-1;
8388 regs[i].regmap_entry[hr]=r;
8391 if((current.uu>>(r&63))&1) {
8392 regs[i].regmap_entry[hr]=-1;
8393 //regs[i].regmap[hr]=-1;
8394 current.regmap[hr]=-1;
8396 regs[i].regmap_entry[hr]=r;
8400 // Branches expect CCREG to be allocated at the target
8401 if(regmap_pre[i][hr]==CCREG)
8402 regs[i].regmap_entry[hr]=CCREG;
8404 regs[i].regmap_entry[hr]=-1;
8407 memcpy(regs[i].regmap,current.regmap,sizeof(current.regmap));
8410 if(i>0&&(itype[i-1]==STORE||itype[i-1]==STORELR||(itype[i-1]==C2LS&&opcode[i-1]==0x3a))&&(u_int)imm[i-1]<0x800)
8411 current.waswritten|=1<<rs1[i-1];
8412 current.waswritten&=~(1<<rt1[i]);
8413 current.waswritten&=~(1<<rt2[i]);
8414 if((itype[i]==STORE||itype[i]==STORELR||(itype[i]==C2LS&&opcode[i]==0x3a))&&(u_int)imm[i]>=0x800)
8415 current.waswritten&=~(1<<rs1[i]);
8417 /* Branch post-alloc */
8420 current.was32=current.is32;
8421 current.wasdirty=current.dirty;
8422 switch(itype[i-1]) {
8424 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8425 branch_regs[i-1].isconst=0;
8426 branch_regs[i-1].wasconst=0;
8427 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8428 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8429 alloc_cc(&branch_regs[i-1],i-1);
8430 dirty_reg(&branch_regs[i-1],CCREG);
8431 if(rt1[i-1]==31) { // JAL
8432 alloc_reg(&branch_regs[i-1],i-1,31);
8433 dirty_reg(&branch_regs[i-1],31);
8434 branch_regs[i-1].is32|=1LL<<31;
8436 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8437 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
8440 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8441 branch_regs[i-1].isconst=0;
8442 branch_regs[i-1].wasconst=0;
8443 branch_regs[i-1].u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8444 branch_regs[i-1].uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8445 alloc_cc(&branch_regs[i-1],i-1);
8446 dirty_reg(&branch_regs[i-1],CCREG);
8447 alloc_reg(&branch_regs[i-1],i-1,rs1[i-1]);
8448 if(rt1[i-1]!=0) { // JALR
8449 alloc_reg(&branch_regs[i-1],i-1,rt1[i-1]);
8450 dirty_reg(&branch_regs[i-1],rt1[i-1]);
8451 branch_regs[i-1].is32|=1LL<<rt1[i-1];
8454 if(rs1[i-1]==31) { // JALR
8455 alloc_reg(&branch_regs[i-1],i-1,RHASH);
8456 #ifndef HOST_IMM_ADDR32
8457 alloc_reg(&branch_regs[i-1],i-1,RHTBL);
8461 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8462 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
8465 if((opcode[i-1]&0x3E)==4) // BEQ/BNE
8467 alloc_cc(¤t,i-1);
8468 dirty_reg(¤t,CCREG);
8469 if((rs1[i-1]&&(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]))||
8470 (rs2[i-1]&&(rs2[i-1]==rt1[i]||rs2[i-1]==rt2[i]))) {
8471 // The delay slot overwrote one of our conditions
8472 // Delay slot goes after the test (in order)
8473 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8474 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8475 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8478 delayslot_alloc(¤t,i);
8483 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i-1])|(1LL<<rs2[i-1]));
8484 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i-1])|(1LL<<us2[i-1]));
8485 // Alloc the branch condition registers
8486 if(rs1[i-1]) alloc_reg(¤t,i-1,rs1[i-1]);
8487 if(rs2[i-1]) alloc_reg(¤t,i-1,rs2[i-1]);
8488 if(!((current.is32>>rs1[i-1])&(current.is32>>rs2[i-1])&1))
8490 if(rs1[i-1]) alloc_reg64(¤t,i-1,rs1[i-1]);
8491 if(rs2[i-1]) alloc_reg64(¤t,i-1,rs2[i-1]);
8494 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8495 branch_regs[i-1].isconst=0;
8496 branch_regs[i-1].wasconst=0;
8497 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8498 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
8501 if((opcode[i-1]&0x3E)==6) // BLEZ/BGTZ
8503 alloc_cc(¤t,i-1);
8504 dirty_reg(¤t,CCREG);
8505 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
8506 // The delay slot overwrote the branch condition
8507 // Delay slot goes after the test (in order)
8508 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8509 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8510 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8513 delayslot_alloc(¤t,i);
8518 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8519 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8520 // Alloc the branch condition register
8521 alloc_reg(¤t,i-1,rs1[i-1]);
8522 if(!(current.is32>>rs1[i-1]&1))
8524 alloc_reg64(¤t,i-1,rs1[i-1]);
8527 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8528 branch_regs[i-1].isconst=0;
8529 branch_regs[i-1].wasconst=0;
8530 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8531 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
8534 // Alloc the delay slot in case the branch is taken
8535 if((opcode[i-1]&0x3E)==0x14) // BEQL/BNEL
8537 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8538 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8539 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8540 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8541 alloc_cc(&branch_regs[i-1],i);
8542 dirty_reg(&branch_regs[i-1],CCREG);
8543 delayslot_alloc(&branch_regs[i-1],i);
8544 branch_regs[i-1].isconst=0;
8545 alloc_reg(¤t,i,CCREG); // Not taken path
8546 dirty_reg(¤t,CCREG);
8547 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8550 if((opcode[i-1]&0x3E)==0x16) // BLEZL/BGTZL
8552 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8553 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8554 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8555 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8556 alloc_cc(&branch_regs[i-1],i);
8557 dirty_reg(&branch_regs[i-1],CCREG);
8558 delayslot_alloc(&branch_regs[i-1],i);
8559 branch_regs[i-1].isconst=0;
8560 alloc_reg(¤t,i,CCREG); // Not taken path
8561 dirty_reg(¤t,CCREG);
8562 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8566 //if((opcode2[i-1]&0x1E)==0) // BLTZ/BGEZ
8567 if((opcode2[i-1]&0x0E)==0) // BLTZ/BGEZ
8569 alloc_cc(¤t,i-1);
8570 dirty_reg(¤t,CCREG);
8571 if(rs1[i-1]==rt1[i]||rs1[i-1]==rt2[i]) {
8572 // The delay slot overwrote the branch condition
8573 // Delay slot goes after the test (in order)
8574 current.u=branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i]));
8575 current.uu=branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i]));
8576 if((~current.uu>>rt1[i])&1) current.uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]));
8579 delayslot_alloc(¤t,i);
8584 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8585 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8586 // Alloc the branch condition register
8587 alloc_reg(¤t,i-1,rs1[i-1]);
8588 if(!(current.is32>>rs1[i-1]&1))
8590 alloc_reg64(¤t,i-1,rs1[i-1]);
8593 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8594 branch_regs[i-1].isconst=0;
8595 branch_regs[i-1].wasconst=0;
8596 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8597 memcpy(constmap[i],constmap[i-1],sizeof(current_constmap));
8600 // Alloc the delay slot in case the branch is taken
8601 if((opcode2[i-1]&0x1E)==2) // BLTZL/BGEZL
8603 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8604 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8605 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8606 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8607 alloc_cc(&branch_regs[i-1],i);
8608 dirty_reg(&branch_regs[i-1],CCREG);
8609 delayslot_alloc(&branch_regs[i-1],i);
8610 branch_regs[i-1].isconst=0;
8611 alloc_reg(¤t,i,CCREG); // Not taken path
8612 dirty_reg(¤t,CCREG);
8613 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8615 // FIXME: BLTZAL/BGEZAL
8616 if(opcode2[i-1]&0x10) { // BxxZAL
8617 alloc_reg(&branch_regs[i-1],i-1,31);
8618 dirty_reg(&branch_regs[i-1],31);
8619 branch_regs[i-1].is32|=1LL<<31;
8623 if(likely[i-1]==0) // BC1F/BC1T
8625 alloc_cc(¤t,i-1);
8626 dirty_reg(¤t,CCREG);
8627 if(itype[i]==FCOMP) {
8628 // The delay slot overwrote the branch condition
8629 // Delay slot goes after the test (in order)
8630 delayslot_alloc(¤t,i);
8635 current.u=branch_unneeded_reg[i-1]&~(1LL<<rs1[i-1]);
8636 current.uu=branch_unneeded_reg_upper[i-1]&~(1LL<<us1[i-1]);
8637 // Alloc the branch condition register
8638 alloc_reg(¤t,i-1,FSREG);
8640 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8641 memcpy(&branch_regs[i-1].regmap_entry,¤t.regmap,sizeof(current.regmap));
8645 // Alloc the delay slot in case the branch is taken
8646 memcpy(&branch_regs[i-1],¤t,sizeof(current));
8647 branch_regs[i-1].u=(branch_unneeded_reg[i-1]&~((1LL<<rs1[i])|(1LL<<rs2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8648 branch_regs[i-1].uu=(branch_unneeded_reg_upper[i-1]&~((1LL<<us1[i])|(1LL<<us2[i])|(1LL<<rt1[i])|(1LL<<rt2[i])))|1;
8649 if((~branch_regs[i-1].uu>>rt1[i])&1) branch_regs[i-1].uu&=~((1LL<<dep1[i])|(1LL<<dep2[i]))|1;
8650 alloc_cc(&branch_regs[i-1],i);
8651 dirty_reg(&branch_regs[i-1],CCREG);
8652 delayslot_alloc(&branch_regs[i-1],i);
8653 branch_regs[i-1].isconst=0;
8654 alloc_reg(¤t,i,CCREG); // Not taken path
8655 dirty_reg(¤t,CCREG);
8656 memcpy(&branch_regs[i-1].regmap_entry,&branch_regs[i-1].regmap,sizeof(current.regmap));
8661 if(itype[i-1]==UJUMP||itype[i-1]==RJUMP||(source[i-1]>>16)==0x1000)
8663 if(rt1[i-1]==31) // JAL/JALR
8665 // Subroutine call will return here, don't alloc any registers
8668 clear_all_regs(current.regmap);
8669 alloc_reg(¤t,i,CCREG);
8670 dirty_reg(¤t,CCREG);
8674 // Internal branch will jump here, match registers to caller
8675 current.is32=0x3FFFFFFFFLL;
8677 clear_all_regs(current.regmap);
8678 alloc_reg(¤t,i,CCREG);
8679 dirty_reg(¤t,CCREG);
8682 if(ba[j]==start+i*4+4) {
8683 memcpy(current.regmap,branch_regs[j].regmap,sizeof(current.regmap));
8684 current.is32=branch_regs[j].is32;
8685 current.dirty=branch_regs[j].dirty;
8690 if(ba[j]==start+i*4+4) {
8691 for(hr=0;hr<HOST_REGS;hr++) {
8692 if(current.regmap[hr]!=branch_regs[j].regmap[hr]) {
8693 current.regmap[hr]=-1;
8695 current.is32&=branch_regs[j].is32;
8696 current.dirty&=branch_regs[j].dirty;
8705 // Count cycles in between branches
8707 if(i>0&&(itype[i-1]==RJUMP||itype[i-1]==UJUMP||itype[i-1]==CJUMP||itype[i-1]==SJUMP||itype[i-1]==FJUMP||itype[i]==SYSCALL||itype[i]==HLECALL))
8711 #if !defined(DRC_DBG)
8712 else if(itype[i]==C2OP&>e_cycletab[source[i]&0x3f]>2)
8714 // GTE runs in parallel until accessed, divide by 2 for a rough guess
8715 cc+=gte_cycletab[source[i]&0x3f]/2;
8717 else if(/*itype[i]==LOAD||itype[i]==STORE||*/itype[i]==C1LS) // load,store causes weird timing issues
8719 cc+=2; // 2 cycle penalty (after CLOCK_DIVIDER)
8721 else if(i>1&&itype[i]==STORE&&itype[i-1]==STORE&&itype[i-2]==STORE&&!bt[i])
8725 else if(itype[i]==C2LS)
8735 flush_dirty_uppers(¤t);
8737 regs[i].is32=current.is32;
8738 regs[i].dirty=current.dirty;
8739 regs[i].isconst=current.isconst;
8740 memcpy(constmap[i],current_constmap,sizeof(current_constmap));
8742 for(hr=0;hr<HOST_REGS;hr++) {
8743 if(hr!=EXCLUDE_REG&®s[i].regmap[hr]>=0) {
8744 if(regmap_pre[i][hr]!=regs[i].regmap[hr]) {
8745 regs[i].wasconst&=~(1<<hr);
8749 if(current.regmap[HOST_BTREG]==BTREG) current.regmap[HOST_BTREG]=-1;
8750 regs[i].waswritten=current.waswritten;
8753 /* Pass 4 - Cull unused host registers */
8757 for (i=slen-1;i>=0;i--)
8760 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
8762 if(ba[i]<start || ba[i]>=(start+slen*4))
8764 // Branch out of this block, don't need anything
8770 // Need whatever matches the target
8772 int t=(ba[i]-start)>>2;
8773 for(hr=0;hr<HOST_REGS;hr++)
8775 if(regs[i].regmap_entry[hr]>=0) {
8776 if(regs[i].regmap_entry[hr]==regs[t].regmap_entry[hr]) nr|=1<<hr;
8780 // Conditional branch may need registers for following instructions
8781 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
8784 nr|=needed_reg[i+2];
8785 for(hr=0;hr<HOST_REGS;hr++)
8787 if(regmap_pre[i+2][hr]>=0&&get_reg(regs[i+2].regmap_entry,regmap_pre[i+2][hr])<0) nr&=~(1<<hr);
8788 //if((regmap_entry[i+2][hr])>=0) if(!((nr>>hr)&1)) printf("%x-bogus(%d=%d)\n",start+i*4,hr,regmap_entry[i+2][hr]);
8792 // Don't need stuff which is overwritten
8793 //if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8794 //if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8795 // Merge in delay slot
8796 for(hr=0;hr<HOST_REGS;hr++)
8799 // These are overwritten unless the branch is "likely"
8800 // and the delay slot is nullified if not taken
8801 if(rt1[i+1]&&rt1[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8802 if(rt2[i+1]&&rt2[i+1]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8804 if(us1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8805 if(us2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8806 if(rs1[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
8807 if(rs2[i+1]==regmap_pre[i][hr]) nr|=1<<hr;
8808 if(us1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8809 if(us2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8810 if(rs1[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8811 if(rs2[i+1]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8812 if(dep1[i+1]&&!((unneeded_reg_upper[i]>>dep1[i+1])&1)) {
8813 if(dep1[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8814 if(dep2[i+1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8816 if(dep2[i+1]&&!((unneeded_reg_upper[i]>>dep2[i+1])&1)) {
8817 if(dep1[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8818 if(dep2[i+1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8820 if(itype[i+1]==STORE || itype[i+1]==STORELR || (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) {
8821 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8822 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8826 else if(itype[i]==SYSCALL||itype[i]==HLECALL||itype[i]==INTCALL)
8828 // SYSCALL instruction (software interrupt)
8831 else if(itype[i]==COP0 && (source[i]&0x3f)==0x18)
8833 // ERET instruction (return from interrupt)
8839 for(hr=0;hr<HOST_REGS;hr++) {
8840 if(regmap_pre[i+1][hr]>=0&&get_reg(regs[i+1].regmap_entry,regmap_pre[i+1][hr])<0) nr&=~(1<<hr);
8841 if(regs[i].regmap[hr]!=regmap_pre[i+1][hr]) nr&=~(1<<hr);
8842 if(regs[i].regmap[hr]!=regmap_pre[i][hr]) nr&=~(1<<hr);
8843 if(regs[i].regmap[hr]<0) nr&=~(1<<hr);
8847 for(hr=0;hr<HOST_REGS;hr++)
8849 // Overwritten registers are not needed
8850 if(rt1[i]&&rt1[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8851 if(rt2[i]&&rt2[i]==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8852 if(FTEMP==(regs[i].regmap[hr]&63)) nr&=~(1<<hr);
8853 // Source registers are needed
8854 if(us1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8855 if(us2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8856 if(rs1[i]==regmap_pre[i][hr]) nr|=1<<hr;
8857 if(rs2[i]==regmap_pre[i][hr]) nr|=1<<hr;
8858 if(us1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8859 if(us2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8860 if(rs1[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8861 if(rs2[i]==regs[i].regmap_entry[hr]) nr|=1<<hr;
8862 if(dep1[i]&&!((unneeded_reg_upper[i]>>dep1[i])&1)) {
8863 if(dep1[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8864 if(dep1[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8866 if(dep2[i]&&!((unneeded_reg_upper[i]>>dep2[i])&1)) {
8867 if(dep2[i]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8868 if(dep2[i]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8870 if(itype[i]==STORE || itype[i]==STORELR || (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) {
8871 if(regmap_pre[i][hr]==INVCP) nr|=1<<hr;
8872 if(regs[i].regmap_entry[hr]==INVCP) nr|=1<<hr;
8874 // Don't store a register immediately after writing it,
8875 // may prevent dual-issue.
8876 // But do so if this is a branch target, otherwise we
8877 // might have to load the register before the branch.
8878 if(i>0&&!bt[i]&&((regs[i].wasdirty>>hr)&1)) {
8879 if((regmap_pre[i][hr]>0&®map_pre[i][hr]<64&&!((unneeded_reg[i]>>regmap_pre[i][hr])&1)) ||
8880 (regmap_pre[i][hr]>64&&!((unneeded_reg_upper[i]>>(regmap_pre[i][hr]&63))&1)) ) {
8881 if(rt1[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8882 if(rt2[i-1]==(regmap_pre[i][hr]&63)) nr|=1<<hr;
8884 if((regs[i].regmap_entry[hr]>0&®s[i].regmap_entry[hr]<64&&!((unneeded_reg[i]>>regs[i].regmap_entry[hr])&1)) ||
8885 (regs[i].regmap_entry[hr]>64&&!((unneeded_reg_upper[i]>>(regs[i].regmap_entry[hr]&63))&1)) ) {
8886 if(rt1[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8887 if(rt2[i-1]==(regs[i].regmap_entry[hr]&63)) nr|=1<<hr;
8891 // Cycle count is needed at branches. Assume it is needed at the target too.
8892 if(i==0||bt[i]||itype[i]==CJUMP||itype[i]==FJUMP||itype[i]==SPAN) {
8893 if(regmap_pre[i][HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8894 if(regs[i].regmap_entry[HOST_CCREG]==CCREG) nr|=1<<HOST_CCREG;
8899 // Deallocate unneeded registers
8900 for(hr=0;hr<HOST_REGS;hr++)
8903 if(regs[i].regmap_entry[hr]!=CCREG) regs[i].regmap_entry[hr]=-1;
8904 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
8905 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
8906 (regs[i].regmap[hr]&63)!=PTEMP && (regs[i].regmap[hr]&63)!=CCREG)
8908 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
8911 regs[i].regmap[hr]=-1;
8912 regs[i].isconst&=~(1<<hr);
8914 regmap_pre[i+2][hr]=-1;
8915 regs[i+2].wasconst&=~(1<<hr);
8920 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
8922 int d1=0,d2=0,map=0,temp=0;
8923 if(get_reg(regs[i].regmap,rt1[i+1]|64)>=0||get_reg(branch_regs[i].regmap,rt1[i+1]|64)>=0)
8928 if(itype[i+1]==STORE || itype[i+1]==STORELR ||
8929 (opcode[i+1]&0x3b)==0x39 || (opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
8932 if(itype[i+1]==LOADLR || itype[i+1]==STORELR ||
8933 itype[i+1]==C1LS || itype[i+1]==C2LS)
8935 if((regs[i].regmap[hr]&63)!=rs1[i] && (regs[i].regmap[hr]&63)!=rs2[i] &&
8936 (regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
8937 (regs[i].regmap[hr]&63)!=rt1[i+1] && (regs[i].regmap[hr]&63)!=rt2[i+1] &&
8938 (regs[i].regmap[hr]^64)!=us1[i+1] && (regs[i].regmap[hr]^64)!=us2[i+1] &&
8939 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
8940 regs[i].regmap[hr]!=rs1[i+1] && regs[i].regmap[hr]!=rs2[i+1] &&
8941 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=PTEMP &&
8942 regs[i].regmap[hr]!=RHASH && regs[i].regmap[hr]!=RHTBL &&
8943 regs[i].regmap[hr]!=RTEMP && regs[i].regmap[hr]!=CCREG &&
8944 regs[i].regmap[hr]!=map )
8946 regs[i].regmap[hr]=-1;
8947 regs[i].isconst&=~(1<<hr);
8948 if((branch_regs[i].regmap[hr]&63)!=rs1[i] && (branch_regs[i].regmap[hr]&63)!=rs2[i] &&
8949 (branch_regs[i].regmap[hr]&63)!=rt1[i] && (branch_regs[i].regmap[hr]&63)!=rt2[i] &&
8950 (branch_regs[i].regmap[hr]&63)!=rt1[i+1] && (branch_regs[i].regmap[hr]&63)!=rt2[i+1] &&
8951 (branch_regs[i].regmap[hr]^64)!=us1[i+1] && (branch_regs[i].regmap[hr]^64)!=us2[i+1] &&
8952 (branch_regs[i].regmap[hr]^64)!=d1 && (branch_regs[i].regmap[hr]^64)!=d2 &&
8953 branch_regs[i].regmap[hr]!=rs1[i+1] && branch_regs[i].regmap[hr]!=rs2[i+1] &&
8954 (branch_regs[i].regmap[hr]&63)!=temp && branch_regs[i].regmap[hr]!=PTEMP &&
8955 branch_regs[i].regmap[hr]!=RHASH && branch_regs[i].regmap[hr]!=RHTBL &&
8956 branch_regs[i].regmap[hr]!=RTEMP && branch_regs[i].regmap[hr]!=CCREG &&
8957 branch_regs[i].regmap[hr]!=map)
8959 branch_regs[i].regmap[hr]=-1;
8960 branch_regs[i].regmap_entry[hr]=-1;
8961 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000)
8963 if(!likely[i]&&i<slen-2) {
8964 regmap_pre[i+2][hr]=-1;
8965 regs[i+2].wasconst&=~(1<<hr);
8976 int d1=0,d2=0,map=-1,temp=-1;
8977 if(get_reg(regs[i].regmap,rt1[i]|64)>=0)
8982 if(itype[i]==STORE || itype[i]==STORELR ||
8983 (opcode[i]&0x3b)==0x39 || (opcode[i]&0x3b)==0x3a) { // SWC1/SDC1 || SWC2/SDC2
8986 if(itype[i]==LOADLR || itype[i]==STORELR ||
8987 itype[i]==C1LS || itype[i]==C2LS)
8989 if((regs[i].regmap[hr]&63)!=rt1[i] && (regs[i].regmap[hr]&63)!=rt2[i] &&
8990 (regs[i].regmap[hr]^64)!=us1[i] && (regs[i].regmap[hr]^64)!=us2[i] &&
8991 (regs[i].regmap[hr]^64)!=d1 && (regs[i].regmap[hr]^64)!=d2 &&
8992 regs[i].regmap[hr]!=rs1[i] && regs[i].regmap[hr]!=rs2[i] &&
8993 (regs[i].regmap[hr]&63)!=temp && regs[i].regmap[hr]!=map &&
8994 (itype[i]!=SPAN||regs[i].regmap[hr]!=CCREG))
8996 if(i<slen-1&&!is_ds[i]) {
8997 if(regmap_pre[i+1][hr]!=-1 || regs[i].regmap[hr]!=-1)
8998 if(regmap_pre[i+1][hr]!=regs[i].regmap[hr])
8999 if(regs[i].regmap[hr]<64||!((regs[i].was32>>(regs[i].regmap[hr]&63))&1))
9001 SysPrintf("fail: %x (%d %d!=%d)\n",start+i*4,hr,regmap_pre[i+1][hr],regs[i].regmap[hr]);
9002 assert(regmap_pre[i+1][hr]==regs[i].regmap[hr]);
9004 regmap_pre[i+1][hr]=-1;
9005 if(regs[i+1].regmap_entry[hr]==CCREG) regs[i+1].regmap_entry[hr]=-1;
9006 regs[i+1].wasconst&=~(1<<hr);
9008 regs[i].regmap[hr]=-1;
9009 regs[i].isconst&=~(1<<hr);
9017 /* Pass 5 - Pre-allocate registers */
9019 // If a register is allocated during a loop, try to allocate it for the
9020 // entire loop, if possible. This avoids loading/storing registers
9021 // inside of the loop.
9023 signed char f_regmap[HOST_REGS];
9024 clear_all_regs(f_regmap);
9025 for(i=0;i<slen-1;i++)
9027 if(itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9029 if(ba[i]>=start && ba[i]<(start+i*4))
9030 if(itype[i+1]==NOP||itype[i+1]==MOV||itype[i+1]==ALU
9031 ||itype[i+1]==SHIFTIMM||itype[i+1]==IMM16||itype[i+1]==LOAD
9032 ||itype[i+1]==STORE||itype[i+1]==STORELR||itype[i+1]==C1LS
9033 ||itype[i+1]==SHIFT||itype[i+1]==COP1||itype[i+1]==FLOAT
9034 ||itype[i+1]==FCOMP||itype[i+1]==FCONV
9035 ||itype[i+1]==COP2||itype[i+1]==C2LS||itype[i+1]==C2OP)
9037 int t=(ba[i]-start)>>2;
9038 if(t>0&&(itype[t-1]!=UJUMP&&itype[t-1]!=RJUMP&&itype[t-1]!=CJUMP&&itype[t-1]!=SJUMP&&itype[t-1]!=FJUMP)) // loop_preload can't handle jumps into delay slots
9039 if(t<2||(itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||rt1[t-2]!=31) // call/ret assumes no registers allocated
9040 for(hr=0;hr<HOST_REGS;hr++)
9042 if(regs[i].regmap[hr]>64) {
9043 if(!((regs[i].dirty>>hr)&1))
9044 f_regmap[hr]=regs[i].regmap[hr];
9045 else f_regmap[hr]=-1;
9047 else if(regs[i].regmap[hr]>=0) {
9048 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9049 // dealloc old register
9051 for(n=0;n<HOST_REGS;n++)
9053 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9055 // and alloc new one
9056 f_regmap[hr]=regs[i].regmap[hr];
9059 if(branch_regs[i].regmap[hr]>64) {
9060 if(!((branch_regs[i].dirty>>hr)&1))
9061 f_regmap[hr]=branch_regs[i].regmap[hr];
9062 else f_regmap[hr]=-1;
9064 else if(branch_regs[i].regmap[hr]>=0) {
9065 if(f_regmap[hr]!=branch_regs[i].regmap[hr]) {
9066 // dealloc old register
9068 for(n=0;n<HOST_REGS;n++)
9070 if(f_regmap[n]==branch_regs[i].regmap[hr]) {f_regmap[n]=-1;}
9072 // and alloc new one
9073 f_regmap[hr]=branch_regs[i].regmap[hr];
9077 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1])
9078 f_regmap[hr]=branch_regs[i].regmap[hr];
9080 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1])
9081 f_regmap[hr]=branch_regs[i].regmap[hr];
9083 // Avoid dirty->clean transition
9084 #ifdef DESTRUCTIVE_WRITEBACK
9085 if(t>0) if(get_reg(regmap_pre[t],f_regmap[hr])>=0) if((regs[t].wasdirty>>get_reg(regmap_pre[t],f_regmap[hr]))&1) f_regmap[hr]=-1;
9087 // This check is only strictly required in the DESTRUCTIVE_WRITEBACK
9088 // case above, however it's always a good idea. We can't hoist the
9089 // load if the register was already allocated, so there's no point
9090 // wasting time analyzing most of these cases. It only "succeeds"
9091 // when the mapping was different and the load can be replaced with
9092 // a mov, which is of negligible benefit. So such cases are
9094 if(f_regmap[hr]>0) {
9095 if(regs[t].regmap[hr]==f_regmap[hr]||(regs[t].regmap_entry[hr]<0&&get_reg(regmap_pre[t],f_regmap[hr])<0)) {
9099 //printf("Test %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9100 if(r<34&&((unneeded_reg[j]>>r)&1)) break;
9101 if(r>63&&((unneeded_reg_upper[j]>>(r&63))&1)) break;
9103 // NB This can exclude the case where the upper-half
9104 // register is lower numbered than the lower-half
9105 // register. Not sure if it's worth fixing...
9106 if(get_reg(regs[j].regmap,r&63)<0) break;
9107 if(get_reg(regs[j].regmap_entry,r&63)<0) break;
9108 if(regs[j].is32&(1LL<<(r&63))) break;
9110 if(regs[j].regmap[hr]==f_regmap[hr]&&(f_regmap[hr]&63)<TEMPREG) {
9111 //printf("Hit %x -> %x, %x %d/%d\n",start+i*4,ba[i],start+j*4,hr,r);
9113 if(regs[i].regmap[hr]==-1&&branch_regs[i].regmap[hr]==-1) {
9114 if(get_reg(regs[i+2].regmap,f_regmap[hr])>=0) break;
9116 if(get_reg(regs[i].regmap,r&63)<0) break;
9117 if(get_reg(branch_regs[i].regmap,r&63)<0) break;
9120 while(k>1&®s[k-1].regmap[hr]==-1) {
9121 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9122 //printf("no free regs for store %x\n",start+(k-1)*4);
9125 if(get_reg(regs[k-1].regmap,f_regmap[hr])>=0) {
9126 //printf("no-match due to different register\n");
9129 if(itype[k-2]==UJUMP||itype[k-2]==RJUMP||itype[k-2]==CJUMP||itype[k-2]==SJUMP||itype[k-2]==FJUMP) {
9130 //printf("no-match due to branch\n");
9133 // call/ret fast path assumes no registers allocated
9134 if(k>2&&(itype[k-3]==UJUMP||itype[k-3]==RJUMP)&&rt1[k-3]==31) {
9138 // NB This can exclude the case where the upper-half
9139 // register is lower numbered than the lower-half
9140 // register. Not sure if it's worth fixing...
9141 if(get_reg(regs[k-1].regmap,r&63)<0) break;
9142 if(regs[k-1].is32&(1LL<<(r&63))) break;
9147 if((regs[k].is32&(1LL<<f_regmap[hr]))!=
9148 (regs[i+2].was32&(1LL<<f_regmap[hr]))) {
9149 //printf("bad match after branch\n");
9153 if(regs[k-1].regmap[hr]==f_regmap[hr]&®map_pre[k][hr]==f_regmap[hr]) {
9154 //printf("Extend r%d, %x ->\n",hr,start+k*4);
9156 regs[k].regmap_entry[hr]=f_regmap[hr];
9157 regs[k].regmap[hr]=f_regmap[hr];
9158 regmap_pre[k+1][hr]=f_regmap[hr];
9159 regs[k].wasdirty&=~(1<<hr);
9160 regs[k].dirty&=~(1<<hr);
9161 regs[k].wasdirty|=(1<<hr)®s[k-1].dirty;
9162 regs[k].dirty|=(1<<hr)®s[k].wasdirty;
9163 regs[k].wasconst&=~(1<<hr);
9164 regs[k].isconst&=~(1<<hr);
9169 //printf("Fail Extend r%d, %x ->\n",hr,start+k*4);
9172 assert(regs[i-1].regmap[hr]==f_regmap[hr]);
9173 if(regs[i-1].regmap[hr]==f_regmap[hr]&®map_pre[i][hr]==f_regmap[hr]) {
9174 //printf("OK fill %x (r%d)\n",start+i*4,hr);
9175 regs[i].regmap_entry[hr]=f_regmap[hr];
9176 regs[i].regmap[hr]=f_regmap[hr];
9177 regs[i].wasdirty&=~(1<<hr);
9178 regs[i].dirty&=~(1<<hr);
9179 regs[i].wasdirty|=(1<<hr)®s[i-1].dirty;
9180 regs[i].dirty|=(1<<hr)®s[i-1].dirty;
9181 regs[i].wasconst&=~(1<<hr);
9182 regs[i].isconst&=~(1<<hr);
9183 branch_regs[i].regmap_entry[hr]=f_regmap[hr];
9184 branch_regs[i].wasdirty&=~(1<<hr);
9185 branch_regs[i].wasdirty|=(1<<hr)®s[i].dirty;
9186 branch_regs[i].regmap[hr]=f_regmap[hr];
9187 branch_regs[i].dirty&=~(1<<hr);
9188 branch_regs[i].dirty|=(1<<hr)®s[i].dirty;
9189 branch_regs[i].wasconst&=~(1<<hr);
9190 branch_regs[i].isconst&=~(1<<hr);
9191 if(itype[i]!=RJUMP&&itype[i]!=UJUMP&&(source[i]>>16)!=0x1000) {
9192 regmap_pre[i+2][hr]=f_regmap[hr];
9193 regs[i+2].wasdirty&=~(1<<hr);
9194 regs[i+2].wasdirty|=(1<<hr)®s[i].dirty;
9195 assert((branch_regs[i].is32&(1LL<<f_regmap[hr]))==
9196 (regs[i+2].was32&(1LL<<f_regmap[hr])));
9201 // Alloc register clean at beginning of loop,
9202 // but may dirty it in pass 6
9203 regs[k].regmap_entry[hr]=f_regmap[hr];
9204 regs[k].regmap[hr]=f_regmap[hr];
9205 regs[k].dirty&=~(1<<hr);
9206 regs[k].wasconst&=~(1<<hr);
9207 regs[k].isconst&=~(1<<hr);
9208 if(itype[k]==UJUMP||itype[k]==RJUMP||itype[k]==CJUMP||itype[k]==SJUMP||itype[k]==FJUMP) {
9209 branch_regs[k].regmap_entry[hr]=f_regmap[hr];
9210 branch_regs[k].regmap[hr]=f_regmap[hr];
9211 branch_regs[k].dirty&=~(1<<hr);
9212 branch_regs[k].wasconst&=~(1<<hr);
9213 branch_regs[k].isconst&=~(1<<hr);
9214 if(itype[k]!=RJUMP&&itype[k]!=UJUMP&&(source[k]>>16)!=0x1000) {
9215 regmap_pre[k+2][hr]=f_regmap[hr];
9216 regs[k+2].wasdirty&=~(1<<hr);
9217 assert((branch_regs[k].is32&(1LL<<f_regmap[hr]))==
9218 (regs[k+2].was32&(1LL<<f_regmap[hr])));
9223 regmap_pre[k+1][hr]=f_regmap[hr];
9224 regs[k+1].wasdirty&=~(1<<hr);
9227 if(regs[j].regmap[hr]==f_regmap[hr])
9228 regs[j].regmap_entry[hr]=f_regmap[hr];
9232 if(regs[j].regmap[hr]>=0)
9234 if(get_reg(regs[j].regmap,f_regmap[hr])>=0) {
9235 //printf("no-match due to different register\n");
9238 if((regs[j+1].is32&(1LL<<f_regmap[hr]))!=(regs[j].is32&(1LL<<f_regmap[hr]))) {
9239 //printf("32/64 mismatch %x %d\n",start+j*4,hr);
9242 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9244 // Stop on unconditional branch
9247 if(itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP)
9250 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1])
9253 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1])
9256 if(get_reg(branch_regs[j].regmap,f_regmap[hr])>=0) {
9257 //printf("no-match due to different register (branch)\n");
9261 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9262 //printf("No free regs for store %x\n",start+j*4);
9265 if(f_regmap[hr]>=64) {
9266 if(regs[j].is32&(1LL<<(f_regmap[hr]&63))) {
9271 if(get_reg(regs[j].regmap,f_regmap[hr]&63)<0) {
9282 // Non branch or undetermined branch target
9283 for(hr=0;hr<HOST_REGS;hr++)
9285 if(hr!=EXCLUDE_REG) {
9286 if(regs[i].regmap[hr]>64) {
9287 if(!((regs[i].dirty>>hr)&1))
9288 f_regmap[hr]=regs[i].regmap[hr];
9290 else if(regs[i].regmap[hr]>=0) {
9291 if(f_regmap[hr]!=regs[i].regmap[hr]) {
9292 // dealloc old register
9294 for(n=0;n<HOST_REGS;n++)
9296 if(f_regmap[n]==regs[i].regmap[hr]) {f_regmap[n]=-1;}
9298 // and alloc new one
9299 f_regmap[hr]=regs[i].regmap[hr];
9304 // Try to restore cycle count at branch targets
9306 for(j=i;j<slen-1;j++) {
9307 if(regs[j].regmap[HOST_CCREG]!=-1) break;
9308 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) {
9309 //printf("no free regs for store %x\n",start+j*4);
9313 if(regs[j].regmap[HOST_CCREG]==CCREG) {
9315 //printf("Extend CC, %x -> %x\n",start+k*4,start+j*4);
9317 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9318 regs[k].regmap[HOST_CCREG]=CCREG;
9319 regmap_pre[k+1][HOST_CCREG]=CCREG;
9320 regs[k+1].wasdirty|=1<<HOST_CCREG;
9321 regs[k].dirty|=1<<HOST_CCREG;
9322 regs[k].wasconst&=~(1<<HOST_CCREG);
9323 regs[k].isconst&=~(1<<HOST_CCREG);
9326 regs[j].regmap_entry[HOST_CCREG]=CCREG;
9328 // Work backwards from the branch target
9329 if(j>i&&f_regmap[HOST_CCREG]==CCREG)
9331 //printf("Extend backwards\n");
9334 while(regs[k-1].regmap[HOST_CCREG]==-1) {
9335 if(count_free_regs(regs[k-1].regmap)<=minimum_free_regs[k-1]) {
9336 //printf("no free regs for store %x\n",start+(k-1)*4);
9341 if(regs[k-1].regmap[HOST_CCREG]==CCREG) {
9342 //printf("Extend CC, %x ->\n",start+k*4);
9344 regs[k].regmap_entry[HOST_CCREG]=CCREG;
9345 regs[k].regmap[HOST_CCREG]=CCREG;
9346 regmap_pre[k+1][HOST_CCREG]=CCREG;
9347 regs[k+1].wasdirty|=1<<HOST_CCREG;
9348 regs[k].dirty|=1<<HOST_CCREG;
9349 regs[k].wasconst&=~(1<<HOST_CCREG);
9350 regs[k].isconst&=~(1<<HOST_CCREG);
9355 //printf("Fail Extend CC, %x ->\n",start+k*4);
9359 if(itype[i]!=STORE&&itype[i]!=STORELR&&itype[i]!=C1LS&&itype[i]!=SHIFT&&
9360 itype[i]!=NOP&&itype[i]!=MOV&&itype[i]!=ALU&&itype[i]!=SHIFTIMM&&
9361 itype[i]!=IMM16&&itype[i]!=LOAD&&itype[i]!=COP1&&itype[i]!=FLOAT&&
9362 itype[i]!=FCONV&&itype[i]!=FCOMP)
9364 memcpy(f_regmap,regs[i].regmap,sizeof(f_regmap));
9369 // Cache memory offset or tlb map pointer if a register is available
9370 #ifndef HOST_IMM_ADDR32
9375 int earliest_available[HOST_REGS];
9376 int loop_start[HOST_REGS];
9377 int score[HOST_REGS];
9382 for(hr=0;hr<HOST_REGS;hr++) {
9383 score[hr]=0;earliest_available[hr]=0;
9384 loop_start[hr]=MAXBLOCK;
9386 for(i=0;i<slen-1;i++)
9388 // Can't do anything if no registers are available
9389 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i]) {
9390 for(hr=0;hr<HOST_REGS;hr++) {
9391 score[hr]=0;earliest_available[hr]=i+1;
9392 loop_start[hr]=MAXBLOCK;
9395 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9397 if(count_free_regs(branch_regs[i].regmap)<=minimum_free_regs[i+1]) {
9398 for(hr=0;hr<HOST_REGS;hr++) {
9399 score[hr]=0;earliest_available[hr]=i+1;
9400 loop_start[hr]=MAXBLOCK;
9404 if(count_free_regs(regs[i].regmap)<=minimum_free_regs[i+1]) {
9405 for(hr=0;hr<HOST_REGS;hr++) {
9406 score[hr]=0;earliest_available[hr]=i+1;
9407 loop_start[hr]=MAXBLOCK;
9412 // Mark unavailable registers
9413 for(hr=0;hr<HOST_REGS;hr++) {
9414 if(regs[i].regmap[hr]>=0) {
9415 score[hr]=0;earliest_available[hr]=i+1;
9416 loop_start[hr]=MAXBLOCK;
9418 if(itype[i]==UJUMP||itype[i]==RJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9419 if(branch_regs[i].regmap[hr]>=0) {
9420 score[hr]=0;earliest_available[hr]=i+2;
9421 loop_start[hr]=MAXBLOCK;
9425 // No register allocations after unconditional jumps
9426 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
9428 for(hr=0;hr<HOST_REGS;hr++) {
9429 score[hr]=0;earliest_available[hr]=i+2;
9430 loop_start[hr]=MAXBLOCK;
9432 i++; // Skip delay slot too
9433 //printf("skip delay slot: %x\n",start+i*4);
9437 if(itype[i]==LOAD||itype[i]==LOADLR||
9438 itype[i]==STORE||itype[i]==STORELR||itype[i]==C1LS) {
9439 for(hr=0;hr<HOST_REGS;hr++) {
9440 if(hr!=EXCLUDE_REG) {
9442 for(j=i;j<slen-1;j++) {
9443 if(regs[j].regmap[hr]>=0) break;
9444 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9445 if(branch_regs[j].regmap[hr]>=0) break;
9447 if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j+1]) break;
9449 if(count_free_regs(branch_regs[j].regmap)<=minimum_free_regs[j+1]) break;
9452 else if(count_free_regs(regs[j].regmap)<=minimum_free_regs[j]) break;
9453 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9454 int t=(ba[j]-start)>>2;
9455 if(t<j&&t>=earliest_available[hr]) {
9456 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) { // call/ret assumes no registers allocated
9457 // Score a point for hoisting loop invariant
9458 if(t<loop_start[hr]) loop_start[hr]=t;
9459 //printf("set loop_start: i=%x j=%x (%x)\n",start+i*4,start+j*4,start+t*4);
9465 if(regs[t].regmap[hr]==reg) {
9466 // Score a point if the branch target matches this register
9471 if(itype[j+1]==LOAD||itype[j+1]==LOADLR||
9472 itype[j+1]==STORE||itype[j+1]==STORELR||itype[j+1]==C1LS) {
9477 if(itype[j]==UJUMP||itype[j]==RJUMP||(source[j]>>16)==0x1000)
9479 // Stop on unconditional branch
9483 if(itype[j]==LOAD||itype[j]==LOADLR||
9484 itype[j]==STORE||itype[j]==STORELR||itype[j]==C1LS) {
9491 // Find highest score and allocate that register
9493 for(hr=0;hr<HOST_REGS;hr++) {
9494 if(hr!=EXCLUDE_REG) {
9495 if(score[hr]>score[maxscore]) {
9497 //printf("highest score: %d %d (%x->%x)\n",score[hr],hr,start+i*4,start+end[hr]*4);
9501 if(score[maxscore]>1)
9503 if(i<loop_start[maxscore]) loop_start[maxscore]=i;
9504 for(j=loop_start[maxscore];j<slen&&j<=end[maxscore];j++) {
9505 //if(regs[j].regmap[maxscore]>=0) {printf("oops: %x %x was %d=%d\n",loop_start[maxscore]*4+start,j*4+start,maxscore,regs[j].regmap[maxscore]);}
9506 assert(regs[j].regmap[maxscore]<0);
9507 if(j>loop_start[maxscore]) regs[j].regmap_entry[maxscore]=reg;
9508 regs[j].regmap[maxscore]=reg;
9509 regs[j].dirty&=~(1<<maxscore);
9510 regs[j].wasconst&=~(1<<maxscore);
9511 regs[j].isconst&=~(1<<maxscore);
9512 if(itype[j]==UJUMP||itype[j]==RJUMP||itype[j]==CJUMP||itype[j]==SJUMP||itype[j]==FJUMP) {
9513 branch_regs[j].regmap[maxscore]=reg;
9514 branch_regs[j].wasdirty&=~(1<<maxscore);
9515 branch_regs[j].dirty&=~(1<<maxscore);
9516 branch_regs[j].wasconst&=~(1<<maxscore);
9517 branch_regs[j].isconst&=~(1<<maxscore);
9518 if(itype[j]!=RJUMP&&itype[j]!=UJUMP&&(source[j]>>16)!=0x1000) {
9519 regmap_pre[j+2][maxscore]=reg;
9520 regs[j+2].wasdirty&=~(1<<maxscore);
9522 // loop optimization (loop_preload)
9523 int t=(ba[j]-start)>>2;
9524 if(t==loop_start[maxscore]) {
9525 if(t==1||(t>1&&itype[t-2]!=UJUMP&&itype[t-2]!=RJUMP)||(t>1&&rt1[t-2]!=31)) // call/ret assumes no registers allocated
9526 regs[t].regmap_entry[maxscore]=reg;
9531 if(j<1||(itype[j-1]!=RJUMP&&itype[j-1]!=UJUMP&&itype[j-1]!=CJUMP&&itype[j-1]!=SJUMP&&itype[j-1]!=FJUMP)) {
9532 regmap_pre[j+1][maxscore]=reg;
9533 regs[j+1].wasdirty&=~(1<<maxscore);
9538 if(itype[j-1]==RJUMP||itype[j-1]==UJUMP||itype[j-1]==CJUMP||itype[j-1]==SJUMP||itype[j-1]==FJUMP) i++; // skip delay slot
9539 for(hr=0;hr<HOST_REGS;hr++) {
9540 score[hr]=0;earliest_available[hr]=i+i;
9541 loop_start[hr]=MAXBLOCK;
9549 // This allocates registers (if possible) one instruction prior
9550 // to use, which can avoid a load-use penalty on certain CPUs.
9551 for(i=0;i<slen-1;i++)
9553 if(!i||(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP))
9557 if(itype[i]==ALU||itype[i]==MOV||itype[i]==LOAD||itype[i]==SHIFTIMM||itype[i]==IMM16
9558 ||((itype[i]==COP1||itype[i]==COP2)&&opcode2[i]<3))
9561 if((hr=get_reg(regs[i+1].regmap,rs1[i+1]))>=0)
9563 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9565 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9566 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9567 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9568 regs[i].isconst&=~(1<<hr);
9569 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9570 constmap[i][hr]=constmap[i+1][hr];
9571 regs[i+1].wasdirty&=~(1<<hr);
9572 regs[i].dirty&=~(1<<hr);
9577 if((hr=get_reg(regs[i+1].regmap,rs2[i+1]))>=0)
9579 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9581 regs[i].regmap[hr]=regs[i+1].regmap[hr];
9582 regmap_pre[i+1][hr]=regs[i+1].regmap[hr];
9583 regs[i+1].regmap_entry[hr]=regs[i+1].regmap[hr];
9584 regs[i].isconst&=~(1<<hr);
9585 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9586 constmap[i][hr]=constmap[i+1][hr];
9587 regs[i+1].wasdirty&=~(1<<hr);
9588 regs[i].dirty&=~(1<<hr);
9592 // Preload target address for load instruction (non-constant)
9593 if(itype[i+1]==LOAD&&rs1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9594 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9596 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9598 regs[i].regmap[hr]=rs1[i+1];
9599 regmap_pre[i+1][hr]=rs1[i+1];
9600 regs[i+1].regmap_entry[hr]=rs1[i+1];
9601 regs[i].isconst&=~(1<<hr);
9602 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9603 constmap[i][hr]=constmap[i+1][hr];
9604 regs[i+1].wasdirty&=~(1<<hr);
9605 regs[i].dirty&=~(1<<hr);
9609 // Load source into target register
9610 if(lt1[i+1]&&get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9611 if((hr=get_reg(regs[i+1].regmap,rt1[i+1]))>=0)
9613 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9615 regs[i].regmap[hr]=rs1[i+1];
9616 regmap_pre[i+1][hr]=rs1[i+1];
9617 regs[i+1].regmap_entry[hr]=rs1[i+1];
9618 regs[i].isconst&=~(1<<hr);
9619 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9620 constmap[i][hr]=constmap[i+1][hr];
9621 regs[i+1].wasdirty&=~(1<<hr);
9622 regs[i].dirty&=~(1<<hr);
9626 // Address for store instruction (non-constant)
9627 if(itype[i+1]==STORE||itype[i+1]==STORELR
9628 ||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SB/SH/SW/SD/SWC1/SDC1/SWC2/SDC2
9629 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9630 hr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1);
9631 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9632 else {regs[i+1].regmap[hr]=AGEN1+((i+1)&1);regs[i+1].isconst&=~(1<<hr);}
9634 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9636 regs[i].regmap[hr]=rs1[i+1];
9637 regmap_pre[i+1][hr]=rs1[i+1];
9638 regs[i+1].regmap_entry[hr]=rs1[i+1];
9639 regs[i].isconst&=~(1<<hr);
9640 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9641 constmap[i][hr]=constmap[i+1][hr];
9642 regs[i+1].wasdirty&=~(1<<hr);
9643 regs[i].dirty&=~(1<<hr);
9647 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) { // LWC1/LDC1, LWC2/LDC2
9648 if(get_reg(regs[i+1].regmap,rs1[i+1])<0) {
9650 hr=get_reg(regs[i+1].regmap,FTEMP);
9652 if(regs[i].regmap[hr]<0&®s[i+1].regmap_entry[hr]<0)
9654 regs[i].regmap[hr]=rs1[i+1];
9655 regmap_pre[i+1][hr]=rs1[i+1];
9656 regs[i+1].regmap_entry[hr]=rs1[i+1];
9657 regs[i].isconst&=~(1<<hr);
9658 regs[i].isconst|=regs[i+1].isconst&(1<<hr);
9659 constmap[i][hr]=constmap[i+1][hr];
9660 regs[i+1].wasdirty&=~(1<<hr);
9661 regs[i].dirty&=~(1<<hr);
9663 else if((nr=get_reg2(regs[i].regmap,regs[i+1].regmap,-1))>=0)
9665 // move it to another register
9666 regs[i+1].regmap[hr]=-1;
9667 regmap_pre[i+2][hr]=-1;
9668 regs[i+1].regmap[nr]=FTEMP;
9669 regmap_pre[i+2][nr]=FTEMP;
9670 regs[i].regmap[nr]=rs1[i+1];
9671 regmap_pre[i+1][nr]=rs1[i+1];
9672 regs[i+1].regmap_entry[nr]=rs1[i+1];
9673 regs[i].isconst&=~(1<<nr);
9674 regs[i+1].isconst&=~(1<<nr);
9675 regs[i].dirty&=~(1<<nr);
9676 regs[i+1].wasdirty&=~(1<<nr);
9677 regs[i+1].dirty&=~(1<<nr);
9678 regs[i+2].wasdirty&=~(1<<nr);
9682 if(itype[i+1]==LOAD||itype[i+1]==LOADLR||itype[i+1]==STORE||itype[i+1]==STORELR/*||itype[i+1]==C1LS||||itype[i+1]==C2LS*/) {
9683 if(itype[i+1]==LOAD)
9684 hr=get_reg(regs[i+1].regmap,rt1[i+1]);
9685 if(itype[i+1]==LOADLR||(opcode[i+1]&0x3b)==0x31||(opcode[i+1]&0x3b)==0x32) // LWC1/LDC1, LWC2/LDC2
9686 hr=get_reg(regs[i+1].regmap,FTEMP);
9687 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a) { // SWC1/SDC1/SWC2/SDC2
9688 hr=get_reg(regs[i+1].regmap,AGEN1+((i+1)&1));
9689 if(hr<0) hr=get_reg(regs[i+1].regmap,-1);
9691 if(hr>=0&®s[i].regmap[hr]<0) {
9692 int rs=get_reg(regs[i+1].regmap,rs1[i+1]);
9693 if(rs>=0&&((regs[i+1].wasconst>>rs)&1)) {
9694 regs[i].regmap[hr]=AGEN1+((i+1)&1);
9695 regmap_pre[i+1][hr]=AGEN1+((i+1)&1);
9696 regs[i+1].regmap_entry[hr]=AGEN1+((i+1)&1);
9697 regs[i].isconst&=~(1<<hr);
9698 regs[i+1].wasdirty&=~(1<<hr);
9699 regs[i].dirty&=~(1<<hr);
9708 /* Pass 6 - Optimize clean/dirty state */
9709 clean_registers(0,slen-1,1);
9711 /* Pass 7 - Identify 32-bit registers */
9712 for (i=slen-1;i>=0;i--)
9714 if(itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9716 // Conditional branch
9717 if((source[i]>>16)!=0x1000&&i<slen-2) {
9718 // Mark this address as a branch target since it may be called
9719 // upon return from interrupt
9725 if(itype[slen-1]==SPAN) {
9726 bt[slen-1]=1; // Mark as a branch target so instruction can restart after exception
9730 /* Debug/disassembly */
9735 for(r=1;r<=CCREG;r++) {
9736 if((unneeded_reg[i]>>r)&1) {
9737 if(r==HIREG) printf(" HI");
9738 else if(r==LOREG) printf(" LO");
9739 else printf(" r%d",r);
9743 #if defined(__i386__) || defined(__x86_64__)
9744 printf("pre: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7]);
9747 printf("pre: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regmap_pre[i][0],regmap_pre[i][1],regmap_pre[i][2],regmap_pre[i][3],regmap_pre[i][4],regmap_pre[i][5],regmap_pre[i][6],regmap_pre[i][7],regmap_pre[i][8],regmap_pre[i][9],regmap_pre[i][10],regmap_pre[i][12]);
9750 if(needed_reg[i]&1) printf("eax ");
9751 if((needed_reg[i]>>1)&1) printf("ecx ");
9752 if((needed_reg[i]>>2)&1) printf("edx ");
9753 if((needed_reg[i]>>3)&1) printf("ebx ");
9754 if((needed_reg[i]>>5)&1) printf("ebp ");
9755 if((needed_reg[i]>>6)&1) printf("esi ");
9756 if((needed_reg[i]>>7)&1) printf("edi ");
9758 #if defined(__i386__) || defined(__x86_64__)
9759 printf("entry: eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7]);
9761 if(regs[i].wasdirty&1) printf("eax ");
9762 if((regs[i].wasdirty>>1)&1) printf("ecx ");
9763 if((regs[i].wasdirty>>2)&1) printf("edx ");
9764 if((regs[i].wasdirty>>3)&1) printf("ebx ");
9765 if((regs[i].wasdirty>>5)&1) printf("ebp ");
9766 if((regs[i].wasdirty>>6)&1) printf("esi ");
9767 if((regs[i].wasdirty>>7)&1) printf("edi ");
9770 printf("entry: r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d\n",regs[i].regmap_entry[0],regs[i].regmap_entry[1],regs[i].regmap_entry[2],regs[i].regmap_entry[3],regs[i].regmap_entry[4],regs[i].regmap_entry[5],regs[i].regmap_entry[6],regs[i].regmap_entry[7],regs[i].regmap_entry[8],regs[i].regmap_entry[9],regs[i].regmap_entry[10],regs[i].regmap_entry[12]);
9772 if(regs[i].wasdirty&1) printf("r0 ");
9773 if((regs[i].wasdirty>>1)&1) printf("r1 ");
9774 if((regs[i].wasdirty>>2)&1) printf("r2 ");
9775 if((regs[i].wasdirty>>3)&1) printf("r3 ");
9776 if((regs[i].wasdirty>>4)&1) printf("r4 ");
9777 if((regs[i].wasdirty>>5)&1) printf("r5 ");
9778 if((regs[i].wasdirty>>6)&1) printf("r6 ");
9779 if((regs[i].wasdirty>>7)&1) printf("r7 ");
9780 if((regs[i].wasdirty>>8)&1) printf("r8 ");
9781 if((regs[i].wasdirty>>9)&1) printf("r9 ");
9782 if((regs[i].wasdirty>>10)&1) printf("r10 ");
9783 if((regs[i].wasdirty>>12)&1) printf("r12 ");
9786 disassemble_inst(i);
9787 //printf ("ccadj[%d] = %d\n",i,ccadj[i]);
9788 #if defined(__i386__) || defined(__x86_64__)
9789 printf("eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7]);
9790 if(regs[i].dirty&1) printf("eax ");
9791 if((regs[i].dirty>>1)&1) printf("ecx ");
9792 if((regs[i].dirty>>2)&1) printf("edx ");
9793 if((regs[i].dirty>>3)&1) printf("ebx ");
9794 if((regs[i].dirty>>5)&1) printf("ebp ");
9795 if((regs[i].dirty>>6)&1) printf("esi ");
9796 if((regs[i].dirty>>7)&1) printf("edi ");
9799 printf("r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",regs[i].regmap[0],regs[i].regmap[1],regs[i].regmap[2],regs[i].regmap[3],regs[i].regmap[4],regs[i].regmap[5],regs[i].regmap[6],regs[i].regmap[7],regs[i].regmap[8],regs[i].regmap[9],regs[i].regmap[10],regs[i].regmap[12]);
9800 if(regs[i].dirty&1) printf("r0 ");
9801 if((regs[i].dirty>>1)&1) printf("r1 ");
9802 if((regs[i].dirty>>2)&1) printf("r2 ");
9803 if((regs[i].dirty>>3)&1) printf("r3 ");
9804 if((regs[i].dirty>>4)&1) printf("r4 ");
9805 if((regs[i].dirty>>5)&1) printf("r5 ");
9806 if((regs[i].dirty>>6)&1) printf("r6 ");
9807 if((regs[i].dirty>>7)&1) printf("r7 ");
9808 if((regs[i].dirty>>8)&1) printf("r8 ");
9809 if((regs[i].dirty>>9)&1) printf("r9 ");
9810 if((regs[i].dirty>>10)&1) printf("r10 ");
9811 if((regs[i].dirty>>12)&1) printf("r12 ");
9814 if(regs[i].isconst) {
9815 printf("constants: ");
9816 #if defined(__i386__) || defined(__x86_64__)
9817 if(regs[i].isconst&1) printf("eax=%x ",(int)constmap[i][0]);
9818 if((regs[i].isconst>>1)&1) printf("ecx=%x ",(int)constmap[i][1]);
9819 if((regs[i].isconst>>2)&1) printf("edx=%x ",(int)constmap[i][2]);
9820 if((regs[i].isconst>>3)&1) printf("ebx=%x ",(int)constmap[i][3]);
9821 if((regs[i].isconst>>5)&1) printf("ebp=%x ",(int)constmap[i][5]);
9822 if((regs[i].isconst>>6)&1) printf("esi=%x ",(int)constmap[i][6]);
9823 if((regs[i].isconst>>7)&1) printf("edi=%x ",(int)constmap[i][7]);
9826 if(regs[i].isconst&1) printf("r0=%x ",(int)constmap[i][0]);
9827 if((regs[i].isconst>>1)&1) printf("r1=%x ",(int)constmap[i][1]);
9828 if((regs[i].isconst>>2)&1) printf("r2=%x ",(int)constmap[i][2]);
9829 if((regs[i].isconst>>3)&1) printf("r3=%x ",(int)constmap[i][3]);
9830 if((regs[i].isconst>>4)&1) printf("r4=%x ",(int)constmap[i][4]);
9831 if((regs[i].isconst>>5)&1) printf("r5=%x ",(int)constmap[i][5]);
9832 if((regs[i].isconst>>6)&1) printf("r6=%x ",(int)constmap[i][6]);
9833 if((regs[i].isconst>>7)&1) printf("r7=%x ",(int)constmap[i][7]);
9834 if((regs[i].isconst>>8)&1) printf("r8=%x ",(int)constmap[i][8]);
9835 if((regs[i].isconst>>9)&1) printf("r9=%x ",(int)constmap[i][9]);
9836 if((regs[i].isconst>>10)&1) printf("r10=%x ",(int)constmap[i][10]);
9837 if((regs[i].isconst>>12)&1) printf("r12=%x ",(int)constmap[i][12]);
9841 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP) {
9842 #if defined(__i386__) || defined(__x86_64__)
9843 printf("branch(%d): eax=%d ecx=%d edx=%d ebx=%d ebp=%d esi=%d edi=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7]);
9844 if(branch_regs[i].dirty&1) printf("eax ");
9845 if((branch_regs[i].dirty>>1)&1) printf("ecx ");
9846 if((branch_regs[i].dirty>>2)&1) printf("edx ");
9847 if((branch_regs[i].dirty>>3)&1) printf("ebx ");
9848 if((branch_regs[i].dirty>>5)&1) printf("ebp ");
9849 if((branch_regs[i].dirty>>6)&1) printf("esi ");
9850 if((branch_regs[i].dirty>>7)&1) printf("edi ");
9853 printf("branch(%d): r0=%d r1=%d r2=%d r3=%d r4=%d r5=%d r6=%d r7=%d r8=%d r9=%d r10=%d r12=%d dirty: ",i,branch_regs[i].regmap[0],branch_regs[i].regmap[1],branch_regs[i].regmap[2],branch_regs[i].regmap[3],branch_regs[i].regmap[4],branch_regs[i].regmap[5],branch_regs[i].regmap[6],branch_regs[i].regmap[7],branch_regs[i].regmap[8],branch_regs[i].regmap[9],branch_regs[i].regmap[10],branch_regs[i].regmap[12]);
9854 if(branch_regs[i].dirty&1) printf("r0 ");
9855 if((branch_regs[i].dirty>>1)&1) printf("r1 ");
9856 if((branch_regs[i].dirty>>2)&1) printf("r2 ");
9857 if((branch_regs[i].dirty>>3)&1) printf("r3 ");
9858 if((branch_regs[i].dirty>>4)&1) printf("r4 ");
9859 if((branch_regs[i].dirty>>5)&1) printf("r5 ");
9860 if((branch_regs[i].dirty>>6)&1) printf("r6 ");
9861 if((branch_regs[i].dirty>>7)&1) printf("r7 ");
9862 if((branch_regs[i].dirty>>8)&1) printf("r8 ");
9863 if((branch_regs[i].dirty>>9)&1) printf("r9 ");
9864 if((branch_regs[i].dirty>>10)&1) printf("r10 ");
9865 if((branch_regs[i].dirty>>12)&1) printf("r12 ");
9871 /* Pass 8 - Assembly */
9872 linkcount=0;stubcount=0;
9873 ds=0;is_delayslot=0;
9875 uint64_t is32_pre=0;
9877 void *beginning=start_block();
9882 void *instr_addr0_override = NULL;
9884 if (start == 0x80030000) {
9885 // nasty hack for fastbios thing
9886 // override block entry to this code
9887 instr_addr0_override = out;
9888 emit_movimm(start,0);
9889 // abuse io address var as a flag that we
9890 // have already returned here once
9891 emit_readword((int)&address,1);
9892 emit_writeword(0,(int)&pcaddr);
9893 emit_writeword(0,(int)&address);
9895 emit_jne((int)new_dyna_leave);
9899 //if(ds) printf("ds: ");
9900 disassemble_inst(i);
9902 ds=0; // Skip delay slot
9903 if(bt[i]) assem_debug("OOPS - branch into delay slot\n");
9904 instr_addr[i] = NULL;
9906 speculate_register_values(i);
9907 #ifndef DESTRUCTIVE_WRITEBACK
9908 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
9910 wb_valid(regmap_pre[i],regs[i].regmap_entry,dirty_pre,regs[i].wasdirty,is32_pre,
9911 unneeded_reg[i],unneeded_reg_upper[i]);
9913 if((itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)&&!likely[i]) {
9914 is32_pre=branch_regs[i].is32;
9915 dirty_pre=branch_regs[i].dirty;
9917 is32_pre=regs[i].is32;
9918 dirty_pre=regs[i].dirty;
9922 if(i<2||(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000))
9924 wb_invalidate(regmap_pre[i],regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32,
9925 unneeded_reg[i],unneeded_reg_upper[i]);
9926 loop_preload(regmap_pre[i],regs[i].regmap_entry);
9928 // branch target entry point
9929 instr_addr[i] = out;
9930 assem_debug("<->\n");
9931 drc_dbg_emit_do_cmp(i);
9934 if(regs[i].regmap_entry[HOST_CCREG]==CCREG&®s[i].regmap[HOST_CCREG]!=CCREG)
9935 wb_register(CCREG,regs[i].regmap_entry,regs[i].wasdirty,regs[i].was32);
9936 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i],rs2[i]);
9937 address_generation(i,®s[i],regs[i].regmap_entry);
9938 load_consts(regmap_pre[i],regs[i].regmap,regs[i].was32,i);
9939 if(itype[i]==RJUMP||itype[i]==UJUMP||itype[i]==CJUMP||itype[i]==SJUMP||itype[i]==FJUMP)
9941 // Load the delay slot registers if necessary
9942 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i]&&(rs1[i+1]!=rt1[i]||rt1[i]==0))
9943 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
9944 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i]&&(rs2[i+1]!=rt1[i]||rt1[i]==0))
9945 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
9946 if(itype[i+1]==STORE||itype[i+1]==STORELR||(opcode[i+1]&0x3b)==0x39||(opcode[i+1]&0x3b)==0x3a)
9947 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
9951 // Preload registers for following instruction
9952 if(rs1[i+1]!=rs1[i]&&rs1[i+1]!=rs2[i])
9953 if(rs1[i+1]!=rt1[i]&&rs1[i+1]!=rt2[i])
9954 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs1[i+1],rs1[i+1]);
9955 if(rs2[i+1]!=rs1[i+1]&&rs2[i+1]!=rs1[i]&&rs2[i+1]!=rs2[i])
9956 if(rs2[i+1]!=rt1[i]&&rs2[i+1]!=rt2[i])
9957 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,rs2[i+1],rs2[i+1]);
9959 // TODO: if(is_ooo(i)) address_generation(i+1);
9960 if(itype[i]==CJUMP||itype[i]==FJUMP)
9961 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,CCREG,CCREG);
9962 if(itype[i]==STORE||itype[i]==STORELR||(opcode[i]&0x3b)==0x39||(opcode[i]&0x3b)==0x3a)
9963 load_regs(regs[i].regmap_entry,regs[i].regmap,regs[i].was32,INVCP,INVCP);
9964 if(bt[i]) cop1_usable=0;
9968 alu_assemble(i,®s[i]);break;
9970 imm16_assemble(i,®s[i]);break;
9972 shift_assemble(i,®s[i]);break;
9974 shiftimm_assemble(i,®s[i]);break;
9976 load_assemble(i,®s[i]);break;
9978 loadlr_assemble(i,®s[i]);break;
9980 store_assemble(i,®s[i]);break;
9982 storelr_assemble(i,®s[i]);break;
9984 cop0_assemble(i,®s[i]);break;
9986 cop1_assemble(i,®s[i]);break;
9988 c1ls_assemble(i,®s[i]);break;
9990 cop2_assemble(i,®s[i]);break;
9992 c2ls_assemble(i,®s[i]);break;
9994 c2op_assemble(i,®s[i]);break;
9996 fconv_assemble(i,®s[i]);break;
9998 float_assemble(i,®s[i]);break;
10000 fcomp_assemble(i,®s[i]);break;
10002 multdiv_assemble(i,®s[i]);break;
10004 mov_assemble(i,®s[i]);break;
10006 syscall_assemble(i,®s[i]);break;
10008 hlecall_assemble(i,®s[i]);break;
10010 intcall_assemble(i,®s[i]);break;
10012 ujump_assemble(i,®s[i]);ds=1;break;
10014 rjump_assemble(i,®s[i]);ds=1;break;
10016 cjump_assemble(i,®s[i]);ds=1;break;
10018 sjump_assemble(i,®s[i]);ds=1;break;
10020 fjump_assemble(i,®s[i]);ds=1;break;
10022 pagespan_assemble(i,®s[i]);break;
10024 if(itype[i]==UJUMP||itype[i]==RJUMP||(source[i]>>16)==0x1000)
10025 literal_pool(1024);
10027 literal_pool_jumpover(256);
10030 //assert(itype[i-2]==UJUMP||itype[i-2]==RJUMP||(source[i-2]>>16)==0x1000);
10031 // If the block did not end with an unconditional branch,
10032 // add a jump to the next instruction.
10034 if(itype[i-2]!=UJUMP&&itype[i-2]!=RJUMP&&(source[i-2]>>16)!=0x1000&&itype[i-1]!=SPAN) {
10035 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10037 if(itype[i-2]!=CJUMP&&itype[i-2]!=SJUMP&&itype[i-2]!=FJUMP) {
10038 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10039 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10040 emit_loadreg(CCREG,HOST_CCREG);
10041 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
10043 else if(!likely[i-2])
10045 store_regs_bt(branch_regs[i-2].regmap,branch_regs[i-2].is32,branch_regs[i-2].dirty,start+i*4);
10046 assert(branch_regs[i-2].regmap[HOST_CCREG]==CCREG);
10050 store_regs_bt(regs[i-2].regmap,regs[i-2].is32,regs[i-2].dirty,start+i*4);
10051 assert(regs[i-2].regmap[HOST_CCREG]==CCREG);
10053 add_to_linker((int)out,start+i*4,0);
10060 assert(itype[i-1]!=UJUMP&&itype[i-1]!=CJUMP&&itype[i-1]!=SJUMP&&itype[i-1]!=RJUMP&&itype[i-1]!=FJUMP);
10061 store_regs_bt(regs[i-1].regmap,regs[i-1].is32,regs[i-1].dirty,start+i*4);
10062 if(regs[i-1].regmap[HOST_CCREG]!=CCREG)
10063 emit_loadreg(CCREG,HOST_CCREG);
10064 emit_addimm(HOST_CCREG,CLOCK_ADJUST(ccadj[i-1]+1),HOST_CCREG);
10065 add_to_linker((int)out,start+i*4,0);
10069 // TODO: delay slot stubs?
10071 for(i=0;i<stubcount;i++)
10073 switch(stubs[i].type)
10081 do_readstub(i);break;
10086 do_writestub(i);break;
10088 do_ccstub(i);break;
10090 do_invstub(i);break;
10092 do_cop1stub(i);break;
10094 do_unalignedwritestub(i);break;
10098 if (instr_addr0_override)
10099 instr_addr[0] = instr_addr0_override;
10101 /* Pass 9 - Linker */
10102 for(i=0;i<linkcount;i++)
10104 assem_debug("%8x -> %8x\n",link_addr[i][0],link_addr[i][1]);
10106 if(!link_addr[i][2])
10109 void *addr=check_addr(link_addr[i][1]);
10110 emit_extjump(link_addr[i][0],link_addr[i][1]);
10112 set_jump_target(link_addr[i][0], addr);
10113 add_link(link_addr[i][1],stub);
10115 else set_jump_target(link_addr[i][0], stub);
10120 int target=(link_addr[i][1]-start)>>2;
10121 assert(target>=0&&target<slen);
10122 assert(instr_addr[target]);
10123 //#ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10124 //set_jump_target_fillslot(link_addr[i][0],instr_addr[target],link_addr[i][2]>>1);
10126 set_jump_target(link_addr[i][0],instr_addr[target]);
10130 // External Branch Targets (jump_in)
10131 if(copy+slen*4>(void *)shadow+sizeof(shadow)) copy=shadow;
10132 for(i=0;i<slen;i++)
10136 if(instr_addr[i]) // TODO - delay slots (=null)
10138 u_int vaddr=start+i*4;
10139 u_int page=get_page(vaddr);
10140 u_int vpage=get_vpage(vaddr);
10143 assem_debug("%p (%d) <- %8x\n",instr_addr[i],i,start+i*4);
10144 assem_debug("jump_in: %x\n",start+i*4);
10145 ll_add(jump_dirty+vpage,vaddr,out);
10146 void *entry_point = do_dirty_stub(i);
10147 ll_add_flags(jump_in+page,vaddr,state_rflags,entry_point);
10148 // If there was an existing entry in the hash table,
10149 // replace it with the new address.
10150 // Don't add new entries. We'll insert the
10151 // ones that actually get used in check_addr().
10152 struct ht_entry *ht_bin = hash_table_get(vaddr);
10153 if (ht_bin->vaddr[0] == vaddr)
10154 ht_bin->tcaddr[0] = entry_point;
10155 if (ht_bin->vaddr[1] == vaddr)
10156 ht_bin->tcaddr[1] = entry_point;
10161 // Write out the literal pool if necessary
10163 #ifdef CORTEX_A8_BRANCH_PREDICTION_HACK
10165 if(((u_int)out)&7) emit_addnop(13);
10167 assert((u_int)out-(u_int)beginning<MAX_OUTPUT_BLOCK_SIZE);
10168 //printf("shadow buffer: %x-%x\n",(int)copy,(int)copy+slen*4);
10169 memcpy(copy,source,slen*4);
10172 end_block(beginning);
10174 // If we're within 256K of the end of the buffer,
10175 // start over from the beginning. (Is 256K enough?)
10176 if((u_int)out>(u_int)BASE_ADDR+(1<<TARGET_SIZE_2)-MAX_OUTPUT_BLOCK_SIZE) out=(u_char *)BASE_ADDR;
10178 // Trap writes to any of the pages we compiled
10179 for(i=start>>12;i<=(start+slen*4)>>12;i++) {
10182 inv_code_start=inv_code_end=~0;
10184 // for PCSX we need to mark all mirrors too
10185 if(get_page(start)<(RAM_SIZE>>12))
10186 for(i=start>>12;i<=(start+slen*4)>>12;i++)
10187 invalid_code[((u_int)0x00000000>>12)|(i&0x1ff)]=
10188 invalid_code[((u_int)0x80000000>>12)|(i&0x1ff)]=
10189 invalid_code[((u_int)0xa0000000>>12)|(i&0x1ff)]=0;
10191 /* Pass 10 - Free memory by expiring oldest blocks */
10193 int end=((((int)out-(int)BASE_ADDR)>>(TARGET_SIZE_2-16))+16384)&65535;
10194 while(expirep!=end)
10196 int shift=TARGET_SIZE_2-3; // Divide into 8 blocks
10197 uintptr_t base=(uintptr_t)BASE_ADDR+((expirep>>13)<<shift); // Base address of this block
10198 inv_debug("EXP: Phase %d\n",expirep);
10199 switch((expirep>>11)&3)
10202 // Clear jump_in and jump_dirty
10203 ll_remove_matching_addrs(jump_in+(expirep&2047),base,shift);
10204 ll_remove_matching_addrs(jump_dirty+(expirep&2047),base,shift);
10205 ll_remove_matching_addrs(jump_in+2048+(expirep&2047),base,shift);
10206 ll_remove_matching_addrs(jump_dirty+2048+(expirep&2047),base,shift);
10210 ll_kill_pointers(jump_out[expirep&2047],base,shift);
10211 ll_kill_pointers(jump_out[(expirep&2047)+2048],base,shift);
10214 // Clear hash table
10215 for(i=0;i<32;i++) {
10216 struct ht_entry *ht_bin = &hash_table[((expirep&2047)<<5)+i];
10217 if (((uintptr_t)ht_bin->tcaddr[1]>>shift) == (base>>shift) ||
10218 (((uintptr_t)ht_bin->tcaddr[1]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10219 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[1],ht_bin->tcaddr[1]);
10220 ht_bin->vaddr[1] = -1;
10221 ht_bin->tcaddr[1] = NULL;
10223 if (((uintptr_t)ht_bin->tcaddr[0]>>shift) == (base>>shift) ||
10224 (((uintptr_t)ht_bin->tcaddr[0]-MAX_OUTPUT_BLOCK_SIZE)>>shift)==(base>>shift)) {
10225 inv_debug("EXP: Remove hash %x -> %p\n",ht_bin->vaddr[0],ht_bin->tcaddr[0]);
10226 ht_bin->vaddr[0] = ht_bin->vaddr[1];
10227 ht_bin->tcaddr[0] = ht_bin->tcaddr[1];
10228 ht_bin->vaddr[1] = -1;
10229 ht_bin->tcaddr[1] = NULL;
10236 if((expirep&2047)==0)
10239 ll_remove_matching_addrs(jump_out+(expirep&2047),base,shift);
10240 ll_remove_matching_addrs(jump_out+2048+(expirep&2047),base,shift);
10243 expirep=(expirep+1)&65535;
10248 // vim:shiftwidth=2:expandtab