2 * (C) GraÅžvydas "notaz" Ignotas, 2010-2011
4 * This work is licensed under the terms of GNU GPL version 2 or later.
5 * See the COPYING file in the top-level directory.
16 //#define memprintf printf
17 #define memprintf(...)
19 static u8 unmapped_mem[0x1000];
26 static void write_mem_dummy(u32 data)
28 memprintf("unmapped w %08x, %08x @%08x %u\n", address, data, psxRegs.pc, psxRegs.cycle);
32 static u32 io_read_sio16()
34 return sioRead8() | (sioRead8() << 8);
37 static u32 io_read_sio32()
39 return sioRead8() | (sioRead8() << 8) | (sioRead8() << 16) | (sioRead8() << 24);
42 static void io_write_sio16(u32 value)
44 sioWrite8((unsigned char)value);
45 sioWrite8((unsigned char)(value>>8));
48 static void io_write_sio32(u32 value)
50 sioWrite8((unsigned char)value);
51 sioWrite8((unsigned char)(value >> 8));
52 sioWrite8((unsigned char)(value >> 16));
53 sioWrite8((unsigned char)(value >> 24));
56 #define make_rcnt_funcs(i) \
57 static u32 io_rcnt_read_count##i() { return psxRcntRcount(i); } \
58 static u32 io_rcnt_read_mode##i() { return psxRcntRmode(i); } \
59 static u32 io_rcnt_read_target##i() { return psxRcntRtarget(i); } \
60 static void io_rcnt_write_count##i(u32 val) { psxRcntWcount(i, val & 0xffff); } \
61 static void io_rcnt_write_mode##i(u32 val) { psxRcntWmode(i, val); } \
62 static void io_rcnt_write_target##i(u32 val) { psxRcntWtarget(i, val & 0xffff); }
68 static void io_write_ireg16(u32 value)
70 if (Config.Sio) psxHu16ref(0x1070) |= 0x80;
71 if (Config.SpuIrq) psxHu16ref(0x1070) |= 0x200;
72 psxHu16ref(0x1070) &= psxHu16(0x1074) & value;
75 static void io_write_imask16(u32 value)
77 psxHu16ref(0x1074) = value;
78 if (psxHu16ref(0x1070) & value)
79 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
82 static void io_write_ireg32(u32 value)
84 if (Config.Sio) psxHu32ref(0x1070) |= 0x80;
85 if (Config.SpuIrq) psxHu32ref(0x1070) |= 0x200;
86 psxHu32ref(0x1070) &= psxHu32(0x1074) & value;
89 static void io_write_imask32(u32 value)
91 psxHu32ref(0x1074) = value;
92 if (psxHu32ref(0x1070) & value)
93 new_dyna_set_event(PSXINT_NEWDRC_CHECK, 1);
96 static void io_write_dma_icr32(u32 value)
98 u32 tmp = value & 0x00ff803f;
99 tmp |= (SWAPu32(HW_DMA_ICR) & ~value) & 0x7f000000;
100 if ((tmp & HW_DMA_ICR_GLOBAL_ENABLE && tmp & 0x7f000000)
101 || tmp & HW_DMA_ICR_BUS_ERROR) {
102 if (!(SWAPu32(HW_DMA_ICR) & HW_DMA_ICR_IRQ_SENT))
103 psxHu32ref(0x1070) |= SWAP32(8);
104 tmp |= HW_DMA_ICR_IRQ_SENT;
106 HW_DMA_ICR = SWAPu32(tmp);
109 #define make_dma_func(n) \
110 static void io_write_chcr##n(u32 value) \
112 HW_DMA##n##_CHCR = value; \
113 if (value & 0x01000000 && HW_DMA_PCR & (8 << (n * 4))) { \
114 psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, value); \
125 static void io_spu_write16(u32 value)
128 SPU_writeRegister(address, value);
131 static void io_spu_write32(u32 value)
133 SPUwriteRegister wfunc = SPU_writeRegister;
136 wfunc(a, value & 0xffff);
137 wfunc(a + 2, value >> 16);
140 static u32 *mem_readtab;
141 static u32 *mem_writetab;
142 static u32 mem_iortab[(1+2+4) * 0x1000 / 4];
143 static u32 mem_iowtab[(1+2+4) * 0x1000 / 4];
144 static u32 mem_ffwtab[(1+2+4) * 0x1000 / 4];
145 //static u32 mem_unmrtab[(1+2+4) * 0x1000 / 4];
146 static u32 mem_unmwtab[(1+2+4) * 0x1000 / 4];
148 static void map_item(u32 *out, const void *h, u32 flag)
152 fprintf(stderr, "%p has LSB set\n", h);
153 *out = (hv >> 1) | (flag << 31);
156 // size must be power of 2, at least 4k
157 #define map_l1_mem(tab, i, addr, size, base) \
158 map_item(&tab[((addr)>>12) + i], (u8 *)(base) - (u32)(addr) - ((i << 12) & ~(size - 1)), 0)
160 #define IOMEM32(a) (((a) & 0xfff) / 4)
161 #define IOMEM16(a) (0x1000/4 + (((a) & 0xfff) / 2))
162 #define IOMEM8(a) (0x1000/4 + 0x1000/2 + ((a) & 0xfff))
164 static void map_ram_write(void)
168 for (i = 0; i < (0x800000 >> 12); i++) {
169 map_l1_mem(mem_writetab, i, 0x80000000, 0x200000, psxM);
170 map_l1_mem(mem_writetab, i, 0x00000000, 0x200000, psxM);
171 map_l1_mem(mem_writetab, i, 0xa0000000, 0x200000, psxM);
175 static void unmap_ram_write(void)
179 for (i = 0; i < (0x800000 >> 12); i++) {
180 map_item(&mem_writetab[0x80000|i], mem_unmwtab, 1);
181 map_item(&mem_writetab[0x00000|i], mem_unmwtab, 1);
182 map_item(&mem_writetab[0xa0000|i], mem_unmwtab, 1);
186 static void write_biu(u32 value)
188 memprintf("write_biu %08x, %08x @%08x %u\n", address, value, psxRegs.pc, psxRegs.cycle);
190 if (address != 0xfffe0130)
194 case 0x800: case 0x804:
197 case 0: case 0x1e988:
201 printf("write_biu: unexpected val: %08x\n", value);
206 void new_dyna_pcsx_mem_init(void)
210 // have to map these further to keep tcache close to .text
211 mem_readtab = mmap((void *)0x08000000, 0x200000 * 4, PROT_READ | PROT_WRITE,
212 MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
213 if (mem_readtab == MAP_FAILED) {
214 fprintf(stderr, "failed to map mem tables\n");
217 mem_writetab = mem_readtab + 0x100000;
223 // 0: direct mem variable
226 // default/unmapped memhandlers
227 for (i = 0; i < 0x100000; i++) {
228 //map_item(&mem_readtab[i], mem_unmrtab, 1);
229 map_l1_mem(mem_readtab, i, 0, 0x1000, unmapped_mem);
230 map_item(&mem_writetab[i], mem_unmwtab, 1);
233 // RAM and it's mirrors
234 for (i = 0; i < (0x800000 >> 12); i++) {
235 map_l1_mem(mem_readtab, i, 0x80000000, 0x200000, psxM);
236 map_l1_mem(mem_readtab, i, 0x00000000, 0x200000, psxM);
237 map_l1_mem(mem_readtab, i, 0xa0000000, 0x200000, psxM);
241 // BIOS and it's mirrors
242 for (i = 0; i < (0x80000 >> 12); i++) {
243 map_l1_mem(mem_readtab, i, 0x1fc00000, 0x80000, psxR);
244 map_l1_mem(mem_readtab, i, 0xbfc00000, 0x80000, psxR);
248 map_l1_mem(mem_readtab, 0, 0x1f800000, 0x1000, psxH);
249 map_l1_mem(mem_writetab, 0, 0x1f800000, 0x1000, psxH);
252 map_item(&mem_readtab[0x1f801000 >> 12], mem_iortab, 1);
253 map_item(&mem_writetab[0x1f801000 >> 12], mem_iowtab, 1);
257 for (i = 0; i < (1+2+4) * 0x1000 / 4; i++)
258 map_item(&mem_unmwtab[i], write_mem_dummy, 1);
261 for (i = 0; i < 0x1000/4; i++) {
262 map_item(&mem_iortab[i], &psxH[0x1000], 0);
263 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
265 for (; i < 0x1000/4 + 0x1000/2; i++) {
266 map_item(&mem_iortab[i], &psxH[0x1000], 0);
267 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
269 for (; i < 0x1000/4 + 0x1000/2 + 0x1000; i++) {
270 map_item(&mem_iortab[i], &psxH[0x1000], 0);
271 map_item(&mem_iowtab[i], &psxH[0x1000], 0);
274 map_item(&mem_iortab[IOMEM32(0x1040)], io_read_sio32, 1);
275 map_item(&mem_iortab[IOMEM32(0x1100)], io_rcnt_read_count0, 1);
276 map_item(&mem_iortab[IOMEM32(0x1104)], io_rcnt_read_mode0, 1);
277 map_item(&mem_iortab[IOMEM32(0x1108)], io_rcnt_read_target0, 1);
278 map_item(&mem_iortab[IOMEM32(0x1110)], io_rcnt_read_count1, 1);
279 map_item(&mem_iortab[IOMEM32(0x1114)], io_rcnt_read_mode1, 1);
280 map_item(&mem_iortab[IOMEM32(0x1118)], io_rcnt_read_target1, 1);
281 map_item(&mem_iortab[IOMEM32(0x1120)], io_rcnt_read_count2, 1);
282 map_item(&mem_iortab[IOMEM32(0x1124)], io_rcnt_read_mode2, 1);
283 map_item(&mem_iortab[IOMEM32(0x1128)], io_rcnt_read_target2, 1);
284 // map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
285 // map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
286 map_item(&mem_iortab[IOMEM32(0x1820)], mdecRead0, 1);
287 map_item(&mem_iortab[IOMEM32(0x1824)], mdecRead1, 1);
289 map_item(&mem_iortab[IOMEM16(0x1040)], io_read_sio16, 1);
290 map_item(&mem_iortab[IOMEM16(0x1044)], sioReadStat16, 1);
291 map_item(&mem_iortab[IOMEM16(0x1048)], sioReadMode16, 1);
292 map_item(&mem_iortab[IOMEM16(0x104a)], sioReadCtrl16, 1);
293 map_item(&mem_iortab[IOMEM16(0x104e)], sioReadBaud16, 1);
294 map_item(&mem_iortab[IOMEM16(0x1100)], io_rcnt_read_count0, 1);
295 map_item(&mem_iortab[IOMEM16(0x1104)], io_rcnt_read_mode0, 1);
296 map_item(&mem_iortab[IOMEM16(0x1108)], io_rcnt_read_target0, 1);
297 map_item(&mem_iortab[IOMEM16(0x1110)], io_rcnt_read_count1, 1);
298 map_item(&mem_iortab[IOMEM16(0x1114)], io_rcnt_read_mode1, 1);
299 map_item(&mem_iortab[IOMEM16(0x1118)], io_rcnt_read_target1, 1);
300 map_item(&mem_iortab[IOMEM16(0x1120)], io_rcnt_read_count2, 1);
301 map_item(&mem_iortab[IOMEM16(0x1124)], io_rcnt_read_mode2, 1);
302 map_item(&mem_iortab[IOMEM16(0x1128)], io_rcnt_read_target2, 1);
304 map_item(&mem_iortab[IOMEM8(0x1040)], sioRead8, 1);
305 map_item(&mem_iortab[IOMEM8(0x1800)], cdrRead0, 1);
306 map_item(&mem_iortab[IOMEM8(0x1801)], cdrRead1, 1);
307 map_item(&mem_iortab[IOMEM8(0x1802)], cdrRead2, 1);
308 map_item(&mem_iortab[IOMEM8(0x1803)], cdrRead3, 1);
311 map_item(&mem_iowtab[IOMEM32(0x1040)], io_write_sio32, 1);
312 map_item(&mem_iowtab[IOMEM32(0x1070)], io_write_ireg32, 1);
313 map_item(&mem_iowtab[IOMEM32(0x1074)], io_write_imask32, 1);
314 map_item(&mem_iowtab[IOMEM32(0x1088)], io_write_chcr0, 1);
315 map_item(&mem_iowtab[IOMEM32(0x1098)], io_write_chcr1, 1);
316 map_item(&mem_iowtab[IOMEM32(0x10a8)], io_write_chcr2, 1);
317 map_item(&mem_iowtab[IOMEM32(0x10b8)], io_write_chcr3, 1);
318 map_item(&mem_iowtab[IOMEM32(0x10c8)], io_write_chcr4, 1);
319 map_item(&mem_iowtab[IOMEM32(0x10e8)], io_write_chcr6, 1);
320 map_item(&mem_iowtab[IOMEM32(0x10f4)], io_write_dma_icr32, 1);
321 map_item(&mem_iowtab[IOMEM32(0x1100)], io_rcnt_write_count0, 1);
322 map_item(&mem_iowtab[IOMEM32(0x1104)], io_rcnt_write_mode0, 1);
323 map_item(&mem_iowtab[IOMEM32(0x1108)], io_rcnt_write_target0, 1);
324 map_item(&mem_iowtab[IOMEM32(0x1110)], io_rcnt_write_count1, 1);
325 map_item(&mem_iowtab[IOMEM32(0x1114)], io_rcnt_write_mode1, 1);
326 map_item(&mem_iowtab[IOMEM32(0x1118)], io_rcnt_write_target1, 1);
327 map_item(&mem_iowtab[IOMEM32(0x1120)], io_rcnt_write_count2, 1);
328 map_item(&mem_iowtab[IOMEM32(0x1124)], io_rcnt_write_mode2, 1);
329 map_item(&mem_iowtab[IOMEM32(0x1128)], io_rcnt_write_target2, 1);
330 // map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
331 // map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);
332 map_item(&mem_iowtab[IOMEM32(0x1820)], mdecWrite0, 1);
333 map_item(&mem_iowtab[IOMEM32(0x1824)], mdecWrite1, 1);
335 map_item(&mem_iowtab[IOMEM16(0x1040)], io_write_sio16, 1);
336 map_item(&mem_iowtab[IOMEM16(0x1044)], sioWriteStat16, 1);
337 map_item(&mem_iowtab[IOMEM16(0x1048)], sioWriteMode16, 1);
338 map_item(&mem_iowtab[IOMEM16(0x104a)], sioWriteCtrl16, 1);
339 map_item(&mem_iowtab[IOMEM16(0x104e)], sioWriteBaud16, 1);
340 map_item(&mem_iowtab[IOMEM16(0x1070)], io_write_ireg16, 1);
341 map_item(&mem_iowtab[IOMEM16(0x1074)], io_write_imask16, 1);
342 map_item(&mem_iowtab[IOMEM16(0x1100)], io_rcnt_write_count0, 1);
343 map_item(&mem_iowtab[IOMEM16(0x1104)], io_rcnt_write_mode0, 1);
344 map_item(&mem_iowtab[IOMEM16(0x1108)], io_rcnt_write_target0, 1);
345 map_item(&mem_iowtab[IOMEM16(0x1110)], io_rcnt_write_count1, 1);
346 map_item(&mem_iowtab[IOMEM16(0x1114)], io_rcnt_write_mode1, 1);
347 map_item(&mem_iowtab[IOMEM16(0x1118)], io_rcnt_write_target1, 1);
348 map_item(&mem_iowtab[IOMEM16(0x1120)], io_rcnt_write_count2, 1);
349 map_item(&mem_iowtab[IOMEM16(0x1124)], io_rcnt_write_mode2, 1);
350 map_item(&mem_iowtab[IOMEM16(0x1128)], io_rcnt_write_target2, 1);
352 map_item(&mem_iowtab[IOMEM8(0x1040)], sioWrite8, 1);
353 map_item(&mem_iowtab[IOMEM8(0x1800)], cdrWrite0, 1);
354 map_item(&mem_iowtab[IOMEM8(0x1801)], cdrWrite1, 1);
355 map_item(&mem_iowtab[IOMEM8(0x1802)], cdrWrite2, 1);
356 map_item(&mem_iowtab[IOMEM8(0x1803)], cdrWrite3, 1);
358 for (i = 0x1c00; i < 0x1e00; i += 2) {
359 map_item(&mem_iowtab[IOMEM16(i)], io_spu_write16, 1);
360 map_item(&mem_iowtab[IOMEM32(i)], io_spu_write32, 1);
364 map_item(&mem_writetab[0xfffe0130 >> 12], mem_ffwtab, 1);
365 for (i = 0; i < 0x1000/4 + 0x1000/2 + 0x1000; i++)
366 map_item(&mem_ffwtab[i], write_biu, 1);
368 mem_rtab = mem_readtab;
369 mem_wtab = mem_writetab;
372 void new_dyna_pcsx_mem_reset(void)
376 // plugins might change so update the pointers
377 map_item(&mem_iortab[IOMEM32(0x1810)], GPU_readData, 1);
378 map_item(&mem_iortab[IOMEM32(0x1814)], GPU_readStatus, 1);
380 for (i = 0x1c00; i < 0x1e00; i += 2)
381 map_item(&mem_iortab[IOMEM16(i)], SPU_readRegister, 1);
383 map_item(&mem_iowtab[IOMEM32(0x1810)], GPU_writeData, 1);
384 map_item(&mem_iowtab[IOMEM32(0x1814)], GPU_writeStatus, 1);