1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
27 /******************************************************************************/
31 Rc0Gate = 0x0001, // 0 not implemented
32 Rc1Gate = 0x0001, // 0 not implemented
33 Rc2Disable = 0x0001, // 0 partially implemented
34 RcUnknown1 = 0x0002, // 1 ?
35 RcUnknown2 = 0x0004, // 2 ?
36 RcCountToTarget = 0x0008, // 3
37 RcIrqOnTarget = 0x0010, // 4
38 RcIrqOnOverflow = 0x0020, // 5
39 RcIrqRegenerate = 0x0040, // 6
40 RcUnknown7 = 0x0080, // 7 ?
41 Rc0PixelClock = 0x0100, // 8 fake implementation
42 Rc1HSyncClock = 0x0100, // 8
43 Rc2Unknown8 = 0x0100, // 8 ?
44 Rc0Unknown9 = 0x0200, // 9 ?
45 Rc1Unknown9 = 0x0200, // 9 ?
46 Rc2OneEighthClock = 0x0200, // 9
47 RcUnknown10 = 0x0400, // 10 ?
48 RcCountEqTarget = 0x0800, // 11
49 RcOverflow = 0x1000, // 12
50 RcUnknown13 = 0x2000, // 13 ? (always zero)
51 RcUnknown14 = 0x4000, // 14 ? (always zero)
52 RcUnknown15 = 0x8000, // 15 ? (always zero)
55 #define CounterQuantity ( 4 )
56 //static const u32 CounterQuantity = 4;
58 static const u32 CountToOverflow = 0;
59 static const u32 CountToTarget = 1;
61 static const u32 FrameRate[] = { 60, 50 };
62 static const u32 VBlankStart[] = { 240, 256 };
63 static const u32 HSyncTotal[] = { 263, 313 };
64 static const u32 SpuUpdInterval[] = { 32, 32 };
66 #define VERBOSE_LEVEL 0
67 static const s32 VerboseLevel = VERBOSE_LEVEL;
69 /******************************************************************************/
71 Rcnt rcnts[ CounterQuantity ];
73 static u32 hSyncCount = 0;
74 static u32 spuSyncCount = 0;
75 static u32 hsync_steps = 0;
76 static u32 gpu_wants_hcnt = 0;
77 static u32 base_cycle = 0;
79 u32 psxNextCounter = 0, psxNextsCounter = 0;
81 /******************************************************************************/
84 void setIrq( u32 irq )
86 psxHu32ref(0x1070) |= SWAPu32(irq);
90 void verboseLog( u32 level, const char *str, ... )
93 if( level <= VerboseLevel )
99 vsprintf( buf, str, va );
108 /******************************************************************************/
111 void _psxRcntWcount( u32 index, u32 value )
115 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
119 rcnts[index].cycleStart = psxRegs.cycle;
120 rcnts[index].cycleStart -= value * rcnts[index].rate;
123 if( value < rcnts[index].target )
125 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
126 rcnts[index].counterState = CountToTarget;
130 rcnts[index].cycle = 0xffff * rcnts[index].rate;
131 rcnts[index].counterState = CountToOverflow;
136 u32 _psxRcntRcount( u32 index )
140 count = psxRegs.cycle;
141 count -= rcnts[index].cycleStart;
142 if (rcnts[index].rate > 1)
143 count /= rcnts[index].rate;
147 verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
154 /******************************************************************************/
162 psxNextsCounter = psxRegs.cycle;
163 psxNextCounter = 0x7fffffff;
165 for( i = 0; i < CounterQuantity; ++i )
167 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
169 if( countToUpdate < 0 )
175 if( countToUpdate < (s32)psxNextCounter )
177 psxNextCounter = countToUpdate;
181 psxRegs.interrupt |= (1 << PSXINT_RCNT);
182 new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
185 /******************************************************************************/
188 void psxRcntReset( u32 index )
192 if( rcnts[index].counterState == CountToTarget )
194 if( rcnts[index].mode & RcCountToTarget )
196 count = psxRegs.cycle;
197 count -= rcnts[index].cycleStart;
198 if (rcnts[index].rate > 1)
199 count /= rcnts[index].rate;
200 count -= rcnts[index].target;
204 count = _psxRcntRcount( index );
207 _psxRcntWcount( index, count );
209 if( rcnts[index].mode & RcIrqOnTarget )
211 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
213 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
214 setIrq( rcnts[index].irq );
215 rcnts[index].irqState = 1;
219 rcnts[index].mode |= RcCountEqTarget;
221 else if( rcnts[index].counterState == CountToOverflow )
223 count = psxRegs.cycle;
224 count -= rcnts[index].cycleStart;
225 if (rcnts[index].rate > 1)
226 count /= rcnts[index].rate;
229 _psxRcntWcount( index, count );
231 if( rcnts[index].mode & RcIrqOnOverflow )
233 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
235 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
236 setIrq( rcnts[index].irq );
237 rcnts[index].irqState = 1;
241 rcnts[index].mode |= RcOverflow;
244 rcnts[index].mode |= RcUnknown10;
253 cycle = psxRegs.cycle;
256 if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
262 if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
268 if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
274 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
276 u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
277 u32 next_vsync, next_lace;
279 spuSyncCount += hsync_steps;
280 hSyncCount += hsync_steps;
283 if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
289 SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
294 if( hSyncCount == VBlankStart[Config.PsxType] )
296 GPU_vBlank( 1, &hSyncCount, &gpu_wants_hcnt );
298 // For the best times. :D
302 // Update lace. (with InuYasha fix)
303 if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
307 GPU_vBlank( 0, &hSyncCount, &gpu_wants_hcnt );
314 // Schedule next call, in hsyncs
315 hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
316 next_vsync = VBlankStart[Config.PsxType] - hSyncCount; // ok to overflow
317 next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
318 if( next_vsync && next_vsync < hsync_steps )
319 hsync_steps = next_vsync;
320 if( next_lace && next_lace < hsync_steps )
321 hsync_steps = next_lace;
325 rcnts[3].cycleStart = cycle - leftover_cycles;
327 // 20.12 precision, clk / 50 / 313 ~= 2164.14
328 base_cycle += hsync_steps * 8864320;
330 // clk / 60 / 263 ~= 2146.31
331 base_cycle += hsync_steps * 8791293;
332 rcnts[3].cycle = base_cycle >> 12;
342 /******************************************************************************/
344 void psxRcntWcount( u32 index, u32 value )
346 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
348 _psxRcntWcount( index, value );
352 void psxRcntWmode( u32 index, u32 value )
354 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
356 rcnts[index].mode = value;
357 rcnts[index].irqState = 0;
362 if( value & Rc0PixelClock )
364 rcnts[index].rate = 5;
368 rcnts[index].rate = 1;
372 if( value & Rc1HSyncClock )
374 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
378 rcnts[index].rate = 1;
382 if( value & Rc2OneEighthClock )
384 rcnts[index].rate = 8;
388 rcnts[index].rate = 1;
391 // TODO: wcount must work.
392 if( value & Rc2Disable )
394 rcnts[index].rate = 0xffffffff;
399 _psxRcntWcount( index, 0 );
403 void psxRcntWtarget( u32 index, u32 value )
405 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
407 rcnts[index].target = value;
409 _psxRcntWcount( index, _psxRcntRcount( index ) );
413 /******************************************************************************/
415 u32 psxRcntRcount( u32 index )
419 count = _psxRcntRcount( index );
421 // Parasite Eve 2 fix.
426 if( rcnts[index].counterState == CountToTarget )
433 verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
438 u32 psxRcntRmode( u32 index )
442 mode = rcnts[index].mode;
443 rcnts[index].mode &= 0xe7ff;
445 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
450 u32 psxRcntRtarget( u32 index )
452 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
454 return rcnts[index].target;
457 /******************************************************************************/
477 rcnts[3].mode = RcCountToTarget;
478 rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
480 for( i = 0; i < CounterQuantity; ++i )
482 _psxRcntWcount( i, 0 );
492 /******************************************************************************/
494 s32 psxRcntFreeze( gzFile f, s32 Mode )
496 gzfreeze( &rcnts, sizeof(rcnts) );
497 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
498 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
499 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
500 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
503 hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
510 /******************************************************************************/