1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
29 /******************************************************************************/
33 RcSyncModeEnable = 0x0001, // 0
34 Rc01BlankPause = 0 << 1, // 1,2
35 Rc01UnblankReset = 1 << 1, // 1,2
36 Rc01UnblankReset2 = 2 << 1, // 1,2
37 Rc2Stop = 0 << 1, // 1,2
38 Rc2Stop2 = 3 << 1, // 1,2
39 RcCountToTarget = 0x0008, // 3
40 RcIrqOnTarget = 0x0010, // 4
41 RcIrqOnOverflow = 0x0020, // 5
42 RcIrqRegenerate = 0x0040, // 6
43 RcUnknown7 = 0x0080, // 7 ?
44 Rc0PixelClock = 0x0100, // 8 fake implementation
45 Rc1HSyncClock = 0x0100, // 8
46 Rc2Unknown8 = 0x0100, // 8 ?
47 Rc0Unknown9 = 0x0200, // 9 ?
48 Rc1Unknown9 = 0x0200, // 9 ?
49 Rc2OneEighthClock = 0x0200, // 9
50 RcUnknown10 = 0x0400, // 10 ?
51 RcCountEqTarget = 0x0800, // 11
52 RcOverflow = 0x1000, // 12
53 RcUnknown13 = 0x2000, // 13 ? (always zero)
54 RcUnknown14 = 0x4000, // 14 ? (always zero)
55 RcUnknown15 = 0x8000, // 15 ? (always zero)
58 #define CounterQuantity ( 4 )
59 //static const u32 CounterQuantity = 4;
61 static const u32 CountToOverflow = 0;
62 static const u32 CountToTarget = 1;
64 static const u32 FrameRate[] = { 60, 50 };
65 static const u32 HSyncTotal[] = { 263, 314 }; // actually one more on odd lines for PAL
66 #define VBlankStart 240
68 #define VERBOSE_LEVEL 0
70 /******************************************************************************/
72 Rcnt rcnts[ CounterQuantity ];
75 u32 frame_counter = 0;
76 static u32 hsync_steps = 0;
78 u32 psxNextCounter = 0, psxNextsCounter = 0;
80 /******************************************************************************/
83 void setIrq( u32 irq )
85 psxHu32ref(0x1070) |= SWAPu32(irq);
89 void verboseLog( u32 level, const char *str, ... )
92 if( level <= VERBOSE_LEVEL )
98 vsprintf( buf, str, va );
107 /******************************************************************************/
110 void _psxRcntWcount( u32 index, u32 value )
114 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
118 rcnts[index].cycleStart = psxRegs.cycle;
119 rcnts[index].cycleStart -= value * rcnts[index].rate;
122 if( value < rcnts[index].target )
124 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
125 rcnts[index].counterState = CountToTarget;
129 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
130 rcnts[index].counterState = CountToOverflow;
135 u32 _psxRcntRcount( u32 index )
139 count = psxRegs.cycle;
140 count -= rcnts[index].cycleStart;
141 if (rcnts[index].rate > 1)
142 count /= rcnts[index].rate;
144 if( count > 0x10000 )
146 verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
154 void _psxRcntWmode( u32 index, u32 value )
156 rcnts[index].mode = value;
161 if( value & Rc0PixelClock )
163 rcnts[index].rate = 5;
167 rcnts[index].rate = 1;
171 if( value & Rc1HSyncClock )
173 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
177 rcnts[index].rate = 1;
181 if( value & Rc2OneEighthClock )
183 rcnts[index].rate = 8;
187 rcnts[index].rate = 1;
190 // TODO: wcount must work.
191 if( (value & 7) == (RcSyncModeEnable | Rc2Stop) ||
192 (value & 7) == (RcSyncModeEnable | Rc2Stop2) )
194 rcnts[index].rate = 0xffffffff;
200 /******************************************************************************/
208 psxNextsCounter = psxRegs.cycle;
209 psxNextCounter = 0x7fffffff;
211 for( i = 0; i < CounterQuantity; ++i )
213 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
215 if( countToUpdate < 0 )
221 if( countToUpdate < (s32)psxNextCounter )
223 psxNextCounter = countToUpdate;
227 psxRegs.interrupt |= (1 << PSXINT_RCNT);
228 new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
231 /******************************************************************************/
234 void psxRcntReset( u32 index )
238 rcnts[index].mode |= RcUnknown10;
240 if( rcnts[index].counterState == CountToTarget )
242 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
243 if( rcnts[index].mode & RcCountToTarget )
245 rcycles -= rcnts[index].target * rcnts[index].rate;
246 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
250 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
251 rcnts[index].counterState = CountToOverflow;
254 if( rcnts[index].mode & RcIrqOnTarget )
256 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
258 verboseLog( 3, "[RCNT %i] irq\n", index );
259 setIrq( rcnts[index].irq );
260 rcnts[index].irqState = 1;
264 rcnts[index].mode |= RcCountEqTarget;
266 if( rcycles < 0x10000 * rcnts[index].rate )
270 if( rcnts[index].counterState == CountToOverflow )
272 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
273 rcycles -= 0x10000 * rcnts[index].rate;
275 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
277 if( rcycles < rcnts[index].target * rcnts[index].rate )
279 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
280 rcnts[index].counterState = CountToTarget;
283 if( rcnts[index].mode & RcIrqOnOverflow )
285 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
287 verboseLog( 3, "[RCNT %i] irq\n", index );
288 setIrq( rcnts[index].irq );
289 rcnts[index].irqState = 1;
293 rcnts[index].mode |= RcOverflow;
297 static void scheduleRcntBase(void)
299 // Schedule next call, in hsyncs
300 if (hSyncCount < VBlankStart)
301 hsync_steps = VBlankStart - hSyncCount;
303 hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
305 if (hSyncCount + hsync_steps == HSyncTotal[Config.PsxType])
307 rcnts[3].cycle = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
311 // clk / 50 / 314 ~= 2157.25
312 // clk / 60 / 263 ~= 2146.31
313 u32 mult = Config.PsxType ? 8836089 : 8791293;
314 rcnts[3].cycle = hsync_steps * mult >> 12;
320 u32 cycle, cycles_passed;
322 cycle = psxRegs.cycle;
325 cycles_passed = cycle - rcnts[0].cycleStart;
326 while( cycles_passed >= rcnts[0].cycle )
328 if (((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
329 (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
330 && cycles_passed > PSXCLK / 60 / 263)
332 u32 q = cycles_passed / (PSXCLK / 60 / 263 + 1u);
333 rcnts[0].cycleStart += q * (PSXCLK / 60) / 263u;
339 cycles_passed = cycle - rcnts[0].cycleStart;
343 while( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
349 while( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
355 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
357 hSyncCount += hsync_steps;
360 if( hSyncCount == VBlankStart )
362 HW_GPU_STATUS &= SWAP32(~PSXGPU_LCF);
371 SPU_async( cycle, 1 );
376 if( hSyncCount >= HSyncTotal[Config.PsxType] )
378 u32 status, field = 0, i;
379 rcnts[3].cycleStart += Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
384 status = SWAP32(HW_GPU_STATUS) | PSXGPU_FIELD;
385 if ((status & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS) {
386 field = frame_counter & 1;
387 status |= field << 31;
388 status ^= field << 13;
390 HW_GPU_STATUS = SWAP32(status);
391 GPU_vBlank(0, field);
393 for (i = 0; i < 2; i++)
395 if ((rcnts[i].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
396 (rcnts[i].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
398 rcnts[i].cycleStart = rcnts[3].cycleStart;
413 /******************************************************************************/
415 void psxRcntWcount( u32 index, u32 value )
417 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
419 _psxRcntWcount( index, value );
423 void psxRcntWmode( u32 index, u32 value )
425 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
427 _psxRcntWmode( index, value );
428 _psxRcntWcount( index, 0 );
430 rcnts[index].irqState = 0;
434 void psxRcntWtarget( u32 index, u32 value )
436 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
438 rcnts[index].target = value;
440 _psxRcntWcount( index, _psxRcntRcount( index ) );
444 /******************************************************************************/
451 if ((rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset) ||
452 (rcnts[0].mode & 7) == (RcSyncModeEnable | Rc01UnblankReset2))
454 count = psxRegs.cycle - rcnts[index].cycleStart;
455 count = ((16u * count) % (16u * PSXCLK / 60 / 263)) / 16u;
456 rcnts[index].cycleStart = psxRegs.cycle - count;
459 count = _psxRcntRcount( index );
461 verboseLog( 2, "[RCNT 0] rcount: %04x m: %04x\n", count, rcnts[index].mode);
471 count = _psxRcntRcount( index );
473 verboseLog( 2, "[RCNT 1] rcount: %04x m: %04x\n", count, rcnts[index].mode);
483 count = _psxRcntRcount( index );
485 verboseLog( 2, "[RCNT 2] rcount: %04x m: %04x\n", count, rcnts[index].mode);
490 u32 psxRcntRmode( u32 index )
494 mode = rcnts[index].mode;
495 rcnts[index].mode &= 0xe7ff;
497 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
502 u32 psxRcntRtarget( u32 index )
504 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
506 return rcnts[index].target;
509 /******************************************************************************/
529 rcnts[3].mode = RcCountToTarget;
530 rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
532 for( i = 0; i < CounterQuantity; ++i )
534 _psxRcntWcount( i, 0 );
543 /******************************************************************************/
545 s32 psxRcntFreeze( void *f, s32 Mode )
547 u32 spuSyncCount = 0;
551 gzfreeze( &rcnts, sizeof(Rcnt) * CounterQuantity );
552 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
553 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
554 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
555 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
559 // don't trust things from a savestate
561 for( i = 0; i < CounterQuantity; ++i )
563 _psxRcntWmode( i, rcnts[i].mode );
564 count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
565 _psxRcntWcount( i, count );
574 /******************************************************************************/
575 // vim:ts=4:shiftwidth=4:expandtab