1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
28 /******************************************************************************/
32 Rc0Gate = 0x0001, // 0 not implemented
33 Rc1Gate = 0x0001, // 0 not implemented
34 Rc2Disable = 0x0001, // 0 partially implemented
35 RcUnknown1 = 0x0002, // 1 ?
36 RcUnknown2 = 0x0004, // 2 ?
37 RcCountToTarget = 0x0008, // 3
38 RcIrqOnTarget = 0x0010, // 4
39 RcIrqOnOverflow = 0x0020, // 5
40 RcIrqRegenerate = 0x0040, // 6
41 RcUnknown7 = 0x0080, // 7 ?
42 Rc0PixelClock = 0x0100, // 8 fake implementation
43 Rc1HSyncClock = 0x0100, // 8
44 Rc2Unknown8 = 0x0100, // 8 ?
45 Rc0Unknown9 = 0x0200, // 9 ?
46 Rc1Unknown9 = 0x0200, // 9 ?
47 Rc2OneEighthClock = 0x0200, // 9
48 RcUnknown10 = 0x0400, // 10 ?
49 RcCountEqTarget = 0x0800, // 11
50 RcOverflow = 0x1000, // 12
51 RcUnknown13 = 0x2000, // 13 ? (always zero)
52 RcUnknown14 = 0x4000, // 14 ? (always zero)
53 RcUnknown15 = 0x8000, // 15 ? (always zero)
56 #define CounterQuantity ( 4 )
57 //static const u32 CounterQuantity = 4;
59 static const u32 CountToOverflow = 0;
60 static const u32 CountToTarget = 1;
62 static const u32 FrameRate[] = { 60, 50 };
63 static const u32 HSyncTotal[] = { 263, 313 };
64 static const u32 SpuUpdInterval[] = { 32, 32 };
65 #define VBlankStart 240
67 #define VERBOSE_LEVEL 0
68 static const s32 VerboseLevel = VERBOSE_LEVEL;
70 /******************************************************************************/
72 Rcnt rcnts[ CounterQuantity ];
75 u32 frame_counter = 0;
76 static u32 spuSyncCount = 0;
77 static u32 hsync_steps = 0;
78 static u32 base_cycle = 0;
80 u32 psxNextCounter = 0, psxNextsCounter = 0;
82 /******************************************************************************/
85 void setIrq( u32 irq )
87 psxHu32ref(0x1070) |= SWAPu32(irq);
91 void verboseLog( u32 level, const char *str, ... )
94 if( level <= VerboseLevel )
100 vsprintf( buf, str, va );
109 /******************************************************************************/
112 void _psxRcntWcount( u32 index, u32 value )
116 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
120 rcnts[index].cycleStart = psxRegs.cycle;
121 rcnts[index].cycleStart -= value * rcnts[index].rate;
124 if( value < rcnts[index].target )
126 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
127 rcnts[index].counterState = CountToTarget;
131 rcnts[index].cycle = 0xffff * rcnts[index].rate;
132 rcnts[index].counterState = CountToOverflow;
137 u32 _psxRcntRcount( u32 index )
141 count = psxRegs.cycle;
142 count -= rcnts[index].cycleStart;
143 if (rcnts[index].rate > 1)
144 count /= rcnts[index].rate;
148 verboseLog( 1, "[RCNT %i] rcount > 0xffff: %x\n", index, count );
155 /******************************************************************************/
163 psxNextsCounter = psxRegs.cycle;
164 psxNextCounter = 0x7fffffff;
166 for( i = 0; i < CounterQuantity; ++i )
168 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
170 if( countToUpdate < 0 )
176 if( countToUpdate < (s32)psxNextCounter )
178 psxNextCounter = countToUpdate;
182 psxRegs.interrupt |= (1 << PSXINT_RCNT);
183 new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
186 /******************************************************************************/
189 void psxRcntReset( u32 index )
193 rcnts[index].mode |= RcUnknown10;
195 if( rcnts[index].counterState == CountToTarget )
197 count = psxRegs.cycle;
198 count -= rcnts[index].cycleStart;
199 if( rcnts[index].rate > 1 )
200 count /= rcnts[index].rate;
201 if( rcnts[index].mode & RcCountToTarget )
202 count -= rcnts[index].target;
204 _psxRcntWcount( index, count );
206 if( rcnts[index].mode & RcIrqOnTarget )
208 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
210 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
211 setIrq( rcnts[index].irq );
212 rcnts[index].irqState = 1;
216 rcnts[index].mode |= RcCountEqTarget;
218 if( count < 0xffff ) // special case, overflow too?
222 if( rcnts[index].counterState == CountToOverflow )
224 count = psxRegs.cycle;
225 count -= rcnts[index].cycleStart;
226 if (rcnts[index].rate > 1)
227 count /= rcnts[index].rate;
230 _psxRcntWcount( index, count );
232 if( rcnts[index].mode & RcIrqOnOverflow )
234 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
236 verboseLog( 3, "[RCNT %i] irq: %x\n", index, count );
237 setIrq( rcnts[index].irq );
238 rcnts[index].irqState = 1;
242 rcnts[index].mode |= RcOverflow;
250 cycle = psxRegs.cycle;
253 if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
259 if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
265 if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
271 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
273 u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
274 u32 next_vsync, next_lace;
276 spuSyncCount += hsync_steps;
277 hSyncCount += hsync_steps;
280 if( spuSyncCount >= SpuUpdInterval[Config.PsxType] )
286 SPU_async( SpuUpdInterval[Config.PsxType] * rcnts[3].target );
291 if( hSyncCount == VBlankStart )
293 HW_GPU_STATUS &= ~PSXGPU_LCF;
301 // Update lace. (with InuYasha fix)
302 if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
308 if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
309 HW_GPU_STATUS |= frame_counter << 31;
310 GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
313 // Schedule next call, in hsyncs
314 hsync_steps = SpuUpdInterval[Config.PsxType] - spuSyncCount;
315 next_vsync = VBlankStart - hSyncCount; // ok to overflow
316 next_lace = HSyncTotal[Config.PsxType] - hSyncCount;
317 if( next_vsync && next_vsync < hsync_steps )
318 hsync_steps = next_vsync;
319 if( next_lace && next_lace < hsync_steps )
320 hsync_steps = next_lace;
322 rcnts[3].cycleStart = cycle - leftover_cycles;
324 // 20.12 precision, clk / 50 / 313 ~= 2164.14
325 base_cycle += hsync_steps * 8864320;
327 // clk / 60 / 263 ~= 2146.31
328 base_cycle += hsync_steps * 8791293;
329 rcnts[3].cycle = base_cycle >> 12;
340 /******************************************************************************/
342 void psxRcntWcount( u32 index, u32 value )
344 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
346 _psxRcntWcount( index, value );
350 void psxRcntWmode( u32 index, u32 value )
352 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
354 rcnts[index].mode = value;
355 rcnts[index].irqState = 0;
360 if( value & Rc0PixelClock )
362 rcnts[index].rate = 5;
366 rcnts[index].rate = 1;
370 if( value & Rc1HSyncClock )
372 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
376 rcnts[index].rate = 1;
380 if( value & Rc2OneEighthClock )
382 rcnts[index].rate = 8;
386 rcnts[index].rate = 1;
389 // TODO: wcount must work.
390 if( value & Rc2Disable )
392 rcnts[index].rate = 0xffffffff;
397 _psxRcntWcount( index, 0 );
401 void psxRcntWtarget( u32 index, u32 value )
403 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
405 rcnts[index].target = value;
407 _psxRcntWcount( index, _psxRcntRcount( index ) );
411 /******************************************************************************/
413 u32 psxRcntRcount( u32 index )
417 count = _psxRcntRcount( index );
419 // Parasite Eve 2 fix.
424 if( rcnts[index].counterState == CountToTarget )
431 verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
436 u32 psxRcntRmode( u32 index )
440 mode = rcnts[index].mode;
441 rcnts[index].mode &= 0xe7ff;
443 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
448 u32 psxRcntRtarget( u32 index )
450 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
452 return rcnts[index].target;
455 /******************************************************************************/
475 rcnts[3].mode = RcCountToTarget;
476 rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
478 for( i = 0; i < CounterQuantity; ++i )
480 _psxRcntWcount( i, 0 );
490 /******************************************************************************/
492 s32 psxRcntFreeze( gzFile f, s32 Mode )
494 gzfreeze( &rcnts, sizeof(rcnts) );
495 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
496 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
497 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
498 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
501 hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
508 /******************************************************************************/