1 /***************************************************************************
2 * Copyright (C) 2010 by Blade_Arma *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * Internal PSX counters.
24 #include "psxcounters.h"
28 /******************************************************************************/
32 Rc0Gate = 0x0001, // 0 not implemented
33 Rc1Gate = 0x0001, // 0 not implemented
34 Rc2Disable = 0x0001, // 0 partially implemented
35 RcUnknown1 = 0x0002, // 1 ?
36 RcUnknown2 = 0x0004, // 2 ?
37 RcCountToTarget = 0x0008, // 3
38 RcIrqOnTarget = 0x0010, // 4
39 RcIrqOnOverflow = 0x0020, // 5
40 RcIrqRegenerate = 0x0040, // 6
41 RcUnknown7 = 0x0080, // 7 ?
42 Rc0PixelClock = 0x0100, // 8 fake implementation
43 Rc1HSyncClock = 0x0100, // 8
44 Rc2Unknown8 = 0x0100, // 8 ?
45 Rc0Unknown9 = 0x0200, // 9 ?
46 Rc1Unknown9 = 0x0200, // 9 ?
47 Rc2OneEighthClock = 0x0200, // 9
48 RcUnknown10 = 0x0400, // 10 ?
49 RcCountEqTarget = 0x0800, // 11
50 RcOverflow = 0x1000, // 12
51 RcUnknown13 = 0x2000, // 13 ? (always zero)
52 RcUnknown14 = 0x4000, // 14 ? (always zero)
53 RcUnknown15 = 0x8000, // 15 ? (always zero)
56 #define CounterQuantity ( 4 )
57 //static const u32 CounterQuantity = 4;
59 static const u32 CountToOverflow = 0;
60 static const u32 CountToTarget = 1;
62 static const u32 FrameRate[] = { 60, 50 };
63 static const u32 HSyncTotal[] = { 263, 313 };
64 #define VBlankStart 240
66 #define VERBOSE_LEVEL 0
68 static const s32 VerboseLevel = VERBOSE_LEVEL;
71 /******************************************************************************/
74 u32 frame_counter = 0;
75 static u32 hsync_steps = 0;
76 static u32 base_cycle = 0;
78 u32 psxNextCounter = 0, psxNextsCounter = 0;
80 /******************************************************************************/
83 void setIrq( u32 irq )
85 psxHu32ref(0x1070) |= SWAPu32(irq);
89 void verboseLog( u32 level, const char *str, ... )
92 if( level <= VerboseLevel )
98 vsprintf( buf, str, va );
107 /******************************************************************************/
110 void _psxRcntWcount( u32 index, u32 value )
114 verboseLog( 1, "[RCNT %i] wcount > 0xffff: %x\n", index, value );
118 rcnts[index].cycleStart = psxRegs.cycle;
119 rcnts[index].cycleStart -= value * rcnts[index].rate;
122 if( value < rcnts[index].target )
124 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
125 rcnts[index].counterState = CountToTarget;
129 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
130 rcnts[index].counterState = CountToOverflow;
135 u32 _psxRcntRcount( u32 index )
139 count = psxRegs.cycle;
140 count -= rcnts[index].cycleStart;
141 if (rcnts[index].rate > 1)
142 count /= rcnts[index].rate;
144 if( count > 0x10000 )
146 verboseLog( 1, "[RCNT %i] rcount > 0x10000: %x\n", index, count );
154 void _psxRcntWmode( u32 index, u32 value )
156 rcnts[index].mode = value;
161 if( value & Rc0PixelClock )
163 rcnts[index].rate = 5;
167 rcnts[index].rate = 1;
171 if( value & Rc1HSyncClock )
173 rcnts[index].rate = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
177 rcnts[index].rate = 1;
181 if( value & Rc2OneEighthClock )
183 rcnts[index].rate = 8;
187 rcnts[index].rate = 1;
190 // TODO: wcount must work.
191 if( value & Rc2Disable )
193 rcnts[index].rate = 0xffffffff;
199 /******************************************************************************/
207 psxNextsCounter = psxRegs.cycle;
208 psxNextCounter = 0x7fffffff;
210 for( i = 0; i < CounterQuantity; ++i )
212 countToUpdate = rcnts[i].cycle - (psxNextsCounter - rcnts[i].cycleStart);
214 if( countToUpdate < 0 )
220 if( countToUpdate < (s32)psxNextCounter )
222 psxNextCounter = countToUpdate;
226 psxRegs.interrupt |= (1 << PSXINT_RCNT);
227 new_dyna_set_event(PSXINT_RCNT, psxNextCounter);
230 /******************************************************************************/
233 void psxRcntReset( u32 index )
237 rcnts[index].mode |= RcUnknown10;
239 if( rcnts[index].counterState == CountToTarget )
241 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
242 if( rcnts[index].mode & RcCountToTarget )
244 rcycles -= rcnts[index].target * rcnts[index].rate;
245 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
249 rcnts[index].cycle = 0x10000 * rcnts[index].rate;
250 rcnts[index].counterState = CountToOverflow;
253 if( rcnts[index].mode & RcIrqOnTarget )
255 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
257 verboseLog( 3, "[RCNT %i] irq\n", index );
258 setIrq( rcnts[index].irq );
259 rcnts[index].irqState = 1;
263 rcnts[index].mode |= RcCountEqTarget;
265 if( rcycles < 0x10000 * rcnts[index].rate )
269 if( rcnts[index].counterState == CountToOverflow )
271 rcycles = psxRegs.cycle - rcnts[index].cycleStart;
272 rcycles -= 0x10000 * rcnts[index].rate;
274 rcnts[index].cycleStart = psxRegs.cycle - rcycles;
276 if( rcycles < rcnts[index].target * rcnts[index].rate )
278 rcnts[index].cycle = rcnts[index].target * rcnts[index].rate;
279 rcnts[index].counterState = CountToTarget;
282 if( rcnts[index].mode & RcIrqOnOverflow )
284 if( (rcnts[index].mode & RcIrqRegenerate) || (!rcnts[index].irqState) )
286 verboseLog( 3, "[RCNT %i] irq\n", index );
287 setIrq( rcnts[index].irq );
288 rcnts[index].irqState = 1;
292 rcnts[index].mode |= RcOverflow;
300 cycle = psxRegs.cycle;
303 if( cycle - rcnts[0].cycleStart >= rcnts[0].cycle )
309 if( cycle - rcnts[1].cycleStart >= rcnts[1].cycle )
315 if( cycle - rcnts[2].cycleStart >= rcnts[2].cycle )
321 if( cycle - rcnts[3].cycleStart >= rcnts[3].cycle )
323 u32 leftover_cycles = cycle - rcnts[3].cycleStart - rcnts[3].cycle;
326 hSyncCount += hsync_steps;
329 if( hSyncCount == VBlankStart )
331 HW_GPU_STATUS &= ~PSXGPU_LCF;
340 SPU_async( cycle, 1 );
344 // Update lace. (with InuYasha fix)
345 if( hSyncCount >= (Config.VSyncWA ? HSyncTotal[Config.PsxType] / BIAS : HSyncTotal[Config.PsxType]) )
351 if( (HW_GPU_STATUS & PSXGPU_ILACE_BITS) == PSXGPU_ILACE_BITS )
352 HW_GPU_STATUS |= frame_counter << 31;
353 GPU_vBlank( 0, HW_GPU_STATUS >> 31 );
356 // Schedule next call, in hsyncs
357 hsync_steps = HSyncTotal[Config.PsxType] - hSyncCount;
358 next_vsync = VBlankStart - hSyncCount; // ok to overflow
359 if( next_vsync && next_vsync < hsync_steps )
360 hsync_steps = next_vsync;
362 rcnts[3].cycleStart = cycle - leftover_cycles;
364 // 20.12 precision, clk / 50 / 313 ~= 2164.14
365 base_cycle += hsync_steps * 8864320;
367 // clk / 60 / 263 ~= 2146.31
368 base_cycle += hsync_steps * 8791293;
369 rcnts[3].cycle = base_cycle >> 12;
380 /******************************************************************************/
382 void psxRcntWcount( u32 index, u32 value )
384 verboseLog( 2, "[RCNT %i] wcount: %x\n", index, value );
386 _psxRcntWcount( index, value );
390 void psxRcntWmode( u32 index, u32 value )
392 verboseLog( 1, "[RCNT %i] wmode: %x\n", index, value );
394 _psxRcntWmode( index, value );
395 _psxRcntWcount( index, 0 );
397 rcnts[index].irqState = 0;
401 void psxRcntWtarget( u32 index, u32 value )
403 verboseLog( 1, "[RCNT %i] wtarget: %x\n", index, value );
405 rcnts[index].target = value;
407 _psxRcntWcount( index, _psxRcntRcount( index ) );
411 /******************************************************************************/
413 u32 psxRcntRcount( u32 index )
417 count = _psxRcntRcount( index );
419 // Parasite Eve 2 fix.
424 if( rcnts[index].counterState == CountToTarget )
431 verboseLog( 2, "[RCNT %i] rcount: %x\n", index, count );
436 u32 psxRcntRmode( u32 index )
440 mode = rcnts[index].mode;
441 rcnts[index].mode &= 0xe7ff;
443 verboseLog( 2, "[RCNT %i] rmode: %x\n", index, mode );
448 u32 psxRcntRtarget( u32 index )
450 verboseLog( 2, "[RCNT %i] rtarget: %x\n", index, rcnts[index].target );
452 return rcnts[index].target;
455 /******************************************************************************/
475 rcnts[3].mode = RcCountToTarget;
476 rcnts[3].target = (PSXCLK / (FrameRate[Config.PsxType] * HSyncTotal[Config.PsxType]));
478 for( i = 0; i < CounterQuantity; ++i )
480 _psxRcntWcount( i, 0 );
489 /******************************************************************************/
491 s32 psxRcntFreeze( void *f, s32 Mode )
493 u32 spuSyncCount = 0;
497 gzfreeze( &rcnts, sizeof(*rcnts) * CounterQuantity );
498 gzfreeze( &hSyncCount, sizeof(hSyncCount) );
499 gzfreeze( &spuSyncCount, sizeof(spuSyncCount) );
500 gzfreeze( &psxNextCounter, sizeof(psxNextCounter) );
501 gzfreeze( &psxNextsCounter, sizeof(psxNextsCounter) );
505 // don't trust things from a savestate
506 for( i = 0; i < CounterQuantity; ++i )
508 _psxRcntWmode( i, rcnts[i].mode );
509 count = (psxRegs.cycle - rcnts[i].cycleStart) / rcnts[i].rate;
510 _psxRcntWcount( i, count );
512 hsync_steps = (psxRegs.cycle - rcnts[3].cycleStart) / rcnts[3].target;
521 /******************************************************************************/