cdrom: Rename "stat" to "cdr_stat"
[pcsx_rearmed.git] / libpcsxcore / psxdma.c
1 /***************************************************************************
2  *   Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team              *
3  *                                                                         *
4  *   This program is free software; you can redistribute it and/or modify  *
5  *   it under the terms of the GNU General Public License as published by  *
6  *   the Free Software Foundation; either version 2 of the License, or     *
7  *   (at your option) any later version.                                   *
8  *                                                                         *
9  *   This program is distributed in the hope that it will be useful,       *
10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
12  *   GNU General Public License for more details.                          *
13  *                                                                         *
14  *   You should have received a copy of the GNU General Public License     *
15  *   along with this program; if not, write to the                         *
16  *   Free Software Foundation, Inc.,                                       *
17  *   51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA.           *
18  ***************************************************************************/
19
20 /*
21 * Handles PSX DMA functions.
22 */
23
24 #include "psxdma.h"
25 #include "gpu.h"
26
27 #ifndef min
28 #define min(a, b) ((b) < (a) ? (b) : (a))
29 #endif
30 #ifndef PSXDMA_LOG
31 #define PSXDMA_LOG(...)
32 #endif
33
34 // Dma0/1 in Mdec.c
35 // Dma3   in CdRom.c
36
37 void spuInterrupt() {
38         if (HW_DMA4_CHCR & SWAP32(0x01000000))
39         {
40                 HW_DMA4_CHCR &= SWAP32(~0x01000000);
41                 DMA_INTERRUPT(4);
42         }
43 }
44
45 void psxDma4(u32 madr, u32 bcr, u32 chcr) { // SPU
46         u32 words, words_max = 0, words_copy;
47         u16 *ptr;
48
49         madr &= ~3;
50         ptr = getDmaRam(madr, &words_max);
51         if (ptr == INVALID_PTR)
52                 log_unhandled("bad dma4 madr %x\n", madr);
53
54         words = words_copy = (bcr >> 16) * (bcr & 0xffff);
55         if (words_copy > words_max) {
56                 log_unhandled("bad dma4 madr %x bcr %x\n", madr, bcr);
57                 words_copy = words_max;
58         }
59
60         switch (chcr) {
61                 case 0x01000201: //cpu to spu transfer
62                         PSXDMA_LOG("*** DMA4 SPU - mem2spu *** %x addr = %x size = %x\n", chcr, madr, bcr);
63                         if (ptr == INVALID_PTR)
64                                 break;
65                         SPU_writeDMAMem(ptr, words_copy * 2, psxRegs.cycle);
66                         HW_DMA4_MADR = SWAPu32(madr + words_copy * 2);
67                         // This should be much slower, like 12+ cycles/byte, it's like
68                         // that because the CPU runs too fast and fifo is not emulated.
69                         // See also set_dma_end().
70                         set_event(PSXINT_SPUDMA, words * 4 * 4);
71                         return;
72
73                 case 0x01000200: //spu to cpu transfer
74                         PSXDMA_LOG("*** DMA4 SPU - spu2mem *** %x addr = %x size = %x\n", chcr, madr, bcr);
75                         if (ptr == INVALID_PTR)
76                                 break;
77                         SPU_readDMAMem(ptr, words_copy * 2, psxRegs.cycle);
78                         psxCpu->Clear(madr, words_copy);
79
80                         HW_DMA4_MADR = SWAPu32(madr + words_copy * 4);
81                         set_event(PSXINT_SPUDMA, words * 4 * 4);
82                         return;
83
84                 default:
85                         log_unhandled("*** DMA4 SPU - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
86                         break;
87         }
88
89         HW_DMA4_CHCR &= SWAP32(~0x01000000);
90         DMA_INTERRUPT(4);
91 }
92
93 #if 0
94 // Taken from PEOPS SOFTGPU
95 static inline boolean CheckForEndlessLoop(u32 laddr, u32 *lUsedAddr) {
96         if (laddr == lUsedAddr[1]) return TRUE;
97         if (laddr == lUsedAddr[2]) return TRUE;
98
99         if (laddr < lUsedAddr[0]) lUsedAddr[1] = laddr;
100         else lUsedAddr[2] = laddr;
101
102         lUsedAddr[0] = laddr;
103
104         return FALSE;
105 }
106
107 static u32 gpuDmaChainSize(u32 addr) {
108         u32 size;
109         u32 DMACommandCounter = 0;
110         u32 lUsedAddr[3];
111
112         lUsedAddr[0] = lUsedAddr[1] = lUsedAddr[2] = 0xffffff;
113
114         // initial linked list ptr (word)
115         size = 1;
116
117         do {
118                 addr &= 0x1ffffc;
119
120                 if (DMACommandCounter++ > 2000000) break;
121                 if (CheckForEndlessLoop(addr, lUsedAddr)) break;
122
123                 // # 32-bit blocks to transfer
124                 size += psxMu8( addr + 3 );
125
126                 // next 32-bit pointer
127                 addr = psxMu32( addr & ~0x3 ) & 0xffffff;
128                 size += 1;
129         } while (!(addr & 0x800000)); // contrary to some documentation, the end-of-linked-list marker is not actually 0xFF'FFFF
130                                   // any pointer with bit 23 set will do.
131
132         return size;
133 }
134 #endif
135
136 void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
137         u32 *ptr, madr_next, *madr_next_p;
138         u32 words, words_left, words_max, words_copy;
139         int cycles_sum, cycles_last_cmd = 0, do_walking;
140
141         madr &= ~3;
142         switch (chcr) {
143                 case 0x01000200: // vram2mem
144                         PSXDMA_LOG("*** DMA2 GPU - vram2mem *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
145                         ptr = getDmaRam(madr, &words_max);
146                         if (ptr == INVALID_PTR) {
147                                 log_unhandled("bad dma2 madr %x\n", madr);
148                                 break;
149                         }
150                         // BA blocks * BS words (word = 32-bits)
151                         words = words_copy = (bcr >> 16) * (bcr & 0xffff);
152                         if (words > words_max) {
153                                 log_unhandled("bad dma2 madr %x bcr %x\n", madr, bcr);
154                                 words_copy = words_max;
155                         }
156                         GPU_readDataMem(ptr, words_copy);
157                         psxCpu->Clear(madr, words_copy);
158
159                         HW_DMA2_MADR = SWAPu32(madr + words_copy * 4);
160
161                         // careful: gpu_state_change() also messes with this
162                         psxRegs.gpuIdleAfter = psxRegs.cycle + words / 4 + 16;
163                         // already 32-bit word size ((size * 4) / 4)
164                         set_event(PSXINT_GPUDMA, words / 4);
165                         return;
166
167                 case 0x01000201: // mem2vram
168                         PSXDMA_LOG("*** DMA 2 - GPU mem2vram *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
169                         words = words_left = (bcr >> 16) * (bcr & 0xffff);
170                         while (words_left > 0) {
171                                 ptr = getDmaRam(madr, &words_max);
172                                 if (ptr == INVALID_PTR) {
173                                         log_unhandled("bad2 dma madr %x\n", madr);
174                                         break;
175                                 }
176                                 words_copy = min(words_left, words_max);
177                                 GPU_writeDataMem(ptr, words_copy);
178                                 words_left -= words_copy;
179                                 madr += words_copy * 4;
180                         }
181
182                         HW_DMA2_MADR = SWAPu32(madr);
183
184                         // careful: gpu_state_change() also messes with this
185                         psxRegs.gpuIdleAfter = psxRegs.cycle + words / 4 + 16;
186                         // already 32-bit word size ((size * 4) / 4)
187                         set_event(PSXINT_GPUDMA, words / 4);
188                         return;
189
190                 case 0x01000401: // dma chain
191                         PSXDMA_LOG("*** DMA 2 - GPU dma chain *** %lx addr = %lx size = %lx\n", chcr, madr, bcr);
192                         // when not emulating walking progress, end immediately
193                         madr_next = 0xffffff;
194
195                         do_walking = Config.GpuListWalking;
196                         if (do_walking < 0 || Config.hacks.gpu_timing1024)
197                                 do_walking = Config.hacks.gpu_slow_list_walking;
198                         madr_next_p = do_walking ? &madr_next : NULL;
199
200                         cycles_sum = GPU_dmaChain((u32 *)psxM, madr & 0x1fffff,
201                                         madr_next_p, &cycles_last_cmd);
202
203                         HW_DMA2_MADR = SWAPu32(madr_next);
204
205                         // a hack for Judge Dredd which is annoyingly sensitive to timing
206                         if (Config.hacks.gpu_timing1024)
207                                 cycles_sum = 1024;
208
209                         psxRegs.gpuIdleAfter = psxRegs.cycle + cycles_sum + cycles_last_cmd;
210                         set_event(PSXINT_GPUDMA, cycles_sum);
211                         //printf("%u dma2cf: %6d,%4d %08x %08x %08x %08x\n", psxRegs.cycle,
212                         //  cycles_sum, cycles_last_cmd, madr, bcr, chcr, HW_DMA2_MADR);
213                         return;
214
215                 default:
216                         log_unhandled("*** DMA 2 - GPU unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
217                         break;
218         }
219
220         HW_DMA2_CHCR &= SWAP32(~0x01000000);
221         DMA_INTERRUPT(2);
222 }
223
224 void gpuInterrupt() {
225         if (HW_DMA2_CHCR == SWAP32(0x01000401) && !(HW_DMA2_MADR & SWAP32(0x800000)))
226         {
227                 u32 madr_next = 0xffffff, madr = SWAPu32(HW_DMA2_MADR);
228                 int cycles_sum, cycles_last_cmd = 0;
229                 cycles_sum = GPU_dmaChain((u32 *)psxM, madr & 0x1fffff,
230                                 &madr_next, &cycles_last_cmd);
231                 HW_DMA2_MADR = SWAPu32(madr_next);
232                 if ((s32)(psxRegs.gpuIdleAfter - psxRegs.cycle) > 0)
233                         cycles_sum += psxRegs.gpuIdleAfter - psxRegs.cycle;
234                 psxRegs.gpuIdleAfter = psxRegs.cycle + cycles_sum + cycles_last_cmd;
235                 set_event(PSXINT_GPUDMA, cycles_sum);
236                 //printf("%u dma2cn: %6d,%4d %08x\n", psxRegs.cycle, cycles_sum,
237                 //      cycles_last_cmd, HW_DMA2_MADR);
238                 return;
239         }
240         if (HW_DMA2_CHCR & SWAP32(0x01000000))
241         {
242                 HW_DMA2_CHCR &= SWAP32(~0x01000000);
243                 DMA_INTERRUPT(2);
244         }
245 }
246
247 void psxAbortDma2() {
248         psxRegs.gpuIdleAfter = psxRegs.cycle + 32;
249 }
250
251 void psxDma6(u32 madr, u32 bcr, u32 chcr) {
252         u32 words, words_max;
253         u32 *mem;
254
255         PSXDMA_LOG("*** DMA6 OT *** %x addr = %x size = %x\n", chcr, madr, bcr);
256
257         if (chcr == 0x11000002) {
258                 madr &= ~3;
259                 mem = getDmaRam(madr, &words_max);
260                 if (mem == INVALID_PTR) {
261                         log_unhandled("bad6 dma madr %x\n", madr);
262                         HW_DMA6_CHCR &= SWAP32(~0x11000000);
263                         DMA_INTERRUPT(6);
264                         return;
265                 }
266
267                 // already 32-bit size
268                 words = bcr;
269
270                 while (bcr-- && mem > (u32 *)psxM) {
271                         *mem-- = SWAP32((madr - 4) & 0xffffff);
272                         madr -= 4;
273                 }
274                 *++mem = SWAP32(0xffffff);
275
276                 // halted
277                 psxRegs.cycle += words;
278                 set_event(PSXINT_GPUOTCDMA, 16);
279                 return;
280         }
281         else {
282                 // Unknown option
283                 log_unhandled("*** DMA6 OT - unknown *** %x addr = %x size = %x\n", chcr, madr, bcr);
284         }
285
286         HW_DMA6_CHCR &= SWAP32(~0x11000000);
287         DMA_INTERRUPT(6);
288 }
289
290 void gpuotcInterrupt()
291 {
292         if (HW_DMA6_CHCR & SWAP32(0x01000000))
293         {
294                 HW_DMA6_CHCR &= SWAP32(~0x11000000);
295                 DMA_INTERRUPT(6);
296         }
297 }