1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * PSX assembly interpreter.
24 #include "psxcommon.h"
28 #include "psxinterpreter.h"
32 #define ProcessDebug()
34 static int branch = 0;
35 static int branch2 = 0;
38 // These macros are used to assemble the repassembler functions
41 #define debugI() PSXCPU_LOG("%s\n", disR3000AF(psxRegs.code, psxRegs.pc));
47 #define INT_ATTR __attribute__((regparm(2)))
52 #define INVALID_PTR NULL
56 static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code);
57 static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code);
59 static u32 INT_ATTR fetchNoCache(u8 **memRLUT, u32 pc)
61 u8 *base = memRLUT[pc >> 16];
62 if (base == INVALID_PTR)
64 u32 *code = (u32 *)(base + (pc & 0xfffc));
70 Use old CPU cache code when the RAM location is updated with new code (affects in-game racing)
72 static struct cache_entry {
77 static u32 INT_ATTR fetchICache(u8 **memRLUT, u32 pc)
82 // this is not how the hardware works but whatever
83 struct cache_entry *entry = &ICache[(pc & 0xff0) >> 4];
85 if (((entry->tag ^ pc) & 0xfffffff0) != 0 || pc < entry->tag)
87 const u8 *base = memRLUT[pc >> 16];
89 if (base == INVALID_PTR)
91 code = (u32 *)(base + (pc & 0xfff0));
94 // treat as 4 words, although other configurations are said to be possible
97 case 0x00: entry->data[0] = SWAP32(code[0]);
98 case 0x04: entry->data[1] = SWAP32(code[1]);
99 case 0x08: entry->data[2] = SWAP32(code[2]);
100 case 0x0c: entry->data[3] = SWAP32(code[3]);
103 return entry->data[(pc & 0x0f) >> 2];
106 return fetchNoCache(memRLUT, pc);
109 static u32 (INT_ATTR *fetch)(u8 **memRLUT, u32 pc) = fetchNoCache;
111 static void delayRead(int reg, u32 bpc) {
114 // SysPrintf("delayRead at %x!\n", psxRegs.pc);
116 rold = psxRegs.GPR.r[reg];
117 psxBSC[psxRegs.code >> 26](&psxRegs, psxRegs.code); // branch delay load
118 rnew = psxRegs.GPR.r[reg];
124 psxRegs.GPR.r[reg] = rold;
125 execI(); // first branch opcode
126 psxRegs.GPR.r[reg] = rnew;
131 static void delayWrite(int reg, u32 bpc) {
133 /* SysPrintf("delayWrite at %x!\n", psxRegs.pc);
135 SysPrintf("%s\n", disR3000AF(psxRegs.code, psxRegs.pc-4));
136 SysPrintf("%s\n", disR3000AF(PSXMu32(bpc), bpc));*/
138 // no changes from normal behavior
140 psxBSC[psxRegs.code >> 26](&psxRegs, psxRegs.code);
148 static void delayReadWrite(int reg, u32 bpc) {
150 // SysPrintf("delayReadWrite at %x!\n", psxRegs.pc);
152 // the branch delay load is skipped
160 /**** R3000A Instruction Macros ****/
161 #define _PC_ regs_->pc // The next PC to be executed
163 #define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register
164 #define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register
165 #define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register
166 #define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register
167 #define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register
168 #define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register
169 #define _fIm_(code) ((u16)code) // The immediate part of the instruction register
170 #define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register
172 #define _fImm_(code) ((s16)code) // sign-extended immediate
173 #define _fImmU_(code) (code&0xffff) // zero-extended immediate
175 #define _Op_ _fOp_(code)
176 #define _Funct_ _fFunct_(code)
177 #define _Rd_ _fRd_(code)
178 #define _Rt_ _fRt_(code)
179 #define _Rs_ _fRs_(code)
180 #define _Sa_ _fSa_(code)
181 #define _Im_ _fIm_(code)
182 #define _Target_ _fTarget_(code)
184 #define _Imm_ _fImm_(code)
185 #define _ImmU_ _fImmU_(code)
187 #define _rRs_ regs_->GPR.r[_Rs_] // Rs register
188 #define _rRt_ regs_->GPR.r[_Rt_] // Rt register
189 #define _rRd_ regs_->GPR.r[_Rd_] // Rd register
190 #define _rSa_ regs_->GPR.r[_Sa_] // Sa register
191 #define _rFs_ regs_->CP0.r[_Rd_] // Fs register
193 #define _rHi_ regs_->GPR.n.hi // The HI register
194 #define _rLo_ regs_->GPR.n.lo // The LO register
196 #define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
197 #define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction
199 #define _SetLink(x) regs_->GPR.r[x] = _PC_ + 4; // Sets the return address in the link register
202 static inline INT_ATTR void name(psxRegisters *regs_, u32 code)
204 // this defines shall be used with the tmp
205 // of the next func (instead of _Funct_...)
206 #define _tFunct_ ((tmp ) & 0x3F) // The funct part of the instruction register
207 #define _tRd_ ((tmp >> 11) & 0x1F) // The rd part of the instruction register
208 #define _tRt_ ((tmp >> 16) & 0x1F) // The rt part of the instruction register
209 #define _tRs_ ((tmp >> 21) & 0x1F) // The rs part of the instruction register
210 #define _tSa_ ((tmp >> 6) & 0x1F) // The sa part of the instruction register
212 #define _i32(x) (s32)(x)
213 #define _u32(x) (u32)(x)
215 static int psxTestLoadDelay(int reg, u32 tmp) {
216 if (tmp == 0) return 0; // NOP
218 case 0x00: // SPECIAL
221 case 0x02: case 0x03: // SRL/SRA
222 if (_tRd_ == reg && _tRt_ == reg) return 1; else
223 if (_tRt_ == reg) return 2; else
224 if (_tRd_ == reg) return 3;
228 if (_tRs_ == reg) return 2;
231 if (_tRd_ == reg && _tRs_ == reg) return 1; else
232 if (_tRs_ == reg) return 2; else
233 if (_tRd_ == reg) return 3;
236 // SYSCALL/BREAK just a break;
238 case 0x20: case 0x21: case 0x22: case 0x23:
239 case 0x24: case 0x25: case 0x26: case 0x27:
240 case 0x2a: case 0x2b: // ADD/ADDU...
241 case 0x04: case 0x06: case 0x07: // SLLV...
242 if (_tRd_ == reg && (_tRt_ == reg || _tRs_ == reg)) return 1; else
243 if (_tRt_ == reg || _tRs_ == reg) return 2; else
244 if (_tRd_ == reg) return 3;
247 case 0x10: case 0x12: // MFHI/MFLO
248 if (_tRd_ == reg) return 3;
250 case 0x11: case 0x13: // MTHI/MTLO
251 if (_tRs_ == reg) return 2;
254 case 0x18: case 0x19:
255 case 0x1a: case 0x1b: // MULT/DIV...
256 if (_tRt_ == reg || _tRs_ == reg) return 2;
263 case 0x00: case 0x01:
264 case 0x10: case 0x11: // BLTZ/BGEZ...
265 // Xenogears - lbu v0 / beq v0
266 // - no load delay (fixes battle loading)
269 if (_tRs_ == reg) return 2;
274 // J would be just a break;
276 if (31 == reg) return 3;
279 case 0x04: case 0x05: // BEQ/BNE
280 // Xenogears - lbu v0 / beq v0
281 // - no load delay (fixes battle loading)
284 if (_tRs_ == reg || _tRt_ == reg) return 2;
287 case 0x06: case 0x07: // BLEZ/BGTZ
288 // Xenogears - lbu v0 / beq v0
289 // - no load delay (fixes battle loading)
292 if (_tRs_ == reg) return 2;
295 case 0x08: case 0x09: case 0x0a: case 0x0b:
296 case 0x0c: case 0x0d: case 0x0e: // ADDI/ADDIU...
297 if (_tRt_ == reg && _tRs_ == reg) return 1; else
298 if (_tRs_ == reg) return 2; else
299 if (_tRt_ == reg) return 3;
303 if (_tRt_ == reg) return 3;
309 if (_tRt_ == reg) return 3;
312 if (_tRt_ == reg) return 3;
315 if (_tRt_ == reg) return 2;
318 if (_tRt_ == reg) return 2;
329 if (_tRt_ == reg) return 3;
332 if (_tRt_ == reg) return 3;
335 if (_tRt_ == reg) return 2;
338 if (_tRt_ == reg) return 2;
346 case 0x22: case 0x26: // LWL/LWR
347 if (_tRt_ == reg) return 3; else
348 if (_tRs_ == reg) return 2;
351 case 0x20: case 0x21: case 0x23:
352 case 0x24: case 0x25: // LB/LH/LW/LBU/LHU
353 if (_tRt_ == reg && _tRs_ == reg) return 1; else
354 if (_tRs_ == reg) return 2; else
355 if (_tRt_ == reg) return 3;
358 case 0x28: case 0x29: case 0x2a:
359 case 0x2b: case 0x2e: // SB/SH/SWL/SW/SWR
360 if (_tRt_ == reg || _tRs_ == reg) return 2;
363 case 0x32: case 0x3a: // LWC2/SWC2
364 if (_tRs_ == reg) return 2;
371 static void psxDelayTest(int reg, u32 bpc) {
372 u32 tmp = fetch(psxMemRLUT, bpc);
375 switch (psxTestLoadDelay(reg, tmp)) {
377 delayReadWrite(reg, bpc); return;
379 delayRead(reg, bpc); return;
381 delayWrite(reg, bpc); return;
383 psxBSC[psxRegs.code >> 26](&psxRegs, psxRegs.code);
391 static u32 psxBranchNoDelay(psxRegisters *regs_) {
394 regs_->code = code = fetch(psxMemRLUT, regs_->pc);
396 case 0x00: // SPECIAL
402 if (_Rd_) { _SetLink(_Rd_); }
410 return _BranchTarget_;
413 if (_i32(_rRs_) >= 0)
414 return _BranchTarget_;
417 if (_i32(_rRs_) < 0) {
419 return _BranchTarget_;
423 if (_i32(_rRs_) >= 0) {
425 return _BranchTarget_;
436 if (_i32(_rRs_) == _i32(_rRt_))
437 return _BranchTarget_;
440 if (_i32(_rRs_) != _i32(_rRt_))
441 return _BranchTarget_;
444 if (_i32(_rRs_) <= 0)
445 return _BranchTarget_;
449 return _BranchTarget_;
456 static int psxDelayBranchExec(u32 tar) {
461 psxRegs.cycle += BIAS;
466 static int psxDelayBranchTest(u32 tar1) {
467 u32 tar2, tmp1, tmp2;
469 tar2 = psxBranchNoDelay(&psxRegs);
476 * Branch in delay slot:
477 * - execute 1 instruction at tar1
478 * - jump to tar2 (target of branch in delay slot; this branch
479 * has no normal delay slot, instruction at tar1 was fetched instead)
482 tmp1 = psxBranchNoDelay(&psxRegs);
483 if (tmp1 == (u32)-1) {
484 return psxDelayBranchExec(tar2);
487 psxRegs.cycle += BIAS;
490 * Got a branch at tar1:
491 * - execute 1 instruction at tar2
492 * - jump to target of that branch (tmp1)
495 tmp2 = psxBranchNoDelay(&psxRegs);
496 if (tmp2 == (u32)-1) {
497 return psxDelayBranchExec(tmp1);
500 psxRegs.cycle += BIAS;
503 * Got a branch at tar2:
504 * - execute 1 instruction at tmp1
505 * - jump to target of that branch (tmp2)
508 return psxDelayBranchExec(tmp2);
511 static void doBranch(u32 tar) {
514 branch2 = branch = 1;
517 // check for branch in delay slot
518 if (psxDelayBranchTest(tar))
521 psxRegs.code = code = fetch(psxMemRLUT, psxRegs.pc);
526 psxRegs.cycle += BIAS;
528 // check for load delay
529 tmp = psxRegs.code >> 26;
535 psxDelayTest(_Rt_, branchPC);
545 psxDelayTest(_Rt_, branchPC);
552 psxDelayTest(_Rt_, branchPC);
555 if (tmp >= 0x20 && tmp <= 0x26) { // LB/LH/LWL/LW/LBU/LHU/LWR
556 psxDelayTest(_Rt_, branchPC);
562 psxBSC[psxRegs.code >> 26](&psxRegs, psxRegs.code);
565 psxRegs.pc = branchPC;
570 /*********************************************************
571 * Arithmetic with immediate operand *
572 * Format: OP rt, rs, immediate *
573 *********************************************************/
574 OP(psxADDI) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) + _Imm_ ; } // Rt = Rs + Im (Exception on Integer Overflow)
575 OP(psxADDIU) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) + _Imm_ ; } // Rt = Rs + Im
576 OP(psxANDI) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) & _ImmU_; } // Rt = Rs And Im
577 OP(psxORI) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) | _ImmU_; } // Rt = Rs Or Im
578 OP(psxXORI) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) ^ _ImmU_; } // Rt = Rs Xor Im
579 OP(psxSLTI) { if (!_Rt_) return; _rRt_ = _i32(_rRs_) < _Imm_ ; } // Rt = Rs < Im (Signed)
580 OP(psxSLTIU) { if (!_Rt_) return; _rRt_ = _u32(_rRs_) < ((u32)_Imm_); } // Rt = Rs < Im (Unsigned)
582 /*********************************************************
583 * Register arithmetic *
584 * Format: OP rd, rs, rt *
585 *********************************************************/
586 OP(psxADD) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) + _u32(_rRt_); } // Rd = Rs + Rt (Exception on Integer Overflow)
587 OP(psxADDU) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) + _u32(_rRt_); } // Rd = Rs + Rt
588 OP(psxSUB) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) - _u32(_rRt_); } // Rd = Rs - Rt (Exception on Integer Overflow)
589 OP(psxSUBU) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) - _u32(_rRt_); } // Rd = Rs - Rt
590 OP(psxAND) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) & _u32(_rRt_); } // Rd = Rs And Rt
591 OP(psxOR) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) | _u32(_rRt_); } // Rd = Rs Or Rt
592 OP(psxXOR) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) ^ _u32(_rRt_); } // Rd = Rs Xor Rt
593 OP(psxNOR) { if (!_Rd_) return; _rRd_ =~(_u32(_rRs_) | _u32(_rRt_)); }// Rd = Rs Nor Rt
594 OP(psxSLT) { if (!_Rd_) return; _rRd_ = _i32(_rRs_) < _i32(_rRt_); } // Rd = Rs < Rt (Signed)
595 OP(psxSLTU) { if (!_Rd_) return; _rRd_ = _u32(_rRs_) < _u32(_rRt_); } // Rd = Rs < Rt (Unsigned)
597 /*********************************************************
598 * Register mult/div & Register trap logic *
599 * Format: OP rs, rt *
600 *********************************************************/
604 if (_rRs_ & 0x80000000) {
610 #if !defined(__arm__) && !defined(__aarch64__)
611 else if (_rRs_ == 0x80000000 && _rRt_ == 0xFFFFFFFF) {
617 _rLo_ = _i32(_rRs_) / _i32(_rRt_);
618 _rHi_ = _i32(_rRs_) % _i32(_rRt_);
623 regs_->muldivBusyCycle = regs_->cycle + 37;
629 _rLo_ = _rRs_ / _rRt_;
630 _rHi_ = _rRs_ % _rRt_;
639 regs_->muldivBusyCycle = regs_->cycle + 37;
640 psxDIVU(regs_, code);
644 u64 res = (s64)_i32(_rRs_) * _i32(_rRt_);
646 regs_->GPR.n.lo = (u32)res;
647 regs_->GPR.n.hi = (u32)(res >> 32);
651 // approximate, but maybe good enough
653 u32 lz = __builtin_clz(((rs ^ ((s32)rs >> 21)) | 1));
654 u32 c = 7 + (2 - (lz / 11)) * 4;
655 regs_->muldivBusyCycle = regs_->cycle + c;
656 psxMULT(regs_, code);
660 u64 res = (u64)_u32(_rRs_) * _u32(_rRt_);
662 regs_->GPR.n.lo = (u32)(res & 0xffffffff);
663 regs_->GPR.n.hi = (u32)((res >> 32) & 0xffffffff);
667 // approximate, but maybe good enough
668 u32 lz = __builtin_clz(_rRs_ | 1);
669 u32 c = 7 + (2 - (lz / 11)) * 4;
670 regs_->muldivBusyCycle = regs_->cycle + c;
671 psxMULTU(regs_, code);
674 /*********************************************************
675 * Register branch logic *
676 * Format: OP rs, offset *
677 *********************************************************/
678 #define RepZBranchi32(op) if(_i32(_rRs_) op 0) doBranch(_BranchTarget_);
679 #define RepZBranchLinki32(op) { _SetLink(31); if(_i32(_rRs_) op 0) { doBranch(_BranchTarget_); } }
681 OP(psxBGEZ) { RepZBranchi32(>=) } // Branch if Rs >= 0
682 OP(psxBGEZAL) { RepZBranchLinki32(>=) } // Branch if Rs >= 0 and link
683 OP(psxBGTZ) { RepZBranchi32(>) } // Branch if Rs > 0
684 OP(psxBLEZ) { RepZBranchi32(<=) } // Branch if Rs <= 0
685 OP(psxBLTZ) { RepZBranchi32(<) } // Branch if Rs < 0
686 OP(psxBLTZAL) { RepZBranchLinki32(<) } // Branch if Rs < 0 and link
688 /*********************************************************
689 * Shift arithmetic with constant shift *
690 * Format: OP rd, rt, sa *
691 *********************************************************/
692 OP(psxSLL) { if (!_Rd_) return; _rRd_ = _u32(_rRt_) << _Sa_; } // Rd = Rt << sa
693 OP(psxSRA) { if (!_Rd_) return; _rRd_ = _i32(_rRt_) >> _Sa_; } // Rd = Rt >> sa (arithmetic)
694 OP(psxSRL) { if (!_Rd_) return; _rRd_ = _u32(_rRt_) >> _Sa_; } // Rd = Rt >> sa (logical)
696 /*********************************************************
697 * Shift arithmetic with variant register shift *
698 * Format: OP rd, rt, rs *
699 *********************************************************/
700 OP(psxSLLV) { if (!_Rd_) return; _rRd_ = _u32(_rRt_) << (_u32(_rRs_) & 0x1F); } // Rd = Rt << rs
701 OP(psxSRAV) { if (!_Rd_) return; _rRd_ = _i32(_rRt_) >> (_u32(_rRs_) & 0x1F); } // Rd = Rt >> rs (arithmetic)
702 OP(psxSRLV) { if (!_Rd_) return; _rRd_ = _u32(_rRt_) >> (_u32(_rRs_) & 0x1F); } // Rd = Rt >> rs (logical)
704 /*********************************************************
705 * Load higher 16 bits of the first word in GPR with imm *
706 * Format: OP rt, immediate *
707 *********************************************************/
708 OP(psxLUI) { if (!_Rt_) return; _rRt_ = code << 16; } // Upper halfword of Rt = Im
710 /*********************************************************
711 * Move from HI/LO to GPR *
713 *********************************************************/
714 OP(psxMFHI) { if (!_Rd_) return; _rRd_ = _rHi_; } // Rd = Hi
715 OP(psxMFLO) { if (!_Rd_) return; _rRd_ = _rLo_; } // Rd = Lo
717 static void mflohiCheckStall(psxRegisters *regs_)
719 u32 left = regs_->muldivBusyCycle - regs_->cycle;
721 //printf("muldiv stall %u\n", left);
722 regs_->cycle = regs_->muldivBusyCycle;
726 OP(psxMFHI_stall) { mflohiCheckStall(regs_); psxMFHI(regs_, code); }
727 OP(psxMFLO_stall) { mflohiCheckStall(regs_); psxMFLO(regs_, code); }
729 /*********************************************************
730 * Move to GPR to HI/LO & Register jump *
732 *********************************************************/
733 OP(psxMTHI) { _rHi_ = _rRs_; } // Hi = Rs
734 OP(psxMTLO) { _rLo_ = _rRs_; } // Lo = Rs
736 /*********************************************************
737 * Special purpose instructions *
739 *********************************************************/
742 psxException(0x24, branch);
747 psxException(0x20, branch);
750 static inline void psxTestSWInts(psxRegisters *regs_) {
751 if (regs_->CP0.n.Cause & regs_->CP0.n.Status & 0x0300 &&
752 regs_->CP0.n.Status & 0x1) {
753 regs_->CP0.n.Cause &= ~0x7c;
754 psxException(regs_->CP0.n.Cause, branch);
759 // SysPrintf("psxRFE\n");
760 regs_->CP0.n.Status = (regs_->CP0.n.Status & 0xfffffff0) |
761 ((regs_->CP0.n.Status & 0x3c) >> 2);
762 psxTestSWInts(regs_);
765 /*********************************************************
766 * Register branch logic *
767 * Format: OP rs, rt, offset *
768 *********************************************************/
769 #define RepBranchi32(op) if(_i32(_rRs_) op _i32(_rRt_)) doBranch(_BranchTarget_);
771 OP(psxBEQ) { RepBranchi32(==) } // Branch if Rs == Rt
772 OP(psxBNE) { RepBranchi32(!=) } // Branch if Rs != Rt
774 /*********************************************************
776 * Format: OP target *
777 *********************************************************/
778 OP(psxJ) { doBranch(_JumpTarget_); }
779 OP(psxJAL) { _SetLink(31); doBranch(_JumpTarget_); }
781 /*********************************************************
783 * Format: OP rs, rd *
784 *********************************************************/
786 doBranch(_rRs_ & ~3);
791 u32 temp = _u32(_rRs_);
792 if (_Rd_) { _SetLink(_Rd_); }
796 /*********************************************************
797 * Load and store for GPR *
798 * Format: OP rt, offset(base) *
799 *********************************************************/
801 #define _oB_ (regs_->GPR.r[_Rs_] + _Imm_)
803 OP(psxLB) { u32 v = (s8)psxMemRead8(_oB_); if (_Rt_) _rRt_ = v; }
804 OP(psxLBU) { u32 v = psxMemRead8(_oB_); if (_Rt_) _rRt_ = v; }
805 OP(psxLH) { u32 v = (s16)psxMemRead16(_oB_); if (_Rt_) _rRt_ = v; }
806 OP(psxLHU) { u32 v = psxMemRead16(_oB_); if (_Rt_) _rRt_ = v; }
807 OP(psxLW) { u32 v = psxMemRead32(_oB_); if (_Rt_) _rRt_ = v; }
810 static const u32 LWL_MASK[4] = { 0xffffff, 0xffff, 0xff, 0 };
811 static const u32 LWL_SHIFT[4] = { 24, 16, 8, 0 };
813 u32 shift = addr & 3;
814 u32 mem = psxMemRead32(addr & ~3);
817 _rRt_ = (_u32(_rRt_) & LWL_MASK[shift]) | (mem << LWL_SHIFT[shift]);
820 Mem = 1234. Reg = abcd
822 0 4bcd (mem << 24) | (reg & 0x00ffffff)
823 1 34cd (mem << 16) | (reg & 0x0000ffff)
824 2 234d (mem << 8) | (reg & 0x000000ff)
825 3 1234 (mem ) | (reg & 0x00000000)
830 static const u32 LWR_MASK[4] = { 0, 0xff000000, 0xffff0000, 0xffffff00 };
831 static const u32 LWR_SHIFT[4] = { 0, 8, 16, 24 };
833 u32 shift = addr & 3;
834 u32 mem = psxMemRead32(addr & ~3);
837 _rRt_ = (_u32(_rRt_) & LWR_MASK[shift]) | (mem >> LWR_SHIFT[shift]);
840 Mem = 1234. Reg = abcd
842 0 1234 (mem ) | (reg & 0x00000000)
843 1 a123 (mem >> 8) | (reg & 0xff000000)
844 2 ab12 (mem >> 16) | (reg & 0xffff0000)
845 3 abc1 (mem >> 24) | (reg & 0xffffff00)
849 OP(psxSB) { psxMemWrite8 (_oB_, _rRt_ & 0xff); }
850 OP(psxSH) { psxMemWrite16(_oB_, _rRt_ & 0xffff); }
851 OP(psxSW) { psxMemWrite32(_oB_, _rRt_); }
854 static const u32 SWL_MASK[4] = { 0xffffff00, 0xffff0000, 0xff000000, 0 };
855 static const u32 SWL_SHIFT[4] = { 24, 16, 8, 0 };
857 u32 shift = addr & 3;
858 u32 mem = psxMemRead32(addr & ~3);
860 psxMemWrite32(addr & ~3, (_u32(_rRt_) >> SWL_SHIFT[shift]) |
861 ( mem & SWL_MASK[shift]) );
863 Mem = 1234. Reg = abcd
865 0 123a (reg >> 24) | (mem & 0xffffff00)
866 1 12ab (reg >> 16) | (mem & 0xffff0000)
867 2 1abc (reg >> 8) | (mem & 0xff000000)
868 3 abcd (reg ) | (mem & 0x00000000)
873 static const u32 SWR_MASK[4] = { 0, 0xff, 0xffff, 0xffffff };
874 static const u32 SWR_SHIFT[4] = { 0, 8, 16, 24 };
876 u32 shift = addr & 3;
877 u32 mem = psxMemRead32(addr & ~3);
879 psxMemWrite32(addr & ~3, (_u32(_rRt_) << SWR_SHIFT[shift]) |
880 ( mem & SWR_MASK[shift]) );
883 Mem = 1234. Reg = abcd
885 0 abcd (reg ) | (mem & 0x00000000)
886 1 bcd4 (reg << 8) | (mem & 0x000000ff)
887 2 cd34 (reg << 16) | (mem & 0x0000ffff)
888 3 d234 (reg << 24) | (mem & 0x00ffffff)
892 /*********************************************************
893 * Moves between GPR and COPx *
894 * Format: OP rt, fs *
895 *********************************************************/
896 OP(psxMFC0) { if (!_Rt_) return; _rRt_ = _rFs_; }
897 OP(psxCFC0) { if (!_Rt_) return; _rRt_ = _rFs_; }
899 void MTC0(psxRegisters *regs_, int reg, u32 val) {
900 // SysPrintf("MTC0 %d: %x\n", reg, val);
903 regs_->CP0.r[12] = val;
904 psxTestSWInts(regs_);
908 regs_->CP0.n.Cause &= ~0x0300;
909 regs_->CP0.n.Cause |= val & 0x0300;
910 psxTestSWInts(regs_);
914 regs_->CP0.r[reg] = val;
919 OP(psxMTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
920 OP(psxCTC0) { MTC0(regs_, _Rd_, _u32(_rRt_)); }
922 /*********************************************************
923 * Unknow instruction (would generate an exception) *
925 *********************************************************/
926 static inline void psxNULL_(void) {
928 PSXCPU_LOG("psx: Unimplemented op %x\n", psxRegs.code);
932 OP(psxNULL) { psxNULL_(); }
933 void gteNULL(struct psxCP2Regs *regs) { psxNULL_(); }
936 psxSPC[_Funct_](regs_, code);
941 case 0x00: psxMFC0(regs_, code); break;
942 case 0x02: psxCFC0(regs_, code); break;
943 case 0x04: psxMTC0(regs_, code); break;
944 case 0x06: psxCTC0(regs_, code); break;
945 case 0x10: psxRFE(regs_, code); break;
946 default: psxNULL_(); break;
951 psxCP2[_Funct_](®s_->CP2);
957 psxCP2[f](®s_->CP2);
962 regs_->GPR.r[_Rt_] = MFC2(®s_->CP2, _Rd_);
967 regs_->GPR.r[_Rt_] = regs_->CP2C.r[_Rd_];
971 MTC2(®s_->CP2, regs_->GPR.r[_Rt_], _Rd_);
975 CTC2(®s_->CP2, regs_->GPR.r[_Rt_], _Rd_);
979 MTC2(®s_->CP2, psxMemRead32(_oB_), _Rt_);
983 psxMemWrite32(_oB_, MFC2(®s_->CP2, _Rt_));
988 gteLWC2(regs_, code);
993 gteSWC2(regs_, code);
996 static void psxBASIC(struct psxCP2Regs *cp2regs) {
997 psxRegisters *regs_ = (void *)((char *)cp2regs - offsetof(psxRegisters, CP2));
998 u32 code = regs_->code;
999 assert(regs_ == &psxRegs);
1001 case 0x00: gteMFC2(regs_, code); break;
1002 case 0x02: gteCFC2(regs_, code); break;
1003 case 0x04: gteMTC2(regs_, code); break;
1004 case 0x06: gteCTC2(regs_, code); break;
1005 default: psxNULL_(); break;
1011 case 0x00: psxBLTZ(regs_, code); break;
1012 case 0x01: psxBGEZ(regs_, code); break;
1013 case 0x10: psxBLTZAL(regs_, code); break;
1014 case 0x11: psxBGEZAL(regs_, code); break;
1015 default: psxNULL_(); break;
1020 uint32_t hleCode = code & 0x03ffffff;
1021 if (hleCode >= (sizeof(psxHLEt) / sizeof(psxHLEt[0]))) {
1028 static void (INT_ATTR *psxBSC[64])(psxRegisters *regs_, u32 code) = {
1029 psxSPECIAL, psxREGIMM, psxJ , psxJAL , psxBEQ , psxBNE , psxBLEZ, psxBGTZ,
1030 psxADDI , psxADDIU , psxSLTI, psxSLTIU, psxANDI, psxORI , psxXORI, psxLUI ,
1031 psxCOP0 , psxNULL , psxCOP2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
1032 psxNULL , psxNULL , psxNULL, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
1033 psxLB , psxLH , psxLWL , psxLW , psxLBU , psxLHU , psxLWR , psxNULL,
1034 psxSB , psxSH , psxSWL , psxSW , psxNULL, psxNULL, psxSWR , psxNULL,
1035 psxNULL , psxNULL , gteLWC2, psxNULL , psxNULL, psxNULL, psxNULL, psxNULL,
1036 psxNULL , psxNULL , gteSWC2, psxHLE , psxNULL, psxNULL, psxNULL, psxNULL
1039 static void (INT_ATTR *psxSPC[64])(psxRegisters *regs_, u32 code) = {
1040 psxSLL , psxNULL , psxSRL , psxSRA , psxSLLV , psxNULL , psxSRLV, psxSRAV,
1041 psxJR , psxJALR , psxNULL, psxNULL, psxSYSCALL, psxBREAK, psxNULL, psxNULL,
1042 psxMFHI, psxMTHI , psxMFLO, psxMTLO, psxNULL , psxNULL , psxNULL, psxNULL,
1043 psxMULT, psxMULTU, psxDIV , psxDIVU, psxNULL , psxNULL , psxNULL, psxNULL,
1044 psxADD , psxADDU , psxSUB , psxSUBU, psxAND , psxOR , psxXOR , psxNOR ,
1045 psxNULL, psxNULL , psxSLT , psxSLTU, psxNULL , psxNULL , psxNULL, psxNULL,
1046 psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL,
1047 psxNULL, psxNULL , psxNULL, psxNULL, psxNULL , psxNULL , psxNULL, psxNULL
1050 void (*psxCP2[64])(struct psxCP2Regs *regs) = {
1051 psxBASIC, gteRTPS , gteNULL , gteNULL, gteNULL, gteNULL , gteNCLIP, gteNULL, // 00
1052 gteNULL , gteNULL , gteNULL , gteNULL, gteOP , gteNULL , gteNULL , gteNULL, // 08
1053 gteDPCS , gteINTPL, gteMVMVA, gteNCDS, gteCDP , gteNULL , gteNCDT , gteNULL, // 10
1054 gteNULL , gteNULL , gteNULL , gteNCCS, gteCC , gteNULL , gteNCS , gteNULL, // 18
1055 gteNCT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 20
1056 gteSQR , gteDCPL , gteDPCT , gteNULL, gteNULL, gteAVSZ3, gteAVSZ4, gteNULL, // 28
1057 gteRTPT , gteNULL , gteNULL , gteNULL, gteNULL, gteNULL , gteNULL , gteNULL, // 30
1058 gteNULL , gteNULL , gteNULL , gteNULL, gteNULL, gteGPF , gteGPL , gteNCCT // 38
1061 ///////////////////////////////////////////
1063 static int intInit() {
1067 static void intReset() {
1068 memset(&ICache, 0xff, sizeof(ICache));
1071 static inline void execI_(u8 **memRLUT, psxRegisters *regs_) {
1072 regs_->code = fetch(memRLUT, regs_->pc);
1076 if (Config.Debug) ProcessDebug();
1079 regs_->cycle += BIAS;
1081 psxBSC[regs_->code >> 26](regs_, regs_->code);
1084 static void intExecute() {
1085 psxRegisters *regs_ = &psxRegs;
1086 u8 **memRLUT = psxMemRLUT;
1090 execI_(memRLUT, regs_);
1093 static void intExecuteBlock() {
1094 psxRegisters *regs_ = &psxRegs;
1095 u8 **memRLUT = psxMemRLUT;
1099 execI_(memRLUT, regs_);
1102 static void intClear(u32 Addr, u32 Size) {
1105 void intNotify (int note, void *data) {
1106 /* Gameblabla - Only clear the icache if it's isolated */
1107 if (note == R3000ACPU_NOTIFY_CACHE_ISOLATED)
1109 memset(&ICache, 0xff, sizeof(ICache));
1113 void intApplyConfig() {
1114 assert(psxBSC[18] == psxCOP2 || psxBSC[18] == psxCOP2_stall);
1115 assert(psxBSC[50] == gteLWC2 || psxBSC[50] == gteLWC2_stall);
1116 assert(psxBSC[58] == gteSWC2 || psxBSC[58] == gteSWC2_stall);
1117 assert(psxSPC[16] == psxMFHI || psxSPC[16] == psxMFHI_stall);
1118 assert(psxSPC[18] == psxMFLO || psxSPC[18] == psxMFLO_stall);
1119 assert(psxSPC[24] == psxMULT || psxSPC[24] == psxMULT_stall);
1120 assert(psxSPC[25] == psxMULTU || psxSPC[25] == psxMULTU_stall);
1121 assert(psxSPC[26] == psxDIV || psxSPC[26] == psxDIV_stall);
1122 assert(psxSPC[27] == psxDIVU || psxSPC[27] == psxDIVU_stall);
1124 if (Config.DisableStalls) {
1125 psxBSC[18] = psxCOP2;
1126 psxBSC[50] = gteLWC2;
1127 psxBSC[58] = gteSWC2;
1128 psxSPC[16] = psxMFHI;
1129 psxSPC[18] = psxMFLO;
1130 psxSPC[24] = psxMULT;
1131 psxSPC[25] = psxMULTU;
1132 psxSPC[26] = psxDIV;
1133 psxSPC[27] = psxDIVU;
1135 psxBSC[18] = psxCOP2_stall;
1136 psxBSC[50] = gteLWC2_stall;
1137 psxBSC[58] = gteSWC2_stall;
1138 psxSPC[16] = psxMFHI_stall;
1139 psxSPC[18] = psxMFLO_stall;
1140 psxSPC[24] = psxMULT_stall;
1141 psxSPC[25] = psxMULTU_stall;
1142 psxSPC[26] = psxDIV_stall;
1143 psxSPC[27] = psxDIVU_stall;
1146 // dynarec may occasionally call the interpreter, in such a case the
1147 // cache won't work (cache only works right if all fetches go through it)
1148 if (!Config.icache_emulation || psxCpu != &psxInt)
1149 fetch = fetchNoCache;
1151 fetch = fetchICache;
1154 static void intShutdown() {
1157 // single step (may do several ops in case of a branch)
1159 execI_(psxMemRLUT, &psxRegs);
1162 R3000Acpu psxInt = {