1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * R3000A CPU functions.
28 #include "psxinterpreter.h"
30 #include "../include/compiler_features.h"
32 R3000Acpu *psxCpu = NULL;
38 SysPrintf(_("Running PCSX Version %s (%s).\n"), PCSX_VERSION, __DATE__);
41 if (Config.Cpu == CPU_INTERPRETER) {
43 } else psxCpu = &psxRec;
45 Config.Cpu = CPU_INTERPRETER;
51 if (psxMemInit() == -1) return -1;
53 return psxCpu->Init();
57 boolean introBypassed = FALSE;
60 memset(&psxRegs, 0, sizeof(psxRegs));
62 psxRegs.pc = 0xbfc00000; // Start in bootstrap
64 psxRegs.CP0.n.SR = 0x10600000; // COP0 enabled | BEV = 1 | TS = 1
65 psxRegs.CP0.n.PRid = 0x00000002; // PRevID = Revision ID, same as R3000A
67 psxRegs.CP0.n.SR |= 1u << 30; // COP2 enabled
68 psxRegs.CP0.n.SR &= ~(1u << 22); // RAM exception vector
71 psxCpu->ApplyConfig();
79 if (psxRegs.pc == 0x80030000 && !Config.SlowBoot) {
84 if (Config.HLE || introBypassed)
85 psxBiosSetupBootState();
88 EMU_LOG("*BIOS END*\n");
101 // cp0 is passed separately for lightrec to be less messy
102 void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
103 u32 opcode = intFakeFetch(psxRegs.pc);
105 if (unlikely(!Config.HLE && (opcode >> 25) == 0x25)) {
106 // "hokuto no ken" / "Crash Bandicot 2" ...
107 // BIOS does not allow to return to GTE instructions
108 // (just skips it, supposedly because it's scheduled already)
109 // so we execute it here
110 psxCP2Regs *cp2 = (psxCP2Regs *)(cp0 + 1);
111 psxRegs.code = opcode;
112 psxCP2[opcode & 0x3f](cp2);
116 cp0->n.Cause = (bdt << 30) | (cp0->n.Cause & 0x700) | cause;
119 cp0->n.EPC = bdt ? psxRegs.pc - 4 : psxRegs.pc;
121 if (cp0->n.SR & 0x400000)
122 psxRegs.pc = 0xbfc00180;
124 psxRegs.pc = 0x80000080;
127 cp0->n.SR = (cp0->n.SR & ~0x3f) | ((cp0->n.SR & 0x0f) << 2);
130 void psxBranchTest() {
131 if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
134 if (psxRegs.interrupt) {
135 if ((psxRegs.interrupt & (1 << PSXINT_SIO))) { // sio
136 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SIO].sCycle) >= psxRegs.intCycle[PSXINT_SIO].cycle) {
137 psxRegs.interrupt &= ~(1 << PSXINT_SIO);
141 if (psxRegs.interrupt & (1 << PSXINT_CDR)) { // cdr
142 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDR].sCycle) >= psxRegs.intCycle[PSXINT_CDR].cycle) {
143 psxRegs.interrupt &= ~(1 << PSXINT_CDR);
147 if (psxRegs.interrupt & (1 << PSXINT_CDREAD)) { // cdr read
148 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDREAD].sCycle) >= psxRegs.intCycle[PSXINT_CDREAD].cycle) {
149 psxRegs.interrupt &= ~(1 << PSXINT_CDREAD);
150 cdrPlayReadInterrupt();
153 if (psxRegs.interrupt & (1 << PSXINT_GPUDMA)) { // gpu dma
154 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUDMA].cycle) {
155 psxRegs.interrupt &= ~(1 << PSXINT_GPUDMA);
159 if (psxRegs.interrupt & (1 << PSXINT_MDECOUTDMA)) { // mdec out dma
160 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECOUTDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECOUTDMA].cycle) {
161 psxRegs.interrupt &= ~(1 << PSXINT_MDECOUTDMA);
165 if (psxRegs.interrupt & (1 << PSXINT_SPUDMA)) { // spu dma
166 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPUDMA].sCycle) >= psxRegs.intCycle[PSXINT_SPUDMA].cycle) {
167 psxRegs.interrupt &= ~(1 << PSXINT_SPUDMA);
171 if (psxRegs.interrupt & (1 << PSXINT_MDECINDMA)) { // mdec in
172 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_MDECINDMA].sCycle) >= psxRegs.intCycle[PSXINT_MDECINDMA].cycle) {
173 psxRegs.interrupt &= ~(1 << PSXINT_MDECINDMA);
177 if (psxRegs.interrupt & (1 << PSXINT_GPUOTCDMA)) { // gpu otc
178 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_GPUOTCDMA].sCycle) >= psxRegs.intCycle[PSXINT_GPUOTCDMA].cycle) {
179 psxRegs.interrupt &= ~(1 << PSXINT_GPUOTCDMA);
183 if (psxRegs.interrupt & (1 << PSXINT_CDRDMA)) { // cdrom
184 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRDMA].sCycle) >= psxRegs.intCycle[PSXINT_CDRDMA].cycle) {
185 psxRegs.interrupt &= ~(1 << PSXINT_CDRDMA);
189 if (psxRegs.interrupt & (1 << PSXINT_CDRLID)) { // cdr lid states
190 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_CDRLID].sCycle) >= psxRegs.intCycle[PSXINT_CDRLID].cycle) {
191 psxRegs.interrupt &= ~(1 << PSXINT_CDRLID);
192 cdrLidSeekInterrupt();
195 if (psxRegs.interrupt & (1 << PSXINT_IRQ10)) { // irq10 - controller port pin8
196 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_IRQ10].sCycle) >= psxRegs.intCycle[PSXINT_IRQ10].cycle) {
197 psxRegs.interrupt &= ~(1 << PSXINT_IRQ10);
201 if (psxRegs.interrupt & (1 << PSXINT_SPU_UPDATE)) { // scheduled spu update
202 if ((psxRegs.cycle - psxRegs.intCycle[PSXINT_SPU_UPDATE].sCycle) >= psxRegs.intCycle[PSXINT_SPU_UPDATE].cycle) {
203 psxRegs.interrupt &= ~(1 << PSXINT_SPU_UPDATE);
209 psxRegs.CP0.n.Cause &= ~0x400;
210 if (psxHu32(0x1070) & psxHu32(0x1074))
211 psxRegs.CP0.n.Cause |= 0x400;
212 if (((psxRegs.CP0.n.Cause | 1) & psxRegs.CP0.n.SR & 0x401) == 0x401)
213 psxException(0, 0, &psxRegs.CP0);
214 else if (unlikely(psxRegs.pc == psxRegs.biosBranchCheck))
215 psxBiosCheckBranch();
219 if (!Config.HLE && Config.PsxOut) {
220 u32 call = psxRegs.GPR.n.t1 & 0xff;
221 switch (psxRegs.pc & 0x1fffff) {
224 if (call != 0x28 && call != 0xe) {
225 PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
232 if (call != 0x17 && call != 0xb) {
233 PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
240 PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
249 void psxExecuteBios() {
251 for (i = 0; i < 5000000; i++) {
252 psxCpu->ExecuteBlock(EXEC_CALLER_BOOT);
253 if ((psxRegs.pc & 0xff800000) == 0x80000000)
256 if (psxRegs.pc != 0x80030000)
257 SysPrintf("non-standard BIOS detected (%d, %08x)\n", i, psxRegs.pc);
260 // irq10 stuff, very preliminary
261 static int irq10count;
263 static void psxScheduleIrq10One(u32 cycles_abs) {
264 // schedule relative to frame start
265 u32 c = cycles_abs - rcnts[3].cycleStart;
267 psxRegs.interrupt |= 1 << PSXINT_IRQ10;
268 psxRegs.intCycle[PSXINT_IRQ10].cycle = c;
269 psxRegs.intCycle[PSXINT_IRQ10].sCycle = rcnts[3].cycleStart;
270 new_dyna_set_event_abs(PSXINT_IRQ10, cycles_abs);
273 void irq10Interrupt() {
274 u32 prevc = psxRegs.intCycle[PSXINT_IRQ10].sCycle
275 + psxRegs.intCycle[PSXINT_IRQ10].cycle;
277 psxHu32ref(0x1070) |= SWAPu32(0x400);
280 s32 framec = psxRegs.cycle - rcnts[3].cycleStart;
281 printf("%d:%03d irq10 #%d %3d m=%d,%d\n", frame_counter,
282 (s32)((float)framec / (PSXCLK / 60 / 263.0f)),
283 irq10count, psxRegs.cycle - prevc,
284 (psxRegs.CP0.n.SR & 0x401) != 0x401, !(psxHu32(0x1074) & 0x400));
286 if (--irq10count > 0) {
287 u32 cycles_per_line = Config.PsxType
288 ? PSXCLK / 50 / 314 : PSXCLK / 60 / 263;
289 psxScheduleIrq10One(prevc + cycles_per_line);
293 void psxScheduleIrq10(int irq_count, int x_cycles, int y) {
294 //printf("%s %d, %d, %d\n", __func__, irq_count, x_cycles, y);
295 u32 cycles_per_frame = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
296 u32 cycles = rcnts[3].cycleStart + cycles_per_frame;
297 cycles += y * cycles_per_frame / (Config.PsxType ? 314 : 263);
299 psxScheduleIrq10One(cycles);
300 irq10count = irq_count;