1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
21 * R3000A CPU functions.
28 #include "psxinterpreter.h"
30 #include "psxevents.h"
31 #include "../include/compiler_features.h"
33 R3000Acpu *psxCpu = NULL;
40 if (Config.Cpu == CPU_INTERPRETER) {
42 } else psxCpu = &psxRec;
44 Config.Cpu = CPU_INTERPRETER;
50 if (psxMemInit() == -1) return -1;
52 return psxCpu->Init();
56 boolean introBypassed = FALSE;
59 memset(&psxRegs, 0, sizeof(psxRegs));
61 psxRegs.pc = 0xbfc00000; // Start in bootstrap
63 psxRegs.CP0.n.SR = 0x10600000; // COP0 enabled | BEV = 1 | TS = 1
64 psxRegs.CP0.n.PRid = 0x00000002; // PRevID = Revision ID, same as R3000A
66 psxRegs.CP0.n.SR |= 1u << 30; // COP2 enabled
67 psxRegs.CP0.n.SR &= ~(1u << 22); // RAM exception vector
70 psxCpu->ApplyConfig();
78 if (psxRegs.pc == 0x80030000 && !Config.SlowBoot) {
83 if (Config.HLE || introBypassed)
84 psxBiosSetupBootState();
87 EMU_LOG("*BIOS END*\n");
100 // cp0 is passed separately for lightrec to be less messy
101 void psxException(u32 cause, enum R3000Abdt bdt, psxCP0Regs *cp0) {
102 u32 opcode = intFakeFetch(psxRegs.pc);
104 if (unlikely(!Config.HLE && (opcode >> 25) == 0x25)) {
105 // "hokuto no ken" / "Crash Bandicot 2" ...
106 // BIOS does not allow to return to GTE instructions
107 // (just skips it, supposedly because it's scheduled already)
108 // so we execute it here
109 psxCP2Regs *cp2 = (psxCP2Regs *)(cp0 + 1);
110 psxRegs.code = opcode;
111 psxCP2[opcode & 0x3f](cp2);
115 cp0->n.Cause = (bdt << 30) | (cp0->n.Cause & 0x700) | cause;
118 cp0->n.EPC = bdt ? psxRegs.pc - 4 : psxRegs.pc;
120 if (cp0->n.SR & 0x400000)
121 psxRegs.pc = 0xbfc00180;
123 psxRegs.pc = 0x80000080;
126 cp0->n.SR = (cp0->n.SR & ~0x3f) | ((cp0->n.SR & 0x0f) << 2);
129 void psxBranchTest() {
130 if ((psxRegs.cycle - psxNextsCounter) >= psxNextCounter)
133 irq_test(&psxRegs.CP0);
135 if (unlikely(psxRegs.pc == psxRegs.biosBranchCheck))
136 psxBiosCheckBranch();
140 if (!Config.HLE && Config.PsxOut) {
141 u32 call = psxRegs.GPR.n.t1 & 0xff;
142 switch (psxRegs.pc & 0x1fffff) {
145 if (call != 0x28 && call != 0xe) {
146 PSXBIOS_LOG("Bios call a0: %s (%x) %x,%x,%x,%x\n", biosA0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
153 if (call != 0x17 && call != 0xb) {
154 PSXBIOS_LOG("Bios call b0: %s (%x) %x,%x,%x,%x\n", biosB0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3); }
161 PSXBIOS_LOG("Bios call c0: %s (%x) %x,%x,%x,%x\n", biosC0n[call], call, psxRegs.GPR.n.a0, psxRegs.GPR.n.a1, psxRegs.GPR.n.a2, psxRegs.GPR.n.a3);
170 void psxExecuteBios() {
172 for (i = 0; i < 5000000; i++) {
173 psxCpu->ExecuteBlock(EXEC_CALLER_BOOT);
174 if ((psxRegs.pc & 0xff800000) == 0x80000000)
177 if (psxRegs.pc != 0x80030000)
178 SysPrintf("non-standard BIOS detected (%d, %08x)\n", i, psxRegs.pc);
181 // irq10 stuff, very preliminary
182 static int irq10count;
184 static void psxScheduleIrq10One(u32 cycles_abs) {
185 // schedule relative to frame start
186 u32 c = cycles_abs - rcnts[3].cycleStart;
188 psxRegs.interrupt |= 1 << PSXINT_IRQ10;
189 psxRegs.intCycle[PSXINT_IRQ10].cycle = c;
190 psxRegs.intCycle[PSXINT_IRQ10].sCycle = rcnts[3].cycleStart;
191 set_event_raw_abs(PSXINT_IRQ10, cycles_abs);
194 void irq10Interrupt() {
195 u32 prevc = psxRegs.intCycle[PSXINT_IRQ10].sCycle
196 + psxRegs.intCycle[PSXINT_IRQ10].cycle;
198 psxHu32ref(0x1070) |= SWAPu32(0x400);
201 s32 framec = psxRegs.cycle - rcnts[3].cycleStart;
202 printf("%d:%03d irq10 #%d %3d m=%d,%d\n", frame_counter,
203 (s32)((float)framec / (PSXCLK / 60 / 263.0f)),
204 irq10count, psxRegs.cycle - prevc,
205 (psxRegs.CP0.n.SR & 0x401) != 0x401, !(psxHu32(0x1074) & 0x400));
207 if (--irq10count > 0) {
208 u32 cycles_per_line = Config.PsxType
209 ? PSXCLK / 50 / 314 : PSXCLK / 60 / 263;
210 psxScheduleIrq10One(prevc + cycles_per_line);
214 void psxScheduleIrq10(int irq_count, int x_cycles, int y) {
215 //printf("%s %d, %d, %d\n", __func__, irq_count, x_cycles, y);
216 u32 cycles_per_frame = Config.PsxType ? PSXCLK / 50 : PSXCLK / 60;
217 u32 cycles = rcnts[3].cycleStart + cycles_per_frame;
218 cycles += y * cycles_per_frame / (Config.PsxType ? 314 : 263);
220 psxScheduleIrq10One(cycles);
221 irq10count = irq_count;