1 /***************************************************************************
2 * Copyright (C) 2007 Ryan Schultz, PCSX-df Team, PCSX team *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 51 Franklin Street, Fifth Floor, Boston, MA 02111-1307 USA. *
18 ***************************************************************************/
27 #include "psxcommon.h"
29 #include "psxcounters.h"
35 void (*Execute)(); /* executes up to a break */
36 void (*ExecuteBlock)(); /* executes up to a jump */
37 void (*Clear)(u32 Addr, u32 Size);
41 extern R3000Acpu *psxCpu;
42 extern R3000Acpu psxInt;
43 extern R3000Acpu psxRec;
47 #if defined(__BIGENDIAN__)
48 struct { u8 h3, h2, h, l; } b;
49 struct { s8 h3, h2, h, l; } sb;
50 struct { u16 h, l; } w;
51 struct { s16 h, l; } sw;
53 struct { u8 l, h, h2, h3; } b;
54 struct { u16 l, h; } w;
55 struct { s8 l, h, h2, h3; } sb;
56 struct { s16 l, h; } sw;
62 u32 r0, at, v0, v1, a0, a1, a2, a3,
63 t0, t1, t2, t3, t4, t5, t6, t7,
64 s0, s1, s2, s3, s4, s5, s6, s7,
65 t8, t9, k0, k1, gp, sp, s8, ra, lo, hi;
67 u32 r[34]; /* Lo, Hi in r[32] and r[33] */
73 u32 Index, Random, EntryLo0, EntryLo1,
74 Context, PageMask, Wired, Reserved0,
75 BadVAddr, Count, EntryHi, Compare,
76 Status, Cause, EPC, PRid,
77 Config, LLAddr, WatchLO, WatchHI,
78 XContext, Reserved1, Reserved2, Reserved3,
79 Reserved4, Reserved5, ECC, CacheErr,
80 TagLo, TagHi, ErrorEPC, Reserved6;
103 unsigned char r, g, b, c;
107 short m11, m12, m13, m21, m22, m23, m31, m32, m33, pad;
112 SVector3D v0, v1, v2;
115 s32 ir0, ir1, ir2, ir3;
116 SVector2D sxy0, sxy1, sxy2, sxyp;
117 SVector2Dz sz0, sz1, sz2, sz3;
118 CBGR rgb0, rgb1, rgb2;
120 s32 mac0, mac1, mac2, mac3;
165 typedef struct psxCP2Regs {
166 psxCP2Data CP2D; /* Cop2 data registers */
167 psxCP2Ctrl CP2C; /* Cop2 control registers */
171 psxGPRRegs GPR; /* General Purpose Registers */
172 psxCP0Regs CP0; /* Coprocessor0 Registers */
175 psxCP2Data CP2D; /* Cop2 data registers */
176 psxCP2Ctrl CP2C; /* Cop2 control registers */
180 u32 pc; /* Program counter */
181 u32 code; /* The instruction */
184 struct { u32 sCycle, cycle; } intCycle[32];
187 extern psxRegisters psxRegs;
189 /* new_dynarec stuff */
190 extern u32 event_cycles[PSXINT_COUNT];
191 extern u32 next_interupt;
193 void new_dyna_before_save(void);
194 void new_dyna_after_save(void);
195 void new_dyna_freeze(void *f, int mode);
197 #define new_dyna_set_event(e, c) { \
199 u32 abs_ = psxRegs.cycle + c_; \
200 s32 odi_ = next_interupt - psxRegs.cycle; \
201 event_cycles[e] = abs_; \
203 /*printf("%u: next_interupt %d -> %d (%u)\n", psxRegs.cycle, odi_, c_, abs_);*/ \
204 next_interupt = abs_; \
208 #if defined(__BIGENDIAN__)
210 #define _i32(x) *(s32 *)&x
213 #define _i16(x) (((short *)&x)[1])
214 #define _u16(x) (((unsigned short *)&x)[1])
216 #define _i8(x) (((char *)&x)[3])
217 #define _u8(x) (((unsigned char *)&x)[3])
221 #define _i32(x) *(s32 *)&x
224 #define _i16(x) *(short *)&x
225 #define _u16(x) *(unsigned short *)&x
227 #define _i8(x) *(char *)&x
228 #define _u8(x) *(unsigned char *)&x
232 /**** R3000A Instruction Macros ****/
233 #define _PC_ psxRegs.pc // The next PC to be executed
235 #define _fOp_(code) ((code >> 26) ) // The opcode part of the instruction register
236 #define _fFunct_(code) ((code ) & 0x3F) // The funct part of the instruction register
237 #define _fRd_(code) ((code >> 11) & 0x1F) // The rd part of the instruction register
238 #define _fRt_(code) ((code >> 16) & 0x1F) // The rt part of the instruction register
239 #define _fRs_(code) ((code >> 21) & 0x1F) // The rs part of the instruction register
240 #define _fSa_(code) ((code >> 6) & 0x1F) // The sa part of the instruction register
241 #define _fIm_(code) ((u16)code) // The immediate part of the instruction register
242 #define _fTarget_(code) (code & 0x03ffffff) // The target part of the instruction register
244 #define _fImm_(code) ((s16)code) // sign-extended immediate
245 #define _fImmU_(code) (code&0xffff) // zero-extended immediate
247 #define _Op_ _fOp_(psxRegs.code)
248 #define _Funct_ _fFunct_(psxRegs.code)
249 #define _Rd_ _fRd_(psxRegs.code)
250 #define _Rt_ _fRt_(psxRegs.code)
251 #define _Rs_ _fRs_(psxRegs.code)
252 #define _Sa_ _fSa_(psxRegs.code)
253 #define _Im_ _fIm_(psxRegs.code)
254 #define _Target_ _fTarget_(psxRegs.code)
256 #define _Imm_ _fImm_(psxRegs.code)
257 #define _ImmU_ _fImmU_(psxRegs.code)
259 #define _rRs_ psxRegs.GPR.r[_Rs_] // Rs register
260 #define _rRt_ psxRegs.GPR.r[_Rt_] // Rt register
261 #define _rRd_ psxRegs.GPR.r[_Rd_] // Rd register
262 #define _rSa_ psxRegs.GPR.r[_Sa_] // Sa register
263 #define _rFs_ psxRegs.CP0.r[_Rd_] // Fs register
265 #define _c2dRs_ psxRegs.CP2D.r[_Rs_] // Rs cop2 data register
266 #define _c2dRt_ psxRegs.CP2D.r[_Rt_] // Rt cop2 data register
267 #define _c2dRd_ psxRegs.CP2D.r[_Rd_] // Rd cop2 data register
268 #define _c2dSa_ psxRegs.CP2D.r[_Sa_] // Sa cop2 data register
270 #define _rHi_ psxRegs.GPR.n.hi // The HI register
271 #define _rLo_ psxRegs.GPR.n.lo // The LO register
273 #define _JumpTarget_ ((_Target_ * 4) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
274 #define _BranchTarget_ ((s16)_Im_ * 4 + _PC_) // Calculates the target during a branch instruction
276 #define _SetLink(x) psxRegs.GPR.r[x] = _PC_ + 4; // Sets the return address in the link register
281 void psxException(u32 code, u32 bd);
282 void psxBranchTest();
283 void psxExecuteBios();
284 int psxTestLoadDelay(int reg, u32 tmp);
285 void psxDelayTest(int reg, u32 bpc);
286 void psxTestSWInts();